1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 * 5 * DisplayPort support for G4x,ILK,SNB,IVB,VLV,CHV (HSW+ handled by the DDI code). 6 */ 7 8 #include <linux/string_helpers.h> 9 10 #include <drm/drm_print.h> 11 12 #include "g4x_dp.h" 13 #include "i915_reg.h" 14 #include "i915_utils.h" 15 #include "intel_audio.h" 16 #include "intel_backlight.h" 17 #include "intel_connector.h" 18 #include "intel_crtc.h" 19 #include "intel_de.h" 20 #include "intel_display_power.h" 21 #include "intel_display_regs.h" 22 #include "intel_display_types.h" 23 #include "intel_dp.h" 24 #include "intel_dp_aux.h" 25 #include "intel_dp_link_training.h" 26 #include "intel_dp_test.h" 27 #include "intel_dpio_phy.h" 28 #include "intel_encoder.h" 29 #include "intel_fifo_underrun.h" 30 #include "intel_hdmi.h" 31 #include "intel_hotplug.h" 32 #include "intel_pch_display.h" 33 #include "intel_pps.h" 34 35 static const struct dpll g4x_dpll[] = { 36 { .dot = 162000, .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8, }, 37 { .dot = 270000, .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2, }, 38 }; 39 40 static const struct dpll pch_dpll[] = { 41 { .dot = 162000, .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9, }, 42 { .dot = 270000, .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8, }, 43 }; 44 45 static const struct dpll vlv_dpll[] = { 46 { .dot = 162000, .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81, }, 47 { .dot = 270000, .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27, }, 48 }; 49 50 static const struct dpll chv_dpll[] = { 51 /* m2 is .22 binary fixed point */ 52 { .dot = 162000, .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ }, 53 { .dot = 270000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 /* 27.0 */ }, 54 }; 55 56 const struct dpll *vlv_get_dpll(struct intel_display *display) 57 { 58 return display->platform.cherryview ? &chv_dpll[0] : &vlv_dpll[0]; 59 } 60 61 static void g4x_dp_set_clock(struct intel_encoder *encoder, 62 struct intel_crtc_state *pipe_config) 63 { 64 struct intel_display *display = to_intel_display(encoder); 65 const struct dpll *divisor = NULL; 66 int i, count = 0; 67 68 if (display->platform.g4x) { 69 divisor = g4x_dpll; 70 count = ARRAY_SIZE(g4x_dpll); 71 } else if (HAS_PCH_SPLIT(display)) { 72 divisor = pch_dpll; 73 count = ARRAY_SIZE(pch_dpll); 74 } else if (display->platform.cherryview) { 75 divisor = chv_dpll; 76 count = ARRAY_SIZE(chv_dpll); 77 } else if (display->platform.valleyview) { 78 divisor = vlv_dpll; 79 count = ARRAY_SIZE(vlv_dpll); 80 } 81 82 if (divisor && count) { 83 for (i = 0; i < count; i++) { 84 if (pipe_config->port_clock == divisor[i].dot) { 85 pipe_config->dpll = divisor[i]; 86 pipe_config->clock_set = true; 87 break; 88 } 89 } 90 } 91 } 92 93 static void intel_dp_prepare(struct intel_encoder *encoder, 94 const struct intel_crtc_state *pipe_config) 95 { 96 struct intel_display *display = to_intel_display(encoder); 97 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 98 enum port port = encoder->port; 99 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 100 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 101 102 intel_dp_set_link_params(intel_dp, 103 pipe_config->port_clock, 104 pipe_config->lane_count); 105 106 /* 107 * There are four kinds of DP registers: 108 * IBX PCH 109 * SNB CPU 110 * IVB CPU 111 * CPT PCH 112 * 113 * IBX PCH and CPU are the same for almost everything, 114 * except that the CPU DP PLL is configured in this 115 * register 116 * 117 * CPT PCH is quite different, having many bits moved 118 * to the TRANS_DP_CTL register instead. That 119 * configuration happens (oddly) in ilk_pch_enable 120 */ 121 122 /* Preserve the BIOS-computed detected bit. This is 123 * supposed to be read-only. 124 */ 125 intel_dp->DP = intel_de_read(display, intel_dp->output_reg) & DP_DETECTED; 126 127 /* Handle DP bits in common between all three register formats */ 128 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 129 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count); 130 131 /* Split out the IBX/CPU vs CPT settings */ 132 133 if (display->platform.ivybridge && port == PORT_A) { 134 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 135 intel_dp->DP |= DP_SYNC_HS_HIGH; 136 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 137 intel_dp->DP |= DP_SYNC_VS_HIGH; 138 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 139 140 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 141 intel_dp->DP |= DP_ENHANCED_FRAMING; 142 143 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe); 144 } else if (HAS_PCH_CPT(display) && port != PORT_A) { 145 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 146 147 intel_de_rmw(display, TRANS_DP_CTL(crtc->pipe), 148 TRANS_DP_ENH_FRAMING, 149 pipe_config->enhanced_framing ? 150 TRANS_DP_ENH_FRAMING : 0); 151 } else { 152 if (display->platform.g4x && pipe_config->limited_color_range) 153 intel_dp->DP |= DP_COLOR_RANGE_16_235; 154 155 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 156 intel_dp->DP |= DP_SYNC_HS_HIGH; 157 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 158 intel_dp->DP |= DP_SYNC_VS_HIGH; 159 intel_dp->DP |= DP_LINK_TRAIN_OFF; 160 161 if (pipe_config->enhanced_framing) 162 intel_dp->DP |= DP_ENHANCED_FRAMING; 163 164 if (display->platform.cherryview) 165 intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe); 166 else 167 intel_dp->DP |= DP_PIPE_SEL(crtc->pipe); 168 } 169 } 170 171 static void assert_dp_port(struct intel_dp *intel_dp, bool state) 172 { 173 struct intel_display *display = to_intel_display(intel_dp); 174 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 175 bool cur_state = intel_de_read(display, intel_dp->output_reg) & DP_PORT_EN; 176 177 INTEL_DISPLAY_STATE_WARN(display, cur_state != state, 178 "[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n", 179 dig_port->base.base.base.id, dig_port->base.base.name, 180 str_on_off(state), str_on_off(cur_state)); 181 } 182 #define assert_dp_port_disabled(d) assert_dp_port((d), false) 183 184 static void assert_edp_pll(struct intel_display *display, bool state) 185 { 186 bool cur_state = intel_de_read(display, DP_A) & EDP_PLL_ENABLE; 187 188 INTEL_DISPLAY_STATE_WARN(display, cur_state != state, 189 "eDP PLL state assertion failure (expected %s, current %s)\n", 190 str_on_off(state), str_on_off(cur_state)); 191 } 192 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true) 193 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false) 194 195 static void ilk_edp_pll_on(struct intel_dp *intel_dp, 196 const struct intel_crtc_state *pipe_config) 197 { 198 struct intel_display *display = to_intel_display(intel_dp); 199 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 200 201 assert_transcoder_disabled(display, pipe_config->cpu_transcoder); 202 assert_dp_port_disabled(intel_dp); 203 assert_edp_pll_disabled(display); 204 205 drm_dbg_kms(display->drm, "enabling eDP PLL for clock %d\n", 206 pipe_config->port_clock); 207 208 intel_dp->DP &= ~EDP_PLL_FREQ_MASK; 209 210 if (pipe_config->port_clock == 162000) 211 intel_dp->DP |= EDP_PLL_FREQ_162MHZ; 212 else 213 intel_dp->DP |= EDP_PLL_FREQ_270MHZ; 214 215 intel_de_write(display, DP_A, intel_dp->DP); 216 intel_de_posting_read(display, DP_A); 217 udelay(500); 218 219 /* 220 * [DevILK] Work around required when enabling DP PLL 221 * while a pipe is enabled going to FDI: 222 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI 223 * 2. Program DP PLL enable 224 */ 225 if (display->platform.ironlake) 226 intel_wait_for_vblank_if_active(display, !crtc->pipe); 227 228 intel_dp->DP |= EDP_PLL_ENABLE; 229 230 intel_de_write(display, DP_A, intel_dp->DP); 231 intel_de_posting_read(display, DP_A); 232 udelay(200); 233 } 234 235 static void ilk_edp_pll_off(struct intel_dp *intel_dp, 236 const struct intel_crtc_state *old_crtc_state) 237 { 238 struct intel_display *display = to_intel_display(intel_dp); 239 240 assert_transcoder_disabled(display, old_crtc_state->cpu_transcoder); 241 assert_dp_port_disabled(intel_dp); 242 assert_edp_pll_enabled(display); 243 244 drm_dbg_kms(display->drm, "disabling eDP PLL\n"); 245 246 intel_dp->DP &= ~EDP_PLL_ENABLE; 247 248 intel_de_write(display, DP_A, intel_dp->DP); 249 intel_de_posting_read(display, DP_A); 250 udelay(200); 251 } 252 253 static bool cpt_dp_port_selected(struct intel_display *display, 254 enum port port, enum pipe *pipe) 255 { 256 enum pipe p; 257 258 for_each_pipe(display, p) { 259 u32 val = intel_de_read(display, TRANS_DP_CTL(p)); 260 261 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) { 262 *pipe = p; 263 return true; 264 } 265 } 266 267 drm_dbg_kms(display->drm, "No pipe for DP port %c found\n", 268 port_name(port)); 269 270 /* must initialize pipe to something for the asserts */ 271 *pipe = PIPE_A; 272 273 return false; 274 } 275 276 bool g4x_dp_port_enabled(struct intel_display *display, 277 i915_reg_t dp_reg, enum port port, 278 enum pipe *pipe) 279 { 280 bool ret; 281 u32 val; 282 283 val = intel_de_read(display, dp_reg); 284 285 ret = val & DP_PORT_EN; 286 287 /* asserts want to know the pipe even if the port is disabled */ 288 if (display->platform.ivybridge && port == PORT_A) 289 *pipe = REG_FIELD_GET(DP_PIPE_SEL_MASK_IVB, val); 290 else if (HAS_PCH_CPT(display) && port != PORT_A) 291 ret &= cpt_dp_port_selected(display, port, pipe); 292 else if (display->platform.cherryview) 293 *pipe = REG_FIELD_GET(DP_PIPE_SEL_MASK_CHV, val); 294 else 295 *pipe = REG_FIELD_GET(DP_PIPE_SEL_MASK, val); 296 297 return ret; 298 } 299 300 static bool intel_dp_get_hw_state(struct intel_encoder *encoder, 301 enum pipe *pipe) 302 { 303 struct intel_display *display = to_intel_display(encoder); 304 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 305 intel_wakeref_t wakeref; 306 bool ret; 307 308 wakeref = intel_display_power_get_if_enabled(display, 309 encoder->power_domain); 310 if (!wakeref) 311 return false; 312 313 ret = g4x_dp_port_enabled(display, intel_dp->output_reg, 314 encoder->port, pipe); 315 316 intel_display_power_put(display, encoder->power_domain, wakeref); 317 318 return ret; 319 } 320 321 static void g4x_dp_get_m_n(struct intel_crtc_state *crtc_state) 322 { 323 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 324 325 if (crtc_state->has_pch_encoder) { 326 intel_pch_transcoder_get_m1_n1(crtc, &crtc_state->dp_m_n); 327 intel_pch_transcoder_get_m2_n2(crtc, &crtc_state->dp_m2_n2); 328 } else { 329 intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder, 330 &crtc_state->dp_m_n); 331 intel_cpu_transcoder_get_m2_n2(crtc, crtc_state->cpu_transcoder, 332 &crtc_state->dp_m2_n2); 333 } 334 } 335 336 static void intel_dp_get_config(struct intel_encoder *encoder, 337 struct intel_crtc_state *pipe_config) 338 { 339 struct intel_display *display = to_intel_display(encoder); 340 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 341 u32 tmp, flags = 0; 342 enum port port = encoder->port; 343 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 344 345 if (encoder->type == INTEL_OUTPUT_EDP) 346 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 347 else 348 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 349 350 tmp = intel_de_read(display, intel_dp->output_reg); 351 352 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; 353 354 if (HAS_PCH_CPT(display) && port != PORT_A) { 355 u32 trans_dp = intel_de_read(display, 356 TRANS_DP_CTL(crtc->pipe)); 357 358 if (trans_dp & TRANS_DP_ENH_FRAMING) 359 pipe_config->enhanced_framing = true; 360 361 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH) 362 flags |= DRM_MODE_FLAG_PHSYNC; 363 else 364 flags |= DRM_MODE_FLAG_NHSYNC; 365 366 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH) 367 flags |= DRM_MODE_FLAG_PVSYNC; 368 else 369 flags |= DRM_MODE_FLAG_NVSYNC; 370 } else { 371 if (tmp & DP_ENHANCED_FRAMING) 372 pipe_config->enhanced_framing = true; 373 374 if (tmp & DP_SYNC_HS_HIGH) 375 flags |= DRM_MODE_FLAG_PHSYNC; 376 else 377 flags |= DRM_MODE_FLAG_NHSYNC; 378 379 if (tmp & DP_SYNC_VS_HIGH) 380 flags |= DRM_MODE_FLAG_PVSYNC; 381 else 382 flags |= DRM_MODE_FLAG_NVSYNC; 383 } 384 385 pipe_config->hw.adjusted_mode.flags |= flags; 386 387 if (display->platform.g4x && tmp & DP_COLOR_RANGE_16_235) 388 pipe_config->limited_color_range = true; 389 390 pipe_config->lane_count = REG_FIELD_GET(DP_PORT_WIDTH_MASK, tmp) + 1; 391 392 g4x_dp_get_m_n(pipe_config); 393 394 if (port == PORT_A) { 395 if ((intel_de_read(display, DP_A) & EDP_PLL_FREQ_MASK) == EDP_PLL_FREQ_162MHZ) 396 pipe_config->port_clock = 162000; 397 else 398 pipe_config->port_clock = 270000; 399 } 400 401 pipe_config->hw.adjusted_mode.crtc_clock = 402 intel_dotclock_calculate(pipe_config->port_clock, 403 &pipe_config->dp_m_n); 404 405 if (intel_dp_is_edp(intel_dp)) 406 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); 407 408 intel_audio_codec_get_config(encoder, pipe_config); 409 } 410 411 static void 412 intel_dp_link_down(struct intel_encoder *encoder, 413 const struct intel_crtc_state *old_crtc_state) 414 { 415 struct intel_display *display = to_intel_display(encoder); 416 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 417 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 418 enum port port = encoder->port; 419 420 if (drm_WARN_ON(display->drm, 421 (intel_de_read(display, intel_dp->output_reg) & 422 DP_PORT_EN) == 0)) 423 return; 424 425 drm_dbg_kms(display->drm, "\n"); 426 427 if ((display->platform.ivybridge && port == PORT_A) || 428 (HAS_PCH_CPT(display) && port != PORT_A)) { 429 intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT; 430 intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; 431 } else { 432 intel_dp->DP &= ~DP_LINK_TRAIN_MASK; 433 intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE; 434 } 435 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); 436 intel_de_posting_read(display, intel_dp->output_reg); 437 438 intel_dp->DP &= ~DP_PORT_EN; 439 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); 440 intel_de_posting_read(display, intel_dp->output_reg); 441 442 /* 443 * HW workaround for IBX, we need to move the port 444 * to transcoder A after disabling it to allow the 445 * matching HDMI port to be enabled on transcoder A. 446 */ 447 if (HAS_PCH_IBX(display) && crtc->pipe == PIPE_B && port != PORT_A) { 448 /* 449 * We get CPU/PCH FIFO underruns on the other pipe when 450 * doing the workaround. Sweep them under the rug. 451 */ 452 intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, false); 453 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false); 454 455 /* always enable with pattern 1 (as per spec) */ 456 intel_dp->DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK); 457 intel_dp->DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) | 458 DP_LINK_TRAIN_PAT_1; 459 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); 460 intel_de_posting_read(display, intel_dp->output_reg); 461 462 intel_dp->DP &= ~DP_PORT_EN; 463 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); 464 intel_de_posting_read(display, intel_dp->output_reg); 465 466 intel_wait_for_vblank_if_active(display, PIPE_A); 467 intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, true); 468 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true); 469 } 470 471 msleep(intel_dp->pps.panel_power_down_delay); 472 473 if (display->platform.valleyview || display->platform.cherryview) 474 vlv_pps_port_disable(encoder, old_crtc_state); 475 } 476 477 static void g4x_dp_audio_enable(struct intel_encoder *encoder, 478 const struct intel_crtc_state *crtc_state, 479 const struct drm_connector_state *conn_state) 480 { 481 struct intel_display *display = to_intel_display(encoder); 482 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 483 484 if (!crtc_state->has_audio) 485 return; 486 487 /* Enable audio presence detect */ 488 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; 489 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); 490 491 intel_audio_codec_enable(encoder, crtc_state, conn_state); 492 } 493 494 static void g4x_dp_audio_disable(struct intel_encoder *encoder, 495 const struct intel_crtc_state *old_crtc_state, 496 const struct drm_connector_state *old_conn_state) 497 { 498 struct intel_display *display = to_intel_display(encoder); 499 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 500 501 if (!old_crtc_state->has_audio) 502 return; 503 504 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); 505 506 /* Disable audio presence detect */ 507 intel_dp->DP &= ~DP_AUDIO_OUTPUT_ENABLE; 508 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); 509 } 510 511 static void intel_disable_dp(struct intel_atomic_state *state, 512 struct intel_encoder *encoder, 513 const struct intel_crtc_state *old_crtc_state, 514 const struct drm_connector_state *old_conn_state) 515 { 516 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 517 518 intel_dp->link.active = false; 519 520 /* 521 * Make sure the panel is off before trying to change the mode. 522 * But also ensure that we have vdd while we switch off the panel. 523 */ 524 intel_pps_vdd_on(intel_dp); 525 intel_edp_backlight_off(old_conn_state); 526 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 527 intel_pps_off(intel_dp); 528 } 529 530 static void g4x_disable_dp(struct intel_atomic_state *state, 531 struct intel_encoder *encoder, 532 const struct intel_crtc_state *old_crtc_state, 533 const struct drm_connector_state *old_conn_state) 534 { 535 intel_disable_dp(state, encoder, old_crtc_state, old_conn_state); 536 } 537 538 static void vlv_disable_dp(struct intel_atomic_state *state, 539 struct intel_encoder *encoder, 540 const struct intel_crtc_state *old_crtc_state, 541 const struct drm_connector_state *old_conn_state) 542 { 543 intel_disable_dp(state, encoder, old_crtc_state, old_conn_state); 544 } 545 546 static void g4x_post_disable_dp(struct intel_atomic_state *state, 547 struct intel_encoder *encoder, 548 const struct intel_crtc_state *old_crtc_state, 549 const struct drm_connector_state *old_conn_state) 550 { 551 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 552 enum port port = encoder->port; 553 554 /* 555 * Bspec does not list a specific disable sequence for g4x DP. 556 * Follow the ilk+ sequence (disable pipe before the port) for 557 * g4x DP as it does not suffer from underruns like the normal 558 * g4x modeset sequence (disable pipe after the port). 559 */ 560 intel_dp_link_down(encoder, old_crtc_state); 561 562 /* Only ilk+ has port A */ 563 if (port == PORT_A) 564 ilk_edp_pll_off(intel_dp, old_crtc_state); 565 } 566 567 static void vlv_post_disable_dp(struct intel_atomic_state *state, 568 struct intel_encoder *encoder, 569 const struct intel_crtc_state *old_crtc_state, 570 const struct drm_connector_state *old_conn_state) 571 { 572 intel_dp_link_down(encoder, old_crtc_state); 573 } 574 575 static void chv_post_disable_dp(struct intel_atomic_state *state, 576 struct intel_encoder *encoder, 577 const struct intel_crtc_state *old_crtc_state, 578 const struct drm_connector_state *old_conn_state) 579 { 580 intel_dp_link_down(encoder, old_crtc_state); 581 582 /* Assert data lane reset */ 583 chv_data_lane_soft_reset(encoder, old_crtc_state, true); 584 } 585 586 static void 587 cpt_set_link_train(struct intel_dp *intel_dp, 588 const struct intel_crtc_state *crtc_state, 589 u8 dp_train_pat) 590 { 591 struct intel_display *display = to_intel_display(intel_dp); 592 593 intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT; 594 595 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 596 case DP_TRAINING_PATTERN_DISABLE: 597 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 598 break; 599 case DP_TRAINING_PATTERN_1: 600 intel_dp->DP |= DP_LINK_TRAIN_PAT_1_CPT; 601 break; 602 case DP_TRAINING_PATTERN_2: 603 intel_dp->DP |= DP_LINK_TRAIN_PAT_2_CPT; 604 break; 605 default: 606 MISSING_CASE(intel_dp_training_pattern_symbol(dp_train_pat)); 607 return; 608 } 609 610 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); 611 intel_de_posting_read(display, intel_dp->output_reg); 612 } 613 614 static void 615 g4x_set_link_train(struct intel_dp *intel_dp, 616 const struct intel_crtc_state *crtc_state, 617 u8 dp_train_pat) 618 { 619 struct intel_display *display = to_intel_display(intel_dp); 620 621 intel_dp->DP &= ~DP_LINK_TRAIN_MASK; 622 623 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 624 case DP_TRAINING_PATTERN_DISABLE: 625 intel_dp->DP |= DP_LINK_TRAIN_OFF; 626 break; 627 case DP_TRAINING_PATTERN_1: 628 intel_dp->DP |= DP_LINK_TRAIN_PAT_1; 629 break; 630 case DP_TRAINING_PATTERN_2: 631 intel_dp->DP |= DP_LINK_TRAIN_PAT_2; 632 break; 633 default: 634 MISSING_CASE(intel_dp_training_pattern_symbol(dp_train_pat)); 635 return; 636 } 637 638 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); 639 intel_de_posting_read(display, intel_dp->output_reg); 640 } 641 642 static void intel_dp_enable_port(struct intel_dp *intel_dp, 643 const struct intel_crtc_state *crtc_state) 644 { 645 struct intel_display *display = to_intel_display(intel_dp); 646 647 /* enable with pattern 1 (as per spec) */ 648 649 intel_dp_program_link_training_pattern(intel_dp, crtc_state, 650 DP_PHY_DPRX, DP_TRAINING_PATTERN_1); 651 652 /* 653 * Magic for VLV/CHV. We _must_ first set up the register 654 * without actually enabling the port, and then do another 655 * write to enable the port. Otherwise link training will 656 * fail when the power sequencer is freshly used for this port. 657 */ 658 intel_dp->DP |= DP_PORT_EN; 659 660 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); 661 intel_de_posting_read(display, intel_dp->output_reg); 662 } 663 664 static void intel_enable_dp(struct intel_atomic_state *state, 665 struct intel_encoder *encoder, 666 const struct intel_crtc_state *pipe_config, 667 const struct drm_connector_state *conn_state) 668 { 669 struct intel_display *display = to_intel_display(state); 670 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 671 u32 dp_reg = intel_de_read(display, intel_dp->output_reg); 672 intel_wakeref_t wakeref; 673 674 if (drm_WARN_ON(display->drm, dp_reg & DP_PORT_EN)) 675 return; 676 677 with_intel_pps_lock(intel_dp, wakeref) { 678 if (display->platform.valleyview || display->platform.cherryview) 679 vlv_pps_port_enable_unlocked(encoder, pipe_config); 680 681 intel_dp_enable_port(intel_dp, pipe_config); 682 683 intel_pps_vdd_on_unlocked(intel_dp); 684 intel_pps_on_unlocked(intel_dp); 685 intel_pps_vdd_off_unlocked(intel_dp, true); 686 } 687 688 if (display->platform.valleyview || display->platform.cherryview) { 689 unsigned int lane_mask = 0x0; 690 691 if (display->platform.cherryview) 692 lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count); 693 694 vlv_wait_port_ready(encoder, lane_mask); 695 } 696 697 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 698 intel_dp_configure_protocol_converter(intel_dp, pipe_config); 699 intel_dp_check_frl_training(intel_dp); 700 intel_dp_pcon_dsc_configure(intel_dp, pipe_config); 701 intel_dp_start_link_train(state, intel_dp, pipe_config); 702 intel_dp_stop_link_train(intel_dp, pipe_config); 703 } 704 705 static void g4x_enable_dp(struct intel_atomic_state *state, 706 struct intel_encoder *encoder, 707 const struct intel_crtc_state *pipe_config, 708 const struct drm_connector_state *conn_state) 709 { 710 intel_enable_dp(state, encoder, pipe_config, conn_state); 711 intel_edp_backlight_on(pipe_config, conn_state); 712 } 713 714 static void vlv_enable_dp(struct intel_atomic_state *state, 715 struct intel_encoder *encoder, 716 const struct intel_crtc_state *pipe_config, 717 const struct drm_connector_state *conn_state) 718 { 719 intel_edp_backlight_on(pipe_config, conn_state); 720 } 721 722 static void g4x_pre_enable_dp(struct intel_atomic_state *state, 723 struct intel_encoder *encoder, 724 const struct intel_crtc_state *pipe_config, 725 const struct drm_connector_state *conn_state) 726 { 727 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 728 enum port port = encoder->port; 729 730 intel_dp_prepare(encoder, pipe_config); 731 732 /* Only ilk+ has port A */ 733 if (port == PORT_A) 734 ilk_edp_pll_on(intel_dp, pipe_config); 735 } 736 737 static void vlv_pre_enable_dp(struct intel_atomic_state *state, 738 struct intel_encoder *encoder, 739 const struct intel_crtc_state *pipe_config, 740 const struct drm_connector_state *conn_state) 741 { 742 vlv_phy_pre_encoder_enable(encoder, pipe_config); 743 744 intel_enable_dp(state, encoder, pipe_config, conn_state); 745 } 746 747 static void vlv_dp_pre_pll_enable(struct intel_atomic_state *state, 748 struct intel_encoder *encoder, 749 const struct intel_crtc_state *pipe_config, 750 const struct drm_connector_state *conn_state) 751 { 752 intel_dp_prepare(encoder, pipe_config); 753 754 vlv_phy_pre_pll_enable(encoder, pipe_config); 755 } 756 757 static void chv_pre_enable_dp(struct intel_atomic_state *state, 758 struct intel_encoder *encoder, 759 const struct intel_crtc_state *pipe_config, 760 const struct drm_connector_state *conn_state) 761 { 762 chv_phy_pre_encoder_enable(encoder, pipe_config); 763 764 intel_enable_dp(state, encoder, pipe_config, conn_state); 765 766 /* Second common lane will stay alive on its own now */ 767 chv_phy_release_cl2_override(encoder); 768 } 769 770 static void chv_dp_pre_pll_enable(struct intel_atomic_state *state, 771 struct intel_encoder *encoder, 772 const struct intel_crtc_state *pipe_config, 773 const struct drm_connector_state *conn_state) 774 { 775 intel_dp_prepare(encoder, pipe_config); 776 777 chv_phy_pre_pll_enable(encoder, pipe_config); 778 } 779 780 static void chv_dp_post_pll_disable(struct intel_atomic_state *state, 781 struct intel_encoder *encoder, 782 const struct intel_crtc_state *old_crtc_state, 783 const struct drm_connector_state *old_conn_state) 784 { 785 chv_phy_post_pll_disable(encoder, old_crtc_state); 786 } 787 788 static u8 intel_dp_voltage_max_2(struct intel_dp *intel_dp, 789 const struct intel_crtc_state *crtc_state) 790 { 791 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 792 } 793 794 static u8 intel_dp_voltage_max_3(struct intel_dp *intel_dp, 795 const struct intel_crtc_state *crtc_state) 796 { 797 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 798 } 799 800 static u8 intel_dp_preemph_max_2(struct intel_dp *intel_dp) 801 { 802 return DP_TRAIN_PRE_EMPH_LEVEL_2; 803 } 804 805 static u8 intel_dp_preemph_max_3(struct intel_dp *intel_dp) 806 { 807 return DP_TRAIN_PRE_EMPH_LEVEL_3; 808 } 809 810 static void vlv_set_signal_levels(struct intel_encoder *encoder, 811 const struct intel_crtc_state *crtc_state) 812 { 813 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 814 unsigned long demph_reg_value, preemph_reg_value, 815 uniqtranscale_reg_value; 816 u8 train_set = intel_dp->train_set[0]; 817 818 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 819 case DP_TRAIN_PRE_EMPH_LEVEL_0: 820 preemph_reg_value = 0x0004000; 821 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 822 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 823 demph_reg_value = 0x2B405555; 824 uniqtranscale_reg_value = 0x552AB83A; 825 break; 826 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 827 demph_reg_value = 0x2B404040; 828 uniqtranscale_reg_value = 0x5548B83A; 829 break; 830 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 831 demph_reg_value = 0x2B245555; 832 uniqtranscale_reg_value = 0x5560B83A; 833 break; 834 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 835 demph_reg_value = 0x2B405555; 836 uniqtranscale_reg_value = 0x5598DA3A; 837 break; 838 default: 839 return; 840 } 841 break; 842 case DP_TRAIN_PRE_EMPH_LEVEL_1: 843 preemph_reg_value = 0x0002000; 844 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 845 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 846 demph_reg_value = 0x2B404040; 847 uniqtranscale_reg_value = 0x5552B83A; 848 break; 849 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 850 demph_reg_value = 0x2B404848; 851 uniqtranscale_reg_value = 0x5580B83A; 852 break; 853 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 854 demph_reg_value = 0x2B404040; 855 uniqtranscale_reg_value = 0x55ADDA3A; 856 break; 857 default: 858 return; 859 } 860 break; 861 case DP_TRAIN_PRE_EMPH_LEVEL_2: 862 preemph_reg_value = 0x0000000; 863 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 864 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 865 demph_reg_value = 0x2B305555; 866 uniqtranscale_reg_value = 0x5570B83A; 867 break; 868 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 869 demph_reg_value = 0x2B2B4040; 870 uniqtranscale_reg_value = 0x55ADDA3A; 871 break; 872 default: 873 return; 874 } 875 break; 876 case DP_TRAIN_PRE_EMPH_LEVEL_3: 877 preemph_reg_value = 0x0006000; 878 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 879 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 880 demph_reg_value = 0x1B405555; 881 uniqtranscale_reg_value = 0x55ADDA3A; 882 break; 883 default: 884 return; 885 } 886 break; 887 default: 888 return; 889 } 890 891 vlv_set_phy_signal_level(encoder, crtc_state, 892 demph_reg_value, preemph_reg_value, 893 uniqtranscale_reg_value, 0); 894 } 895 896 static void chv_set_signal_levels(struct intel_encoder *encoder, 897 const struct intel_crtc_state *crtc_state) 898 { 899 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 900 u32 deemph_reg_value, margin_reg_value; 901 bool uniq_trans_scale = false; 902 u8 train_set = intel_dp->train_set[0]; 903 904 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 905 case DP_TRAIN_PRE_EMPH_LEVEL_0: 906 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 907 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 908 deemph_reg_value = 128; 909 margin_reg_value = 52; 910 break; 911 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 912 deemph_reg_value = 128; 913 margin_reg_value = 77; 914 break; 915 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 916 deemph_reg_value = 128; 917 margin_reg_value = 102; 918 break; 919 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 920 deemph_reg_value = 128; 921 margin_reg_value = 154; 922 uniq_trans_scale = true; 923 break; 924 default: 925 return; 926 } 927 break; 928 case DP_TRAIN_PRE_EMPH_LEVEL_1: 929 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 930 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 931 deemph_reg_value = 85; 932 margin_reg_value = 78; 933 break; 934 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 935 deemph_reg_value = 85; 936 margin_reg_value = 116; 937 break; 938 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 939 deemph_reg_value = 85; 940 margin_reg_value = 154; 941 break; 942 default: 943 return; 944 } 945 break; 946 case DP_TRAIN_PRE_EMPH_LEVEL_2: 947 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 948 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 949 deemph_reg_value = 64; 950 margin_reg_value = 104; 951 break; 952 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 953 deemph_reg_value = 64; 954 margin_reg_value = 154; 955 break; 956 default: 957 return; 958 } 959 break; 960 case DP_TRAIN_PRE_EMPH_LEVEL_3: 961 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 962 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 963 deemph_reg_value = 43; 964 margin_reg_value = 154; 965 break; 966 default: 967 return; 968 } 969 break; 970 default: 971 return; 972 } 973 974 chv_set_phy_signal_level(encoder, crtc_state, 975 deemph_reg_value, margin_reg_value, 976 uniq_trans_scale); 977 } 978 979 static u32 g4x_signal_levels(u8 train_set) 980 { 981 u32 signal_levels = 0; 982 983 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 984 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 985 default: 986 signal_levels |= DP_VOLTAGE_0_4; 987 break; 988 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 989 signal_levels |= DP_VOLTAGE_0_6; 990 break; 991 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 992 signal_levels |= DP_VOLTAGE_0_8; 993 break; 994 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 995 signal_levels |= DP_VOLTAGE_1_2; 996 break; 997 } 998 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 999 case DP_TRAIN_PRE_EMPH_LEVEL_0: 1000 default: 1001 signal_levels |= DP_PRE_EMPHASIS_0; 1002 break; 1003 case DP_TRAIN_PRE_EMPH_LEVEL_1: 1004 signal_levels |= DP_PRE_EMPHASIS_3_5; 1005 break; 1006 case DP_TRAIN_PRE_EMPH_LEVEL_2: 1007 signal_levels |= DP_PRE_EMPHASIS_6; 1008 break; 1009 case DP_TRAIN_PRE_EMPH_LEVEL_3: 1010 signal_levels |= DP_PRE_EMPHASIS_9_5; 1011 break; 1012 } 1013 return signal_levels; 1014 } 1015 1016 static void 1017 g4x_set_signal_levels(struct intel_encoder *encoder, 1018 const struct intel_crtc_state *crtc_state) 1019 { 1020 struct intel_display *display = to_intel_display(encoder); 1021 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1022 u8 train_set = intel_dp->train_set[0]; 1023 u32 signal_levels; 1024 1025 signal_levels = g4x_signal_levels(train_set); 1026 1027 drm_dbg_kms(display->drm, "Using signal levels %08x\n", 1028 signal_levels); 1029 1030 intel_dp->DP &= ~(DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK); 1031 intel_dp->DP |= signal_levels; 1032 1033 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); 1034 intel_de_posting_read(display, intel_dp->output_reg); 1035 } 1036 1037 /* SNB CPU eDP voltage swing and pre-emphasis control */ 1038 static u32 snb_cpu_edp_signal_levels(u8 train_set) 1039 { 1040 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1041 DP_TRAIN_PRE_EMPHASIS_MASK); 1042 1043 switch (signal_levels) { 1044 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1045 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1046 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 1047 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: 1048 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; 1049 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: 1050 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: 1051 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; 1052 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: 1053 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: 1054 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; 1055 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1056 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1057 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; 1058 default: 1059 MISSING_CASE(signal_levels); 1060 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 1061 } 1062 } 1063 1064 static void 1065 snb_cpu_edp_set_signal_levels(struct intel_encoder *encoder, 1066 const struct intel_crtc_state *crtc_state) 1067 { 1068 struct intel_display *display = to_intel_display(encoder); 1069 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1070 u8 train_set = intel_dp->train_set[0]; 1071 u32 signal_levels; 1072 1073 signal_levels = snb_cpu_edp_signal_levels(train_set); 1074 1075 drm_dbg_kms(display->drm, "Using signal levels %08x\n", 1076 signal_levels); 1077 1078 intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; 1079 intel_dp->DP |= signal_levels; 1080 1081 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); 1082 intel_de_posting_read(display, intel_dp->output_reg); 1083 } 1084 1085 /* IVB CPU eDP voltage swing and pre-emphasis control */ 1086 static u32 ivb_cpu_edp_signal_levels(u8 train_set) 1087 { 1088 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1089 DP_TRAIN_PRE_EMPHASIS_MASK); 1090 1091 switch (signal_levels) { 1092 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1093 return EDP_LINK_TRAIN_400MV_0DB_IVB; 1094 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: 1095 return EDP_LINK_TRAIN_400MV_3_5DB_IVB; 1096 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: 1097 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: 1098 return EDP_LINK_TRAIN_400MV_6DB_IVB; 1099 1100 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1101 return EDP_LINK_TRAIN_600MV_0DB_IVB; 1102 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: 1103 return EDP_LINK_TRAIN_600MV_3_5DB_IVB; 1104 1105 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1106 return EDP_LINK_TRAIN_800MV_0DB_IVB; 1107 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: 1108 return EDP_LINK_TRAIN_800MV_3_5DB_IVB; 1109 1110 default: 1111 MISSING_CASE(signal_levels); 1112 return EDP_LINK_TRAIN_500MV_0DB_IVB; 1113 } 1114 } 1115 1116 static void 1117 ivb_cpu_edp_set_signal_levels(struct intel_encoder *encoder, 1118 const struct intel_crtc_state *crtc_state) 1119 { 1120 struct intel_display *display = to_intel_display(encoder); 1121 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1122 u8 train_set = intel_dp->train_set[0]; 1123 u32 signal_levels; 1124 1125 signal_levels = ivb_cpu_edp_signal_levels(train_set); 1126 1127 drm_dbg_kms(display->drm, "Using signal levels %08x\n", 1128 signal_levels); 1129 1130 intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; 1131 intel_dp->DP |= signal_levels; 1132 1133 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); 1134 intel_de_posting_read(display, intel_dp->output_reg); 1135 } 1136 1137 /* 1138 * If display is now connected check links status, 1139 * there has been known issues of link loss triggering 1140 * long pulse. 1141 * 1142 * Some sinks (eg. ASUS PB287Q) seem to perform some 1143 * weird HPD ping pong during modesets. So we can apparently 1144 * end up with HPD going low during a modeset, and then 1145 * going back up soon after. And once that happens we must 1146 * retrain the link to get a picture. That's in case no 1147 * userspace component reacted to intermittent HPD dip. 1148 */ 1149 static enum intel_hotplug_state 1150 intel_dp_hotplug(struct intel_encoder *encoder, 1151 struct intel_connector *connector) 1152 { 1153 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1154 enum intel_hotplug_state state; 1155 1156 if (intel_dp_test_phy(intel_dp)) 1157 return INTEL_HOTPLUG_UNCHANGED; 1158 1159 state = intel_encoder_hotplug(encoder, connector); 1160 1161 intel_dp_check_link_state(intel_dp); 1162 1163 /* 1164 * Keeping it consistent with intel_ddi_hotplug() and 1165 * intel_hdmi_hotplug(). 1166 */ 1167 if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries) 1168 state = INTEL_HOTPLUG_RETRY; 1169 1170 return state; 1171 } 1172 1173 static bool ibx_digital_port_connected(struct intel_encoder *encoder) 1174 { 1175 struct intel_display *display = to_intel_display(encoder); 1176 u32 bit = display->hotplug.pch_hpd[encoder->hpd_pin]; 1177 1178 return intel_de_read(display, SDEISR) & bit; 1179 } 1180 1181 static bool g4x_digital_port_connected(struct intel_encoder *encoder) 1182 { 1183 struct intel_display *display = to_intel_display(encoder); 1184 u32 bit; 1185 1186 switch (encoder->hpd_pin) { 1187 case HPD_PORT_B: 1188 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; 1189 break; 1190 case HPD_PORT_C: 1191 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; 1192 break; 1193 case HPD_PORT_D: 1194 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; 1195 break; 1196 default: 1197 MISSING_CASE(encoder->hpd_pin); 1198 return false; 1199 } 1200 1201 return intel_de_read(display, PORT_HOTPLUG_STAT(display)) & bit; 1202 } 1203 1204 static bool ilk_digital_port_connected(struct intel_encoder *encoder) 1205 { 1206 struct intel_display *display = to_intel_display(encoder); 1207 u32 bit = display->hotplug.hpd[encoder->hpd_pin]; 1208 1209 return intel_de_read(display, DEISR) & bit; 1210 } 1211 1212 static int g4x_dp_compute_config(struct intel_encoder *encoder, 1213 struct intel_crtc_state *crtc_state, 1214 struct drm_connector_state *conn_state) 1215 { 1216 struct intel_display *display = to_intel_display(encoder); 1217 int ret; 1218 1219 if (HAS_PCH_SPLIT(display) && encoder->port != PORT_A) 1220 crtc_state->has_pch_encoder = true; 1221 1222 ret = intel_dp_compute_config(encoder, crtc_state, conn_state); 1223 if (ret) 1224 return ret; 1225 1226 g4x_dp_set_clock(encoder, crtc_state); 1227 1228 return 0; 1229 } 1230 1231 static void g4x_dp_suspend_complete(struct intel_encoder *encoder) 1232 { 1233 /* 1234 * TODO: Move this to intel_dp_encoder_suspend(), 1235 * once modeset locking around that is removed. 1236 */ 1237 intel_encoder_link_check_flush_work(encoder); 1238 } 1239 1240 static void intel_dp_encoder_destroy(struct drm_encoder *encoder) 1241 { 1242 intel_dp_encoder_flush_work(encoder); 1243 1244 drm_encoder_cleanup(encoder); 1245 kfree(enc_to_dig_port(to_intel_encoder(encoder))); 1246 } 1247 1248 static void intel_dp_encoder_reset(struct drm_encoder *encoder) 1249 { 1250 struct intel_display *display = to_intel_display(encoder->dev); 1251 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 1252 1253 intel_dp->DP = intel_de_read(display, intel_dp->output_reg); 1254 1255 intel_dp->reset_link_params = true; 1256 intel_dp_invalidate_source_oui(intel_dp); 1257 1258 if (display->platform.valleyview || display->platform.cherryview) 1259 vlv_pps_pipe_reset(intel_dp); 1260 1261 intel_pps_encoder_reset(intel_dp); 1262 } 1263 1264 static const struct drm_encoder_funcs intel_dp_enc_funcs = { 1265 .reset = intel_dp_encoder_reset, 1266 .destroy = intel_dp_encoder_destroy, 1267 }; 1268 1269 bool g4x_dp_init(struct intel_display *display, 1270 i915_reg_t output_reg, enum port port) 1271 { 1272 const struct intel_bios_encoder_data *devdata; 1273 struct intel_digital_port *dig_port; 1274 struct intel_encoder *intel_encoder; 1275 struct drm_encoder *encoder; 1276 struct intel_connector *intel_connector; 1277 1278 if (!assert_port_valid(display, port)) 1279 return false; 1280 1281 devdata = intel_bios_encoder_data_lookup(display, port); 1282 1283 /* FIXME bail? */ 1284 if (!devdata) 1285 drm_dbg_kms(display->drm, "No VBT child device for DP-%c\n", 1286 port_name(port)); 1287 1288 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 1289 if (!dig_port) 1290 return false; 1291 1292 dig_port->aux_ch = AUX_CH_NONE; 1293 1294 intel_connector = intel_connector_alloc(); 1295 if (!intel_connector) 1296 goto err_connector_alloc; 1297 1298 intel_encoder = &dig_port->base; 1299 encoder = &intel_encoder->base; 1300 1301 intel_encoder->devdata = devdata; 1302 1303 mutex_init(&dig_port->hdcp.mutex); 1304 1305 if (drm_encoder_init(display->drm, &intel_encoder->base, 1306 &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS, 1307 "DP %c", port_name(port))) 1308 goto err_encoder_init; 1309 1310 intel_encoder_link_check_init(intel_encoder, intel_dp_link_check); 1311 1312 intel_encoder->hotplug = intel_dp_hotplug; 1313 intel_encoder->compute_config = g4x_dp_compute_config; 1314 intel_encoder->get_hw_state = intel_dp_get_hw_state; 1315 intel_encoder->get_config = intel_dp_get_config; 1316 intel_encoder->sync_state = intel_dp_sync_state; 1317 intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check; 1318 intel_encoder->update_pipe = intel_backlight_update; 1319 intel_encoder->suspend = intel_dp_encoder_suspend; 1320 intel_encoder->suspend_complete = g4x_dp_suspend_complete; 1321 intel_encoder->shutdown = intel_dp_encoder_shutdown; 1322 if (display->platform.cherryview) { 1323 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; 1324 intel_encoder->pre_enable = chv_pre_enable_dp; 1325 intel_encoder->enable = vlv_enable_dp; 1326 intel_encoder->disable = vlv_disable_dp; 1327 intel_encoder->post_disable = chv_post_disable_dp; 1328 intel_encoder->post_pll_disable = chv_dp_post_pll_disable; 1329 } else if (display->platform.valleyview) { 1330 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; 1331 intel_encoder->pre_enable = vlv_pre_enable_dp; 1332 intel_encoder->enable = vlv_enable_dp; 1333 intel_encoder->disable = vlv_disable_dp; 1334 intel_encoder->post_disable = vlv_post_disable_dp; 1335 } else { 1336 intel_encoder->pre_enable = g4x_pre_enable_dp; 1337 intel_encoder->enable = g4x_enable_dp; 1338 intel_encoder->disable = g4x_disable_dp; 1339 intel_encoder->post_disable = g4x_post_disable_dp; 1340 } 1341 intel_encoder->audio_enable = g4x_dp_audio_enable; 1342 intel_encoder->audio_disable = g4x_dp_audio_disable; 1343 1344 if ((display->platform.ivybridge && port == PORT_A) || 1345 (HAS_PCH_CPT(display) && port != PORT_A)) 1346 dig_port->dp.set_link_train = cpt_set_link_train; 1347 else 1348 dig_port->dp.set_link_train = g4x_set_link_train; 1349 1350 if (display->platform.cherryview) 1351 intel_encoder->set_signal_levels = chv_set_signal_levels; 1352 else if (display->platform.valleyview) 1353 intel_encoder->set_signal_levels = vlv_set_signal_levels; 1354 else if (display->platform.ivybridge && port == PORT_A) 1355 intel_encoder->set_signal_levels = ivb_cpu_edp_set_signal_levels; 1356 else if (display->platform.sandybridge && port == PORT_A) 1357 intel_encoder->set_signal_levels = snb_cpu_edp_set_signal_levels; 1358 else 1359 intel_encoder->set_signal_levels = g4x_set_signal_levels; 1360 1361 if (display->platform.valleyview || display->platform.cherryview || 1362 (HAS_PCH_SPLIT(display) && port != PORT_A)) { 1363 dig_port->dp.preemph_max = intel_dp_preemph_max_3; 1364 dig_port->dp.voltage_max = intel_dp_voltage_max_3; 1365 } else { 1366 dig_port->dp.preemph_max = intel_dp_preemph_max_2; 1367 dig_port->dp.voltage_max = intel_dp_voltage_max_2; 1368 } 1369 1370 dig_port->dp.output_reg = output_reg; 1371 dig_port->max_lanes = 4; 1372 1373 intel_encoder->type = INTEL_OUTPUT_DP; 1374 intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port); 1375 if (display->platform.cherryview) { 1376 if (port == PORT_D) 1377 intel_encoder->pipe_mask = BIT(PIPE_C); 1378 else 1379 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); 1380 } else { 1381 intel_encoder->pipe_mask = ~0; 1382 } 1383 intel_encoder->cloneable = 0; 1384 intel_encoder->port = port; 1385 intel_encoder->hpd_pin = intel_hpd_pin_default(port); 1386 1387 dig_port->hpd_pulse = intel_dp_hpd_pulse; 1388 1389 if (HAS_GMCH(display)) { 1390 dig_port->connected = g4x_digital_port_connected; 1391 } else { 1392 if (port == PORT_A) 1393 dig_port->connected = ilk_digital_port_connected; 1394 else 1395 dig_port->connected = ibx_digital_port_connected; 1396 } 1397 1398 if (port != PORT_A) 1399 intel_infoframe_init(dig_port); 1400 1401 dig_port->aux_ch = intel_dp_aux_ch(intel_encoder); 1402 if (dig_port->aux_ch == AUX_CH_NONE) 1403 goto err_init_connector; 1404 1405 if (!intel_dp_init_connector(dig_port, intel_connector)) 1406 goto err_init_connector; 1407 1408 return true; 1409 1410 err_init_connector: 1411 drm_encoder_cleanup(encoder); 1412 err_encoder_init: 1413 kfree(intel_connector); 1414 err_connector_alloc: 1415 kfree(dig_port); 1416 return false; 1417 } 1418