1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 * 5 * DisplayPort support for G4x,ILK,SNB,IVB,VLV,CHV (HSW+ handled by the DDI code). 6 */ 7 8 #include <linux/string_helpers.h> 9 10 #include <drm/drm_print.h> 11 12 #include "g4x_dp.h" 13 #include "i915_reg.h" 14 #include "i915_utils.h" 15 #include "intel_audio.h" 16 #include "intel_backlight.h" 17 #include "intel_connector.h" 18 #include "intel_crtc.h" 19 #include "intel_de.h" 20 #include "intel_display_power.h" 21 #include "intel_display_types.h" 22 #include "intel_dp.h" 23 #include "intel_dp_aux.h" 24 #include "intel_dp_link_training.h" 25 #include "intel_dp_test.h" 26 #include "intel_dpio_phy.h" 27 #include "intel_encoder.h" 28 #include "intel_fifo_underrun.h" 29 #include "intel_hdmi.h" 30 #include "intel_hotplug.h" 31 #include "intel_pch_display.h" 32 #include "intel_pps.h" 33 34 static const struct dpll g4x_dpll[] = { 35 { .dot = 162000, .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8, }, 36 { .dot = 270000, .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2, }, 37 }; 38 39 static const struct dpll pch_dpll[] = { 40 { .dot = 162000, .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9, }, 41 { .dot = 270000, .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8, }, 42 }; 43 44 static const struct dpll vlv_dpll[] = { 45 { .dot = 162000, .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81, }, 46 { .dot = 270000, .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27, }, 47 }; 48 49 static const struct dpll chv_dpll[] = { 50 /* m2 is .22 binary fixed point */ 51 { .dot = 162000, .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ }, 52 { .dot = 270000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 /* 27.0 */ }, 53 }; 54 55 const struct dpll *vlv_get_dpll(struct intel_display *display) 56 { 57 return display->platform.cherryview ? &chv_dpll[0] : &vlv_dpll[0]; 58 } 59 60 static void g4x_dp_set_clock(struct intel_encoder *encoder, 61 struct intel_crtc_state *pipe_config) 62 { 63 struct intel_display *display = to_intel_display(encoder); 64 const struct dpll *divisor = NULL; 65 int i, count = 0; 66 67 if (display->platform.g4x) { 68 divisor = g4x_dpll; 69 count = ARRAY_SIZE(g4x_dpll); 70 } else if (HAS_PCH_SPLIT(display)) { 71 divisor = pch_dpll; 72 count = ARRAY_SIZE(pch_dpll); 73 } else if (display->platform.cherryview) { 74 divisor = chv_dpll; 75 count = ARRAY_SIZE(chv_dpll); 76 } else if (display->platform.valleyview) { 77 divisor = vlv_dpll; 78 count = ARRAY_SIZE(vlv_dpll); 79 } 80 81 if (divisor && count) { 82 for (i = 0; i < count; i++) { 83 if (pipe_config->port_clock == divisor[i].dot) { 84 pipe_config->dpll = divisor[i]; 85 pipe_config->clock_set = true; 86 break; 87 } 88 } 89 } 90 } 91 92 static void intel_dp_prepare(struct intel_encoder *encoder, 93 const struct intel_crtc_state *pipe_config) 94 { 95 struct intel_display *display = to_intel_display(encoder); 96 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 97 enum port port = encoder->port; 98 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 99 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 100 101 intel_dp_set_link_params(intel_dp, 102 pipe_config->port_clock, 103 pipe_config->lane_count); 104 105 /* 106 * There are four kinds of DP registers: 107 * IBX PCH 108 * SNB CPU 109 * IVB CPU 110 * CPT PCH 111 * 112 * IBX PCH and CPU are the same for almost everything, 113 * except that the CPU DP PLL is configured in this 114 * register 115 * 116 * CPT PCH is quite different, having many bits moved 117 * to the TRANS_DP_CTL register instead. That 118 * configuration happens (oddly) in ilk_pch_enable 119 */ 120 121 /* Preserve the BIOS-computed detected bit. This is 122 * supposed to be read-only. 123 */ 124 intel_dp->DP = intel_de_read(display, intel_dp->output_reg) & DP_DETECTED; 125 126 /* Handle DP bits in common between all three register formats */ 127 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 128 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count); 129 130 /* Split out the IBX/CPU vs CPT settings */ 131 132 if (display->platform.ivybridge && port == PORT_A) { 133 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 134 intel_dp->DP |= DP_SYNC_HS_HIGH; 135 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 136 intel_dp->DP |= DP_SYNC_VS_HIGH; 137 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 138 139 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 140 intel_dp->DP |= DP_ENHANCED_FRAMING; 141 142 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe); 143 } else if (HAS_PCH_CPT(display) && port != PORT_A) { 144 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 145 146 intel_de_rmw(display, TRANS_DP_CTL(crtc->pipe), 147 TRANS_DP_ENH_FRAMING, 148 pipe_config->enhanced_framing ? 149 TRANS_DP_ENH_FRAMING : 0); 150 } else { 151 if (display->platform.g4x && pipe_config->limited_color_range) 152 intel_dp->DP |= DP_COLOR_RANGE_16_235; 153 154 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 155 intel_dp->DP |= DP_SYNC_HS_HIGH; 156 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 157 intel_dp->DP |= DP_SYNC_VS_HIGH; 158 intel_dp->DP |= DP_LINK_TRAIN_OFF; 159 160 if (pipe_config->enhanced_framing) 161 intel_dp->DP |= DP_ENHANCED_FRAMING; 162 163 if (display->platform.cherryview) 164 intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe); 165 else 166 intel_dp->DP |= DP_PIPE_SEL(crtc->pipe); 167 } 168 } 169 170 static void assert_dp_port(struct intel_dp *intel_dp, bool state) 171 { 172 struct intel_display *display = to_intel_display(intel_dp); 173 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 174 bool cur_state = intel_de_read(display, intel_dp->output_reg) & DP_PORT_EN; 175 176 INTEL_DISPLAY_STATE_WARN(display, cur_state != state, 177 "[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n", 178 dig_port->base.base.base.id, dig_port->base.base.name, 179 str_on_off(state), str_on_off(cur_state)); 180 } 181 #define assert_dp_port_disabled(d) assert_dp_port((d), false) 182 183 static void assert_edp_pll(struct intel_display *display, bool state) 184 { 185 bool cur_state = intel_de_read(display, DP_A) & EDP_PLL_ENABLE; 186 187 INTEL_DISPLAY_STATE_WARN(display, cur_state != state, 188 "eDP PLL state assertion failure (expected %s, current %s)\n", 189 str_on_off(state), str_on_off(cur_state)); 190 } 191 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true) 192 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false) 193 194 static void ilk_edp_pll_on(struct intel_dp *intel_dp, 195 const struct intel_crtc_state *pipe_config) 196 { 197 struct intel_display *display = to_intel_display(intel_dp); 198 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 199 200 assert_transcoder_disabled(display, pipe_config->cpu_transcoder); 201 assert_dp_port_disabled(intel_dp); 202 assert_edp_pll_disabled(display); 203 204 drm_dbg_kms(display->drm, "enabling eDP PLL for clock %d\n", 205 pipe_config->port_clock); 206 207 intel_dp->DP &= ~EDP_PLL_FREQ_MASK; 208 209 if (pipe_config->port_clock == 162000) 210 intel_dp->DP |= EDP_PLL_FREQ_162MHZ; 211 else 212 intel_dp->DP |= EDP_PLL_FREQ_270MHZ; 213 214 intel_de_write(display, DP_A, intel_dp->DP); 215 intel_de_posting_read(display, DP_A); 216 udelay(500); 217 218 /* 219 * [DevILK] Work around required when enabling DP PLL 220 * while a pipe is enabled going to FDI: 221 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI 222 * 2. Program DP PLL enable 223 */ 224 if (display->platform.ironlake) 225 intel_wait_for_vblank_if_active(display, !crtc->pipe); 226 227 intel_dp->DP |= EDP_PLL_ENABLE; 228 229 intel_de_write(display, DP_A, intel_dp->DP); 230 intel_de_posting_read(display, DP_A); 231 udelay(200); 232 } 233 234 static void ilk_edp_pll_off(struct intel_dp *intel_dp, 235 const struct intel_crtc_state *old_crtc_state) 236 { 237 struct intel_display *display = to_intel_display(intel_dp); 238 239 assert_transcoder_disabled(display, old_crtc_state->cpu_transcoder); 240 assert_dp_port_disabled(intel_dp); 241 assert_edp_pll_enabled(display); 242 243 drm_dbg_kms(display->drm, "disabling eDP PLL\n"); 244 245 intel_dp->DP &= ~EDP_PLL_ENABLE; 246 247 intel_de_write(display, DP_A, intel_dp->DP); 248 intel_de_posting_read(display, DP_A); 249 udelay(200); 250 } 251 252 static bool cpt_dp_port_selected(struct intel_display *display, 253 enum port port, enum pipe *pipe) 254 { 255 enum pipe p; 256 257 for_each_pipe(display, p) { 258 u32 val = intel_de_read(display, TRANS_DP_CTL(p)); 259 260 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) { 261 *pipe = p; 262 return true; 263 } 264 } 265 266 drm_dbg_kms(display->drm, "No pipe for DP port %c found\n", 267 port_name(port)); 268 269 /* must initialize pipe to something for the asserts */ 270 *pipe = PIPE_A; 271 272 return false; 273 } 274 275 bool g4x_dp_port_enabled(struct intel_display *display, 276 i915_reg_t dp_reg, enum port port, 277 enum pipe *pipe) 278 { 279 bool ret; 280 u32 val; 281 282 val = intel_de_read(display, dp_reg); 283 284 ret = val & DP_PORT_EN; 285 286 /* asserts want to know the pipe even if the port is disabled */ 287 if (display->platform.ivybridge && port == PORT_A) 288 *pipe = REG_FIELD_GET(DP_PIPE_SEL_MASK_IVB, val); 289 else if (HAS_PCH_CPT(display) && port != PORT_A) 290 ret &= cpt_dp_port_selected(display, port, pipe); 291 else if (display->platform.cherryview) 292 *pipe = REG_FIELD_GET(DP_PIPE_SEL_MASK_CHV, val); 293 else 294 *pipe = REG_FIELD_GET(DP_PIPE_SEL_MASK, val); 295 296 return ret; 297 } 298 299 static bool intel_dp_get_hw_state(struct intel_encoder *encoder, 300 enum pipe *pipe) 301 { 302 struct intel_display *display = to_intel_display(encoder); 303 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 304 intel_wakeref_t wakeref; 305 bool ret; 306 307 wakeref = intel_display_power_get_if_enabled(display, 308 encoder->power_domain); 309 if (!wakeref) 310 return false; 311 312 ret = g4x_dp_port_enabled(display, intel_dp->output_reg, 313 encoder->port, pipe); 314 315 intel_display_power_put(display, encoder->power_domain, wakeref); 316 317 return ret; 318 } 319 320 static void g4x_dp_get_m_n(struct intel_crtc_state *crtc_state) 321 { 322 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 323 324 if (crtc_state->has_pch_encoder) { 325 intel_pch_transcoder_get_m1_n1(crtc, &crtc_state->dp_m_n); 326 intel_pch_transcoder_get_m2_n2(crtc, &crtc_state->dp_m2_n2); 327 } else { 328 intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder, 329 &crtc_state->dp_m_n); 330 intel_cpu_transcoder_get_m2_n2(crtc, crtc_state->cpu_transcoder, 331 &crtc_state->dp_m2_n2); 332 } 333 } 334 335 static void intel_dp_get_config(struct intel_encoder *encoder, 336 struct intel_crtc_state *pipe_config) 337 { 338 struct intel_display *display = to_intel_display(encoder); 339 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 340 u32 tmp, flags = 0; 341 enum port port = encoder->port; 342 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 343 344 if (encoder->type == INTEL_OUTPUT_EDP) 345 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 346 else 347 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 348 349 tmp = intel_de_read(display, intel_dp->output_reg); 350 351 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; 352 353 if (HAS_PCH_CPT(display) && port != PORT_A) { 354 u32 trans_dp = intel_de_read(display, 355 TRANS_DP_CTL(crtc->pipe)); 356 357 if (trans_dp & TRANS_DP_ENH_FRAMING) 358 pipe_config->enhanced_framing = true; 359 360 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH) 361 flags |= DRM_MODE_FLAG_PHSYNC; 362 else 363 flags |= DRM_MODE_FLAG_NHSYNC; 364 365 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH) 366 flags |= DRM_MODE_FLAG_PVSYNC; 367 else 368 flags |= DRM_MODE_FLAG_NVSYNC; 369 } else { 370 if (tmp & DP_ENHANCED_FRAMING) 371 pipe_config->enhanced_framing = true; 372 373 if (tmp & DP_SYNC_HS_HIGH) 374 flags |= DRM_MODE_FLAG_PHSYNC; 375 else 376 flags |= DRM_MODE_FLAG_NHSYNC; 377 378 if (tmp & DP_SYNC_VS_HIGH) 379 flags |= DRM_MODE_FLAG_PVSYNC; 380 else 381 flags |= DRM_MODE_FLAG_NVSYNC; 382 } 383 384 pipe_config->hw.adjusted_mode.flags |= flags; 385 386 if (display->platform.g4x && tmp & DP_COLOR_RANGE_16_235) 387 pipe_config->limited_color_range = true; 388 389 pipe_config->lane_count = REG_FIELD_GET(DP_PORT_WIDTH_MASK, tmp) + 1; 390 391 g4x_dp_get_m_n(pipe_config); 392 393 if (port == PORT_A) { 394 if ((intel_de_read(display, DP_A) & EDP_PLL_FREQ_MASK) == EDP_PLL_FREQ_162MHZ) 395 pipe_config->port_clock = 162000; 396 else 397 pipe_config->port_clock = 270000; 398 } 399 400 pipe_config->hw.adjusted_mode.crtc_clock = 401 intel_dotclock_calculate(pipe_config->port_clock, 402 &pipe_config->dp_m_n); 403 404 if (intel_dp_is_edp(intel_dp)) 405 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); 406 407 intel_audio_codec_get_config(encoder, pipe_config); 408 } 409 410 static void 411 intel_dp_link_down(struct intel_encoder *encoder, 412 const struct intel_crtc_state *old_crtc_state) 413 { 414 struct intel_display *display = to_intel_display(encoder); 415 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 416 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 417 enum port port = encoder->port; 418 419 if (drm_WARN_ON(display->drm, 420 (intel_de_read(display, intel_dp->output_reg) & 421 DP_PORT_EN) == 0)) 422 return; 423 424 drm_dbg_kms(display->drm, "\n"); 425 426 if ((display->platform.ivybridge && port == PORT_A) || 427 (HAS_PCH_CPT(display) && port != PORT_A)) { 428 intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT; 429 intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; 430 } else { 431 intel_dp->DP &= ~DP_LINK_TRAIN_MASK; 432 intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE; 433 } 434 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); 435 intel_de_posting_read(display, intel_dp->output_reg); 436 437 intel_dp->DP &= ~DP_PORT_EN; 438 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); 439 intel_de_posting_read(display, intel_dp->output_reg); 440 441 /* 442 * HW workaround for IBX, we need to move the port 443 * to transcoder A after disabling it to allow the 444 * matching HDMI port to be enabled on transcoder A. 445 */ 446 if (HAS_PCH_IBX(display) && crtc->pipe == PIPE_B && port != PORT_A) { 447 /* 448 * We get CPU/PCH FIFO underruns on the other pipe when 449 * doing the workaround. Sweep them under the rug. 450 */ 451 intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, false); 452 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false); 453 454 /* always enable with pattern 1 (as per spec) */ 455 intel_dp->DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK); 456 intel_dp->DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) | 457 DP_LINK_TRAIN_PAT_1; 458 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); 459 intel_de_posting_read(display, intel_dp->output_reg); 460 461 intel_dp->DP &= ~DP_PORT_EN; 462 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); 463 intel_de_posting_read(display, intel_dp->output_reg); 464 465 intel_wait_for_vblank_if_active(display, PIPE_A); 466 intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, true); 467 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true); 468 } 469 470 msleep(intel_dp->pps.panel_power_down_delay); 471 472 if (display->platform.valleyview || display->platform.cherryview) 473 vlv_pps_port_disable(encoder, old_crtc_state); 474 } 475 476 static void g4x_dp_audio_enable(struct intel_encoder *encoder, 477 const struct intel_crtc_state *crtc_state, 478 const struct drm_connector_state *conn_state) 479 { 480 struct intel_display *display = to_intel_display(encoder); 481 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 482 483 if (!crtc_state->has_audio) 484 return; 485 486 /* Enable audio presence detect */ 487 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; 488 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); 489 490 intel_audio_codec_enable(encoder, crtc_state, conn_state); 491 } 492 493 static void g4x_dp_audio_disable(struct intel_encoder *encoder, 494 const struct intel_crtc_state *old_crtc_state, 495 const struct drm_connector_state *old_conn_state) 496 { 497 struct intel_display *display = to_intel_display(encoder); 498 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 499 500 if (!old_crtc_state->has_audio) 501 return; 502 503 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); 504 505 /* Disable audio presence detect */ 506 intel_dp->DP &= ~DP_AUDIO_OUTPUT_ENABLE; 507 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); 508 } 509 510 static void intel_disable_dp(struct intel_atomic_state *state, 511 struct intel_encoder *encoder, 512 const struct intel_crtc_state *old_crtc_state, 513 const struct drm_connector_state *old_conn_state) 514 { 515 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 516 517 intel_dp->link.active = false; 518 519 /* 520 * Make sure the panel is off before trying to change the mode. 521 * But also ensure that we have vdd while we switch off the panel. 522 */ 523 intel_pps_vdd_on(intel_dp); 524 intel_edp_backlight_off(old_conn_state); 525 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 526 intel_pps_off(intel_dp); 527 } 528 529 static void g4x_disable_dp(struct intel_atomic_state *state, 530 struct intel_encoder *encoder, 531 const struct intel_crtc_state *old_crtc_state, 532 const struct drm_connector_state *old_conn_state) 533 { 534 intel_disable_dp(state, encoder, old_crtc_state, old_conn_state); 535 } 536 537 static void vlv_disable_dp(struct intel_atomic_state *state, 538 struct intel_encoder *encoder, 539 const struct intel_crtc_state *old_crtc_state, 540 const struct drm_connector_state *old_conn_state) 541 { 542 intel_disable_dp(state, encoder, old_crtc_state, old_conn_state); 543 } 544 545 static void g4x_post_disable_dp(struct intel_atomic_state *state, 546 struct intel_encoder *encoder, 547 const struct intel_crtc_state *old_crtc_state, 548 const struct drm_connector_state *old_conn_state) 549 { 550 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 551 enum port port = encoder->port; 552 553 /* 554 * Bspec does not list a specific disable sequence for g4x DP. 555 * Follow the ilk+ sequence (disable pipe before the port) for 556 * g4x DP as it does not suffer from underruns like the normal 557 * g4x modeset sequence (disable pipe after the port). 558 */ 559 intel_dp_link_down(encoder, old_crtc_state); 560 561 /* Only ilk+ has port A */ 562 if (port == PORT_A) 563 ilk_edp_pll_off(intel_dp, old_crtc_state); 564 } 565 566 static void vlv_post_disable_dp(struct intel_atomic_state *state, 567 struct intel_encoder *encoder, 568 const struct intel_crtc_state *old_crtc_state, 569 const struct drm_connector_state *old_conn_state) 570 { 571 intel_dp_link_down(encoder, old_crtc_state); 572 } 573 574 static void chv_post_disable_dp(struct intel_atomic_state *state, 575 struct intel_encoder *encoder, 576 const struct intel_crtc_state *old_crtc_state, 577 const struct drm_connector_state *old_conn_state) 578 { 579 intel_dp_link_down(encoder, old_crtc_state); 580 581 /* Assert data lane reset */ 582 chv_data_lane_soft_reset(encoder, old_crtc_state, true); 583 } 584 585 static void 586 cpt_set_link_train(struct intel_dp *intel_dp, 587 const struct intel_crtc_state *crtc_state, 588 u8 dp_train_pat) 589 { 590 struct intel_display *display = to_intel_display(intel_dp); 591 592 intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT; 593 594 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 595 case DP_TRAINING_PATTERN_DISABLE: 596 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 597 break; 598 case DP_TRAINING_PATTERN_1: 599 intel_dp->DP |= DP_LINK_TRAIN_PAT_1_CPT; 600 break; 601 case DP_TRAINING_PATTERN_2: 602 intel_dp->DP |= DP_LINK_TRAIN_PAT_2_CPT; 603 break; 604 default: 605 MISSING_CASE(intel_dp_training_pattern_symbol(dp_train_pat)); 606 return; 607 } 608 609 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); 610 intel_de_posting_read(display, intel_dp->output_reg); 611 } 612 613 static void 614 g4x_set_link_train(struct intel_dp *intel_dp, 615 const struct intel_crtc_state *crtc_state, 616 u8 dp_train_pat) 617 { 618 struct intel_display *display = to_intel_display(intel_dp); 619 620 intel_dp->DP &= ~DP_LINK_TRAIN_MASK; 621 622 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 623 case DP_TRAINING_PATTERN_DISABLE: 624 intel_dp->DP |= DP_LINK_TRAIN_OFF; 625 break; 626 case DP_TRAINING_PATTERN_1: 627 intel_dp->DP |= DP_LINK_TRAIN_PAT_1; 628 break; 629 case DP_TRAINING_PATTERN_2: 630 intel_dp->DP |= DP_LINK_TRAIN_PAT_2; 631 break; 632 default: 633 MISSING_CASE(intel_dp_training_pattern_symbol(dp_train_pat)); 634 return; 635 } 636 637 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); 638 intel_de_posting_read(display, intel_dp->output_reg); 639 } 640 641 static void intel_dp_enable_port(struct intel_dp *intel_dp, 642 const struct intel_crtc_state *crtc_state) 643 { 644 struct intel_display *display = to_intel_display(intel_dp); 645 646 /* enable with pattern 1 (as per spec) */ 647 648 intel_dp_program_link_training_pattern(intel_dp, crtc_state, 649 DP_PHY_DPRX, DP_TRAINING_PATTERN_1); 650 651 /* 652 * Magic for VLV/CHV. We _must_ first set up the register 653 * without actually enabling the port, and then do another 654 * write to enable the port. Otherwise link training will 655 * fail when the power sequencer is freshly used for this port. 656 */ 657 intel_dp->DP |= DP_PORT_EN; 658 659 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); 660 intel_de_posting_read(display, intel_dp->output_reg); 661 } 662 663 static void intel_enable_dp(struct intel_atomic_state *state, 664 struct intel_encoder *encoder, 665 const struct intel_crtc_state *pipe_config, 666 const struct drm_connector_state *conn_state) 667 { 668 struct intel_display *display = to_intel_display(state); 669 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 670 u32 dp_reg = intel_de_read(display, intel_dp->output_reg); 671 intel_wakeref_t wakeref; 672 673 if (drm_WARN_ON(display->drm, dp_reg & DP_PORT_EN)) 674 return; 675 676 with_intel_pps_lock(intel_dp, wakeref) { 677 if (display->platform.valleyview || display->platform.cherryview) 678 vlv_pps_port_enable_unlocked(encoder, pipe_config); 679 680 intel_dp_enable_port(intel_dp, pipe_config); 681 682 intel_pps_vdd_on_unlocked(intel_dp); 683 intel_pps_on_unlocked(intel_dp); 684 intel_pps_vdd_off_unlocked(intel_dp, true); 685 } 686 687 if (display->platform.valleyview || display->platform.cherryview) { 688 unsigned int lane_mask = 0x0; 689 690 if (display->platform.cherryview) 691 lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count); 692 693 vlv_wait_port_ready(encoder, lane_mask); 694 } 695 696 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 697 intel_dp_configure_protocol_converter(intel_dp, pipe_config); 698 intel_dp_check_frl_training(intel_dp); 699 intel_dp_pcon_dsc_configure(intel_dp, pipe_config); 700 intel_dp_start_link_train(state, intel_dp, pipe_config); 701 intel_dp_stop_link_train(intel_dp, pipe_config); 702 } 703 704 static void g4x_enable_dp(struct intel_atomic_state *state, 705 struct intel_encoder *encoder, 706 const struct intel_crtc_state *pipe_config, 707 const struct drm_connector_state *conn_state) 708 { 709 intel_enable_dp(state, encoder, pipe_config, conn_state); 710 intel_edp_backlight_on(pipe_config, conn_state); 711 } 712 713 static void vlv_enable_dp(struct intel_atomic_state *state, 714 struct intel_encoder *encoder, 715 const struct intel_crtc_state *pipe_config, 716 const struct drm_connector_state *conn_state) 717 { 718 intel_edp_backlight_on(pipe_config, conn_state); 719 } 720 721 static void g4x_pre_enable_dp(struct intel_atomic_state *state, 722 struct intel_encoder *encoder, 723 const struct intel_crtc_state *pipe_config, 724 const struct drm_connector_state *conn_state) 725 { 726 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 727 enum port port = encoder->port; 728 729 intel_dp_prepare(encoder, pipe_config); 730 731 /* Only ilk+ has port A */ 732 if (port == PORT_A) 733 ilk_edp_pll_on(intel_dp, pipe_config); 734 } 735 736 static void vlv_pre_enable_dp(struct intel_atomic_state *state, 737 struct intel_encoder *encoder, 738 const struct intel_crtc_state *pipe_config, 739 const struct drm_connector_state *conn_state) 740 { 741 vlv_phy_pre_encoder_enable(encoder, pipe_config); 742 743 intel_enable_dp(state, encoder, pipe_config, conn_state); 744 } 745 746 static void vlv_dp_pre_pll_enable(struct intel_atomic_state *state, 747 struct intel_encoder *encoder, 748 const struct intel_crtc_state *pipe_config, 749 const struct drm_connector_state *conn_state) 750 { 751 intel_dp_prepare(encoder, pipe_config); 752 753 vlv_phy_pre_pll_enable(encoder, pipe_config); 754 } 755 756 static void chv_pre_enable_dp(struct intel_atomic_state *state, 757 struct intel_encoder *encoder, 758 const struct intel_crtc_state *pipe_config, 759 const struct drm_connector_state *conn_state) 760 { 761 chv_phy_pre_encoder_enable(encoder, pipe_config); 762 763 intel_enable_dp(state, encoder, pipe_config, conn_state); 764 765 /* Second common lane will stay alive on its own now */ 766 chv_phy_release_cl2_override(encoder); 767 } 768 769 static void chv_dp_pre_pll_enable(struct intel_atomic_state *state, 770 struct intel_encoder *encoder, 771 const struct intel_crtc_state *pipe_config, 772 const struct drm_connector_state *conn_state) 773 { 774 intel_dp_prepare(encoder, pipe_config); 775 776 chv_phy_pre_pll_enable(encoder, pipe_config); 777 } 778 779 static void chv_dp_post_pll_disable(struct intel_atomic_state *state, 780 struct intel_encoder *encoder, 781 const struct intel_crtc_state *old_crtc_state, 782 const struct drm_connector_state *old_conn_state) 783 { 784 chv_phy_post_pll_disable(encoder, old_crtc_state); 785 } 786 787 static u8 intel_dp_voltage_max_2(struct intel_dp *intel_dp, 788 const struct intel_crtc_state *crtc_state) 789 { 790 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 791 } 792 793 static u8 intel_dp_voltage_max_3(struct intel_dp *intel_dp, 794 const struct intel_crtc_state *crtc_state) 795 { 796 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 797 } 798 799 static u8 intel_dp_preemph_max_2(struct intel_dp *intel_dp) 800 { 801 return DP_TRAIN_PRE_EMPH_LEVEL_2; 802 } 803 804 static u8 intel_dp_preemph_max_3(struct intel_dp *intel_dp) 805 { 806 return DP_TRAIN_PRE_EMPH_LEVEL_3; 807 } 808 809 static void vlv_set_signal_levels(struct intel_encoder *encoder, 810 const struct intel_crtc_state *crtc_state) 811 { 812 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 813 unsigned long demph_reg_value, preemph_reg_value, 814 uniqtranscale_reg_value; 815 u8 train_set = intel_dp->train_set[0]; 816 817 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 818 case DP_TRAIN_PRE_EMPH_LEVEL_0: 819 preemph_reg_value = 0x0004000; 820 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 821 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 822 demph_reg_value = 0x2B405555; 823 uniqtranscale_reg_value = 0x552AB83A; 824 break; 825 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 826 demph_reg_value = 0x2B404040; 827 uniqtranscale_reg_value = 0x5548B83A; 828 break; 829 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 830 demph_reg_value = 0x2B245555; 831 uniqtranscale_reg_value = 0x5560B83A; 832 break; 833 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 834 demph_reg_value = 0x2B405555; 835 uniqtranscale_reg_value = 0x5598DA3A; 836 break; 837 default: 838 return; 839 } 840 break; 841 case DP_TRAIN_PRE_EMPH_LEVEL_1: 842 preemph_reg_value = 0x0002000; 843 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 844 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 845 demph_reg_value = 0x2B404040; 846 uniqtranscale_reg_value = 0x5552B83A; 847 break; 848 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 849 demph_reg_value = 0x2B404848; 850 uniqtranscale_reg_value = 0x5580B83A; 851 break; 852 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 853 demph_reg_value = 0x2B404040; 854 uniqtranscale_reg_value = 0x55ADDA3A; 855 break; 856 default: 857 return; 858 } 859 break; 860 case DP_TRAIN_PRE_EMPH_LEVEL_2: 861 preemph_reg_value = 0x0000000; 862 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 863 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 864 demph_reg_value = 0x2B305555; 865 uniqtranscale_reg_value = 0x5570B83A; 866 break; 867 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 868 demph_reg_value = 0x2B2B4040; 869 uniqtranscale_reg_value = 0x55ADDA3A; 870 break; 871 default: 872 return; 873 } 874 break; 875 case DP_TRAIN_PRE_EMPH_LEVEL_3: 876 preemph_reg_value = 0x0006000; 877 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 878 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 879 demph_reg_value = 0x1B405555; 880 uniqtranscale_reg_value = 0x55ADDA3A; 881 break; 882 default: 883 return; 884 } 885 break; 886 default: 887 return; 888 } 889 890 vlv_set_phy_signal_level(encoder, crtc_state, 891 demph_reg_value, preemph_reg_value, 892 uniqtranscale_reg_value, 0); 893 } 894 895 static void chv_set_signal_levels(struct intel_encoder *encoder, 896 const struct intel_crtc_state *crtc_state) 897 { 898 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 899 u32 deemph_reg_value, margin_reg_value; 900 bool uniq_trans_scale = false; 901 u8 train_set = intel_dp->train_set[0]; 902 903 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 904 case DP_TRAIN_PRE_EMPH_LEVEL_0: 905 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 906 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 907 deemph_reg_value = 128; 908 margin_reg_value = 52; 909 break; 910 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 911 deemph_reg_value = 128; 912 margin_reg_value = 77; 913 break; 914 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 915 deemph_reg_value = 128; 916 margin_reg_value = 102; 917 break; 918 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 919 deemph_reg_value = 128; 920 margin_reg_value = 154; 921 uniq_trans_scale = true; 922 break; 923 default: 924 return; 925 } 926 break; 927 case DP_TRAIN_PRE_EMPH_LEVEL_1: 928 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 929 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 930 deemph_reg_value = 85; 931 margin_reg_value = 78; 932 break; 933 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 934 deemph_reg_value = 85; 935 margin_reg_value = 116; 936 break; 937 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 938 deemph_reg_value = 85; 939 margin_reg_value = 154; 940 break; 941 default: 942 return; 943 } 944 break; 945 case DP_TRAIN_PRE_EMPH_LEVEL_2: 946 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 947 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 948 deemph_reg_value = 64; 949 margin_reg_value = 104; 950 break; 951 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 952 deemph_reg_value = 64; 953 margin_reg_value = 154; 954 break; 955 default: 956 return; 957 } 958 break; 959 case DP_TRAIN_PRE_EMPH_LEVEL_3: 960 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 961 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 962 deemph_reg_value = 43; 963 margin_reg_value = 154; 964 break; 965 default: 966 return; 967 } 968 break; 969 default: 970 return; 971 } 972 973 chv_set_phy_signal_level(encoder, crtc_state, 974 deemph_reg_value, margin_reg_value, 975 uniq_trans_scale); 976 } 977 978 static u32 g4x_signal_levels(u8 train_set) 979 { 980 u32 signal_levels = 0; 981 982 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 983 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 984 default: 985 signal_levels |= DP_VOLTAGE_0_4; 986 break; 987 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 988 signal_levels |= DP_VOLTAGE_0_6; 989 break; 990 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 991 signal_levels |= DP_VOLTAGE_0_8; 992 break; 993 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 994 signal_levels |= DP_VOLTAGE_1_2; 995 break; 996 } 997 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 998 case DP_TRAIN_PRE_EMPH_LEVEL_0: 999 default: 1000 signal_levels |= DP_PRE_EMPHASIS_0; 1001 break; 1002 case DP_TRAIN_PRE_EMPH_LEVEL_1: 1003 signal_levels |= DP_PRE_EMPHASIS_3_5; 1004 break; 1005 case DP_TRAIN_PRE_EMPH_LEVEL_2: 1006 signal_levels |= DP_PRE_EMPHASIS_6; 1007 break; 1008 case DP_TRAIN_PRE_EMPH_LEVEL_3: 1009 signal_levels |= DP_PRE_EMPHASIS_9_5; 1010 break; 1011 } 1012 return signal_levels; 1013 } 1014 1015 static void 1016 g4x_set_signal_levels(struct intel_encoder *encoder, 1017 const struct intel_crtc_state *crtc_state) 1018 { 1019 struct intel_display *display = to_intel_display(encoder); 1020 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1021 u8 train_set = intel_dp->train_set[0]; 1022 u32 signal_levels; 1023 1024 signal_levels = g4x_signal_levels(train_set); 1025 1026 drm_dbg_kms(display->drm, "Using signal levels %08x\n", 1027 signal_levels); 1028 1029 intel_dp->DP &= ~(DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK); 1030 intel_dp->DP |= signal_levels; 1031 1032 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); 1033 intel_de_posting_read(display, intel_dp->output_reg); 1034 } 1035 1036 /* SNB CPU eDP voltage swing and pre-emphasis control */ 1037 static u32 snb_cpu_edp_signal_levels(u8 train_set) 1038 { 1039 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1040 DP_TRAIN_PRE_EMPHASIS_MASK); 1041 1042 switch (signal_levels) { 1043 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1044 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1045 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 1046 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: 1047 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; 1048 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: 1049 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: 1050 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; 1051 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: 1052 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: 1053 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; 1054 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1055 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1056 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; 1057 default: 1058 MISSING_CASE(signal_levels); 1059 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 1060 } 1061 } 1062 1063 static void 1064 snb_cpu_edp_set_signal_levels(struct intel_encoder *encoder, 1065 const struct intel_crtc_state *crtc_state) 1066 { 1067 struct intel_display *display = to_intel_display(encoder); 1068 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1069 u8 train_set = intel_dp->train_set[0]; 1070 u32 signal_levels; 1071 1072 signal_levels = snb_cpu_edp_signal_levels(train_set); 1073 1074 drm_dbg_kms(display->drm, "Using signal levels %08x\n", 1075 signal_levels); 1076 1077 intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; 1078 intel_dp->DP |= signal_levels; 1079 1080 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); 1081 intel_de_posting_read(display, intel_dp->output_reg); 1082 } 1083 1084 /* IVB CPU eDP voltage swing and pre-emphasis control */ 1085 static u32 ivb_cpu_edp_signal_levels(u8 train_set) 1086 { 1087 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1088 DP_TRAIN_PRE_EMPHASIS_MASK); 1089 1090 switch (signal_levels) { 1091 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1092 return EDP_LINK_TRAIN_400MV_0DB_IVB; 1093 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: 1094 return EDP_LINK_TRAIN_400MV_3_5DB_IVB; 1095 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: 1096 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: 1097 return EDP_LINK_TRAIN_400MV_6DB_IVB; 1098 1099 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1100 return EDP_LINK_TRAIN_600MV_0DB_IVB; 1101 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: 1102 return EDP_LINK_TRAIN_600MV_3_5DB_IVB; 1103 1104 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1105 return EDP_LINK_TRAIN_800MV_0DB_IVB; 1106 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: 1107 return EDP_LINK_TRAIN_800MV_3_5DB_IVB; 1108 1109 default: 1110 MISSING_CASE(signal_levels); 1111 return EDP_LINK_TRAIN_500MV_0DB_IVB; 1112 } 1113 } 1114 1115 static void 1116 ivb_cpu_edp_set_signal_levels(struct intel_encoder *encoder, 1117 const struct intel_crtc_state *crtc_state) 1118 { 1119 struct intel_display *display = to_intel_display(encoder); 1120 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1121 u8 train_set = intel_dp->train_set[0]; 1122 u32 signal_levels; 1123 1124 signal_levels = ivb_cpu_edp_signal_levels(train_set); 1125 1126 drm_dbg_kms(display->drm, "Using signal levels %08x\n", 1127 signal_levels); 1128 1129 intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; 1130 intel_dp->DP |= signal_levels; 1131 1132 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); 1133 intel_de_posting_read(display, intel_dp->output_reg); 1134 } 1135 1136 /* 1137 * If display is now connected check links status, 1138 * there has been known issues of link loss triggering 1139 * long pulse. 1140 * 1141 * Some sinks (eg. ASUS PB287Q) seem to perform some 1142 * weird HPD ping pong during modesets. So we can apparently 1143 * end up with HPD going low during a modeset, and then 1144 * going back up soon after. And once that happens we must 1145 * retrain the link to get a picture. That's in case no 1146 * userspace component reacted to intermittent HPD dip. 1147 */ 1148 static enum intel_hotplug_state 1149 intel_dp_hotplug(struct intel_encoder *encoder, 1150 struct intel_connector *connector) 1151 { 1152 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1153 enum intel_hotplug_state state; 1154 1155 if (intel_dp_test_phy(intel_dp)) 1156 return INTEL_HOTPLUG_UNCHANGED; 1157 1158 state = intel_encoder_hotplug(encoder, connector); 1159 1160 intel_dp_check_link_state(intel_dp); 1161 1162 /* 1163 * Keeping it consistent with intel_ddi_hotplug() and 1164 * intel_hdmi_hotplug(). 1165 */ 1166 if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries) 1167 state = INTEL_HOTPLUG_RETRY; 1168 1169 return state; 1170 } 1171 1172 static bool ibx_digital_port_connected(struct intel_encoder *encoder) 1173 { 1174 struct intel_display *display = to_intel_display(encoder); 1175 u32 bit = display->hotplug.pch_hpd[encoder->hpd_pin]; 1176 1177 return intel_de_read(display, SDEISR) & bit; 1178 } 1179 1180 static bool g4x_digital_port_connected(struct intel_encoder *encoder) 1181 { 1182 struct intel_display *display = to_intel_display(encoder); 1183 u32 bit; 1184 1185 switch (encoder->hpd_pin) { 1186 case HPD_PORT_B: 1187 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; 1188 break; 1189 case HPD_PORT_C: 1190 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; 1191 break; 1192 case HPD_PORT_D: 1193 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; 1194 break; 1195 default: 1196 MISSING_CASE(encoder->hpd_pin); 1197 return false; 1198 } 1199 1200 return intel_de_read(display, PORT_HOTPLUG_STAT(display)) & bit; 1201 } 1202 1203 static bool ilk_digital_port_connected(struct intel_encoder *encoder) 1204 { 1205 struct intel_display *display = to_intel_display(encoder); 1206 u32 bit = display->hotplug.hpd[encoder->hpd_pin]; 1207 1208 return intel_de_read(display, DEISR) & bit; 1209 } 1210 1211 static int g4x_dp_compute_config(struct intel_encoder *encoder, 1212 struct intel_crtc_state *crtc_state, 1213 struct drm_connector_state *conn_state) 1214 { 1215 struct intel_display *display = to_intel_display(encoder); 1216 int ret; 1217 1218 if (HAS_PCH_SPLIT(display) && encoder->port != PORT_A) 1219 crtc_state->has_pch_encoder = true; 1220 1221 ret = intel_dp_compute_config(encoder, crtc_state, conn_state); 1222 if (ret) 1223 return ret; 1224 1225 g4x_dp_set_clock(encoder, crtc_state); 1226 1227 return 0; 1228 } 1229 1230 static void g4x_dp_suspend_complete(struct intel_encoder *encoder) 1231 { 1232 /* 1233 * TODO: Move this to intel_dp_encoder_suspend(), 1234 * once modeset locking around that is removed. 1235 */ 1236 intel_encoder_link_check_flush_work(encoder); 1237 } 1238 1239 static void intel_dp_encoder_destroy(struct drm_encoder *encoder) 1240 { 1241 intel_dp_encoder_flush_work(encoder); 1242 1243 drm_encoder_cleanup(encoder); 1244 kfree(enc_to_dig_port(to_intel_encoder(encoder))); 1245 } 1246 1247 static void intel_dp_encoder_reset(struct drm_encoder *encoder) 1248 { 1249 struct intel_display *display = to_intel_display(encoder->dev); 1250 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 1251 1252 intel_dp->DP = intel_de_read(display, intel_dp->output_reg); 1253 1254 intel_dp->reset_link_params = true; 1255 intel_dp_invalidate_source_oui(intel_dp); 1256 1257 if (display->platform.valleyview || display->platform.cherryview) 1258 vlv_pps_pipe_reset(intel_dp); 1259 1260 intel_pps_encoder_reset(intel_dp); 1261 } 1262 1263 static const struct drm_encoder_funcs intel_dp_enc_funcs = { 1264 .reset = intel_dp_encoder_reset, 1265 .destroy = intel_dp_encoder_destroy, 1266 }; 1267 1268 bool g4x_dp_init(struct intel_display *display, 1269 i915_reg_t output_reg, enum port port) 1270 { 1271 const struct intel_bios_encoder_data *devdata; 1272 struct intel_digital_port *dig_port; 1273 struct intel_encoder *intel_encoder; 1274 struct drm_encoder *encoder; 1275 struct intel_connector *intel_connector; 1276 1277 if (!assert_port_valid(display, port)) 1278 return false; 1279 1280 devdata = intel_bios_encoder_data_lookup(display, port); 1281 1282 /* FIXME bail? */ 1283 if (!devdata) 1284 drm_dbg_kms(display->drm, "No VBT child device for DP-%c\n", 1285 port_name(port)); 1286 1287 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 1288 if (!dig_port) 1289 return false; 1290 1291 dig_port->aux_ch = AUX_CH_NONE; 1292 1293 intel_connector = intel_connector_alloc(); 1294 if (!intel_connector) 1295 goto err_connector_alloc; 1296 1297 intel_encoder = &dig_port->base; 1298 encoder = &intel_encoder->base; 1299 1300 intel_encoder->devdata = devdata; 1301 1302 mutex_init(&dig_port->hdcp.mutex); 1303 1304 if (drm_encoder_init(display->drm, &intel_encoder->base, 1305 &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS, 1306 "DP %c", port_name(port))) 1307 goto err_encoder_init; 1308 1309 intel_encoder_link_check_init(intel_encoder, intel_dp_link_check); 1310 1311 intel_encoder->hotplug = intel_dp_hotplug; 1312 intel_encoder->compute_config = g4x_dp_compute_config; 1313 intel_encoder->get_hw_state = intel_dp_get_hw_state; 1314 intel_encoder->get_config = intel_dp_get_config; 1315 intel_encoder->sync_state = intel_dp_sync_state; 1316 intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check; 1317 intel_encoder->update_pipe = intel_backlight_update; 1318 intel_encoder->suspend = intel_dp_encoder_suspend; 1319 intel_encoder->suspend_complete = g4x_dp_suspend_complete; 1320 intel_encoder->shutdown = intel_dp_encoder_shutdown; 1321 if (display->platform.cherryview) { 1322 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; 1323 intel_encoder->pre_enable = chv_pre_enable_dp; 1324 intel_encoder->enable = vlv_enable_dp; 1325 intel_encoder->disable = vlv_disable_dp; 1326 intel_encoder->post_disable = chv_post_disable_dp; 1327 intel_encoder->post_pll_disable = chv_dp_post_pll_disable; 1328 } else if (display->platform.valleyview) { 1329 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; 1330 intel_encoder->pre_enable = vlv_pre_enable_dp; 1331 intel_encoder->enable = vlv_enable_dp; 1332 intel_encoder->disable = vlv_disable_dp; 1333 intel_encoder->post_disable = vlv_post_disable_dp; 1334 } else { 1335 intel_encoder->pre_enable = g4x_pre_enable_dp; 1336 intel_encoder->enable = g4x_enable_dp; 1337 intel_encoder->disable = g4x_disable_dp; 1338 intel_encoder->post_disable = g4x_post_disable_dp; 1339 } 1340 intel_encoder->audio_enable = g4x_dp_audio_enable; 1341 intel_encoder->audio_disable = g4x_dp_audio_disable; 1342 1343 if ((display->platform.ivybridge && port == PORT_A) || 1344 (HAS_PCH_CPT(display) && port != PORT_A)) 1345 dig_port->dp.set_link_train = cpt_set_link_train; 1346 else 1347 dig_port->dp.set_link_train = g4x_set_link_train; 1348 1349 if (display->platform.cherryview) 1350 intel_encoder->set_signal_levels = chv_set_signal_levels; 1351 else if (display->platform.valleyview) 1352 intel_encoder->set_signal_levels = vlv_set_signal_levels; 1353 else if (display->platform.ivybridge && port == PORT_A) 1354 intel_encoder->set_signal_levels = ivb_cpu_edp_set_signal_levels; 1355 else if (display->platform.sandybridge && port == PORT_A) 1356 intel_encoder->set_signal_levels = snb_cpu_edp_set_signal_levels; 1357 else 1358 intel_encoder->set_signal_levels = g4x_set_signal_levels; 1359 1360 if (display->platform.valleyview || display->platform.cherryview || 1361 (HAS_PCH_SPLIT(display) && port != PORT_A)) { 1362 dig_port->dp.preemph_max = intel_dp_preemph_max_3; 1363 dig_port->dp.voltage_max = intel_dp_voltage_max_3; 1364 } else { 1365 dig_port->dp.preemph_max = intel_dp_preemph_max_2; 1366 dig_port->dp.voltage_max = intel_dp_voltage_max_2; 1367 } 1368 1369 dig_port->dp.output_reg = output_reg; 1370 dig_port->max_lanes = 4; 1371 1372 intel_encoder->type = INTEL_OUTPUT_DP; 1373 intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port); 1374 if (display->platform.cherryview) { 1375 if (port == PORT_D) 1376 intel_encoder->pipe_mask = BIT(PIPE_C); 1377 else 1378 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); 1379 } else { 1380 intel_encoder->pipe_mask = ~0; 1381 } 1382 intel_encoder->cloneable = 0; 1383 intel_encoder->port = port; 1384 intel_encoder->hpd_pin = intel_hpd_pin_default(port); 1385 1386 dig_port->hpd_pulse = intel_dp_hpd_pulse; 1387 1388 if (HAS_GMCH(display)) { 1389 dig_port->connected = g4x_digital_port_connected; 1390 } else { 1391 if (port == PORT_A) 1392 dig_port->connected = ilk_digital_port_connected; 1393 else 1394 dig_port->connected = ibx_digital_port_connected; 1395 } 1396 1397 if (port != PORT_A) 1398 intel_infoframe_init(dig_port); 1399 1400 dig_port->aux_ch = intel_dp_aux_ch(intel_encoder); 1401 if (dig_port->aux_ch == AUX_CH_NONE) 1402 goto err_init_connector; 1403 1404 if (!intel_dp_init_connector(dig_port, intel_connector)) 1405 goto err_init_connector; 1406 1407 return true; 1408 1409 err_init_connector: 1410 drm_encoder_cleanup(encoder); 1411 err_encoder_init: 1412 kfree(intel_connector); 1413 err_connector_alloc: 1414 kfree(dig_port); 1415 return false; 1416 } 1417