1 /* 2 * Copyright © 2006 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Thomas Richter <thor@math.tu-berlin.de> 26 * 27 * Minor modifications (Dithering enable): 28 * Thomas Richter <thor@math.tu-berlin.de> 29 * 30 */ 31 32 #include <drm/drm_print.h> 33 34 #include "intel_display_types.h" 35 #include "intel_dvo_dev.h" 36 37 /* 38 * register definitions for the i82807aa. 39 * 40 * Documentation on this chipset can be found in datasheet #29069001 at 41 * intel.com. 42 */ 43 44 /* 45 * VCH Revision & GMBus Base Addr 46 */ 47 #define VR00 0x00 48 # define VR00_BASE_ADDRESS_MASK 0x007f 49 50 /* 51 * Functionality Enable 52 */ 53 #define VR01 0x01 54 55 /* 56 * Enable the panel fitter 57 */ 58 # define VR01_PANEL_FIT_ENABLE (1 << 3) 59 /* 60 * Enables the LCD display. 61 * 62 * This must not be set while VR01_DVO_BYPASS_ENABLE is set. 63 */ 64 # define VR01_LCD_ENABLE (1 << 2) 65 /* Enables the DVO repeater. */ 66 # define VR01_DVO_BYPASS_ENABLE (1 << 1) 67 /* Enables the DVO clock */ 68 # define VR01_DVO_ENABLE (1 << 0) 69 /* Enable dithering for 18bpp panels. Not documented. */ 70 # define VR01_DITHER_ENABLE (1 << 4) 71 72 /* 73 * LCD Interface Format 74 */ 75 #define VR10 0x10 76 /* Enables LVDS output instead of CMOS */ 77 # define VR10_LVDS_ENABLE (1 << 4) 78 /* Enables 18-bit LVDS output. */ 79 # define VR10_INTERFACE_1X18 (0 << 2) 80 /* Enables 24-bit LVDS or CMOS output */ 81 # define VR10_INTERFACE_1X24 (1 << 2) 82 /* Enables 2x18-bit LVDS or CMOS output. */ 83 # define VR10_INTERFACE_2X18 (2 << 2) 84 /* Enables 2x24-bit LVDS output */ 85 # define VR10_INTERFACE_2X24 (3 << 2) 86 /* Mask that defines the depth of the pipeline */ 87 # define VR10_INTERFACE_DEPTH_MASK (3 << 2) 88 89 /* 90 * VR20 LCD Horizontal Display Size 91 */ 92 #define VR20 0x20 93 94 /* 95 * LCD Vertical Display Size 96 */ 97 #define VR21 0x21 98 99 /* 100 * Panel power down status 101 */ 102 #define VR30 0x30 103 /* Read only bit indicating that the panel is not in a safe poweroff state. */ 104 # define VR30_PANEL_ON (1 << 15) 105 106 #define VR40 0x40 107 # define VR40_STALL_ENABLE (1 << 13) 108 # define VR40_VERTICAL_INTERP_ENABLE (1 << 12) 109 # define VR40_ENHANCED_PANEL_FITTING (1 << 11) 110 # define VR40_HORIZONTAL_INTERP_ENABLE (1 << 10) 111 # define VR40_AUTO_RATIO_ENABLE (1 << 9) 112 # define VR40_CLOCK_GATING_ENABLE (1 << 8) 113 114 /* 115 * Panel Fitting Vertical Ratio 116 * (((image_height - 1) << 16) / ((panel_height - 1))) >> 2 117 */ 118 #define VR41 0x41 119 120 /* 121 * Panel Fitting Horizontal Ratio 122 * (((image_width - 1) << 16) / ((panel_width - 1))) >> 2 123 */ 124 #define VR42 0x42 125 126 /* 127 * Horizontal Image Size 128 */ 129 #define VR43 0x43 130 131 /* VR80 GPIO 0 132 */ 133 #define VR80 0x80 134 #define VR81 0x81 135 #define VR82 0x82 136 #define VR83 0x83 137 #define VR84 0x84 138 #define VR85 0x85 139 #define VR86 0x86 140 #define VR87 0x87 141 142 /* VR88 GPIO 8 143 */ 144 #define VR88 0x88 145 146 /* Graphics BIOS scratch 0 147 */ 148 #define VR8E 0x8E 149 # define VR8E_PANEL_TYPE_MASK (0xf << 0) 150 # define VR8E_PANEL_INTERFACE_CMOS (0 << 4) 151 # define VR8E_PANEL_INTERFACE_LVDS (1 << 4) 152 # define VR8E_FORCE_DEFAULT_PANEL (1 << 5) 153 154 /* Graphics BIOS scratch 1 155 */ 156 #define VR8F 0x8F 157 # define VR8F_VCH_PRESENT (1 << 0) 158 # define VR8F_DISPLAY_CONN (1 << 1) 159 # define VR8F_POWER_MASK (0x3c) 160 # define VR8F_POWER_POS (2) 161 162 /* Some Bios implementations do not restore the DVO state upon 163 * resume from standby. Thus, this driver has to handle it 164 * instead. The following list contains all registers that 165 * require saving. 166 */ 167 static const u16 backup_addresses[] = { 168 0x11, 0x12, 169 0x18, 0x19, 0x1a, 0x1f, 170 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 171 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 172 0x8e, 0x8f, 173 0x10 /* this must come last */ 174 }; 175 176 177 struct ivch_priv { 178 bool quiet; 179 180 u16 width, height; 181 182 /* Register backup */ 183 184 u16 reg_backup[ARRAY_SIZE(backup_addresses)]; 185 }; 186 187 188 static void ivch_dump_regs(struct intel_dvo_device *dvo); 189 /* 190 * Reads a register on the ivch. 191 * 192 * Each of the 256 registers are 16 bits long. 193 */ 194 static bool ivch_read(struct intel_dvo_device *dvo, int addr, u16 *data) 195 { 196 struct ivch_priv *priv = dvo->dev_priv; 197 struct i2c_adapter *adapter = dvo->i2c_bus; 198 u8 out_buf[1]; 199 u8 in_buf[2]; 200 201 struct i2c_msg msgs[] = { 202 { 203 .addr = dvo->target_addr, 204 .flags = I2C_M_RD, 205 .len = 0, 206 }, 207 { 208 .addr = 0, 209 .flags = I2C_M_NOSTART, 210 .len = 1, 211 .buf = out_buf, 212 }, 213 { 214 .addr = dvo->target_addr, 215 .flags = I2C_M_RD | I2C_M_NOSTART, 216 .len = 2, 217 .buf = in_buf, 218 } 219 }; 220 221 out_buf[0] = addr; 222 223 if (i2c_transfer(adapter, msgs, 3) == 3) { 224 *data = (in_buf[1] << 8) | in_buf[0]; 225 return true; 226 } 227 228 if (!priv->quiet) { 229 DRM_DEBUG_KMS("Unable to read register 0x%02x from " 230 "%s:%02x.\n", 231 addr, adapter->name, dvo->target_addr); 232 } 233 return false; 234 } 235 236 /* Writes a 16-bit register on the ivch */ 237 static bool ivch_write(struct intel_dvo_device *dvo, int addr, u16 data) 238 { 239 struct ivch_priv *priv = dvo->dev_priv; 240 struct i2c_adapter *adapter = dvo->i2c_bus; 241 u8 out_buf[3]; 242 struct i2c_msg msg = { 243 .addr = dvo->target_addr, 244 .flags = 0, 245 .len = 3, 246 .buf = out_buf, 247 }; 248 249 out_buf[0] = addr; 250 out_buf[1] = data & 0xff; 251 out_buf[2] = data >> 8; 252 253 if (i2c_transfer(adapter, &msg, 1) == 1) 254 return true; 255 256 if (!priv->quiet) { 257 DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n", 258 addr, adapter->name, dvo->target_addr); 259 } 260 261 return false; 262 } 263 264 /* Probes the given bus and target address for an ivch */ 265 static bool ivch_init(struct intel_dvo_device *dvo, 266 struct i2c_adapter *adapter) 267 { 268 struct ivch_priv *priv; 269 u16 temp; 270 int i; 271 272 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 273 if (priv == NULL) 274 return false; 275 276 dvo->i2c_bus = adapter; 277 dvo->dev_priv = priv; 278 priv->quiet = true; 279 280 if (!ivch_read(dvo, VR00, &temp)) 281 goto out; 282 priv->quiet = false; 283 284 /* Since the identification bits are probably zeroes, which doesn't seem 285 * very unique, check that the value in the base address field matches 286 * the address it's responding on. 287 */ 288 if ((temp & VR00_BASE_ADDRESS_MASK) != dvo->target_addr) { 289 DRM_DEBUG_KMS("ivch detect failed due to address mismatch " 290 "(%d vs %d)\n", 291 (temp & VR00_BASE_ADDRESS_MASK), dvo->target_addr); 292 goto out; 293 } 294 295 ivch_read(dvo, VR20, &priv->width); 296 ivch_read(dvo, VR21, &priv->height); 297 298 /* Make a backup of the registers to be able to restore them 299 * upon suspend. 300 */ 301 for (i = 0; i < ARRAY_SIZE(backup_addresses); i++) 302 ivch_read(dvo, backup_addresses[i], priv->reg_backup + i); 303 304 ivch_dump_regs(dvo); 305 306 return true; 307 308 out: 309 kfree(priv); 310 return false; 311 } 312 313 static enum drm_connector_status ivch_detect(struct intel_dvo_device *dvo) 314 { 315 return connector_status_connected; 316 } 317 318 static enum drm_mode_status ivch_mode_valid(struct intel_dvo_device *dvo, 319 const struct drm_display_mode *mode) 320 { 321 if (mode->clock > 112000) 322 return MODE_CLOCK_HIGH; 323 324 return MODE_OK; 325 } 326 327 /* Restore the DVO registers after a resume 328 * from RAM. Registers have been saved during 329 * the initialization. 330 */ 331 static void ivch_reset(struct intel_dvo_device *dvo) 332 { 333 struct ivch_priv *priv = dvo->dev_priv; 334 int i; 335 336 DRM_DEBUG_KMS("Resetting the IVCH registers\n"); 337 338 ivch_write(dvo, VR10, 0x0000); 339 340 for (i = 0; i < ARRAY_SIZE(backup_addresses); i++) 341 ivch_write(dvo, backup_addresses[i], priv->reg_backup[i]); 342 } 343 344 /* Sets the power state of the panel connected to the ivch */ 345 static void ivch_dpms(struct intel_dvo_device *dvo, bool enable) 346 { 347 int i; 348 u16 vr01, vr30, backlight; 349 350 ivch_reset(dvo); 351 352 /* Set the new power state of the panel. */ 353 if (!ivch_read(dvo, VR01, &vr01)) 354 return; 355 356 if (enable) 357 backlight = 1; 358 else 359 backlight = 0; 360 361 ivch_write(dvo, VR80, backlight); 362 363 if (enable) 364 vr01 |= VR01_LCD_ENABLE | VR01_DVO_ENABLE; 365 else 366 vr01 &= ~(VR01_LCD_ENABLE | VR01_DVO_ENABLE); 367 368 ivch_write(dvo, VR01, vr01); 369 370 /* Wait for the panel to make its state transition */ 371 for (i = 0; i < 100; i++) { 372 if (!ivch_read(dvo, VR30, &vr30)) 373 break; 374 375 if (((vr30 & VR30_PANEL_ON) != 0) == enable) 376 break; 377 udelay(1000); 378 } 379 /* wait some more; vch may fail to resync sometimes without this */ 380 udelay(16 * 1000); 381 } 382 383 static bool ivch_get_hw_state(struct intel_dvo_device *dvo) 384 { 385 u16 vr01; 386 387 ivch_reset(dvo); 388 389 /* Set the new power state of the panel. */ 390 if (!ivch_read(dvo, VR01, &vr01)) 391 return false; 392 393 if (vr01 & VR01_LCD_ENABLE) 394 return true; 395 else 396 return false; 397 } 398 399 static void ivch_mode_set(struct intel_dvo_device *dvo, 400 const struct drm_display_mode *mode, 401 const struct drm_display_mode *adjusted_mode) 402 { 403 struct ivch_priv *priv = dvo->dev_priv; 404 u16 vr40 = 0; 405 u16 vr01 = 0; 406 u16 vr10; 407 408 ivch_reset(dvo); 409 410 vr10 = priv->reg_backup[ARRAY_SIZE(backup_addresses) - 1]; 411 412 /* Enable dithering for 18 bpp pipelines */ 413 vr10 &= VR10_INTERFACE_DEPTH_MASK; 414 if (vr10 == VR10_INTERFACE_2X18 || vr10 == VR10_INTERFACE_1X18) 415 vr01 = VR01_DITHER_ENABLE; 416 417 vr40 = (VR40_STALL_ENABLE | VR40_VERTICAL_INTERP_ENABLE | 418 VR40_HORIZONTAL_INTERP_ENABLE); 419 420 if (mode->hdisplay != adjusted_mode->crtc_hdisplay || 421 mode->vdisplay != adjusted_mode->crtc_vdisplay) { 422 u16 x_ratio, y_ratio; 423 424 vr01 |= VR01_PANEL_FIT_ENABLE; 425 vr40 |= VR40_CLOCK_GATING_ENABLE; 426 x_ratio = (((mode->hdisplay - 1) << 16) / 427 (adjusted_mode->crtc_hdisplay - 1)) >> 2; 428 y_ratio = (((mode->vdisplay - 1) << 16) / 429 (adjusted_mode->crtc_vdisplay - 1)) >> 2; 430 ivch_write(dvo, VR42, x_ratio); 431 ivch_write(dvo, VR41, y_ratio); 432 } else { 433 vr01 &= ~VR01_PANEL_FIT_ENABLE; 434 vr40 &= ~VR40_CLOCK_GATING_ENABLE; 435 } 436 vr40 &= ~VR40_AUTO_RATIO_ENABLE; 437 438 ivch_write(dvo, VR01, vr01); 439 ivch_write(dvo, VR40, vr40); 440 } 441 442 static void ivch_dump_regs(struct intel_dvo_device *dvo) 443 { 444 u16 val; 445 446 ivch_read(dvo, VR00, &val); 447 DRM_DEBUG_KMS("VR00: 0x%04x\n", val); 448 ivch_read(dvo, VR01, &val); 449 DRM_DEBUG_KMS("VR01: 0x%04x\n", val); 450 ivch_read(dvo, VR10, &val); 451 DRM_DEBUG_KMS("VR10: 0x%04x\n", val); 452 ivch_read(dvo, VR30, &val); 453 DRM_DEBUG_KMS("VR30: 0x%04x\n", val); 454 ivch_read(dvo, VR40, &val); 455 DRM_DEBUG_KMS("VR40: 0x%04x\n", val); 456 457 /* GPIO registers */ 458 ivch_read(dvo, VR80, &val); 459 DRM_DEBUG_KMS("VR80: 0x%04x\n", val); 460 ivch_read(dvo, VR81, &val); 461 DRM_DEBUG_KMS("VR81: 0x%04x\n", val); 462 ivch_read(dvo, VR82, &val); 463 DRM_DEBUG_KMS("VR82: 0x%04x\n", val); 464 ivch_read(dvo, VR83, &val); 465 DRM_DEBUG_KMS("VR83: 0x%04x\n", val); 466 ivch_read(dvo, VR84, &val); 467 DRM_DEBUG_KMS("VR84: 0x%04x\n", val); 468 ivch_read(dvo, VR85, &val); 469 DRM_DEBUG_KMS("VR85: 0x%04x\n", val); 470 ivch_read(dvo, VR86, &val); 471 DRM_DEBUG_KMS("VR86: 0x%04x\n", val); 472 ivch_read(dvo, VR87, &val); 473 DRM_DEBUG_KMS("VR87: 0x%04x\n", val); 474 ivch_read(dvo, VR88, &val); 475 DRM_DEBUG_KMS("VR88: 0x%04x\n", val); 476 477 /* Scratch register 0 - AIM Panel type */ 478 ivch_read(dvo, VR8E, &val); 479 DRM_DEBUG_KMS("VR8E: 0x%04x\n", val); 480 481 /* Scratch register 1 - Status register */ 482 ivch_read(dvo, VR8F, &val); 483 DRM_DEBUG_KMS("VR8F: 0x%04x\n", val); 484 } 485 486 static void ivch_destroy(struct intel_dvo_device *dvo) 487 { 488 struct ivch_priv *priv = dvo->dev_priv; 489 490 if (priv) { 491 kfree(priv); 492 dvo->dev_priv = NULL; 493 } 494 } 495 496 const struct intel_dvo_dev_ops ivch_ops = { 497 .init = ivch_init, 498 .dpms = ivch_dpms, 499 .get_hw_state = ivch_get_hw_state, 500 .mode_valid = ivch_mode_valid, 501 .mode_set = ivch_mode_set, 502 .detect = ivch_detect, 503 .dump_regs = ivch_dump_regs, 504 .destroy = ivch_destroy, 505 }; 506