1 /* 2 * Copyright (C) 2012 Texas Instruments 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 19 20 #include <linux/module.h> 21 22 #include <drm/drmP.h> 23 #include <drm/drm_crtc_helper.h> 24 #include <drm/drm_encoder_slave.h> 25 #include <drm/drm_edid.h> 26 #include <drm/i2c/tda998x.h> 27 28 #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) 29 30 struct tda998x_priv { 31 struct i2c_client *cec; 32 uint16_t rev; 33 uint8_t current_page; 34 int dpms; 35 bool is_hdmi_sink; 36 u8 vip_cntrl_0; 37 u8 vip_cntrl_1; 38 u8 vip_cntrl_2; 39 struct tda998x_encoder_params params; 40 }; 41 42 #define to_tda998x_priv(x) ((struct tda998x_priv *)to_encoder_slave(x)->slave_priv) 43 44 /* The TDA9988 series of devices use a paged register scheme.. to simplify 45 * things we encode the page # in upper bits of the register #. To read/ 46 * write a given register, we need to make sure CURPAGE register is set 47 * appropriately. Which implies reads/writes are not atomic. Fun! 48 */ 49 50 #define REG(page, addr) (((page) << 8) | (addr)) 51 #define REG2ADDR(reg) ((reg) & 0xff) 52 #define REG2PAGE(reg) (((reg) >> 8) & 0xff) 53 54 #define REG_CURPAGE 0xff /* write */ 55 56 57 /* Page 00h: General Control */ 58 #define REG_VERSION_LSB REG(0x00, 0x00) /* read */ 59 #define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */ 60 # define MAIN_CNTRL0_SR (1 << 0) 61 # define MAIN_CNTRL0_DECS (1 << 1) 62 # define MAIN_CNTRL0_DEHS (1 << 2) 63 # define MAIN_CNTRL0_CECS (1 << 3) 64 # define MAIN_CNTRL0_CEHS (1 << 4) 65 # define MAIN_CNTRL0_SCALER (1 << 7) 66 #define REG_VERSION_MSB REG(0x00, 0x02) /* read */ 67 #define REG_SOFTRESET REG(0x00, 0x0a) /* write */ 68 # define SOFTRESET_AUDIO (1 << 0) 69 # define SOFTRESET_I2C_MASTER (1 << 1) 70 #define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */ 71 #define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */ 72 #define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */ 73 # define I2C_MASTER_DIS_MM (1 << 0) 74 # define I2C_MASTER_DIS_FILT (1 << 1) 75 # define I2C_MASTER_APP_STRT_LAT (1 << 2) 76 #define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */ 77 # define FEAT_POWERDOWN_SPDIF (1 << 3) 78 #define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */ 79 #define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */ 80 #define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */ 81 # define INT_FLAGS_2_EDID_BLK_RD (1 << 1) 82 #define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */ 83 #define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */ 84 #define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */ 85 #define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */ 86 #define REG_ENA_AP REG(0x00, 0x1e) /* read/write */ 87 #define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */ 88 # define VIP_CNTRL_0_MIRR_A (1 << 7) 89 # define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4) 90 # define VIP_CNTRL_0_MIRR_B (1 << 3) 91 # define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0) 92 #define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */ 93 # define VIP_CNTRL_1_MIRR_C (1 << 7) 94 # define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4) 95 # define VIP_CNTRL_1_MIRR_D (1 << 3) 96 # define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0) 97 #define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */ 98 # define VIP_CNTRL_2_MIRR_E (1 << 7) 99 # define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4) 100 # define VIP_CNTRL_2_MIRR_F (1 << 3) 101 # define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0) 102 #define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */ 103 # define VIP_CNTRL_3_X_TGL (1 << 0) 104 # define VIP_CNTRL_3_H_TGL (1 << 1) 105 # define VIP_CNTRL_3_V_TGL (1 << 2) 106 # define VIP_CNTRL_3_EMB (1 << 3) 107 # define VIP_CNTRL_3_SYNC_DE (1 << 4) 108 # define VIP_CNTRL_3_SYNC_HS (1 << 5) 109 # define VIP_CNTRL_3_DE_INT (1 << 6) 110 # define VIP_CNTRL_3_EDGE (1 << 7) 111 #define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */ 112 # define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0) 113 # define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2) 114 # define VIP_CNTRL_4_CCIR656 (1 << 4) 115 # define VIP_CNTRL_4_656_ALT (1 << 5) 116 # define VIP_CNTRL_4_TST_656 (1 << 6) 117 # define VIP_CNTRL_4_TST_PAT (1 << 7) 118 #define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */ 119 # define VIP_CNTRL_5_CKCASE (1 << 0) 120 # define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1) 121 #define REG_MUX_AP REG(0x00, 0x26) /* read/write */ 122 #define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */ 123 #define REG_MAT_CONTRL REG(0x00, 0x80) /* write */ 124 # define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0) 125 # define MAT_CONTRL_MAT_BP (1 << 2) 126 #define REG_VIDFORMAT REG(0x00, 0xa0) /* write */ 127 #define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */ 128 #define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */ 129 #define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */ 130 #define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */ 131 #define REG_NPIX_MSB REG(0x00, 0xa5) /* write */ 132 #define REG_NPIX_LSB REG(0x00, 0xa6) /* write */ 133 #define REG_NLINE_MSB REG(0x00, 0xa7) /* write */ 134 #define REG_NLINE_LSB REG(0x00, 0xa8) /* write */ 135 #define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */ 136 #define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */ 137 #define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */ 138 #define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */ 139 #define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */ 140 #define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */ 141 #define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */ 142 #define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */ 143 #define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */ 144 #define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */ 145 #define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */ 146 #define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */ 147 #define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */ 148 #define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */ 149 #define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */ 150 #define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */ 151 #define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */ 152 #define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */ 153 #define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */ 154 #define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */ 155 #define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */ 156 #define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */ 157 #define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */ 158 #define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */ 159 #define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */ 160 #define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */ 161 #define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */ 162 #define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */ 163 #define REG_DE_START_MSB REG(0x00, 0xc5) /* write */ 164 #define REG_DE_START_LSB REG(0x00, 0xc6) /* write */ 165 #define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */ 166 #define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */ 167 #define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */ 168 # define TBG_CNTRL_0_TOP_TGL (1 << 0) 169 # define TBG_CNTRL_0_TOP_SEL (1 << 1) 170 # define TBG_CNTRL_0_DE_EXT (1 << 2) 171 # define TBG_CNTRL_0_TOP_EXT (1 << 3) 172 # define TBG_CNTRL_0_FRAME_DIS (1 << 5) 173 # define TBG_CNTRL_0_SYNC_MTHD (1 << 6) 174 # define TBG_CNTRL_0_SYNC_ONCE (1 << 7) 175 #define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */ 176 # define TBG_CNTRL_1_H_TGL (1 << 0) 177 # define TBG_CNTRL_1_V_TGL (1 << 1) 178 # define TBG_CNTRL_1_TGL_EN (1 << 2) 179 # define TBG_CNTRL_1_X_EXT (1 << 3) 180 # define TBG_CNTRL_1_H_EXT (1 << 4) 181 # define TBG_CNTRL_1_V_EXT (1 << 5) 182 # define TBG_CNTRL_1_DWIN_DIS (1 << 6) 183 #define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */ 184 #define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */ 185 # define HVF_CNTRL_0_SM (1 << 7) 186 # define HVF_CNTRL_0_RWB (1 << 6) 187 # define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2) 188 # define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0) 189 #define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */ 190 # define HVF_CNTRL_1_FOR (1 << 0) 191 # define HVF_CNTRL_1_YUVBLK (1 << 1) 192 # define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2) 193 # define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4) 194 # define HVF_CNTRL_1_SEMI_PLANAR (1 << 6) 195 #define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */ 196 #define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */ 197 # define I2S_FORMAT(x) (((x) & 3) << 0) 198 #define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */ 199 # define AIP_CLKSEL_FS(x) (((x) & 3) << 0) 200 # define AIP_CLKSEL_CLK_POL(x) (((x) & 1) << 2) 201 # define AIP_CLKSEL_AIP(x) (((x) & 7) << 3) 202 203 204 /* Page 02h: PLL settings */ 205 #define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */ 206 # define PLL_SERIAL_1_SRL_FDN (1 << 0) 207 # define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1) 208 # define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6) 209 #define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */ 210 # define PLL_SERIAL_2_SRL_NOSC(x) (((x) & 3) << 0) 211 # define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4) 212 #define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */ 213 # define PLL_SERIAL_3_SRL_CCIR (1 << 0) 214 # define PLL_SERIAL_3_SRL_DE (1 << 2) 215 # define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4) 216 #define REG_SERIALIZER REG(0x02, 0x03) /* read/write */ 217 #define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */ 218 #define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */ 219 #define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */ 220 #define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */ 221 #define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */ 222 #define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */ 223 #define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */ 224 #define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */ 225 # define AUDIO_DIV_SERCLK_1 0 226 # define AUDIO_DIV_SERCLK_2 1 227 # define AUDIO_DIV_SERCLK_4 2 228 # define AUDIO_DIV_SERCLK_8 3 229 # define AUDIO_DIV_SERCLK_16 4 230 # define AUDIO_DIV_SERCLK_32 5 231 #define REG_SEL_CLK REG(0x02, 0x11) /* read/write */ 232 # define SEL_CLK_SEL_CLK1 (1 << 0) 233 # define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1) 234 # define SEL_CLK_ENA_SC_CLK (1 << 3) 235 #define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */ 236 237 238 /* Page 09h: EDID Control */ 239 #define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */ 240 /* next 127 successive registers are the EDID block */ 241 #define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */ 242 #define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */ 243 #define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */ 244 #define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */ 245 #define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */ 246 247 248 /* Page 10h: information frames and packets */ 249 #define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */ 250 #define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */ 251 #define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */ 252 #define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */ 253 #define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */ 254 255 256 /* Page 11h: audio settings and content info packets */ 257 #define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */ 258 # define AIP_CNTRL_0_RST_FIFO (1 << 0) 259 # define AIP_CNTRL_0_SWAP (1 << 1) 260 # define AIP_CNTRL_0_LAYOUT (1 << 2) 261 # define AIP_CNTRL_0_ACR_MAN (1 << 5) 262 # define AIP_CNTRL_0_RST_CTS (1 << 6) 263 #define REG_CA_I2S REG(0x11, 0x01) /* read/write */ 264 # define CA_I2S_CA_I2S(x) (((x) & 31) << 0) 265 # define CA_I2S_HBR_CHSTAT (1 << 6) 266 #define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */ 267 #define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */ 268 #define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */ 269 #define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */ 270 #define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */ 271 #define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */ 272 #define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */ 273 #define REG_CTS_N REG(0x11, 0x0c) /* read/write */ 274 # define CTS_N_K(x) (((x) & 7) << 0) 275 # define CTS_N_M(x) (((x) & 3) << 4) 276 #define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */ 277 # define ENC_CNTRL_RST_ENC (1 << 0) 278 # define ENC_CNTRL_RST_SEL (1 << 1) 279 # define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2) 280 #define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */ 281 # define DIP_FLAGS_ACR (1 << 0) 282 # define DIP_FLAGS_GC (1 << 1) 283 #define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */ 284 # define DIP_IF_FLAGS_IF1 (1 << 1) 285 # define DIP_IF_FLAGS_IF2 (1 << 2) 286 # define DIP_IF_FLAGS_IF3 (1 << 3) 287 # define DIP_IF_FLAGS_IF4 (1 << 4) 288 # define DIP_IF_FLAGS_IF5 (1 << 5) 289 #define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */ 290 291 292 /* Page 12h: HDCP and OTP */ 293 #define REG_TX3 REG(0x12, 0x9a) /* read/write */ 294 #define REG_TX4 REG(0x12, 0x9b) /* read/write */ 295 # define TX4_PD_RAM (1 << 1) 296 #define REG_TX33 REG(0x12, 0xb8) /* read/write */ 297 # define TX33_HDMI (1 << 1) 298 299 300 /* Page 13h: Gamut related metadata packets */ 301 302 303 304 /* CEC registers: (not paged) 305 */ 306 #define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */ 307 # define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7) 308 # define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6) 309 # define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1) 310 # define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0) 311 #define REG_CEC_RXSHPDLEV 0xfe /* read */ 312 # define CEC_RXSHPDLEV_RXSENS (1 << 0) 313 # define CEC_RXSHPDLEV_HPD (1 << 1) 314 315 #define REG_CEC_ENAMODS 0xff /* read/write */ 316 # define CEC_ENAMODS_DIS_FRO (1 << 6) 317 # define CEC_ENAMODS_DIS_CCLK (1 << 5) 318 # define CEC_ENAMODS_EN_RXSENS (1 << 2) 319 # define CEC_ENAMODS_EN_HDMI (1 << 1) 320 # define CEC_ENAMODS_EN_CEC (1 << 0) 321 322 323 /* Device versions: */ 324 #define TDA9989N2 0x0101 325 #define TDA19989 0x0201 326 #define TDA19989N2 0x0202 327 #define TDA19988 0x0301 328 329 static void 330 cec_write(struct drm_encoder *encoder, uint16_t addr, uint8_t val) 331 { 332 struct i2c_client *client = to_tda998x_priv(encoder)->cec; 333 uint8_t buf[] = {addr, val}; 334 int ret; 335 336 ret = i2c_master_send(client, buf, ARRAY_SIZE(buf)); 337 if (ret < 0) 338 dev_err(&client->dev, "Error %d writing to cec:0x%x\n", ret, addr); 339 } 340 341 static uint8_t 342 cec_read(struct drm_encoder *encoder, uint8_t addr) 343 { 344 struct i2c_client *client = to_tda998x_priv(encoder)->cec; 345 uint8_t val; 346 int ret; 347 348 ret = i2c_master_send(client, &addr, sizeof(addr)); 349 if (ret < 0) 350 goto fail; 351 352 ret = i2c_master_recv(client, &val, sizeof(val)); 353 if (ret < 0) 354 goto fail; 355 356 return val; 357 358 fail: 359 dev_err(&client->dev, "Error %d reading from cec:0x%x\n", ret, addr); 360 return 0; 361 } 362 363 static void 364 set_page(struct drm_encoder *encoder, uint16_t reg) 365 { 366 struct tda998x_priv *priv = to_tda998x_priv(encoder); 367 368 if (REG2PAGE(reg) != priv->current_page) { 369 struct i2c_client *client = drm_i2c_encoder_get_client(encoder); 370 uint8_t buf[] = { 371 REG_CURPAGE, REG2PAGE(reg) 372 }; 373 int ret = i2c_master_send(client, buf, sizeof(buf)); 374 if (ret < 0) 375 dev_err(&client->dev, "Error %d writing to REG_CURPAGE\n", ret); 376 377 priv->current_page = REG2PAGE(reg); 378 } 379 } 380 381 static int 382 reg_read_range(struct drm_encoder *encoder, uint16_t reg, char *buf, int cnt) 383 { 384 struct i2c_client *client = drm_i2c_encoder_get_client(encoder); 385 uint8_t addr = REG2ADDR(reg); 386 int ret; 387 388 set_page(encoder, reg); 389 390 ret = i2c_master_send(client, &addr, sizeof(addr)); 391 if (ret < 0) 392 goto fail; 393 394 ret = i2c_master_recv(client, buf, cnt); 395 if (ret < 0) 396 goto fail; 397 398 return ret; 399 400 fail: 401 dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg); 402 return ret; 403 } 404 405 static void 406 reg_write_range(struct drm_encoder *encoder, uint16_t reg, uint8_t *p, int cnt) 407 { 408 struct i2c_client *client = drm_i2c_encoder_get_client(encoder); 409 uint8_t buf[cnt+1]; 410 int ret; 411 412 buf[0] = REG2ADDR(reg); 413 memcpy(&buf[1], p, cnt); 414 415 set_page(encoder, reg); 416 417 ret = i2c_master_send(client, buf, cnt + 1); 418 if (ret < 0) 419 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); 420 } 421 422 static uint8_t 423 reg_read(struct drm_encoder *encoder, uint16_t reg) 424 { 425 uint8_t val = 0; 426 reg_read_range(encoder, reg, &val, sizeof(val)); 427 return val; 428 } 429 430 static void 431 reg_write(struct drm_encoder *encoder, uint16_t reg, uint8_t val) 432 { 433 struct i2c_client *client = drm_i2c_encoder_get_client(encoder); 434 uint8_t buf[] = {REG2ADDR(reg), val}; 435 int ret; 436 437 set_page(encoder, reg); 438 439 ret = i2c_master_send(client, buf, ARRAY_SIZE(buf)); 440 if (ret < 0) 441 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); 442 } 443 444 static void 445 reg_write16(struct drm_encoder *encoder, uint16_t reg, uint16_t val) 446 { 447 struct i2c_client *client = drm_i2c_encoder_get_client(encoder); 448 uint8_t buf[] = {REG2ADDR(reg), val >> 8, val}; 449 int ret; 450 451 set_page(encoder, reg); 452 453 ret = i2c_master_send(client, buf, ARRAY_SIZE(buf)); 454 if (ret < 0) 455 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); 456 } 457 458 static void 459 reg_set(struct drm_encoder *encoder, uint16_t reg, uint8_t val) 460 { 461 reg_write(encoder, reg, reg_read(encoder, reg) | val); 462 } 463 464 static void 465 reg_clear(struct drm_encoder *encoder, uint16_t reg, uint8_t val) 466 { 467 reg_write(encoder, reg, reg_read(encoder, reg) & ~val); 468 } 469 470 static void 471 tda998x_reset(struct drm_encoder *encoder) 472 { 473 /* reset audio and i2c master: */ 474 reg_set(encoder, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER); 475 msleep(50); 476 reg_clear(encoder, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER); 477 msleep(50); 478 479 /* reset transmitter: */ 480 reg_set(encoder, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); 481 reg_clear(encoder, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); 482 483 /* PLL registers common configuration */ 484 reg_write(encoder, REG_PLL_SERIAL_1, 0x00); 485 reg_write(encoder, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1)); 486 reg_write(encoder, REG_PLL_SERIAL_3, 0x00); 487 reg_write(encoder, REG_SERIALIZER, 0x00); 488 reg_write(encoder, REG_BUFFER_OUT, 0x00); 489 reg_write(encoder, REG_PLL_SCG1, 0x00); 490 reg_write(encoder, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8); 491 reg_write(encoder, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); 492 reg_write(encoder, REG_PLL_SCGN1, 0xfa); 493 reg_write(encoder, REG_PLL_SCGN2, 0x00); 494 reg_write(encoder, REG_PLL_SCGR1, 0x5b); 495 reg_write(encoder, REG_PLL_SCGR2, 0x00); 496 reg_write(encoder, REG_PLL_SCG2, 0x10); 497 498 /* Write the default value MUX register */ 499 reg_write(encoder, REG_MUX_VP_VIP_OUT, 0x24); 500 } 501 502 static uint8_t tda998x_cksum(uint8_t *buf, size_t bytes) 503 { 504 uint8_t sum = 0; 505 506 while (bytes--) 507 sum += *buf++; 508 return (255 - sum) + 1; 509 } 510 511 #define HB(x) (x) 512 #define PB(x) (HB(2) + 1 + (x)) 513 514 static void 515 tda998x_write_if(struct drm_encoder *encoder, uint8_t bit, uint16_t addr, 516 uint8_t *buf, size_t size) 517 { 518 buf[PB(0)] = tda998x_cksum(buf, size); 519 520 reg_clear(encoder, REG_DIP_IF_FLAGS, bit); 521 reg_write_range(encoder, addr, buf, size); 522 reg_set(encoder, REG_DIP_IF_FLAGS, bit); 523 } 524 525 static void 526 tda998x_write_aif(struct drm_encoder *encoder, struct tda998x_encoder_params *p) 527 { 528 uint8_t buf[PB(5) + 1]; 529 530 buf[HB(0)] = 0x84; 531 buf[HB(1)] = 0x01; 532 buf[HB(2)] = 10; 533 buf[PB(0)] = 0; 534 buf[PB(1)] = p->audio_frame[1] & 0x07; /* CC */ 535 buf[PB(2)] = p->audio_frame[2] & 0x1c; /* SF */ 536 buf[PB(4)] = p->audio_frame[4]; 537 buf[PB(5)] = p->audio_frame[5] & 0xf8; /* DM_INH + LSV */ 538 539 tda998x_write_if(encoder, DIP_IF_FLAGS_IF4, REG_IF4_HB0, buf, 540 sizeof(buf)); 541 } 542 543 static void 544 tda998x_write_avi(struct drm_encoder *encoder, struct drm_display_mode *mode) 545 { 546 uint8_t buf[PB(13) + 1]; 547 548 memset(buf, 0, sizeof(buf)); 549 buf[HB(0)] = 0x82; 550 buf[HB(1)] = 0x02; 551 buf[HB(2)] = 13; 552 buf[PB(4)] = drm_match_cea_mode(mode); 553 554 tda998x_write_if(encoder, DIP_IF_FLAGS_IF2, REG_IF2_HB0, buf, 555 sizeof(buf)); 556 } 557 558 static void tda998x_audio_mute(struct drm_encoder *encoder, bool on) 559 { 560 if (on) { 561 reg_set(encoder, REG_SOFTRESET, SOFTRESET_AUDIO); 562 reg_clear(encoder, REG_SOFTRESET, SOFTRESET_AUDIO); 563 reg_set(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); 564 } else { 565 reg_clear(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); 566 } 567 } 568 569 static void 570 tda998x_configure_audio(struct drm_encoder *encoder, 571 struct drm_display_mode *mode, struct tda998x_encoder_params *p) 572 { 573 uint8_t buf[6], clksel_aip, clksel_fs, ca_i2s, cts_n, adiv; 574 uint32_t n; 575 576 /* Enable audio ports */ 577 reg_write(encoder, REG_ENA_AP, p->audio_cfg); 578 reg_write(encoder, REG_ENA_ACLK, p->audio_clk_cfg); 579 580 /* Set audio input source */ 581 switch (p->audio_format) { 582 case AFMT_SPDIF: 583 reg_write(encoder, REG_MUX_AP, 0x40); 584 clksel_aip = AIP_CLKSEL_AIP(0); 585 /* FS64SPDIF */ 586 clksel_fs = AIP_CLKSEL_FS(2); 587 cts_n = CTS_N_M(3) | CTS_N_K(3); 588 ca_i2s = 0; 589 break; 590 591 case AFMT_I2S: 592 reg_write(encoder, REG_MUX_AP, 0x64); 593 clksel_aip = AIP_CLKSEL_AIP(1); 594 /* ACLK */ 595 clksel_fs = AIP_CLKSEL_FS(0); 596 cts_n = CTS_N_M(3) | CTS_N_K(3); 597 ca_i2s = CA_I2S_CA_I2S(0); 598 break; 599 600 default: 601 BUG(); 602 return; 603 } 604 605 reg_write(encoder, REG_AIP_CLKSEL, clksel_aip); 606 reg_clear(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT); 607 608 /* Enable automatic CTS generation */ 609 reg_clear(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_ACR_MAN); 610 reg_write(encoder, REG_CTS_N, cts_n); 611 612 /* 613 * Audio input somehow depends on HDMI line rate which is 614 * related to pixclk. Testing showed that modes with pixclk 615 * >100MHz need a larger divider while <40MHz need the default. 616 * There is no detailed info in the datasheet, so we just 617 * assume 100MHz requires larger divider. 618 */ 619 if (mode->clock > 100000) 620 adiv = AUDIO_DIV_SERCLK_16; 621 else 622 adiv = AUDIO_DIV_SERCLK_8; 623 reg_write(encoder, REG_AUDIO_DIV, adiv); 624 625 /* 626 * This is the approximate value of N, which happens to be 627 * the recommended values for non-coherent clocks. 628 */ 629 n = 128 * p->audio_sample_rate / 1000; 630 631 /* Write the CTS and N values */ 632 buf[0] = 0x44; 633 buf[1] = 0x42; 634 buf[2] = 0x01; 635 buf[3] = n; 636 buf[4] = n >> 8; 637 buf[5] = n >> 16; 638 reg_write_range(encoder, REG_ACR_CTS_0, buf, 6); 639 640 /* Set CTS clock reference */ 641 reg_write(encoder, REG_AIP_CLKSEL, clksel_aip | clksel_fs); 642 643 /* Reset CTS generator */ 644 reg_set(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS); 645 reg_clear(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS); 646 647 /* Write the channel status */ 648 buf[0] = 0x04; 649 buf[1] = 0x00; 650 buf[2] = 0x00; 651 buf[3] = 0xf1; 652 reg_write_range(encoder, REG_CH_STAT_B(0), buf, 4); 653 654 tda998x_audio_mute(encoder, true); 655 mdelay(20); 656 tda998x_audio_mute(encoder, false); 657 658 /* Write the audio information packet */ 659 tda998x_write_aif(encoder, p); 660 } 661 662 /* DRM encoder functions */ 663 664 static void 665 tda998x_encoder_set_config(struct drm_encoder *encoder, void *params) 666 { 667 struct tda998x_priv *priv = to_tda998x_priv(encoder); 668 struct tda998x_encoder_params *p = params; 669 670 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) | 671 (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) | 672 VIP_CNTRL_0_SWAP_B(p->swap_b) | 673 (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0); 674 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) | 675 (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) | 676 VIP_CNTRL_1_SWAP_D(p->swap_d) | 677 (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0); 678 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) | 679 (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) | 680 VIP_CNTRL_2_SWAP_F(p->swap_f) | 681 (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0); 682 683 priv->params = *p; 684 } 685 686 static void 687 tda998x_encoder_dpms(struct drm_encoder *encoder, int mode) 688 { 689 struct tda998x_priv *priv = to_tda998x_priv(encoder); 690 691 /* we only care about on or off: */ 692 if (mode != DRM_MODE_DPMS_ON) 693 mode = DRM_MODE_DPMS_OFF; 694 695 if (mode == priv->dpms) 696 return; 697 698 switch (mode) { 699 case DRM_MODE_DPMS_ON: 700 /* enable video ports, audio will be enabled later */ 701 reg_write(encoder, REG_ENA_VP_0, 0xff); 702 reg_write(encoder, REG_ENA_VP_1, 0xff); 703 reg_write(encoder, REG_ENA_VP_2, 0xff); 704 /* set muxing after enabling ports: */ 705 reg_write(encoder, REG_VIP_CNTRL_0, priv->vip_cntrl_0); 706 reg_write(encoder, REG_VIP_CNTRL_1, priv->vip_cntrl_1); 707 reg_write(encoder, REG_VIP_CNTRL_2, priv->vip_cntrl_2); 708 break; 709 case DRM_MODE_DPMS_OFF: 710 /* disable audio and video ports */ 711 reg_write(encoder, REG_ENA_AP, 0x00); 712 reg_write(encoder, REG_ENA_VP_0, 0x00); 713 reg_write(encoder, REG_ENA_VP_1, 0x00); 714 reg_write(encoder, REG_ENA_VP_2, 0x00); 715 break; 716 } 717 718 priv->dpms = mode; 719 } 720 721 static void 722 tda998x_encoder_save(struct drm_encoder *encoder) 723 { 724 DBG(""); 725 } 726 727 static void 728 tda998x_encoder_restore(struct drm_encoder *encoder) 729 { 730 DBG(""); 731 } 732 733 static bool 734 tda998x_encoder_mode_fixup(struct drm_encoder *encoder, 735 const struct drm_display_mode *mode, 736 struct drm_display_mode *adjusted_mode) 737 { 738 return true; 739 } 740 741 static int 742 tda998x_encoder_mode_valid(struct drm_encoder *encoder, 743 struct drm_display_mode *mode) 744 { 745 return MODE_OK; 746 } 747 748 static void 749 tda998x_encoder_mode_set(struct drm_encoder *encoder, 750 struct drm_display_mode *mode, 751 struct drm_display_mode *adjusted_mode) 752 { 753 struct tda998x_priv *priv = to_tda998x_priv(encoder); 754 uint16_t ref_pix, ref_line, n_pix, n_line; 755 uint16_t hs_pix_s, hs_pix_e; 756 uint16_t vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e; 757 uint16_t vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e; 758 uint16_t vwin1_line_s, vwin1_line_e; 759 uint16_t vwin2_line_s, vwin2_line_e; 760 uint16_t de_pix_s, de_pix_e; 761 uint8_t reg, div, rep; 762 763 /* 764 * Internally TDA998x is using ITU-R BT.656 style sync but 765 * we get VESA style sync. TDA998x is using a reference pixel 766 * relative to ITU to sync to the input frame and for output 767 * sync generation. Currently, we are using reference detection 768 * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point 769 * which is position of rising VS with coincident rising HS. 770 * 771 * Now there is some issues to take care of: 772 * - HDMI data islands require sync-before-active 773 * - TDA998x register values must be > 0 to be enabled 774 * - REFLINE needs an additional offset of +1 775 * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB 776 * 777 * So we add +1 to all horizontal and vertical register values, 778 * plus an additional +3 for REFPIX as we are using RGB input only. 779 */ 780 n_pix = mode->htotal; 781 n_line = mode->vtotal; 782 783 hs_pix_e = mode->hsync_end - mode->hdisplay; 784 hs_pix_s = mode->hsync_start - mode->hdisplay; 785 de_pix_e = mode->htotal; 786 de_pix_s = mode->htotal - mode->hdisplay; 787 ref_pix = 3 + hs_pix_s; 788 789 /* 790 * Attached LCD controllers may generate broken sync. Allow 791 * those to adjust the position of the rising VS edge by adding 792 * HSKEW to ref_pix. 793 */ 794 if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW) 795 ref_pix += adjusted_mode->hskew; 796 797 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) { 798 ref_line = 1 + mode->vsync_start - mode->vdisplay; 799 vwin1_line_s = mode->vtotal - mode->vdisplay - 1; 800 vwin1_line_e = vwin1_line_s + mode->vdisplay; 801 vs1_pix_s = vs1_pix_e = hs_pix_s; 802 vs1_line_s = mode->vsync_start - mode->vdisplay; 803 vs1_line_e = vs1_line_s + 804 mode->vsync_end - mode->vsync_start; 805 vwin2_line_s = vwin2_line_e = 0; 806 vs2_pix_s = vs2_pix_e = 0; 807 vs2_line_s = vs2_line_e = 0; 808 } else { 809 ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2; 810 vwin1_line_s = (mode->vtotal - mode->vdisplay)/2; 811 vwin1_line_e = vwin1_line_s + mode->vdisplay/2; 812 vs1_pix_s = vs1_pix_e = hs_pix_s; 813 vs1_line_s = (mode->vsync_start - mode->vdisplay)/2; 814 vs1_line_e = vs1_line_s + 815 (mode->vsync_end - mode->vsync_start)/2; 816 vwin2_line_s = vwin1_line_s + mode->vtotal/2; 817 vwin2_line_e = vwin2_line_s + mode->vdisplay/2; 818 vs2_pix_s = vs2_pix_e = hs_pix_s + mode->htotal/2; 819 vs2_line_s = vs1_line_s + mode->vtotal/2 ; 820 vs2_line_e = vs2_line_s + 821 (mode->vsync_end - mode->vsync_start)/2; 822 } 823 824 div = 148500 / mode->clock; 825 826 /* mute the audio FIFO: */ 827 reg_set(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); 828 829 /* set HDMI HDCP mode off: */ 830 reg_set(encoder, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS); 831 reg_clear(encoder, REG_TX33, TX33_HDMI); 832 833 reg_write(encoder, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0)); 834 /* no pre-filter or interpolator: */ 835 reg_write(encoder, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) | 836 HVF_CNTRL_0_INTPOL(0)); 837 reg_write(encoder, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0)); 838 reg_write(encoder, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) | 839 VIP_CNTRL_4_BLC(0)); 840 reg_clear(encoder, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR); 841 842 reg_clear(encoder, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ); 843 reg_clear(encoder, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_DE); 844 reg_write(encoder, REG_SERIALIZER, 0); 845 reg_write(encoder, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0)); 846 847 /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */ 848 rep = 0; 849 reg_write(encoder, REG_RPT_CNTRL, 0); 850 reg_write(encoder, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) | 851 SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); 852 853 reg_write(encoder, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) | 854 PLL_SERIAL_2_SRL_PR(rep)); 855 856 /* set color matrix bypass flag: */ 857 reg_set(encoder, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP); 858 859 /* set BIAS tmds value: */ 860 reg_write(encoder, REG_ANA_GENERAL, 0x09); 861 862 reg_clear(encoder, REG_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_MTHD); 863 864 /* 865 * Sync on rising HSYNC/VSYNC 866 */ 867 reg_write(encoder, REG_VIP_CNTRL_3, 0); 868 reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_SYNC_HS); 869 870 /* 871 * TDA19988 requires high-active sync at input stage, 872 * so invert low-active sync provided by master encoder here 873 */ 874 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 875 reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_H_TGL); 876 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 877 reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_V_TGL); 878 879 /* 880 * Always generate sync polarity relative to input sync and 881 * revert input stage toggled sync at output stage 882 */ 883 reg = TBG_CNTRL_1_TGL_EN; 884 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 885 reg |= TBG_CNTRL_1_H_TGL; 886 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 887 reg |= TBG_CNTRL_1_V_TGL; 888 reg_write(encoder, REG_TBG_CNTRL_1, reg); 889 890 reg_write(encoder, REG_VIDFORMAT, 0x00); 891 reg_write16(encoder, REG_REFPIX_MSB, ref_pix); 892 reg_write16(encoder, REG_REFLINE_MSB, ref_line); 893 reg_write16(encoder, REG_NPIX_MSB, n_pix); 894 reg_write16(encoder, REG_NLINE_MSB, n_line); 895 reg_write16(encoder, REG_VS_LINE_STRT_1_MSB, vs1_line_s); 896 reg_write16(encoder, REG_VS_PIX_STRT_1_MSB, vs1_pix_s); 897 reg_write16(encoder, REG_VS_LINE_END_1_MSB, vs1_line_e); 898 reg_write16(encoder, REG_VS_PIX_END_1_MSB, vs1_pix_e); 899 reg_write16(encoder, REG_VS_LINE_STRT_2_MSB, vs2_line_s); 900 reg_write16(encoder, REG_VS_PIX_STRT_2_MSB, vs2_pix_s); 901 reg_write16(encoder, REG_VS_LINE_END_2_MSB, vs2_line_e); 902 reg_write16(encoder, REG_VS_PIX_END_2_MSB, vs2_pix_e); 903 reg_write16(encoder, REG_HS_PIX_START_MSB, hs_pix_s); 904 reg_write16(encoder, REG_HS_PIX_STOP_MSB, hs_pix_e); 905 reg_write16(encoder, REG_VWIN_START_1_MSB, vwin1_line_s); 906 reg_write16(encoder, REG_VWIN_END_1_MSB, vwin1_line_e); 907 reg_write16(encoder, REG_VWIN_START_2_MSB, vwin2_line_s); 908 reg_write16(encoder, REG_VWIN_END_2_MSB, vwin2_line_e); 909 reg_write16(encoder, REG_DE_START_MSB, de_pix_s); 910 reg_write16(encoder, REG_DE_STOP_MSB, de_pix_e); 911 912 if (priv->rev == TDA19988) { 913 /* let incoming pixels fill the active space (if any) */ 914 reg_write(encoder, REG_ENABLE_SPACE, 0x01); 915 } 916 917 /* must be last register set: */ 918 reg_clear(encoder, REG_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_ONCE); 919 920 /* Only setup the info frames if the sink is HDMI */ 921 if (priv->is_hdmi_sink) { 922 /* We need to turn HDMI HDCP stuff on to get audio through */ 923 reg_clear(encoder, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS); 924 reg_write(encoder, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1)); 925 reg_set(encoder, REG_TX33, TX33_HDMI); 926 927 tda998x_write_avi(encoder, adjusted_mode); 928 929 if (priv->params.audio_cfg) 930 tda998x_configure_audio(encoder, adjusted_mode, 931 &priv->params); 932 } 933 } 934 935 static enum drm_connector_status 936 tda998x_encoder_detect(struct drm_encoder *encoder, 937 struct drm_connector *connector) 938 { 939 uint8_t val = cec_read(encoder, REG_CEC_RXSHPDLEV); 940 return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected : 941 connector_status_disconnected; 942 } 943 944 static int 945 read_edid_block(struct drm_encoder *encoder, uint8_t *buf, int blk) 946 { 947 uint8_t offset, segptr; 948 int ret, i; 949 950 /* enable EDID read irq: */ 951 reg_set(encoder, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); 952 953 offset = (blk & 1) ? 128 : 0; 954 segptr = blk / 2; 955 956 reg_write(encoder, REG_DDC_ADDR, 0xa0); 957 reg_write(encoder, REG_DDC_OFFS, offset); 958 reg_write(encoder, REG_DDC_SEGM_ADDR, 0x60); 959 reg_write(encoder, REG_DDC_SEGM, segptr); 960 961 /* enable reading EDID: */ 962 reg_write(encoder, REG_EDID_CTRL, 0x1); 963 964 /* flag must be cleared by sw: */ 965 reg_write(encoder, REG_EDID_CTRL, 0x0); 966 967 /* wait for block read to complete: */ 968 for (i = 100; i > 0; i--) { 969 uint8_t val = reg_read(encoder, REG_INT_FLAGS_2); 970 if (val & INT_FLAGS_2_EDID_BLK_RD) 971 break; 972 msleep(1); 973 } 974 975 if (i == 0) 976 return -ETIMEDOUT; 977 978 ret = reg_read_range(encoder, REG_EDID_DATA_0, buf, EDID_LENGTH); 979 if (ret != EDID_LENGTH) { 980 dev_err(encoder->dev->dev, "failed to read edid block %d: %d", 981 blk, ret); 982 return ret; 983 } 984 985 reg_clear(encoder, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); 986 987 return 0; 988 } 989 990 static uint8_t * 991 do_get_edid(struct drm_encoder *encoder) 992 { 993 struct tda998x_priv *priv = to_tda998x_priv(encoder); 994 int j = 0, valid_extensions = 0; 995 uint8_t *block, *new; 996 bool print_bad_edid = drm_debug & DRM_UT_KMS; 997 998 if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) 999 return NULL; 1000 1001 if (priv->rev == TDA19988) 1002 reg_clear(encoder, REG_TX4, TX4_PD_RAM); 1003 1004 /* base block fetch */ 1005 if (read_edid_block(encoder, block, 0)) 1006 goto fail; 1007 1008 if (!drm_edid_block_valid(block, 0, print_bad_edid)) 1009 goto fail; 1010 1011 /* if there's no extensions, we're done */ 1012 if (block[0x7e] == 0) 1013 goto done; 1014 1015 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL); 1016 if (!new) 1017 goto fail; 1018 block = new; 1019 1020 for (j = 1; j <= block[0x7e]; j++) { 1021 uint8_t *ext_block = block + (valid_extensions + 1) * EDID_LENGTH; 1022 if (read_edid_block(encoder, ext_block, j)) 1023 goto fail; 1024 1025 if (!drm_edid_block_valid(ext_block, j, print_bad_edid)) 1026 goto fail; 1027 1028 valid_extensions++; 1029 } 1030 1031 if (valid_extensions != block[0x7e]) { 1032 block[EDID_LENGTH-1] += block[0x7e] - valid_extensions; 1033 block[0x7e] = valid_extensions; 1034 new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1035 if (!new) 1036 goto fail; 1037 block = new; 1038 } 1039 1040 done: 1041 if (priv->rev == TDA19988) 1042 reg_set(encoder, REG_TX4, TX4_PD_RAM); 1043 1044 return block; 1045 1046 fail: 1047 if (priv->rev == TDA19988) 1048 reg_set(encoder, REG_TX4, TX4_PD_RAM); 1049 dev_warn(encoder->dev->dev, "failed to read EDID\n"); 1050 kfree(block); 1051 return NULL; 1052 } 1053 1054 static int 1055 tda998x_encoder_get_modes(struct drm_encoder *encoder, 1056 struct drm_connector *connector) 1057 { 1058 struct tda998x_priv *priv = to_tda998x_priv(encoder); 1059 struct edid *edid = (struct edid *)do_get_edid(encoder); 1060 int n = 0; 1061 1062 if (edid) { 1063 drm_mode_connector_update_edid_property(connector, edid); 1064 n = drm_add_edid_modes(connector, edid); 1065 priv->is_hdmi_sink = drm_detect_hdmi_monitor(edid); 1066 kfree(edid); 1067 } 1068 1069 return n; 1070 } 1071 1072 static int 1073 tda998x_encoder_create_resources(struct drm_encoder *encoder, 1074 struct drm_connector *connector) 1075 { 1076 DBG(""); 1077 return 0; 1078 } 1079 1080 static int 1081 tda998x_encoder_set_property(struct drm_encoder *encoder, 1082 struct drm_connector *connector, 1083 struct drm_property *property, 1084 uint64_t val) 1085 { 1086 DBG(""); 1087 return 0; 1088 } 1089 1090 static void 1091 tda998x_encoder_destroy(struct drm_encoder *encoder) 1092 { 1093 struct tda998x_priv *priv = to_tda998x_priv(encoder); 1094 drm_i2c_encoder_destroy(encoder); 1095 kfree(priv); 1096 } 1097 1098 static struct drm_encoder_slave_funcs tda998x_encoder_funcs = { 1099 .set_config = tda998x_encoder_set_config, 1100 .destroy = tda998x_encoder_destroy, 1101 .dpms = tda998x_encoder_dpms, 1102 .save = tda998x_encoder_save, 1103 .restore = tda998x_encoder_restore, 1104 .mode_fixup = tda998x_encoder_mode_fixup, 1105 .mode_valid = tda998x_encoder_mode_valid, 1106 .mode_set = tda998x_encoder_mode_set, 1107 .detect = tda998x_encoder_detect, 1108 .get_modes = tda998x_encoder_get_modes, 1109 .create_resources = tda998x_encoder_create_resources, 1110 .set_property = tda998x_encoder_set_property, 1111 }; 1112 1113 /* I2C driver functions */ 1114 1115 static int 1116 tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id) 1117 { 1118 return 0; 1119 } 1120 1121 static int 1122 tda998x_remove(struct i2c_client *client) 1123 { 1124 return 0; 1125 } 1126 1127 static int 1128 tda998x_encoder_init(struct i2c_client *client, 1129 struct drm_device *dev, 1130 struct drm_encoder_slave *encoder_slave) 1131 { 1132 struct drm_encoder *encoder = &encoder_slave->base; 1133 struct tda998x_priv *priv; 1134 1135 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 1136 if (!priv) 1137 return -ENOMEM; 1138 1139 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3); 1140 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1); 1141 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5); 1142 1143 priv->current_page = 0; 1144 priv->cec = i2c_new_dummy(client->adapter, 0x34); 1145 priv->dpms = DRM_MODE_DPMS_OFF; 1146 1147 encoder_slave->slave_priv = priv; 1148 encoder_slave->slave_funcs = &tda998x_encoder_funcs; 1149 1150 /* wake up the device: */ 1151 cec_write(encoder, REG_CEC_ENAMODS, 1152 CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI); 1153 1154 tda998x_reset(encoder); 1155 1156 /* read version: */ 1157 priv->rev = reg_read(encoder, REG_VERSION_LSB) | 1158 reg_read(encoder, REG_VERSION_MSB) << 8; 1159 1160 /* mask off feature bits: */ 1161 priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */ 1162 1163 switch (priv->rev) { 1164 case TDA9989N2: dev_info(dev->dev, "found TDA9989 n2"); break; 1165 case TDA19989: dev_info(dev->dev, "found TDA19989"); break; 1166 case TDA19989N2: dev_info(dev->dev, "found TDA19989 n2"); break; 1167 case TDA19988: dev_info(dev->dev, "found TDA19988"); break; 1168 default: 1169 DBG("found unsupported device: %04x", priv->rev); 1170 goto fail; 1171 } 1172 1173 /* after reset, enable DDC: */ 1174 reg_write(encoder, REG_DDC_DISABLE, 0x00); 1175 1176 /* set clock on DDC channel: */ 1177 reg_write(encoder, REG_TX3, 39); 1178 1179 /* if necessary, disable multi-master: */ 1180 if (priv->rev == TDA19989) 1181 reg_set(encoder, REG_I2C_MASTER, I2C_MASTER_DIS_MM); 1182 1183 cec_write(encoder, REG_CEC_FRO_IM_CLK_CTRL, 1184 CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL); 1185 1186 return 0; 1187 1188 fail: 1189 /* if encoder_init fails, the encoder slave is never registered, 1190 * so cleanup here: 1191 */ 1192 if (priv->cec) 1193 i2c_unregister_device(priv->cec); 1194 kfree(priv); 1195 encoder_slave->slave_priv = NULL; 1196 encoder_slave->slave_funcs = NULL; 1197 return -ENXIO; 1198 } 1199 1200 static struct i2c_device_id tda998x_ids[] = { 1201 { "tda998x", 0 }, 1202 { } 1203 }; 1204 MODULE_DEVICE_TABLE(i2c, tda998x_ids); 1205 1206 static struct drm_i2c_encoder_driver tda998x_driver = { 1207 .i2c_driver = { 1208 .probe = tda998x_probe, 1209 .remove = tda998x_remove, 1210 .driver = { 1211 .name = "tda998x", 1212 }, 1213 .id_table = tda998x_ids, 1214 }, 1215 .encoder_init = tda998x_encoder_init, 1216 }; 1217 1218 /* Module initialization */ 1219 1220 static int __init 1221 tda998x_init(void) 1222 { 1223 DBG(""); 1224 return drm_i2c_encoder_register(THIS_MODULE, &tda998x_driver); 1225 } 1226 1227 static void __exit 1228 tda998x_exit(void) 1229 { 1230 DBG(""); 1231 drm_i2c_encoder_unregister(&tda998x_driver); 1232 } 1233 1234 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); 1235 MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder"); 1236 MODULE_LICENSE("GPL"); 1237 1238 module_init(tda998x_init); 1239 module_exit(tda998x_exit); 1240