1 /* 2 * Copyright (C) 2009 Francisco Jerez. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining 6 * a copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sublicense, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial 15 * portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 */ 26 27 #ifndef __DRM_I2C_CH7006_PRIV_H__ 28 #define __DRM_I2C_CH7006_PRIV_H__ 29 30 #include <drm/drm_encoder_slave.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/i2c/ch7006.h> 33 34 typedef int64_t fixed; 35 #define fixed1 (1LL << 32) 36 37 enum ch7006_tv_norm { 38 TV_NORM_PAL, 39 TV_NORM_PAL_M, 40 TV_NORM_PAL_N, 41 TV_NORM_PAL_NC, 42 TV_NORM_PAL_60, 43 TV_NORM_NTSC_M, 44 TV_NORM_NTSC_J, 45 NUM_TV_NORMS 46 }; 47 48 struct ch7006_tv_norm_info { 49 fixed vrefresh; 50 int vdisplay; 51 int vtotal; 52 int hvirtual; 53 54 fixed subc_freq; 55 fixed black_level; 56 57 uint32_t dispmode; 58 int voffset; 59 }; 60 61 struct ch7006_mode { 62 struct drm_display_mode mode; 63 64 int enc_hdisp; 65 int enc_vdisp; 66 67 fixed subc_coeff; 68 uint32_t dispmode; 69 70 uint32_t valid_scales; 71 uint32_t valid_norms; 72 }; 73 74 struct ch7006_state { 75 uint8_t regs[0x26]; 76 }; 77 78 struct ch7006_priv { 79 struct ch7006_encoder_params params; 80 const struct ch7006_mode *mode; 81 82 struct ch7006_state state; 83 struct ch7006_state saved_state; 84 85 struct drm_property *scale_property; 86 87 int select_subconnector; 88 int subconnector; 89 int hmargin; 90 int vmargin; 91 enum ch7006_tv_norm norm; 92 int brightness; 93 int contrast; 94 int flicker; 95 int scale; 96 97 int chip_version; 98 int last_dpms; 99 }; 100 101 #define to_ch7006_priv(x) \ 102 ((struct ch7006_priv *)to_encoder_slave(x)->slave_priv) 103 104 extern int ch7006_debug; 105 extern char *ch7006_tv_norm; 106 extern int ch7006_scale; 107 108 extern const char * const ch7006_tv_norm_names[]; 109 extern const struct ch7006_tv_norm_info ch7006_tv_norms[]; 110 extern const struct ch7006_mode ch7006_modes[]; 111 112 const struct ch7006_mode *ch7006_lookup_mode(struct drm_encoder *encoder, 113 const struct drm_display_mode *drm_mode); 114 115 void ch7006_setup_levels(struct drm_encoder *encoder); 116 void ch7006_setup_subcarrier(struct drm_encoder *encoder); 117 void ch7006_setup_pll(struct drm_encoder *encoder); 118 void ch7006_setup_power_state(struct drm_encoder *encoder); 119 void ch7006_setup_properties(struct drm_encoder *encoder); 120 121 void ch7006_write(struct i2c_client *client, uint8_t addr, uint8_t val); 122 uint8_t ch7006_read(struct i2c_client *client, uint8_t addr); 123 124 void ch7006_state_load(struct i2c_client *client, 125 struct ch7006_state *state); 126 void ch7006_state_save(struct i2c_client *client, 127 struct ch7006_state *state); 128 129 /* Some helper macros */ 130 131 #define ch7006_dbg(client, format, ...) do { \ 132 if (ch7006_debug) \ 133 dev_printk(KERN_DEBUG, &client->dev, \ 134 "%s: " format, __func__, ## __VA_ARGS__); \ 135 } while (0) 136 #define ch7006_info(client, format, ...) \ 137 dev_info(&client->dev, format, __VA_ARGS__) 138 #define ch7006_err(client, format, ...) \ 139 dev_err(&client->dev, format, __VA_ARGS__) 140 141 #define __mask(src, bitfield) \ 142 (((2 << (1 ? bitfield)) - 1) & ~((1 << (0 ? bitfield)) - 1)) 143 #define mask(bitfield) __mask(bitfield) 144 145 #define __bitf(src, bitfield, x) \ 146 (((x) >> (src) << (0 ? bitfield)) & __mask(src, bitfield)) 147 #define bitf(bitfield, x) __bitf(bitfield, x) 148 #define bitfs(bitfield, s) __bitf(bitfield, bitfield##_##s) 149 #define setbitf(state, reg, bitfield, x) \ 150 state->regs[reg] = (state->regs[reg] & ~mask(reg##_##bitfield)) \ 151 | bitf(reg##_##bitfield, x) 152 153 #define __unbitf(src, bitfield, x) \ 154 ((x & __mask(src, bitfield)) >> (0 ? bitfield) << (src)) 155 #define unbitf(bitfield, x) __unbitf(bitfield, x) 156 157 static inline int interpolate(int y0, int y1, int y2, int x) 158 { 159 return y1 + (x < 50 ? y1 - y0 : y2 - y1) * (x - 50) / 50; 160 } 161 162 static inline int32_t round_fixed(fixed x) 163 { 164 return (x + fixed1/2) >> 32; 165 } 166 167 #define ch7006_load_reg(client, state, reg) ch7006_write(client, reg, state->regs[reg]) 168 #define ch7006_save_reg(client, state, reg) state->regs[reg] = ch7006_read(client, reg) 169 170 /* Fixed hardware specs */ 171 172 #define CH7006_FREQ0 14318 173 #define CH7006_MAXN 650 174 #define CH7006_MAXM 315 175 176 /* Register definitions */ 177 178 #define CH7006_DISPMODE 0x00 179 #define CH7006_DISPMODE_INPUT_RES 0, 7:5 180 #define CH7006_DISPMODE_INPUT_RES_512x384 0x0 181 #define CH7006_DISPMODE_INPUT_RES_720x400 0x1 182 #define CH7006_DISPMODE_INPUT_RES_640x400 0x2 183 #define CH7006_DISPMODE_INPUT_RES_640x480 0x3 184 #define CH7006_DISPMODE_INPUT_RES_800x600 0x4 185 #define CH7006_DISPMODE_INPUT_RES_NATIVE 0x5 186 #define CH7006_DISPMODE_OUTPUT_STD 0, 4:3 187 #define CH7006_DISPMODE_OUTPUT_STD_PAL 0x0 188 #define CH7006_DISPMODE_OUTPUT_STD_NTSC 0x1 189 #define CH7006_DISPMODE_OUTPUT_STD_PAL_M 0x2 190 #define CH7006_DISPMODE_OUTPUT_STD_NTSC_J 0x3 191 #define CH7006_DISPMODE_SCALING_RATIO 0, 2:0 192 #define CH7006_DISPMODE_SCALING_RATIO_5_4 0x0 193 #define CH7006_DISPMODE_SCALING_RATIO_1_1 0x1 194 #define CH7006_DISPMODE_SCALING_RATIO_7_8 0x2 195 #define CH7006_DISPMODE_SCALING_RATIO_5_6 0x3 196 #define CH7006_DISPMODE_SCALING_RATIO_3_4 0x4 197 #define CH7006_DISPMODE_SCALING_RATIO_7_10 0x5 198 199 #define CH7006_FFILTER 0x01 200 #define CH7006_FFILTER_TEXT 0, 5:4 201 #define CH7006_FFILTER_LUMA 0, 3:2 202 #define CH7006_FFILTER_CHROMA 0, 1:0 203 #define CH7006_FFILTER_CHROMA_NO_DCRAWL 0x3 204 205 #define CH7006_BWIDTH 0x03 206 #define CH7006_BWIDTH_5L_FFILER (1 << 7) 207 #define CH7006_BWIDTH_CVBS_NO_CHROMA (1 << 6) 208 #define CH7006_BWIDTH_CHROMA 0, 5:4 209 #define CH7006_BWIDTH_SVIDEO_YPEAK (1 << 3) 210 #define CH7006_BWIDTH_SVIDEO_LUMA 0, 2:1 211 #define CH7006_BWIDTH_CVBS_LUMA 0, 0:0 212 213 #define CH7006_INPUT_FORMAT 0x04 214 #define CH7006_INPUT_FORMAT_DAC_GAIN (1 << 6) 215 #define CH7006_INPUT_FORMAT_RGB_PASS_THROUGH (1 << 5) 216 #define CH7006_INPUT_FORMAT_FORMAT 0, 3:0 217 #define CH7006_INPUT_FORMAT_FORMAT_RGB16 0x0 218 #define CH7006_INPUT_FORMAT_FORMAT_YCrCb24m16 0x1 219 #define CH7006_INPUT_FORMAT_FORMAT_RGB24m16 0x2 220 #define CH7006_INPUT_FORMAT_FORMAT_RGB15 0x3 221 #define CH7006_INPUT_FORMAT_FORMAT_RGB24m12C 0x4 222 #define CH7006_INPUT_FORMAT_FORMAT_RGB24m12I 0x5 223 #define CH7006_INPUT_FORMAT_FORMAT_RGB24m8 0x6 224 #define CH7006_INPUT_FORMAT_FORMAT_RGB16m8 0x7 225 #define CH7006_INPUT_FORMAT_FORMAT_RGB15m8 0x8 226 #define CH7006_INPUT_FORMAT_FORMAT_YCrCb24m8 0x9 227 228 #define CH7006_CLKMODE 0x06 229 #define CH7006_CLKMODE_SUBC_LOCK (1 << 7) 230 #define CH7006_CLKMODE_MASTER (1 << 6) 231 #define CH7006_CLKMODE_POS_EDGE (1 << 4) 232 #define CH7006_CLKMODE_XCM 0, 3:2 233 #define CH7006_CLKMODE_PCM 0, 1:0 234 235 #define CH7006_START_ACTIVE 0x07 236 #define CH7006_START_ACTIVE_0 0, 7:0 237 238 #define CH7006_POV 0x08 239 #define CH7006_POV_START_ACTIVE_8 8, 2:2 240 #define CH7006_POV_HPOS_8 8, 1:1 241 #define CH7006_POV_VPOS_8 8, 0:0 242 243 #define CH7006_BLACK_LEVEL 0x09 244 #define CH7006_BLACK_LEVEL_0 0, 7:0 245 246 #define CH7006_HPOS 0x0a 247 #define CH7006_HPOS_0 0, 7:0 248 249 #define CH7006_VPOS 0x0b 250 #define CH7006_VPOS_0 0, 7:0 251 252 #define CH7006_INPUT_SYNC 0x0d 253 #define CH7006_INPUT_SYNC_EMBEDDED (1 << 3) 254 #define CH7006_INPUT_SYNC_OUTPUT (1 << 2) 255 #define CH7006_INPUT_SYNC_PVSYNC (1 << 1) 256 #define CH7006_INPUT_SYNC_PHSYNC (1 << 0) 257 258 #define CH7006_POWER 0x0e 259 #define CH7006_POWER_SCART (1 << 4) 260 #define CH7006_POWER_RESET (1 << 3) 261 #define CH7006_POWER_LEVEL 0, 2:0 262 #define CH7006_POWER_LEVEL_CVBS_OFF 0x0 263 #define CH7006_POWER_LEVEL_POWER_OFF 0x1 264 #define CH7006_POWER_LEVEL_SVIDEO_OFF 0x2 265 #define CH7006_POWER_LEVEL_NORMAL 0x3 266 #define CH7006_POWER_LEVEL_FULL_POWER_OFF 0x4 267 268 #define CH7006_DETECT 0x10 269 #define CH7006_DETECT_SVIDEO_Y_TEST (1 << 3) 270 #define CH7006_DETECT_SVIDEO_C_TEST (1 << 2) 271 #define CH7006_DETECT_CVBS_TEST (1 << 1) 272 #define CH7006_DETECT_SENSE (1 << 0) 273 274 #define CH7006_CONTRAST 0x11 275 #define CH7006_CONTRAST_0 0, 2:0 276 277 #define CH7006_PLLOV 0x13 278 #define CH7006_PLLOV_N_8 8, 2:1 279 #define CH7006_PLLOV_M_8 8, 0:0 280 281 #define CH7006_PLLM 0x14 282 #define CH7006_PLLM_0 0, 7:0 283 284 #define CH7006_PLLN 0x15 285 #define CH7006_PLLN_0 0, 7:0 286 287 #define CH7006_BCLKOUT 0x17 288 289 #define CH7006_SUBC_INC0 0x18 290 #define CH7006_SUBC_INC0_28 28, 3:0 291 292 #define CH7006_SUBC_INC1 0x19 293 #define CH7006_SUBC_INC1_24 24, 3:0 294 295 #define CH7006_SUBC_INC2 0x1a 296 #define CH7006_SUBC_INC2_20 20, 3:0 297 298 #define CH7006_SUBC_INC3 0x1b 299 #define CH7006_SUBC_INC3_GPIO1_VAL (1 << 7) 300 #define CH7006_SUBC_INC3_GPIO0_VAL (1 << 6) 301 #define CH7006_SUBC_INC3_POUT_3_3V (1 << 5) 302 #define CH7006_SUBC_INC3_POUT_INV (1 << 4) 303 #define CH7006_SUBC_INC3_16 16, 3:0 304 305 #define CH7006_SUBC_INC4 0x1c 306 #define CH7006_SUBC_INC4_GPIO1_IN (1 << 7) 307 #define CH7006_SUBC_INC4_GPIO0_IN (1 << 6) 308 #define CH7006_SUBC_INC4_DS_INPUT (1 << 4) 309 #define CH7006_SUBC_INC4_12 12, 3:0 310 311 #define CH7006_SUBC_INC5 0x1d 312 #define CH7006_SUBC_INC5_8 8, 3:0 313 314 #define CH7006_SUBC_INC6 0x1e 315 #define CH7006_SUBC_INC6_4 4, 3:0 316 317 #define CH7006_SUBC_INC7 0x1f 318 #define CH7006_SUBC_INC7_0 0, 3:0 319 320 #define CH7006_PLL_CONTROL 0x20 321 #define CH7006_PLL_CONTROL_CPI (1 << 5) 322 #define CH7006_PLL_CONTROL_CAPACITOR (1 << 4) 323 #define CH7006_PLL_CONTROL_7STAGES (1 << 3) 324 #define CH7006_PLL_CONTROL_DIGITAL_5V (1 << 2) 325 #define CH7006_PLL_CONTROL_ANALOG_5V (1 << 1) 326 #define CH7006_PLL_CONTROL_MEMORY_5V (1 << 0) 327 328 #define CH7006_CALC_SUBC_INC0 0x21 329 #define CH7006_CALC_SUBC_INC0_24 24, 4:3 330 #define CH7006_CALC_SUBC_INC0_HYST 0, 2:1 331 #define CH7006_CALC_SUBC_INC0_AUTO (1 << 0) 332 333 #define CH7006_CALC_SUBC_INC1 0x22 334 #define CH7006_CALC_SUBC_INC1_16 16, 7:0 335 336 #define CH7006_CALC_SUBC_INC2 0x23 337 #define CH7006_CALC_SUBC_INC2_8 8, 7:0 338 339 #define CH7006_CALC_SUBC_INC3 0x24 340 #define CH7006_CALC_SUBC_INC3_0 0, 7:0 341 342 #define CH7006_VERSION_ID 0x25 343 344 #endif 345