1 /* 2 * Hisilicon Hi6220 SoC ADE(Advanced Display Engine)'s crtc&plane driver 3 * 4 * Copyright (c) 2016 Linaro Limited. 5 * Copyright (c) 2014-2016 Hisilicon Limited. 6 * 7 * Author: 8 * Xinliang Liu <z.liuxinliang@hisilicon.com> 9 * Xinliang Liu <xinliang.liu@linaro.org> 10 * Xinwei Kong <kong.kongxinwei@hisilicon.com> 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License version 2 as 14 * published by the Free Software Foundation. 15 * 16 */ 17 18 #include <linux/bitops.h> 19 #include <linux/clk.h> 20 #include <video/display_timing.h> 21 #include <linux/mfd/syscon.h> 22 #include <linux/regmap.h> 23 #include <linux/reset.h> 24 25 #include <drm/drmP.h> 26 #include <drm/drm_crtc.h> 27 #include <drm/drm_crtc_helper.h> 28 #include <drm/drm_atomic.h> 29 #include <drm/drm_atomic_helper.h> 30 #include <drm/drm_plane_helper.h> 31 #include <drm/drm_gem_cma_helper.h> 32 #include <drm/drm_fb_cma_helper.h> 33 34 #include "kirin_drm_drv.h" 35 #include "kirin_ade_reg.h" 36 37 #define PRIMARY_CH ADE_CH1 /* primary plane */ 38 #define OUT_OVLY ADE_OVLY2 /* output overlay compositor */ 39 #define ADE_DEBUG 1 40 41 #define to_ade_crtc(crtc) \ 42 container_of(crtc, struct ade_crtc, base) 43 44 #define to_ade_plane(plane) \ 45 container_of(plane, struct ade_plane, base) 46 47 struct ade_hw_ctx { 48 void __iomem *base; 49 struct regmap *noc_regmap; 50 struct clk *ade_core_clk; 51 struct clk *media_noc_clk; 52 struct clk *ade_pix_clk; 53 struct reset_control *reset; 54 bool power_on; 55 int irq; 56 }; 57 58 struct ade_crtc { 59 struct drm_crtc base; 60 struct ade_hw_ctx *ctx; 61 bool enable; 62 u32 out_format; 63 }; 64 65 struct ade_plane { 66 struct drm_plane base; 67 void *ctx; 68 u8 ch; /* channel */ 69 }; 70 71 struct ade_data { 72 struct ade_crtc acrtc; 73 struct ade_plane aplane[ADE_CH_NUM]; 74 struct ade_hw_ctx ctx; 75 }; 76 77 /* ade-format info: */ 78 struct ade_format { 79 u32 pixel_format; 80 enum ade_fb_format ade_format; 81 }; 82 83 static const struct ade_format ade_formats[] = { 84 /* 16bpp RGB: */ 85 { DRM_FORMAT_RGB565, ADE_RGB_565 }, 86 { DRM_FORMAT_BGR565, ADE_BGR_565 }, 87 /* 24bpp RGB: */ 88 { DRM_FORMAT_RGB888, ADE_RGB_888 }, 89 { DRM_FORMAT_BGR888, ADE_BGR_888 }, 90 /* 32bpp [A]RGB: */ 91 { DRM_FORMAT_XRGB8888, ADE_XRGB_8888 }, 92 { DRM_FORMAT_XBGR8888, ADE_XBGR_8888 }, 93 { DRM_FORMAT_RGBA8888, ADE_RGBA_8888 }, 94 { DRM_FORMAT_BGRA8888, ADE_BGRA_8888 }, 95 { DRM_FORMAT_ARGB8888, ADE_ARGB_8888 }, 96 { DRM_FORMAT_ABGR8888, ADE_ABGR_8888 }, 97 }; 98 99 static const u32 channel_formats1[] = { 100 /* channel 1,2,3,4 */ 101 DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, DRM_FORMAT_RGB888, 102 DRM_FORMAT_BGR888, DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888, 103 DRM_FORMAT_RGBA8888, DRM_FORMAT_BGRA8888, DRM_FORMAT_ARGB8888, 104 DRM_FORMAT_ABGR8888 105 }; 106 107 u32 ade_get_channel_formats(u8 ch, const u32 **formats) 108 { 109 switch (ch) { 110 case ADE_CH1: 111 *formats = channel_formats1; 112 return ARRAY_SIZE(channel_formats1); 113 default: 114 DRM_ERROR("no this channel %d\n", ch); 115 *formats = NULL; 116 return 0; 117 } 118 } 119 120 /* convert from fourcc format to ade format */ 121 static u32 ade_get_format(u32 pixel_format) 122 { 123 int i; 124 125 for (i = 0; i < ARRAY_SIZE(ade_formats); i++) 126 if (ade_formats[i].pixel_format == pixel_format) 127 return ade_formats[i].ade_format; 128 129 /* not found */ 130 DRM_ERROR("Not found pixel format!!fourcc_format= %d\n", 131 pixel_format); 132 return ADE_FORMAT_UNSUPPORT; 133 } 134 135 static void ade_update_reload_bit(void __iomem *base, u32 bit_num, u32 val) 136 { 137 u32 bit_ofst, reg_num; 138 139 bit_ofst = bit_num % 32; 140 reg_num = bit_num / 32; 141 142 ade_update_bits(base + ADE_RELOAD_DIS(reg_num), bit_ofst, 143 MASK(1), !!val); 144 } 145 146 static u32 ade_read_reload_bit(void __iomem *base, u32 bit_num) 147 { 148 u32 tmp, bit_ofst, reg_num; 149 150 bit_ofst = bit_num % 32; 151 reg_num = bit_num / 32; 152 153 tmp = readl(base + ADE_RELOAD_DIS(reg_num)); 154 return !!(BIT(bit_ofst) & tmp); 155 } 156 157 static void ade_init(struct ade_hw_ctx *ctx) 158 { 159 void __iomem *base = ctx->base; 160 161 /* enable clk gate */ 162 ade_update_bits(base + ADE_CTRL1, AUTO_CLK_GATE_EN_OFST, 163 AUTO_CLK_GATE_EN, ADE_ENABLE); 164 /* clear overlay */ 165 writel(0, base + ADE_OVLY1_TRANS_CFG); 166 writel(0, base + ADE_OVLY_CTL); 167 writel(0, base + ADE_OVLYX_CTL(OUT_OVLY)); 168 /* clear reset and reload regs */ 169 writel(MASK(32), base + ADE_SOFT_RST_SEL(0)); 170 writel(MASK(32), base + ADE_SOFT_RST_SEL(1)); 171 writel(MASK(32), base + ADE_RELOAD_DIS(0)); 172 writel(MASK(32), base + ADE_RELOAD_DIS(1)); 173 /* 174 * for video mode, all the ade registers should 175 * become effective at frame end. 176 */ 177 ade_update_bits(base + ADE_CTRL, FRM_END_START_OFST, 178 FRM_END_START_MASK, REG_EFFECTIVE_IN_ADEEN_FRMEND); 179 } 180 181 static void ade_set_pix_clk(struct ade_hw_ctx *ctx, 182 struct drm_display_mode *mode, 183 struct drm_display_mode *adj_mode) 184 { 185 u32 clk_Hz = mode->clock * 1000; 186 int ret; 187 188 /* 189 * Success should be guaranteed in mode_valid call back, 190 * so failure shouldn't happen here 191 */ 192 ret = clk_set_rate(ctx->ade_pix_clk, clk_Hz); 193 if (ret) 194 DRM_ERROR("failed to set pixel clk %dHz (%d)\n", clk_Hz, ret); 195 adj_mode->clock = clk_get_rate(ctx->ade_pix_clk) / 1000; 196 } 197 198 static void ade_ldi_set_mode(struct ade_crtc *acrtc, 199 struct drm_display_mode *mode, 200 struct drm_display_mode *adj_mode) 201 { 202 struct ade_hw_ctx *ctx = acrtc->ctx; 203 void __iomem *base = ctx->base; 204 u32 width = mode->hdisplay; 205 u32 height = mode->vdisplay; 206 u32 hfp, hbp, hsw, vfp, vbp, vsw; 207 u32 plr_flags; 208 209 plr_flags = (mode->flags & DRM_MODE_FLAG_NVSYNC) ? FLAG_NVSYNC : 0; 210 plr_flags |= (mode->flags & DRM_MODE_FLAG_NHSYNC) ? FLAG_NHSYNC : 0; 211 hfp = mode->hsync_start - mode->hdisplay; 212 hbp = mode->htotal - mode->hsync_end; 213 hsw = mode->hsync_end - mode->hsync_start; 214 vfp = mode->vsync_start - mode->vdisplay; 215 vbp = mode->vtotal - mode->vsync_end; 216 vsw = mode->vsync_end - mode->vsync_start; 217 if (vsw > 15) { 218 DRM_DEBUG_DRIVER("vsw exceeded 15\n"); 219 vsw = 15; 220 } 221 222 writel((hbp << HBP_OFST) | hfp, base + LDI_HRZ_CTRL0); 223 /* the configured value is actual value - 1 */ 224 writel(hsw - 1, base + LDI_HRZ_CTRL1); 225 writel((vbp << VBP_OFST) | vfp, base + LDI_VRT_CTRL0); 226 /* the configured value is actual value - 1 */ 227 writel(vsw - 1, base + LDI_VRT_CTRL1); 228 /* the configured value is actual value - 1 */ 229 writel(((height - 1) << VSIZE_OFST) | (width - 1), 230 base + LDI_DSP_SIZE); 231 writel(plr_flags, base + LDI_PLR_CTRL); 232 233 /* set overlay compositor output size */ 234 writel(((width - 1) << OUTPUT_XSIZE_OFST) | (height - 1), 235 base + ADE_OVLY_OUTPUT_SIZE(OUT_OVLY)); 236 237 /* ctran6 setting */ 238 writel(CTRAN_BYPASS_ON, base + ADE_CTRAN_DIS(ADE_CTRAN6)); 239 /* the configured value is actual value - 1 */ 240 writel(width * height - 1, base + ADE_CTRAN_IMAGE_SIZE(ADE_CTRAN6)); 241 ade_update_reload_bit(base, CTRAN_OFST + ADE_CTRAN6, 0); 242 243 ade_set_pix_clk(ctx, mode, adj_mode); 244 245 DRM_DEBUG_DRIVER("set mode: %dx%d\n", width, height); 246 } 247 248 static int ade_power_up(struct ade_hw_ctx *ctx) 249 { 250 int ret; 251 252 ret = clk_prepare_enable(ctx->media_noc_clk); 253 if (ret) { 254 DRM_ERROR("failed to enable media_noc_clk (%d)\n", ret); 255 return ret; 256 } 257 258 ret = reset_control_deassert(ctx->reset); 259 if (ret) { 260 DRM_ERROR("failed to deassert reset\n"); 261 return ret; 262 } 263 264 ret = clk_prepare_enable(ctx->ade_core_clk); 265 if (ret) { 266 DRM_ERROR("failed to enable ade_core_clk (%d)\n", ret); 267 return ret; 268 } 269 270 ade_init(ctx); 271 ctx->power_on = true; 272 return 0; 273 } 274 275 static void ade_power_down(struct ade_hw_ctx *ctx) 276 { 277 void __iomem *base = ctx->base; 278 279 writel(ADE_DISABLE, base + LDI_CTRL); 280 /* dsi pixel off */ 281 writel(DSI_PCLK_OFF, base + LDI_HDMI_DSI_GT); 282 283 clk_disable_unprepare(ctx->ade_core_clk); 284 reset_control_assert(ctx->reset); 285 clk_disable_unprepare(ctx->media_noc_clk); 286 ctx->power_on = false; 287 } 288 289 static void ade_set_medianoc_qos(struct ade_crtc *acrtc) 290 { 291 struct ade_hw_ctx *ctx = acrtc->ctx; 292 struct regmap *map = ctx->noc_regmap; 293 294 regmap_update_bits(map, ADE0_QOSGENERATOR_MODE, 295 QOSGENERATOR_MODE_MASK, BYPASS_MODE); 296 regmap_update_bits(map, ADE0_QOSGENERATOR_EXTCONTROL, 297 SOCKET_QOS_EN, SOCKET_QOS_EN); 298 299 regmap_update_bits(map, ADE1_QOSGENERATOR_MODE, 300 QOSGENERATOR_MODE_MASK, BYPASS_MODE); 301 regmap_update_bits(map, ADE1_QOSGENERATOR_EXTCONTROL, 302 SOCKET_QOS_EN, SOCKET_QOS_EN); 303 } 304 305 static int ade_enable_vblank(struct drm_device *dev, unsigned int pipe) 306 { 307 struct kirin_drm_private *priv = dev->dev_private; 308 struct ade_crtc *acrtc = to_ade_crtc(priv->crtc[pipe]); 309 struct ade_hw_ctx *ctx = acrtc->ctx; 310 void __iomem *base = ctx->base; 311 312 if (!ctx->power_on) 313 (void)ade_power_up(ctx); 314 315 ade_update_bits(base + LDI_INT_EN, FRAME_END_INT_EN_OFST, 316 MASK(1), 1); 317 318 return 0; 319 } 320 321 static void ade_disable_vblank(struct drm_device *dev, unsigned int pipe) 322 { 323 struct kirin_drm_private *priv = dev->dev_private; 324 struct ade_crtc *acrtc = to_ade_crtc(priv->crtc[pipe]); 325 struct ade_hw_ctx *ctx = acrtc->ctx; 326 void __iomem *base = ctx->base; 327 328 if (!ctx->power_on) { 329 DRM_ERROR("power is down! vblank disable fail\n"); 330 return; 331 } 332 333 ade_update_bits(base + LDI_INT_EN, FRAME_END_INT_EN_OFST, 334 MASK(1), 0); 335 } 336 337 static irqreturn_t ade_irq_handler(int irq, void *data) 338 { 339 struct ade_crtc *acrtc = data; 340 struct ade_hw_ctx *ctx = acrtc->ctx; 341 struct drm_crtc *crtc = &acrtc->base; 342 void __iomem *base = ctx->base; 343 u32 status; 344 345 status = readl(base + LDI_MSK_INT); 346 DRM_DEBUG_VBL("LDI IRQ: status=0x%X\n", status); 347 348 /* vblank irq */ 349 if (status & BIT(FRAME_END_INT_EN_OFST)) { 350 ade_update_bits(base + LDI_INT_CLR, FRAME_END_INT_EN_OFST, 351 MASK(1), 1); 352 drm_crtc_handle_vblank(crtc); 353 } 354 355 return IRQ_HANDLED; 356 } 357 358 static void ade_display_enable(struct ade_crtc *acrtc) 359 { 360 struct ade_hw_ctx *ctx = acrtc->ctx; 361 void __iomem *base = ctx->base; 362 u32 out_fmt = acrtc->out_format; 363 364 /* enable output overlay compositor */ 365 writel(ADE_ENABLE, base + ADE_OVLYX_CTL(OUT_OVLY)); 366 ade_update_reload_bit(base, OVLY_OFST + OUT_OVLY, 0); 367 368 /* display source setting */ 369 writel(DISP_SRC_OVLY2, base + ADE_DISP_SRC_CFG); 370 371 /* enable ade */ 372 writel(ADE_ENABLE, base + ADE_EN); 373 /* enable ldi */ 374 writel(NORMAL_MODE, base + LDI_WORK_MODE); 375 writel((out_fmt << BPP_OFST) | DATA_GATE_EN | LDI_EN, 376 base + LDI_CTRL); 377 /* dsi pixel on */ 378 writel(DSI_PCLK_ON, base + LDI_HDMI_DSI_GT); 379 } 380 381 #if ADE_DEBUG 382 static void ade_rdma_dump_regs(void __iomem *base, u32 ch) 383 { 384 u32 reg_ctrl, reg_addr, reg_size, reg_stride, reg_space, reg_en; 385 u32 val; 386 387 reg_ctrl = RD_CH_CTRL(ch); 388 reg_addr = RD_CH_ADDR(ch); 389 reg_size = RD_CH_SIZE(ch); 390 reg_stride = RD_CH_STRIDE(ch); 391 reg_space = RD_CH_SPACE(ch); 392 reg_en = RD_CH_EN(ch); 393 394 val = ade_read_reload_bit(base, RDMA_OFST + ch); 395 DRM_DEBUG_DRIVER("[rdma%d]: reload(%d)\n", ch + 1, val); 396 val = readl(base + reg_ctrl); 397 DRM_DEBUG_DRIVER("[rdma%d]: reg_ctrl(0x%08x)\n", ch + 1, val); 398 val = readl(base + reg_addr); 399 DRM_DEBUG_DRIVER("[rdma%d]: reg_addr(0x%08x)\n", ch + 1, val); 400 val = readl(base + reg_size); 401 DRM_DEBUG_DRIVER("[rdma%d]: reg_size(0x%08x)\n", ch + 1, val); 402 val = readl(base + reg_stride); 403 DRM_DEBUG_DRIVER("[rdma%d]: reg_stride(0x%08x)\n", ch + 1, val); 404 val = readl(base + reg_space); 405 DRM_DEBUG_DRIVER("[rdma%d]: reg_space(0x%08x)\n", ch + 1, val); 406 val = readl(base + reg_en); 407 DRM_DEBUG_DRIVER("[rdma%d]: reg_en(0x%08x)\n", ch + 1, val); 408 } 409 410 static void ade_clip_dump_regs(void __iomem *base, u32 ch) 411 { 412 u32 val; 413 414 val = ade_read_reload_bit(base, CLIP_OFST + ch); 415 DRM_DEBUG_DRIVER("[clip%d]: reload(%d)\n", ch + 1, val); 416 val = readl(base + ADE_CLIP_DISABLE(ch)); 417 DRM_DEBUG_DRIVER("[clip%d]: reg_clip_disable(0x%08x)\n", ch + 1, val); 418 val = readl(base + ADE_CLIP_SIZE0(ch)); 419 DRM_DEBUG_DRIVER("[clip%d]: reg_clip_size0(0x%08x)\n", ch + 1, val); 420 val = readl(base + ADE_CLIP_SIZE1(ch)); 421 DRM_DEBUG_DRIVER("[clip%d]: reg_clip_size1(0x%08x)\n", ch + 1, val); 422 } 423 424 static void ade_compositor_routing_dump_regs(void __iomem *base, u32 ch) 425 { 426 u8 ovly_ch = 0; /* TODO: Only primary plane now */ 427 u32 val; 428 429 val = readl(base + ADE_OVLY_CH_XY0(ovly_ch)); 430 DRM_DEBUG_DRIVER("[overlay ch%d]: reg_ch_xy0(0x%08x)\n", ovly_ch, val); 431 val = readl(base + ADE_OVLY_CH_XY1(ovly_ch)); 432 DRM_DEBUG_DRIVER("[overlay ch%d]: reg_ch_xy1(0x%08x)\n", ovly_ch, val); 433 val = readl(base + ADE_OVLY_CH_CTL(ovly_ch)); 434 DRM_DEBUG_DRIVER("[overlay ch%d]: reg_ch_ctl(0x%08x)\n", ovly_ch, val); 435 } 436 437 static void ade_dump_overlay_compositor_regs(void __iomem *base, u32 comp) 438 { 439 u32 val; 440 441 val = ade_read_reload_bit(base, OVLY_OFST + comp); 442 DRM_DEBUG_DRIVER("[overlay%d]: reload(%d)\n", comp + 1, val); 443 writel(ADE_ENABLE, base + ADE_OVLYX_CTL(comp)); 444 DRM_DEBUG_DRIVER("[overlay%d]: reg_ctl(0x%08x)\n", comp + 1, val); 445 val = readl(base + ADE_OVLY_CTL); 446 DRM_DEBUG_DRIVER("ovly_ctl(0x%08x)\n", val); 447 } 448 449 static void ade_dump_regs(void __iomem *base) 450 { 451 u32 i; 452 453 /* dump channel regs */ 454 for (i = 0; i < ADE_CH_NUM; i++) { 455 /* dump rdma regs */ 456 ade_rdma_dump_regs(base, i); 457 458 /* dump clip regs */ 459 ade_clip_dump_regs(base, i); 460 461 /* dump compositor routing regs */ 462 ade_compositor_routing_dump_regs(base, i); 463 } 464 465 /* dump overlay compositor regs */ 466 ade_dump_overlay_compositor_regs(base, OUT_OVLY); 467 } 468 #else 469 static void ade_dump_regs(void __iomem *base) { } 470 #endif 471 472 static void ade_crtc_enable(struct drm_crtc *crtc) 473 { 474 struct ade_crtc *acrtc = to_ade_crtc(crtc); 475 struct ade_hw_ctx *ctx = acrtc->ctx; 476 int ret; 477 478 if (acrtc->enable) 479 return; 480 481 if (!ctx->power_on) { 482 ret = ade_power_up(ctx); 483 if (ret) 484 return; 485 } 486 487 ade_set_medianoc_qos(acrtc); 488 ade_display_enable(acrtc); 489 ade_dump_regs(ctx->base); 490 acrtc->enable = true; 491 } 492 493 static void ade_crtc_disable(struct drm_crtc *crtc) 494 { 495 struct ade_crtc *acrtc = to_ade_crtc(crtc); 496 struct ade_hw_ctx *ctx = acrtc->ctx; 497 498 if (!acrtc->enable) 499 return; 500 501 ade_power_down(ctx); 502 acrtc->enable = false; 503 } 504 505 static int ade_crtc_atomic_check(struct drm_crtc *crtc, 506 struct drm_crtc_state *state) 507 { 508 /* do nothing */ 509 return 0; 510 } 511 512 static void ade_crtc_mode_set_nofb(struct drm_crtc *crtc) 513 { 514 struct ade_crtc *acrtc = to_ade_crtc(crtc); 515 struct ade_hw_ctx *ctx = acrtc->ctx; 516 struct drm_display_mode *mode = &crtc->state->mode; 517 struct drm_display_mode *adj_mode = &crtc->state->adjusted_mode; 518 519 if (!ctx->power_on) 520 (void)ade_power_up(ctx); 521 ade_ldi_set_mode(acrtc, mode, adj_mode); 522 } 523 524 static void ade_crtc_atomic_begin(struct drm_crtc *crtc, 525 struct drm_crtc_state *old_state) 526 { 527 struct ade_crtc *acrtc = to_ade_crtc(crtc); 528 struct ade_hw_ctx *ctx = acrtc->ctx; 529 530 if (!ctx->power_on) 531 (void)ade_power_up(ctx); 532 } 533 534 static void ade_crtc_atomic_flush(struct drm_crtc *crtc, 535 struct drm_crtc_state *old_state) 536 537 { 538 struct ade_crtc *acrtc = to_ade_crtc(crtc); 539 struct ade_hw_ctx *ctx = acrtc->ctx; 540 void __iomem *base = ctx->base; 541 542 /* only crtc is enabled regs take effect */ 543 if (acrtc->enable) { 544 ade_dump_regs(base); 545 /* flush ade registers */ 546 writel(ADE_ENABLE, base + ADE_EN); 547 } 548 } 549 550 static const struct drm_crtc_helper_funcs ade_crtc_helper_funcs = { 551 .enable = ade_crtc_enable, 552 .disable = ade_crtc_disable, 553 .atomic_check = ade_crtc_atomic_check, 554 .mode_set_nofb = ade_crtc_mode_set_nofb, 555 .atomic_begin = ade_crtc_atomic_begin, 556 .atomic_flush = ade_crtc_atomic_flush, 557 }; 558 559 static const struct drm_crtc_funcs ade_crtc_funcs = { 560 .destroy = drm_crtc_cleanup, 561 .set_config = drm_atomic_helper_set_config, 562 .page_flip = drm_atomic_helper_page_flip, 563 .reset = drm_atomic_helper_crtc_reset, 564 .set_property = drm_atomic_helper_crtc_set_property, 565 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 566 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 567 }; 568 569 static int ade_crtc_init(struct drm_device *dev, struct drm_crtc *crtc, 570 struct drm_plane *plane) 571 { 572 struct kirin_drm_private *priv = dev->dev_private; 573 struct device_node *port; 574 int ret; 575 576 /* set crtc port so that 577 * drm_of_find_possible_crtcs call works 578 */ 579 port = of_get_child_by_name(dev->dev->of_node, "port"); 580 if (!port) { 581 DRM_ERROR("no port node found in %s\n", 582 dev->dev->of_node->full_name); 583 return -EINVAL; 584 } 585 of_node_put(port); 586 crtc->port = port; 587 588 ret = drm_crtc_init_with_planes(dev, crtc, plane, NULL, 589 &ade_crtc_funcs, NULL); 590 if (ret) { 591 DRM_ERROR("failed to init crtc.\n"); 592 return ret; 593 } 594 595 drm_crtc_helper_add(crtc, &ade_crtc_helper_funcs); 596 priv->crtc[drm_crtc_index(crtc)] = crtc; 597 598 return 0; 599 } 600 601 static void ade_rdma_set(void __iomem *base, struct drm_framebuffer *fb, 602 u32 ch, u32 y, u32 in_h, u32 fmt) 603 { 604 struct drm_gem_cma_object *obj = drm_fb_cma_get_gem_obj(fb, 0); 605 u32 reg_ctrl, reg_addr, reg_size, reg_stride, reg_space, reg_en; 606 u32 stride = fb->pitches[0]; 607 u32 addr = (u32)obj->paddr + y * stride; 608 609 DRM_DEBUG_DRIVER("rdma%d: (y=%d, height=%d), stride=%d, paddr=0x%x\n", 610 ch + 1, y, in_h, stride, (u32)obj->paddr); 611 DRM_DEBUG_DRIVER("addr=0x%x, fb:%dx%d, pixel_format=%d(%s)\n", 612 addr, fb->width, fb->height, fmt, 613 drm_get_format_name(fb->pixel_format)); 614 615 /* get reg offset */ 616 reg_ctrl = RD_CH_CTRL(ch); 617 reg_addr = RD_CH_ADDR(ch); 618 reg_size = RD_CH_SIZE(ch); 619 reg_stride = RD_CH_STRIDE(ch); 620 reg_space = RD_CH_SPACE(ch); 621 reg_en = RD_CH_EN(ch); 622 623 /* 624 * TODO: set rotation 625 */ 626 writel((fmt << 16) & 0x1f0000, base + reg_ctrl); 627 writel(addr, base + reg_addr); 628 writel((in_h << 16) | stride, base + reg_size); 629 writel(stride, base + reg_stride); 630 writel(in_h * stride, base + reg_space); 631 writel(ADE_ENABLE, base + reg_en); 632 ade_update_reload_bit(base, RDMA_OFST + ch, 0); 633 } 634 635 static void ade_rdma_disable(void __iomem *base, u32 ch) 636 { 637 u32 reg_en; 638 639 /* get reg offset */ 640 reg_en = RD_CH_EN(ch); 641 writel(0, base + reg_en); 642 ade_update_reload_bit(base, RDMA_OFST + ch, 1); 643 } 644 645 static void ade_clip_set(void __iomem *base, u32 ch, u32 fb_w, u32 x, 646 u32 in_w, u32 in_h) 647 { 648 u32 disable_val; 649 u32 clip_left; 650 u32 clip_right; 651 652 /* 653 * clip width, no need to clip height 654 */ 655 if (fb_w == in_w) { /* bypass */ 656 disable_val = 1; 657 clip_left = 0; 658 clip_right = 0; 659 } else { 660 disable_val = 0; 661 clip_left = x; 662 clip_right = fb_w - (x + in_w) - 1; 663 } 664 665 DRM_DEBUG_DRIVER("clip%d: clip_left=%d, clip_right=%d\n", 666 ch + 1, clip_left, clip_right); 667 668 writel(disable_val, base + ADE_CLIP_DISABLE(ch)); 669 writel((fb_w - 1) << 16 | (in_h - 1), base + ADE_CLIP_SIZE0(ch)); 670 writel(clip_left << 16 | clip_right, base + ADE_CLIP_SIZE1(ch)); 671 ade_update_reload_bit(base, CLIP_OFST + ch, 0); 672 } 673 674 static void ade_clip_disable(void __iomem *base, u32 ch) 675 { 676 writel(1, base + ADE_CLIP_DISABLE(ch)); 677 ade_update_reload_bit(base, CLIP_OFST + ch, 1); 678 } 679 680 static bool has_Alpha_channel(int format) 681 { 682 switch (format) { 683 case ADE_ARGB_8888: 684 case ADE_ABGR_8888: 685 case ADE_RGBA_8888: 686 case ADE_BGRA_8888: 687 return true; 688 default: 689 return false; 690 } 691 } 692 693 static void ade_get_blending_params(u32 fmt, u8 glb_alpha, u8 *alp_mode, 694 u8 *alp_sel, u8 *under_alp_sel) 695 { 696 bool has_alpha = has_Alpha_channel(fmt); 697 698 /* 699 * get alp_mode 700 */ 701 if (has_alpha && glb_alpha < 255) 702 *alp_mode = ADE_ALP_PIXEL_AND_GLB; 703 else if (has_alpha) 704 *alp_mode = ADE_ALP_PIXEL; 705 else 706 *alp_mode = ADE_ALP_GLOBAL; 707 708 /* 709 * get alp sel 710 */ 711 *alp_sel = ADE_ALP_MUL_COEFF_3; /* 1 */ 712 *under_alp_sel = ADE_ALP_MUL_COEFF_2; /* 0 */ 713 } 714 715 static void ade_compositor_routing_set(void __iomem *base, u8 ch, 716 u32 x0, u32 y0, 717 u32 in_w, u32 in_h, u32 fmt) 718 { 719 u8 ovly_ch = 0; /* TODO: This is the zpos, only one plane now */ 720 u8 glb_alpha = 255; 721 u32 x1 = x0 + in_w - 1; 722 u32 y1 = y0 + in_h - 1; 723 u32 val; 724 u8 alp_sel; 725 u8 under_alp_sel; 726 u8 alp_mode; 727 728 ade_get_blending_params(fmt, glb_alpha, &alp_mode, &alp_sel, 729 &under_alp_sel); 730 731 /* overlay routing setting 732 */ 733 writel(x0 << 16 | y0, base + ADE_OVLY_CH_XY0(ovly_ch)); 734 writel(x1 << 16 | y1, base + ADE_OVLY_CH_XY1(ovly_ch)); 735 val = (ch + 1) << CH_SEL_OFST | BIT(CH_EN_OFST) | 736 alp_sel << CH_ALP_SEL_OFST | 737 under_alp_sel << CH_UNDER_ALP_SEL_OFST | 738 glb_alpha << CH_ALP_GBL_OFST | 739 alp_mode << CH_ALP_MODE_OFST; 740 writel(val, base + ADE_OVLY_CH_CTL(ovly_ch)); 741 /* connect this plane/channel to overlay2 compositor */ 742 ade_update_bits(base + ADE_OVLY_CTL, CH_OVLY_SEL_OFST(ovly_ch), 743 CH_OVLY_SEL_MASK, CH_OVLY_SEL_VAL(OUT_OVLY)); 744 } 745 746 static void ade_compositor_routing_disable(void __iomem *base, u32 ch) 747 { 748 u8 ovly_ch = 0; /* TODO: Only primary plane now */ 749 750 /* disable this plane/channel */ 751 ade_update_bits(base + ADE_OVLY_CH_CTL(ovly_ch), CH_EN_OFST, 752 MASK(1), 0); 753 /* dis-connect this plane/channel of overlay2 compositor */ 754 ade_update_bits(base + ADE_OVLY_CTL, CH_OVLY_SEL_OFST(ovly_ch), 755 CH_OVLY_SEL_MASK, 0); 756 } 757 758 /* 759 * Typicaly, a channel looks like: DMA-->clip-->scale-->ctrans-->compositor 760 */ 761 static void ade_update_channel(struct ade_plane *aplane, 762 struct drm_framebuffer *fb, int crtc_x, 763 int crtc_y, unsigned int crtc_w, 764 unsigned int crtc_h, u32 src_x, 765 u32 src_y, u32 src_w, u32 src_h) 766 { 767 struct ade_hw_ctx *ctx = aplane->ctx; 768 void __iomem *base = ctx->base; 769 u32 fmt = ade_get_format(fb->pixel_format); 770 u32 ch = aplane->ch; 771 u32 in_w; 772 u32 in_h; 773 774 DRM_DEBUG_DRIVER("channel%d: src:(%d, %d)-%dx%d, crtc:(%d, %d)-%dx%d", 775 ch + 1, src_x, src_y, src_w, src_h, 776 crtc_x, crtc_y, crtc_w, crtc_h); 777 778 /* 1) DMA setting */ 779 in_w = src_w; 780 in_h = src_h; 781 ade_rdma_set(base, fb, ch, src_y, in_h, fmt); 782 783 /* 2) clip setting */ 784 ade_clip_set(base, ch, fb->width, src_x, in_w, in_h); 785 786 /* 3) TODO: scale setting for overlay planes */ 787 788 /* 4) TODO: ctran/csc setting for overlay planes */ 789 790 /* 5) compositor routing setting */ 791 ade_compositor_routing_set(base, ch, crtc_x, crtc_y, in_w, in_h, fmt); 792 } 793 794 static void ade_disable_channel(struct ade_plane *aplane) 795 { 796 struct ade_hw_ctx *ctx = aplane->ctx; 797 void __iomem *base = ctx->base; 798 u32 ch = aplane->ch; 799 800 DRM_DEBUG_DRIVER("disable channel%d\n", ch + 1); 801 802 /* disable read DMA */ 803 ade_rdma_disable(base, ch); 804 805 /* disable clip */ 806 ade_clip_disable(base, ch); 807 808 /* disable compositor routing */ 809 ade_compositor_routing_disable(base, ch); 810 } 811 812 static int ade_plane_prepare_fb(struct drm_plane *plane, 813 const struct drm_plane_state *new_state) 814 { 815 /* do nothing */ 816 return 0; 817 } 818 819 static void ade_plane_cleanup_fb(struct drm_plane *plane, 820 const struct drm_plane_state *old_state) 821 { 822 /* do nothing */ 823 } 824 825 static int ade_plane_atomic_check(struct drm_plane *plane, 826 struct drm_plane_state *state) 827 { 828 struct drm_framebuffer *fb = state->fb; 829 struct drm_crtc *crtc = state->crtc; 830 struct drm_crtc_state *crtc_state; 831 u32 src_x = state->src_x >> 16; 832 u32 src_y = state->src_y >> 16; 833 u32 src_w = state->src_w >> 16; 834 u32 src_h = state->src_h >> 16; 835 int crtc_x = state->crtc_x; 836 int crtc_y = state->crtc_y; 837 u32 crtc_w = state->crtc_w; 838 u32 crtc_h = state->crtc_h; 839 u32 fmt; 840 841 if (!crtc || !fb) 842 return 0; 843 844 fmt = ade_get_format(fb->pixel_format); 845 if (fmt == ADE_FORMAT_UNSUPPORT) 846 return -EINVAL; 847 848 crtc_state = drm_atomic_get_crtc_state(state->state, crtc); 849 if (IS_ERR(crtc_state)) 850 return PTR_ERR(crtc_state); 851 852 if (src_w != crtc_w || src_h != crtc_h) { 853 DRM_ERROR("Scale not support!!!\n"); 854 return -EINVAL; 855 } 856 857 if (src_x + src_w > fb->width || 858 src_y + src_h > fb->height) 859 return -EINVAL; 860 861 if (crtc_x < 0 || crtc_y < 0) 862 return -EINVAL; 863 864 if (crtc_x + crtc_w > crtc_state->adjusted_mode.hdisplay || 865 crtc_y + crtc_h > crtc_state->adjusted_mode.vdisplay) 866 return -EINVAL; 867 868 return 0; 869 } 870 871 static void ade_plane_atomic_update(struct drm_plane *plane, 872 struct drm_plane_state *old_state) 873 { 874 struct drm_plane_state *state = plane->state; 875 struct ade_plane *aplane = to_ade_plane(plane); 876 877 ade_update_channel(aplane, state->fb, state->crtc_x, state->crtc_y, 878 state->crtc_w, state->crtc_h, 879 state->src_x >> 16, state->src_y >> 16, 880 state->src_w >> 16, state->src_h >> 16); 881 } 882 883 static void ade_plane_atomic_disable(struct drm_plane *plane, 884 struct drm_plane_state *old_state) 885 { 886 struct ade_plane *aplane = to_ade_plane(plane); 887 888 ade_disable_channel(aplane); 889 } 890 891 static const struct drm_plane_helper_funcs ade_plane_helper_funcs = { 892 .prepare_fb = ade_plane_prepare_fb, 893 .cleanup_fb = ade_plane_cleanup_fb, 894 .atomic_check = ade_plane_atomic_check, 895 .atomic_update = ade_plane_atomic_update, 896 .atomic_disable = ade_plane_atomic_disable, 897 }; 898 899 static struct drm_plane_funcs ade_plane_funcs = { 900 .update_plane = drm_atomic_helper_update_plane, 901 .disable_plane = drm_atomic_helper_disable_plane, 902 .set_property = drm_atomic_helper_plane_set_property, 903 .destroy = drm_plane_cleanup, 904 .reset = drm_atomic_helper_plane_reset, 905 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 906 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 907 }; 908 909 static int ade_plane_init(struct drm_device *dev, struct ade_plane *aplane, 910 enum drm_plane_type type) 911 { 912 const u32 *fmts; 913 u32 fmts_cnt; 914 int ret = 0; 915 916 /* get properties */ 917 fmts_cnt = ade_get_channel_formats(aplane->ch, &fmts); 918 if (ret) 919 return ret; 920 921 ret = drm_universal_plane_init(dev, &aplane->base, 1, &ade_plane_funcs, 922 fmts, fmts_cnt, type, NULL); 923 if (ret) { 924 DRM_ERROR("fail to init plane, ch=%d\n", aplane->ch); 925 return ret; 926 } 927 928 drm_plane_helper_add(&aplane->base, &ade_plane_helper_funcs); 929 930 return 0; 931 } 932 933 static int ade_dts_parse(struct platform_device *pdev, struct ade_hw_ctx *ctx) 934 { 935 struct resource *res; 936 struct device *dev = &pdev->dev; 937 struct device_node *np = pdev->dev.of_node; 938 939 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 940 ctx->base = devm_ioremap_resource(dev, res); 941 if (IS_ERR(ctx->base)) { 942 DRM_ERROR("failed to remap ade io base\n"); 943 return PTR_ERR(ctx->base); 944 } 945 946 ctx->reset = devm_reset_control_get(dev, NULL); 947 if (IS_ERR(ctx->reset)) 948 return PTR_ERR(ctx->reset); 949 950 ctx->noc_regmap = 951 syscon_regmap_lookup_by_phandle(np, "hisilicon,noc-syscon"); 952 if (IS_ERR(ctx->noc_regmap)) { 953 DRM_ERROR("failed to get noc regmap\n"); 954 return PTR_ERR(ctx->noc_regmap); 955 } 956 957 ctx->irq = platform_get_irq(pdev, 0); 958 if (ctx->irq < 0) { 959 DRM_ERROR("failed to get irq\n"); 960 return -ENODEV; 961 } 962 963 ctx->ade_core_clk = devm_clk_get(dev, "clk_ade_core"); 964 if (!ctx->ade_core_clk) { 965 DRM_ERROR("failed to parse clk ADE_CORE\n"); 966 return -ENODEV; 967 } 968 969 ctx->media_noc_clk = devm_clk_get(dev, "clk_codec_jpeg"); 970 if (!ctx->media_noc_clk) { 971 DRM_ERROR("failed to parse clk CODEC_JPEG\n"); 972 return -ENODEV; 973 } 974 975 ctx->ade_pix_clk = devm_clk_get(dev, "clk_ade_pix"); 976 if (!ctx->ade_pix_clk) { 977 DRM_ERROR("failed to parse clk ADE_PIX\n"); 978 return -ENODEV; 979 } 980 981 return 0; 982 } 983 984 static int ade_drm_init(struct drm_device *dev) 985 { 986 struct platform_device *pdev = dev->platformdev; 987 struct ade_data *ade; 988 struct ade_hw_ctx *ctx; 989 struct ade_crtc *acrtc; 990 struct ade_plane *aplane; 991 enum drm_plane_type type; 992 int ret; 993 int i; 994 995 ade = devm_kzalloc(dev->dev, sizeof(*ade), GFP_KERNEL); 996 if (!ade) { 997 DRM_ERROR("failed to alloc ade_data\n"); 998 return -ENOMEM; 999 } 1000 platform_set_drvdata(pdev, ade); 1001 1002 ctx = &ade->ctx; 1003 acrtc = &ade->acrtc; 1004 acrtc->ctx = ctx; 1005 acrtc->out_format = LDI_OUT_RGB_888; 1006 1007 ret = ade_dts_parse(pdev, ctx); 1008 if (ret) 1009 return ret; 1010 1011 /* 1012 * plane init 1013 * TODO: Now only support primary plane, overlay planes 1014 * need to do. 1015 */ 1016 for (i = 0; i < ADE_CH_NUM; i++) { 1017 aplane = &ade->aplane[i]; 1018 aplane->ch = i; 1019 aplane->ctx = ctx; 1020 type = i == PRIMARY_CH ? DRM_PLANE_TYPE_PRIMARY : 1021 DRM_PLANE_TYPE_OVERLAY; 1022 1023 ret = ade_plane_init(dev, aplane, type); 1024 if (ret) 1025 return ret; 1026 } 1027 1028 /* crtc init */ 1029 ret = ade_crtc_init(dev, &acrtc->base, &ade->aplane[PRIMARY_CH].base); 1030 if (ret) 1031 return ret; 1032 1033 /* vblank irq init */ 1034 ret = devm_request_irq(dev->dev, ctx->irq, ade_irq_handler, 1035 IRQF_SHARED, dev->driver->name, acrtc); 1036 if (ret) 1037 return ret; 1038 dev->driver->get_vblank_counter = drm_vblank_no_hw_counter; 1039 dev->driver->enable_vblank = ade_enable_vblank; 1040 dev->driver->disable_vblank = ade_disable_vblank; 1041 1042 return 0; 1043 } 1044 1045 static void ade_drm_cleanup(struct drm_device *dev) 1046 { 1047 struct platform_device *pdev = dev->platformdev; 1048 struct ade_data *ade = platform_get_drvdata(pdev); 1049 struct drm_crtc *crtc = &ade->acrtc.base; 1050 1051 drm_crtc_cleanup(crtc); 1052 } 1053 1054 const struct kirin_dc_ops ade_dc_ops = { 1055 .init = ade_drm_init, 1056 .cleanup = ade_drm_cleanup 1057 }; 1058