1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* Hisilicon Hibmc SoC drm driver 3 * 4 * Based on the bochs drm driver. 5 * 6 * Copyright (c) 2016 Huawei Limited. 7 * 8 * Author: 9 * Rongrong Zou <zourongrong@huawei.com> 10 * Rongrong Zou <zourongrong@gmail.com> 11 * Jianhua Li <lijianhua@huawei.com> 12 */ 13 14 #ifndef HIBMC_DRM_HW_H 15 #define HIBMC_DRM_HW_H 16 17 /* register definition */ 18 #define HIBMC_MISC_CTRL 0x4 19 20 #define HIBMC_MSCCTL_LOCALMEM_RESET(x) ((x) << 6) 21 #define HIBMC_MSCCTL_LOCALMEM_RESET_MASK 0x40 22 23 #define HIBMC_CURRENT_GATE 0x000040 24 #define HIBMC_CURR_GATE_DISPLAY(x) ((x) << 2) 25 #define HIBMC_CURR_GATE_DISPLAY_MASK 0x4 26 27 #define HIBMC_CURR_GATE_LOCALMEM(x) ((x) << 1) 28 #define HIBMC_CURR_GATE_LOCALMEM_MASK 0x2 29 30 #define HIBMC_MODE0_GATE 0x000044 31 #define HIBMC_MODE1_GATE 0x000048 32 #define HIBMC_POWER_MODE_CTRL 0x00004C 33 34 #define HIBMC_PW_MODE_CTL_OSC_INPUT(x) ((x) << 3) 35 #define HIBMC_PW_MODE_CTL_OSC_INPUT_MASK 0x8 36 37 #define HIBMC_PW_MODE_CTL_MODE(x) ((x) << 0) 38 #define HIBMC_PW_MODE_CTL_MODE_MASK 0x03 39 #define HIBMC_PW_MODE_CTL_MODE_SHIFT 0 40 41 #define HIBMC_PW_MODE_CTL_MODE_MODE0 0 42 #define HIBMC_PW_MODE_CTL_MODE_MODE1 1 43 #define HIBMC_PW_MODE_CTL_MODE_SLEEP 2 44 45 #define HIBMC_PANEL_PLL_CTRL 0x00005C 46 #define HIBMC_CRT_PLL_CTRL 0x000060 47 48 #define HIBMC_PLL_CTRL_BYPASS(x) ((x) << 18) 49 #define HIBMC_PLL_CTRL_BYPASS_MASK 0x40000 50 51 #define HIBMC_PLL_CTRL_POWER(x) ((x) << 17) 52 #define HIBMC_PLL_CTRL_POWER_MASK 0x20000 53 54 #define HIBMC_PLL_CTRL_INPUT(x) ((x) << 16) 55 #define HIBMC_PLL_CTRL_INPUT_MASK 0x10000 56 57 #define HIBMC_PLL_CTRL_POD(x) ((x) << 14) 58 #define HIBMC_PLL_CTRL_POD_MASK 0xC000 59 60 #define HIBMC_PLL_CTRL_OD(x) ((x) << 12) 61 #define HIBMC_PLL_CTRL_OD_MASK 0x3000 62 63 #define HIBMC_PLL_CTRL_N(x) ((x) << 8) 64 #define HIBMC_PLL_CTRL_N_MASK 0xF00 65 66 #define HIBMC_PLL_CTRL_M(x) ((x) << 0) 67 #define HIBMC_PLL_CTRL_M_MASK 0xFF 68 69 #define HIBMC_CRT_DISP_CTL 0x80200 70 71 #define HIBMC_CRT_DISP_CTL_DPMS(x) ((x) << 30) 72 #define HIBMC_CRT_DISP_CTL_DPMS_MASK 0xc0000000 73 74 #define HIBMC_CRT_DPMS_ON 0 75 #define HIBMC_CRT_DPMS_OFF 3 76 77 #define HIBMC_CRT_DISP_CTL_CRTSELECT(x) ((x) << 25) 78 #define HIBMC_CRT_DISP_CTL_CRTSELECT_MASK 0x2000000 79 80 #define HIBMC_CRTSELECT_CRT 1 81 82 #define HIBMC_CRT_DISP_CTL_CLOCK_PHASE(x) ((x) << 14) 83 #define HIBMC_CRT_DISP_CTL_CLOCK_PHASE_MASK 0x4000 84 85 #define HIBMC_CRT_DISP_CTL_VSYNC_PHASE(x) ((x) << 13) 86 #define HIBMC_CRT_DISP_CTL_VSYNC_PHASE_MASK 0x2000 87 88 #define HIBMC_CRT_DISP_CTL_HSYNC_PHASE(x) ((x) << 12) 89 #define HIBMC_CRT_DISP_CTL_HSYNC_PHASE_MASK 0x1000 90 91 #define HIBMC_CRT_DISP_CTL_TIMING(x) ((x) << 8) 92 #define HIBMC_CRT_DISP_CTL_TIMING_MASK 0x100 93 94 #define HIBMC_CTL_DISP_CTL_GAMMA(x) ((x) << 3) 95 #define HIBMC_CTL_DISP_CTL_GAMMA_MASK 0x08 96 97 #define HIBMC_CRT_DISP_CTL_PLANE(x) ((x) << 2) 98 #define HIBMC_CRT_DISP_CTL_PLANE_MASK 4 99 100 #define HIBMC_CRT_DISP_CTL_FORMAT(x) ((x) << 0) 101 #define HIBMC_CRT_DISP_CTL_FORMAT_MASK 0x03 102 103 #define HIBMC_CRT_FB_ADDRESS 0x080204 104 105 #define HIBMC_CRT_FB_WIDTH 0x080208 106 #define HIBMC_CRT_FB_WIDTH_WIDTH(x) ((x) << 16) 107 #define HIBMC_CRT_FB_WIDTH_WIDTH_MASK 0x3FFF0000 108 #define HIBMC_CRT_FB_WIDTH_OFFS(x) ((x) << 0) 109 #define HIBMC_CRT_FB_WIDTH_OFFS_MASK 0x3FFF 110 111 #define HIBMC_CRT_HORZ_TOTAL 0x08020C 112 #define HIBMC_CRT_HORZ_TOTAL_TOTAL(x) ((x) << 16) 113 #define HIBMC_CRT_HORZ_TOTAL_TOTAL_MASK 0xFFF0000 114 115 #define HIBMC_CRT_HORZ_TOTAL_DISP_END(x) ((x) << 0) 116 #define HIBMC_CRT_HORZ_TOTAL_DISP_END_MASK 0xFFF 117 118 #define HIBMC_CRT_HORZ_SYNC 0x080210 119 #define HIBMC_CRT_HORZ_SYNC_WIDTH(x) ((x) << 16) 120 #define HIBMC_CRT_HORZ_SYNC_WIDTH_MASK 0xFF0000 121 122 #define HIBMC_CRT_HORZ_SYNC_START(x) ((x) << 0) 123 #define HIBMC_CRT_HORZ_SYNC_START_MASK 0xFFF 124 125 #define HIBMC_CRT_VERT_TOTAL 0x080214 126 #define HIBMC_CRT_VERT_TOTAL_TOTAL(x) ((x) << 16) 127 #define HIBMC_CRT_VERT_TOTAL_TOTAL_MASK 0x7FFF0000 128 129 #define HIBMC_CRT_VERT_TOTAL_DISP_END(x) ((x) << 0) 130 #define HIBMC_CRT_VERT_TOTAL_DISP_END_MASK 0x7FF 131 132 #define HIBMC_CRT_VERT_SYNC 0x080218 133 #define HIBMC_CRT_VERT_SYNC_HEIGHT(x) ((x) << 16) 134 #define HIBMC_CRT_VERT_SYNC_HEIGHT_MASK 0x3F0000 135 136 #define HIBMC_CRT_VERT_SYNC_START(x) ((x) << 0) 137 #define HIBMC_CRT_VERT_SYNC_START_MASK 0x7FF 138 139 /* Auto Centering */ 140 #define HIBMC_CRT_AUTO_CENTERING_TL 0x080280 141 #define HIBMC_CRT_AUTO_CENTERING_TL_TOP(x) ((x) << 16) 142 #define HIBMC_CRT_AUTO_CENTERING_TL_TOP_MASK 0x7FF0000 143 144 #define HIBMC_CRT_AUTO_CENTERING_TL_LEFT(x) ((x) << 0) 145 #define HIBMC_CRT_AUTO_CENTERING_TL_LEFT_MASK 0x7FF 146 147 #define HIBMC_CRT_AUTO_CENTERING_BR 0x080284 148 #define HIBMC_CRT_AUTO_CENTERING_BR_BOTTOM(x) ((x) << 16) 149 #define HIBMC_CRT_AUTO_CENTERING_BR_BOTTOM_MASK 0x7FF0000 150 151 #define HIBMC_CRT_AUTO_CENTERING_BR_RIGHT(x) ((x) << 0) 152 #define HIBMC_CRT_AUTO_CENTERING_BR_RIGHT_MASK 0x7FF 153 154 /* register to control panel output */ 155 #define HIBMC_DISPLAY_CONTROL_HISILE 0x80288 156 #define HIBMC_DISPLAY_CONTROL_FPVDDEN(x) ((x) << 0) 157 #define HIBMC_DISPLAY_CONTROL_PANELDATE(x) ((x) << 1) 158 #define HIBMC_DISPLAY_CONTROL_FPEN(x) ((x) << 2) 159 #define HIBMC_DISPLAY_CONTROL_VBIASEN(x) ((x) << 3) 160 161 #define HIBMC_RAW_INTERRUPT 0x80290 162 #define HIBMC_RAW_INTERRUPT_VBLANK(x) ((x) << 2) 163 #define HIBMC_RAW_INTERRUPT_VBLANK_MASK 0x4 164 165 #define HIBMC_RAW_INTERRUPT_EN 0x80298 166 #define HIBMC_RAW_INTERRUPT_EN_VBLANK(x) ((x) << 2) 167 #define HIBMC_RAW_INTERRUPT_EN_VBLANK_MASK 0x4 168 169 /* register and values for PLL control */ 170 #define CRT_PLL1_HS 0x802a8 171 #define CRT_PLL1_HS_OUTER_BYPASS(x) ((x) << 30) 172 #define CRT_PLL1_HS_INTER_BYPASS(x) ((x) << 29) 173 #define CRT_PLL1_HS_POWERON(x) ((x) << 24) 174 175 #define CRT_PLL1_HS_25MHZ 0x23d40f02 176 #define CRT_PLL1_HS_40MHZ 0x23940801 177 #define CRT_PLL1_HS_65MHZ 0x23940d01 178 #define CRT_PLL1_HS_78MHZ 0x23540F82 179 #define CRT_PLL1_HS_74MHZ 0x23941dc2 180 #define CRT_PLL1_HS_80MHZ 0x23941001 181 #define CRT_PLL1_HS_80MHZ_1152 0x23540fc2 182 #define CRT_PLL1_HS_106MHZ 0x237C1641 183 #define CRT_PLL1_HS_108MHZ 0x23b41b01 184 #define CRT_PLL1_HS_162MHZ 0x23480681 185 #define CRT_PLL1_HS_148MHZ 0x23541dc2 186 #define CRT_PLL1_HS_193MHZ 0x234807c1 187 188 #define CRT_PLL2_HS 0x802ac 189 #define CRT_PLL2_HS_25MHZ 0x206B851E 190 #define CRT_PLL2_HS_40MHZ 0x30000000 191 #define CRT_PLL2_HS_65MHZ 0x40000000 192 #define CRT_PLL2_HS_78MHZ 0x50E147AE 193 #define CRT_PLL2_HS_74MHZ 0x602B6AE7 194 #define CRT_PLL2_HS_80MHZ 0x70000000 195 #define CRT_PLL2_HS_106MHZ 0x0075c28f 196 #define CRT_PLL2_HS_108MHZ 0x80000000 197 #define CRT_PLL2_HS_162MHZ 0xA0000000 198 #define CRT_PLL2_HS_148MHZ 0xB0CCCCCD 199 #define CRT_PLL2_HS_193MHZ 0xC0872B02 200 201 #define HIBMC_CRT_PALETTE 0x80C00 202 203 #define HIBMC_FIELD(field, value) (field(value) & field##_MASK) 204 #endif 205