1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* Hisilicon Hibmc SoC drm driver 3 * 4 * Based on the bochs drm driver. 5 * 6 * Copyright (c) 2016 Huawei Limited. 7 * 8 * Author: 9 * Rongrong Zou <zourongrong@huawei.com> 10 * Rongrong Zou <zourongrong@gmail.com> 11 * Jianhua Li <lijianhua@huawei.com> 12 */ 13 14 #include <linux/aperture.h> 15 #include <linux/module.h> 16 #include <linux/pci.h> 17 18 #include <drm/drm_atomic_helper.h> 19 #include <drm/drm_client_setup.h> 20 #include <drm/drm_drv.h> 21 #include <drm/drm_fbdev_ttm.h> 22 #include <drm/drm_gem_framebuffer_helper.h> 23 #include <drm/drm_gem_vram_helper.h> 24 #include <drm/drm_managed.h> 25 #include <drm/drm_module.h> 26 #include <drm/drm_vblank.h> 27 28 #include "hibmc_drm_drv.h" 29 #include "hibmc_drm_regs.h" 30 31 DEFINE_DRM_GEM_FOPS(hibmc_fops); 32 33 static irqreturn_t hibmc_interrupt(int irq, void *arg) 34 { 35 struct drm_device *dev = (struct drm_device *)arg; 36 struct hibmc_drm_private *priv = to_hibmc_drm_private(dev); 37 u32 status; 38 39 status = readl(priv->mmio + HIBMC_RAW_INTERRUPT); 40 41 if (status & HIBMC_RAW_INTERRUPT_VBLANK(1)) { 42 writel(HIBMC_RAW_INTERRUPT_VBLANK(1), 43 priv->mmio + HIBMC_RAW_INTERRUPT); 44 drm_handle_vblank(dev, 0); 45 } 46 47 return IRQ_HANDLED; 48 } 49 50 static int hibmc_dumb_create(struct drm_file *file, struct drm_device *dev, 51 struct drm_mode_create_dumb *args) 52 { 53 return drm_gem_vram_fill_create_dumb(file, dev, 0, 128, args); 54 } 55 56 static const struct drm_driver hibmc_driver = { 57 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC, 58 .fops = &hibmc_fops, 59 .name = "hibmc", 60 .date = "20160828", 61 .desc = "hibmc drm driver", 62 .major = 1, 63 .minor = 0, 64 .debugfs_init = drm_vram_mm_debugfs_init, 65 .dumb_create = hibmc_dumb_create, 66 .dumb_map_offset = drm_gem_ttm_dumb_map_offset, 67 DRM_FBDEV_TTM_DRIVER_OPS, 68 }; 69 70 static int __maybe_unused hibmc_pm_suspend(struct device *dev) 71 { 72 struct drm_device *drm_dev = dev_get_drvdata(dev); 73 74 return drm_mode_config_helper_suspend(drm_dev); 75 } 76 77 static int __maybe_unused hibmc_pm_resume(struct device *dev) 78 { 79 struct drm_device *drm_dev = dev_get_drvdata(dev); 80 81 return drm_mode_config_helper_resume(drm_dev); 82 } 83 84 static const struct dev_pm_ops hibmc_pm_ops = { 85 SET_SYSTEM_SLEEP_PM_OPS(hibmc_pm_suspend, 86 hibmc_pm_resume) 87 }; 88 89 static const struct drm_mode_config_funcs hibmc_mode_funcs = { 90 .mode_valid = drm_vram_helper_mode_valid, 91 .atomic_check = drm_atomic_helper_check, 92 .atomic_commit = drm_atomic_helper_commit, 93 .fb_create = drm_gem_fb_create, 94 }; 95 96 static int hibmc_kms_init(struct hibmc_drm_private *priv) 97 { 98 struct drm_device *dev = &priv->dev; 99 int ret; 100 101 ret = drmm_mode_config_init(dev); 102 if (ret) 103 return ret; 104 105 dev->mode_config.min_width = 0; 106 dev->mode_config.min_height = 0; 107 dev->mode_config.max_width = 1920; 108 dev->mode_config.max_height = 1200; 109 110 dev->mode_config.preferred_depth = 24; 111 dev->mode_config.prefer_shadow = 1; 112 113 dev->mode_config.funcs = (void *)&hibmc_mode_funcs; 114 115 ret = hibmc_de_init(priv); 116 if (ret) { 117 drm_err(dev, "failed to init de: %d\n", ret); 118 return ret; 119 } 120 121 ret = hibmc_vdac_init(priv); 122 if (ret) { 123 drm_err(dev, "failed to init vdac: %d\n", ret); 124 return ret; 125 } 126 127 return 0; 128 } 129 130 /* 131 * It can operate in one of three modes: 0, 1 or Sleep. 132 */ 133 void hibmc_set_power_mode(struct hibmc_drm_private *priv, u32 power_mode) 134 { 135 u32 control_value = 0; 136 void __iomem *mmio = priv->mmio; 137 u32 input = 1; 138 139 if (power_mode > HIBMC_PW_MODE_CTL_MODE_SLEEP) 140 return; 141 142 if (power_mode == HIBMC_PW_MODE_CTL_MODE_SLEEP) 143 input = 0; 144 145 control_value = readl(mmio + HIBMC_POWER_MODE_CTRL); 146 control_value &= ~(HIBMC_PW_MODE_CTL_MODE_MASK | 147 HIBMC_PW_MODE_CTL_OSC_INPUT_MASK); 148 control_value |= HIBMC_FIELD(HIBMC_PW_MODE_CTL_MODE, power_mode); 149 control_value |= HIBMC_FIELD(HIBMC_PW_MODE_CTL_OSC_INPUT, input); 150 writel(control_value, mmio + HIBMC_POWER_MODE_CTRL); 151 } 152 153 void hibmc_set_current_gate(struct hibmc_drm_private *priv, unsigned int gate) 154 { 155 u32 gate_reg; 156 u32 mode; 157 void __iomem *mmio = priv->mmio; 158 159 /* Get current power mode. */ 160 mode = (readl(mmio + HIBMC_POWER_MODE_CTRL) & 161 HIBMC_PW_MODE_CTL_MODE_MASK) >> HIBMC_PW_MODE_CTL_MODE_SHIFT; 162 163 switch (mode) { 164 case HIBMC_PW_MODE_CTL_MODE_MODE0: 165 gate_reg = HIBMC_MODE0_GATE; 166 break; 167 168 case HIBMC_PW_MODE_CTL_MODE_MODE1: 169 gate_reg = HIBMC_MODE1_GATE; 170 break; 171 172 default: 173 gate_reg = HIBMC_MODE0_GATE; 174 break; 175 } 176 writel(gate, mmio + gate_reg); 177 } 178 179 static void hibmc_hw_config(struct hibmc_drm_private *priv) 180 { 181 u32 reg; 182 183 /* On hardware reset, power mode 0 is default. */ 184 hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_MODE0); 185 186 /* Enable display power gate & LOCALMEM power gate*/ 187 reg = readl(priv->mmio + HIBMC_CURRENT_GATE); 188 reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK; 189 reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK; 190 reg |= HIBMC_CURR_GATE_DISPLAY(1); 191 reg |= HIBMC_CURR_GATE_LOCALMEM(1); 192 193 hibmc_set_current_gate(priv, reg); 194 195 /* 196 * Reset the memory controller. If the memory controller 197 * is not reset in chip,the system might hang when sw accesses 198 * the memory.The memory should be resetted after 199 * changing the MXCLK. 200 */ 201 reg = readl(priv->mmio + HIBMC_MISC_CTRL); 202 reg &= ~HIBMC_MSCCTL_LOCALMEM_RESET_MASK; 203 reg |= HIBMC_MSCCTL_LOCALMEM_RESET(0); 204 writel(reg, priv->mmio + HIBMC_MISC_CTRL); 205 206 reg &= ~HIBMC_MSCCTL_LOCALMEM_RESET_MASK; 207 reg |= HIBMC_MSCCTL_LOCALMEM_RESET(1); 208 209 writel(reg, priv->mmio + HIBMC_MISC_CTRL); 210 } 211 212 static int hibmc_hw_map(struct hibmc_drm_private *priv) 213 { 214 struct drm_device *dev = &priv->dev; 215 struct pci_dev *pdev = to_pci_dev(dev->dev); 216 resource_size_t ioaddr, iosize; 217 218 ioaddr = pci_resource_start(pdev, 1); 219 iosize = pci_resource_len(pdev, 1); 220 priv->mmio = devm_ioremap(dev->dev, ioaddr, iosize); 221 if (!priv->mmio) { 222 drm_err(dev, "Cannot map mmio region\n"); 223 return -ENOMEM; 224 } 225 226 return 0; 227 } 228 229 static int hibmc_hw_init(struct hibmc_drm_private *priv) 230 { 231 int ret; 232 233 ret = hibmc_hw_map(priv); 234 if (ret) 235 return ret; 236 237 hibmc_hw_config(priv); 238 239 return 0; 240 } 241 242 static int hibmc_unload(struct drm_device *dev) 243 { 244 struct pci_dev *pdev = to_pci_dev(dev->dev); 245 246 drm_atomic_helper_shutdown(dev); 247 248 free_irq(pdev->irq, dev); 249 250 pci_disable_msi(to_pci_dev(dev->dev)); 251 252 return 0; 253 } 254 255 static int hibmc_load(struct drm_device *dev) 256 { 257 struct pci_dev *pdev = to_pci_dev(dev->dev); 258 struct hibmc_drm_private *priv = to_hibmc_drm_private(dev); 259 int ret; 260 261 ret = hibmc_hw_init(priv); 262 if (ret) 263 goto err; 264 265 ret = drmm_vram_helper_init(dev, pci_resource_start(pdev, 0), 266 pci_resource_len(pdev, 0)); 267 if (ret) { 268 drm_err(dev, "Error initializing VRAM MM; %d\n", ret); 269 goto err; 270 } 271 272 ret = hibmc_kms_init(priv); 273 if (ret) 274 goto err; 275 276 ret = drm_vblank_init(dev, dev->mode_config.num_crtc); 277 if (ret) { 278 drm_err(dev, "failed to initialize vblank: %d\n", ret); 279 goto err; 280 } 281 282 ret = pci_enable_msi(pdev); 283 if (ret) { 284 drm_warn(dev, "enabling MSI failed: %d\n", ret); 285 } else { 286 /* PCI devices require shared interrupts. */ 287 ret = request_irq(pdev->irq, hibmc_interrupt, IRQF_SHARED, 288 dev->driver->name, dev); 289 if (ret) 290 drm_warn(dev, "install irq failed: %d\n", ret); 291 } 292 293 /* reset all the states of crtc/plane/encoder/connector */ 294 drm_mode_config_reset(dev); 295 296 return 0; 297 298 err: 299 hibmc_unload(dev); 300 drm_err(dev, "failed to initialize drm driver: %d\n", ret); 301 return ret; 302 } 303 304 static int hibmc_pci_probe(struct pci_dev *pdev, 305 const struct pci_device_id *ent) 306 { 307 struct hibmc_drm_private *priv; 308 struct drm_device *dev; 309 int ret; 310 311 ret = aperture_remove_conflicting_pci_devices(pdev, hibmc_driver.name); 312 if (ret) 313 return ret; 314 315 priv = devm_drm_dev_alloc(&pdev->dev, &hibmc_driver, 316 struct hibmc_drm_private, dev); 317 if (IS_ERR(priv)) { 318 DRM_ERROR("failed to allocate drm_device\n"); 319 return PTR_ERR(priv); 320 } 321 322 dev = &priv->dev; 323 pci_set_drvdata(pdev, dev); 324 325 ret = pcim_enable_device(pdev); 326 if (ret) { 327 drm_err(dev, "failed to enable pci device: %d\n", ret); 328 goto err_return; 329 } 330 331 ret = hibmc_load(dev); 332 if (ret) { 333 drm_err(dev, "failed to load hibmc: %d\n", ret); 334 goto err_return; 335 } 336 337 ret = drm_dev_register(dev, 0); 338 if (ret) { 339 drm_err(dev, "failed to register drv for userspace access: %d\n", 340 ret); 341 goto err_unload; 342 } 343 344 drm_client_setup(dev, NULL); 345 346 return 0; 347 348 err_unload: 349 hibmc_unload(dev); 350 err_return: 351 return ret; 352 } 353 354 static void hibmc_pci_remove(struct pci_dev *pdev) 355 { 356 struct drm_device *dev = pci_get_drvdata(pdev); 357 358 drm_dev_unregister(dev); 359 hibmc_unload(dev); 360 } 361 362 static void hibmc_pci_shutdown(struct pci_dev *pdev) 363 { 364 drm_atomic_helper_shutdown(pci_get_drvdata(pdev)); 365 } 366 367 static const struct pci_device_id hibmc_pci_table[] = { 368 { PCI_VDEVICE(HUAWEI, 0x1711) }, 369 {0,} 370 }; 371 372 static struct pci_driver hibmc_pci_driver = { 373 .name = "hibmc-drm", 374 .id_table = hibmc_pci_table, 375 .probe = hibmc_pci_probe, 376 .remove = hibmc_pci_remove, 377 .shutdown = hibmc_pci_shutdown, 378 .driver.pm = &hibmc_pm_ops, 379 }; 380 381 drm_module_pci_driver(hibmc_pci_driver); 382 383 MODULE_DEVICE_TABLE(pci, hibmc_pci_table); 384 MODULE_AUTHOR("RongrongZou <zourongrong@huawei.com>"); 385 MODULE_DESCRIPTION("DRM Driver for Hisilicon Hibmc"); 386 MODULE_LICENSE("GPL v2"); 387