1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* Hisilicon Hibmc SoC drm driver 3 * 4 * Based on the bochs drm driver. 5 * 6 * Copyright (c) 2016 Huawei Limited. 7 * 8 * Author: 9 * Rongrong Zou <zourongrong@huawei.com> 10 * Rongrong Zou <zourongrong@gmail.com> 11 * Jianhua Li <lijianhua@huawei.com> 12 */ 13 14 #include <linux/delay.h> 15 16 #include <drm/drm_atomic.h> 17 #include <drm/drm_atomic_helper.h> 18 #include <drm/drm_fourcc.h> 19 #include <drm/drm_gem_vram_helper.h> 20 #include <drm/drm_vblank.h> 21 22 #include "hibmc_drm_drv.h" 23 #include "hibmc_drm_regs.h" 24 25 struct hibmc_display_panel_pll { 26 u64 M; 27 u64 N; 28 u64 OD; 29 u64 POD; 30 }; 31 32 struct hibmc_dislay_pll_config { 33 u64 hdisplay; 34 u64 vdisplay; 35 u32 pll1_config_value; 36 u32 pll2_config_value; 37 }; 38 39 static const struct hibmc_dislay_pll_config hibmc_pll_table[] = { 40 {640, 480, CRT_PLL1_HS_25MHZ, CRT_PLL2_HS_25MHZ}, 41 {800, 600, CRT_PLL1_HS_40MHZ, CRT_PLL2_HS_40MHZ}, 42 {1024, 768, CRT_PLL1_HS_65MHZ, CRT_PLL2_HS_65MHZ}, 43 {1152, 864, CRT_PLL1_HS_80MHZ_1152, CRT_PLL2_HS_80MHZ}, 44 {1280, 768, CRT_PLL1_HS_80MHZ, CRT_PLL2_HS_80MHZ}, 45 {1280, 720, CRT_PLL1_HS_74MHZ, CRT_PLL2_HS_74MHZ}, 46 {1280, 960, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ}, 47 {1280, 1024, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ}, 48 {1440, 900, CRT_PLL1_HS_106MHZ, CRT_PLL2_HS_106MHZ}, 49 {1600, 900, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ}, 50 {1600, 1200, CRT_PLL1_HS_162MHZ, CRT_PLL2_HS_162MHZ}, 51 {1920, 1080, CRT_PLL1_HS_148MHZ, CRT_PLL2_HS_148MHZ}, 52 {1920, 1200, CRT_PLL1_HS_193MHZ, CRT_PLL2_HS_193MHZ}, 53 }; 54 55 static int hibmc_plane_atomic_check(struct drm_plane *plane, 56 struct drm_atomic_state *state) 57 { 58 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 59 plane); 60 struct drm_framebuffer *fb = new_plane_state->fb; 61 struct drm_crtc *crtc = new_plane_state->crtc; 62 struct drm_crtc_state *crtc_state; 63 u32 src_w = new_plane_state->src_w >> 16; 64 u32 src_h = new_plane_state->src_h >> 16; 65 66 if (!crtc || !fb) 67 return 0; 68 69 crtc_state = drm_atomic_get_crtc_state(state, crtc); 70 if (IS_ERR(crtc_state)) 71 return PTR_ERR(crtc_state); 72 73 if (src_w != new_plane_state->crtc_w || src_h != new_plane_state->crtc_h) { 74 drm_dbg_atomic(plane->dev, "scale not support\n"); 75 return -EINVAL; 76 } 77 78 if (new_plane_state->crtc_x < 0 || new_plane_state->crtc_y < 0) { 79 drm_dbg_atomic(plane->dev, "crtc_x/y of drm_plane state is invalid\n"); 80 return -EINVAL; 81 } 82 83 if (!crtc_state->enable) 84 return 0; 85 86 if (new_plane_state->crtc_x + new_plane_state->crtc_w > 87 crtc_state->adjusted_mode.hdisplay || 88 new_plane_state->crtc_y + new_plane_state->crtc_h > 89 crtc_state->adjusted_mode.vdisplay) { 90 drm_dbg_atomic(plane->dev, "visible portion of plane is invalid\n"); 91 return -EINVAL; 92 } 93 94 if (new_plane_state->fb->pitches[0] % 128 != 0) { 95 drm_dbg_atomic(plane->dev, "wrong stride with 128-byte aligned\n"); 96 return -EINVAL; 97 } 98 return 0; 99 } 100 101 static void hibmc_plane_atomic_update(struct drm_plane *plane, 102 struct drm_atomic_state *state) 103 { 104 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 105 plane); 106 u32 reg; 107 s64 gpu_addr = 0; 108 u32 line_l; 109 struct hibmc_drm_private *priv = to_hibmc_drm_private(plane->dev); 110 struct drm_gem_vram_object *gbo; 111 112 if (!new_state->fb) 113 return; 114 115 gbo = drm_gem_vram_of_gem(new_state->fb->obj[0]); 116 117 gpu_addr = drm_gem_vram_offset(gbo); 118 if (WARN_ON_ONCE(gpu_addr < 0)) 119 return; /* Bug: we didn't pin the BO to VRAM in prepare_fb. */ 120 121 writel(gpu_addr, priv->mmio + HIBMC_CRT_FB_ADDRESS); 122 123 reg = new_state->fb->width * (new_state->fb->format->cpp[0]); 124 125 line_l = new_state->fb->pitches[0]; 126 writel(HIBMC_FIELD(HIBMC_CRT_FB_WIDTH_WIDTH, reg) | 127 HIBMC_FIELD(HIBMC_CRT_FB_WIDTH_OFFS, line_l), 128 priv->mmio + HIBMC_CRT_FB_WIDTH); 129 130 /* SET PIXEL FORMAT */ 131 reg = readl(priv->mmio + HIBMC_CRT_DISP_CTL); 132 reg &= ~HIBMC_CRT_DISP_CTL_FORMAT_MASK; 133 reg |= HIBMC_FIELD(HIBMC_CRT_DISP_CTL_FORMAT, 134 new_state->fb->format->cpp[0] * 8 / 16); 135 writel(reg, priv->mmio + HIBMC_CRT_DISP_CTL); 136 } 137 138 static const u32 channel_formats1[] = { 139 DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, DRM_FORMAT_RGB888, 140 DRM_FORMAT_BGR888, DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888, 141 DRM_FORMAT_RGBA8888, DRM_FORMAT_BGRA8888, DRM_FORMAT_ARGB8888, 142 DRM_FORMAT_ABGR8888 143 }; 144 145 static const struct drm_plane_funcs hibmc_plane_funcs = { 146 .update_plane = drm_atomic_helper_update_plane, 147 .disable_plane = drm_atomic_helper_disable_plane, 148 .destroy = drm_plane_cleanup, 149 .reset = drm_atomic_helper_plane_reset, 150 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 151 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 152 }; 153 154 static const struct drm_plane_helper_funcs hibmc_plane_helper_funcs = { 155 DRM_GEM_VRAM_PLANE_HELPER_FUNCS, 156 .atomic_check = hibmc_plane_atomic_check, 157 .atomic_update = hibmc_plane_atomic_update, 158 }; 159 160 static void hibmc_crtc_dpms(struct drm_crtc *crtc, u32 dpms) 161 { 162 struct hibmc_drm_private *priv = to_hibmc_drm_private(crtc->dev); 163 u32 reg; 164 165 reg = readl(priv->mmio + HIBMC_CRT_DISP_CTL); 166 reg &= ~HIBMC_CRT_DISP_CTL_DPMS_MASK; 167 reg |= HIBMC_FIELD(HIBMC_CRT_DISP_CTL_DPMS, dpms); 168 reg &= ~HIBMC_CRT_DISP_CTL_TIMING_MASK; 169 if (dpms == HIBMC_CRT_DPMS_ON) 170 reg |= HIBMC_CRT_DISP_CTL_TIMING(1); 171 writel(reg, priv->mmio + HIBMC_CRT_DISP_CTL); 172 } 173 174 static void hibmc_crtc_atomic_enable(struct drm_crtc *crtc, 175 struct drm_atomic_state *state) 176 { 177 u32 reg; 178 struct hibmc_drm_private *priv = to_hibmc_drm_private(crtc->dev); 179 180 hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_MODE0); 181 182 /* Enable display power gate & LOCALMEM power gate*/ 183 reg = readl(priv->mmio + HIBMC_CURRENT_GATE); 184 reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK; 185 reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK; 186 reg |= HIBMC_CURR_GATE_LOCALMEM(1); 187 reg |= HIBMC_CURR_GATE_DISPLAY(1); 188 hibmc_set_current_gate(priv, reg); 189 drm_crtc_vblank_on(crtc); 190 hibmc_crtc_dpms(crtc, HIBMC_CRT_DPMS_ON); 191 } 192 193 static void hibmc_crtc_atomic_disable(struct drm_crtc *crtc, 194 struct drm_atomic_state *state) 195 { 196 u32 reg; 197 struct hibmc_drm_private *priv = to_hibmc_drm_private(crtc->dev); 198 199 hibmc_crtc_dpms(crtc, HIBMC_CRT_DPMS_OFF); 200 drm_crtc_vblank_off(crtc); 201 202 hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_SLEEP); 203 204 /* Enable display power gate & LOCALMEM power gate*/ 205 reg = readl(priv->mmio + HIBMC_CURRENT_GATE); 206 reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK; 207 reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK; 208 reg |= HIBMC_CURR_GATE_LOCALMEM(0); 209 reg |= HIBMC_CURR_GATE_DISPLAY(0); 210 hibmc_set_current_gate(priv, reg); 211 } 212 213 static enum drm_mode_status 214 hibmc_crtc_mode_valid(struct drm_crtc *crtc, 215 const struct drm_display_mode *mode) 216 { 217 size_t i = 0; 218 int vrefresh = drm_mode_vrefresh(mode); 219 220 if (vrefresh < 59 || vrefresh > 61) 221 return MODE_NOCLOCK; 222 223 for (i = 0; i < ARRAY_SIZE(hibmc_pll_table); i++) { 224 if (hibmc_pll_table[i].hdisplay == mode->hdisplay && 225 hibmc_pll_table[i].vdisplay == mode->vdisplay) 226 return MODE_OK; 227 } 228 229 return MODE_BAD; 230 } 231 232 static u32 format_pll_reg(void) 233 { 234 u32 pllreg = 0; 235 struct hibmc_display_panel_pll pll = {0}; 236 237 /* 238 * Note that all PLL's have the same format. Here, 239 * we just use Panel PLL parameter to work out the bit 240 * fields in the register.On returning a 32 bit number, the value can 241 * be applied to any PLL in the calling function. 242 */ 243 pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_BYPASS, 0); 244 pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_POWER, 1); 245 pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_INPUT, 0); 246 pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_POD, pll.POD); 247 pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_OD, pll.OD); 248 pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_N, pll.N); 249 pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_M, pll.M); 250 251 return pllreg; 252 } 253 254 static void set_vclock_hisilicon(struct drm_device *dev, u64 pll) 255 { 256 u32 val; 257 struct hibmc_drm_private *priv = to_hibmc_drm_private(dev); 258 259 val = readl(priv->mmio + CRT_PLL1_HS); 260 val &= ~(CRT_PLL1_HS_OUTER_BYPASS(1)); 261 writel(val, priv->mmio + CRT_PLL1_HS); 262 263 val = CRT_PLL1_HS_INTER_BYPASS(1) | CRT_PLL1_HS_POWERON(1); 264 writel(val, priv->mmio + CRT_PLL1_HS); 265 266 writel(pll, priv->mmio + CRT_PLL1_HS); 267 268 usleep_range(1000, 2000); 269 270 val = pll & ~(CRT_PLL1_HS_POWERON(1)); 271 writel(val, priv->mmio + CRT_PLL1_HS); 272 273 usleep_range(1000, 2000); 274 275 val &= ~(CRT_PLL1_HS_INTER_BYPASS(1)); 276 writel(val, priv->mmio + CRT_PLL1_HS); 277 278 usleep_range(1000, 2000); 279 280 val |= CRT_PLL1_HS_OUTER_BYPASS(1); 281 writel(val, priv->mmio + CRT_PLL1_HS); 282 } 283 284 static void get_pll_config(u64 x, u64 y, u32 *pll1, u32 *pll2) 285 { 286 size_t i; 287 size_t count = ARRAY_SIZE(hibmc_pll_table); 288 289 for (i = 0; i < count; i++) { 290 if (hibmc_pll_table[i].hdisplay == x && 291 hibmc_pll_table[i].vdisplay == y) { 292 *pll1 = hibmc_pll_table[i].pll1_config_value; 293 *pll2 = hibmc_pll_table[i].pll2_config_value; 294 return; 295 } 296 } 297 298 /* if found none, we use default value */ 299 *pll1 = CRT_PLL1_HS_25MHZ; 300 *pll2 = CRT_PLL2_HS_25MHZ; 301 } 302 303 /* 304 * This function takes care the extra registers and bit fields required to 305 * setup a mode in board. 306 * Explanation about Display Control register: 307 * FPGA only supports 7 predefined pixel clocks, and clock select is 308 * in bit 4:0 of new register 0x802a8. 309 */ 310 static u32 display_ctrl_adjust(struct drm_device *dev, 311 struct drm_display_mode *mode, 312 u32 ctrl) 313 { 314 u64 x, y; 315 u32 pll1; /* bit[31:0] of PLL */ 316 u32 pll2; /* bit[63:32] of PLL */ 317 struct hibmc_drm_private *priv = to_hibmc_drm_private(dev); 318 319 x = mode->hdisplay; 320 y = mode->vdisplay; 321 322 get_pll_config(x, y, &pll1, &pll2); 323 writel(pll2, priv->mmio + CRT_PLL2_HS); 324 set_vclock_hisilicon(dev, pll1); 325 326 /* 327 * Hisilicon has to set up the top-left and bottom-right 328 * registers as well. 329 * Note that normal chip only use those two register for 330 * auto-centering mode. 331 */ 332 writel(HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_TL_TOP, 0) | 333 HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_TL_LEFT, 0), 334 priv->mmio + HIBMC_CRT_AUTO_CENTERING_TL); 335 336 writel(HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_BR_BOTTOM, y - 1) | 337 HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_BR_RIGHT, x - 1), 338 priv->mmio + HIBMC_CRT_AUTO_CENTERING_BR); 339 340 /* 341 * Assume common fields in ctrl have been properly set before 342 * calling this function. 343 * This function only sets the extra fields in ctrl. 344 */ 345 346 /* Set bit 25 of display controller: Select CRT or VGA clock */ 347 ctrl &= ~HIBMC_CRT_DISP_CTL_CRTSELECT_MASK; 348 ctrl &= ~HIBMC_CRT_DISP_CTL_CLOCK_PHASE_MASK; 349 350 ctrl |= HIBMC_CRT_DISP_CTL_CRTSELECT(HIBMC_CRTSELECT_CRT); 351 352 /* clock_phase_polarity is 0 */ 353 ctrl |= HIBMC_CRT_DISP_CTL_CLOCK_PHASE(0); 354 355 writel(ctrl, priv->mmio + HIBMC_CRT_DISP_CTL); 356 357 return ctrl; 358 } 359 360 static void hibmc_crtc_mode_set_nofb(struct drm_crtc *crtc) 361 { 362 u32 val; 363 struct drm_display_mode *mode = &crtc->state->mode; 364 struct drm_device *dev = crtc->dev; 365 struct hibmc_drm_private *priv = to_hibmc_drm_private(dev); 366 u32 width = mode->hsync_end - mode->hsync_start; 367 u32 height = mode->vsync_end - mode->vsync_start; 368 369 writel(format_pll_reg(), priv->mmio + HIBMC_CRT_PLL_CTRL); 370 writel(HIBMC_FIELD(HIBMC_CRT_HORZ_TOTAL_TOTAL, mode->htotal - 1) | 371 HIBMC_FIELD(HIBMC_CRT_HORZ_TOTAL_DISP_END, mode->hdisplay - 1), 372 priv->mmio + HIBMC_CRT_HORZ_TOTAL); 373 374 writel(HIBMC_FIELD(HIBMC_CRT_HORZ_SYNC_WIDTH, width) | 375 HIBMC_FIELD(HIBMC_CRT_HORZ_SYNC_START, mode->hsync_start - 1), 376 priv->mmio + HIBMC_CRT_HORZ_SYNC); 377 378 writel(HIBMC_FIELD(HIBMC_CRT_VERT_TOTAL_TOTAL, mode->vtotal - 1) | 379 HIBMC_FIELD(HIBMC_CRT_VERT_TOTAL_DISP_END, mode->vdisplay - 1), 380 priv->mmio + HIBMC_CRT_VERT_TOTAL); 381 382 writel(HIBMC_FIELD(HIBMC_CRT_VERT_SYNC_HEIGHT, height) | 383 HIBMC_FIELD(HIBMC_CRT_VERT_SYNC_START, mode->vsync_start - 1), 384 priv->mmio + HIBMC_CRT_VERT_SYNC); 385 386 val = HIBMC_FIELD(HIBMC_CRT_DISP_CTL_VSYNC_PHASE, 0); 387 val |= HIBMC_FIELD(HIBMC_CRT_DISP_CTL_HSYNC_PHASE, 0); 388 val |= HIBMC_CRT_DISP_CTL_TIMING(1); 389 val |= HIBMC_CRT_DISP_CTL_PLANE(1); 390 391 display_ctrl_adjust(dev, mode, val); 392 } 393 394 static void hibmc_crtc_atomic_begin(struct drm_crtc *crtc, 395 struct drm_atomic_state *state) 396 { 397 u32 reg; 398 struct drm_device *dev = crtc->dev; 399 struct hibmc_drm_private *priv = to_hibmc_drm_private(dev); 400 401 hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_MODE0); 402 403 /* Enable display power gate & LOCALMEM power gate*/ 404 reg = readl(priv->mmio + HIBMC_CURRENT_GATE); 405 reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK; 406 reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK; 407 reg |= HIBMC_CURR_GATE_DISPLAY(1); 408 reg |= HIBMC_CURR_GATE_LOCALMEM(1); 409 hibmc_set_current_gate(priv, reg); 410 411 /* We can add more initialization as needed. */ 412 } 413 414 static void hibmc_crtc_atomic_flush(struct drm_crtc *crtc, 415 struct drm_atomic_state *state) 416 417 { 418 unsigned long flags; 419 420 spin_lock_irqsave(&crtc->dev->event_lock, flags); 421 if (crtc->state->event) 422 drm_crtc_send_vblank_event(crtc, crtc->state->event); 423 crtc->state->event = NULL; 424 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 425 } 426 427 static int hibmc_crtc_enable_vblank(struct drm_crtc *crtc) 428 { 429 struct hibmc_drm_private *priv = to_hibmc_drm_private(crtc->dev); 430 431 writel(HIBMC_RAW_INTERRUPT_EN_VBLANK(1), 432 priv->mmio + HIBMC_RAW_INTERRUPT_EN); 433 434 return 0; 435 } 436 437 static void hibmc_crtc_disable_vblank(struct drm_crtc *crtc) 438 { 439 struct hibmc_drm_private *priv = to_hibmc_drm_private(crtc->dev); 440 441 writel(HIBMC_RAW_INTERRUPT_EN_VBLANK(0), 442 priv->mmio + HIBMC_RAW_INTERRUPT_EN); 443 } 444 445 static void hibmc_crtc_load_lut(struct drm_crtc *crtc) 446 { 447 struct hibmc_drm_private *priv = to_hibmc_drm_private(crtc->dev); 448 void __iomem *mmio = priv->mmio; 449 u16 *r, *g, *b; 450 u32 reg; 451 u32 i; 452 453 r = crtc->gamma_store; 454 g = r + crtc->gamma_size; 455 b = g + crtc->gamma_size; 456 457 for (i = 0; i < crtc->gamma_size; i++) { 458 u32 offset = i << 2; 459 u8 red = *r++ >> 8; 460 u8 green = *g++ >> 8; 461 u8 blue = *b++ >> 8; 462 u32 rgb = (red << 16) | (green << 8) | blue; 463 464 writel(rgb, mmio + HIBMC_CRT_PALETTE + offset); 465 } 466 467 reg = readl(priv->mmio + HIBMC_CRT_DISP_CTL); 468 reg |= HIBMC_FIELD(HIBMC_CTL_DISP_CTL_GAMMA, 1); 469 writel(reg, priv->mmio + HIBMC_CRT_DISP_CTL); 470 } 471 472 static int hibmc_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 473 u16 *blue, uint32_t size, 474 struct drm_modeset_acquire_ctx *ctx) 475 { 476 hibmc_crtc_load_lut(crtc); 477 478 return 0; 479 } 480 481 static const struct drm_crtc_funcs hibmc_crtc_funcs = { 482 .page_flip = drm_atomic_helper_page_flip, 483 .set_config = drm_atomic_helper_set_config, 484 .destroy = drm_crtc_cleanup, 485 .reset = drm_atomic_helper_crtc_reset, 486 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 487 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 488 .enable_vblank = hibmc_crtc_enable_vblank, 489 .disable_vblank = hibmc_crtc_disable_vblank, 490 .gamma_set = hibmc_crtc_gamma_set, 491 }; 492 493 static const struct drm_crtc_helper_funcs hibmc_crtc_helper_funcs = { 494 .mode_set_nofb = hibmc_crtc_mode_set_nofb, 495 .atomic_begin = hibmc_crtc_atomic_begin, 496 .atomic_flush = hibmc_crtc_atomic_flush, 497 .atomic_enable = hibmc_crtc_atomic_enable, 498 .atomic_disable = hibmc_crtc_atomic_disable, 499 .mode_valid = hibmc_crtc_mode_valid, 500 }; 501 502 int hibmc_de_init(struct hibmc_drm_private *priv) 503 { 504 struct drm_device *dev = &priv->dev; 505 struct drm_crtc *crtc = &priv->crtc; 506 struct drm_plane *plane = &priv->primary_plane; 507 int ret; 508 509 ret = drm_universal_plane_init(dev, plane, 1, &hibmc_plane_funcs, 510 channel_formats1, 511 ARRAY_SIZE(channel_formats1), 512 NULL, 513 DRM_PLANE_TYPE_PRIMARY, 514 NULL); 515 516 if (ret) { 517 drm_err(dev, "failed to init plane: %d\n", ret); 518 return ret; 519 } 520 521 drm_plane_helper_add(plane, &hibmc_plane_helper_funcs); 522 523 ret = drm_crtc_init_with_planes(dev, crtc, plane, 524 NULL, &hibmc_crtc_funcs, NULL); 525 if (ret) { 526 drm_err(dev, "failed to init crtc: %d\n", ret); 527 return ret; 528 } 529 530 ret = drm_mode_crtc_set_gamma_size(crtc, 256); 531 if (ret) { 532 drm_err(dev, "failed to set gamma size: %d\n", ret); 533 return ret; 534 } 535 drm_crtc_helper_add(crtc, &hibmc_crtc_helper_funcs); 536 537 return 0; 538 } 539