1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2007 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 */ 28 29 #include <linux/delay.h> 30 #include <linux/i2c.h> 31 #include <linux/kernel.h> 32 #include <linux/module.h> 33 #include <linux/slab.h> 34 35 #include <drm/drm_crtc.h> 36 #include <drm/drm_edid.h> 37 38 #include "psb_drv.h" 39 #include "psb_intel_drv.h" 40 #include "psb_intel_reg.h" 41 #include "psb_intel_sdvo_regs.h" 42 43 #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1) 44 #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1) 45 #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1) 46 #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0) 47 48 #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\ 49 SDVO_TV_MASK) 50 51 #define IS_TV(c) (c->output_flag & SDVO_TV_MASK) 52 #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK) 53 #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK) 54 #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK)) 55 56 57 static const char *tv_format_names[] = { 58 "NTSC_M" , "NTSC_J" , "NTSC_443", 59 "PAL_B" , "PAL_D" , "PAL_G" , 60 "PAL_H" , "PAL_I" , "PAL_M" , 61 "PAL_N" , "PAL_NC" , "PAL_60" , 62 "SECAM_B" , "SECAM_D" , "SECAM_G" , 63 "SECAM_K" , "SECAM_K1", "SECAM_L" , 64 "SECAM_60" 65 }; 66 67 struct psb_intel_sdvo { 68 struct gma_encoder base; 69 70 struct i2c_adapter *i2c; 71 u8 slave_addr; 72 73 struct i2c_adapter ddc; 74 75 /* Register for the SDVO device: SDVOB or SDVOC */ 76 int sdvo_reg; 77 78 /* Active outputs controlled by this SDVO output */ 79 uint16_t controlled_output; 80 81 /* 82 * Capabilities of the SDVO device returned by 83 * i830_sdvo_get_capabilities() 84 */ 85 struct psb_intel_sdvo_caps caps; 86 87 /* Pixel clock limitations reported by the SDVO device, in kHz */ 88 int pixel_clock_min, pixel_clock_max; 89 90 /* 91 * For multiple function SDVO device, 92 * this is for current attached outputs. 93 */ 94 uint16_t attached_output; 95 96 /** 97 * This is used to select the color range of RBG outputs in HDMI mode. 98 * It is only valid when using TMDS encoding and 8 bit per color mode. 99 */ 100 uint32_t color_range; 101 102 /** 103 * This is set if we're going to treat the device as TV-out. 104 * 105 * While we have these nice friendly flags for output types that ought 106 * to decide this for us, the S-Video output on our HDMI+S-Video card 107 * shows up as RGB1 (VGA). 108 */ 109 bool is_tv; 110 111 /* This is for current tv format name */ 112 int tv_format_index; 113 114 /** 115 * This is set if we treat the device as HDMI, instead of DVI. 116 */ 117 bool is_hdmi; 118 bool has_hdmi_monitor; 119 bool has_hdmi_audio; 120 121 /** 122 * This is set if we detect output of sdvo device as LVDS and 123 * have a valid fixed mode to use with the panel. 124 */ 125 bool is_lvds; 126 127 /** 128 * This is sdvo fixed panel mode pointer 129 */ 130 struct drm_display_mode *sdvo_lvds_fixed_mode; 131 132 /* DDC bus used by this SDVO encoder */ 133 uint8_t ddc_bus; 134 135 u8 pixel_multiplier; 136 137 /* Input timings for adjusted_mode */ 138 struct psb_intel_sdvo_dtd input_dtd; 139 140 /* Saved SDVO output states */ 141 uint32_t saveSDVO; /* Can be SDVOB or SDVOC depending on sdvo_reg */ 142 }; 143 144 struct psb_intel_sdvo_connector { 145 struct gma_connector base; 146 147 /* Mark the type of connector */ 148 uint16_t output_flag; 149 150 int force_audio; 151 152 /* This contains all current supported TV format */ 153 u8 tv_format_supported[ARRAY_SIZE(tv_format_names)]; 154 int format_supported_num; 155 struct drm_property *tv_format; 156 157 /* add the property for the SDVO-TV */ 158 struct drm_property *left; 159 struct drm_property *right; 160 struct drm_property *top; 161 struct drm_property *bottom; 162 struct drm_property *hpos; 163 struct drm_property *vpos; 164 struct drm_property *contrast; 165 struct drm_property *saturation; 166 struct drm_property *hue; 167 struct drm_property *sharpness; 168 struct drm_property *flicker_filter; 169 struct drm_property *flicker_filter_adaptive; 170 struct drm_property *flicker_filter_2d; 171 struct drm_property *tv_chroma_filter; 172 struct drm_property *tv_luma_filter; 173 struct drm_property *dot_crawl; 174 175 /* add the property for the SDVO-TV/LVDS */ 176 struct drm_property *brightness; 177 178 /* Add variable to record current setting for the above property */ 179 u32 left_margin, right_margin, top_margin, bottom_margin; 180 181 /* this is to get the range of margin.*/ 182 u32 max_hscan, max_vscan; 183 u32 max_hpos, cur_hpos; 184 u32 max_vpos, cur_vpos; 185 u32 cur_brightness, max_brightness; 186 u32 cur_contrast, max_contrast; 187 u32 cur_saturation, max_saturation; 188 u32 cur_hue, max_hue; 189 u32 cur_sharpness, max_sharpness; 190 u32 cur_flicker_filter, max_flicker_filter; 191 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive; 192 u32 cur_flicker_filter_2d, max_flicker_filter_2d; 193 u32 cur_tv_chroma_filter, max_tv_chroma_filter; 194 u32 cur_tv_luma_filter, max_tv_luma_filter; 195 u32 cur_dot_crawl, max_dot_crawl; 196 }; 197 198 static struct psb_intel_sdvo *to_psb_intel_sdvo(struct drm_encoder *encoder) 199 { 200 return container_of(encoder, struct psb_intel_sdvo, base.base); 201 } 202 203 static struct psb_intel_sdvo *intel_attached_sdvo(struct drm_connector *connector) 204 { 205 return container_of(gma_attached_encoder(connector), 206 struct psb_intel_sdvo, base); 207 } 208 209 static struct psb_intel_sdvo_connector *to_psb_intel_sdvo_connector(struct drm_connector *connector) 210 { 211 return container_of(to_gma_connector(connector), struct psb_intel_sdvo_connector, base); 212 } 213 214 static bool 215 psb_intel_sdvo_output_setup(struct psb_intel_sdvo *psb_intel_sdvo, uint16_t flags); 216 static bool 217 psb_intel_sdvo_tv_create_property(struct psb_intel_sdvo *psb_intel_sdvo, 218 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector, 219 int type); 220 static bool 221 psb_intel_sdvo_create_enhance_property(struct psb_intel_sdvo *psb_intel_sdvo, 222 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector); 223 224 /* 225 * Writes the SDVOB or SDVOC with the given value, but always writes both 226 * SDVOB and SDVOC to work around apparent hardware issues (according to 227 * comments in the BIOS). 228 */ 229 static void psb_intel_sdvo_write_sdvox(struct psb_intel_sdvo *psb_intel_sdvo, u32 val) 230 { 231 struct drm_device *dev = psb_intel_sdvo->base.base.dev; 232 u32 bval = val, cval = val; 233 int i, j; 234 int need_aux = IS_MRST(dev) ? 1 : 0; 235 236 for (j = 0; j <= need_aux; j++) { 237 if (psb_intel_sdvo->sdvo_reg == SDVOB) 238 cval = REG_READ_WITH_AUX(SDVOC, j); 239 else 240 bval = REG_READ_WITH_AUX(SDVOB, j); 241 242 /* 243 * Write the registers twice for luck. Sometimes, 244 * writing them only once doesn't appear to 'stick'. 245 * The BIOS does this too. Yay, magic 246 */ 247 for (i = 0; i < 2; i++) { 248 REG_WRITE_WITH_AUX(SDVOB, bval, j); 249 REG_READ_WITH_AUX(SDVOB, j); 250 REG_WRITE_WITH_AUX(SDVOC, cval, j); 251 REG_READ_WITH_AUX(SDVOC, j); 252 } 253 } 254 } 255 256 static bool psb_intel_sdvo_read_byte(struct psb_intel_sdvo *psb_intel_sdvo, u8 addr, u8 *ch) 257 { 258 struct i2c_msg msgs[] = { 259 { 260 .addr = psb_intel_sdvo->slave_addr, 261 .flags = 0, 262 .len = 1, 263 .buf = &addr, 264 }, 265 { 266 .addr = psb_intel_sdvo->slave_addr, 267 .flags = I2C_M_RD, 268 .len = 1, 269 .buf = ch, 270 } 271 }; 272 int ret; 273 274 if ((ret = i2c_transfer(psb_intel_sdvo->i2c, msgs, 2)) == 2) 275 return true; 276 277 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret); 278 return false; 279 } 280 281 #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd} 282 /** Mapping of command numbers to names, for debug output */ 283 static const struct _sdvo_cmd_name { 284 u8 cmd; 285 const char *name; 286 } sdvo_cmd_names[] = { 287 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET), 288 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS), 289 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV), 290 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS), 291 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS), 292 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS), 293 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP), 294 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP), 295 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS), 296 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT), 297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG), 298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG), 299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE), 300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT), 301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT), 302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1), 303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2), 304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), 305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2), 306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), 307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1), 308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2), 309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1), 310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2), 311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING), 312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1), 313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2), 314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE), 315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE), 316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS), 317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT), 318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT), 319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS), 320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT), 321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT), 322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES), 323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE), 324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE), 325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE), 326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH), 327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT), 328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT), 329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS), 330 331 /* Add the op code for SDVO enhancements */ 332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS), 333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS), 334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS), 335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS), 336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS), 337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS), 338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION), 339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION), 340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION), 341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE), 342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE), 343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE), 344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST), 345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST), 346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST), 347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS), 348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS), 349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS), 350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H), 351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H), 352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H), 353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V), 354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V), 355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V), 356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER), 357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER), 358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER), 359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE), 360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE), 361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE), 362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D), 363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D), 364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D), 365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS), 366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS), 367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS), 368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL), 369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL), 370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER), 371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER), 372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER), 373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER), 374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER), 375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER), 376 377 /* HDMI op code */ 378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE), 379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE), 380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE), 381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI), 382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI), 383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP), 384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY), 385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY), 386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER), 387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT), 388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT), 389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX), 390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX), 391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO), 392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT), 393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT), 394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE), 395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE), 396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA), 397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA), 398 }; 399 400 #define IS_SDVOB(reg) (reg == SDVOB) 401 #define SDVO_NAME(svdo) (IS_SDVOB((svdo)->sdvo_reg) ? "SDVOB" : "SDVOC") 402 403 static void psb_intel_sdvo_debug_write(struct psb_intel_sdvo *psb_intel_sdvo, 404 u8 cmd, const void *args, int args_len) 405 { 406 struct drm_device *dev = psb_intel_sdvo->base.base.dev; 407 int i, pos = 0; 408 char buffer[73]; 409 410 #define BUF_PRINT(args...) \ 411 pos += snprintf(buffer + pos, max_t(int, sizeof(buffer) - pos, 0), args) 412 413 for (i = 0; i < args_len; i++) { 414 BUF_PRINT("%02X ", ((u8 *)args)[i]); 415 } 416 417 for (; i < 8; i++) { 418 BUF_PRINT(" "); 419 } 420 421 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) { 422 if (cmd == sdvo_cmd_names[i].cmd) { 423 BUF_PRINT("(%s)", sdvo_cmd_names[i].name); 424 break; 425 } 426 } 427 428 if (i == ARRAY_SIZE(sdvo_cmd_names)) 429 BUF_PRINT("(%02X)", cmd); 430 431 drm_WARN_ON(dev, pos >= sizeof(buffer) - 1); 432 #undef BUF_PRINT 433 434 DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(psb_intel_sdvo), cmd, buffer); 435 } 436 437 static const char *cmd_status_names[] = { 438 "Power on", 439 "Success", 440 "Not supported", 441 "Invalid arg", 442 "Pending", 443 "Target not specified", 444 "Scaling not supported" 445 }; 446 447 #define MAX_ARG_LEN 32 448 449 static bool psb_intel_sdvo_write_cmd(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd, 450 const void *args, int args_len) 451 { 452 u8 buf[MAX_ARG_LEN*2 + 2], status; 453 struct i2c_msg msgs[MAX_ARG_LEN + 3]; 454 int i, ret; 455 456 if (args_len > MAX_ARG_LEN) { 457 DRM_ERROR("Need to increase arg length\n"); 458 return false; 459 } 460 461 psb_intel_sdvo_debug_write(psb_intel_sdvo, cmd, args, args_len); 462 463 for (i = 0; i < args_len; i++) { 464 msgs[i].addr = psb_intel_sdvo->slave_addr; 465 msgs[i].flags = 0; 466 msgs[i].len = 2; 467 msgs[i].buf = buf + 2 *i; 468 buf[2*i + 0] = SDVO_I2C_ARG_0 - i; 469 buf[2*i + 1] = ((u8*)args)[i]; 470 } 471 msgs[i].addr = psb_intel_sdvo->slave_addr; 472 msgs[i].flags = 0; 473 msgs[i].len = 2; 474 msgs[i].buf = buf + 2*i; 475 buf[2*i + 0] = SDVO_I2C_OPCODE; 476 buf[2*i + 1] = cmd; 477 478 /* the following two are to read the response */ 479 status = SDVO_I2C_CMD_STATUS; 480 msgs[i+1].addr = psb_intel_sdvo->slave_addr; 481 msgs[i+1].flags = 0; 482 msgs[i+1].len = 1; 483 msgs[i+1].buf = &status; 484 485 msgs[i+2].addr = psb_intel_sdvo->slave_addr; 486 msgs[i+2].flags = I2C_M_RD; 487 msgs[i+2].len = 1; 488 msgs[i+2].buf = &status; 489 490 ret = i2c_transfer(psb_intel_sdvo->i2c, msgs, i+3); 491 if (ret < 0) { 492 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret); 493 return false; 494 } 495 if (ret != i+3) { 496 /* failure in I2C transfer */ 497 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3); 498 return false; 499 } 500 501 return true; 502 } 503 504 static bool psb_intel_sdvo_read_response(struct psb_intel_sdvo *psb_intel_sdvo, 505 void *response, int response_len) 506 { 507 struct drm_device *dev = psb_intel_sdvo->base.base.dev; 508 char buffer[73]; 509 int i, pos = 0; 510 u8 retry = 5; 511 u8 status; 512 513 /* 514 * The documentation states that all commands will be 515 * processed within 15µs, and that we need only poll 516 * the status byte a maximum of 3 times in order for the 517 * command to be complete. 518 * 519 * Check 5 times in case the hardware failed to read the docs. 520 */ 521 if (!psb_intel_sdvo_read_byte(psb_intel_sdvo, 522 SDVO_I2C_CMD_STATUS, 523 &status)) 524 goto log_fail; 525 526 while ((status == SDVO_CMD_STATUS_PENDING || 527 status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && retry--) { 528 udelay(15); 529 if (!psb_intel_sdvo_read_byte(psb_intel_sdvo, 530 SDVO_I2C_CMD_STATUS, 531 &status)) 532 goto log_fail; 533 } 534 535 #define BUF_PRINT(args...) \ 536 pos += snprintf(buffer + pos, max_t(int, sizeof(buffer) - pos, 0), args) 537 538 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP) 539 BUF_PRINT("(%s)", cmd_status_names[status]); 540 else 541 BUF_PRINT("(??? %d)", status); 542 543 if (status != SDVO_CMD_STATUS_SUCCESS) 544 goto log_fail; 545 546 /* Read the command response */ 547 for (i = 0; i < response_len; i++) { 548 if (!psb_intel_sdvo_read_byte(psb_intel_sdvo, 549 SDVO_I2C_RETURN_0 + i, 550 &((u8 *)response)[i])) 551 goto log_fail; 552 BUF_PRINT(" %02X", ((u8 *)response)[i]); 553 } 554 555 drm_WARN_ON(dev, pos >= sizeof(buffer) - 1); 556 #undef BUF_PRINT 557 558 DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(psb_intel_sdvo), buffer); 559 return true; 560 561 log_fail: 562 DRM_DEBUG_KMS("%s: R: ... failed %s\n", 563 SDVO_NAME(psb_intel_sdvo), buffer); 564 return false; 565 } 566 567 static int psb_intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode) 568 { 569 if (mode->clock >= 100000) 570 return 1; 571 else if (mode->clock >= 50000) 572 return 2; 573 else 574 return 4; 575 } 576 577 static bool psb_intel_sdvo_set_control_bus_switch(struct psb_intel_sdvo *psb_intel_sdvo, 578 u8 ddc_bus) 579 { 580 /* This must be the immediately preceding write before the i2c xfer */ 581 return psb_intel_sdvo_write_cmd(psb_intel_sdvo, 582 SDVO_CMD_SET_CONTROL_BUS_SWITCH, 583 &ddc_bus, 1); 584 } 585 586 static bool psb_intel_sdvo_set_value(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd, const void *data, int len) 587 { 588 if (!psb_intel_sdvo_write_cmd(psb_intel_sdvo, cmd, data, len)) 589 return false; 590 591 return psb_intel_sdvo_read_response(psb_intel_sdvo, NULL, 0); 592 } 593 594 static bool 595 psb_intel_sdvo_get_value(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd, void *value, int len) 596 { 597 if (!psb_intel_sdvo_write_cmd(psb_intel_sdvo, cmd, NULL, 0)) 598 return false; 599 600 return psb_intel_sdvo_read_response(psb_intel_sdvo, value, len); 601 } 602 603 static bool psb_intel_sdvo_set_target_input(struct psb_intel_sdvo *psb_intel_sdvo) 604 { 605 struct psb_intel_sdvo_set_target_input_args targets = {0}; 606 return psb_intel_sdvo_set_value(psb_intel_sdvo, 607 SDVO_CMD_SET_TARGET_INPUT, 608 &targets, sizeof(targets)); 609 } 610 611 /* 612 * Return whether each input is trained. 613 * 614 * This function is making an assumption about the layout of the response, 615 * which should be checked against the docs. 616 */ 617 static bool psb_intel_sdvo_get_trained_inputs(struct psb_intel_sdvo *psb_intel_sdvo, bool *input_1, bool *input_2) 618 { 619 struct psb_intel_sdvo_get_trained_inputs_response response; 620 621 BUILD_BUG_ON(sizeof(response) != 1); 622 if (!psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS, 623 &response, sizeof(response))) 624 return false; 625 626 *input_1 = response.input0_trained; 627 *input_2 = response.input1_trained; 628 return true; 629 } 630 631 static bool psb_intel_sdvo_set_active_outputs(struct psb_intel_sdvo *psb_intel_sdvo, 632 u16 outputs) 633 { 634 return psb_intel_sdvo_set_value(psb_intel_sdvo, 635 SDVO_CMD_SET_ACTIVE_OUTPUTS, 636 &outputs, sizeof(outputs)); 637 } 638 639 static bool psb_intel_sdvo_set_encoder_power_state(struct psb_intel_sdvo *psb_intel_sdvo, 640 int mode) 641 { 642 u8 state = SDVO_ENCODER_STATE_ON; 643 644 switch (mode) { 645 case DRM_MODE_DPMS_ON: 646 state = SDVO_ENCODER_STATE_ON; 647 break; 648 case DRM_MODE_DPMS_STANDBY: 649 state = SDVO_ENCODER_STATE_STANDBY; 650 break; 651 case DRM_MODE_DPMS_SUSPEND: 652 state = SDVO_ENCODER_STATE_SUSPEND; 653 break; 654 case DRM_MODE_DPMS_OFF: 655 state = SDVO_ENCODER_STATE_OFF; 656 break; 657 } 658 659 return psb_intel_sdvo_set_value(psb_intel_sdvo, 660 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state)); 661 } 662 663 static bool psb_intel_sdvo_get_input_pixel_clock_range(struct psb_intel_sdvo *psb_intel_sdvo, 664 int *clock_min, 665 int *clock_max) 666 { 667 struct psb_intel_sdvo_pixel_clock_range clocks; 668 669 BUILD_BUG_ON(sizeof(clocks) != 4); 670 if (!psb_intel_sdvo_get_value(psb_intel_sdvo, 671 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, 672 &clocks, sizeof(clocks))) 673 return false; 674 675 /* Convert the values from units of 10 kHz to kHz. */ 676 *clock_min = clocks.min * 10; 677 *clock_max = clocks.max * 10; 678 return true; 679 } 680 681 static bool psb_intel_sdvo_set_target_output(struct psb_intel_sdvo *psb_intel_sdvo, 682 u16 outputs) 683 { 684 return psb_intel_sdvo_set_value(psb_intel_sdvo, 685 SDVO_CMD_SET_TARGET_OUTPUT, 686 &outputs, sizeof(outputs)); 687 } 688 689 static bool psb_intel_sdvo_set_timing(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd, 690 struct psb_intel_sdvo_dtd *dtd) 691 { 692 return psb_intel_sdvo_set_value(psb_intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && 693 psb_intel_sdvo_set_value(psb_intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 694 } 695 696 static bool psb_intel_sdvo_set_input_timing(struct psb_intel_sdvo *psb_intel_sdvo, 697 struct psb_intel_sdvo_dtd *dtd) 698 { 699 return psb_intel_sdvo_set_timing(psb_intel_sdvo, 700 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); 701 } 702 703 static bool psb_intel_sdvo_set_output_timing(struct psb_intel_sdvo *psb_intel_sdvo, 704 struct psb_intel_sdvo_dtd *dtd) 705 { 706 return psb_intel_sdvo_set_timing(psb_intel_sdvo, 707 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); 708 } 709 710 static bool 711 psb_intel_sdvo_create_preferred_input_timing(struct psb_intel_sdvo *psb_intel_sdvo, 712 uint16_t clock, 713 uint16_t width, 714 uint16_t height) 715 { 716 struct psb_intel_sdvo_preferred_input_timing_args args; 717 718 memset(&args, 0, sizeof(args)); 719 args.clock = clock; 720 args.width = width; 721 args.height = height; 722 args.interlace = 0; 723 724 if (psb_intel_sdvo->is_lvds && 725 (psb_intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width || 726 psb_intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height)) 727 args.scaled = 1; 728 729 return psb_intel_sdvo_set_value(psb_intel_sdvo, 730 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, 731 &args, sizeof(args)); 732 } 733 734 static bool psb_intel_sdvo_get_preferred_input_timing(struct psb_intel_sdvo *psb_intel_sdvo, 735 struct psb_intel_sdvo_dtd *dtd) 736 { 737 BUILD_BUG_ON(sizeof(dtd->part1) != 8); 738 BUILD_BUG_ON(sizeof(dtd->part2) != 8); 739 return psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, 740 &dtd->part1, sizeof(dtd->part1)) && 741 psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, 742 &dtd->part2, sizeof(dtd->part2)); 743 } 744 745 static bool psb_intel_sdvo_set_clock_rate_mult(struct psb_intel_sdvo *psb_intel_sdvo, u8 val) 746 { 747 return psb_intel_sdvo_set_value(psb_intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); 748 } 749 750 static void psb_intel_sdvo_get_dtd_from_mode(struct psb_intel_sdvo_dtd *dtd, 751 const struct drm_display_mode *mode) 752 { 753 uint16_t width, height; 754 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len; 755 uint16_t h_sync_offset, v_sync_offset; 756 757 width = mode->crtc_hdisplay; 758 height = mode->crtc_vdisplay; 759 760 /* do some mode translations */ 761 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start; 762 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 763 764 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start; 765 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 766 767 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start; 768 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start; 769 770 dtd->part1.clock = mode->clock / 10; 771 dtd->part1.h_active = width & 0xff; 772 dtd->part1.h_blank = h_blank_len & 0xff; 773 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | 774 ((h_blank_len >> 8) & 0xf); 775 dtd->part1.v_active = height & 0xff; 776 dtd->part1.v_blank = v_blank_len & 0xff; 777 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | 778 ((v_blank_len >> 8) & 0xf); 779 780 dtd->part2.h_sync_off = h_sync_offset & 0xff; 781 dtd->part2.h_sync_width = h_sync_len & 0xff; 782 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | 783 (v_sync_len & 0xf); 784 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) | 785 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) | 786 ((v_sync_len & 0x30) >> 4); 787 788 dtd->part2.dtd_flags = 0x18; 789 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 790 dtd->part2.dtd_flags |= 0x2; 791 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 792 dtd->part2.dtd_flags |= 0x4; 793 794 dtd->part2.sdvo_flags = 0; 795 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0; 796 dtd->part2.reserved = 0; 797 } 798 799 static void psb_intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode, 800 const struct psb_intel_sdvo_dtd *dtd) 801 { 802 mode->hdisplay = dtd->part1.h_active; 803 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; 804 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off; 805 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; 806 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width; 807 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; 808 mode->htotal = mode->hdisplay + dtd->part1.h_blank; 809 mode->htotal += (dtd->part1.h_high & 0xf) << 8; 810 811 mode->vdisplay = dtd->part1.v_active; 812 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; 813 mode->vsync_start = mode->vdisplay; 814 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; 815 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; 816 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0; 817 mode->vsync_end = mode->vsync_start + 818 (dtd->part2.v_sync_off_width & 0xf); 819 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4; 820 mode->vtotal = mode->vdisplay + dtd->part1.v_blank; 821 mode->vtotal += (dtd->part1.v_high & 0xf) << 8; 822 823 mode->clock = dtd->part1.clock * 10; 824 825 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); 826 if (dtd->part2.dtd_flags & 0x2) 827 mode->flags |= DRM_MODE_FLAG_PHSYNC; 828 if (dtd->part2.dtd_flags & 0x4) 829 mode->flags |= DRM_MODE_FLAG_PVSYNC; 830 } 831 832 static bool psb_intel_sdvo_check_supp_encode(struct psb_intel_sdvo *psb_intel_sdvo) 833 { 834 struct psb_intel_sdvo_encode encode; 835 836 BUILD_BUG_ON(sizeof(encode) != 2); 837 return psb_intel_sdvo_get_value(psb_intel_sdvo, 838 SDVO_CMD_GET_SUPP_ENCODE, 839 &encode, sizeof(encode)); 840 } 841 842 static bool psb_intel_sdvo_set_encode(struct psb_intel_sdvo *psb_intel_sdvo, 843 uint8_t mode) 844 { 845 return psb_intel_sdvo_set_value(psb_intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1); 846 } 847 848 static bool psb_intel_sdvo_set_colorimetry(struct psb_intel_sdvo *psb_intel_sdvo, 849 uint8_t mode) 850 { 851 return psb_intel_sdvo_set_value(psb_intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1); 852 } 853 854 #if 0 855 static void psb_intel_sdvo_dump_hdmi_buf(struct psb_intel_sdvo *psb_intel_sdvo) 856 { 857 int i, j; 858 uint8_t set_buf_index[2]; 859 uint8_t av_split; 860 uint8_t buf_size; 861 uint8_t buf[48]; 862 uint8_t *pos; 863 864 psb_intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1); 865 866 for (i = 0; i <= av_split; i++) { 867 set_buf_index[0] = i; set_buf_index[1] = 0; 868 psb_intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX, 869 set_buf_index, 2); 870 psb_intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0); 871 psb_intel_sdvo_read_response(encoder, &buf_size, 1); 872 873 pos = buf; 874 for (j = 0; j <= buf_size; j += 8) { 875 psb_intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA, 876 NULL, 0); 877 psb_intel_sdvo_read_response(encoder, pos, 8); 878 pos += 8; 879 } 880 } 881 } 882 #endif 883 884 static bool psb_intel_sdvo_set_avi_infoframe(struct psb_intel_sdvo *psb_intel_sdvo) 885 { 886 DRM_INFO("HDMI is not supported yet"); 887 888 return false; 889 } 890 891 static bool psb_intel_sdvo_set_tv_format(struct psb_intel_sdvo *psb_intel_sdvo) 892 { 893 struct psb_intel_sdvo_tv_format format; 894 uint32_t format_map; 895 896 format_map = 1 << psb_intel_sdvo->tv_format_index; 897 memset(&format, 0, sizeof(format)); 898 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map))); 899 900 BUILD_BUG_ON(sizeof(format) != 6); 901 return psb_intel_sdvo_set_value(psb_intel_sdvo, 902 SDVO_CMD_SET_TV_FORMAT, 903 &format, sizeof(format)); 904 } 905 906 static bool 907 psb_intel_sdvo_set_output_timings_from_mode(struct psb_intel_sdvo *psb_intel_sdvo, 908 const struct drm_display_mode *mode) 909 { 910 struct psb_intel_sdvo_dtd output_dtd; 911 912 if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo, 913 psb_intel_sdvo->attached_output)) 914 return false; 915 916 psb_intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 917 if (!psb_intel_sdvo_set_output_timing(psb_intel_sdvo, &output_dtd)) 918 return false; 919 920 return true; 921 } 922 923 static bool 924 psb_intel_sdvo_set_input_timings_for_mode(struct psb_intel_sdvo *psb_intel_sdvo, 925 const struct drm_display_mode *mode, 926 struct drm_display_mode *adjusted_mode) 927 { 928 /* Reset the input timing to the screen. Assume always input 0. */ 929 if (!psb_intel_sdvo_set_target_input(psb_intel_sdvo)) 930 return false; 931 932 if (!psb_intel_sdvo_create_preferred_input_timing(psb_intel_sdvo, 933 mode->clock / 10, 934 mode->hdisplay, 935 mode->vdisplay)) 936 return false; 937 938 if (!psb_intel_sdvo_get_preferred_input_timing(psb_intel_sdvo, 939 &psb_intel_sdvo->input_dtd)) 940 return false; 941 942 psb_intel_sdvo_get_mode_from_dtd(adjusted_mode, &psb_intel_sdvo->input_dtd); 943 944 drm_mode_set_crtcinfo(adjusted_mode, 0); 945 return true; 946 } 947 948 static bool psb_intel_sdvo_mode_fixup(struct drm_encoder *encoder, 949 const struct drm_display_mode *mode, 950 struct drm_display_mode *adjusted_mode) 951 { 952 struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder); 953 954 /* We need to construct preferred input timings based on our 955 * output timings. To do that, we have to set the output 956 * timings, even though this isn't really the right place in 957 * the sequence to do it. Oh well. 958 */ 959 if (psb_intel_sdvo->is_tv) { 960 if (!psb_intel_sdvo_set_output_timings_from_mode(psb_intel_sdvo, mode)) 961 return false; 962 963 (void) psb_intel_sdvo_set_input_timings_for_mode(psb_intel_sdvo, 964 mode, 965 adjusted_mode); 966 } else if (psb_intel_sdvo->is_lvds) { 967 if (!psb_intel_sdvo_set_output_timings_from_mode(psb_intel_sdvo, 968 psb_intel_sdvo->sdvo_lvds_fixed_mode)) 969 return false; 970 971 (void) psb_intel_sdvo_set_input_timings_for_mode(psb_intel_sdvo, 972 mode, 973 adjusted_mode); 974 } 975 976 /* Make the CRTC code factor in the SDVO pixel multiplier. The 977 * SDVO device will factor out the multiplier during mode_set. 978 */ 979 psb_intel_sdvo->pixel_multiplier = 980 psb_intel_sdvo_get_pixel_multiplier(adjusted_mode); 981 adjusted_mode->clock *= psb_intel_sdvo->pixel_multiplier; 982 983 return true; 984 } 985 986 static void psb_intel_sdvo_mode_set(struct drm_encoder *encoder, 987 struct drm_display_mode *mode, 988 struct drm_display_mode *adjusted_mode) 989 { 990 struct drm_device *dev = encoder->dev; 991 struct drm_crtc *crtc = encoder->crtc; 992 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 993 struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder); 994 u32 sdvox; 995 struct psb_intel_sdvo_in_out_map in_out; 996 struct psb_intel_sdvo_dtd input_dtd; 997 int rate; 998 int need_aux = IS_MRST(dev) ? 1 : 0; 999 1000 if (!mode) 1001 return; 1002 1003 /* First, set the input mapping for the first input to our controlled 1004 * output. This is only correct if we're a single-input device, in 1005 * which case the first input is the output from the appropriate SDVO 1006 * channel on the motherboard. In a two-input device, the first input 1007 * will be SDVOB and the second SDVOC. 1008 */ 1009 in_out.in0 = psb_intel_sdvo->attached_output; 1010 in_out.in1 = 0; 1011 1012 psb_intel_sdvo_set_value(psb_intel_sdvo, 1013 SDVO_CMD_SET_IN_OUT_MAP, 1014 &in_out, sizeof(in_out)); 1015 1016 /* Set the output timings to the screen */ 1017 if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo, 1018 psb_intel_sdvo->attached_output)) 1019 return; 1020 1021 /* We have tried to get input timing in mode_fixup, and filled into 1022 * adjusted_mode. 1023 */ 1024 if (psb_intel_sdvo->is_tv || psb_intel_sdvo->is_lvds) { 1025 input_dtd = psb_intel_sdvo->input_dtd; 1026 } else { 1027 /* Set the output timing to the screen */ 1028 if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo, 1029 psb_intel_sdvo->attached_output)) 1030 return; 1031 1032 psb_intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); 1033 (void) psb_intel_sdvo_set_output_timing(psb_intel_sdvo, &input_dtd); 1034 } 1035 1036 /* Set the input timing to the screen. Assume always input 0. */ 1037 if (!psb_intel_sdvo_set_target_input(psb_intel_sdvo)) 1038 return; 1039 1040 if (psb_intel_sdvo->has_hdmi_monitor) { 1041 psb_intel_sdvo_set_encode(psb_intel_sdvo, SDVO_ENCODE_HDMI); 1042 psb_intel_sdvo_set_colorimetry(psb_intel_sdvo, 1043 SDVO_COLORIMETRY_RGB256); 1044 psb_intel_sdvo_set_avi_infoframe(psb_intel_sdvo); 1045 } else 1046 psb_intel_sdvo_set_encode(psb_intel_sdvo, SDVO_ENCODE_DVI); 1047 1048 if (psb_intel_sdvo->is_tv && 1049 !psb_intel_sdvo_set_tv_format(psb_intel_sdvo)) 1050 return; 1051 1052 (void) psb_intel_sdvo_set_input_timing(psb_intel_sdvo, &input_dtd); 1053 1054 switch (psb_intel_sdvo->pixel_multiplier) { 1055 default: 1056 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; 1057 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break; 1058 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break; 1059 } 1060 if (!psb_intel_sdvo_set_clock_rate_mult(psb_intel_sdvo, rate)) 1061 return; 1062 1063 /* Set the SDVO control regs. */ 1064 if (need_aux) 1065 sdvox = REG_READ_AUX(psb_intel_sdvo->sdvo_reg); 1066 else 1067 sdvox = REG_READ(psb_intel_sdvo->sdvo_reg); 1068 1069 switch (psb_intel_sdvo->sdvo_reg) { 1070 case SDVOB: 1071 sdvox &= SDVOB_PRESERVE_MASK; 1072 break; 1073 case SDVOC: 1074 sdvox &= SDVOC_PRESERVE_MASK; 1075 break; 1076 } 1077 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; 1078 1079 if (gma_crtc->pipe == 1) 1080 sdvox |= SDVO_PIPE_B_SELECT; 1081 if (psb_intel_sdvo->has_hdmi_audio) 1082 sdvox |= SDVO_AUDIO_ENABLE; 1083 1084 /* FIXME: Check if this is needed for PSB 1085 sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT; 1086 */ 1087 1088 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL) 1089 sdvox |= SDVO_STALL_SELECT; 1090 psb_intel_sdvo_write_sdvox(psb_intel_sdvo, sdvox); 1091 } 1092 1093 static void psb_intel_sdvo_dpms(struct drm_encoder *encoder, int mode) 1094 { 1095 struct drm_device *dev = encoder->dev; 1096 struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder); 1097 u32 temp; 1098 int i; 1099 int need_aux = IS_MRST(dev) ? 1 : 0; 1100 1101 switch (mode) { 1102 case DRM_MODE_DPMS_ON: 1103 DRM_DEBUG("DPMS_ON"); 1104 break; 1105 case DRM_MODE_DPMS_OFF: 1106 DRM_DEBUG("DPMS_OFF"); 1107 break; 1108 default: 1109 DRM_DEBUG("DPMS: %d", mode); 1110 } 1111 1112 if (mode != DRM_MODE_DPMS_ON) { 1113 psb_intel_sdvo_set_active_outputs(psb_intel_sdvo, 0); 1114 if (0) 1115 psb_intel_sdvo_set_encoder_power_state(psb_intel_sdvo, mode); 1116 1117 if (mode == DRM_MODE_DPMS_OFF) { 1118 if (need_aux) 1119 temp = REG_READ_AUX(psb_intel_sdvo->sdvo_reg); 1120 else 1121 temp = REG_READ(psb_intel_sdvo->sdvo_reg); 1122 1123 if ((temp & SDVO_ENABLE) != 0) { 1124 psb_intel_sdvo_write_sdvox(psb_intel_sdvo, temp & ~SDVO_ENABLE); 1125 } 1126 } 1127 } else { 1128 bool input1, input2; 1129 u8 status; 1130 1131 if (need_aux) 1132 temp = REG_READ_AUX(psb_intel_sdvo->sdvo_reg); 1133 else 1134 temp = REG_READ(psb_intel_sdvo->sdvo_reg); 1135 1136 if ((temp & SDVO_ENABLE) == 0) 1137 psb_intel_sdvo_write_sdvox(psb_intel_sdvo, temp | SDVO_ENABLE); 1138 1139 for (i = 0; i < 2; i++) 1140 gma_wait_for_vblank(dev); 1141 1142 status = psb_intel_sdvo_get_trained_inputs(psb_intel_sdvo, &input1, &input2); 1143 /* Warn if the device reported failure to sync. 1144 * A lot of SDVO devices fail to notify of sync, but it's 1145 * a given it the status is a success, we succeeded. 1146 */ 1147 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) { 1148 DRM_DEBUG_KMS("First %s output reported failure to " 1149 "sync\n", SDVO_NAME(psb_intel_sdvo)); 1150 } 1151 1152 if (0) 1153 psb_intel_sdvo_set_encoder_power_state(psb_intel_sdvo, mode); 1154 psb_intel_sdvo_set_active_outputs(psb_intel_sdvo, psb_intel_sdvo->attached_output); 1155 } 1156 return; 1157 } 1158 1159 static enum drm_mode_status psb_intel_sdvo_mode_valid(struct drm_connector *connector, 1160 struct drm_display_mode *mode) 1161 { 1162 struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector); 1163 1164 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1165 return MODE_NO_DBLESCAN; 1166 1167 if (psb_intel_sdvo->pixel_clock_min > mode->clock) 1168 return MODE_CLOCK_LOW; 1169 1170 if (psb_intel_sdvo->pixel_clock_max < mode->clock) 1171 return MODE_CLOCK_HIGH; 1172 1173 if (psb_intel_sdvo->is_lvds) { 1174 if (mode->hdisplay > psb_intel_sdvo->sdvo_lvds_fixed_mode->hdisplay) 1175 return MODE_PANEL; 1176 1177 if (mode->vdisplay > psb_intel_sdvo->sdvo_lvds_fixed_mode->vdisplay) 1178 return MODE_PANEL; 1179 } 1180 1181 return MODE_OK; 1182 } 1183 1184 static bool psb_intel_sdvo_get_capabilities(struct psb_intel_sdvo *psb_intel_sdvo, struct psb_intel_sdvo_caps *caps) 1185 { 1186 BUILD_BUG_ON(sizeof(*caps) != 8); 1187 if (!psb_intel_sdvo_get_value(psb_intel_sdvo, 1188 SDVO_CMD_GET_DEVICE_CAPS, 1189 caps, sizeof(*caps))) 1190 return false; 1191 1192 DRM_DEBUG_KMS("SDVO capabilities:\n" 1193 " vendor_id: %d\n" 1194 " device_id: %d\n" 1195 " device_rev_id: %d\n" 1196 " sdvo_version_major: %d\n" 1197 " sdvo_version_minor: %d\n" 1198 " sdvo_inputs_mask: %d\n" 1199 " smooth_scaling: %d\n" 1200 " sharp_scaling: %d\n" 1201 " up_scaling: %d\n" 1202 " down_scaling: %d\n" 1203 " stall_support: %d\n" 1204 " output_flags: %d\n", 1205 caps->vendor_id, 1206 caps->device_id, 1207 caps->device_rev_id, 1208 caps->sdvo_version_major, 1209 caps->sdvo_version_minor, 1210 caps->sdvo_inputs_mask, 1211 caps->smooth_scaling, 1212 caps->sharp_scaling, 1213 caps->up_scaling, 1214 caps->down_scaling, 1215 caps->stall_support, 1216 caps->output_flags); 1217 1218 return true; 1219 } 1220 1221 static bool 1222 psb_intel_sdvo_multifunc_encoder(struct psb_intel_sdvo *psb_intel_sdvo) 1223 { 1224 /* Is there more than one type of output? */ 1225 int caps = psb_intel_sdvo->caps.output_flags & 0xf; 1226 return caps & -caps; 1227 } 1228 1229 static struct edid * 1230 psb_intel_sdvo_get_edid(struct drm_connector *connector) 1231 { 1232 struct psb_intel_sdvo *sdvo = intel_attached_sdvo(connector); 1233 return drm_get_edid(connector, &sdvo->ddc); 1234 } 1235 1236 /* Mac mini hack -- use the same DDC as the analog connector */ 1237 static struct edid * 1238 psb_intel_sdvo_get_analog_edid(struct drm_connector *connector) 1239 { 1240 struct drm_psb_private *dev_priv = to_drm_psb_private(connector->dev); 1241 1242 return drm_get_edid(connector, 1243 &dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter); 1244 } 1245 1246 static enum drm_connector_status 1247 psb_intel_sdvo_hdmi_sink_detect(struct drm_connector *connector) 1248 { 1249 struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector); 1250 enum drm_connector_status status; 1251 struct edid *edid; 1252 1253 edid = psb_intel_sdvo_get_edid(connector); 1254 1255 if (edid == NULL && psb_intel_sdvo_multifunc_encoder(psb_intel_sdvo)) { 1256 u8 ddc, saved_ddc = psb_intel_sdvo->ddc_bus; 1257 1258 /* 1259 * Don't use the 1 as the argument of DDC bus switch to get 1260 * the EDID. It is used for SDVO SPD ROM. 1261 */ 1262 for (ddc = psb_intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) { 1263 psb_intel_sdvo->ddc_bus = ddc; 1264 edid = psb_intel_sdvo_get_edid(connector); 1265 if (edid) 1266 break; 1267 } 1268 /* 1269 * If we found the EDID on the other bus, 1270 * assume that is the correct DDC bus. 1271 */ 1272 if (edid == NULL) 1273 psb_intel_sdvo->ddc_bus = saved_ddc; 1274 } 1275 1276 /* 1277 * When there is no edid and no monitor is connected with VGA 1278 * port, try to use the CRT ddc to read the EDID for DVI-connector. 1279 */ 1280 if (edid == NULL) 1281 edid = psb_intel_sdvo_get_analog_edid(connector); 1282 1283 status = connector_status_unknown; 1284 if (edid != NULL) { 1285 /* DDC bus is shared, match EDID to connector type */ 1286 if (edid->input & DRM_EDID_INPUT_DIGITAL) { 1287 status = connector_status_connected; 1288 if (psb_intel_sdvo->is_hdmi) { 1289 psb_intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid); 1290 psb_intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid); 1291 } 1292 } else 1293 status = connector_status_disconnected; 1294 kfree(edid); 1295 } 1296 1297 if (status == connector_status_connected) { 1298 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector); 1299 if (psb_intel_sdvo_connector->force_audio) 1300 psb_intel_sdvo->has_hdmi_audio = psb_intel_sdvo_connector->force_audio > 0; 1301 } 1302 1303 return status; 1304 } 1305 1306 static enum drm_connector_status 1307 psb_intel_sdvo_detect(struct drm_connector *connector, bool force) 1308 { 1309 uint16_t response; 1310 struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector); 1311 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector); 1312 enum drm_connector_status ret; 1313 1314 if (!psb_intel_sdvo_write_cmd(psb_intel_sdvo, 1315 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0)) 1316 return connector_status_unknown; 1317 1318 /* add 30ms delay when the output type might be TV */ 1319 if (psb_intel_sdvo->caps.output_flags & 1320 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_CVBS0)) 1321 mdelay(30); 1322 1323 if (!psb_intel_sdvo_read_response(psb_intel_sdvo, &response, 2)) 1324 return connector_status_unknown; 1325 1326 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n", 1327 response & 0xff, response >> 8, 1328 psb_intel_sdvo_connector->output_flag); 1329 1330 if (response == 0) 1331 return connector_status_disconnected; 1332 1333 psb_intel_sdvo->attached_output = response; 1334 1335 psb_intel_sdvo->has_hdmi_monitor = false; 1336 psb_intel_sdvo->has_hdmi_audio = false; 1337 1338 if ((psb_intel_sdvo_connector->output_flag & response) == 0) 1339 ret = connector_status_disconnected; 1340 else if (IS_TMDS(psb_intel_sdvo_connector)) 1341 ret = psb_intel_sdvo_hdmi_sink_detect(connector); 1342 else { 1343 struct edid *edid; 1344 1345 /* if we have an edid check it matches the connection */ 1346 edid = psb_intel_sdvo_get_edid(connector); 1347 if (edid == NULL) 1348 edid = psb_intel_sdvo_get_analog_edid(connector); 1349 if (edid != NULL) { 1350 if (edid->input & DRM_EDID_INPUT_DIGITAL) 1351 ret = connector_status_disconnected; 1352 else 1353 ret = connector_status_connected; 1354 kfree(edid); 1355 } else 1356 ret = connector_status_connected; 1357 } 1358 1359 /* May update encoder flag for like clock for SDVO TV, etc.*/ 1360 if (ret == connector_status_connected) { 1361 psb_intel_sdvo->is_tv = false; 1362 psb_intel_sdvo->is_lvds = false; 1363 psb_intel_sdvo->base.needs_tv_clock = false; 1364 1365 if (response & SDVO_TV_MASK) { 1366 psb_intel_sdvo->is_tv = true; 1367 psb_intel_sdvo->base.needs_tv_clock = true; 1368 } 1369 if (response & SDVO_LVDS_MASK) 1370 psb_intel_sdvo->is_lvds = psb_intel_sdvo->sdvo_lvds_fixed_mode != NULL; 1371 } 1372 1373 return ret; 1374 } 1375 1376 static void psb_intel_sdvo_get_ddc_modes(struct drm_connector *connector) 1377 { 1378 struct edid *edid; 1379 1380 /* set the bus switch and get the modes */ 1381 edid = psb_intel_sdvo_get_edid(connector); 1382 1383 /* 1384 * Mac mini hack. On this device, the DVI-I connector shares one DDC 1385 * link between analog and digital outputs. So, if the regular SDVO 1386 * DDC fails, check to see if the analog output is disconnected, in 1387 * which case we'll look there for the digital DDC data. 1388 */ 1389 if (edid == NULL) 1390 edid = psb_intel_sdvo_get_analog_edid(connector); 1391 1392 if (edid != NULL) { 1393 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector); 1394 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL); 1395 bool connector_is_digital = !!IS_TMDS(psb_intel_sdvo_connector); 1396 1397 if (connector_is_digital == monitor_is_digital) { 1398 drm_connector_update_edid_property(connector, edid); 1399 drm_add_edid_modes(connector, edid); 1400 } 1401 1402 kfree(edid); 1403 } 1404 } 1405 1406 /* 1407 * Set of SDVO TV modes. 1408 * Note! This is in reply order (see loop in get_tv_modes). 1409 * XXX: all 60Hz refresh? 1410 */ 1411 static const struct drm_display_mode sdvo_tv_modes[] = { 1412 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384, 1413 416, 0, 200, 201, 232, 233, 0, 1414 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1415 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384, 1416 416, 0, 240, 241, 272, 273, 0, 1417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1418 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464, 1419 496, 0, 300, 301, 332, 333, 0, 1420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1421 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704, 1422 736, 0, 350, 351, 382, 383, 0, 1423 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1424 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704, 1425 736, 0, 400, 401, 432, 433, 0, 1426 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1427 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704, 1428 736, 0, 480, 481, 512, 513, 0, 1429 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1430 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768, 1431 800, 0, 480, 481, 512, 513, 0, 1432 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1433 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768, 1434 800, 0, 576, 577, 608, 609, 0, 1435 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1436 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784, 1437 816, 0, 350, 351, 382, 383, 0, 1438 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1439 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784, 1440 816, 0, 400, 401, 432, 433, 0, 1441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1442 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784, 1443 816, 0, 480, 481, 512, 513, 0, 1444 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1445 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784, 1446 816, 0, 540, 541, 572, 573, 0, 1447 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1448 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784, 1449 816, 0, 576, 577, 608, 609, 0, 1450 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1451 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832, 1452 864, 0, 576, 577, 608, 609, 0, 1453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1454 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864, 1455 896, 0, 600, 601, 632, 633, 0, 1456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1457 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896, 1458 928, 0, 624, 625, 656, 657, 0, 1459 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1460 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984, 1461 1016, 0, 766, 767, 798, 799, 0, 1462 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1463 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088, 1464 1120, 0, 768, 769, 800, 801, 0, 1465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1466 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344, 1467 1376, 0, 1024, 1025, 1056, 1057, 0, 1468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1469 }; 1470 1471 static void psb_intel_sdvo_get_tv_modes(struct drm_connector *connector) 1472 { 1473 struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector); 1474 struct psb_intel_sdvo_sdtv_resolution_request tv_res; 1475 uint32_t reply = 0, format_map = 0; 1476 int i; 1477 1478 /* Read the list of supported input resolutions for the selected TV 1479 * format. 1480 */ 1481 format_map = 1 << psb_intel_sdvo->tv_format_index; 1482 memcpy(&tv_res, &format_map, 1483 min(sizeof(format_map), sizeof(struct psb_intel_sdvo_sdtv_resolution_request))); 1484 1485 if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo, psb_intel_sdvo->attached_output)) 1486 return; 1487 1488 BUILD_BUG_ON(sizeof(tv_res) != 3); 1489 if (!psb_intel_sdvo_write_cmd(psb_intel_sdvo, 1490 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, 1491 &tv_res, sizeof(tv_res))) 1492 return; 1493 if (!psb_intel_sdvo_read_response(psb_intel_sdvo, &reply, 3)) 1494 return; 1495 1496 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) 1497 if (reply & (1 << i)) { 1498 struct drm_display_mode *nmode; 1499 nmode = drm_mode_duplicate(connector->dev, 1500 &sdvo_tv_modes[i]); 1501 if (nmode) 1502 drm_mode_probed_add(connector, nmode); 1503 } 1504 } 1505 1506 static void psb_intel_sdvo_get_lvds_modes(struct drm_connector *connector) 1507 { 1508 struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector); 1509 struct drm_psb_private *dev_priv = to_drm_psb_private(connector->dev); 1510 struct drm_display_mode *newmode; 1511 1512 /* 1513 * Attempt to get the mode list from DDC. 1514 * Assume that the preferred modes are 1515 * arranged in priority order. 1516 */ 1517 psb_intel_ddc_get_modes(connector, psb_intel_sdvo->i2c); 1518 if (list_empty(&connector->probed_modes) == false) 1519 goto end; 1520 1521 /* Fetch modes from VBT */ 1522 if (dev_priv->sdvo_lvds_vbt_mode != NULL) { 1523 newmode = drm_mode_duplicate(connector->dev, 1524 dev_priv->sdvo_lvds_vbt_mode); 1525 if (newmode != NULL) { 1526 /* Guarantee the mode is preferred */ 1527 newmode->type = (DRM_MODE_TYPE_PREFERRED | 1528 DRM_MODE_TYPE_DRIVER); 1529 drm_mode_probed_add(connector, newmode); 1530 } 1531 } 1532 1533 end: 1534 list_for_each_entry(newmode, &connector->probed_modes, head) { 1535 if (newmode->type & DRM_MODE_TYPE_PREFERRED) { 1536 psb_intel_sdvo->sdvo_lvds_fixed_mode = 1537 drm_mode_duplicate(connector->dev, newmode); 1538 1539 drm_mode_set_crtcinfo(psb_intel_sdvo->sdvo_lvds_fixed_mode, 1540 0); 1541 1542 psb_intel_sdvo->is_lvds = true; 1543 break; 1544 } 1545 } 1546 1547 } 1548 1549 static int psb_intel_sdvo_get_modes(struct drm_connector *connector) 1550 { 1551 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector); 1552 1553 if (IS_TV(psb_intel_sdvo_connector)) 1554 psb_intel_sdvo_get_tv_modes(connector); 1555 else if (IS_LVDS(psb_intel_sdvo_connector)) 1556 psb_intel_sdvo_get_lvds_modes(connector); 1557 else 1558 psb_intel_sdvo_get_ddc_modes(connector); 1559 1560 return !list_empty(&connector->probed_modes); 1561 } 1562 1563 static void psb_intel_sdvo_destroy(struct drm_connector *connector) 1564 { 1565 struct gma_connector *gma_connector = to_gma_connector(connector); 1566 1567 drm_connector_cleanup(connector); 1568 kfree(gma_connector); 1569 } 1570 1571 static bool psb_intel_sdvo_detect_hdmi_audio(struct drm_connector *connector) 1572 { 1573 struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector); 1574 struct edid *edid; 1575 bool has_audio = false; 1576 1577 if (!psb_intel_sdvo->is_hdmi) 1578 return false; 1579 1580 edid = psb_intel_sdvo_get_edid(connector); 1581 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL) 1582 has_audio = drm_detect_monitor_audio(edid); 1583 1584 return has_audio; 1585 } 1586 1587 static int 1588 psb_intel_sdvo_set_property(struct drm_connector *connector, 1589 struct drm_property *property, 1590 uint64_t val) 1591 { 1592 struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector); 1593 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector); 1594 struct drm_psb_private *dev_priv = to_drm_psb_private(connector->dev); 1595 uint16_t temp_value; 1596 uint8_t cmd; 1597 int ret; 1598 1599 ret = drm_object_property_set_value(&connector->base, property, val); 1600 if (ret) 1601 return ret; 1602 1603 if (property == dev_priv->force_audio_property) { 1604 int i = val; 1605 bool has_audio; 1606 1607 if (i == psb_intel_sdvo_connector->force_audio) 1608 return 0; 1609 1610 psb_intel_sdvo_connector->force_audio = i; 1611 1612 if (i == 0) 1613 has_audio = psb_intel_sdvo_detect_hdmi_audio(connector); 1614 else 1615 has_audio = i > 0; 1616 1617 if (has_audio == psb_intel_sdvo->has_hdmi_audio) 1618 return 0; 1619 1620 psb_intel_sdvo->has_hdmi_audio = has_audio; 1621 goto done; 1622 } 1623 1624 if (property == dev_priv->broadcast_rgb_property) { 1625 if (val == !!psb_intel_sdvo->color_range) 1626 return 0; 1627 1628 psb_intel_sdvo->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0; 1629 goto done; 1630 } 1631 1632 #define CHECK_PROPERTY(name, NAME) \ 1633 if (psb_intel_sdvo_connector->name == property) { \ 1634 if (psb_intel_sdvo_connector->cur_##name == temp_value) return 0; \ 1635 if (psb_intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \ 1636 cmd = SDVO_CMD_SET_##NAME; \ 1637 psb_intel_sdvo_connector->cur_##name = temp_value; \ 1638 goto set_value; \ 1639 } 1640 1641 if (property == psb_intel_sdvo_connector->tv_format) { 1642 if (val >= ARRAY_SIZE(tv_format_names)) 1643 return -EINVAL; 1644 1645 if (psb_intel_sdvo->tv_format_index == 1646 psb_intel_sdvo_connector->tv_format_supported[val]) 1647 return 0; 1648 1649 psb_intel_sdvo->tv_format_index = psb_intel_sdvo_connector->tv_format_supported[val]; 1650 goto done; 1651 } else if (IS_TV_OR_LVDS(psb_intel_sdvo_connector)) { 1652 temp_value = val; 1653 if (psb_intel_sdvo_connector->left == property) { 1654 drm_object_property_set_value(&connector->base, 1655 psb_intel_sdvo_connector->right, val); 1656 if (psb_intel_sdvo_connector->left_margin == temp_value) 1657 return 0; 1658 1659 psb_intel_sdvo_connector->left_margin = temp_value; 1660 psb_intel_sdvo_connector->right_margin = temp_value; 1661 temp_value = psb_intel_sdvo_connector->max_hscan - 1662 psb_intel_sdvo_connector->left_margin; 1663 cmd = SDVO_CMD_SET_OVERSCAN_H; 1664 goto set_value; 1665 } else if (psb_intel_sdvo_connector->right == property) { 1666 drm_object_property_set_value(&connector->base, 1667 psb_intel_sdvo_connector->left, val); 1668 if (psb_intel_sdvo_connector->right_margin == temp_value) 1669 return 0; 1670 1671 psb_intel_sdvo_connector->left_margin = temp_value; 1672 psb_intel_sdvo_connector->right_margin = temp_value; 1673 temp_value = psb_intel_sdvo_connector->max_hscan - 1674 psb_intel_sdvo_connector->left_margin; 1675 cmd = SDVO_CMD_SET_OVERSCAN_H; 1676 goto set_value; 1677 } else if (psb_intel_sdvo_connector->top == property) { 1678 drm_object_property_set_value(&connector->base, 1679 psb_intel_sdvo_connector->bottom, val); 1680 if (psb_intel_sdvo_connector->top_margin == temp_value) 1681 return 0; 1682 1683 psb_intel_sdvo_connector->top_margin = temp_value; 1684 psb_intel_sdvo_connector->bottom_margin = temp_value; 1685 temp_value = psb_intel_sdvo_connector->max_vscan - 1686 psb_intel_sdvo_connector->top_margin; 1687 cmd = SDVO_CMD_SET_OVERSCAN_V; 1688 goto set_value; 1689 } else if (psb_intel_sdvo_connector->bottom == property) { 1690 drm_object_property_set_value(&connector->base, 1691 psb_intel_sdvo_connector->top, val); 1692 if (psb_intel_sdvo_connector->bottom_margin == temp_value) 1693 return 0; 1694 1695 psb_intel_sdvo_connector->top_margin = temp_value; 1696 psb_intel_sdvo_connector->bottom_margin = temp_value; 1697 temp_value = psb_intel_sdvo_connector->max_vscan - 1698 psb_intel_sdvo_connector->top_margin; 1699 cmd = SDVO_CMD_SET_OVERSCAN_V; 1700 goto set_value; 1701 } 1702 CHECK_PROPERTY(hpos, HPOS) 1703 CHECK_PROPERTY(vpos, VPOS) 1704 CHECK_PROPERTY(saturation, SATURATION) 1705 CHECK_PROPERTY(contrast, CONTRAST) 1706 CHECK_PROPERTY(hue, HUE) 1707 CHECK_PROPERTY(brightness, BRIGHTNESS) 1708 CHECK_PROPERTY(sharpness, SHARPNESS) 1709 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER) 1710 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D) 1711 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE) 1712 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER) 1713 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER) 1714 CHECK_PROPERTY(dot_crawl, DOT_CRAWL) 1715 } 1716 1717 return -EINVAL; /* unknown property */ 1718 1719 set_value: 1720 if (!psb_intel_sdvo_set_value(psb_intel_sdvo, cmd, &temp_value, 2)) 1721 return -EIO; 1722 1723 1724 done: 1725 if (psb_intel_sdvo->base.base.crtc) { 1726 struct drm_crtc *crtc = psb_intel_sdvo->base.base.crtc; 1727 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x, 1728 crtc->y, crtc->primary->fb); 1729 } 1730 1731 return 0; 1732 #undef CHECK_PROPERTY 1733 } 1734 1735 static void psb_intel_sdvo_save(struct drm_connector *connector) 1736 { 1737 struct drm_device *dev = connector->dev; 1738 struct gma_encoder *gma_encoder = gma_attached_encoder(connector); 1739 struct psb_intel_sdvo *sdvo = to_psb_intel_sdvo(&gma_encoder->base); 1740 1741 sdvo->saveSDVO = REG_READ(sdvo->sdvo_reg); 1742 } 1743 1744 static void psb_intel_sdvo_restore(struct drm_connector *connector) 1745 { 1746 struct drm_device *dev = connector->dev; 1747 struct drm_encoder *encoder = &gma_attached_encoder(connector)->base; 1748 struct psb_intel_sdvo *sdvo = to_psb_intel_sdvo(encoder); 1749 struct drm_crtc *crtc = encoder->crtc; 1750 1751 REG_WRITE(sdvo->sdvo_reg, sdvo->saveSDVO); 1752 1753 /* Force a full mode set on the crtc. We're supposed to have the 1754 mode_config lock already. */ 1755 if (connector->status == connector_status_connected) 1756 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, 1757 NULL); 1758 } 1759 1760 static const struct drm_encoder_helper_funcs psb_intel_sdvo_helper_funcs = { 1761 .dpms = psb_intel_sdvo_dpms, 1762 .mode_fixup = psb_intel_sdvo_mode_fixup, 1763 .prepare = gma_encoder_prepare, 1764 .mode_set = psb_intel_sdvo_mode_set, 1765 .commit = gma_encoder_commit, 1766 }; 1767 1768 static const struct drm_connector_funcs psb_intel_sdvo_connector_funcs = { 1769 .dpms = drm_helper_connector_dpms, 1770 .detect = psb_intel_sdvo_detect, 1771 .fill_modes = drm_helper_probe_single_connector_modes, 1772 .set_property = psb_intel_sdvo_set_property, 1773 .destroy = psb_intel_sdvo_destroy, 1774 }; 1775 1776 static const struct drm_connector_helper_funcs psb_intel_sdvo_connector_helper_funcs = { 1777 .get_modes = psb_intel_sdvo_get_modes, 1778 .mode_valid = psb_intel_sdvo_mode_valid, 1779 .best_encoder = gma_best_encoder, 1780 }; 1781 1782 static void psb_intel_sdvo_enc_destroy(struct drm_encoder *encoder) 1783 { 1784 struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder); 1785 1786 if (psb_intel_sdvo->sdvo_lvds_fixed_mode != NULL) 1787 drm_mode_destroy(encoder->dev, 1788 psb_intel_sdvo->sdvo_lvds_fixed_mode); 1789 1790 i2c_del_adapter(&psb_intel_sdvo->ddc); 1791 gma_encoder_destroy(encoder); 1792 } 1793 1794 static const struct drm_encoder_funcs psb_intel_sdvo_enc_funcs = { 1795 .destroy = psb_intel_sdvo_enc_destroy, 1796 }; 1797 1798 static void 1799 psb_intel_sdvo_guess_ddc_bus(struct psb_intel_sdvo *sdvo) 1800 { 1801 /* FIXME: At the moment, ddc_bus = 2 is the only thing that works. 1802 * We need to figure out if this is true for all available poulsbo 1803 * hardware, or if we need to fiddle with the guessing code above. 1804 * The problem might go away if we can parse sdvo mappings from bios */ 1805 sdvo->ddc_bus = 2; 1806 1807 #if 0 1808 uint16_t mask = 0; 1809 unsigned int num_bits; 1810 1811 /* Make a mask of outputs less than or equal to our own priority in the 1812 * list. 1813 */ 1814 switch (sdvo->controlled_output) { 1815 case SDVO_OUTPUT_LVDS1: 1816 mask |= SDVO_OUTPUT_LVDS1; 1817 case SDVO_OUTPUT_LVDS0: 1818 mask |= SDVO_OUTPUT_LVDS0; 1819 case SDVO_OUTPUT_TMDS1: 1820 mask |= SDVO_OUTPUT_TMDS1; 1821 case SDVO_OUTPUT_TMDS0: 1822 mask |= SDVO_OUTPUT_TMDS0; 1823 case SDVO_OUTPUT_RGB1: 1824 mask |= SDVO_OUTPUT_RGB1; 1825 case SDVO_OUTPUT_RGB0: 1826 mask |= SDVO_OUTPUT_RGB0; 1827 break; 1828 } 1829 1830 /* Count bits to find what number we are in the priority list. */ 1831 mask &= sdvo->caps.output_flags; 1832 num_bits = hweight16(mask); 1833 /* If more than 3 outputs, default to DDC bus 3 for now. */ 1834 if (num_bits > 3) 1835 num_bits = 3; 1836 1837 /* Corresponds to SDVO_CONTROL_BUS_DDCx */ 1838 sdvo->ddc_bus = 1 << num_bits; 1839 #endif 1840 } 1841 1842 /* 1843 * Choose the appropriate DDC bus for control bus switch command for this 1844 * SDVO output based on the controlled output. 1845 * 1846 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS 1847 * outputs, then LVDS outputs. 1848 */ 1849 static void 1850 psb_intel_sdvo_select_ddc_bus(struct drm_psb_private *dev_priv, 1851 struct psb_intel_sdvo *sdvo, u32 reg) 1852 { 1853 struct sdvo_device_mapping *mapping; 1854 1855 if (IS_SDVOB(reg)) 1856 mapping = &(dev_priv->sdvo_mappings[0]); 1857 else 1858 mapping = &(dev_priv->sdvo_mappings[1]); 1859 1860 if (mapping->initialized) 1861 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4); 1862 else 1863 psb_intel_sdvo_guess_ddc_bus(sdvo); 1864 } 1865 1866 static void 1867 psb_intel_sdvo_select_i2c_bus(struct drm_psb_private *dev_priv, 1868 struct psb_intel_sdvo *sdvo, u32 reg) 1869 { 1870 struct sdvo_device_mapping *mapping; 1871 u8 pin, speed; 1872 1873 if (IS_SDVOB(reg)) 1874 mapping = &dev_priv->sdvo_mappings[0]; 1875 else 1876 mapping = &dev_priv->sdvo_mappings[1]; 1877 1878 pin = GMBUS_PORT_DPB; 1879 speed = GMBUS_RATE_1MHZ >> 8; 1880 if (mapping->initialized) { 1881 pin = mapping->i2c_pin; 1882 speed = mapping->i2c_speed; 1883 } 1884 1885 if (pin < GMBUS_NUM_PORTS) { 1886 sdvo->i2c = &dev_priv->gmbus[pin].adapter; 1887 gma_intel_gmbus_set_speed(sdvo->i2c, speed); 1888 gma_intel_gmbus_force_bit(sdvo->i2c, true); 1889 } else 1890 sdvo->i2c = &dev_priv->gmbus[GMBUS_PORT_DPB].adapter; 1891 } 1892 1893 static bool 1894 psb_intel_sdvo_is_hdmi_connector(struct psb_intel_sdvo *psb_intel_sdvo, int device) 1895 { 1896 return psb_intel_sdvo_check_supp_encode(psb_intel_sdvo); 1897 } 1898 1899 static u8 1900 psb_intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg) 1901 { 1902 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 1903 struct sdvo_device_mapping *my_mapping, *other_mapping; 1904 1905 if (IS_SDVOB(sdvo_reg)) { 1906 my_mapping = &dev_priv->sdvo_mappings[0]; 1907 other_mapping = &dev_priv->sdvo_mappings[1]; 1908 } else { 1909 my_mapping = &dev_priv->sdvo_mappings[1]; 1910 other_mapping = &dev_priv->sdvo_mappings[0]; 1911 } 1912 1913 /* If the BIOS described our SDVO device, take advantage of it. */ 1914 if (my_mapping->slave_addr) 1915 return my_mapping->slave_addr; 1916 1917 /* If the BIOS only described a different SDVO device, use the 1918 * address that it isn't using. 1919 */ 1920 if (other_mapping->slave_addr) { 1921 if (other_mapping->slave_addr == 0x70) 1922 return 0x72; 1923 else 1924 return 0x70; 1925 } 1926 1927 /* No SDVO device info is found for another DVO port, 1928 * so use mapping assumption we had before BIOS parsing. 1929 */ 1930 if (IS_SDVOB(sdvo_reg)) 1931 return 0x70; 1932 else 1933 return 0x72; 1934 } 1935 1936 static void 1937 psb_intel_sdvo_connector_init(struct psb_intel_sdvo_connector *connector, 1938 struct psb_intel_sdvo *encoder) 1939 { 1940 drm_connector_init(encoder->base.base.dev, 1941 &connector->base.base, 1942 &psb_intel_sdvo_connector_funcs, 1943 connector->base.base.connector_type); 1944 1945 drm_connector_helper_add(&connector->base.base, 1946 &psb_intel_sdvo_connector_helper_funcs); 1947 1948 connector->base.base.interlace_allowed = 0; 1949 connector->base.base.doublescan_allowed = 0; 1950 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB; 1951 1952 connector->base.save = psb_intel_sdvo_save; 1953 connector->base.restore = psb_intel_sdvo_restore; 1954 1955 gma_connector_attach_encoder(&connector->base, &encoder->base); 1956 } 1957 1958 static void 1959 psb_intel_sdvo_add_hdmi_properties(struct psb_intel_sdvo_connector *connector) 1960 { 1961 /* FIXME: We don't support HDMI at the moment 1962 struct drm_device *dev = connector->base.base.dev; 1963 1964 intel_attach_force_audio_property(&connector->base.base); 1965 intel_attach_broadcast_rgb_property(&connector->base.base); 1966 */ 1967 } 1968 1969 static bool 1970 psb_intel_sdvo_dvi_init(struct psb_intel_sdvo *psb_intel_sdvo, int device) 1971 { 1972 struct drm_encoder *encoder = &psb_intel_sdvo->base.base; 1973 struct drm_connector *connector; 1974 struct gma_connector *intel_connector; 1975 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector; 1976 1977 psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL); 1978 if (!psb_intel_sdvo_connector) 1979 return false; 1980 1981 if (device == 0) { 1982 psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0; 1983 psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0; 1984 } else if (device == 1) { 1985 psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1; 1986 psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1; 1987 } 1988 1989 intel_connector = &psb_intel_sdvo_connector->base; 1990 connector = &intel_connector->base; 1991 // connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; 1992 encoder->encoder_type = DRM_MODE_ENCODER_TMDS; 1993 connector->connector_type = DRM_MODE_CONNECTOR_DVID; 1994 1995 if (psb_intel_sdvo_is_hdmi_connector(psb_intel_sdvo, device)) { 1996 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; 1997 psb_intel_sdvo->is_hdmi = true; 1998 } 1999 psb_intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) | 2000 (1 << INTEL_ANALOG_CLONE_BIT)); 2001 2002 psb_intel_sdvo_connector_init(psb_intel_sdvo_connector, psb_intel_sdvo); 2003 if (psb_intel_sdvo->is_hdmi) 2004 psb_intel_sdvo_add_hdmi_properties(psb_intel_sdvo_connector); 2005 2006 return true; 2007 } 2008 2009 static bool 2010 psb_intel_sdvo_tv_init(struct psb_intel_sdvo *psb_intel_sdvo, int type) 2011 { 2012 struct drm_encoder *encoder = &psb_intel_sdvo->base.base; 2013 struct drm_connector *connector; 2014 struct gma_connector *intel_connector; 2015 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector; 2016 2017 psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL); 2018 if (!psb_intel_sdvo_connector) 2019 return false; 2020 2021 intel_connector = &psb_intel_sdvo_connector->base; 2022 connector = &intel_connector->base; 2023 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; 2024 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; 2025 2026 psb_intel_sdvo->controlled_output |= type; 2027 psb_intel_sdvo_connector->output_flag = type; 2028 2029 psb_intel_sdvo->is_tv = true; 2030 psb_intel_sdvo->base.needs_tv_clock = true; 2031 psb_intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT; 2032 2033 psb_intel_sdvo_connector_init(psb_intel_sdvo_connector, psb_intel_sdvo); 2034 2035 if (!psb_intel_sdvo_tv_create_property(psb_intel_sdvo, psb_intel_sdvo_connector, type)) 2036 goto err; 2037 2038 if (!psb_intel_sdvo_create_enhance_property(psb_intel_sdvo, psb_intel_sdvo_connector)) 2039 goto err; 2040 2041 return true; 2042 2043 err: 2044 psb_intel_sdvo_destroy(connector); 2045 return false; 2046 } 2047 2048 static bool 2049 psb_intel_sdvo_analog_init(struct psb_intel_sdvo *psb_intel_sdvo, int device) 2050 { 2051 struct drm_encoder *encoder = &psb_intel_sdvo->base.base; 2052 struct drm_connector *connector; 2053 struct gma_connector *intel_connector; 2054 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector; 2055 2056 psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL); 2057 if (!psb_intel_sdvo_connector) 2058 return false; 2059 2060 intel_connector = &psb_intel_sdvo_connector->base; 2061 connector = &intel_connector->base; 2062 connector->polled = DRM_CONNECTOR_POLL_CONNECT; 2063 encoder->encoder_type = DRM_MODE_ENCODER_DAC; 2064 connector->connector_type = DRM_MODE_CONNECTOR_VGA; 2065 2066 if (device == 0) { 2067 psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0; 2068 psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0; 2069 } else if (device == 1) { 2070 psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1; 2071 psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1; 2072 } 2073 2074 psb_intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) | 2075 (1 << INTEL_ANALOG_CLONE_BIT)); 2076 2077 psb_intel_sdvo_connector_init(psb_intel_sdvo_connector, 2078 psb_intel_sdvo); 2079 return true; 2080 } 2081 2082 static bool 2083 psb_intel_sdvo_lvds_init(struct psb_intel_sdvo *psb_intel_sdvo, int device) 2084 { 2085 struct drm_encoder *encoder = &psb_intel_sdvo->base.base; 2086 struct drm_connector *connector; 2087 struct gma_connector *intel_connector; 2088 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector; 2089 2090 psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL); 2091 if (!psb_intel_sdvo_connector) 2092 return false; 2093 2094 intel_connector = &psb_intel_sdvo_connector->base; 2095 connector = &intel_connector->base; 2096 encoder->encoder_type = DRM_MODE_ENCODER_LVDS; 2097 connector->connector_type = DRM_MODE_CONNECTOR_LVDS; 2098 2099 if (device == 0) { 2100 psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0; 2101 psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0; 2102 } else if (device == 1) { 2103 psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1; 2104 psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1; 2105 } 2106 2107 psb_intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) | 2108 (1 << INTEL_SDVO_LVDS_CLONE_BIT)); 2109 2110 psb_intel_sdvo_connector_init(psb_intel_sdvo_connector, psb_intel_sdvo); 2111 if (!psb_intel_sdvo_create_enhance_property(psb_intel_sdvo, psb_intel_sdvo_connector)) 2112 goto err; 2113 2114 return true; 2115 2116 err: 2117 psb_intel_sdvo_destroy(connector); 2118 return false; 2119 } 2120 2121 static bool 2122 psb_intel_sdvo_output_setup(struct psb_intel_sdvo *psb_intel_sdvo, uint16_t flags) 2123 { 2124 psb_intel_sdvo->is_tv = false; 2125 psb_intel_sdvo->base.needs_tv_clock = false; 2126 psb_intel_sdvo->is_lvds = false; 2127 2128 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/ 2129 2130 if (flags & SDVO_OUTPUT_TMDS0) 2131 if (!psb_intel_sdvo_dvi_init(psb_intel_sdvo, 0)) 2132 return false; 2133 2134 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK) 2135 if (!psb_intel_sdvo_dvi_init(psb_intel_sdvo, 1)) 2136 return false; 2137 2138 /* TV has no XXX1 function block */ 2139 if (flags & SDVO_OUTPUT_SVID0) 2140 if (!psb_intel_sdvo_tv_init(psb_intel_sdvo, SDVO_OUTPUT_SVID0)) 2141 return false; 2142 2143 if (flags & SDVO_OUTPUT_CVBS0) 2144 if (!psb_intel_sdvo_tv_init(psb_intel_sdvo, SDVO_OUTPUT_CVBS0)) 2145 return false; 2146 2147 if (flags & SDVO_OUTPUT_RGB0) 2148 if (!psb_intel_sdvo_analog_init(psb_intel_sdvo, 0)) 2149 return false; 2150 2151 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK) 2152 if (!psb_intel_sdvo_analog_init(psb_intel_sdvo, 1)) 2153 return false; 2154 2155 if (flags & SDVO_OUTPUT_LVDS0) 2156 if (!psb_intel_sdvo_lvds_init(psb_intel_sdvo, 0)) 2157 return false; 2158 2159 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK) 2160 if (!psb_intel_sdvo_lvds_init(psb_intel_sdvo, 1)) 2161 return false; 2162 2163 if ((flags & SDVO_OUTPUT_MASK) == 0) { 2164 unsigned char bytes[2]; 2165 2166 psb_intel_sdvo->controlled_output = 0; 2167 memcpy(bytes, &psb_intel_sdvo->caps.output_flags, 2); 2168 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n", 2169 SDVO_NAME(psb_intel_sdvo), 2170 bytes[0], bytes[1]); 2171 return false; 2172 } 2173 psb_intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1); 2174 2175 return true; 2176 } 2177 2178 static bool psb_intel_sdvo_tv_create_property(struct psb_intel_sdvo *psb_intel_sdvo, 2179 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector, 2180 int type) 2181 { 2182 struct drm_device *dev = psb_intel_sdvo->base.base.dev; 2183 struct psb_intel_sdvo_tv_format format; 2184 uint32_t format_map, i; 2185 2186 if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo, type)) 2187 return false; 2188 2189 BUILD_BUG_ON(sizeof(format) != 6); 2190 if (!psb_intel_sdvo_get_value(psb_intel_sdvo, 2191 SDVO_CMD_GET_SUPPORTED_TV_FORMATS, 2192 &format, sizeof(format))) 2193 return false; 2194 2195 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format))); 2196 2197 if (format_map == 0) 2198 return false; 2199 2200 psb_intel_sdvo_connector->format_supported_num = 0; 2201 for (i = 0 ; i < ARRAY_SIZE(tv_format_names); i++) 2202 if (format_map & (1 << i)) 2203 psb_intel_sdvo_connector->tv_format_supported[psb_intel_sdvo_connector->format_supported_num++] = i; 2204 2205 2206 psb_intel_sdvo_connector->tv_format = 2207 drm_property_create(dev, DRM_MODE_PROP_ENUM, 2208 "mode", psb_intel_sdvo_connector->format_supported_num); 2209 if (!psb_intel_sdvo_connector->tv_format) 2210 return false; 2211 2212 for (i = 0; i < psb_intel_sdvo_connector->format_supported_num; i++) 2213 drm_property_add_enum( 2214 psb_intel_sdvo_connector->tv_format, 2215 i, tv_format_names[psb_intel_sdvo_connector->tv_format_supported[i]]); 2216 2217 psb_intel_sdvo->tv_format_index = psb_intel_sdvo_connector->tv_format_supported[0]; 2218 drm_object_attach_property(&psb_intel_sdvo_connector->base.base.base, 2219 psb_intel_sdvo_connector->tv_format, 0); 2220 return true; 2221 2222 } 2223 2224 #define ENHANCEMENT(name, NAME) do { \ 2225 if (enhancements.name) { \ 2226 if (!psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \ 2227 !psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \ 2228 return false; \ 2229 psb_intel_sdvo_connector->max_##name = data_value[0]; \ 2230 psb_intel_sdvo_connector->cur_##name = response; \ 2231 psb_intel_sdvo_connector->name = \ 2232 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \ 2233 if (!psb_intel_sdvo_connector->name) return false; \ 2234 drm_object_attach_property(&connector->base, \ 2235 psb_intel_sdvo_connector->name, \ 2236 psb_intel_sdvo_connector->cur_##name); \ 2237 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \ 2238 data_value[0], data_value[1], response); \ 2239 } \ 2240 } while(0) 2241 2242 static bool 2243 psb_intel_sdvo_create_enhance_property_tv(struct psb_intel_sdvo *psb_intel_sdvo, 2244 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector, 2245 struct psb_intel_sdvo_enhancements_reply enhancements) 2246 { 2247 struct drm_device *dev = psb_intel_sdvo->base.base.dev; 2248 struct drm_connector *connector = &psb_intel_sdvo_connector->base.base; 2249 uint16_t response, data_value[2]; 2250 2251 /* when horizontal overscan is supported, Add the left/right property */ 2252 if (enhancements.overscan_h) { 2253 if (!psb_intel_sdvo_get_value(psb_intel_sdvo, 2254 SDVO_CMD_GET_MAX_OVERSCAN_H, 2255 &data_value, 4)) 2256 return false; 2257 2258 if (!psb_intel_sdvo_get_value(psb_intel_sdvo, 2259 SDVO_CMD_GET_OVERSCAN_H, 2260 &response, 2)) 2261 return false; 2262 2263 psb_intel_sdvo_connector->max_hscan = data_value[0]; 2264 psb_intel_sdvo_connector->left_margin = data_value[0] - response; 2265 psb_intel_sdvo_connector->right_margin = psb_intel_sdvo_connector->left_margin; 2266 psb_intel_sdvo_connector->left = 2267 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]); 2268 if (!psb_intel_sdvo_connector->left) 2269 return false; 2270 2271 drm_object_attach_property(&connector->base, 2272 psb_intel_sdvo_connector->left, 2273 psb_intel_sdvo_connector->left_margin); 2274 2275 psb_intel_sdvo_connector->right = 2276 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]); 2277 if (!psb_intel_sdvo_connector->right) 2278 return false; 2279 2280 drm_object_attach_property(&connector->base, 2281 psb_intel_sdvo_connector->right, 2282 psb_intel_sdvo_connector->right_margin); 2283 DRM_DEBUG_KMS("h_overscan: max %d, " 2284 "default %d, current %d\n", 2285 data_value[0], data_value[1], response); 2286 } 2287 2288 if (enhancements.overscan_v) { 2289 if (!psb_intel_sdvo_get_value(psb_intel_sdvo, 2290 SDVO_CMD_GET_MAX_OVERSCAN_V, 2291 &data_value, 4)) 2292 return false; 2293 2294 if (!psb_intel_sdvo_get_value(psb_intel_sdvo, 2295 SDVO_CMD_GET_OVERSCAN_V, 2296 &response, 2)) 2297 return false; 2298 2299 psb_intel_sdvo_connector->max_vscan = data_value[0]; 2300 psb_intel_sdvo_connector->top_margin = data_value[0] - response; 2301 psb_intel_sdvo_connector->bottom_margin = psb_intel_sdvo_connector->top_margin; 2302 psb_intel_sdvo_connector->top = 2303 drm_property_create_range(dev, 0, "top_margin", 0, data_value[0]); 2304 if (!psb_intel_sdvo_connector->top) 2305 return false; 2306 2307 drm_object_attach_property(&connector->base, 2308 psb_intel_sdvo_connector->top, 2309 psb_intel_sdvo_connector->top_margin); 2310 2311 psb_intel_sdvo_connector->bottom = 2312 drm_property_create_range(dev, 0, "bottom_margin", 0, data_value[0]); 2313 if (!psb_intel_sdvo_connector->bottom) 2314 return false; 2315 2316 drm_object_attach_property(&connector->base, 2317 psb_intel_sdvo_connector->bottom, 2318 psb_intel_sdvo_connector->bottom_margin); 2319 DRM_DEBUG_KMS("v_overscan: max %d, " 2320 "default %d, current %d\n", 2321 data_value[0], data_value[1], response); 2322 } 2323 2324 ENHANCEMENT(hpos, HPOS); 2325 ENHANCEMENT(vpos, VPOS); 2326 ENHANCEMENT(saturation, SATURATION); 2327 ENHANCEMENT(contrast, CONTRAST); 2328 ENHANCEMENT(hue, HUE); 2329 ENHANCEMENT(sharpness, SHARPNESS); 2330 ENHANCEMENT(brightness, BRIGHTNESS); 2331 ENHANCEMENT(flicker_filter, FLICKER_FILTER); 2332 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); 2333 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D); 2334 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER); 2335 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER); 2336 2337 if (enhancements.dot_crawl) { 2338 if (!psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2)) 2339 return false; 2340 2341 psb_intel_sdvo_connector->max_dot_crawl = 1; 2342 psb_intel_sdvo_connector->cur_dot_crawl = response & 0x1; 2343 psb_intel_sdvo_connector->dot_crawl = 2344 drm_property_create_range(dev, 0, "dot_crawl", 0, 1); 2345 if (!psb_intel_sdvo_connector->dot_crawl) 2346 return false; 2347 2348 drm_object_attach_property(&connector->base, 2349 psb_intel_sdvo_connector->dot_crawl, 2350 psb_intel_sdvo_connector->cur_dot_crawl); 2351 DRM_DEBUG_KMS("dot crawl: current %d\n", response); 2352 } 2353 2354 return true; 2355 } 2356 2357 static bool 2358 psb_intel_sdvo_create_enhance_property_lvds(struct psb_intel_sdvo *psb_intel_sdvo, 2359 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector, 2360 struct psb_intel_sdvo_enhancements_reply enhancements) 2361 { 2362 struct drm_device *dev = psb_intel_sdvo->base.base.dev; 2363 struct drm_connector *connector = &psb_intel_sdvo_connector->base.base; 2364 uint16_t response, data_value[2]; 2365 2366 ENHANCEMENT(brightness, BRIGHTNESS); 2367 2368 return true; 2369 } 2370 #undef ENHANCEMENT 2371 2372 static bool psb_intel_sdvo_create_enhance_property(struct psb_intel_sdvo *psb_intel_sdvo, 2373 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector) 2374 { 2375 union { 2376 struct psb_intel_sdvo_enhancements_reply reply; 2377 uint16_t response; 2378 } enhancements; 2379 2380 BUILD_BUG_ON(sizeof(enhancements) != 2); 2381 2382 enhancements.response = 0; 2383 psb_intel_sdvo_get_value(psb_intel_sdvo, 2384 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, 2385 &enhancements, sizeof(enhancements)); 2386 if (enhancements.response == 0) { 2387 DRM_DEBUG_KMS("No enhancement is supported\n"); 2388 return true; 2389 } 2390 2391 if (IS_TV(psb_intel_sdvo_connector)) 2392 return psb_intel_sdvo_create_enhance_property_tv(psb_intel_sdvo, psb_intel_sdvo_connector, enhancements.reply); 2393 else if(IS_LVDS(psb_intel_sdvo_connector)) 2394 return psb_intel_sdvo_create_enhance_property_lvds(psb_intel_sdvo, psb_intel_sdvo_connector, enhancements.reply); 2395 else 2396 return true; 2397 } 2398 2399 static int psb_intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter, 2400 struct i2c_msg *msgs, 2401 int num) 2402 { 2403 struct psb_intel_sdvo *sdvo = adapter->algo_data; 2404 2405 if (!psb_intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus)) 2406 return -EIO; 2407 2408 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num); 2409 } 2410 2411 static u32 psb_intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter) 2412 { 2413 struct psb_intel_sdvo *sdvo = adapter->algo_data; 2414 return sdvo->i2c->algo->functionality(sdvo->i2c); 2415 } 2416 2417 static const struct i2c_algorithm psb_intel_sdvo_ddc_proxy = { 2418 .master_xfer = psb_intel_sdvo_ddc_proxy_xfer, 2419 .functionality = psb_intel_sdvo_ddc_proxy_func 2420 }; 2421 2422 static bool 2423 psb_intel_sdvo_init_ddc_proxy(struct psb_intel_sdvo *sdvo, 2424 struct drm_device *dev) 2425 { 2426 sdvo->ddc.owner = THIS_MODULE; 2427 sdvo->ddc.class = I2C_CLASS_DDC; 2428 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy"); 2429 sdvo->ddc.dev.parent = dev->dev; 2430 sdvo->ddc.algo_data = sdvo; 2431 sdvo->ddc.algo = &psb_intel_sdvo_ddc_proxy; 2432 2433 return i2c_add_adapter(&sdvo->ddc) == 0; 2434 } 2435 2436 bool psb_intel_sdvo_init(struct drm_device *dev, int sdvo_reg) 2437 { 2438 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 2439 struct gma_encoder *gma_encoder; 2440 struct psb_intel_sdvo *psb_intel_sdvo; 2441 int i; 2442 2443 psb_intel_sdvo = kzalloc(sizeof(struct psb_intel_sdvo), GFP_KERNEL); 2444 if (!psb_intel_sdvo) 2445 return false; 2446 2447 psb_intel_sdvo->sdvo_reg = sdvo_reg; 2448 psb_intel_sdvo->slave_addr = psb_intel_sdvo_get_slave_addr(dev, sdvo_reg) >> 1; 2449 psb_intel_sdvo_select_i2c_bus(dev_priv, psb_intel_sdvo, sdvo_reg); 2450 if (!psb_intel_sdvo_init_ddc_proxy(psb_intel_sdvo, dev)) { 2451 kfree(psb_intel_sdvo); 2452 return false; 2453 } 2454 2455 /* encoder type will be decided later */ 2456 gma_encoder = &psb_intel_sdvo->base; 2457 gma_encoder->type = INTEL_OUTPUT_SDVO; 2458 drm_encoder_init(dev, &gma_encoder->base, &psb_intel_sdvo_enc_funcs, 2459 0, NULL); 2460 2461 /* Read the regs to test if we can talk to the device */ 2462 for (i = 0; i < 0x40; i++) { 2463 u8 byte; 2464 2465 if (!psb_intel_sdvo_read_byte(psb_intel_sdvo, i, &byte)) { 2466 DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n", 2467 IS_SDVOB(sdvo_reg) ? 'B' : 'C'); 2468 goto err; 2469 } 2470 } 2471 2472 if (IS_SDVOB(sdvo_reg)) 2473 dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS; 2474 else 2475 dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS; 2476 2477 drm_encoder_helper_add(&gma_encoder->base, &psb_intel_sdvo_helper_funcs); 2478 2479 /* In default case sdvo lvds is false */ 2480 if (!psb_intel_sdvo_get_capabilities(psb_intel_sdvo, &psb_intel_sdvo->caps)) 2481 goto err; 2482 2483 if (psb_intel_sdvo_output_setup(psb_intel_sdvo, 2484 psb_intel_sdvo->caps.output_flags) != true) { 2485 DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n", 2486 IS_SDVOB(sdvo_reg) ? 'B' : 'C'); 2487 goto err; 2488 } 2489 2490 psb_intel_sdvo_select_ddc_bus(dev_priv, psb_intel_sdvo, sdvo_reg); 2491 2492 /* Set the input timing to the screen. Assume always input 0. */ 2493 if (!psb_intel_sdvo_set_target_input(psb_intel_sdvo)) 2494 goto err; 2495 2496 if (!psb_intel_sdvo_get_input_pixel_clock_range(psb_intel_sdvo, 2497 &psb_intel_sdvo->pixel_clock_min, 2498 &psb_intel_sdvo->pixel_clock_max)) 2499 goto err; 2500 2501 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " 2502 "clock range %dMHz - %dMHz, " 2503 "input 1: %c, input 2: %c, " 2504 "output 1: %c, output 2: %c\n", 2505 SDVO_NAME(psb_intel_sdvo), 2506 psb_intel_sdvo->caps.vendor_id, psb_intel_sdvo->caps.device_id, 2507 psb_intel_sdvo->caps.device_rev_id, 2508 psb_intel_sdvo->pixel_clock_min / 1000, 2509 psb_intel_sdvo->pixel_clock_max / 1000, 2510 (psb_intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N', 2511 (psb_intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N', 2512 /* check currently supported outputs */ 2513 psb_intel_sdvo->caps.output_flags & 2514 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N', 2515 psb_intel_sdvo->caps.output_flags & 2516 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); 2517 return true; 2518 2519 err: 2520 drm_encoder_cleanup(&gma_encoder->base); 2521 i2c_del_adapter(&psb_intel_sdvo->ddc); 2522 kfree(psb_intel_sdvo); 2523 2524 return false; 2525 } 2526