15c49fd3aSAlan Cox /************************************************************************** 25c49fd3aSAlan Cox * Copyright (c) 2007-2011, Intel Corporation. 35c49fd3aSAlan Cox * All Rights Reserved. 45c49fd3aSAlan Cox * 55c49fd3aSAlan Cox * This program is free software; you can redistribute it and/or modify it 65c49fd3aSAlan Cox * under the terms and conditions of the GNU General Public License, 75c49fd3aSAlan Cox * version 2, as published by the Free Software Foundation. 85c49fd3aSAlan Cox * 95c49fd3aSAlan Cox * This program is distributed in the hope it will be useful, but WITHOUT 105c49fd3aSAlan Cox * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 115c49fd3aSAlan Cox * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 125c49fd3aSAlan Cox * more details. 135c49fd3aSAlan Cox * 145c49fd3aSAlan Cox * You should have received a copy of the GNU General Public License along with 155c49fd3aSAlan Cox * this program; if not, write to the Free Software Foundation, Inc., 165c49fd3aSAlan Cox * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 175c49fd3aSAlan Cox * 185c49fd3aSAlan Cox **************************************************************************/ 195c49fd3aSAlan Cox 205c49fd3aSAlan Cox #ifndef _PSB_DRV_H_ 215c49fd3aSAlan Cox #define _PSB_DRV_H_ 225c49fd3aSAlan Cox 235c49fd3aSAlan Cox #include <linux/kref.h> 245c49fd3aSAlan Cox 255c49fd3aSAlan Cox #include <drm/drmP.h> 265c49fd3aSAlan Cox #include "drm_global.h" 275c49fd3aSAlan Cox #include "gem_glue.h" 28838fa588SAlan Cox #include "gma_drm.h" 295c49fd3aSAlan Cox #include "psb_reg.h" 305c49fd3aSAlan Cox #include "psb_intel_drv.h" 31*d112a816SZhao Yakui #include "intel_bios.h" 325c49fd3aSAlan Cox #include "gtt.h" 335c49fd3aSAlan Cox #include "power.h" 34d839ede4SAlan Cox #include "opregion.h" 355c49fd3aSAlan Cox #include "oaktrail.h" 365c49fd3aSAlan Cox 375c49fd3aSAlan Cox /* Append new drm mode definition here, align with libdrm definition */ 385c49fd3aSAlan Cox #define DRM_MODE_SCALE_NO_SCALE 2 395c49fd3aSAlan Cox 405c49fd3aSAlan Cox enum { 415c49fd3aSAlan Cox CHIP_PSB_8108 = 0, /* Poulsbo */ 425c49fd3aSAlan Cox CHIP_PSB_8109 = 1, /* Poulsbo */ 435c49fd3aSAlan Cox CHIP_MRST_4100 = 2, /* Moorestown/Oaktrail */ 445c49fd3aSAlan Cox CHIP_MFLD_0130 = 3, /* Medfield */ 455c49fd3aSAlan Cox }; 465c49fd3aSAlan Cox 47e036ba59SPatrik Jakobsson #define IS_PSB(dev) (((dev)->pci_device & 0xfffe) == 0x8108) 485c49fd3aSAlan Cox #define IS_MRST(dev) (((dev)->pci_device & 0xfffc) == 0x4100) 495c49fd3aSAlan Cox #define IS_MFLD(dev) (((dev)->pci_device & 0xfff8) == 0x0130) 505c49fd3aSAlan Cox 515c49fd3aSAlan Cox /* 525c49fd3aSAlan Cox * Driver definitions 535c49fd3aSAlan Cox */ 545c49fd3aSAlan Cox 555c49fd3aSAlan Cox #define DRIVER_NAME "gma500" 565c49fd3aSAlan Cox #define DRIVER_DESC "DRM driver for the Intel GMA500" 575c49fd3aSAlan Cox 585c49fd3aSAlan Cox #define PSB_DRM_DRIVER_DATE "2011-06-06" 595c49fd3aSAlan Cox #define PSB_DRM_DRIVER_MAJOR 1 605c49fd3aSAlan Cox #define PSB_DRM_DRIVER_MINOR 0 615c49fd3aSAlan Cox #define PSB_DRM_DRIVER_PATCHLEVEL 0 625c49fd3aSAlan Cox 635c49fd3aSAlan Cox /* 645c49fd3aSAlan Cox * Hardware offsets 655c49fd3aSAlan Cox */ 665c49fd3aSAlan Cox #define PSB_VDC_OFFSET 0x00000000 675c49fd3aSAlan Cox #define PSB_VDC_SIZE 0x000080000 685c49fd3aSAlan Cox #define MRST_MMIO_SIZE 0x0000C0000 695c49fd3aSAlan Cox #define MDFLD_MMIO_SIZE 0x000100000 705c49fd3aSAlan Cox #define PSB_SGX_SIZE 0x8000 715c49fd3aSAlan Cox #define PSB_SGX_OFFSET 0x00040000 725c49fd3aSAlan Cox #define MRST_SGX_OFFSET 0x00080000 735c49fd3aSAlan Cox /* 745c49fd3aSAlan Cox * PCI resource identifiers 755c49fd3aSAlan Cox */ 765c49fd3aSAlan Cox #define PSB_MMIO_RESOURCE 0 775c49fd3aSAlan Cox #define PSB_GATT_RESOURCE 2 785c49fd3aSAlan Cox #define PSB_GTT_RESOURCE 3 795c49fd3aSAlan Cox /* 805c49fd3aSAlan Cox * PCI configuration 815c49fd3aSAlan Cox */ 825c49fd3aSAlan Cox #define PSB_GMCH_CTRL 0x52 835c49fd3aSAlan Cox #define PSB_BSM 0x5C 845c49fd3aSAlan Cox #define _PSB_GMCH_ENABLED 0x4 855c49fd3aSAlan Cox #define PSB_PGETBL_CTL 0x2020 865c49fd3aSAlan Cox #define _PSB_PGETBL_ENABLED 0x00000001 875c49fd3aSAlan Cox #define PSB_SGX_2D_SLAVE_PORT 0x4000 885c49fd3aSAlan Cox 895c49fd3aSAlan Cox /* To get rid of */ 905c49fd3aSAlan Cox #define PSB_TT_PRIV0_LIMIT (256*1024*1024) 915c49fd3aSAlan Cox #define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT) 925c49fd3aSAlan Cox 935c49fd3aSAlan Cox /* 945c49fd3aSAlan Cox * SGX side MMU definitions (these can probably go) 955c49fd3aSAlan Cox */ 965c49fd3aSAlan Cox 975c49fd3aSAlan Cox /* 985c49fd3aSAlan Cox * Flags for external memory type field. 995c49fd3aSAlan Cox */ 1005c49fd3aSAlan Cox #define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */ 1015c49fd3aSAlan Cox #define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */ 1025c49fd3aSAlan Cox #define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */ 1035c49fd3aSAlan Cox /* 1045c49fd3aSAlan Cox * PTE's and PDE's 1055c49fd3aSAlan Cox */ 1065c49fd3aSAlan Cox #define PSB_PDE_MASK 0x003FFFFF 1075c49fd3aSAlan Cox #define PSB_PDE_SHIFT 22 1085c49fd3aSAlan Cox #define PSB_PTE_SHIFT 12 1095c49fd3aSAlan Cox /* 1105c49fd3aSAlan Cox * Cache control 1115c49fd3aSAlan Cox */ 1125c49fd3aSAlan Cox #define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */ 1135c49fd3aSAlan Cox #define PSB_PTE_WO 0x0002 /* Write only */ 1145c49fd3aSAlan Cox #define PSB_PTE_RO 0x0004 /* Read only */ 1155c49fd3aSAlan Cox #define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */ 1165c49fd3aSAlan Cox 1175c49fd3aSAlan Cox /* 1185c49fd3aSAlan Cox * VDC registers and bits 1195c49fd3aSAlan Cox */ 1205c49fd3aSAlan Cox #define PSB_MSVDX_CLOCKGATING 0x2064 1215c49fd3aSAlan Cox #define PSB_TOPAZ_CLOCKGATING 0x2068 1225c49fd3aSAlan Cox #define PSB_HWSTAM 0x2098 1235c49fd3aSAlan Cox #define PSB_INSTPM 0x20C0 1245c49fd3aSAlan Cox #define PSB_INT_IDENTITY_R 0x20A4 125d839ede4SAlan Cox #define _PSB_IRQ_ASLE (1<<0) 1265c49fd3aSAlan Cox #define _MDFLD_PIPEC_EVENT_FLAG (1<<2) 1275c49fd3aSAlan Cox #define _MDFLD_PIPEC_VBLANK_FLAG (1<<3) 1285c49fd3aSAlan Cox #define _PSB_DPST_PIPEB_FLAG (1<<4) 1295c49fd3aSAlan Cox #define _MDFLD_PIPEB_EVENT_FLAG (1<<4) 1305c49fd3aSAlan Cox #define _PSB_VSYNC_PIPEB_FLAG (1<<5) 1315c49fd3aSAlan Cox #define _PSB_DPST_PIPEA_FLAG (1<<6) 1325c49fd3aSAlan Cox #define _PSB_PIPEA_EVENT_FLAG (1<<6) 1335c49fd3aSAlan Cox #define _PSB_VSYNC_PIPEA_FLAG (1<<7) 1345c49fd3aSAlan Cox #define _MDFLD_MIPIA_FLAG (1<<16) 1355c49fd3aSAlan Cox #define _MDFLD_MIPIC_FLAG (1<<17) 13668cb638fSAlan Cox #define _PSB_IRQ_DISP_HOTSYNC (1<<17) 1375c49fd3aSAlan Cox #define _PSB_IRQ_SGX_FLAG (1<<18) 1385c49fd3aSAlan Cox #define _PSB_IRQ_MSVDX_FLAG (1<<19) 1395c49fd3aSAlan Cox #define _LNC_IRQ_TOPAZ_FLAG (1<<20) 1405c49fd3aSAlan Cox 141700e59f6SPatrik Jakobsson #define _PSB_PIPE_EVENT_FLAG (_PSB_VSYNC_PIPEA_FLAG | \ 142700e59f6SPatrik Jakobsson _PSB_VSYNC_PIPEB_FLAG) 143700e59f6SPatrik Jakobsson 1445c49fd3aSAlan Cox /* This flag includes all the display IRQ bits excepts the vblank irqs. */ 1455c49fd3aSAlan Cox #define _MDFLD_DISP_ALL_IRQ_FLAG (_MDFLD_PIPEC_EVENT_FLAG | \ 1465c49fd3aSAlan Cox _MDFLD_PIPEB_EVENT_FLAG | \ 1475c49fd3aSAlan Cox _PSB_PIPEA_EVENT_FLAG | \ 1485c49fd3aSAlan Cox _PSB_VSYNC_PIPEA_FLAG | \ 1495c49fd3aSAlan Cox _MDFLD_MIPIA_FLAG | \ 1505c49fd3aSAlan Cox _MDFLD_MIPIC_FLAG) 1515c49fd3aSAlan Cox #define PSB_INT_IDENTITY_R 0x20A4 1525c49fd3aSAlan Cox #define PSB_INT_MASK_R 0x20A8 1535c49fd3aSAlan Cox #define PSB_INT_ENABLE_R 0x20A0 1545c49fd3aSAlan Cox 1555c49fd3aSAlan Cox #define _PSB_MMU_ER_MASK 0x0001FF00 1565c49fd3aSAlan Cox #define _PSB_MMU_ER_HOST (1 << 16) 1575c49fd3aSAlan Cox #define GPIOA 0x5010 1585c49fd3aSAlan Cox #define GPIOB 0x5014 1595c49fd3aSAlan Cox #define GPIOC 0x5018 1605c49fd3aSAlan Cox #define GPIOD 0x501c 1615c49fd3aSAlan Cox #define GPIOE 0x5020 1625c49fd3aSAlan Cox #define GPIOF 0x5024 1635c49fd3aSAlan Cox #define GPIOG 0x5028 1645c49fd3aSAlan Cox #define GPIOH 0x502c 1655c49fd3aSAlan Cox #define GPIO_CLOCK_DIR_MASK (1 << 0) 1665c49fd3aSAlan Cox #define GPIO_CLOCK_DIR_IN (0 << 1) 1675c49fd3aSAlan Cox #define GPIO_CLOCK_DIR_OUT (1 << 1) 1685c49fd3aSAlan Cox #define GPIO_CLOCK_VAL_MASK (1 << 2) 1695c49fd3aSAlan Cox #define GPIO_CLOCK_VAL_OUT (1 << 3) 1705c49fd3aSAlan Cox #define GPIO_CLOCK_VAL_IN (1 << 4) 1715c49fd3aSAlan Cox #define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) 1725c49fd3aSAlan Cox #define GPIO_DATA_DIR_MASK (1 << 8) 1735c49fd3aSAlan Cox #define GPIO_DATA_DIR_IN (0 << 9) 1745c49fd3aSAlan Cox #define GPIO_DATA_DIR_OUT (1 << 9) 1755c49fd3aSAlan Cox #define GPIO_DATA_VAL_MASK (1 << 10) 1765c49fd3aSAlan Cox #define GPIO_DATA_VAL_OUT (1 << 11) 1775c49fd3aSAlan Cox #define GPIO_DATA_VAL_IN (1 << 12) 1785c49fd3aSAlan Cox #define GPIO_DATA_PULLUP_DISABLE (1 << 13) 1795c49fd3aSAlan Cox 1805c49fd3aSAlan Cox #define VCLK_DIVISOR_VGA0 0x6000 1815c49fd3aSAlan Cox #define VCLK_DIVISOR_VGA1 0x6004 1825c49fd3aSAlan Cox #define VCLK_POST_DIV 0x6010 1835c49fd3aSAlan Cox 1845c49fd3aSAlan Cox #define PSB_COMM_2D (PSB_ENGINE_2D << 4) 1855c49fd3aSAlan Cox #define PSB_COMM_3D (PSB_ENGINE_3D << 4) 1865c49fd3aSAlan Cox #define PSB_COMM_TA (PSB_ENGINE_TA << 4) 1875c49fd3aSAlan Cox #define PSB_COMM_HP (PSB_ENGINE_HP << 4) 1885c49fd3aSAlan Cox #define PSB_COMM_USER_IRQ (1024 >> 2) 1895c49fd3aSAlan Cox #define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1) 1905c49fd3aSAlan Cox #define PSB_COMM_FW (2048 >> 2) 1915c49fd3aSAlan Cox 1925c49fd3aSAlan Cox #define PSB_UIRQ_VISTEST 1 1935c49fd3aSAlan Cox #define PSB_UIRQ_OOM_REPLY 2 1945c49fd3aSAlan Cox #define PSB_UIRQ_FIRE_TA_REPLY 3 1955c49fd3aSAlan Cox #define PSB_UIRQ_FIRE_RASTER_REPLY 4 1965c49fd3aSAlan Cox 1975c49fd3aSAlan Cox #define PSB_2D_SIZE (256*1024*1024) 1985c49fd3aSAlan Cox #define PSB_MAX_RELOC_PAGES 1024 1995c49fd3aSAlan Cox 2005c49fd3aSAlan Cox #define PSB_LOW_REG_OFFS 0x0204 2015c49fd3aSAlan Cox #define PSB_HIGH_REG_OFFS 0x0600 2025c49fd3aSAlan Cox 2035c49fd3aSAlan Cox #define PSB_NUM_VBLANKS 2 2045c49fd3aSAlan Cox 2055c49fd3aSAlan Cox 2065c49fd3aSAlan Cox #define PSB_2D_SIZE (256*1024*1024) 2075c49fd3aSAlan Cox #define PSB_MAX_RELOC_PAGES 1024 2085c49fd3aSAlan Cox 2095c49fd3aSAlan Cox #define PSB_LOW_REG_OFFS 0x0204 2105c49fd3aSAlan Cox #define PSB_HIGH_REG_OFFS 0x0600 2115c49fd3aSAlan Cox 2125c49fd3aSAlan Cox #define PSB_NUM_VBLANKS 2 2135c49fd3aSAlan Cox #define PSB_WATCHDOG_DELAY (DRM_HZ * 2) 2145c49fd3aSAlan Cox #define PSB_LID_DELAY (DRM_HZ / 10) 2155c49fd3aSAlan Cox 2165c49fd3aSAlan Cox #define MDFLD_PNW_B0 0x04 2175c49fd3aSAlan Cox #define MDFLD_PNW_C0 0x08 2185c49fd3aSAlan Cox 2195c49fd3aSAlan Cox #define MDFLD_DSR_2D_3D_0 (1 << 0) 2205c49fd3aSAlan Cox #define MDFLD_DSR_2D_3D_2 (1 << 1) 2215c49fd3aSAlan Cox #define MDFLD_DSR_CURSOR_0 (1 << 2) 2225c49fd3aSAlan Cox #define MDFLD_DSR_CURSOR_2 (1 << 3) 2235c49fd3aSAlan Cox #define MDFLD_DSR_OVERLAY_0 (1 << 4) 2245c49fd3aSAlan Cox #define MDFLD_DSR_OVERLAY_2 (1 << 5) 2255c49fd3aSAlan Cox #define MDFLD_DSR_MIPI_CONTROL (1 << 6) 2265c49fd3aSAlan Cox #define MDFLD_DSR_DAMAGE_MASK_0 ((1 << 0) | (1 << 2) | (1 << 4)) 2275c49fd3aSAlan Cox #define MDFLD_DSR_DAMAGE_MASK_2 ((1 << 1) | (1 << 3) | (1 << 5)) 2285c49fd3aSAlan Cox #define MDFLD_DSR_2D_3D (MDFLD_DSR_2D_3D_0 | MDFLD_DSR_2D_3D_2) 2295c49fd3aSAlan Cox 2305c49fd3aSAlan Cox #define MDFLD_DSR_RR 45 2315c49fd3aSAlan Cox #define MDFLD_DPU_ENABLE (1 << 31) 2325c49fd3aSAlan Cox #define MDFLD_DSR_FULLSCREEN (1 << 30) 2335c49fd3aSAlan Cox #define MDFLD_DSR_DELAY (DRM_HZ / MDFLD_DSR_RR) 2345c49fd3aSAlan Cox 2355c49fd3aSAlan Cox #define PSB_PWR_STATE_ON 1 2365c49fd3aSAlan Cox #define PSB_PWR_STATE_OFF 2 2375c49fd3aSAlan Cox 2385c49fd3aSAlan Cox #define PSB_PMPOLICY_NOPM 0 2395c49fd3aSAlan Cox #define PSB_PMPOLICY_CLOCKGATING 1 2405c49fd3aSAlan Cox #define PSB_PMPOLICY_POWERDOWN 2 2415c49fd3aSAlan Cox 2425c49fd3aSAlan Cox #define PSB_PMSTATE_POWERUP 0 2435c49fd3aSAlan Cox #define PSB_PMSTATE_CLOCKGATED 1 2445c49fd3aSAlan Cox #define PSB_PMSTATE_POWERDOWN 2 2455c49fd3aSAlan Cox #define PSB_PCIx_MSI_ADDR_LOC 0x94 2465c49fd3aSAlan Cox #define PSB_PCIx_MSI_DATA_LOC 0x98 2475c49fd3aSAlan Cox 2485c49fd3aSAlan Cox /* Medfield crystal settings */ 2495c49fd3aSAlan Cox #define KSEL_CRYSTAL_19 1 2505c49fd3aSAlan Cox #define KSEL_BYPASS_19 5 2515c49fd3aSAlan Cox #define KSEL_BYPASS_25 6 2525c49fd3aSAlan Cox #define KSEL_BYPASS_83_100 7 2535c49fd3aSAlan Cox 2545c49fd3aSAlan Cox struct opregion_header; 2555c49fd3aSAlan Cox struct opregion_acpi; 2565c49fd3aSAlan Cox struct opregion_swsci; 2575c49fd3aSAlan Cox struct opregion_asle; 2585c49fd3aSAlan Cox 2595c49fd3aSAlan Cox struct psb_intel_opregion { 2605c49fd3aSAlan Cox struct opregion_header *header; 2615c49fd3aSAlan Cox struct opregion_acpi *acpi; 2625c49fd3aSAlan Cox struct opregion_swsci *swsci; 2635c49fd3aSAlan Cox struct opregion_asle *asle; 2641fb28e9eSAlan Cox void *vbt; 265d839ede4SAlan Cox u32 __iomem *lid_state; 2665c49fd3aSAlan Cox }; 2675c49fd3aSAlan Cox 2685736995bSPatrik Jakobsson struct sdvo_device_mapping { 2695736995bSPatrik Jakobsson u8 initialized; 2705736995bSPatrik Jakobsson u8 dvo_port; 2715736995bSPatrik Jakobsson u8 slave_addr; 2725736995bSPatrik Jakobsson u8 dvo_wiring; 2735736995bSPatrik Jakobsson u8 i2c_pin; 2745736995bSPatrik Jakobsson u8 i2c_speed; 2755736995bSPatrik Jakobsson u8 ddc_pin; 2765736995bSPatrik Jakobsson }; 2775736995bSPatrik Jakobsson 2785c0c1d50SPatrik Jakobsson struct intel_gmbus { 2795c0c1d50SPatrik Jakobsson struct i2c_adapter adapter; 2805c0c1d50SPatrik Jakobsson struct i2c_adapter *force_bit; 2815c0c1d50SPatrik Jakobsson u32 reg0; 2825c0c1d50SPatrik Jakobsson }; 2835c0c1d50SPatrik Jakobsson 284648a8e34SAlan Cox /* 2858512e074SAlan Cox * Register offset maps 2868512e074SAlan Cox */ 2878512e074SAlan Cox 2888512e074SAlan Cox struct psb_offset { 2898512e074SAlan Cox u32 fp0; 2908512e074SAlan Cox u32 fp1; 2918512e074SAlan Cox u32 cntr; 2928512e074SAlan Cox u32 conf; 2938512e074SAlan Cox u32 src; 2948512e074SAlan Cox u32 dpll; 2958512e074SAlan Cox u32 dpll_md; 2968512e074SAlan Cox u32 htotal; 2978512e074SAlan Cox u32 hblank; 2988512e074SAlan Cox u32 hsync; 2998512e074SAlan Cox u32 vtotal; 3008512e074SAlan Cox u32 vblank; 3018512e074SAlan Cox u32 vsync; 3028512e074SAlan Cox u32 stride; 3038512e074SAlan Cox u32 size; 3048512e074SAlan Cox u32 pos; 3058512e074SAlan Cox u32 surf; 3068512e074SAlan Cox u32 addr; 3078512e074SAlan Cox u32 base; 3088512e074SAlan Cox u32 status; 3098512e074SAlan Cox u32 linoff; 3108512e074SAlan Cox u32 tileoff; 3118512e074SAlan Cox u32 palette; 3128512e074SAlan Cox }; 3138512e074SAlan Cox 3148512e074SAlan Cox /* 315648a8e34SAlan Cox * Register save state. This is used to hold the context when the 316648a8e34SAlan Cox * device is powered off. In the case of Oaktrail this can (but does not 317648a8e34SAlan Cox * yet) include screen blank. Operations occuring during the save 318648a8e34SAlan Cox * update the register cache instead. 319648a8e34SAlan Cox */ 3206256304bSAlan Cox 3216256304bSAlan Cox /* 3226256304bSAlan Cox * Common status for pipes. 3236256304bSAlan Cox */ 3246256304bSAlan Cox struct psb_pipe { 3256256304bSAlan Cox u32 fp0; 3266256304bSAlan Cox u32 fp1; 3276256304bSAlan Cox u32 cntr; 3286256304bSAlan Cox u32 conf; 3296256304bSAlan Cox u32 src; 3306256304bSAlan Cox u32 dpll; 3316256304bSAlan Cox u32 dpll_md; 3326256304bSAlan Cox u32 htotal; 3336256304bSAlan Cox u32 hblank; 3346256304bSAlan Cox u32 hsync; 3356256304bSAlan Cox u32 vtotal; 3366256304bSAlan Cox u32 vblank; 3376256304bSAlan Cox u32 vsync; 3386256304bSAlan Cox u32 stride; 3396256304bSAlan Cox u32 size; 3406256304bSAlan Cox u32 pos; 3416256304bSAlan Cox u32 base; 3426256304bSAlan Cox u32 surf; 3436256304bSAlan Cox u32 addr; 3446256304bSAlan Cox u32 status; 3456256304bSAlan Cox u32 linoff; 3466256304bSAlan Cox u32 tileoff; 3476256304bSAlan Cox u32 palette[256]; 3486256304bSAlan Cox }; 3496256304bSAlan Cox 350648a8e34SAlan Cox struct psb_state { 351648a8e34SAlan Cox uint32_t saveVCLK_DIVISOR_VGA0; 352648a8e34SAlan Cox uint32_t saveVCLK_DIVISOR_VGA1; 353648a8e34SAlan Cox uint32_t saveVCLK_POST_DIV; 354648a8e34SAlan Cox uint32_t saveVGACNTRL; 355648a8e34SAlan Cox uint32_t saveADPA; 356648a8e34SAlan Cox uint32_t saveLVDS; 357648a8e34SAlan Cox uint32_t saveDVOA; 358648a8e34SAlan Cox uint32_t saveDVOB; 359648a8e34SAlan Cox uint32_t saveDVOC; 360648a8e34SAlan Cox uint32_t savePP_ON; 361648a8e34SAlan Cox uint32_t savePP_OFF; 362648a8e34SAlan Cox uint32_t savePP_CONTROL; 363648a8e34SAlan Cox uint32_t savePP_CYCLE; 364648a8e34SAlan Cox uint32_t savePFIT_CONTROL; 365648a8e34SAlan Cox uint32_t saveCLOCKGATING; 366648a8e34SAlan Cox uint32_t saveDSPARB; 367648a8e34SAlan Cox uint32_t savePFIT_AUTO_RATIOS; 368648a8e34SAlan Cox uint32_t savePFIT_PGM_RATIOS; 369648a8e34SAlan Cox uint32_t savePP_ON_DELAYS; 370648a8e34SAlan Cox uint32_t savePP_OFF_DELAYS; 371648a8e34SAlan Cox uint32_t savePP_DIVISOR; 372648a8e34SAlan Cox uint32_t saveBCLRPAT_A; 373648a8e34SAlan Cox uint32_t saveBCLRPAT_B; 374648a8e34SAlan Cox uint32_t savePERF_MODE; 375648a8e34SAlan Cox uint32_t saveDSPFW1; 376648a8e34SAlan Cox uint32_t saveDSPFW2; 377648a8e34SAlan Cox uint32_t saveDSPFW3; 378648a8e34SAlan Cox uint32_t saveDSPFW4; 379648a8e34SAlan Cox uint32_t saveDSPFW5; 380648a8e34SAlan Cox uint32_t saveDSPFW6; 381648a8e34SAlan Cox uint32_t saveCHICKENBIT; 382648a8e34SAlan Cox uint32_t saveDSPACURSOR_CTRL; 383648a8e34SAlan Cox uint32_t saveDSPBCURSOR_CTRL; 384648a8e34SAlan Cox uint32_t saveDSPACURSOR_BASE; 385648a8e34SAlan Cox uint32_t saveDSPBCURSOR_BASE; 386648a8e34SAlan Cox uint32_t saveDSPACURSOR_POS; 387648a8e34SAlan Cox uint32_t saveDSPBCURSOR_POS; 388648a8e34SAlan Cox uint32_t saveOV_OVADD; 389648a8e34SAlan Cox uint32_t saveOV_OGAMC0; 390648a8e34SAlan Cox uint32_t saveOV_OGAMC1; 391648a8e34SAlan Cox uint32_t saveOV_OGAMC2; 392648a8e34SAlan Cox uint32_t saveOV_OGAMC3; 393648a8e34SAlan Cox uint32_t saveOV_OGAMC4; 394648a8e34SAlan Cox uint32_t saveOV_OGAMC5; 395648a8e34SAlan Cox uint32_t saveOVC_OVADD; 396648a8e34SAlan Cox uint32_t saveOVC_OGAMC0; 397648a8e34SAlan Cox uint32_t saveOVC_OGAMC1; 398648a8e34SAlan Cox uint32_t saveOVC_OGAMC2; 399648a8e34SAlan Cox uint32_t saveOVC_OGAMC3; 400648a8e34SAlan Cox uint32_t saveOVC_OGAMC4; 401648a8e34SAlan Cox uint32_t saveOVC_OGAMC5; 402648a8e34SAlan Cox 403648a8e34SAlan Cox /* DPST register save */ 404648a8e34SAlan Cox uint32_t saveHISTOGRAM_INT_CONTROL_REG; 405648a8e34SAlan Cox uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG; 406648a8e34SAlan Cox uint32_t savePWM_CONTROL_LOGIC; 407648a8e34SAlan Cox }; 408648a8e34SAlan Cox 409026abc33SKirill A. Shutemov struct medfield_state { 410026abc33SKirill A. Shutemov uint32_t saveMIPI; 411026abc33SKirill A. Shutemov uint32_t saveMIPI_C; 412026abc33SKirill A. Shutemov 413026abc33SKirill A. Shutemov uint32_t savePFIT_CONTROL; 414026abc33SKirill A. Shutemov uint32_t savePFIT_PGM_RATIOS; 415026abc33SKirill A. Shutemov uint32_t saveHDMIPHYMISCCTL; 416026abc33SKirill A. Shutemov uint32_t saveHDMIB_CONTROL; 417026abc33SKirill A. Shutemov }; 418026abc33SKirill A. Shutemov 41909016a11SAlan Cox struct cdv_state { 42009016a11SAlan Cox uint32_t saveDSPCLK_GATE_D; 42109016a11SAlan Cox uint32_t saveRAMCLK_GATE_D; 42209016a11SAlan Cox uint32_t saveDSPARB; 42309016a11SAlan Cox uint32_t saveDSPFW[6]; 42409016a11SAlan Cox uint32_t saveADPA; 42509016a11SAlan Cox uint32_t savePP_CONTROL; 42609016a11SAlan Cox uint32_t savePFIT_PGM_RATIOS; 42709016a11SAlan Cox uint32_t saveLVDS; 42809016a11SAlan Cox uint32_t savePFIT_CONTROL; 42909016a11SAlan Cox uint32_t savePP_ON_DELAYS; 43009016a11SAlan Cox uint32_t savePP_OFF_DELAYS; 43109016a11SAlan Cox uint32_t savePP_CYCLE; 43209016a11SAlan Cox uint32_t saveVGACNTRL; 43309016a11SAlan Cox uint32_t saveIER; 43409016a11SAlan Cox uint32_t saveIMR; 43509016a11SAlan Cox u8 saveLBB; 43609016a11SAlan Cox }; 43709016a11SAlan Cox 438c6265ff5SAlan Cox struct psb_save_area { 4396256304bSAlan Cox struct psb_pipe pipe[3]; 440c6265ff5SAlan Cox uint32_t saveBSM; 441c6265ff5SAlan Cox uint32_t saveVBT; 442c6265ff5SAlan Cox union { 443c6265ff5SAlan Cox struct psb_state psb; 444026abc33SKirill A. Shutemov struct medfield_state mdfld; 44509016a11SAlan Cox struct cdv_state cdv; 446c6265ff5SAlan Cox }; 447c6265ff5SAlan Cox uint32_t saveBLC_PWM_CTL2; 448c6265ff5SAlan Cox uint32_t saveBLC_PWM_CTL; 449c6265ff5SAlan Cox }; 450c6265ff5SAlan Cox 4515c49fd3aSAlan Cox struct psb_ops; 4525c49fd3aSAlan Cox 45304bd564fSAlan Cox #define PSB_NUM_PIPE 3 45404bd564fSAlan Cox 4555c49fd3aSAlan Cox struct drm_psb_private { 4565c49fd3aSAlan Cox struct drm_device *dev; 4575c49fd3aSAlan Cox const struct psb_ops *ops; 4588512e074SAlan Cox const struct psb_offset *regmap; 4595c49fd3aSAlan Cox 4601fb28e9eSAlan Cox struct child_device_config *child_dev; 4611fb28e9eSAlan Cox int child_dev_num; 4621fb28e9eSAlan Cox 4635c49fd3aSAlan Cox struct psb_gtt gtt; 4645c49fd3aSAlan Cox 4655c49fd3aSAlan Cox /* GTT Memory manager */ 4665c49fd3aSAlan Cox struct psb_gtt_mm *gtt_mm; 4675c49fd3aSAlan Cox struct page *scratch_page; 468eab37607SKirill A. Shutemov u32 __iomem *gtt_map; 4695c49fd3aSAlan Cox uint32_t stolen_base; 47037214ca0SKirill A. Shutemov u8 __iomem *vram_addr; 4715c49fd3aSAlan Cox unsigned long vram_stolen_size; 4725c49fd3aSAlan Cox int gtt_initialized; 4735c49fd3aSAlan Cox u16 gmch_ctrl; /* Saved GTT setup */ 4745c49fd3aSAlan Cox u32 pge_ctl; 4755c49fd3aSAlan Cox 4765c49fd3aSAlan Cox struct mutex gtt_mutex; 4775c49fd3aSAlan Cox struct resource *gtt_mem; /* Our PCI resource */ 4785c49fd3aSAlan Cox 4795c49fd3aSAlan Cox struct psb_mmu_driver *mmu; 4805c49fd3aSAlan Cox struct psb_mmu_pd *pf_pd; 4815c49fd3aSAlan Cox 4825c49fd3aSAlan Cox /* 4835c49fd3aSAlan Cox * Register base 4845c49fd3aSAlan Cox */ 4855c49fd3aSAlan Cox 486846a6038SKirill A. Shutemov uint8_t __iomem *sgx_reg; 487846a6038SKirill A. Shutemov uint8_t __iomem *vdc_reg; 4885c49fd3aSAlan Cox uint32_t gatt_free_offset; 4895c49fd3aSAlan Cox 4905c49fd3aSAlan Cox /* 4915c49fd3aSAlan Cox * Fencing / irq. 4925c49fd3aSAlan Cox */ 4935c49fd3aSAlan Cox 4945c49fd3aSAlan Cox uint32_t vdc_irq_mask; 4955c49fd3aSAlan Cox uint32_t pipestat[PSB_NUM_PIPE]; 4965c49fd3aSAlan Cox 4975c49fd3aSAlan Cox spinlock_t irqmask_lock; 4985c49fd3aSAlan Cox 4995c49fd3aSAlan Cox /* 5005c49fd3aSAlan Cox * Power 5015c49fd3aSAlan Cox */ 5025c49fd3aSAlan Cox 5035c49fd3aSAlan Cox bool suspended; 5045c49fd3aSAlan Cox bool display_power; 5055c49fd3aSAlan Cox int display_count; 5065c49fd3aSAlan Cox 5075c49fd3aSAlan Cox /* 5085c49fd3aSAlan Cox * Modesetting 5095c49fd3aSAlan Cox */ 5105c49fd3aSAlan Cox struct psb_intel_mode_device mode_dev; 5114ab2c7f1SAlan Cox bool modeset; /* true if we have done the mode_device setup */ 5125c49fd3aSAlan Cox 5135c49fd3aSAlan Cox struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE]; 5145c49fd3aSAlan Cox struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE]; 5155c49fd3aSAlan Cox uint32_t num_pipe; 5165c49fd3aSAlan Cox 5175c49fd3aSAlan Cox /* 5185c49fd3aSAlan Cox * OSPM info (Power management base) (can go ?) 5195c49fd3aSAlan Cox */ 5205c49fd3aSAlan Cox uint32_t ospm_base; 5215c49fd3aSAlan Cox 5225c49fd3aSAlan Cox /* 5235c49fd3aSAlan Cox * Sizes info 5245c49fd3aSAlan Cox */ 5255c49fd3aSAlan Cox 5265c49fd3aSAlan Cox u32 fuse_reg_value; 5275c49fd3aSAlan Cox u32 video_device_fuse; 5285c49fd3aSAlan Cox 5295c49fd3aSAlan Cox /* PCI revision ID for B0:D2:F0 */ 5305c49fd3aSAlan Cox uint8_t platform_rev_id; 5315c49fd3aSAlan Cox 5325c0c1d50SPatrik Jakobsson /* gmbus */ 5335c0c1d50SPatrik Jakobsson struct intel_gmbus *gmbus; 5345c0c1d50SPatrik Jakobsson 5355736995bSPatrik Jakobsson /* Used by SDVO */ 5365736995bSPatrik Jakobsson int crt_ddc_pin; 5375736995bSPatrik Jakobsson /* FIXME: The mappings should be parsed from bios but for now we can 5385736995bSPatrik Jakobsson pretend there are no mappings available */ 5395736995bSPatrik Jakobsson struct sdvo_device_mapping sdvo_mappings[2]; 5405736995bSPatrik Jakobsson u32 hotplug_supported_mask; 5415736995bSPatrik Jakobsson struct drm_property *broadcast_rgb_property; 5425736995bSPatrik Jakobsson struct drm_property *force_audio_property; 5435736995bSPatrik Jakobsson 5445c49fd3aSAlan Cox /* 5455c49fd3aSAlan Cox * LVDS info 5465c49fd3aSAlan Cox */ 5475c49fd3aSAlan Cox int backlight_duty_cycle; /* restore backlight to this value */ 5485c49fd3aSAlan Cox bool panel_wants_dither; 5495c49fd3aSAlan Cox struct drm_display_mode *panel_fixed_mode; 5505c49fd3aSAlan Cox struct drm_display_mode *lfp_lvds_vbt_mode; 5515c49fd3aSAlan Cox struct drm_display_mode *sdvo_lvds_vbt_mode; 5525c49fd3aSAlan Cox 5535c49fd3aSAlan Cox struct bdb_lvds_backlight *lvds_bl; /* LVDS backlight info from VBT */ 554a12d6a07SPatrik Jakobsson struct psb_intel_i2c_chan *lvds_i2c_bus; /* FIXME: Remove this? */ 5555c49fd3aSAlan Cox 5565c49fd3aSAlan Cox /* Feature bits from the VBIOS */ 5575c49fd3aSAlan Cox unsigned int int_tv_support:1; 5585c49fd3aSAlan Cox unsigned int lvds_dither:1; 5595c49fd3aSAlan Cox unsigned int lvds_vbt:1; 5605c49fd3aSAlan Cox unsigned int int_crt_support:1; 5615c49fd3aSAlan Cox unsigned int lvds_use_ssc:1; 5625c49fd3aSAlan Cox int lvds_ssc_freq; 5635c49fd3aSAlan Cox bool is_lvds_on; 5645c49fd3aSAlan Cox bool is_mipi_on; 5655c49fd3aSAlan Cox u32 mipi_ctrl_display; 5665c49fd3aSAlan Cox 5675c49fd3aSAlan Cox unsigned int core_freq; 5685c49fd3aSAlan Cox uint32_t iLVDS_enable; 5695c49fd3aSAlan Cox 5705c49fd3aSAlan Cox /* Runtime PM state */ 5715c49fd3aSAlan Cox int rpm_enabled; 5725c49fd3aSAlan Cox 5735c49fd3aSAlan Cox /* MID specific */ 5744086b1e2SKirill A. Shutemov bool has_gct; 5755c49fd3aSAlan Cox struct oaktrail_gct_data gct_data; 5765c49fd3aSAlan Cox 577933315acSAlan Cox /* Oaktrail HDMI state */ 5785c49fd3aSAlan Cox struct oaktrail_hdmi_dev *hdmi_priv; 5795c49fd3aSAlan Cox 5805c49fd3aSAlan Cox /* 5815c49fd3aSAlan Cox * Register state 5825c49fd3aSAlan Cox */ 583c6265ff5SAlan Cox 584c6265ff5SAlan Cox struct psb_save_area regs; 585c6265ff5SAlan Cox 5865c49fd3aSAlan Cox /* MSI reg save */ 5875c49fd3aSAlan Cox uint32_t msi_addr; 5885c49fd3aSAlan Cox uint32_t msi_data; 5895c49fd3aSAlan Cox 590ae0a246aSAlan Cox /* 591ae0a246aSAlan Cox * Hotplug handling 592ae0a246aSAlan Cox */ 593ae0a246aSAlan Cox 594ae0a246aSAlan Cox struct work_struct hotplug_work; 5955c49fd3aSAlan Cox 5965c49fd3aSAlan Cox /* 5975c49fd3aSAlan Cox * LID-Switch 5985c49fd3aSAlan Cox */ 5995c49fd3aSAlan Cox spinlock_t lid_lock; 6005c49fd3aSAlan Cox struct timer_list lid_timer; 6015c49fd3aSAlan Cox struct psb_intel_opregion opregion; 6025c49fd3aSAlan Cox u32 lid_last_state; 6035c49fd3aSAlan Cox 6045c49fd3aSAlan Cox /* 6055c49fd3aSAlan Cox * Watchdog 6065c49fd3aSAlan Cox */ 6075c49fd3aSAlan Cox 6085c49fd3aSAlan Cox uint32_t apm_reg; 6095c49fd3aSAlan Cox uint16_t apm_base; 6105c49fd3aSAlan Cox 6115c49fd3aSAlan Cox /* 6125c49fd3aSAlan Cox * Used for modifying backlight from 6135c49fd3aSAlan Cox * xrandr -- consider removing and using HAL instead 6145c49fd3aSAlan Cox */ 6155c49fd3aSAlan Cox struct backlight_device *backlight_device; 6165c49fd3aSAlan Cox struct drm_property *backlight_property; 617*d112a816SZhao Yakui bool backlight_enabled; 618*d112a816SZhao Yakui int backlight_level; 6195c49fd3aSAlan Cox uint32_t blc_adj1; 6205c49fd3aSAlan Cox uint32_t blc_adj2; 6215c49fd3aSAlan Cox 6225c49fd3aSAlan Cox void *fbdev; 6235c49fd3aSAlan Cox 6245c49fd3aSAlan Cox /* 2D acceleration */ 6259242fe23SAlan Cox spinlock_t lock_2d; 626026abc33SKirill A. Shutemov 627026abc33SKirill A. Shutemov /* 628026abc33SKirill A. Shutemov * Panel brightness 629026abc33SKirill A. Shutemov */ 630026abc33SKirill A. Shutemov int brightness; 631026abc33SKirill A. Shutemov int brightness_adjusted; 632026abc33SKirill A. Shutemov 633026abc33SKirill A. Shutemov bool dsr_enable; 634026abc33SKirill A. Shutemov u32 dsr_fb_update; 635026abc33SKirill A. Shutemov bool dpi_panel_on[3]; 636026abc33SKirill A. Shutemov void *dsi_configs[2]; 637026abc33SKirill A. Shutemov u32 bpp; 638026abc33SKirill A. Shutemov u32 bpp2; 639026abc33SKirill A. Shutemov 640026abc33SKirill A. Shutemov u32 pipeconf[3]; 641026abc33SKirill A. Shutemov u32 dspcntr[3]; 642026abc33SKirill A. Shutemov 643026abc33SKirill A. Shutemov int mdfld_panel_id; 644642c52fcSAlan Cox 645642c52fcSAlan Cox bool dplla_96mhz; /* DPLL data from the VBT */ 646*d112a816SZhao Yakui 647*d112a816SZhao Yakui struct { 648*d112a816SZhao Yakui int rate; 649*d112a816SZhao Yakui int lanes; 650*d112a816SZhao Yakui int preemphasis; 651*d112a816SZhao Yakui int vswing; 652*d112a816SZhao Yakui 653*d112a816SZhao Yakui bool initialized; 654*d112a816SZhao Yakui bool support; 655*d112a816SZhao Yakui int bpp; 656*d112a816SZhao Yakui struct edp_power_seq pps; 657*d112a816SZhao Yakui } edp; 658*d112a816SZhao Yakui uint8_t panel_type; 6595c49fd3aSAlan Cox }; 6605c49fd3aSAlan Cox 6615c49fd3aSAlan Cox 6625c49fd3aSAlan Cox /* 6635c49fd3aSAlan Cox * Operations for each board type 6645c49fd3aSAlan Cox */ 6655c49fd3aSAlan Cox 6665c49fd3aSAlan Cox struct psb_ops { 6675c49fd3aSAlan Cox const char *name; 6685c49fd3aSAlan Cox unsigned int accel_2d:1; 6695c49fd3aSAlan Cox int pipes; /* Number of output pipes */ 6705c49fd3aSAlan Cox int crtcs; /* Number of CRTCs */ 6715c49fd3aSAlan Cox int sgx_offset; /* Base offset of SGX device */ 672d235e64aSAlan Cox int hdmi_mask; /* Mask of HDMI CRTCs */ 673d235e64aSAlan Cox int lvds_mask; /* Mask of LVDS CRTCs */ 674bc794829SPatrik Jakobsson int cursor_needs_phys; /* If cursor base reg need physical address */ 6755c49fd3aSAlan Cox 6765c49fd3aSAlan Cox /* Sub functions */ 6775c49fd3aSAlan Cox struct drm_crtc_helper_funcs const *crtc_helper; 6785c49fd3aSAlan Cox struct drm_crtc_funcs const *crtc_funcs; 6795c49fd3aSAlan Cox 6805c49fd3aSAlan Cox /* Setup hooks */ 6815c49fd3aSAlan Cox int (*chip_setup)(struct drm_device *dev); 6825c49fd3aSAlan Cox void (*chip_teardown)(struct drm_device *dev); 683d235e64aSAlan Cox /* Optional helper caller after modeset */ 684d235e64aSAlan Cox void (*errata)(struct drm_device *dev); 6855c49fd3aSAlan Cox 6865c49fd3aSAlan Cox /* Display management hooks */ 6875c49fd3aSAlan Cox int (*output_init)(struct drm_device *dev); 68868cb638fSAlan Cox int (*hotplug)(struct drm_device *dev); 68968cb638fSAlan Cox void (*hotplug_enable)(struct drm_device *dev, bool on); 6905c49fd3aSAlan Cox /* Power management hooks */ 6915c49fd3aSAlan Cox void (*init_pm)(struct drm_device *dev); 6925c49fd3aSAlan Cox int (*save_regs)(struct drm_device *dev); 6935c49fd3aSAlan Cox int (*restore_regs)(struct drm_device *dev); 6945c49fd3aSAlan Cox int (*power_up)(struct drm_device *dev); 6955c49fd3aSAlan Cox int (*power_down)(struct drm_device *dev); 6965c49fd3aSAlan Cox 6975c49fd3aSAlan Cox void (*lvds_bl_power)(struct drm_device *dev, bool on); 6985c49fd3aSAlan Cox #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE 6995c49fd3aSAlan Cox /* Backlight */ 7005c49fd3aSAlan Cox int (*backlight_init)(struct drm_device *dev); 7015c49fd3aSAlan Cox #endif 7025c49fd3aSAlan Cox int i2c_bus; /* I2C bus identifier for Moorestown */ 7035c49fd3aSAlan Cox }; 7045c49fd3aSAlan Cox 7055c49fd3aSAlan Cox 7065c49fd3aSAlan Cox 7075c49fd3aSAlan Cox struct psb_mmu_driver; 7085c49fd3aSAlan Cox 7095c49fd3aSAlan Cox extern int drm_crtc_probe_output_modes(struct drm_device *dev, int, int); 7105c49fd3aSAlan Cox extern int drm_pick_crtcs(struct drm_device *dev); 7115c49fd3aSAlan Cox 7125c49fd3aSAlan Cox static inline struct drm_psb_private *psb_priv(struct drm_device *dev) 7135c49fd3aSAlan Cox { 7145c49fd3aSAlan Cox return (struct drm_psb_private *) dev->dev_private; 7155c49fd3aSAlan Cox } 7165c49fd3aSAlan Cox 7175c49fd3aSAlan Cox /* 7185c49fd3aSAlan Cox * MMU stuff. 7195c49fd3aSAlan Cox */ 7205c49fd3aSAlan Cox 7215c49fd3aSAlan Cox extern struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers, 7225c49fd3aSAlan Cox int trap_pagefaults, 7235c49fd3aSAlan Cox int invalid_type, 7245c49fd3aSAlan Cox struct drm_psb_private *dev_priv); 7255c49fd3aSAlan Cox extern void psb_mmu_driver_takedown(struct psb_mmu_driver *driver); 7265c49fd3aSAlan Cox extern struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver 7275c49fd3aSAlan Cox *driver); 7285c49fd3aSAlan Cox extern void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd, uint32_t mmu_offset, 7295c49fd3aSAlan Cox uint32_t gtt_start, uint32_t gtt_pages); 7305c49fd3aSAlan Cox extern struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver, 7315c49fd3aSAlan Cox int trap_pagefaults, 7325c49fd3aSAlan Cox int invalid_type); 7335c49fd3aSAlan Cox extern void psb_mmu_free_pagedir(struct psb_mmu_pd *pd); 7345c49fd3aSAlan Cox extern void psb_mmu_flush(struct psb_mmu_driver *driver, int rc_prot); 7355c49fd3aSAlan Cox extern void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd, 7365c49fd3aSAlan Cox unsigned long address, 7375c49fd3aSAlan Cox uint32_t num_pages); 7385c49fd3aSAlan Cox extern int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd, 7395c49fd3aSAlan Cox uint32_t start_pfn, 7405c49fd3aSAlan Cox unsigned long address, 7415c49fd3aSAlan Cox uint32_t num_pages, int type); 7425c49fd3aSAlan Cox extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual, 7435c49fd3aSAlan Cox unsigned long *pfn); 7445c49fd3aSAlan Cox 7455c49fd3aSAlan Cox /* 7465c49fd3aSAlan Cox * Enable / disable MMU for different requestors. 7475c49fd3aSAlan Cox */ 7485c49fd3aSAlan Cox 7495c49fd3aSAlan Cox 7505c49fd3aSAlan Cox extern void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context); 7515c49fd3aSAlan Cox extern int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages, 7525c49fd3aSAlan Cox unsigned long address, uint32_t num_pages, 7535c49fd3aSAlan Cox uint32_t desired_tile_stride, 7545c49fd3aSAlan Cox uint32_t hw_tile_stride, int type); 7555c49fd3aSAlan Cox extern void psb_mmu_remove_pages(struct psb_mmu_pd *pd, 7565c49fd3aSAlan Cox unsigned long address, uint32_t num_pages, 7575c49fd3aSAlan Cox uint32_t desired_tile_stride, 7585c49fd3aSAlan Cox uint32_t hw_tile_stride); 7595c49fd3aSAlan Cox /* 7605c49fd3aSAlan Cox *psb_irq.c 7615c49fd3aSAlan Cox */ 7625c49fd3aSAlan Cox 7635c49fd3aSAlan Cox extern irqreturn_t psb_irq_handler(DRM_IRQ_ARGS); 7645c49fd3aSAlan Cox extern int psb_irq_enable_dpst(struct drm_device *dev); 7655c49fd3aSAlan Cox extern int psb_irq_disable_dpst(struct drm_device *dev); 7665c49fd3aSAlan Cox extern void psb_irq_preinstall(struct drm_device *dev); 7675c49fd3aSAlan Cox extern int psb_irq_postinstall(struct drm_device *dev); 7685c49fd3aSAlan Cox extern void psb_irq_uninstall(struct drm_device *dev); 7695c49fd3aSAlan Cox extern void psb_irq_turn_on_dpst(struct drm_device *dev); 7705c49fd3aSAlan Cox extern void psb_irq_turn_off_dpst(struct drm_device *dev); 7715c49fd3aSAlan Cox 7725c49fd3aSAlan Cox extern void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands); 7735c49fd3aSAlan Cox extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence); 7745c49fd3aSAlan Cox extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence); 7755c49fd3aSAlan Cox extern int psb_enable_vblank(struct drm_device *dev, int crtc); 7765c49fd3aSAlan Cox extern void psb_disable_vblank(struct drm_device *dev, int crtc); 7775c49fd3aSAlan Cox void 7785c49fd3aSAlan Cox psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask); 7795c49fd3aSAlan Cox 7805c49fd3aSAlan Cox void 7815c49fd3aSAlan Cox psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask); 7825c49fd3aSAlan Cox 7835c49fd3aSAlan Cox extern u32 psb_get_vblank_counter(struct drm_device *dev, int crtc); 7845c49fd3aSAlan Cox 7855c49fd3aSAlan Cox /* 7865c49fd3aSAlan Cox * framebuffer.c 7875c49fd3aSAlan Cox */ 7885c49fd3aSAlan Cox extern int psbfb_probed(struct drm_device *dev); 7895c49fd3aSAlan Cox extern int psbfb_remove(struct drm_device *dev, 7905c49fd3aSAlan Cox struct drm_framebuffer *fb); 7915c49fd3aSAlan Cox /* 7925c49fd3aSAlan Cox * accel_2d.c 7935c49fd3aSAlan Cox */ 7945c49fd3aSAlan Cox extern void psbfb_copyarea(struct fb_info *info, 7955c49fd3aSAlan Cox const struct fb_copyarea *region); 7965c49fd3aSAlan Cox extern int psbfb_sync(struct fb_info *info); 7975c49fd3aSAlan Cox extern void psb_spank(struct drm_psb_private *dev_priv); 7985c49fd3aSAlan Cox 7995c49fd3aSAlan Cox /* 8005c49fd3aSAlan Cox * psb_reset.c 8015c49fd3aSAlan Cox */ 8025c49fd3aSAlan Cox 8035c49fd3aSAlan Cox extern void psb_lid_timer_init(struct drm_psb_private *dev_priv); 8045c49fd3aSAlan Cox extern void psb_lid_timer_takedown(struct drm_psb_private *dev_priv); 8055c49fd3aSAlan Cox extern void psb_print_pagefault(struct drm_psb_private *dev_priv); 8065c49fd3aSAlan Cox 8075c49fd3aSAlan Cox /* modesetting */ 8085c49fd3aSAlan Cox extern void psb_modeset_init(struct drm_device *dev); 8095c49fd3aSAlan Cox extern void psb_modeset_cleanup(struct drm_device *dev); 8105c49fd3aSAlan Cox extern int psb_fbdev_init(struct drm_device *dev); 8115c49fd3aSAlan Cox 8125c49fd3aSAlan Cox /* backlight.c */ 8135c49fd3aSAlan Cox int gma_backlight_init(struct drm_device *dev); 8145c49fd3aSAlan Cox void gma_backlight_exit(struct drm_device *dev); 815*d112a816SZhao Yakui void gma_backlight_disable(struct drm_device *dev); 816*d112a816SZhao Yakui void gma_backlight_enable(struct drm_device *dev); 817*d112a816SZhao Yakui void gma_backlight_set(struct drm_device *dev, int v); 8185c49fd3aSAlan Cox 8195c49fd3aSAlan Cox /* oaktrail_crtc.c */ 8205c49fd3aSAlan Cox extern const struct drm_crtc_helper_funcs oaktrail_helper_funcs; 8215c49fd3aSAlan Cox 8225c49fd3aSAlan Cox /* oaktrail_lvds.c */ 8235c49fd3aSAlan Cox extern void oaktrail_lvds_init(struct drm_device *dev, 8245c49fd3aSAlan Cox struct psb_intel_mode_device *mode_dev); 8255c49fd3aSAlan Cox 8265c49fd3aSAlan Cox /* psb_intel_display.c */ 8275c49fd3aSAlan Cox extern const struct drm_crtc_helper_funcs psb_intel_helper_funcs; 8285c49fd3aSAlan Cox extern const struct drm_crtc_funcs psb_intel_crtc_funcs; 8295c49fd3aSAlan Cox 8305c49fd3aSAlan Cox /* psb_intel_lvds.c */ 8315c49fd3aSAlan Cox extern const struct drm_connector_helper_funcs 8325c49fd3aSAlan Cox psb_intel_lvds_connector_helper_funcs; 8335c49fd3aSAlan Cox extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs; 8345c49fd3aSAlan Cox 8355c49fd3aSAlan Cox /* gem.c */ 8365c49fd3aSAlan Cox extern int psb_gem_init_object(struct drm_gem_object *obj); 8375c49fd3aSAlan Cox extern void psb_gem_free_object(struct drm_gem_object *obj); 8385c49fd3aSAlan Cox extern int psb_gem_get_aperture(struct drm_device *dev, void *data, 8395c49fd3aSAlan Cox struct drm_file *file); 8405c49fd3aSAlan Cox extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev, 8415c49fd3aSAlan Cox struct drm_mode_create_dumb *args); 8425c49fd3aSAlan Cox extern int psb_gem_dumb_destroy(struct drm_file *file, struct drm_device *dev, 8435c49fd3aSAlan Cox uint32_t handle); 8445c49fd3aSAlan Cox extern int psb_gem_dumb_map_gtt(struct drm_file *file, struct drm_device *dev, 8455c49fd3aSAlan Cox uint32_t handle, uint64_t *offset); 8465c49fd3aSAlan Cox extern int psb_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); 8475c49fd3aSAlan Cox extern int psb_gem_create_ioctl(struct drm_device *dev, void *data, 8485c49fd3aSAlan Cox struct drm_file *file); 8495c49fd3aSAlan Cox extern int psb_gem_mmap_ioctl(struct drm_device *dev, void *data, 8505c49fd3aSAlan Cox struct drm_file *file); 8515c49fd3aSAlan Cox 8525c49fd3aSAlan Cox /* psb_device.c */ 8535c49fd3aSAlan Cox extern const struct psb_ops psb_chip_ops; 8545c49fd3aSAlan Cox 8555c49fd3aSAlan Cox /* oaktrail_device.c */ 8565c49fd3aSAlan Cox extern const struct psb_ops oaktrail_chip_ops; 8575c49fd3aSAlan Cox 858026abc33SKirill A. Shutemov /* mdlfd_device.c */ 859026abc33SKirill A. Shutemov extern const struct psb_ops mdfld_chip_ops; 860026abc33SKirill A. Shutemov 8615c49fd3aSAlan Cox /* cdv_device.c */ 8625c49fd3aSAlan Cox extern const struct psb_ops cdv_chip_ops; 8635c49fd3aSAlan Cox 8645c49fd3aSAlan Cox /* 8655c49fd3aSAlan Cox * Debug print bits setting 8665c49fd3aSAlan Cox */ 8675c49fd3aSAlan Cox #define PSB_D_GENERAL (1 << 0) 8685c49fd3aSAlan Cox #define PSB_D_INIT (1 << 1) 8695c49fd3aSAlan Cox #define PSB_D_IRQ (1 << 2) 8705c49fd3aSAlan Cox #define PSB_D_ENTRY (1 << 3) 8715c49fd3aSAlan Cox /* debug the get H/V BP/FP count */ 8725c49fd3aSAlan Cox #define PSB_D_HV (1 << 4) 8735c49fd3aSAlan Cox #define PSB_D_DBI_BF (1 << 5) 8745c49fd3aSAlan Cox #define PSB_D_PM (1 << 6) 8755c49fd3aSAlan Cox #define PSB_D_RENDER (1 << 7) 8765c49fd3aSAlan Cox #define PSB_D_REG (1 << 8) 8775c49fd3aSAlan Cox #define PSB_D_MSVDX (1 << 9) 8785c49fd3aSAlan Cox #define PSB_D_TOPAZ (1 << 10) 8795c49fd3aSAlan Cox 8805c49fd3aSAlan Cox extern int drm_psb_no_fb; 8815c49fd3aSAlan Cox extern int drm_idle_check_interval; 8825c49fd3aSAlan Cox 8835c49fd3aSAlan Cox /* 8845c49fd3aSAlan Cox * Utilities 8855c49fd3aSAlan Cox */ 8865c49fd3aSAlan Cox 8875c49fd3aSAlan Cox static inline u32 MRST_MSG_READ32(uint port, uint offset) 8885c49fd3aSAlan Cox { 8895c49fd3aSAlan Cox int mcr = (0xD0<<24) | (port << 16) | (offset << 8); 8905c49fd3aSAlan Cox uint32_t ret_val = 0; 8915c49fd3aSAlan Cox struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0); 8925c49fd3aSAlan Cox pci_write_config_dword(pci_root, 0xD0, mcr); 8935c49fd3aSAlan Cox pci_read_config_dword(pci_root, 0xD4, &ret_val); 8945c49fd3aSAlan Cox pci_dev_put(pci_root); 8955c49fd3aSAlan Cox return ret_val; 8965c49fd3aSAlan Cox } 8975c49fd3aSAlan Cox static inline void MRST_MSG_WRITE32(uint port, uint offset, u32 value) 8985c49fd3aSAlan Cox { 8995c49fd3aSAlan Cox int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0; 9005c49fd3aSAlan Cox struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0); 9015c49fd3aSAlan Cox pci_write_config_dword(pci_root, 0xD4, value); 9025c49fd3aSAlan Cox pci_write_config_dword(pci_root, 0xD0, mcr); 9035c49fd3aSAlan Cox pci_dev_put(pci_root); 9045c49fd3aSAlan Cox } 9055c49fd3aSAlan Cox static inline u32 MDFLD_MSG_READ32(uint port, uint offset) 9065c49fd3aSAlan Cox { 9075c49fd3aSAlan Cox int mcr = (0x10<<24) | (port << 16) | (offset << 8); 9085c49fd3aSAlan Cox uint32_t ret_val = 0; 9095c49fd3aSAlan Cox struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0); 9105c49fd3aSAlan Cox pci_write_config_dword(pci_root, 0xD0, mcr); 9115c49fd3aSAlan Cox pci_read_config_dword(pci_root, 0xD4, &ret_val); 9125c49fd3aSAlan Cox pci_dev_put(pci_root); 9135c49fd3aSAlan Cox return ret_val; 9145c49fd3aSAlan Cox } 9155c49fd3aSAlan Cox static inline void MDFLD_MSG_WRITE32(uint port, uint offset, u32 value) 9165c49fd3aSAlan Cox { 9175c49fd3aSAlan Cox int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0; 9185c49fd3aSAlan Cox struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0); 9195c49fd3aSAlan Cox pci_write_config_dword(pci_root, 0xD4, value); 9205c49fd3aSAlan Cox pci_write_config_dword(pci_root, 0xD0, mcr); 9215c49fd3aSAlan Cox pci_dev_put(pci_root); 9225c49fd3aSAlan Cox } 9235c49fd3aSAlan Cox 9245c49fd3aSAlan Cox static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg) 9255c49fd3aSAlan Cox { 9265c49fd3aSAlan Cox struct drm_psb_private *dev_priv = dev->dev_private; 9275c49fd3aSAlan Cox return ioread32(dev_priv->vdc_reg + reg); 9285c49fd3aSAlan Cox } 9295c49fd3aSAlan Cox 9305c49fd3aSAlan Cox #define REG_READ(reg) REGISTER_READ(dev, (reg)) 9315c49fd3aSAlan Cox 9325c49fd3aSAlan Cox static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg, 9335c49fd3aSAlan Cox uint32_t val) 9345c49fd3aSAlan Cox { 9355c49fd3aSAlan Cox struct drm_psb_private *dev_priv = dev->dev_private; 9365c49fd3aSAlan Cox iowrite32((val), dev_priv->vdc_reg + (reg)); 9375c49fd3aSAlan Cox } 9385c49fd3aSAlan Cox 9395c49fd3aSAlan Cox #define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val)) 9405c49fd3aSAlan Cox 9415c49fd3aSAlan Cox static inline void REGISTER_WRITE16(struct drm_device *dev, 9425c49fd3aSAlan Cox uint32_t reg, uint32_t val) 9435c49fd3aSAlan Cox { 9445c49fd3aSAlan Cox struct drm_psb_private *dev_priv = dev->dev_private; 9455c49fd3aSAlan Cox iowrite16((val), dev_priv->vdc_reg + (reg)); 9465c49fd3aSAlan Cox } 9475c49fd3aSAlan Cox 9485c49fd3aSAlan Cox #define REG_WRITE16(reg, val) REGISTER_WRITE16(dev, (reg), (val)) 9495c49fd3aSAlan Cox 9505c49fd3aSAlan Cox static inline void REGISTER_WRITE8(struct drm_device *dev, 9515c49fd3aSAlan Cox uint32_t reg, uint32_t val) 9525c49fd3aSAlan Cox { 9535c49fd3aSAlan Cox struct drm_psb_private *dev_priv = dev->dev_private; 9545c49fd3aSAlan Cox iowrite8((val), dev_priv->vdc_reg + (reg)); 9555c49fd3aSAlan Cox } 9565c49fd3aSAlan Cox 9575c49fd3aSAlan Cox #define REG_WRITE8(reg, val) REGISTER_WRITE8(dev, (reg), (val)) 9585c49fd3aSAlan Cox 9595c49fd3aSAlan Cox #define PSB_WVDC32(_val, _offs) iowrite32(_val, dev_priv->vdc_reg + (_offs)) 9605c49fd3aSAlan Cox #define PSB_RVDC32(_offs) ioread32(dev_priv->vdc_reg + (_offs)) 9615c49fd3aSAlan Cox 9625c49fd3aSAlan Cox /* #define TRAP_SGX_PM_FAULT 1 */ 9635c49fd3aSAlan Cox #ifdef TRAP_SGX_PM_FAULT 9645c49fd3aSAlan Cox #define PSB_RSGX32(_offs) \ 9655c49fd3aSAlan Cox ({ \ 9665c49fd3aSAlan Cox if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) { \ 9675c49fd3aSAlan Cox printk(KERN_ERR \ 9685c49fd3aSAlan Cox "access sgx when it's off!! (READ) %s, %d\n", \ 9695c49fd3aSAlan Cox __FILE__, __LINE__); \ 9705c49fd3aSAlan Cox melay(1000); \ 9715c49fd3aSAlan Cox } \ 9725c49fd3aSAlan Cox ioread32(dev_priv->sgx_reg + (_offs)); \ 9735c49fd3aSAlan Cox }) 9745c49fd3aSAlan Cox #else 9755c49fd3aSAlan Cox #define PSB_RSGX32(_offs) ioread32(dev_priv->sgx_reg + (_offs)) 9765c49fd3aSAlan Cox #endif 9775c49fd3aSAlan Cox #define PSB_WSGX32(_val, _offs) iowrite32(_val, dev_priv->sgx_reg + (_offs)) 9785c49fd3aSAlan Cox 9795c49fd3aSAlan Cox #define MSVDX_REG_DUMP 0 9805c49fd3aSAlan Cox 9815c49fd3aSAlan Cox #define PSB_WMSVDX32(_val, _offs) iowrite32(_val, dev_priv->msvdx_reg + (_offs)) 9825c49fd3aSAlan Cox #define PSB_RMSVDX32(_offs) ioread32(dev_priv->msvdx_reg + (_offs)) 9835c49fd3aSAlan Cox 9845c49fd3aSAlan Cox #endif 985