1 /* 2 * Copyright © 2010 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Li Peng <peng.li@intel.com> 25 */ 26 27 #include <linux/export.h> 28 #include <linux/mutex.h> 29 #include <linux/pci.h> 30 #include <linux/i2c.h> 31 #include <linux/interrupt.h> 32 #include <linux/delay.h> 33 34 #include <drm/drm_print.h> 35 36 #include "psb_drv.h" 37 38 #define HDMI_READ(reg) readl(hdmi_dev->regs + (reg)) 39 #define HDMI_WRITE(reg, val) writel(val, hdmi_dev->regs + (reg)) 40 41 #define HDMI_HCR 0x1000 42 #define HCR_DETECT_HDP (1 << 6) 43 #define HCR_ENABLE_HDCP (1 << 5) 44 #define HCR_ENABLE_AUDIO (1 << 2) 45 #define HCR_ENABLE_PIXEL (1 << 1) 46 #define HCR_ENABLE_TMDS (1 << 0) 47 #define HDMI_HICR 0x1004 48 #define HDMI_INTR_I2C_ERROR (1 << 4) 49 #define HDMI_INTR_I2C_FULL (1 << 3) 50 #define HDMI_INTR_I2C_DONE (1 << 2) 51 #define HDMI_INTR_HPD (1 << 0) 52 #define HDMI_HSR 0x1008 53 #define HDMI_HISR 0x100C 54 #define HDMI_HI2CRDB0 0x1200 55 #define HDMI_HI2CHCR 0x1240 56 #define HI2C_HDCP_WRITE (0 << 2) 57 #define HI2C_HDCP_RI_READ (1 << 2) 58 #define HI2C_HDCP_READ (2 << 2) 59 #define HI2C_EDID_READ (3 << 2) 60 #define HI2C_READ_CONTINUE (1 << 1) 61 #define HI2C_ENABLE_TRANSACTION (1 << 0) 62 63 #define HDMI_ICRH 0x1100 64 #define HDMI_HI2CTDR0 0x1244 65 #define HDMI_HI2CTDR1 0x1248 66 67 #define I2C_STAT_INIT 0 68 #define I2C_READ_DONE 1 69 #define I2C_TRANSACTION_DONE 2 70 71 struct hdmi_i2c_dev { 72 struct i2c_adapter *adap; 73 struct mutex i2c_lock; 74 struct completion complete; 75 int status; 76 struct i2c_msg *msg; 77 int buf_offset; 78 }; 79 80 static void hdmi_i2c_irq_enable(struct oaktrail_hdmi_dev *hdmi_dev) 81 { 82 u32 temp; 83 84 temp = HDMI_READ(HDMI_HICR); 85 temp |= (HDMI_INTR_I2C_ERROR | HDMI_INTR_I2C_FULL | HDMI_INTR_I2C_DONE); 86 HDMI_WRITE(HDMI_HICR, temp); 87 HDMI_READ(HDMI_HICR); 88 } 89 90 static void hdmi_i2c_irq_disable(struct oaktrail_hdmi_dev *hdmi_dev) 91 { 92 HDMI_WRITE(HDMI_HICR, 0x0); 93 HDMI_READ(HDMI_HICR); 94 } 95 96 static int xfer_read(struct i2c_adapter *adap, struct i2c_msg *pmsg) 97 { 98 struct oaktrail_hdmi_dev *hdmi_dev = i2c_get_adapdata(adap); 99 struct hdmi_i2c_dev *i2c_dev = hdmi_dev->i2c_dev; 100 u32 temp; 101 102 i2c_dev->status = I2C_STAT_INIT; 103 i2c_dev->msg = pmsg; 104 i2c_dev->buf_offset = 0; 105 reinit_completion(&i2c_dev->complete); 106 107 /* Enable I2C transaction */ 108 temp = ((pmsg->len) << 20) | HI2C_EDID_READ | HI2C_ENABLE_TRANSACTION; 109 HDMI_WRITE(HDMI_HI2CHCR, temp); 110 HDMI_READ(HDMI_HI2CHCR); 111 112 while (i2c_dev->status != I2C_TRANSACTION_DONE) 113 wait_for_completion_interruptible_timeout(&i2c_dev->complete, 114 10 * HZ); 115 116 return 0; 117 } 118 119 static int xfer_write(struct i2c_adapter *adap, struct i2c_msg *pmsg) 120 { 121 /* 122 * XXX: i2c write seems isn't useful for EDID probe, don't do anything 123 */ 124 return 0; 125 } 126 127 static int oaktrail_hdmi_i2c_access(struct i2c_adapter *adap, 128 struct i2c_msg *pmsg, 129 int num) 130 { 131 struct oaktrail_hdmi_dev *hdmi_dev = i2c_get_adapdata(adap); 132 struct hdmi_i2c_dev *i2c_dev = hdmi_dev->i2c_dev; 133 int i; 134 135 mutex_lock(&i2c_dev->i2c_lock); 136 137 /* Enable i2c unit */ 138 HDMI_WRITE(HDMI_ICRH, 0x00008760); 139 140 /* Enable irq */ 141 hdmi_i2c_irq_enable(hdmi_dev); 142 for (i = 0; i < num; i++) { 143 if (pmsg->len && pmsg->buf) { 144 if (pmsg->flags & I2C_M_RD) 145 xfer_read(adap, pmsg); 146 else 147 xfer_write(adap, pmsg); 148 } 149 pmsg++; /* next message */ 150 } 151 152 /* Disable irq */ 153 hdmi_i2c_irq_disable(hdmi_dev); 154 155 mutex_unlock(&i2c_dev->i2c_lock); 156 157 return i; 158 } 159 160 static u32 oaktrail_hdmi_i2c_func(struct i2c_adapter *adapter) 161 { 162 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR; 163 } 164 165 static const struct i2c_algorithm oaktrail_hdmi_i2c_algorithm = { 166 .master_xfer = oaktrail_hdmi_i2c_access, 167 .functionality = oaktrail_hdmi_i2c_func, 168 }; 169 170 static struct i2c_adapter oaktrail_hdmi_i2c_adapter = { 171 .name = "oaktrail_hdmi_i2c", 172 .nr = 3, 173 .owner = THIS_MODULE, 174 .algo = &oaktrail_hdmi_i2c_algorithm, 175 }; 176 177 static void hdmi_i2c_read(struct oaktrail_hdmi_dev *hdmi_dev) 178 { 179 struct hdmi_i2c_dev *i2c_dev = hdmi_dev->i2c_dev; 180 struct i2c_msg *msg = i2c_dev->msg; 181 u8 *buf = msg->buf; 182 u32 temp; 183 int i, offset; 184 185 offset = i2c_dev->buf_offset; 186 for (i = 0; i < 0x10; i++) { 187 temp = HDMI_READ(HDMI_HI2CRDB0 + (i * 4)); 188 memcpy(buf + (offset + i * 4), &temp, 4); 189 } 190 i2c_dev->buf_offset += (0x10 * 4); 191 192 /* clearing read buffer full intr */ 193 temp = HDMI_READ(HDMI_HISR); 194 HDMI_WRITE(HDMI_HISR, temp | HDMI_INTR_I2C_FULL); 195 HDMI_READ(HDMI_HISR); 196 197 /* continue read transaction */ 198 temp = HDMI_READ(HDMI_HI2CHCR); 199 HDMI_WRITE(HDMI_HI2CHCR, temp | HI2C_READ_CONTINUE); 200 HDMI_READ(HDMI_HI2CHCR); 201 202 i2c_dev->status = I2C_READ_DONE; 203 return; 204 } 205 206 static void hdmi_i2c_transaction_done(struct oaktrail_hdmi_dev *hdmi_dev) 207 { 208 struct hdmi_i2c_dev *i2c_dev = hdmi_dev->i2c_dev; 209 u32 temp; 210 211 /* clear transaction done intr */ 212 temp = HDMI_READ(HDMI_HISR); 213 HDMI_WRITE(HDMI_HISR, temp | HDMI_INTR_I2C_DONE); 214 HDMI_READ(HDMI_HISR); 215 216 217 temp = HDMI_READ(HDMI_HI2CHCR); 218 HDMI_WRITE(HDMI_HI2CHCR, temp & ~HI2C_ENABLE_TRANSACTION); 219 HDMI_READ(HDMI_HI2CHCR); 220 221 i2c_dev->status = I2C_TRANSACTION_DONE; 222 return; 223 } 224 225 static irqreturn_t oaktrail_hdmi_i2c_handler(int this_irq, void *dev) 226 { 227 struct oaktrail_hdmi_dev *hdmi_dev = dev; 228 struct hdmi_i2c_dev *i2c_dev = hdmi_dev->i2c_dev; 229 u32 stat; 230 231 stat = HDMI_READ(HDMI_HISR); 232 233 if (stat & HDMI_INTR_HPD) { 234 HDMI_WRITE(HDMI_HISR, stat | HDMI_INTR_HPD); 235 HDMI_READ(HDMI_HISR); 236 } 237 238 if (stat & HDMI_INTR_I2C_FULL) 239 hdmi_i2c_read(hdmi_dev); 240 241 if (stat & HDMI_INTR_I2C_DONE) 242 hdmi_i2c_transaction_done(hdmi_dev); 243 244 complete(&i2c_dev->complete); 245 246 return IRQ_HANDLED; 247 } 248 249 /* 250 * choose alternate function 2 of GPIO pin 52, 53, 251 * which is used by HDMI I2C logic 252 */ 253 static void oaktrail_hdmi_i2c_gpio_fix(void) 254 { 255 void __iomem *base; 256 unsigned int gpio_base = 0xff12c000; 257 int gpio_len = 0x1000; 258 u32 temp; 259 260 base = ioremap((resource_size_t)gpio_base, gpio_len); 261 if (base == NULL) { 262 DRM_ERROR("gpio ioremap fail\n"); 263 return; 264 } 265 266 temp = readl(base + 0x44); 267 DRM_DEBUG_DRIVER("old gpio val %x\n", temp); 268 writel((temp | 0x00000a00), (base + 0x44)); 269 temp = readl(base + 0x44); 270 DRM_DEBUG_DRIVER("new gpio val %x\n", temp); 271 272 iounmap(base); 273 } 274 275 int oaktrail_hdmi_i2c_init(struct pci_dev *dev) 276 { 277 struct oaktrail_hdmi_dev *hdmi_dev; 278 struct hdmi_i2c_dev *i2c_dev; 279 int ret; 280 281 hdmi_dev = pci_get_drvdata(dev); 282 283 i2c_dev = kzalloc(sizeof(struct hdmi_i2c_dev), GFP_KERNEL); 284 if (!i2c_dev) 285 return -ENOMEM; 286 287 i2c_dev->adap = &oaktrail_hdmi_i2c_adapter; 288 i2c_dev->status = I2C_STAT_INIT; 289 init_completion(&i2c_dev->complete); 290 mutex_init(&i2c_dev->i2c_lock); 291 i2c_set_adapdata(&oaktrail_hdmi_i2c_adapter, hdmi_dev); 292 hdmi_dev->i2c_dev = i2c_dev; 293 294 /* Enable HDMI I2C function on gpio */ 295 oaktrail_hdmi_i2c_gpio_fix(); 296 297 /* request irq */ 298 ret = request_irq(dev->irq, oaktrail_hdmi_i2c_handler, IRQF_SHARED, 299 oaktrail_hdmi_i2c_adapter.name, hdmi_dev); 300 if (ret) { 301 DRM_ERROR("Failed to request IRQ for I2C controller\n"); 302 goto free_dev; 303 } 304 305 /* Adapter registration */ 306 ret = i2c_add_numbered_adapter(&oaktrail_hdmi_i2c_adapter); 307 if (ret) { 308 DRM_ERROR("Failed to add I2C adapter\n"); 309 goto free_irq; 310 } 311 312 return 0; 313 314 free_irq: 315 free_irq(dev->irq, hdmi_dev); 316 free_dev: 317 kfree(i2c_dev); 318 319 return ret; 320 } 321 322 void oaktrail_hdmi_i2c_exit(struct pci_dev *dev) 323 { 324 struct oaktrail_hdmi_dev *hdmi_dev; 325 struct hdmi_i2c_dev *i2c_dev; 326 327 hdmi_dev = pci_get_drvdata(dev); 328 i2c_del_adapter(&oaktrail_hdmi_i2c_adapter); 329 330 i2c_dev = hdmi_dev->i2c_dev; 331 kfree(i2c_dev); 332 free_irq(dev->irq, hdmi_dev); 333 } 334