1 // SPDX-License-Identifier: GPL-2.0-only 2 /************************************************************************** 3 * Copyright (c) 2011, Intel Corporation. 4 * All Rights Reserved. 5 * 6 **************************************************************************/ 7 8 /* TODO 9 * - Split functions by vbt type 10 * - Make them all take drm_device 11 * - Check ioremap failures 12 */ 13 14 #include <drm/drm.h> 15 16 #include "mid_bios.h" 17 #include "psb_drv.h" 18 19 static void mid_get_fuse_settings(struct drm_device *dev) 20 { 21 struct drm_psb_private *dev_priv = dev->dev_private; 22 struct pci_dev *pdev = to_pci_dev(dev->dev); 23 struct pci_dev *pci_root = 24 pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus), 25 0, 0); 26 uint32_t fuse_value = 0; 27 uint32_t fuse_value_tmp = 0; 28 29 #define FB_REG06 0xD0810600 30 #define FB_MIPI_DISABLE (1 << 11) 31 #define FB_REG09 0xD0810900 32 #define FB_SKU_MASK 0x7000 33 #define FB_SKU_SHIFT 12 34 #define FB_SKU_100 0 35 #define FB_SKU_100L 1 36 #define FB_SKU_83 2 37 if (pci_root == NULL) { 38 WARN_ON(1); 39 return; 40 } 41 42 43 pci_write_config_dword(pci_root, 0xD0, FB_REG06); 44 pci_read_config_dword(pci_root, 0xD4, &fuse_value); 45 46 /* FB_MIPI_DISABLE doesn't mean LVDS on with Medfield */ 47 if (IS_MRST(dev)) 48 dev_priv->iLVDS_enable = fuse_value & FB_MIPI_DISABLE; 49 50 DRM_INFO("internal display is %s\n", 51 dev_priv->iLVDS_enable ? "LVDS display" : "MIPI display"); 52 53 /* Prevent runtime suspend at start*/ 54 if (dev_priv->iLVDS_enable) { 55 dev_priv->is_lvds_on = true; 56 dev_priv->is_mipi_on = false; 57 } else { 58 dev_priv->is_mipi_on = true; 59 dev_priv->is_lvds_on = false; 60 } 61 62 dev_priv->video_device_fuse = fuse_value; 63 64 pci_write_config_dword(pci_root, 0xD0, FB_REG09); 65 pci_read_config_dword(pci_root, 0xD4, &fuse_value); 66 67 dev_dbg(dev->dev, "SKU values is 0x%x.\n", fuse_value); 68 fuse_value_tmp = (fuse_value & FB_SKU_MASK) >> FB_SKU_SHIFT; 69 70 dev_priv->fuse_reg_value = fuse_value; 71 72 switch (fuse_value_tmp) { 73 case FB_SKU_100: 74 dev_priv->core_freq = 200; 75 break; 76 case FB_SKU_100L: 77 dev_priv->core_freq = 100; 78 break; 79 case FB_SKU_83: 80 dev_priv->core_freq = 166; 81 break; 82 default: 83 dev_warn(dev->dev, "Invalid SKU values, SKU value = 0x%08x\n", 84 fuse_value_tmp); 85 dev_priv->core_freq = 0; 86 } 87 dev_dbg(dev->dev, "LNC core clk is %dMHz.\n", dev_priv->core_freq); 88 pci_dev_put(pci_root); 89 } 90 91 /* 92 * Get the revison ID, B0:D2:F0;0x08 93 */ 94 static void mid_get_pci_revID(struct drm_psb_private *dev_priv) 95 { 96 uint32_t platform_rev_id = 0; 97 struct pci_dev *pdev = to_pci_dev(dev_priv->dev->dev); 98 int domain = pci_domain_nr(pdev->bus); 99 struct pci_dev *pci_gfx_root = 100 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(2, 0)); 101 102 if (pci_gfx_root == NULL) { 103 WARN_ON(1); 104 return; 105 } 106 pci_read_config_dword(pci_gfx_root, 0x08, &platform_rev_id); 107 dev_priv->platform_rev_id = (uint8_t) platform_rev_id; 108 pci_dev_put(pci_gfx_root); 109 dev_dbg(dev_priv->dev->dev, "platform_rev_id is %x\n", 110 dev_priv->platform_rev_id); 111 } 112 113 struct mid_vbt_header { 114 u32 signature; 115 u8 revision; 116 } __packed; 117 118 /* The same for r0 and r1 */ 119 struct vbt_r0 { 120 struct mid_vbt_header vbt_header; 121 u8 size; 122 u8 checksum; 123 } __packed; 124 125 struct vbt_r10 { 126 struct mid_vbt_header vbt_header; 127 u8 checksum; 128 u16 size; 129 u8 panel_count; 130 u8 primary_panel_idx; 131 u8 secondary_panel_idx; 132 u8 __reserved[5]; 133 } __packed; 134 135 static int read_vbt_r0(u32 addr, struct vbt_r0 *vbt) 136 { 137 void __iomem *vbt_virtual; 138 139 vbt_virtual = ioremap(addr, sizeof(*vbt)); 140 if (vbt_virtual == NULL) 141 return -1; 142 143 memcpy_fromio(vbt, vbt_virtual, sizeof(*vbt)); 144 iounmap(vbt_virtual); 145 146 return 0; 147 } 148 149 static int read_vbt_r10(u32 addr, struct vbt_r10 *vbt) 150 { 151 void __iomem *vbt_virtual; 152 153 vbt_virtual = ioremap(addr, sizeof(*vbt)); 154 if (!vbt_virtual) 155 return -1; 156 157 memcpy_fromio(vbt, vbt_virtual, sizeof(*vbt)); 158 iounmap(vbt_virtual); 159 160 return 0; 161 } 162 163 static int mid_get_vbt_data_r0(struct drm_psb_private *dev_priv, u32 addr) 164 { 165 struct vbt_r0 vbt; 166 void __iomem *gct_virtual; 167 struct gct_r0 gct; 168 u8 bpi; 169 170 if (read_vbt_r0(addr, &vbt)) 171 return -1; 172 173 gct_virtual = ioremap(addr + sizeof(vbt), vbt.size - sizeof(vbt)); 174 if (!gct_virtual) 175 return -1; 176 memcpy_fromio(&gct, gct_virtual, sizeof(gct)); 177 iounmap(gct_virtual); 178 179 bpi = gct.PD.BootPanelIndex; 180 dev_priv->gct_data.bpi = bpi; 181 dev_priv->gct_data.pt = gct.PD.PanelType; 182 dev_priv->gct_data.DTD = gct.panel[bpi].DTD; 183 dev_priv->gct_data.Panel_Port_Control = 184 gct.panel[bpi].Panel_Port_Control; 185 dev_priv->gct_data.Panel_MIPI_Display_Descriptor = 186 gct.panel[bpi].Panel_MIPI_Display_Descriptor; 187 188 return 0; 189 } 190 191 static int mid_get_vbt_data_r1(struct drm_psb_private *dev_priv, u32 addr) 192 { 193 struct vbt_r0 vbt; 194 void __iomem *gct_virtual; 195 struct gct_r1 gct; 196 u8 bpi; 197 198 if (read_vbt_r0(addr, &vbt)) 199 return -1; 200 201 gct_virtual = ioremap(addr + sizeof(vbt), vbt.size - sizeof(vbt)); 202 if (!gct_virtual) 203 return -1; 204 memcpy_fromio(&gct, gct_virtual, sizeof(gct)); 205 iounmap(gct_virtual); 206 207 bpi = gct.PD.BootPanelIndex; 208 dev_priv->gct_data.bpi = bpi; 209 dev_priv->gct_data.pt = gct.PD.PanelType; 210 dev_priv->gct_data.DTD = gct.panel[bpi].DTD; 211 dev_priv->gct_data.Panel_Port_Control = 212 gct.panel[bpi].Panel_Port_Control; 213 dev_priv->gct_data.Panel_MIPI_Display_Descriptor = 214 gct.panel[bpi].Panel_MIPI_Display_Descriptor; 215 216 return 0; 217 } 218 219 static int mid_get_vbt_data_r10(struct drm_psb_private *dev_priv, u32 addr) 220 { 221 struct vbt_r10 vbt; 222 void __iomem *gct_virtual; 223 struct gct_r10 *gct; 224 struct oaktrail_timing_info *dp_ti = &dev_priv->gct_data.DTD; 225 struct gct_r10_timing_info *ti; 226 int ret = -1; 227 228 if (read_vbt_r10(addr, &vbt)) 229 return -1; 230 231 gct = kmalloc_array(vbt.panel_count, sizeof(*gct), GFP_KERNEL); 232 if (!gct) 233 return -ENOMEM; 234 235 gct_virtual = ioremap(addr + sizeof(vbt), 236 sizeof(*gct) * vbt.panel_count); 237 if (!gct_virtual) 238 goto out; 239 memcpy_fromio(gct, gct_virtual, sizeof(*gct)); 240 iounmap(gct_virtual); 241 242 dev_priv->gct_data.bpi = vbt.primary_panel_idx; 243 dev_priv->gct_data.Panel_MIPI_Display_Descriptor = 244 gct[vbt.primary_panel_idx].Panel_MIPI_Display_Descriptor; 245 246 ti = &gct[vbt.primary_panel_idx].DTD; 247 dp_ti->pixel_clock = ti->pixel_clock; 248 dp_ti->hactive_hi = ti->hactive_hi; 249 dp_ti->hactive_lo = ti->hactive_lo; 250 dp_ti->hblank_hi = ti->hblank_hi; 251 dp_ti->hblank_lo = ti->hblank_lo; 252 dp_ti->hsync_offset_hi = ti->hsync_offset_hi; 253 dp_ti->hsync_offset_lo = ti->hsync_offset_lo; 254 dp_ti->hsync_pulse_width_hi = ti->hsync_pulse_width_hi; 255 dp_ti->hsync_pulse_width_lo = ti->hsync_pulse_width_lo; 256 dp_ti->vactive_hi = ti->vactive_hi; 257 dp_ti->vactive_lo = ti->vactive_lo; 258 dp_ti->vblank_hi = ti->vblank_hi; 259 dp_ti->vblank_lo = ti->vblank_lo; 260 dp_ti->vsync_offset_hi = ti->vsync_offset_hi; 261 dp_ti->vsync_offset_lo = ti->vsync_offset_lo; 262 dp_ti->vsync_pulse_width_hi = ti->vsync_pulse_width_hi; 263 dp_ti->vsync_pulse_width_lo = ti->vsync_pulse_width_lo; 264 265 ret = 0; 266 out: 267 kfree(gct); 268 return ret; 269 } 270 271 static void mid_get_vbt_data(struct drm_psb_private *dev_priv) 272 { 273 struct drm_device *dev = dev_priv->dev; 274 struct pci_dev *pdev = to_pci_dev(dev->dev); 275 u32 addr; 276 u8 __iomem *vbt_virtual; 277 struct mid_vbt_header vbt_header; 278 struct pci_dev *pci_gfx_root = 279 pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus), 280 0, PCI_DEVFN(2, 0)); 281 int ret = -1; 282 283 /* Get the address of the platform config vbt */ 284 pci_read_config_dword(pci_gfx_root, 0xFC, &addr); 285 pci_dev_put(pci_gfx_root); 286 287 dev_dbg(dev->dev, "drm platform config address is %x\n", addr); 288 289 if (!addr) 290 goto out; 291 292 /* get the virtual address of the vbt */ 293 vbt_virtual = ioremap(addr, sizeof(vbt_header)); 294 if (!vbt_virtual) 295 goto out; 296 297 memcpy_fromio(&vbt_header, vbt_virtual, sizeof(vbt_header)); 298 iounmap(vbt_virtual); 299 300 if (memcmp(&vbt_header.signature, "$GCT", 4)) 301 goto out; 302 303 dev_dbg(dev->dev, "GCT revision is %02x\n", vbt_header.revision); 304 305 switch (vbt_header.revision) { 306 case 0x00: 307 ret = mid_get_vbt_data_r0(dev_priv, addr); 308 break; 309 case 0x01: 310 ret = mid_get_vbt_data_r1(dev_priv, addr); 311 break; 312 case 0x10: 313 ret = mid_get_vbt_data_r10(dev_priv, addr); 314 break; 315 default: 316 dev_err(dev->dev, "Unknown revision of GCT!\n"); 317 } 318 319 out: 320 if (ret) 321 dev_err(dev->dev, "Unable to read GCT!"); 322 else 323 dev_priv->has_gct = true; 324 } 325 326 int mid_chip_setup(struct drm_device *dev) 327 { 328 struct drm_psb_private *dev_priv = dev->dev_private; 329 mid_get_fuse_settings(dev); 330 mid_get_vbt_data(dev_priv); 331 mid_get_pci_revID(dev_priv); 332 return 0; 333 } 334