1 /* 2 * Copyright © 2006-2011 Intel Corporation 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program; if not, write to the Free Software Foundation, Inc., 15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 16 * 17 * Authors: 18 * Eric Anholt <eric@anholt.net> 19 */ 20 21 #include <linux/i2c.h> 22 #include <linux/pm_runtime.h> 23 24 #include <drm/drmP.h> 25 #include "framebuffer.h" 26 #include "psb_drv.h" 27 #include "psb_intel_drv.h" 28 #include "psb_intel_reg.h" 29 #include "psb_intel_display.h" 30 #include "power.h" 31 #include "cdv_device.h" 32 33 34 struct cdv_intel_range_t { 35 int min, max; 36 }; 37 38 struct cdv_intel_p2_t { 39 int dot_limit; 40 int p2_slow, p2_fast; 41 }; 42 43 struct cdv_intel_clock_t { 44 /* given values */ 45 int n; 46 int m1, m2; 47 int p1, p2; 48 /* derived values */ 49 int dot; 50 int vco; 51 int m; 52 int p; 53 }; 54 55 #define INTEL_P2_NUM 2 56 57 struct cdv_intel_limit_t { 58 struct cdv_intel_range_t dot, vco, n, m, m1, m2, p, p1; 59 struct cdv_intel_p2_t p2; 60 }; 61 62 #define CDV_LIMIT_SINGLE_LVDS_96 0 63 #define CDV_LIMIT_SINGLE_LVDS_100 1 64 #define CDV_LIMIT_DAC_HDMI_27 2 65 #define CDV_LIMIT_DAC_HDMI_96 3 66 67 static const struct cdv_intel_limit_t cdv_intel_limits[] = { 68 { /* CDV_SIGNLE_LVDS_96MHz */ 69 .dot = {.min = 20000, .max = 115500}, 70 .vco = {.min = 1800000, .max = 3600000}, 71 .n = {.min = 2, .max = 6}, 72 .m = {.min = 60, .max = 160}, 73 .m1 = {.min = 0, .max = 0}, 74 .m2 = {.min = 58, .max = 158}, 75 .p = {.min = 28, .max = 140}, 76 .p1 = {.min = 2, .max = 10}, 77 .p2 = {.dot_limit = 200000, 78 .p2_slow = 14, .p2_fast = 14}, 79 }, 80 { /* CDV_SINGLE_LVDS_100MHz */ 81 .dot = {.min = 20000, .max = 115500}, 82 .vco = {.min = 1800000, .max = 3600000}, 83 .n = {.min = 2, .max = 6}, 84 .m = {.min = 60, .max = 160}, 85 .m1 = {.min = 0, .max = 0}, 86 .m2 = {.min = 58, .max = 158}, 87 .p = {.min = 28, .max = 140}, 88 .p1 = {.min = 2, .max = 10}, 89 /* The single-channel range is 25-112Mhz, and dual-channel 90 * is 80-224Mhz. Prefer single channel as much as possible. 91 */ 92 .p2 = {.dot_limit = 200000, .p2_slow = 14, .p2_fast = 14}, 93 }, 94 { /* CDV_DAC_HDMI_27MHz */ 95 .dot = {.min = 20000, .max = 400000}, 96 .vco = {.min = 1809000, .max = 3564000}, 97 .n = {.min = 1, .max = 1}, 98 .m = {.min = 67, .max = 132}, 99 .m1 = {.min = 0, .max = 0}, 100 .m2 = {.min = 65, .max = 130}, 101 .p = {.min = 5, .max = 90}, 102 .p1 = {.min = 1, .max = 9}, 103 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5}, 104 }, 105 { /* CDV_DAC_HDMI_96MHz */ 106 .dot = {.min = 20000, .max = 400000}, 107 .vco = {.min = 1800000, .max = 3600000}, 108 .n = {.min = 2, .max = 6}, 109 .m = {.min = 60, .max = 160}, 110 .m1 = {.min = 0, .max = 0}, 111 .m2 = {.min = 58, .max = 158}, 112 .p = {.min = 5, .max = 100}, 113 .p1 = {.min = 1, .max = 10}, 114 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5}, 115 }, 116 }; 117 118 #define _wait_for(COND, MS, W) ({ \ 119 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \ 120 int ret__ = 0; \ 121 while (!(COND)) { \ 122 if (time_after(jiffies, timeout__)) { \ 123 ret__ = -ETIMEDOUT; \ 124 break; \ 125 } \ 126 if (W && !in_dbg_master()) \ 127 msleep(W); \ 128 } \ 129 ret__; \ 130 }) 131 132 #define wait_for(COND, MS) _wait_for(COND, MS, 1) 133 134 135 static int cdv_sb_read(struct drm_device *dev, u32 reg, u32 *val) 136 { 137 int ret; 138 139 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); 140 if (ret) { 141 DRM_ERROR("timeout waiting for SB to idle before read\n"); 142 return ret; 143 } 144 145 REG_WRITE(SB_ADDR, reg); 146 REG_WRITE(SB_PCKT, 147 SET_FIELD(SB_OPCODE_READ, SB_OPCODE) | 148 SET_FIELD(SB_DEST_DPLL, SB_DEST) | 149 SET_FIELD(0xf, SB_BYTE_ENABLE)); 150 151 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); 152 if (ret) { 153 DRM_ERROR("timeout waiting for SB to idle after read\n"); 154 return ret; 155 } 156 157 *val = REG_READ(SB_DATA); 158 159 return 0; 160 } 161 162 static int cdv_sb_write(struct drm_device *dev, u32 reg, u32 val) 163 { 164 int ret; 165 static bool dpio_debug = true; 166 u32 temp; 167 168 if (dpio_debug) { 169 if (cdv_sb_read(dev, reg, &temp) == 0) 170 DRM_DEBUG_KMS("0x%08x: 0x%08x (before)\n", reg, temp); 171 DRM_DEBUG_KMS("0x%08x: 0x%08x\n", reg, val); 172 } 173 174 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); 175 if (ret) { 176 DRM_ERROR("timeout waiting for SB to idle before write\n"); 177 return ret; 178 } 179 180 REG_WRITE(SB_ADDR, reg); 181 REG_WRITE(SB_DATA, val); 182 REG_WRITE(SB_PCKT, 183 SET_FIELD(SB_OPCODE_WRITE, SB_OPCODE) | 184 SET_FIELD(SB_DEST_DPLL, SB_DEST) | 185 SET_FIELD(0xf, SB_BYTE_ENABLE)); 186 187 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); 188 if (ret) { 189 DRM_ERROR("timeout waiting for SB to idle after write\n"); 190 return ret; 191 } 192 193 if (dpio_debug) { 194 if (cdv_sb_read(dev, reg, &temp) == 0) 195 DRM_DEBUG_KMS("0x%08x: 0x%08x (after)\n", reg, temp); 196 } 197 198 return 0; 199 } 200 201 /* Reset the DPIO configuration register. The BIOS does this at every 202 * mode set. 203 */ 204 static void cdv_sb_reset(struct drm_device *dev) 205 { 206 207 REG_WRITE(DPIO_CFG, 0); 208 REG_READ(DPIO_CFG); 209 REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N); 210 } 211 212 /* Unlike most Intel display engines, on Cedarview the DPLL registers 213 * are behind this sideband bus. They must be programmed while the 214 * DPLL reference clock is on in the DPLL control register, but before 215 * the DPLL is enabled in the DPLL control register. 216 */ 217 static int 218 cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc, 219 struct cdv_intel_clock_t *clock) 220 { 221 struct psb_intel_crtc *psb_crtc = 222 to_psb_intel_crtc(crtc); 223 int pipe = psb_crtc->pipe; 224 u32 m, n_vco, p; 225 int ret = 0; 226 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; 227 u32 ref_value; 228 229 cdv_sb_reset(dev); 230 231 if ((REG_READ(dpll_reg) & DPLL_SYNCLOCK_ENABLE) == 0) { 232 DRM_ERROR("Attempting to set DPLL with refclk disabled\n"); 233 return -EBUSY; 234 } 235 236 /* Follow the BIOS and write the REF/SFR Register. Hardcoded value */ 237 ref_value = 0x68A701; 238 239 cdv_sb_write(dev, SB_REF_SFR(pipe), ref_value); 240 241 /* We don't know what the other fields of these regs are, so 242 * leave them in place. 243 */ 244 ret = cdv_sb_read(dev, SB_M(pipe), &m); 245 if (ret) 246 return ret; 247 m &= ~SB_M_DIVIDER_MASK; 248 m |= ((clock->m2) << SB_M_DIVIDER_SHIFT); 249 ret = cdv_sb_write(dev, SB_M(pipe), m); 250 if (ret) 251 return ret; 252 253 ret = cdv_sb_read(dev, SB_N_VCO(pipe), &n_vco); 254 if (ret) 255 return ret; 256 257 /* Follow the BIOS to program the N_DIVIDER REG */ 258 n_vco &= 0xFFFF; 259 n_vco |= 0x107; 260 n_vco &= ~(SB_N_VCO_SEL_MASK | 261 SB_N_DIVIDER_MASK | 262 SB_N_CB_TUNE_MASK); 263 264 n_vco |= ((clock->n) << SB_N_DIVIDER_SHIFT); 265 266 if (clock->vco < 2250000) { 267 n_vco |= (2 << SB_N_CB_TUNE_SHIFT); 268 n_vco |= (0 << SB_N_VCO_SEL_SHIFT); 269 } else if (clock->vco < 2750000) { 270 n_vco |= (1 << SB_N_CB_TUNE_SHIFT); 271 n_vco |= (1 << SB_N_VCO_SEL_SHIFT); 272 } else if (clock->vco < 3300000) { 273 n_vco |= (0 << SB_N_CB_TUNE_SHIFT); 274 n_vco |= (2 << SB_N_VCO_SEL_SHIFT); 275 } else { 276 n_vco |= (0 << SB_N_CB_TUNE_SHIFT); 277 n_vco |= (3 << SB_N_VCO_SEL_SHIFT); 278 } 279 280 ret = cdv_sb_write(dev, SB_N_VCO(pipe), n_vco); 281 if (ret) 282 return ret; 283 284 ret = cdv_sb_read(dev, SB_P(pipe), &p); 285 if (ret) 286 return ret; 287 p &= ~(SB_P2_DIVIDER_MASK | SB_P1_DIVIDER_MASK); 288 p |= SET_FIELD(clock->p1, SB_P1_DIVIDER); 289 switch (clock->p2) { 290 case 5: 291 p |= SET_FIELD(SB_P2_5, SB_P2_DIVIDER); 292 break; 293 case 10: 294 p |= SET_FIELD(SB_P2_10, SB_P2_DIVIDER); 295 break; 296 case 14: 297 p |= SET_FIELD(SB_P2_14, SB_P2_DIVIDER); 298 break; 299 case 7: 300 p |= SET_FIELD(SB_P2_7, SB_P2_DIVIDER); 301 break; 302 default: 303 DRM_ERROR("Bad P2 clock: %d\n", clock->p2); 304 return -EINVAL; 305 } 306 ret = cdv_sb_write(dev, SB_P(pipe), p); 307 if (ret) 308 return ret; 309 310 /* always Program the Lane Register for the Pipe A*/ 311 if (pipe == 0) { 312 /* Program the Lane0/1 for HDMI B */ 313 u32 lane_reg, lane_value; 314 315 lane_reg = PSB_LANE0; 316 cdv_sb_read(dev, lane_reg, &lane_value); 317 lane_value &= ~(LANE_PLL_MASK); 318 lane_value |= LANE_PLL_ENABLE; 319 cdv_sb_write(dev, lane_reg, lane_value); 320 321 lane_reg = PSB_LANE1; 322 cdv_sb_read(dev, lane_reg, &lane_value); 323 lane_value &= ~(LANE_PLL_MASK); 324 lane_value |= LANE_PLL_ENABLE; 325 cdv_sb_write(dev, lane_reg, lane_value); 326 327 /* Program the Lane2/3 for HDMI C */ 328 lane_reg = PSB_LANE2; 329 cdv_sb_read(dev, lane_reg, &lane_value); 330 lane_value &= ~(LANE_PLL_MASK); 331 lane_value |= LANE_PLL_ENABLE; 332 cdv_sb_write(dev, lane_reg, lane_value); 333 334 lane_reg = PSB_LANE3; 335 cdv_sb_read(dev, lane_reg, &lane_value); 336 lane_value &= ~(LANE_PLL_MASK); 337 lane_value |= LANE_PLL_ENABLE; 338 cdv_sb_write(dev, lane_reg, lane_value); 339 } 340 341 return 0; 342 } 343 344 /* 345 * Returns whether any encoder on the specified pipe is of the specified type 346 */ 347 bool cdv_intel_pipe_has_type(struct drm_crtc *crtc, int type) 348 { 349 struct drm_device *dev = crtc->dev; 350 struct drm_mode_config *mode_config = &dev->mode_config; 351 struct drm_connector *l_entry; 352 353 list_for_each_entry(l_entry, &mode_config->connector_list, head) { 354 if (l_entry->encoder && l_entry->encoder->crtc == crtc) { 355 struct psb_intel_encoder *psb_intel_encoder = 356 psb_intel_attached_encoder(l_entry); 357 if (psb_intel_encoder->type == type) 358 return true; 359 } 360 } 361 return false; 362 } 363 364 static const struct cdv_intel_limit_t *cdv_intel_limit(struct drm_crtc *crtc, 365 int refclk) 366 { 367 const struct cdv_intel_limit_t *limit; 368 if (cdv_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 369 /* 370 * Now only single-channel LVDS is supported on CDV. If it is 371 * incorrect, please add the dual-channel LVDS. 372 */ 373 if (refclk == 96000) 374 limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_96]; 375 else 376 limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_100]; 377 } else { 378 if (refclk == 27000) 379 limit = &cdv_intel_limits[CDV_LIMIT_DAC_HDMI_27]; 380 else 381 limit = &cdv_intel_limits[CDV_LIMIT_DAC_HDMI_96]; 382 } 383 return limit; 384 } 385 386 /* m1 is reserved as 0 in CDV, n is a ring counter */ 387 static void cdv_intel_clock(struct drm_device *dev, 388 int refclk, struct cdv_intel_clock_t *clock) 389 { 390 clock->m = clock->m2 + 2; 391 clock->p = clock->p1 * clock->p2; 392 clock->vco = (refclk * clock->m) / clock->n; 393 clock->dot = clock->vco / clock->p; 394 } 395 396 397 #define INTELPllInvalid(s) { /* ErrorF (s) */; return false; } 398 static bool cdv_intel_PLL_is_valid(struct drm_crtc *crtc, 399 const struct cdv_intel_limit_t *limit, 400 struct cdv_intel_clock_t *clock) 401 { 402 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) 403 INTELPllInvalid("p1 out of range\n"); 404 if (clock->p < limit->p.min || limit->p.max < clock->p) 405 INTELPllInvalid("p out of range\n"); 406 /* unnecessary to check the range of m(m1/M2)/n again */ 407 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) 408 INTELPllInvalid("vco out of range\n"); 409 /* XXX: We may need to be checking "Dot clock" 410 * depending on the multiplier, connector, etc., 411 * rather than just a single range. 412 */ 413 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) 414 INTELPllInvalid("dot out of range\n"); 415 416 return true; 417 } 418 419 static bool cdv_intel_find_best_PLL(struct drm_crtc *crtc, int target, 420 int refclk, 421 struct cdv_intel_clock_t *best_clock) 422 { 423 struct drm_device *dev = crtc->dev; 424 struct cdv_intel_clock_t clock; 425 const struct cdv_intel_limit_t *limit = cdv_intel_limit(crtc, refclk); 426 int err = target; 427 428 429 if (cdv_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && 430 (REG_READ(LVDS) & LVDS_PORT_EN) != 0) { 431 /* 432 * For LVDS, if the panel is on, just rely on its current 433 * settings for dual-channel. We haven't figured out how to 434 * reliably set up different single/dual channel state, if we 435 * even can. 436 */ 437 if ((REG_READ(LVDS) & LVDS_CLKB_POWER_MASK) == 438 LVDS_CLKB_POWER_UP) 439 clock.p2 = limit->p2.p2_fast; 440 else 441 clock.p2 = limit->p2.p2_slow; 442 } else { 443 if (target < limit->p2.dot_limit) 444 clock.p2 = limit->p2.p2_slow; 445 else 446 clock.p2 = limit->p2.p2_fast; 447 } 448 449 memset(best_clock, 0, sizeof(*best_clock)); 450 clock.m1 = 0; 451 /* m1 is reserved as 0 in CDV, n is a ring counter. 452 So skip the m1 loop */ 453 for (clock.n = limit->n.min; clock.n <= limit->n.max; clock.n++) { 454 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; 455 clock.m2++) { 456 for (clock.p1 = limit->p1.min; 457 clock.p1 <= limit->p1.max; 458 clock.p1++) { 459 int this_err; 460 461 cdv_intel_clock(dev, refclk, &clock); 462 463 if (!cdv_intel_PLL_is_valid(crtc, 464 limit, &clock)) 465 continue; 466 467 this_err = abs(clock.dot - target); 468 if (this_err < err) { 469 *best_clock = clock; 470 err = this_err; 471 } 472 } 473 } 474 } 475 476 return err != target; 477 } 478 479 int cdv_intel_pipe_set_base(struct drm_crtc *crtc, 480 int x, int y, struct drm_framebuffer *old_fb) 481 { 482 struct drm_device *dev = crtc->dev; 483 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 484 struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb); 485 int pipe = psb_intel_crtc->pipe; 486 unsigned long start, offset; 487 int dspbase = (pipe == 0 ? DSPABASE : DSPBBASE); 488 int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF); 489 int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE; 490 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; 491 u32 dspcntr; 492 int ret = 0; 493 494 if (!gma_power_begin(dev, true)) 495 return 0; 496 497 /* no fb bound */ 498 if (!crtc->fb) { 499 dev_err(dev->dev, "No FB bound\n"); 500 goto psb_intel_pipe_cleaner; 501 } 502 503 504 /* We are displaying this buffer, make sure it is actually loaded 505 into the GTT */ 506 ret = psb_gtt_pin(psbfb->gtt); 507 if (ret < 0) 508 goto psb_intel_pipe_set_base_exit; 509 start = psbfb->gtt->offset; 510 offset = y * crtc->fb->pitches[0] + x * (crtc->fb->bits_per_pixel / 8); 511 512 REG_WRITE(dspstride, crtc->fb->pitches[0]); 513 514 dspcntr = REG_READ(dspcntr_reg); 515 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; 516 517 switch (crtc->fb->bits_per_pixel) { 518 case 8: 519 dspcntr |= DISPPLANE_8BPP; 520 break; 521 case 16: 522 if (crtc->fb->depth == 15) 523 dspcntr |= DISPPLANE_15_16BPP; 524 else 525 dspcntr |= DISPPLANE_16BPP; 526 break; 527 case 24: 528 case 32: 529 dspcntr |= DISPPLANE_32BPP_NO_ALPHA; 530 break; 531 default: 532 dev_err(dev->dev, "Unknown color depth\n"); 533 ret = -EINVAL; 534 goto psb_intel_pipe_set_base_exit; 535 } 536 REG_WRITE(dspcntr_reg, dspcntr); 537 538 dev_dbg(dev->dev, 539 "Writing base %08lX %08lX %d %d\n", start, offset, x, y); 540 541 REG_WRITE(dspbase, offset); 542 REG_READ(dspbase); 543 REG_WRITE(dspsurf, start); 544 REG_READ(dspsurf); 545 546 psb_intel_pipe_cleaner: 547 /* If there was a previous display we can now unpin it */ 548 if (old_fb) 549 psb_gtt_unpin(to_psb_fb(old_fb)->gtt); 550 551 psb_intel_pipe_set_base_exit: 552 gma_power_end(dev); 553 return ret; 554 } 555 556 /** 557 * Sets the power management mode of the pipe and plane. 558 * 559 * This code should probably grow support for turning the cursor off and back 560 * on appropriately at the same time as we're turning the pipe off/on. 561 */ 562 static void cdv_intel_crtc_dpms(struct drm_crtc *crtc, int mode) 563 { 564 struct drm_device *dev = crtc->dev; 565 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 566 int pipe = psb_intel_crtc->pipe; 567 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; 568 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; 569 int dspbase_reg = (pipe == 0) ? DSPABASE : DSPBBASE; 570 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; 571 u32 temp; 572 bool enabled; 573 574 /* XXX: When our outputs are all unaware of DPMS modes other than off 575 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. 576 */ 577 switch (mode) { 578 case DRM_MODE_DPMS_ON: 579 case DRM_MODE_DPMS_STANDBY: 580 case DRM_MODE_DPMS_SUSPEND: 581 /* Enable the DPLL */ 582 temp = REG_READ(dpll_reg); 583 if ((temp & DPLL_VCO_ENABLE) == 0) { 584 REG_WRITE(dpll_reg, temp); 585 REG_READ(dpll_reg); 586 /* Wait for the clocks to stabilize. */ 587 udelay(150); 588 REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE); 589 REG_READ(dpll_reg); 590 /* Wait for the clocks to stabilize. */ 591 udelay(150); 592 REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE); 593 REG_READ(dpll_reg); 594 /* Wait for the clocks to stabilize. */ 595 udelay(150); 596 } 597 598 /* Jim Bish - switch plan and pipe per scott */ 599 /* Enable the plane */ 600 temp = REG_READ(dspcntr_reg); 601 if ((temp & DISPLAY_PLANE_ENABLE) == 0) { 602 REG_WRITE(dspcntr_reg, 603 temp | DISPLAY_PLANE_ENABLE); 604 /* Flush the plane changes */ 605 REG_WRITE(dspbase_reg, REG_READ(dspbase_reg)); 606 } 607 608 udelay(150); 609 610 /* Enable the pipe */ 611 temp = REG_READ(pipeconf_reg); 612 if ((temp & PIPEACONF_ENABLE) == 0) 613 REG_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE); 614 615 psb_intel_crtc_load_lut(crtc); 616 617 /* Give the overlay scaler a chance to enable 618 * if it's on this pipe */ 619 /* psb_intel_crtc_dpms_video(crtc, true); TODO */ 620 break; 621 case DRM_MODE_DPMS_OFF: 622 /* Give the overlay scaler a chance to disable 623 * if it's on this pipe */ 624 /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */ 625 626 /* Disable the VGA plane that we never use */ 627 REG_WRITE(VGACNTRL, VGA_DISP_DISABLE); 628 629 /* Jim Bish - changed pipe/plane here as well. */ 630 631 /* Wait for vblank for the disable to take effect */ 632 cdv_intel_wait_for_vblank(dev); 633 634 /* Next, disable display pipes */ 635 temp = REG_READ(pipeconf_reg); 636 if ((temp & PIPEACONF_ENABLE) != 0) { 637 REG_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE); 638 REG_READ(pipeconf_reg); 639 } 640 641 /* Wait for vblank for the disable to take effect. */ 642 cdv_intel_wait_for_vblank(dev); 643 644 udelay(150); 645 646 /* Disable display plane */ 647 temp = REG_READ(dspcntr_reg); 648 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { 649 REG_WRITE(dspcntr_reg, 650 temp & ~DISPLAY_PLANE_ENABLE); 651 /* Flush the plane changes */ 652 REG_WRITE(dspbase_reg, REG_READ(dspbase_reg)); 653 REG_READ(dspbase_reg); 654 } 655 656 temp = REG_READ(dpll_reg); 657 if ((temp & DPLL_VCO_ENABLE) != 0) { 658 REG_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE); 659 REG_READ(dpll_reg); 660 } 661 662 /* Wait for the clocks to turn off. */ 663 udelay(150); 664 break; 665 } 666 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF; 667 /*Set FIFO Watermarks*/ 668 REG_WRITE(DSPARB, 0x3F3E); 669 } 670 671 static void cdv_intel_crtc_prepare(struct drm_crtc *crtc) 672 { 673 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; 674 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); 675 } 676 677 static void cdv_intel_crtc_commit(struct drm_crtc *crtc) 678 { 679 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; 680 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); 681 } 682 683 void cdv_intel_encoder_prepare(struct drm_encoder *encoder) 684 { 685 struct drm_encoder_helper_funcs *encoder_funcs = 686 encoder->helper_private; 687 /* lvds has its own version of prepare see cdv_intel_lvds_prepare */ 688 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); 689 } 690 691 void cdv_intel_encoder_commit(struct drm_encoder *encoder) 692 { 693 struct drm_encoder_helper_funcs *encoder_funcs = 694 encoder->helper_private; 695 /* lvds has its own version of commit see cdv_intel_lvds_commit */ 696 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); 697 } 698 699 static bool cdv_intel_crtc_mode_fixup(struct drm_crtc *crtc, 700 struct drm_display_mode *mode, 701 struct drm_display_mode *adjusted_mode) 702 { 703 return true; 704 } 705 706 707 /** 708 * Return the pipe currently connected to the panel fitter, 709 * or -1 if the panel fitter is not present or not in use 710 */ 711 static int cdv_intel_panel_fitter_pipe(struct drm_device *dev) 712 { 713 u32 pfit_control; 714 715 pfit_control = REG_READ(PFIT_CONTROL); 716 717 /* See if the panel fitter is in use */ 718 if ((pfit_control & PFIT_ENABLE) == 0) 719 return -1; 720 return (pfit_control >> 29) & 0x3; 721 } 722 723 static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc, 724 struct drm_display_mode *mode, 725 struct drm_display_mode *adjusted_mode, 726 int x, int y, 727 struct drm_framebuffer *old_fb) 728 { 729 struct drm_device *dev = crtc->dev; 730 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 731 int pipe = psb_intel_crtc->pipe; 732 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; 733 int dpll_md_reg = (psb_intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD; 734 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; 735 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; 736 int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B; 737 int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B; 738 int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B; 739 int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B; 740 int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B; 741 int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B; 742 int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE; 743 int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS; 744 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC; 745 int refclk; 746 struct cdv_intel_clock_t clock; 747 u32 dpll = 0, dspcntr, pipeconf; 748 bool ok, is_sdvo = false, is_dvo = false; 749 bool is_crt = false, is_lvds = false, is_tv = false; 750 bool is_hdmi = false; 751 struct drm_mode_config *mode_config = &dev->mode_config; 752 struct drm_connector *connector; 753 754 list_for_each_entry(connector, &mode_config->connector_list, head) { 755 struct psb_intel_encoder *psb_intel_encoder = 756 psb_intel_attached_encoder(connector); 757 758 if (!connector->encoder 759 || connector->encoder->crtc != crtc) 760 continue; 761 762 switch (psb_intel_encoder->type) { 763 case INTEL_OUTPUT_LVDS: 764 is_lvds = true; 765 break; 766 case INTEL_OUTPUT_SDVO: 767 is_sdvo = true; 768 break; 769 case INTEL_OUTPUT_DVO: 770 is_dvo = true; 771 break; 772 case INTEL_OUTPUT_TVOUT: 773 is_tv = true; 774 break; 775 case INTEL_OUTPUT_ANALOG: 776 is_crt = true; 777 break; 778 case INTEL_OUTPUT_HDMI: 779 is_hdmi = true; 780 break; 781 } 782 } 783 784 refclk = 96000; 785 786 /* Hack selection about ref clk for CRT */ 787 /* Select 27MHz as the reference clk for HDMI */ 788 if (is_crt || is_hdmi) 789 refclk = 27000; 790 791 drm_mode_debug_printmodeline(adjusted_mode); 792 793 ok = cdv_intel_find_best_PLL(crtc, adjusted_mode->clock, refclk, 794 &clock); 795 if (!ok) { 796 dev_err(dev->dev, "Couldn't find PLL settings for mode!\n"); 797 return 0; 798 } 799 800 dpll = DPLL_VGA_MODE_DIS; 801 if (is_tv) { 802 /* XXX: just matching BIOS for now */ 803 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ 804 dpll |= 3; 805 } 806 dpll |= PLL_REF_INPUT_DREFCLK; 807 808 dpll |= DPLL_SYNCLOCK_ENABLE; 809 dpll |= DPLL_VGA_MODE_DIS; 810 if (is_lvds) 811 dpll |= DPLLB_MODE_LVDS; 812 else 813 dpll |= DPLLB_MODE_DAC_SERIAL; 814 /* dpll |= (2 << 11); */ 815 816 /* setup pipeconf */ 817 pipeconf = REG_READ(pipeconf_reg); 818 819 /* Set up the display plane register */ 820 dspcntr = DISPPLANE_GAMMA_ENABLE; 821 822 if (pipe == 0) 823 dspcntr |= DISPPLANE_SEL_PIPE_A; 824 else 825 dspcntr |= DISPPLANE_SEL_PIPE_B; 826 827 dspcntr |= DISPLAY_PLANE_ENABLE; 828 pipeconf |= PIPEACONF_ENABLE; 829 830 REG_WRITE(dpll_reg, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); 831 REG_READ(dpll_reg); 832 833 cdv_dpll_set_clock_cdv(dev, crtc, &clock); 834 835 udelay(150); 836 837 838 /* The LVDS pin pair needs to be on before the DPLLs are enabled. 839 * This is an exception to the general rule that mode_set doesn't turn 840 * things on. 841 */ 842 if (is_lvds) { 843 u32 lvds = REG_READ(LVDS); 844 845 lvds |= 846 LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | 847 LVDS_PIPEB_SELECT; 848 /* Set the B0-B3 data pairs corresponding to 849 * whether we're going to 850 * set the DPLLs for dual-channel mode or not. 851 */ 852 if (clock.p2 == 7) 853 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; 854 else 855 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); 856 857 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) 858 * appropriately here, but we need to look more 859 * thoroughly into how panels behave in the two modes. 860 */ 861 862 REG_WRITE(LVDS, lvds); 863 REG_READ(LVDS); 864 } 865 866 dpll |= DPLL_VCO_ENABLE; 867 868 /* Disable the panel fitter if it was on our pipe */ 869 if (cdv_intel_panel_fitter_pipe(dev) == pipe) 870 REG_WRITE(PFIT_CONTROL, 0); 871 872 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); 873 drm_mode_debug_printmodeline(mode); 874 875 REG_WRITE(dpll_reg, 876 (REG_READ(dpll_reg) & ~DPLL_LOCK) | DPLL_VCO_ENABLE); 877 REG_READ(dpll_reg); 878 /* Wait for the clocks to stabilize. */ 879 udelay(150); /* 42 usec w/o calibration, 110 with. rounded up. */ 880 881 if (!(REG_READ(dpll_reg) & DPLL_LOCK)) { 882 dev_err(dev->dev, "Failed to get DPLL lock\n"); 883 return -EBUSY; 884 } 885 886 { 887 int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock; 888 REG_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT)); 889 } 890 891 REG_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) | 892 ((adjusted_mode->crtc_htotal - 1) << 16)); 893 REG_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) | 894 ((adjusted_mode->crtc_hblank_end - 1) << 16)); 895 REG_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) | 896 ((adjusted_mode->crtc_hsync_end - 1) << 16)); 897 REG_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) | 898 ((adjusted_mode->crtc_vtotal - 1) << 16)); 899 REG_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) | 900 ((adjusted_mode->crtc_vblank_end - 1) << 16)); 901 REG_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) | 902 ((adjusted_mode->crtc_vsync_end - 1) << 16)); 903 /* pipesrc and dspsize control the size that is scaled from, 904 * which should always be the user's requested size. 905 */ 906 REG_WRITE(dspsize_reg, 907 ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1)); 908 REG_WRITE(dsppos_reg, 0); 909 REG_WRITE(pipesrc_reg, 910 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); 911 REG_WRITE(pipeconf_reg, pipeconf); 912 REG_READ(pipeconf_reg); 913 914 cdv_intel_wait_for_vblank(dev); 915 916 REG_WRITE(dspcntr_reg, dspcntr); 917 918 /* Flush the plane changes */ 919 { 920 struct drm_crtc_helper_funcs *crtc_funcs = 921 crtc->helper_private; 922 crtc_funcs->mode_set_base(crtc, x, y, old_fb); 923 } 924 925 cdv_intel_wait_for_vblank(dev); 926 927 return 0; 928 } 929 930 /** Loads the palette/gamma unit for the CRTC with the prepared values */ 931 void cdv_intel_crtc_load_lut(struct drm_crtc *crtc) 932 { 933 struct drm_device *dev = crtc->dev; 934 struct drm_psb_private *dev_priv = 935 (struct drm_psb_private *)dev->dev_private; 936 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 937 int palreg = PALETTE_A; 938 int i; 939 940 /* The clocks have to be on to load the palette. */ 941 if (!crtc->enabled) 942 return; 943 944 switch (psb_intel_crtc->pipe) { 945 case 0: 946 break; 947 case 1: 948 palreg = PALETTE_B; 949 break; 950 case 2: 951 palreg = PALETTE_C; 952 break; 953 default: 954 dev_err(dev->dev, "Illegal Pipe Number.\n"); 955 return; 956 } 957 958 if (gma_power_begin(dev, false)) { 959 for (i = 0; i < 256; i++) { 960 REG_WRITE(palreg + 4 * i, 961 ((psb_intel_crtc->lut_r[i] + 962 psb_intel_crtc->lut_adj[i]) << 16) | 963 ((psb_intel_crtc->lut_g[i] + 964 psb_intel_crtc->lut_adj[i]) << 8) | 965 (psb_intel_crtc->lut_b[i] + 966 psb_intel_crtc->lut_adj[i])); 967 } 968 gma_power_end(dev); 969 } else { 970 for (i = 0; i < 256; i++) { 971 dev_priv->save_palette_a[i] = 972 ((psb_intel_crtc->lut_r[i] + 973 psb_intel_crtc->lut_adj[i]) << 16) | 974 ((psb_intel_crtc->lut_g[i] + 975 psb_intel_crtc->lut_adj[i]) << 8) | 976 (psb_intel_crtc->lut_b[i] + 977 psb_intel_crtc->lut_adj[i]); 978 } 979 980 } 981 } 982 983 /** 984 * Save HW states of giving crtc 985 */ 986 static void cdv_intel_crtc_save(struct drm_crtc *crtc) 987 { 988 struct drm_device *dev = crtc->dev; 989 /* struct drm_psb_private *dev_priv = 990 (struct drm_psb_private *)dev->dev_private; */ 991 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 992 struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state; 993 int pipeA = (psb_intel_crtc->pipe == 0); 994 uint32_t paletteReg; 995 int i; 996 997 if (!crtc_state) { 998 dev_dbg(dev->dev, "No CRTC state found\n"); 999 return; 1000 } 1001 1002 crtc_state->saveDSPCNTR = REG_READ(pipeA ? DSPACNTR : DSPBCNTR); 1003 crtc_state->savePIPECONF = REG_READ(pipeA ? PIPEACONF : PIPEBCONF); 1004 crtc_state->savePIPESRC = REG_READ(pipeA ? PIPEASRC : PIPEBSRC); 1005 crtc_state->saveFP0 = REG_READ(pipeA ? FPA0 : FPB0); 1006 crtc_state->saveFP1 = REG_READ(pipeA ? FPA1 : FPB1); 1007 crtc_state->saveDPLL = REG_READ(pipeA ? DPLL_A : DPLL_B); 1008 crtc_state->saveHTOTAL = REG_READ(pipeA ? HTOTAL_A : HTOTAL_B); 1009 crtc_state->saveHBLANK = REG_READ(pipeA ? HBLANK_A : HBLANK_B); 1010 crtc_state->saveHSYNC = REG_READ(pipeA ? HSYNC_A : HSYNC_B); 1011 crtc_state->saveVTOTAL = REG_READ(pipeA ? VTOTAL_A : VTOTAL_B); 1012 crtc_state->saveVBLANK = REG_READ(pipeA ? VBLANK_A : VBLANK_B); 1013 crtc_state->saveVSYNC = REG_READ(pipeA ? VSYNC_A : VSYNC_B); 1014 crtc_state->saveDSPSTRIDE = REG_READ(pipeA ? DSPASTRIDE : DSPBSTRIDE); 1015 1016 /*NOTE: DSPSIZE DSPPOS only for psb*/ 1017 crtc_state->saveDSPSIZE = REG_READ(pipeA ? DSPASIZE : DSPBSIZE); 1018 crtc_state->saveDSPPOS = REG_READ(pipeA ? DSPAPOS : DSPBPOS); 1019 1020 crtc_state->saveDSPBASE = REG_READ(pipeA ? DSPABASE : DSPBBASE); 1021 1022 DRM_DEBUG("(%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n", 1023 crtc_state->saveDSPCNTR, 1024 crtc_state->savePIPECONF, 1025 crtc_state->savePIPESRC, 1026 crtc_state->saveFP0, 1027 crtc_state->saveFP1, 1028 crtc_state->saveDPLL, 1029 crtc_state->saveHTOTAL, 1030 crtc_state->saveHBLANK, 1031 crtc_state->saveHSYNC, 1032 crtc_state->saveVTOTAL, 1033 crtc_state->saveVBLANK, 1034 crtc_state->saveVSYNC, 1035 crtc_state->saveDSPSTRIDE, 1036 crtc_state->saveDSPSIZE, 1037 crtc_state->saveDSPPOS, 1038 crtc_state->saveDSPBASE 1039 ); 1040 1041 paletteReg = pipeA ? PALETTE_A : PALETTE_B; 1042 for (i = 0; i < 256; ++i) 1043 crtc_state->savePalette[i] = REG_READ(paletteReg + (i << 2)); 1044 } 1045 1046 /** 1047 * Restore HW states of giving crtc 1048 */ 1049 static void cdv_intel_crtc_restore(struct drm_crtc *crtc) 1050 { 1051 struct drm_device *dev = crtc->dev; 1052 /* struct drm_psb_private * dev_priv = 1053 (struct drm_psb_private *)dev->dev_private; */ 1054 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 1055 struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state; 1056 /* struct drm_crtc_helper_funcs * crtc_funcs = crtc->helper_private; */ 1057 int pipeA = (psb_intel_crtc->pipe == 0); 1058 uint32_t paletteReg; 1059 int i; 1060 1061 if (!crtc_state) { 1062 dev_dbg(dev->dev, "No crtc state\n"); 1063 return; 1064 } 1065 1066 DRM_DEBUG( 1067 "current:(%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n", 1068 REG_READ(pipeA ? DSPACNTR : DSPBCNTR), 1069 REG_READ(pipeA ? PIPEACONF : PIPEBCONF), 1070 REG_READ(pipeA ? PIPEASRC : PIPEBSRC), 1071 REG_READ(pipeA ? FPA0 : FPB0), 1072 REG_READ(pipeA ? FPA1 : FPB1), 1073 REG_READ(pipeA ? DPLL_A : DPLL_B), 1074 REG_READ(pipeA ? HTOTAL_A : HTOTAL_B), 1075 REG_READ(pipeA ? HBLANK_A : HBLANK_B), 1076 REG_READ(pipeA ? HSYNC_A : HSYNC_B), 1077 REG_READ(pipeA ? VTOTAL_A : VTOTAL_B), 1078 REG_READ(pipeA ? VBLANK_A : VBLANK_B), 1079 REG_READ(pipeA ? VSYNC_A : VSYNC_B), 1080 REG_READ(pipeA ? DSPASTRIDE : DSPBSTRIDE), 1081 REG_READ(pipeA ? DSPASIZE : DSPBSIZE), 1082 REG_READ(pipeA ? DSPAPOS : DSPBPOS), 1083 REG_READ(pipeA ? DSPABASE : DSPBBASE) 1084 ); 1085 1086 DRM_DEBUG( 1087 "saved: (%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n", 1088 crtc_state->saveDSPCNTR, 1089 crtc_state->savePIPECONF, 1090 crtc_state->savePIPESRC, 1091 crtc_state->saveFP0, 1092 crtc_state->saveFP1, 1093 crtc_state->saveDPLL, 1094 crtc_state->saveHTOTAL, 1095 crtc_state->saveHBLANK, 1096 crtc_state->saveHSYNC, 1097 crtc_state->saveVTOTAL, 1098 crtc_state->saveVBLANK, 1099 crtc_state->saveVSYNC, 1100 crtc_state->saveDSPSTRIDE, 1101 crtc_state->saveDSPSIZE, 1102 crtc_state->saveDSPPOS, 1103 crtc_state->saveDSPBASE 1104 ); 1105 1106 1107 if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) { 1108 REG_WRITE(pipeA ? DPLL_A : DPLL_B, 1109 crtc_state->saveDPLL & ~DPLL_VCO_ENABLE); 1110 REG_READ(pipeA ? DPLL_A : DPLL_B); 1111 DRM_DEBUG("write dpll: %x\n", 1112 REG_READ(pipeA ? DPLL_A : DPLL_B)); 1113 udelay(150); 1114 } 1115 1116 REG_WRITE(pipeA ? FPA0 : FPB0, crtc_state->saveFP0); 1117 REG_READ(pipeA ? FPA0 : FPB0); 1118 1119 REG_WRITE(pipeA ? FPA1 : FPB1, crtc_state->saveFP1); 1120 REG_READ(pipeA ? FPA1 : FPB1); 1121 1122 REG_WRITE(pipeA ? DPLL_A : DPLL_B, crtc_state->saveDPLL); 1123 REG_READ(pipeA ? DPLL_A : DPLL_B); 1124 udelay(150); 1125 1126 REG_WRITE(pipeA ? HTOTAL_A : HTOTAL_B, crtc_state->saveHTOTAL); 1127 REG_WRITE(pipeA ? HBLANK_A : HBLANK_B, crtc_state->saveHBLANK); 1128 REG_WRITE(pipeA ? HSYNC_A : HSYNC_B, crtc_state->saveHSYNC); 1129 REG_WRITE(pipeA ? VTOTAL_A : VTOTAL_B, crtc_state->saveVTOTAL); 1130 REG_WRITE(pipeA ? VBLANK_A : VBLANK_B, crtc_state->saveVBLANK); 1131 REG_WRITE(pipeA ? VSYNC_A : VSYNC_B, crtc_state->saveVSYNC); 1132 REG_WRITE(pipeA ? DSPASTRIDE : DSPBSTRIDE, crtc_state->saveDSPSTRIDE); 1133 1134 REG_WRITE(pipeA ? DSPASIZE : DSPBSIZE, crtc_state->saveDSPSIZE); 1135 REG_WRITE(pipeA ? DSPAPOS : DSPBPOS, crtc_state->saveDSPPOS); 1136 1137 REG_WRITE(pipeA ? PIPEASRC : PIPEBSRC, crtc_state->savePIPESRC); 1138 REG_WRITE(pipeA ? DSPABASE : DSPBBASE, crtc_state->saveDSPBASE); 1139 REG_WRITE(pipeA ? PIPEACONF : PIPEBCONF, crtc_state->savePIPECONF); 1140 1141 cdv_intel_wait_for_vblank(dev); 1142 1143 REG_WRITE(pipeA ? DSPACNTR : DSPBCNTR, crtc_state->saveDSPCNTR); 1144 REG_WRITE(pipeA ? DSPABASE : DSPBBASE, crtc_state->saveDSPBASE); 1145 1146 cdv_intel_wait_for_vblank(dev); 1147 1148 paletteReg = pipeA ? PALETTE_A : PALETTE_B; 1149 for (i = 0; i < 256; ++i) 1150 REG_WRITE(paletteReg + (i << 2), crtc_state->savePalette[i]); 1151 } 1152 1153 static int cdv_intel_crtc_cursor_set(struct drm_crtc *crtc, 1154 struct drm_file *file_priv, 1155 uint32_t handle, 1156 uint32_t width, uint32_t height) 1157 { 1158 struct drm_device *dev = crtc->dev; 1159 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 1160 int pipe = psb_intel_crtc->pipe; 1161 uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR; 1162 uint32_t base = (pipe == 0) ? CURABASE : CURBBASE; 1163 uint32_t temp; 1164 size_t addr = 0; 1165 struct gtt_range *gt; 1166 struct drm_gem_object *obj; 1167 int ret; 1168 1169 /* if we want to turn of the cursor ignore width and height */ 1170 if (!handle) { 1171 /* turn off the cursor */ 1172 temp = CURSOR_MODE_DISABLE; 1173 1174 if (gma_power_begin(dev, false)) { 1175 REG_WRITE(control, temp); 1176 REG_WRITE(base, 0); 1177 gma_power_end(dev); 1178 } 1179 1180 /* unpin the old GEM object */ 1181 if (psb_intel_crtc->cursor_obj) { 1182 gt = container_of(psb_intel_crtc->cursor_obj, 1183 struct gtt_range, gem); 1184 psb_gtt_unpin(gt); 1185 drm_gem_object_unreference(psb_intel_crtc->cursor_obj); 1186 psb_intel_crtc->cursor_obj = NULL; 1187 } 1188 1189 return 0; 1190 } 1191 1192 /* Currently we only support 64x64 cursors */ 1193 if (width != 64 || height != 64) { 1194 dev_dbg(dev->dev, "we currently only support 64x64 cursors\n"); 1195 return -EINVAL; 1196 } 1197 1198 obj = drm_gem_object_lookup(dev, file_priv, handle); 1199 if (!obj) 1200 return -ENOENT; 1201 1202 if (obj->size < width * height * 4) { 1203 dev_dbg(dev->dev, "buffer is to small\n"); 1204 return -ENOMEM; 1205 } 1206 1207 gt = container_of(obj, struct gtt_range, gem); 1208 1209 /* Pin the memory into the GTT */ 1210 ret = psb_gtt_pin(gt); 1211 if (ret) { 1212 dev_err(dev->dev, "Can not pin down handle 0x%x\n", handle); 1213 return ret; 1214 } 1215 1216 addr = gt->offset; /* Or resource.start ??? */ 1217 1218 psb_intel_crtc->cursor_addr = addr; 1219 1220 temp = 0; 1221 /* set the pipe for the cursor */ 1222 temp |= (pipe << 28); 1223 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; 1224 1225 if (gma_power_begin(dev, false)) { 1226 REG_WRITE(control, temp); 1227 REG_WRITE(base, addr); 1228 gma_power_end(dev); 1229 } 1230 1231 /* unpin the old GEM object */ 1232 if (psb_intel_crtc->cursor_obj) { 1233 gt = container_of(psb_intel_crtc->cursor_obj, 1234 struct gtt_range, gem); 1235 psb_gtt_unpin(gt); 1236 drm_gem_object_unreference(psb_intel_crtc->cursor_obj); 1237 psb_intel_crtc->cursor_obj = obj; 1238 } 1239 return 0; 1240 } 1241 1242 static int cdv_intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) 1243 { 1244 struct drm_device *dev = crtc->dev; 1245 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 1246 int pipe = psb_intel_crtc->pipe; 1247 uint32_t temp = 0; 1248 uint32_t adder; 1249 1250 1251 if (x < 0) { 1252 temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT); 1253 x = -x; 1254 } 1255 if (y < 0) { 1256 temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT); 1257 y = -y; 1258 } 1259 1260 temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT); 1261 temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT); 1262 1263 adder = psb_intel_crtc->cursor_addr; 1264 1265 if (gma_power_begin(dev, false)) { 1266 REG_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp); 1267 REG_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder); 1268 gma_power_end(dev); 1269 } 1270 return 0; 1271 } 1272 1273 static void cdv_intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, 1274 u16 *green, u16 *blue, uint32_t start, uint32_t size) 1275 { 1276 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 1277 int i; 1278 int end = (start + size > 256) ? 256 : start + size; 1279 1280 for (i = start; i < end; i++) { 1281 psb_intel_crtc->lut_r[i] = red[i] >> 8; 1282 psb_intel_crtc->lut_g[i] = green[i] >> 8; 1283 psb_intel_crtc->lut_b[i] = blue[i] >> 8; 1284 } 1285 1286 cdv_intel_crtc_load_lut(crtc); 1287 } 1288 1289 static int cdv_crtc_set_config(struct drm_mode_set *set) 1290 { 1291 int ret = 0; 1292 struct drm_device *dev = set->crtc->dev; 1293 struct drm_psb_private *dev_priv = dev->dev_private; 1294 1295 if (!dev_priv->rpm_enabled) 1296 return drm_crtc_helper_set_config(set); 1297 1298 pm_runtime_forbid(&dev->pdev->dev); 1299 1300 ret = drm_crtc_helper_set_config(set); 1301 1302 pm_runtime_allow(&dev->pdev->dev); 1303 1304 return ret; 1305 } 1306 1307 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */ 1308 1309 /* FIXME: why are we using this, should it be cdv_ in this tree ? */ 1310 1311 static void i8xx_clock(int refclk, struct cdv_intel_clock_t *clock) 1312 { 1313 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); 1314 clock->p = clock->p1 * clock->p2; 1315 clock->vco = refclk * clock->m / (clock->n + 2); 1316 clock->dot = clock->vco / clock->p; 1317 } 1318 1319 /* Returns the clock of the currently programmed mode of the given pipe. */ 1320 static int cdv_intel_crtc_clock_get(struct drm_device *dev, 1321 struct drm_crtc *crtc) 1322 { 1323 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 1324 int pipe = psb_intel_crtc->pipe; 1325 u32 dpll; 1326 u32 fp; 1327 struct cdv_intel_clock_t clock; 1328 bool is_lvds; 1329 struct drm_psb_private *dev_priv = dev->dev_private; 1330 1331 if (gma_power_begin(dev, false)) { 1332 dpll = REG_READ((pipe == 0) ? DPLL_A : DPLL_B); 1333 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 1334 fp = REG_READ((pipe == 0) ? FPA0 : FPB0); 1335 else 1336 fp = REG_READ((pipe == 0) ? FPA1 : FPB1); 1337 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN); 1338 gma_power_end(dev); 1339 } else { 1340 dpll = (pipe == 0) ? 1341 dev_priv->saveDPLL_A : dev_priv->saveDPLL_B; 1342 1343 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 1344 fp = (pipe == 0) ? 1345 dev_priv->saveFPA0 : 1346 dev_priv->saveFPB0; 1347 else 1348 fp = (pipe == 0) ? 1349 dev_priv->saveFPA1 : 1350 dev_priv->saveFPB1; 1351 1352 is_lvds = (pipe == 1) && (dev_priv->saveLVDS & LVDS_PORT_EN); 1353 } 1354 1355 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 1356 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 1357 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 1358 1359 if (is_lvds) { 1360 clock.p1 = 1361 ffs((dpll & 1362 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> 1363 DPLL_FPA01_P1_POST_DIV_SHIFT); 1364 if (clock.p1 == 0) { 1365 clock.p1 = 4; 1366 dev_err(dev->dev, "PLL %d\n", dpll); 1367 } 1368 clock.p2 = 14; 1369 1370 if ((dpll & PLL_REF_INPUT_MASK) == 1371 PLLB_REF_INPUT_SPREADSPECTRUMIN) { 1372 /* XXX: might not be 66MHz */ 1373 i8xx_clock(66000, &clock); 1374 } else 1375 i8xx_clock(48000, &clock); 1376 } else { 1377 if (dpll & PLL_P1_DIVIDE_BY_TWO) 1378 clock.p1 = 2; 1379 else { 1380 clock.p1 = 1381 ((dpll & 1382 DPLL_FPA01_P1_POST_DIV_MASK_I830) >> 1383 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; 1384 } 1385 if (dpll & PLL_P2_DIVIDE_BY_4) 1386 clock.p2 = 4; 1387 else 1388 clock.p2 = 2; 1389 1390 i8xx_clock(48000, &clock); 1391 } 1392 1393 /* XXX: It would be nice to validate the clocks, but we can't reuse 1394 * i830PllIsValid() because it relies on the xf86_config connector 1395 * configuration being accurate, which it isn't necessarily. 1396 */ 1397 1398 return clock.dot; 1399 } 1400 1401 /** Returns the currently programmed mode of the given pipe. */ 1402 struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev, 1403 struct drm_crtc *crtc) 1404 { 1405 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 1406 int pipe = psb_intel_crtc->pipe; 1407 struct drm_display_mode *mode; 1408 int htot; 1409 int hsync; 1410 int vtot; 1411 int vsync; 1412 struct drm_psb_private *dev_priv = dev->dev_private; 1413 1414 if (gma_power_begin(dev, false)) { 1415 htot = REG_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B); 1416 hsync = REG_READ((pipe == 0) ? HSYNC_A : HSYNC_B); 1417 vtot = REG_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B); 1418 vsync = REG_READ((pipe == 0) ? VSYNC_A : VSYNC_B); 1419 gma_power_end(dev); 1420 } else { 1421 htot = (pipe == 0) ? 1422 dev_priv->saveHTOTAL_A : dev_priv->saveHTOTAL_B; 1423 hsync = (pipe == 0) ? 1424 dev_priv->saveHSYNC_A : dev_priv->saveHSYNC_B; 1425 vtot = (pipe == 0) ? 1426 dev_priv->saveVTOTAL_A : dev_priv->saveVTOTAL_B; 1427 vsync = (pipe == 0) ? 1428 dev_priv->saveVSYNC_A : dev_priv->saveVSYNC_B; 1429 } 1430 1431 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 1432 if (!mode) 1433 return NULL; 1434 1435 mode->clock = cdv_intel_crtc_clock_get(dev, crtc); 1436 mode->hdisplay = (htot & 0xffff) + 1; 1437 mode->htotal = ((htot & 0xffff0000) >> 16) + 1; 1438 mode->hsync_start = (hsync & 0xffff) + 1; 1439 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; 1440 mode->vdisplay = (vtot & 0xffff) + 1; 1441 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; 1442 mode->vsync_start = (vsync & 0xffff) + 1; 1443 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; 1444 1445 drm_mode_set_name(mode); 1446 drm_mode_set_crtcinfo(mode, 0); 1447 1448 return mode; 1449 } 1450 1451 static void cdv_intel_crtc_destroy(struct drm_crtc *crtc) 1452 { 1453 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 1454 1455 kfree(psb_intel_crtc->crtc_state); 1456 drm_crtc_cleanup(crtc); 1457 kfree(psb_intel_crtc); 1458 } 1459 1460 const struct drm_crtc_helper_funcs cdv_intel_helper_funcs = { 1461 .dpms = cdv_intel_crtc_dpms, 1462 .mode_fixup = cdv_intel_crtc_mode_fixup, 1463 .mode_set = cdv_intel_crtc_mode_set, 1464 .mode_set_base = cdv_intel_pipe_set_base, 1465 .prepare = cdv_intel_crtc_prepare, 1466 .commit = cdv_intel_crtc_commit, 1467 }; 1468 1469 const struct drm_crtc_funcs cdv_intel_crtc_funcs = { 1470 .save = cdv_intel_crtc_save, 1471 .restore = cdv_intel_crtc_restore, 1472 .cursor_set = cdv_intel_crtc_cursor_set, 1473 .cursor_move = cdv_intel_crtc_cursor_move, 1474 .gamma_set = cdv_intel_crtc_gamma_set, 1475 .set_config = cdv_crtc_set_config, 1476 .destroy = cdv_intel_crtc_destroy, 1477 }; 1478 1479 /* 1480 * Set the default value of cursor control and base register 1481 * to zero. This is a workaround for h/w defect on oaktrail 1482 */ 1483 void cdv_intel_cursor_init(struct drm_device *dev, int pipe) 1484 { 1485 uint32_t control; 1486 uint32_t base; 1487 1488 switch (pipe) { 1489 case 0: 1490 control = CURACNTR; 1491 base = CURABASE; 1492 break; 1493 case 1: 1494 control = CURBCNTR; 1495 base = CURBBASE; 1496 break; 1497 case 2: 1498 control = CURCCNTR; 1499 base = CURCBASE; 1500 break; 1501 default: 1502 return; 1503 } 1504 1505 REG_WRITE(control, 0); 1506 REG_WRITE(base, 0); 1507 } 1508 1509