1 /************************************************************************** 2 * Copyright (c) 2011, Intel Corporation. 3 * All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 17 * 18 **************************************************************************/ 19 20 #include <linux/backlight.h> 21 #include <drm/drmP.h> 22 #include <drm/drm.h> 23 #include <drm/gma_drm.h> 24 #include "psb_drv.h" 25 #include "psb_reg.h" 26 #include "psb_intel_reg.h" 27 #include "intel_bios.h" 28 #include "cdv_device.h" 29 #include "gma_device.h" 30 31 #define VGA_SR_INDEX 0x3c4 32 #define VGA_SR_DATA 0x3c5 33 34 static void cdv_disable_vga(struct drm_device *dev) 35 { 36 u8 sr1; 37 u32 vga_reg; 38 39 vga_reg = VGACNTRL; 40 41 outb(1, VGA_SR_INDEX); 42 sr1 = inb(VGA_SR_DATA); 43 outb(sr1 | 1<<5, VGA_SR_DATA); 44 udelay(300); 45 46 REG_WRITE(vga_reg, VGA_DISP_DISABLE); 47 REG_READ(vga_reg); 48 } 49 50 static int cdv_output_init(struct drm_device *dev) 51 { 52 struct drm_psb_private *dev_priv = dev->dev_private; 53 54 drm_mode_create_scaling_mode_property(dev); 55 56 cdv_disable_vga(dev); 57 58 cdv_intel_crt_init(dev, &dev_priv->mode_dev); 59 cdv_intel_lvds_init(dev, &dev_priv->mode_dev); 60 61 /* These bits indicate HDMI not SDVO on CDV */ 62 if (REG_READ(SDVOB) & SDVO_DETECTED) { 63 cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOB); 64 if (REG_READ(DP_B) & DP_DETECTED) 65 cdv_intel_dp_init(dev, &dev_priv->mode_dev, DP_B); 66 } 67 68 if (REG_READ(SDVOC) & SDVO_DETECTED) { 69 cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOC); 70 if (REG_READ(DP_C) & DP_DETECTED) 71 cdv_intel_dp_init(dev, &dev_priv->mode_dev, DP_C); 72 } 73 return 0; 74 } 75 76 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE 77 78 /* 79 * Cedartrail Backlght Interfaces 80 */ 81 82 static struct backlight_device *cdv_backlight_device; 83 84 static int cdv_backlight_combination_mode(struct drm_device *dev) 85 { 86 return REG_READ(BLC_PWM_CTL2) & PWM_LEGACY_MODE; 87 } 88 89 static u32 cdv_get_max_backlight(struct drm_device *dev) 90 { 91 u32 max = REG_READ(BLC_PWM_CTL); 92 93 if (max == 0) { 94 DRM_DEBUG_KMS("LVDS Panel PWM value is 0!\n"); 95 /* i915 does this, I believe which means that we should not 96 * smash PWM control as firmware will take control of it. */ 97 return 1; 98 } 99 100 max >>= 16; 101 if (cdv_backlight_combination_mode(dev)) 102 max *= 0xff; 103 return max; 104 } 105 106 static int cdv_get_brightness(struct backlight_device *bd) 107 { 108 struct drm_device *dev = bl_get_data(bd); 109 u32 val = REG_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; 110 111 if (cdv_backlight_combination_mode(dev)) { 112 u8 lbpc; 113 114 val &= ~1; 115 pci_read_config_byte(dev->pdev, 0xF4, &lbpc); 116 val *= lbpc; 117 } 118 return (val * 100)/cdv_get_max_backlight(dev); 119 120 } 121 122 static int cdv_set_brightness(struct backlight_device *bd) 123 { 124 struct drm_device *dev = bl_get_data(bd); 125 int level = bd->props.brightness; 126 u32 blc_pwm_ctl; 127 128 /* Percentage 1-100% being valid */ 129 if (level < 1) 130 level = 1; 131 132 level *= cdv_get_max_backlight(dev); 133 level /= 100; 134 135 if (cdv_backlight_combination_mode(dev)) { 136 u32 max = cdv_get_max_backlight(dev); 137 u8 lbpc; 138 139 lbpc = level * 0xfe / max + 1; 140 level /= lbpc; 141 142 pci_write_config_byte(dev->pdev, 0xF4, lbpc); 143 } 144 145 blc_pwm_ctl = REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; 146 REG_WRITE(BLC_PWM_CTL, (blc_pwm_ctl | 147 (level << BACKLIGHT_DUTY_CYCLE_SHIFT))); 148 return 0; 149 } 150 151 static const struct backlight_ops cdv_ops = { 152 .get_brightness = cdv_get_brightness, 153 .update_status = cdv_set_brightness, 154 }; 155 156 static int cdv_backlight_init(struct drm_device *dev) 157 { 158 struct drm_psb_private *dev_priv = dev->dev_private; 159 struct backlight_properties props; 160 161 memset(&props, 0, sizeof(struct backlight_properties)); 162 props.max_brightness = 100; 163 props.type = BACKLIGHT_PLATFORM; 164 165 cdv_backlight_device = backlight_device_register("psb-bl", 166 NULL, (void *)dev, &cdv_ops, &props); 167 if (IS_ERR(cdv_backlight_device)) 168 return PTR_ERR(cdv_backlight_device); 169 170 cdv_backlight_device->props.brightness = 171 cdv_get_brightness(cdv_backlight_device); 172 backlight_update_status(cdv_backlight_device); 173 dev_priv->backlight_device = cdv_backlight_device; 174 dev_priv->backlight_enabled = true; 175 return 0; 176 } 177 178 #endif 179 180 /* 181 * Provide the Cedarview specific chip logic and low level methods 182 * for power management 183 * 184 * FIXME: we need to implement the apm/ospm base management bits 185 * for this and the MID devices. 186 */ 187 188 static inline u32 CDV_MSG_READ32(uint port, uint offset) 189 { 190 int mcr = (0x10<<24) | (port << 16) | (offset << 8); 191 uint32_t ret_val = 0; 192 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0); 193 pci_write_config_dword(pci_root, 0xD0, mcr); 194 pci_read_config_dword(pci_root, 0xD4, &ret_val); 195 pci_dev_put(pci_root); 196 return ret_val; 197 } 198 199 static inline void CDV_MSG_WRITE32(uint port, uint offset, u32 value) 200 { 201 int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0; 202 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0); 203 pci_write_config_dword(pci_root, 0xD4, value); 204 pci_write_config_dword(pci_root, 0xD0, mcr); 205 pci_dev_put(pci_root); 206 } 207 208 #define PSB_PM_SSC 0x20 209 #define PSB_PM_SSS 0x30 210 #define PSB_PWRGT_GFX_ON 0x02 211 #define PSB_PWRGT_GFX_OFF 0x01 212 #define PSB_PWRGT_GFX_D0 0x00 213 #define PSB_PWRGT_GFX_D3 0x03 214 215 static void cdv_init_pm(struct drm_device *dev) 216 { 217 struct drm_psb_private *dev_priv = dev->dev_private; 218 u32 pwr_cnt; 219 int i; 220 221 dev_priv->apm_base = CDV_MSG_READ32(PSB_PUNIT_PORT, 222 PSB_APMBA) & 0xFFFF; 223 dev_priv->ospm_base = CDV_MSG_READ32(PSB_PUNIT_PORT, 224 PSB_OSPMBA) & 0xFFFF; 225 226 /* Power status */ 227 pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD); 228 229 /* Enable the GPU */ 230 pwr_cnt &= ~PSB_PWRGT_GFX_MASK; 231 pwr_cnt |= PSB_PWRGT_GFX_ON; 232 outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD); 233 234 /* Wait for the GPU power */ 235 for (i = 0; i < 5; i++) { 236 u32 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS); 237 if ((pwr_sts & PSB_PWRGT_GFX_MASK) == 0) 238 return; 239 udelay(10); 240 } 241 dev_err(dev->dev, "GPU: power management timed out.\n"); 242 } 243 244 static void cdv_errata(struct drm_device *dev) 245 { 246 /* Disable bonus launch. 247 * CPU and GPU competes for memory and display misses updates and 248 * flickers. Worst with dual core, dual displays. 249 * 250 * Fixes were done to Win 7 gfx driver to disable a feature called 251 * Bonus Launch to work around the issue, by degrading 252 * performance. 253 */ 254 CDV_MSG_WRITE32(3, 0x30, 0x08027108); 255 } 256 257 /** 258 * cdv_save_display_registers - save registers lost on suspend 259 * @dev: our DRM device 260 * 261 * Save the state we need in order to be able to restore the interface 262 * upon resume from suspend 263 */ 264 static int cdv_save_display_registers(struct drm_device *dev) 265 { 266 struct drm_psb_private *dev_priv = dev->dev_private; 267 struct psb_save_area *regs = &dev_priv->regs; 268 struct drm_connector *connector; 269 270 dev_dbg(dev->dev, "Saving GPU registers.\n"); 271 272 pci_read_config_byte(dev->pdev, 0xF4, ®s->cdv.saveLBB); 273 274 regs->cdv.saveDSPCLK_GATE_D = REG_READ(DSPCLK_GATE_D); 275 regs->cdv.saveRAMCLK_GATE_D = REG_READ(RAMCLK_GATE_D); 276 277 regs->cdv.saveDSPARB = REG_READ(DSPARB); 278 regs->cdv.saveDSPFW[0] = REG_READ(DSPFW1); 279 regs->cdv.saveDSPFW[1] = REG_READ(DSPFW2); 280 regs->cdv.saveDSPFW[2] = REG_READ(DSPFW3); 281 regs->cdv.saveDSPFW[3] = REG_READ(DSPFW4); 282 regs->cdv.saveDSPFW[4] = REG_READ(DSPFW5); 283 regs->cdv.saveDSPFW[5] = REG_READ(DSPFW6); 284 285 regs->cdv.saveADPA = REG_READ(ADPA); 286 287 regs->cdv.savePP_CONTROL = REG_READ(PP_CONTROL); 288 regs->cdv.savePFIT_PGM_RATIOS = REG_READ(PFIT_PGM_RATIOS); 289 regs->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL); 290 regs->saveBLC_PWM_CTL2 = REG_READ(BLC_PWM_CTL2); 291 regs->cdv.saveLVDS = REG_READ(LVDS); 292 293 regs->cdv.savePFIT_CONTROL = REG_READ(PFIT_CONTROL); 294 295 regs->cdv.savePP_ON_DELAYS = REG_READ(PP_ON_DELAYS); 296 regs->cdv.savePP_OFF_DELAYS = REG_READ(PP_OFF_DELAYS); 297 regs->cdv.savePP_CYCLE = REG_READ(PP_CYCLE); 298 299 regs->cdv.saveVGACNTRL = REG_READ(VGACNTRL); 300 301 regs->cdv.saveIER = REG_READ(PSB_INT_ENABLE_R); 302 regs->cdv.saveIMR = REG_READ(PSB_INT_MASK_R); 303 304 list_for_each_entry(connector, &dev->mode_config.connector_list, head) 305 connector->funcs->dpms(connector, DRM_MODE_DPMS_OFF); 306 307 return 0; 308 } 309 310 /** 311 * cdv_restore_display_registers - restore lost register state 312 * @dev: our DRM device 313 * 314 * Restore register state that was lost during suspend and resume. 315 * 316 * FIXME: review 317 */ 318 static int cdv_restore_display_registers(struct drm_device *dev) 319 { 320 struct drm_psb_private *dev_priv = dev->dev_private; 321 struct psb_save_area *regs = &dev_priv->regs; 322 struct drm_connector *connector; 323 u32 temp; 324 325 pci_write_config_byte(dev->pdev, 0xF4, regs->cdv.saveLBB); 326 327 REG_WRITE(DSPCLK_GATE_D, regs->cdv.saveDSPCLK_GATE_D); 328 REG_WRITE(RAMCLK_GATE_D, regs->cdv.saveRAMCLK_GATE_D); 329 330 /* BIOS does below anyway */ 331 REG_WRITE(DPIO_CFG, 0); 332 REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N); 333 334 temp = REG_READ(DPLL_A); 335 if ((temp & DPLL_SYNCLOCK_ENABLE) == 0) { 336 REG_WRITE(DPLL_A, temp | DPLL_SYNCLOCK_ENABLE); 337 REG_READ(DPLL_A); 338 } 339 340 temp = REG_READ(DPLL_B); 341 if ((temp & DPLL_SYNCLOCK_ENABLE) == 0) { 342 REG_WRITE(DPLL_B, temp | DPLL_SYNCLOCK_ENABLE); 343 REG_READ(DPLL_B); 344 } 345 346 udelay(500); 347 348 REG_WRITE(DSPFW1, regs->cdv.saveDSPFW[0]); 349 REG_WRITE(DSPFW2, regs->cdv.saveDSPFW[1]); 350 REG_WRITE(DSPFW3, regs->cdv.saveDSPFW[2]); 351 REG_WRITE(DSPFW4, regs->cdv.saveDSPFW[3]); 352 REG_WRITE(DSPFW5, regs->cdv.saveDSPFW[4]); 353 REG_WRITE(DSPFW6, regs->cdv.saveDSPFW[5]); 354 355 REG_WRITE(DSPARB, regs->cdv.saveDSPARB); 356 REG_WRITE(ADPA, regs->cdv.saveADPA); 357 358 REG_WRITE(BLC_PWM_CTL2, regs->saveBLC_PWM_CTL2); 359 REG_WRITE(LVDS, regs->cdv.saveLVDS); 360 REG_WRITE(PFIT_CONTROL, regs->cdv.savePFIT_CONTROL); 361 REG_WRITE(PFIT_PGM_RATIOS, regs->cdv.savePFIT_PGM_RATIOS); 362 REG_WRITE(BLC_PWM_CTL, regs->saveBLC_PWM_CTL); 363 REG_WRITE(PP_ON_DELAYS, regs->cdv.savePP_ON_DELAYS); 364 REG_WRITE(PP_OFF_DELAYS, regs->cdv.savePP_OFF_DELAYS); 365 REG_WRITE(PP_CYCLE, regs->cdv.savePP_CYCLE); 366 REG_WRITE(PP_CONTROL, regs->cdv.savePP_CONTROL); 367 368 REG_WRITE(VGACNTRL, regs->cdv.saveVGACNTRL); 369 370 REG_WRITE(PSB_INT_ENABLE_R, regs->cdv.saveIER); 371 REG_WRITE(PSB_INT_MASK_R, regs->cdv.saveIMR); 372 373 /* Fix arbitration bug */ 374 cdv_errata(dev); 375 376 drm_mode_config_reset(dev); 377 378 list_for_each_entry(connector, &dev->mode_config.connector_list, head) 379 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); 380 381 /* Resume the modeset for every activated CRTC */ 382 drm_helper_resume_force_mode(dev); 383 return 0; 384 } 385 386 static int cdv_power_down(struct drm_device *dev) 387 { 388 struct drm_psb_private *dev_priv = dev->dev_private; 389 u32 pwr_cnt, pwr_mask, pwr_sts; 390 int tries = 5; 391 392 pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD); 393 pwr_cnt &= ~PSB_PWRGT_GFX_MASK; 394 pwr_cnt |= PSB_PWRGT_GFX_OFF; 395 pwr_mask = PSB_PWRGT_GFX_MASK; 396 397 outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD); 398 399 while (tries--) { 400 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS); 401 if ((pwr_sts & pwr_mask) == PSB_PWRGT_GFX_D3) 402 return 0; 403 udelay(10); 404 } 405 return 0; 406 } 407 408 static int cdv_power_up(struct drm_device *dev) 409 { 410 struct drm_psb_private *dev_priv = dev->dev_private; 411 u32 pwr_cnt, pwr_mask, pwr_sts; 412 int tries = 5; 413 414 pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD); 415 pwr_cnt &= ~PSB_PWRGT_GFX_MASK; 416 pwr_cnt |= PSB_PWRGT_GFX_ON; 417 pwr_mask = PSB_PWRGT_GFX_MASK; 418 419 outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD); 420 421 while (tries--) { 422 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS); 423 if ((pwr_sts & pwr_mask) == PSB_PWRGT_GFX_D0) 424 return 0; 425 udelay(10); 426 } 427 return 0; 428 } 429 430 static void cdv_hotplug_work_func(struct work_struct *work) 431 { 432 struct drm_psb_private *dev_priv = container_of(work, struct drm_psb_private, 433 hotplug_work); 434 struct drm_device *dev = dev_priv->dev; 435 436 /* Just fire off a uevent and let userspace tell us what to do */ 437 drm_helper_hpd_irq_event(dev); 438 } 439 440 /* The core driver has received a hotplug IRQ. We are in IRQ context 441 so extract the needed information and kick off queued processing */ 442 443 static int cdv_hotplug_event(struct drm_device *dev) 444 { 445 struct drm_psb_private *dev_priv = dev->dev_private; 446 schedule_work(&dev_priv->hotplug_work); 447 REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT)); 448 return 1; 449 } 450 451 static void cdv_hotplug_enable(struct drm_device *dev, bool on) 452 { 453 if (on) { 454 u32 hotplug = REG_READ(PORT_HOTPLUG_EN); 455 hotplug |= HDMIB_HOTPLUG_INT_EN | HDMIC_HOTPLUG_INT_EN | 456 HDMID_HOTPLUG_INT_EN | CRT_HOTPLUG_INT_EN; 457 REG_WRITE(PORT_HOTPLUG_EN, hotplug); 458 } else { 459 REG_WRITE(PORT_HOTPLUG_EN, 0); 460 REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT)); 461 } 462 } 463 464 static const char *force_audio_names[] = { 465 "off", 466 "auto", 467 "on", 468 }; 469 470 void cdv_intel_attach_force_audio_property(struct drm_connector *connector) 471 { 472 struct drm_device *dev = connector->dev; 473 struct drm_psb_private *dev_priv = dev->dev_private; 474 struct drm_property *prop; 475 int i; 476 477 prop = dev_priv->force_audio_property; 478 if (prop == NULL) { 479 prop = drm_property_create(dev, DRM_MODE_PROP_ENUM, 480 "audio", 481 ARRAY_SIZE(force_audio_names)); 482 if (prop == NULL) 483 return; 484 485 for (i = 0; i < ARRAY_SIZE(force_audio_names); i++) 486 drm_property_add_enum(prop, i, i-1, force_audio_names[i]); 487 488 dev_priv->force_audio_property = prop; 489 } 490 drm_object_attach_property(&connector->base, prop, 0); 491 } 492 493 494 static const char *broadcast_rgb_names[] = { 495 "Full", 496 "Limited 16:235", 497 }; 498 499 void cdv_intel_attach_broadcast_rgb_property(struct drm_connector *connector) 500 { 501 struct drm_device *dev = connector->dev; 502 struct drm_psb_private *dev_priv = dev->dev_private; 503 struct drm_property *prop; 504 int i; 505 506 prop = dev_priv->broadcast_rgb_property; 507 if (prop == NULL) { 508 prop = drm_property_create(dev, DRM_MODE_PROP_ENUM, 509 "Broadcast RGB", 510 ARRAY_SIZE(broadcast_rgb_names)); 511 if (prop == NULL) 512 return; 513 514 for (i = 0; i < ARRAY_SIZE(broadcast_rgb_names); i++) 515 drm_property_add_enum(prop, i, i, broadcast_rgb_names[i]); 516 517 dev_priv->broadcast_rgb_property = prop; 518 } 519 520 drm_object_attach_property(&connector->base, prop, 0); 521 } 522 523 /* Cedarview */ 524 static const struct psb_offset cdv_regmap[2] = { 525 { 526 .fp0 = FPA0, 527 .fp1 = FPA1, 528 .cntr = DSPACNTR, 529 .conf = PIPEACONF, 530 .src = PIPEASRC, 531 .dpll = DPLL_A, 532 .dpll_md = DPLL_A_MD, 533 .htotal = HTOTAL_A, 534 .hblank = HBLANK_A, 535 .hsync = HSYNC_A, 536 .vtotal = VTOTAL_A, 537 .vblank = VBLANK_A, 538 .vsync = VSYNC_A, 539 .stride = DSPASTRIDE, 540 .size = DSPASIZE, 541 .pos = DSPAPOS, 542 .base = DSPABASE, 543 .surf = DSPASURF, 544 .addr = DSPABASE, 545 .status = PIPEASTAT, 546 .linoff = DSPALINOFF, 547 .tileoff = DSPATILEOFF, 548 .palette = PALETTE_A, 549 }, 550 { 551 .fp0 = FPB0, 552 .fp1 = FPB1, 553 .cntr = DSPBCNTR, 554 .conf = PIPEBCONF, 555 .src = PIPEBSRC, 556 .dpll = DPLL_B, 557 .dpll_md = DPLL_B_MD, 558 .htotal = HTOTAL_B, 559 .hblank = HBLANK_B, 560 .hsync = HSYNC_B, 561 .vtotal = VTOTAL_B, 562 .vblank = VBLANK_B, 563 .vsync = VSYNC_B, 564 .stride = DSPBSTRIDE, 565 .size = DSPBSIZE, 566 .pos = DSPBPOS, 567 .base = DSPBBASE, 568 .surf = DSPBSURF, 569 .addr = DSPBBASE, 570 .status = PIPEBSTAT, 571 .linoff = DSPBLINOFF, 572 .tileoff = DSPBTILEOFF, 573 .palette = PALETTE_B, 574 } 575 }; 576 577 static int cdv_chip_setup(struct drm_device *dev) 578 { 579 struct drm_psb_private *dev_priv = dev->dev_private; 580 INIT_WORK(&dev_priv->hotplug_work, cdv_hotplug_work_func); 581 582 if (pci_enable_msi(dev->pdev)) 583 dev_warn(dev->dev, "Enabling MSI failed!\n"); 584 dev_priv->regmap = cdv_regmap; 585 gma_get_core_freq(dev); 586 psb_intel_opregion_init(dev); 587 psb_intel_init_bios(dev); 588 cdv_hotplug_enable(dev, false); 589 return 0; 590 } 591 592 /* CDV is much like Poulsbo but has MID like SGX offsets and PM */ 593 594 const struct psb_ops cdv_chip_ops = { 595 .name = "GMA3600/3650", 596 .accel_2d = 0, 597 .pipes = 2, 598 .crtcs = 2, 599 .hdmi_mask = (1 << 0) | (1 << 1), 600 .lvds_mask = (1 << 1), 601 .sdvo_mask = (1 << 0), 602 .cursor_needs_phys = 0, 603 .sgx_offset = MRST_SGX_OFFSET, 604 .chip_setup = cdv_chip_setup, 605 .errata = cdv_errata, 606 607 .crtc_helper = &cdv_intel_helper_funcs, 608 .crtc_funcs = &cdv_intel_crtc_funcs, 609 .clock_funcs = &cdv_clock_funcs, 610 611 .output_init = cdv_output_init, 612 .hotplug = cdv_hotplug_event, 613 .hotplug_enable = cdv_hotplug_enable, 614 615 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE 616 .backlight_init = cdv_backlight_init, 617 #endif 618 619 .init_pm = cdv_init_pm, 620 .save_regs = cdv_save_display_registers, 621 .restore_regs = cdv_restore_display_registers, 622 .power_down = cdv_power_down, 623 .power_up = cdv_power_up, 624 .update_wm = cdv_update_wm, 625 .disable_sr = cdv_disable_sr, 626 }; 627