1 /* 2 * Copyright 2015 Freescale Semiconductor, Inc. 3 * 4 * Freescale DCU drm device driver 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #ifndef __FSL_DCU_DRM_DRV_H__ 13 #define __FSL_DCU_DRM_DRV_H__ 14 15 #include <drm/drm_encoder.h> 16 17 #include "fsl_dcu_drm_crtc.h" 18 #include "fsl_dcu_drm_output.h" 19 #include "fsl_dcu_drm_plane.h" 20 21 #define DCU_DCU_MODE 0x0010 22 #define DCU_MODE_BLEND_ITER(x) ((x) << 20) 23 #define DCU_MODE_RASTER_EN BIT(14) 24 #define DCU_MODE_DCU_MODE(x) (x) 25 #define DCU_MODE_DCU_MODE_MASK 0x03 26 #define DCU_MODE_OFF 0 27 #define DCU_MODE_NORMAL 1 28 #define DCU_MODE_TEST 2 29 #define DCU_MODE_COLORBAR 3 30 31 #define DCU_BGND 0x0014 32 #define DCU_BGND_R(x) ((x) << 16) 33 #define DCU_BGND_G(x) ((x) << 8) 34 #define DCU_BGND_B(x) (x) 35 36 #define DCU_DISP_SIZE 0x0018 37 #define DCU_DISP_SIZE_DELTA_Y(x) ((x) << 16) 38 /*Regisiter value 1/16 of horizontal resolution*/ 39 #define DCU_DISP_SIZE_DELTA_X(x) ((x) >> 4) 40 41 #define DCU_HSYN_PARA 0x001c 42 #define DCU_HSYN_PARA_BP(x) ((x) << 22) 43 #define DCU_HSYN_PARA_PW(x) ((x) << 11) 44 #define DCU_HSYN_PARA_FP(x) (x) 45 46 #define DCU_VSYN_PARA 0x0020 47 #define DCU_VSYN_PARA_BP(x) ((x) << 22) 48 #define DCU_VSYN_PARA_PW(x) ((x) << 11) 49 #define DCU_VSYN_PARA_FP(x) (x) 50 51 #define DCU_SYN_POL 0x0024 52 #define DCU_SYN_POL_INV_PXCK BIT(6) 53 #define DCU_SYN_POL_NEG BIT(5) 54 #define DCU_SYN_POL_INV_VS_LOW BIT(1) 55 #define DCU_SYN_POL_INV_HS_LOW BIT(0) 56 57 #define DCU_THRESHOLD 0x0028 58 #define DCU_THRESHOLD_LS_BF_VS(x) ((x) << 16) 59 #define DCU_THRESHOLD_OUT_BUF_HIGH(x) ((x) << 8) 60 #define DCU_THRESHOLD_OUT_BUF_LOW(x) (x) 61 #define BF_VS_VAL 0x03 62 #define BUF_MAX_VAL 0x78 63 #define BUF_MIN_VAL 0x0a 64 65 #define DCU_INT_STATUS 0x002C 66 #define DCU_INT_STATUS_VSYNC BIT(0) 67 #define DCU_INT_STATUS_UNDRUN BIT(1) 68 #define DCU_INT_STATUS_LSBFVS BIT(2) 69 #define DCU_INT_STATUS_VBLANK BIT(3) 70 #define DCU_INT_STATUS_CRCREADY BIT(4) 71 #define DCU_INT_STATUS_CRCOVERFLOW BIT(5) 72 #define DCU_INT_STATUS_P1FIFOLO BIT(6) 73 #define DCU_INT_STATUS_P1FIFOHI BIT(7) 74 #define DCU_INT_STATUS_P2FIFOLO BIT(8) 75 #define DCU_INT_STATUS_P2FIFOHI BIT(9) 76 #define DCU_INT_STATUS_PROGEND BIT(10) 77 #define DCU_INT_STATUS_IPMERROR BIT(11) 78 #define DCU_INT_STATUS_LYRTRANS BIT(12) 79 #define DCU_INT_STATUS_DMATRANS BIT(14) 80 #define DCU_INT_STATUS_P3FIFOLO BIT(16) 81 #define DCU_INT_STATUS_P3FIFOHI BIT(17) 82 #define DCU_INT_STATUS_P4FIFOLO BIT(18) 83 #define DCU_INT_STATUS_P4FIFOHI BIT(19) 84 #define DCU_INT_STATUS_P1EMPTY BIT(26) 85 #define DCU_INT_STATUS_P2EMPTY BIT(27) 86 #define DCU_INT_STATUS_P3EMPTY BIT(28) 87 #define DCU_INT_STATUS_P4EMPTY BIT(29) 88 89 #define DCU_INT_MASK 0x0030 90 #define DCU_INT_MASK_VSYNC BIT(0) 91 #define DCU_INT_MASK_UNDRUN BIT(1) 92 #define DCU_INT_MASK_LSBFVS BIT(2) 93 #define DCU_INT_MASK_VBLANK BIT(3) 94 #define DCU_INT_MASK_CRCREADY BIT(4) 95 #define DCU_INT_MASK_CRCOVERFLOW BIT(5) 96 #define DCU_INT_MASK_P1FIFOLO BIT(6) 97 #define DCU_INT_MASK_P1FIFOHI BIT(7) 98 #define DCU_INT_MASK_P2FIFOLO BIT(8) 99 #define DCU_INT_MASK_P2FIFOHI BIT(9) 100 #define DCU_INT_MASK_PROGEND BIT(10) 101 #define DCU_INT_MASK_IPMERROR BIT(11) 102 #define DCU_INT_MASK_LYRTRANS BIT(12) 103 #define DCU_INT_MASK_DMATRANS BIT(14) 104 #define DCU_INT_MASK_P3FIFOLO BIT(16) 105 #define DCU_INT_MASK_P3FIFOHI BIT(17) 106 #define DCU_INT_MASK_P4FIFOLO BIT(18) 107 #define DCU_INT_MASK_P4FIFOHI BIT(19) 108 #define DCU_INT_MASK_P1EMPTY BIT(26) 109 #define DCU_INT_MASK_P2EMPTY BIT(27) 110 #define DCU_INT_MASK_P3EMPTY BIT(28) 111 #define DCU_INT_MASK_P4EMPTY BIT(29) 112 113 #define DCU_DIV_RATIO 0x0054 114 115 #define DCU_UPDATE_MODE 0x00cc 116 #define DCU_UPDATE_MODE_MODE BIT(31) 117 #define DCU_UPDATE_MODE_READREG BIT(30) 118 119 #define DCU_DCFB_MAX 0x300 120 121 #define DCU_CTRLDESCLN(layer, reg) (0x200 + (reg - 1) * 4 + (layer) * 0x40) 122 123 #define DCU_LAYER_HEIGHT(x) ((x) << 16) 124 #define DCU_LAYER_WIDTH(x) (x) 125 126 #define DCU_LAYER_POSY(x) ((x) << 16) 127 #define DCU_LAYER_POSX(x) (x) 128 129 #define DCU_LAYER_EN BIT(31) 130 #define DCU_LAYER_TILE_EN BIT(30) 131 #define DCU_LAYER_DATA_SEL_CLUT BIT(29) 132 #define DCU_LAYER_SAFETY_EN BIT(28) 133 #define DCU_LAYER_TRANS(x) ((x) << 20) 134 #define DCU_LAYER_BPP(x) ((x) << 16) 135 #define DCU_LAYER_RLE_EN BIT(15) 136 #define DCU_LAYER_LUOFFS(x) ((x) << 4) 137 #define DCU_LAYER_BB_ON BIT(2) 138 #define DCU_LAYER_AB_NONE 0 139 #define DCU_LAYER_AB_CHROMA_KEYING 1 140 #define DCU_LAYER_AB_WHOLE_FRAME 2 141 142 #define DCU_LAYER_CKMAX_R(x) ((x) << 16) 143 #define DCU_LAYER_CKMAX_G(x) ((x) << 8) 144 #define DCU_LAYER_CKMAX_B(x) (x) 145 146 #define DCU_LAYER_CKMIN_R(x) ((x) << 16) 147 #define DCU_LAYER_CKMIN_G(x) ((x) << 8) 148 #define DCU_LAYER_CKMIN_B(x) (x) 149 150 #define DCU_LAYER_TILE_VER(x) ((x) << 16) 151 #define DCU_LAYER_TILE_HOR(x) (x) 152 153 #define DCU_LAYER_FG_FCOLOR(x) (x) 154 155 #define DCU_LAYER_BG_BCOLOR(x) (x) 156 157 #define DCU_LAYER_POST_SKIP(x) ((x) << 16) 158 #define DCU_LAYER_PRE_SKIP(x) (x) 159 160 #define FSL_DCU_RGB565 4 161 #define FSL_DCU_RGB888 5 162 #define FSL_DCU_ARGB8888 6 163 #define FSL_DCU_ARGB1555 11 164 #define FSL_DCU_ARGB4444 12 165 #define FSL_DCU_YUV422 14 166 167 #define VF610_LAYER_REG_NUM 9 168 #define LS1021A_LAYER_REG_NUM 10 169 170 struct clk; 171 struct device; 172 struct drm_device; 173 174 struct fsl_dcu_soc_data { 175 const char *name; 176 /*total layer number*/ 177 unsigned int total_layer; 178 /*max layer number DCU supported*/ 179 unsigned int max_layer; 180 unsigned int layer_regs; 181 }; 182 183 struct fsl_dcu_drm_device { 184 struct device *dev; 185 struct device_node *np; 186 struct regmap *regmap; 187 int irq; 188 struct clk *clk; 189 struct clk *pix_clk; 190 struct fsl_tcon *tcon; 191 /*protects hardware register*/ 192 spinlock_t irq_lock; 193 struct drm_device *drm; 194 struct drm_fbdev_cma *fbdev; 195 struct drm_crtc crtc; 196 struct drm_encoder encoder; 197 struct fsl_dcu_drm_connector connector; 198 const struct fsl_dcu_soc_data *soc; 199 struct drm_atomic_state *state; 200 }; 201 202 int fsl_dcu_drm_modeset_init(struct fsl_dcu_drm_device *fsl_dev); 203 204 #endif /* __FSL_DCU_DRM_DRV_H__ */ 205