1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright 2015 Freescale Semiconductor, Inc. 4 * 5 * Freescale DCU drm device driver 6 */ 7 8 #ifndef __FSL_DCU_DRM_DRV_H__ 9 #define __FSL_DCU_DRM_DRV_H__ 10 11 #include <drm/drm_encoder.h> 12 13 #include "fsl_dcu_drm_crtc.h" 14 #include "fsl_dcu_drm_output.h" 15 #include "fsl_dcu_drm_plane.h" 16 17 #define DCU_DCU_MODE 0x0010 18 #define DCU_MODE_BLEND_ITER(x) ((x) << 20) 19 #define DCU_MODE_RASTER_EN BIT(14) 20 #define DCU_MODE_DCU_MODE(x) (x) 21 #define DCU_MODE_DCU_MODE_MASK 0x03 22 #define DCU_MODE_OFF 0 23 #define DCU_MODE_NORMAL 1 24 #define DCU_MODE_TEST 2 25 #define DCU_MODE_COLORBAR 3 26 27 #define DCU_BGND 0x0014 28 #define DCU_BGND_R(x) ((x) << 16) 29 #define DCU_BGND_G(x) ((x) << 8) 30 #define DCU_BGND_B(x) (x) 31 32 #define DCU_DISP_SIZE 0x0018 33 #define DCU_DISP_SIZE_DELTA_Y(x) ((x) << 16) 34 /*Regisiter value 1/16 of horizontal resolution*/ 35 #define DCU_DISP_SIZE_DELTA_X(x) ((x) >> 4) 36 37 #define DCU_HSYN_PARA 0x001c 38 #define DCU_HSYN_PARA_BP(x) ((x) << 22) 39 #define DCU_HSYN_PARA_PW(x) ((x) << 11) 40 #define DCU_HSYN_PARA_FP(x) (x) 41 42 #define DCU_VSYN_PARA 0x0020 43 #define DCU_VSYN_PARA_BP(x) ((x) << 22) 44 #define DCU_VSYN_PARA_PW(x) ((x) << 11) 45 #define DCU_VSYN_PARA_FP(x) (x) 46 47 #define DCU_SYN_POL 0x0024 48 #define DCU_SYN_POL_INV_PXCK BIT(6) 49 #define DCU_SYN_POL_NEG BIT(5) 50 #define DCU_SYN_POL_INV_VS_LOW BIT(1) 51 #define DCU_SYN_POL_INV_HS_LOW BIT(0) 52 53 #define DCU_THRESHOLD 0x0028 54 #define DCU_THRESHOLD_LS_BF_VS(x) ((x) << 16) 55 #define DCU_THRESHOLD_OUT_BUF_HIGH(x) ((x) << 8) 56 #define DCU_THRESHOLD_OUT_BUF_LOW(x) (x) 57 #define BF_VS_VAL 0x03 58 #define BUF_MAX_VAL 0x78 59 #define BUF_MIN_VAL 0x0a 60 61 #define DCU_INT_STATUS 0x002C 62 #define DCU_INT_STATUS_VSYNC BIT(0) 63 #define DCU_INT_STATUS_UNDRUN BIT(1) 64 #define DCU_INT_STATUS_LSBFVS BIT(2) 65 #define DCU_INT_STATUS_VBLANK BIT(3) 66 #define DCU_INT_STATUS_CRCREADY BIT(4) 67 #define DCU_INT_STATUS_CRCOVERFLOW BIT(5) 68 #define DCU_INT_STATUS_P1FIFOLO BIT(6) 69 #define DCU_INT_STATUS_P1FIFOHI BIT(7) 70 #define DCU_INT_STATUS_P2FIFOLO BIT(8) 71 #define DCU_INT_STATUS_P2FIFOHI BIT(9) 72 #define DCU_INT_STATUS_PROGEND BIT(10) 73 #define DCU_INT_STATUS_IPMERROR BIT(11) 74 #define DCU_INT_STATUS_LYRTRANS BIT(12) 75 #define DCU_INT_STATUS_DMATRANS BIT(14) 76 #define DCU_INT_STATUS_P3FIFOLO BIT(16) 77 #define DCU_INT_STATUS_P3FIFOHI BIT(17) 78 #define DCU_INT_STATUS_P4FIFOLO BIT(18) 79 #define DCU_INT_STATUS_P4FIFOHI BIT(19) 80 #define DCU_INT_STATUS_P1EMPTY BIT(26) 81 #define DCU_INT_STATUS_P2EMPTY BIT(27) 82 #define DCU_INT_STATUS_P3EMPTY BIT(28) 83 #define DCU_INT_STATUS_P4EMPTY BIT(29) 84 85 #define DCU_INT_MASK 0x0030 86 #define DCU_INT_MASK_VSYNC BIT(0) 87 #define DCU_INT_MASK_UNDRUN BIT(1) 88 #define DCU_INT_MASK_LSBFVS BIT(2) 89 #define DCU_INT_MASK_VBLANK BIT(3) 90 #define DCU_INT_MASK_CRCREADY BIT(4) 91 #define DCU_INT_MASK_CRCOVERFLOW BIT(5) 92 #define DCU_INT_MASK_P1FIFOLO BIT(6) 93 #define DCU_INT_MASK_P1FIFOHI BIT(7) 94 #define DCU_INT_MASK_P2FIFOLO BIT(8) 95 #define DCU_INT_MASK_P2FIFOHI BIT(9) 96 #define DCU_INT_MASK_PROGEND BIT(10) 97 #define DCU_INT_MASK_IPMERROR BIT(11) 98 #define DCU_INT_MASK_LYRTRANS BIT(12) 99 #define DCU_INT_MASK_DMATRANS BIT(14) 100 #define DCU_INT_MASK_P3FIFOLO BIT(16) 101 #define DCU_INT_MASK_P3FIFOHI BIT(17) 102 #define DCU_INT_MASK_P4FIFOLO BIT(18) 103 #define DCU_INT_MASK_P4FIFOHI BIT(19) 104 #define DCU_INT_MASK_P1EMPTY BIT(26) 105 #define DCU_INT_MASK_P2EMPTY BIT(27) 106 #define DCU_INT_MASK_P3EMPTY BIT(28) 107 #define DCU_INT_MASK_P4EMPTY BIT(29) 108 109 #define DCU_DIV_RATIO 0x0054 110 111 #define DCU_UPDATE_MODE 0x00cc 112 #define DCU_UPDATE_MODE_MODE BIT(31) 113 #define DCU_UPDATE_MODE_READREG BIT(30) 114 115 #define DCU_DCFB_MAX 0x300 116 117 #define DCU_CTRLDESCLN(layer, reg) (0x200 + (reg - 1) * 4 + (layer) * 0x40) 118 119 #define DCU_LAYER_HEIGHT(x) ((x) << 16) 120 #define DCU_LAYER_WIDTH(x) (x) 121 122 #define DCU_LAYER_POSY(x) ((x) << 16) 123 #define DCU_LAYER_POSX(x) (x) 124 125 #define DCU_LAYER_EN BIT(31) 126 #define DCU_LAYER_TILE_EN BIT(30) 127 #define DCU_LAYER_DATA_SEL_CLUT BIT(29) 128 #define DCU_LAYER_SAFETY_EN BIT(28) 129 #define DCU_LAYER_TRANS(x) ((x) << 20) 130 #define DCU_LAYER_BPP(x) ((x) << 16) 131 #define DCU_LAYER_RLE_EN BIT(15) 132 #define DCU_LAYER_LUOFFS(x) ((x) << 4) 133 #define DCU_LAYER_BB_ON BIT(2) 134 #define DCU_LAYER_AB_NONE 0 135 #define DCU_LAYER_AB_CHROMA_KEYING 1 136 #define DCU_LAYER_AB_WHOLE_FRAME 2 137 138 #define DCU_LAYER_CKMAX_R(x) ((x) << 16) 139 #define DCU_LAYER_CKMAX_G(x) ((x) << 8) 140 #define DCU_LAYER_CKMAX_B(x) (x) 141 142 #define DCU_LAYER_CKMIN_R(x) ((x) << 16) 143 #define DCU_LAYER_CKMIN_G(x) ((x) << 8) 144 #define DCU_LAYER_CKMIN_B(x) (x) 145 146 #define DCU_LAYER_TILE_VER(x) ((x) << 16) 147 #define DCU_LAYER_TILE_HOR(x) (x) 148 149 #define DCU_LAYER_FG_FCOLOR(x) (x) 150 151 #define DCU_LAYER_BG_BCOLOR(x) (x) 152 153 #define DCU_LAYER_POST_SKIP(x) ((x) << 16) 154 #define DCU_LAYER_PRE_SKIP(x) (x) 155 156 #define FSL_DCU_RGB565 4 157 #define FSL_DCU_RGB888 5 158 #define FSL_DCU_ARGB8888 6 159 #define FSL_DCU_ARGB1555 11 160 #define FSL_DCU_ARGB4444 12 161 #define FSL_DCU_YUV422 14 162 163 #define VF610_LAYER_REG_NUM 9 164 #define LS1021A_LAYER_REG_NUM 10 165 166 struct clk; 167 struct device; 168 struct drm_device; 169 170 struct fsl_dcu_soc_data { 171 const char *name; 172 /*total layer number*/ 173 unsigned int total_layer; 174 /*max layer number DCU supported*/ 175 unsigned int max_layer; 176 unsigned int layer_regs; 177 }; 178 179 struct fsl_dcu_drm_device { 180 struct device *dev; 181 struct device_node *np; 182 struct regmap *regmap; 183 int irq; 184 struct clk *clk; 185 struct clk *pix_clk; 186 struct fsl_tcon *tcon; 187 /*protects hardware register*/ 188 spinlock_t irq_lock; 189 struct drm_device *drm; 190 struct drm_crtc crtc; 191 struct drm_encoder encoder; 192 struct fsl_dcu_drm_connector connector; 193 const struct fsl_dcu_soc_data *soc; 194 }; 195 196 int fsl_dcu_drm_modeset_init(struct fsl_dcu_drm_device *fsl_dev); 197 198 #endif /* __FSL_DCU_DRM_DRV_H__ */ 199