1 /* 2 * Copyright 2015 Freescale Semiconductor, Inc. 3 * 4 * Freescale DCU drm device driver 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/regmap.h> 14 15 #include <drm/drmP.h> 16 #include <drm/drm_atomic.h> 17 #include <drm/drm_atomic_helper.h> 18 #include <drm/drm_crtc.h> 19 #include <drm/drm_crtc_helper.h> 20 21 #include "fsl_dcu_drm_crtc.h" 22 #include "fsl_dcu_drm_drv.h" 23 #include "fsl_dcu_drm_plane.h" 24 25 static void fsl_dcu_drm_crtc_atomic_begin(struct drm_crtc *crtc, 26 struct drm_crtc_state *old_crtc_state) 27 { 28 } 29 30 static int fsl_dcu_drm_crtc_atomic_check(struct drm_crtc *crtc, 31 struct drm_crtc_state *state) 32 { 33 return 0; 34 } 35 36 static void fsl_dcu_drm_crtc_atomic_flush(struct drm_crtc *crtc, 37 struct drm_crtc_state *old_crtc_state) 38 { 39 } 40 41 static void fsl_dcu_drm_disable_crtc(struct drm_crtc *crtc) 42 { 43 struct drm_device *dev = crtc->dev; 44 struct fsl_dcu_drm_device *fsl_dev = dev->dev_private; 45 46 regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE, 47 DCU_MODE_DCU_MODE_MASK, 48 DCU_MODE_DCU_MODE(DCU_MODE_OFF)); 49 regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE, 50 DCU_UPDATE_MODE_READREG); 51 } 52 53 static void fsl_dcu_drm_crtc_enable(struct drm_crtc *crtc) 54 { 55 struct drm_device *dev = crtc->dev; 56 struct fsl_dcu_drm_device *fsl_dev = dev->dev_private; 57 58 regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE, 59 DCU_MODE_DCU_MODE_MASK, 60 DCU_MODE_DCU_MODE(DCU_MODE_NORMAL)); 61 regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE, 62 DCU_UPDATE_MODE_READREG); 63 } 64 65 static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) 66 { 67 struct drm_device *dev = crtc->dev; 68 struct fsl_dcu_drm_device *fsl_dev = dev->dev_private; 69 struct drm_connector *con = &fsl_dev->connector.base; 70 struct drm_display_mode *mode = &crtc->state->mode; 71 unsigned int hbp, hfp, hsw, vbp, vfp, vsw, index, pol = 0; 72 73 index = drm_crtc_index(crtc); 74 clk_set_rate(fsl_dev->pix_clk, mode->clock * 1000); 75 76 /* Configure timings: */ 77 hbp = mode->htotal - mode->hsync_end; 78 hfp = mode->hsync_start - mode->hdisplay; 79 hsw = mode->hsync_end - mode->hsync_start; 80 vbp = mode->vtotal - mode->vsync_end; 81 vfp = mode->vsync_start - mode->vdisplay; 82 vsw = mode->vsync_end - mode->vsync_start; 83 84 /* INV_PXCK as default (most display sample data on rising edge) */ 85 if (!(con->display_info.bus_flags & DRM_BUS_FLAG_PIXDATA_POSEDGE)) 86 pol |= DCU_SYN_POL_INV_PXCK; 87 88 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 89 pol |= DCU_SYN_POL_INV_HS_LOW; 90 91 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 92 pol |= DCU_SYN_POL_INV_VS_LOW; 93 94 regmap_write(fsl_dev->regmap, DCU_HSYN_PARA, 95 DCU_HSYN_PARA_BP(hbp) | 96 DCU_HSYN_PARA_PW(hsw) | 97 DCU_HSYN_PARA_FP(hfp)); 98 regmap_write(fsl_dev->regmap, DCU_VSYN_PARA, 99 DCU_VSYN_PARA_BP(vbp) | 100 DCU_VSYN_PARA_PW(vsw) | 101 DCU_VSYN_PARA_FP(vfp)); 102 regmap_write(fsl_dev->regmap, DCU_DISP_SIZE, 103 DCU_DISP_SIZE_DELTA_Y(mode->vdisplay) | 104 DCU_DISP_SIZE_DELTA_X(mode->hdisplay)); 105 regmap_write(fsl_dev->regmap, DCU_SYN_POL, pol); 106 regmap_write(fsl_dev->regmap, DCU_BGND, DCU_BGND_R(0) | 107 DCU_BGND_G(0) | DCU_BGND_B(0)); 108 regmap_write(fsl_dev->regmap, DCU_DCU_MODE, 109 DCU_MODE_BLEND_ITER(1) | DCU_MODE_RASTER_EN); 110 regmap_write(fsl_dev->regmap, DCU_THRESHOLD, 111 DCU_THRESHOLD_LS_BF_VS(BF_VS_VAL) | 112 DCU_THRESHOLD_OUT_BUF_HIGH(BUF_MAX_VAL) | 113 DCU_THRESHOLD_OUT_BUF_LOW(BUF_MIN_VAL)); 114 regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE, 115 DCU_UPDATE_MODE_READREG); 116 return; 117 } 118 119 static const struct drm_crtc_helper_funcs fsl_dcu_drm_crtc_helper_funcs = { 120 .atomic_begin = fsl_dcu_drm_crtc_atomic_begin, 121 .atomic_check = fsl_dcu_drm_crtc_atomic_check, 122 .atomic_flush = fsl_dcu_drm_crtc_atomic_flush, 123 .disable = fsl_dcu_drm_disable_crtc, 124 .enable = fsl_dcu_drm_crtc_enable, 125 .mode_set_nofb = fsl_dcu_drm_crtc_mode_set_nofb, 126 }; 127 128 static const struct drm_crtc_funcs fsl_dcu_drm_crtc_funcs = { 129 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 130 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 131 .destroy = drm_crtc_cleanup, 132 .page_flip = drm_atomic_helper_page_flip, 133 .reset = drm_atomic_helper_crtc_reset, 134 .set_config = drm_atomic_helper_set_config, 135 }; 136 137 int fsl_dcu_drm_crtc_create(struct fsl_dcu_drm_device *fsl_dev) 138 { 139 struct drm_plane *primary; 140 struct drm_crtc *crtc = &fsl_dev->crtc; 141 unsigned int i, j, reg_num; 142 int ret; 143 144 primary = fsl_dcu_drm_primary_create_plane(fsl_dev->drm); 145 if (!primary) 146 return -ENOMEM; 147 148 ret = drm_crtc_init_with_planes(fsl_dev->drm, crtc, primary, NULL, 149 &fsl_dcu_drm_crtc_funcs, NULL); 150 if (ret) { 151 primary->funcs->destroy(primary); 152 return ret; 153 } 154 155 drm_crtc_helper_add(crtc, &fsl_dcu_drm_crtc_helper_funcs); 156 157 if (!strcmp(fsl_dev->soc->name, "ls1021a")) 158 reg_num = LS1021A_LAYER_REG_NUM; 159 else 160 reg_num = VF610_LAYER_REG_NUM; 161 for (i = 0; i < fsl_dev->soc->total_layer; i++) { 162 for (j = 1; j <= reg_num; j++) 163 regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(i, j), 0); 164 } 165 regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE, 166 DCU_MODE_DCU_MODE_MASK, 167 DCU_MODE_DCU_MODE(DCU_MODE_OFF)); 168 regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE, 169 DCU_UPDATE_MODE_READREG); 170 171 return 0; 172 } 173