1 /* 2 * 3 * Cloned from drivers/media/video/s5p-tv/regs-hdmi.h 4 * 5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. 6 * http://www.samsung.com/ 7 * 8 * HDMI register header file for Samsung TVOUT driver 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15 #ifndef SAMSUNG_REGS_HDMI_H 16 #define SAMSUNG_REGS_HDMI_H 17 18 /* 19 * Register part 20 */ 21 22 #define HDMI_CTRL_BASE(x) ((x) + 0x00000000) 23 #define HDMI_CORE_BASE(x) ((x) + 0x00010000) 24 #define HDMI_TG_BASE(x) ((x) + 0x00050000) 25 26 /* Control registers */ 27 #define HDMI_INTC_CON HDMI_CTRL_BASE(0x0000) 28 #define HDMI_INTC_FLAG HDMI_CTRL_BASE(0x0004) 29 #define HDMI_HPD_STATUS HDMI_CTRL_BASE(0x000C) 30 #define HDMI_PHY_RSTOUT HDMI_CTRL_BASE(0x0014) 31 #define HDMI_PHY_VPLL HDMI_CTRL_BASE(0x0018) 32 #define HDMI_PHY_CMU HDMI_CTRL_BASE(0x001C) 33 #define HDMI_CORE_RSTOUT HDMI_CTRL_BASE(0x0020) 34 35 /* Core registers */ 36 #define HDMI_CON_0 HDMI_CORE_BASE(0x0000) 37 #define HDMI_CON_1 HDMI_CORE_BASE(0x0004) 38 #define HDMI_CON_2 HDMI_CORE_BASE(0x0008) 39 #define HDMI_SYS_STATUS HDMI_CORE_BASE(0x0010) 40 #define HDMI_PHY_STATUS HDMI_CORE_BASE(0x0014) 41 #define HDMI_STATUS_EN HDMI_CORE_BASE(0x0020) 42 #define HDMI_HPD HDMI_CORE_BASE(0x0030) 43 #define HDMI_MODE_SEL HDMI_CORE_BASE(0x0040) 44 #define HDMI_BLUE_SCREEN_0 HDMI_CORE_BASE(0x0050) 45 #define HDMI_BLUE_SCREEN_1 HDMI_CORE_BASE(0x0054) 46 #define HDMI_BLUE_SCREEN_2 HDMI_CORE_BASE(0x0058) 47 #define HDMI_H_BLANK_0 HDMI_CORE_BASE(0x00A0) 48 #define HDMI_H_BLANK_1 HDMI_CORE_BASE(0x00A4) 49 #define HDMI_V_BLANK_0 HDMI_CORE_BASE(0x00B0) 50 #define HDMI_V_BLANK_1 HDMI_CORE_BASE(0x00B4) 51 #define HDMI_V_BLANK_2 HDMI_CORE_BASE(0x00B8) 52 #define HDMI_H_V_LINE_0 HDMI_CORE_BASE(0x00C0) 53 #define HDMI_H_V_LINE_1 HDMI_CORE_BASE(0x00C4) 54 #define HDMI_H_V_LINE_2 HDMI_CORE_BASE(0x00C8) 55 #define HDMI_VSYNC_POL HDMI_CORE_BASE(0x00E4) 56 #define HDMI_INT_PRO_MODE HDMI_CORE_BASE(0x00E8) 57 #define HDMI_V_BLANK_F_0 HDMI_CORE_BASE(0x0110) 58 #define HDMI_V_BLANK_F_1 HDMI_CORE_BASE(0x0114) 59 #define HDMI_V_BLANK_F_2 HDMI_CORE_BASE(0x0118) 60 #define HDMI_H_SYNC_GEN_0 HDMI_CORE_BASE(0x0120) 61 #define HDMI_H_SYNC_GEN_1 HDMI_CORE_BASE(0x0124) 62 #define HDMI_H_SYNC_GEN_2 HDMI_CORE_BASE(0x0128) 63 #define HDMI_V_SYNC_GEN_1_0 HDMI_CORE_BASE(0x0130) 64 #define HDMI_V_SYNC_GEN_1_1 HDMI_CORE_BASE(0x0134) 65 #define HDMI_V_SYNC_GEN_1_2 HDMI_CORE_BASE(0x0138) 66 #define HDMI_V_SYNC_GEN_2_0 HDMI_CORE_BASE(0x0140) 67 #define HDMI_V_SYNC_GEN_2_1 HDMI_CORE_BASE(0x0144) 68 #define HDMI_V_SYNC_GEN_2_2 HDMI_CORE_BASE(0x0148) 69 #define HDMI_V_SYNC_GEN_3_0 HDMI_CORE_BASE(0x0150) 70 #define HDMI_V_SYNC_GEN_3_1 HDMI_CORE_BASE(0x0154) 71 #define HDMI_V_SYNC_GEN_3_2 HDMI_CORE_BASE(0x0158) 72 #define HDMI_ACR_CON HDMI_CORE_BASE(0x0180) 73 #define HDMI_AVI_CON HDMI_CORE_BASE(0x0300) 74 #define HDMI_AVI_BYTE(n) HDMI_CORE_BASE(0x0320 + 4 * (n)) 75 #define HDMI_DC_CONTROL HDMI_CORE_BASE(0x05C0) 76 #define HDMI_VIDEO_PATTERN_GEN HDMI_CORE_BASE(0x05C4) 77 #define HDMI_HPD_GEN HDMI_CORE_BASE(0x05C8) 78 #define HDMI_AUI_CON HDMI_CORE_BASE(0x0360) 79 #define HDMI_SPD_CON HDMI_CORE_BASE(0x0400) 80 81 /* Timing generator registers */ 82 #define HDMI_TG_CMD HDMI_TG_BASE(0x0000) 83 #define HDMI_TG_H_FSZ_L HDMI_TG_BASE(0x0018) 84 #define HDMI_TG_H_FSZ_H HDMI_TG_BASE(0x001C) 85 #define HDMI_TG_HACT_ST_L HDMI_TG_BASE(0x0020) 86 #define HDMI_TG_HACT_ST_H HDMI_TG_BASE(0x0024) 87 #define HDMI_TG_HACT_SZ_L HDMI_TG_BASE(0x0028) 88 #define HDMI_TG_HACT_SZ_H HDMI_TG_BASE(0x002C) 89 #define HDMI_TG_V_FSZ_L HDMI_TG_BASE(0x0030) 90 #define HDMI_TG_V_FSZ_H HDMI_TG_BASE(0x0034) 91 #define HDMI_TG_VSYNC_L HDMI_TG_BASE(0x0038) 92 #define HDMI_TG_VSYNC_H HDMI_TG_BASE(0x003C) 93 #define HDMI_TG_VSYNC2_L HDMI_TG_BASE(0x0040) 94 #define HDMI_TG_VSYNC2_H HDMI_TG_BASE(0x0044) 95 #define HDMI_TG_VACT_ST_L HDMI_TG_BASE(0x0048) 96 #define HDMI_TG_VACT_ST_H HDMI_TG_BASE(0x004C) 97 #define HDMI_TG_VACT_SZ_L HDMI_TG_BASE(0x0050) 98 #define HDMI_TG_VACT_SZ_H HDMI_TG_BASE(0x0054) 99 #define HDMI_TG_FIELD_CHG_L HDMI_TG_BASE(0x0058) 100 #define HDMI_TG_FIELD_CHG_H HDMI_TG_BASE(0x005C) 101 #define HDMI_TG_VACT_ST2_L HDMI_TG_BASE(0x0060) 102 #define HDMI_TG_VACT_ST2_H HDMI_TG_BASE(0x0064) 103 #define HDMI_TG_VSYNC_TOP_HDMI_L HDMI_TG_BASE(0x0078) 104 #define HDMI_TG_VSYNC_TOP_HDMI_H HDMI_TG_BASE(0x007C) 105 #define HDMI_TG_VSYNC_BOT_HDMI_L HDMI_TG_BASE(0x0080) 106 #define HDMI_TG_VSYNC_BOT_HDMI_H HDMI_TG_BASE(0x0084) 107 #define HDMI_TG_FIELD_TOP_HDMI_L HDMI_TG_BASE(0x0088) 108 #define HDMI_TG_FIELD_TOP_HDMI_H HDMI_TG_BASE(0x008C) 109 #define HDMI_TG_FIELD_BOT_HDMI_L HDMI_TG_BASE(0x0090) 110 #define HDMI_TG_FIELD_BOT_HDMI_H HDMI_TG_BASE(0x0094) 111 112 /* 113 * Bit definition part 114 */ 115 116 /* HDMI_INTC_CON */ 117 #define HDMI_INTC_EN_GLOBAL (1 << 6) 118 #define HDMI_INTC_EN_HPD_PLUG (1 << 3) 119 #define HDMI_INTC_EN_HPD_UNPLUG (1 << 2) 120 121 /* HDMI_INTC_FLAG */ 122 #define HDMI_INTC_FLAG_HPD_PLUG (1 << 3) 123 #define HDMI_INTC_FLAG_HPD_UNPLUG (1 << 2) 124 125 /* HDMI_PHY_RSTOUT */ 126 #define HDMI_PHY_SW_RSTOUT (1 << 0) 127 128 /* HDMI_CORE_RSTOUT */ 129 #define HDMI_CORE_SW_RSTOUT (1 << 0) 130 131 /* HDMI_CON_0 */ 132 #define HDMI_BLUE_SCR_EN (1 << 5) 133 #define HDMI_EN (1 << 0) 134 135 /* HDMI_PHY_STATUS */ 136 #define HDMI_PHY_STATUS_READY (1 << 0) 137 138 /* HDMI_MODE_SEL */ 139 #define HDMI_MODE_HDMI_EN (1 << 1) 140 #define HDMI_MODE_DVI_EN (1 << 0) 141 #define HDMI_MODE_MASK (3 << 0) 142 143 /* HDMI_TG_CMD */ 144 #define HDMI_TG_EN (1 << 0) 145 #define HDMI_FIELD_EN (1 << 1) 146 147 #endif /* SAMSUNG_REGS_HDMI_H */ 148