1d8408326SSeung-Woo Kim /* 2d8408326SSeung-Woo Kim * 3d8408326SSeung-Woo Kim * Cloned from drivers/media/video/s5p-tv/regs-hdmi.h 4d8408326SSeung-Woo Kim * 5d8408326SSeung-Woo Kim * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. 6d8408326SSeung-Woo Kim * http://www.samsung.com/ 7d8408326SSeung-Woo Kim * 8d8408326SSeung-Woo Kim * HDMI register header file for Samsung TVOUT driver 9d8408326SSeung-Woo Kim * 10d8408326SSeung-Woo Kim * This program is free software; you can redistribute it and/or modify 11d8408326SSeung-Woo Kim * it under the terms of the GNU General Public License version 2 as 12d8408326SSeung-Woo Kim * published by the Free Software Foundation. 13d8408326SSeung-Woo Kim */ 14d8408326SSeung-Woo Kim 15d8408326SSeung-Woo Kim #ifndef SAMSUNG_REGS_HDMI_H 16d8408326SSeung-Woo Kim #define SAMSUNG_REGS_HDMI_H 17d8408326SSeung-Woo Kim 18d8408326SSeung-Woo Kim /* 19d8408326SSeung-Woo Kim * Register part 20d8408326SSeung-Woo Kim */ 21d8408326SSeung-Woo Kim 223ecd70b1SJoonyoung Shim /* HDMI Version 1.3 & Common */ 23d8408326SSeung-Woo Kim #define HDMI_CTRL_BASE(x) ((x) + 0x00000000) 24d8408326SSeung-Woo Kim #define HDMI_CORE_BASE(x) ((x) + 0x00010000) 253e148bafSSeung-Woo Kim #define HDMI_I2S_BASE(x) ((x) + 0x00040000) 26d8408326SSeung-Woo Kim #define HDMI_TG_BASE(x) ((x) + 0x00050000) 27d8408326SSeung-Woo Kim 28d8408326SSeung-Woo Kim /* Control registers */ 29d8408326SSeung-Woo Kim #define HDMI_INTC_CON HDMI_CTRL_BASE(0x0000) 30d8408326SSeung-Woo Kim #define HDMI_INTC_FLAG HDMI_CTRL_BASE(0x0004) 31d8408326SSeung-Woo Kim #define HDMI_HPD_STATUS HDMI_CTRL_BASE(0x000C) 323ecd70b1SJoonyoung Shim #define HDMI_V13_PHY_RSTOUT HDMI_CTRL_BASE(0x0014) 333ecd70b1SJoonyoung Shim #define HDMI_V13_PHY_VPLL HDMI_CTRL_BASE(0x0018) 343ecd70b1SJoonyoung Shim #define HDMI_V13_PHY_CMU HDMI_CTRL_BASE(0x001C) 353ecd70b1SJoonyoung Shim #define HDMI_V13_CORE_RSTOUT HDMI_CTRL_BASE(0x0020) 36d8408326SSeung-Woo Kim 37d8408326SSeung-Woo Kim /* Core registers */ 38d8408326SSeung-Woo Kim #define HDMI_CON_0 HDMI_CORE_BASE(0x0000) 39d8408326SSeung-Woo Kim #define HDMI_CON_1 HDMI_CORE_BASE(0x0004) 40d8408326SSeung-Woo Kim #define HDMI_CON_2 HDMI_CORE_BASE(0x0008) 41d8408326SSeung-Woo Kim #define HDMI_SYS_STATUS HDMI_CORE_BASE(0x0010) 423ecd70b1SJoonyoung Shim #define HDMI_V13_PHY_STATUS HDMI_CORE_BASE(0x0014) 43d8408326SSeung-Woo Kim #define HDMI_STATUS_EN HDMI_CORE_BASE(0x0020) 44d8408326SSeung-Woo Kim #define HDMI_HPD HDMI_CORE_BASE(0x0030) 45d8408326SSeung-Woo Kim #define HDMI_MODE_SEL HDMI_CORE_BASE(0x0040) 463ecd70b1SJoonyoung Shim #define HDMI_ENC_EN HDMI_CORE_BASE(0x0044) 473ecd70b1SJoonyoung Shim #define HDMI_V13_BLUE_SCREEN_0 HDMI_CORE_BASE(0x0050) 483ecd70b1SJoonyoung Shim #define HDMI_V13_BLUE_SCREEN_1 HDMI_CORE_BASE(0x0054) 493ecd70b1SJoonyoung Shim #define HDMI_V13_BLUE_SCREEN_2 HDMI_CORE_BASE(0x0058) 50d8408326SSeung-Woo Kim #define HDMI_H_BLANK_0 HDMI_CORE_BASE(0x00A0) 51d8408326SSeung-Woo Kim #define HDMI_H_BLANK_1 HDMI_CORE_BASE(0x00A4) 523ecd70b1SJoonyoung Shim #define HDMI_V13_V_BLANK_0 HDMI_CORE_BASE(0x00B0) 533ecd70b1SJoonyoung Shim #define HDMI_V13_V_BLANK_1 HDMI_CORE_BASE(0x00B4) 543ecd70b1SJoonyoung Shim #define HDMI_V13_V_BLANK_2 HDMI_CORE_BASE(0x00B8) 553ecd70b1SJoonyoung Shim #define HDMI_V13_H_V_LINE_0 HDMI_CORE_BASE(0x00C0) 563ecd70b1SJoonyoung Shim #define HDMI_V13_H_V_LINE_1 HDMI_CORE_BASE(0x00C4) 573ecd70b1SJoonyoung Shim #define HDMI_V13_H_V_LINE_2 HDMI_CORE_BASE(0x00C8) 58d8408326SSeung-Woo Kim #define HDMI_VSYNC_POL HDMI_CORE_BASE(0x00E4) 59d8408326SSeung-Woo Kim #define HDMI_INT_PRO_MODE HDMI_CORE_BASE(0x00E8) 603ecd70b1SJoonyoung Shim #define HDMI_V13_V_BLANK_F_0 HDMI_CORE_BASE(0x0110) 613ecd70b1SJoonyoung Shim #define HDMI_V13_V_BLANK_F_1 HDMI_CORE_BASE(0x0114) 623ecd70b1SJoonyoung Shim #define HDMI_V13_V_BLANK_F_2 HDMI_CORE_BASE(0x0118) 633ecd70b1SJoonyoung Shim #define HDMI_V13_H_SYNC_GEN_0 HDMI_CORE_BASE(0x0120) 643ecd70b1SJoonyoung Shim #define HDMI_V13_H_SYNC_GEN_1 HDMI_CORE_BASE(0x0124) 653ecd70b1SJoonyoung Shim #define HDMI_V13_H_SYNC_GEN_2 HDMI_CORE_BASE(0x0128) 663ecd70b1SJoonyoung Shim #define HDMI_V13_V_SYNC_GEN_1_0 HDMI_CORE_BASE(0x0130) 673ecd70b1SJoonyoung Shim #define HDMI_V13_V_SYNC_GEN_1_1 HDMI_CORE_BASE(0x0134) 683ecd70b1SJoonyoung Shim #define HDMI_V13_V_SYNC_GEN_1_2 HDMI_CORE_BASE(0x0138) 693ecd70b1SJoonyoung Shim #define HDMI_V13_V_SYNC_GEN_2_0 HDMI_CORE_BASE(0x0140) 703ecd70b1SJoonyoung Shim #define HDMI_V13_V_SYNC_GEN_2_1 HDMI_CORE_BASE(0x0144) 713ecd70b1SJoonyoung Shim #define HDMI_V13_V_SYNC_GEN_2_2 HDMI_CORE_BASE(0x0148) 723ecd70b1SJoonyoung Shim #define HDMI_V13_V_SYNC_GEN_3_0 HDMI_CORE_BASE(0x0150) 733ecd70b1SJoonyoung Shim #define HDMI_V13_V_SYNC_GEN_3_1 HDMI_CORE_BASE(0x0154) 743ecd70b1SJoonyoung Shim #define HDMI_V13_V_SYNC_GEN_3_2 HDMI_CORE_BASE(0x0158) 753ecd70b1SJoonyoung Shim #define HDMI_V13_ACR_CON HDMI_CORE_BASE(0x0180) 763ecd70b1SJoonyoung Shim #define HDMI_V13_AVI_CON HDMI_CORE_BASE(0x0300) 773ecd70b1SJoonyoung Shim #define HDMI_V13_AVI_BYTE(n) HDMI_CORE_BASE(0x0320 + 4 * (n)) 783ecd70b1SJoonyoung Shim #define HDMI_V13_DC_CONTROL HDMI_CORE_BASE(0x05C0) 793ecd70b1SJoonyoung Shim #define HDMI_V13_VIDEO_PATTERN_GEN HDMI_CORE_BASE(0x05C4) 803ecd70b1SJoonyoung Shim #define HDMI_V13_HPD_GEN HDMI_CORE_BASE(0x05C8) 813ecd70b1SJoonyoung Shim #define HDMI_V13_AUI_CON HDMI_CORE_BASE(0x0360) 823ecd70b1SJoonyoung Shim #define HDMI_V13_SPD_CON HDMI_CORE_BASE(0x0400) 83d8408326SSeung-Woo Kim 84d8408326SSeung-Woo Kim /* Timing generator registers */ 85d8408326SSeung-Woo Kim #define HDMI_TG_CMD HDMI_TG_BASE(0x0000) 86d8408326SSeung-Woo Kim #define HDMI_TG_H_FSZ_L HDMI_TG_BASE(0x0018) 87d8408326SSeung-Woo Kim #define HDMI_TG_H_FSZ_H HDMI_TG_BASE(0x001C) 88d8408326SSeung-Woo Kim #define HDMI_TG_HACT_ST_L HDMI_TG_BASE(0x0020) 89d8408326SSeung-Woo Kim #define HDMI_TG_HACT_ST_H HDMI_TG_BASE(0x0024) 90d8408326SSeung-Woo Kim #define HDMI_TG_HACT_SZ_L HDMI_TG_BASE(0x0028) 91d8408326SSeung-Woo Kim #define HDMI_TG_HACT_SZ_H HDMI_TG_BASE(0x002C) 92d8408326SSeung-Woo Kim #define HDMI_TG_V_FSZ_L HDMI_TG_BASE(0x0030) 93d8408326SSeung-Woo Kim #define HDMI_TG_V_FSZ_H HDMI_TG_BASE(0x0034) 94d8408326SSeung-Woo Kim #define HDMI_TG_VSYNC_L HDMI_TG_BASE(0x0038) 95d8408326SSeung-Woo Kim #define HDMI_TG_VSYNC_H HDMI_TG_BASE(0x003C) 96d8408326SSeung-Woo Kim #define HDMI_TG_VSYNC2_L HDMI_TG_BASE(0x0040) 97d8408326SSeung-Woo Kim #define HDMI_TG_VSYNC2_H HDMI_TG_BASE(0x0044) 98d8408326SSeung-Woo Kim #define HDMI_TG_VACT_ST_L HDMI_TG_BASE(0x0048) 99d8408326SSeung-Woo Kim #define HDMI_TG_VACT_ST_H HDMI_TG_BASE(0x004C) 100d8408326SSeung-Woo Kim #define HDMI_TG_VACT_SZ_L HDMI_TG_BASE(0x0050) 101d8408326SSeung-Woo Kim #define HDMI_TG_VACT_SZ_H HDMI_TG_BASE(0x0054) 102d8408326SSeung-Woo Kim #define HDMI_TG_FIELD_CHG_L HDMI_TG_BASE(0x0058) 103d8408326SSeung-Woo Kim #define HDMI_TG_FIELD_CHG_H HDMI_TG_BASE(0x005C) 104d8408326SSeung-Woo Kim #define HDMI_TG_VACT_ST2_L HDMI_TG_BASE(0x0060) 105d8408326SSeung-Woo Kim #define HDMI_TG_VACT_ST2_H HDMI_TG_BASE(0x0064) 106d8408326SSeung-Woo Kim #define HDMI_TG_VSYNC_TOP_HDMI_L HDMI_TG_BASE(0x0078) 107d8408326SSeung-Woo Kim #define HDMI_TG_VSYNC_TOP_HDMI_H HDMI_TG_BASE(0x007C) 108d8408326SSeung-Woo Kim #define HDMI_TG_VSYNC_BOT_HDMI_L HDMI_TG_BASE(0x0080) 109d8408326SSeung-Woo Kim #define HDMI_TG_VSYNC_BOT_HDMI_H HDMI_TG_BASE(0x0084) 110d8408326SSeung-Woo Kim #define HDMI_TG_FIELD_TOP_HDMI_L HDMI_TG_BASE(0x0088) 111d8408326SSeung-Woo Kim #define HDMI_TG_FIELD_TOP_HDMI_H HDMI_TG_BASE(0x008C) 112d8408326SSeung-Woo Kim #define HDMI_TG_FIELD_BOT_HDMI_L HDMI_TG_BASE(0x0090) 113d8408326SSeung-Woo Kim #define HDMI_TG_FIELD_BOT_HDMI_H HDMI_TG_BASE(0x0094) 114d8408326SSeung-Woo Kim 115d8408326SSeung-Woo Kim /* 116d8408326SSeung-Woo Kim * Bit definition part 117d8408326SSeung-Woo Kim */ 118d8408326SSeung-Woo Kim 119d8408326SSeung-Woo Kim /* HDMI_INTC_CON */ 120d8408326SSeung-Woo Kim #define HDMI_INTC_EN_GLOBAL (1 << 6) 121d8408326SSeung-Woo Kim #define HDMI_INTC_EN_HPD_PLUG (1 << 3) 122d8408326SSeung-Woo Kim #define HDMI_INTC_EN_HPD_UNPLUG (1 << 2) 123d8408326SSeung-Woo Kim 124d8408326SSeung-Woo Kim /* HDMI_INTC_FLAG */ 125d8408326SSeung-Woo Kim #define HDMI_INTC_FLAG_HPD_PLUG (1 << 3) 126d8408326SSeung-Woo Kim #define HDMI_INTC_FLAG_HPD_UNPLUG (1 << 2) 127d8408326SSeung-Woo Kim 128d8408326SSeung-Woo Kim /* HDMI_PHY_RSTOUT */ 129d8408326SSeung-Woo Kim #define HDMI_PHY_SW_RSTOUT (1 << 0) 130d8408326SSeung-Woo Kim 131d8408326SSeung-Woo Kim /* HDMI_CORE_RSTOUT */ 132d8408326SSeung-Woo Kim #define HDMI_CORE_SW_RSTOUT (1 << 0) 133d8408326SSeung-Woo Kim 134d8408326SSeung-Woo Kim /* HDMI_CON_0 */ 135d8408326SSeung-Woo Kim #define HDMI_BLUE_SCR_EN (1 << 5) 1363e148bafSSeung-Woo Kim #define HDMI_ASP_EN (1 << 2) 1373e148bafSSeung-Woo Kim #define HDMI_ASP_DIS (0 << 2) 1383e148bafSSeung-Woo Kim #define HDMI_ASP_MASK (1 << 2) 139d8408326SSeung-Woo Kim #define HDMI_EN (1 << 0) 140d8408326SSeung-Woo Kim 141872d20d6SSeung-Woo Kim /* HDMI_CON_2 */ 142872d20d6SSeung-Woo Kim #define HDMI_VID_PREAMBLE_DIS (1 << 5) 143872d20d6SSeung-Woo Kim #define HDMI_GUARD_BAND_DIS (1 << 1) 144872d20d6SSeung-Woo Kim 145d8408326SSeung-Woo Kim /* HDMI_PHY_STATUS */ 146d8408326SSeung-Woo Kim #define HDMI_PHY_STATUS_READY (1 << 0) 147d8408326SSeung-Woo Kim 148d8408326SSeung-Woo Kim /* HDMI_MODE_SEL */ 149d8408326SSeung-Woo Kim #define HDMI_MODE_HDMI_EN (1 << 1) 150d8408326SSeung-Woo Kim #define HDMI_MODE_DVI_EN (1 << 0) 151d8408326SSeung-Woo Kim #define HDMI_MODE_MASK (3 << 0) 152d8408326SSeung-Woo Kim 153d8408326SSeung-Woo Kim /* HDMI_TG_CMD */ 154d8408326SSeung-Woo Kim #define HDMI_TG_EN (1 << 0) 155d8408326SSeung-Woo Kim #define HDMI_FIELD_EN (1 << 1) 156d8408326SSeung-Woo Kim 1573ecd70b1SJoonyoung Shim 1583ecd70b1SJoonyoung Shim /* HDMI Version 1.4 */ 1593ecd70b1SJoonyoung Shim /* Control registers */ 1603ecd70b1SJoonyoung Shim /* #define HDMI_INTC_CON HDMI_CTRL_BASE(0x0000) */ 1613ecd70b1SJoonyoung Shim /* #define HDMI_INTC_FLAG HDMI_CTRL_BASE(0x0004) */ 1623ecd70b1SJoonyoung Shim #define HDMI_HDCP_KEY_LOAD HDMI_CTRL_BASE(0x0008) 1633ecd70b1SJoonyoung Shim /* #define HDMI_HPD_STATUS HDMI_CTRL_BASE(0x000C) */ 1643ecd70b1SJoonyoung Shim #define HDMI_INTC_CON_1 HDMI_CTRL_BASE(0x0010) 1653ecd70b1SJoonyoung Shim #define HDMI_INTC_FLAG_1 HDMI_CTRL_BASE(0x0014) 1663ecd70b1SJoonyoung Shim #define HDMI_PHY_STATUS_0 HDMI_CTRL_BASE(0x0020) 1673ecd70b1SJoonyoung Shim #define HDMI_PHY_STATUS_CMU HDMI_CTRL_BASE(0x0024) 1683ecd70b1SJoonyoung Shim #define HDMI_PHY_STATUS_PLL HDMI_CTRL_BASE(0x0028) 1693ecd70b1SJoonyoung Shim #define HDMI_PHY_CON_0 HDMI_CTRL_BASE(0x0030) 1703ecd70b1SJoonyoung Shim #define HDMI_HPD_CTRL HDMI_CTRL_BASE(0x0040) 1713ecd70b1SJoonyoung Shim #define HDMI_HPD_ST HDMI_CTRL_BASE(0x0044) 1723ecd70b1SJoonyoung Shim #define HDMI_HPD_TH_X HDMI_CTRL_BASE(0x0050) 1733ecd70b1SJoonyoung Shim #define HDMI_AUDIO_CLKSEL HDMI_CTRL_BASE(0x0070) 174*633d00b3SAndrzej Hajda #define HDMI_V14_PHY_RSTOUT HDMI_CTRL_BASE(0x0074) 1753ecd70b1SJoonyoung Shim #define HDMI_PHY_VPLL HDMI_CTRL_BASE(0x0078) 1763ecd70b1SJoonyoung Shim #define HDMI_PHY_CMU HDMI_CTRL_BASE(0x007C) 1773ecd70b1SJoonyoung Shim #define HDMI_CORE_RSTOUT HDMI_CTRL_BASE(0x0080) 1783ecd70b1SJoonyoung Shim 179a5562257SRahul Sharma /* PHY Control bit definition */ 180a5562257SRahul Sharma 181a5562257SRahul Sharma /* HDMI_PHY_CON_0 */ 182a5562257SRahul Sharma #define HDMI_PHY_POWER_OFF_EN (1 << 0) 183a5562257SRahul Sharma 1843ecd70b1SJoonyoung Shim /* Video related registers */ 1853ecd70b1SJoonyoung Shim #define HDMI_YMAX HDMI_CORE_BASE(0x0060) 1863ecd70b1SJoonyoung Shim #define HDMI_YMIN HDMI_CORE_BASE(0x0064) 1873ecd70b1SJoonyoung Shim #define HDMI_CMAX HDMI_CORE_BASE(0x0068) 1883ecd70b1SJoonyoung Shim #define HDMI_CMIN HDMI_CORE_BASE(0x006C) 1893ecd70b1SJoonyoung Shim 1903ecd70b1SJoonyoung Shim #define HDMI_V2_BLANK_0 HDMI_CORE_BASE(0x00B0) 1913ecd70b1SJoonyoung Shim #define HDMI_V2_BLANK_1 HDMI_CORE_BASE(0x00B4) 1923ecd70b1SJoonyoung Shim #define HDMI_V1_BLANK_0 HDMI_CORE_BASE(0x00B8) 1933ecd70b1SJoonyoung Shim #define HDMI_V1_BLANK_1 HDMI_CORE_BASE(0x00BC) 1943ecd70b1SJoonyoung Shim 1953ecd70b1SJoonyoung Shim #define HDMI_V_LINE_0 HDMI_CORE_BASE(0x00C0) 1963ecd70b1SJoonyoung Shim #define HDMI_V_LINE_1 HDMI_CORE_BASE(0x00C4) 1973ecd70b1SJoonyoung Shim #define HDMI_H_LINE_0 HDMI_CORE_BASE(0x00C8) 1983ecd70b1SJoonyoung Shim #define HDMI_H_LINE_1 HDMI_CORE_BASE(0x00CC) 1993ecd70b1SJoonyoung Shim 2003ecd70b1SJoonyoung Shim #define HDMI_HSYNC_POL HDMI_CORE_BASE(0x00E0) 2013ecd70b1SJoonyoung Shim 2023ecd70b1SJoonyoung Shim #define HDMI_V_BLANK_F0_0 HDMI_CORE_BASE(0x0110) 2033ecd70b1SJoonyoung Shim #define HDMI_V_BLANK_F0_1 HDMI_CORE_BASE(0x0114) 2043ecd70b1SJoonyoung Shim #define HDMI_V_BLANK_F1_0 HDMI_CORE_BASE(0x0118) 2053ecd70b1SJoonyoung Shim #define HDMI_V_BLANK_F1_1 HDMI_CORE_BASE(0x011C) 2063ecd70b1SJoonyoung Shim 2073ecd70b1SJoonyoung Shim #define HDMI_H_SYNC_START_0 HDMI_CORE_BASE(0x0120) 2083ecd70b1SJoonyoung Shim #define HDMI_H_SYNC_START_1 HDMI_CORE_BASE(0x0124) 2093ecd70b1SJoonyoung Shim #define HDMI_H_SYNC_END_0 HDMI_CORE_BASE(0x0128) 2103ecd70b1SJoonyoung Shim #define HDMI_H_SYNC_END_1 HDMI_CORE_BASE(0x012C) 2113ecd70b1SJoonyoung Shim 2123ecd70b1SJoonyoung Shim #define HDMI_V_SYNC_LINE_BEF_2_0 HDMI_CORE_BASE(0x0130) 2133ecd70b1SJoonyoung Shim #define HDMI_V_SYNC_LINE_BEF_2_1 HDMI_CORE_BASE(0x0134) 2143ecd70b1SJoonyoung Shim #define HDMI_V_SYNC_LINE_BEF_1_0 HDMI_CORE_BASE(0x0138) 2153ecd70b1SJoonyoung Shim #define HDMI_V_SYNC_LINE_BEF_1_1 HDMI_CORE_BASE(0x013C) 2163ecd70b1SJoonyoung Shim 2173ecd70b1SJoonyoung Shim #define HDMI_V_SYNC_LINE_AFT_2_0 HDMI_CORE_BASE(0x0140) 2183ecd70b1SJoonyoung Shim #define HDMI_V_SYNC_LINE_AFT_2_1 HDMI_CORE_BASE(0x0144) 2193ecd70b1SJoonyoung Shim #define HDMI_V_SYNC_LINE_AFT_1_0 HDMI_CORE_BASE(0x0148) 2203ecd70b1SJoonyoung Shim #define HDMI_V_SYNC_LINE_AFT_1_1 HDMI_CORE_BASE(0x014C) 2213ecd70b1SJoonyoung Shim 2223ecd70b1SJoonyoung Shim #define HDMI_V_SYNC_LINE_AFT_PXL_2_0 HDMI_CORE_BASE(0x0150) 2233ecd70b1SJoonyoung Shim #define HDMI_V_SYNC_LINE_AFT_PXL_2_1 HDMI_CORE_BASE(0x0154) 2243ecd70b1SJoonyoung Shim #define HDMI_V_SYNC_LINE_AFT_PXL_1_0 HDMI_CORE_BASE(0x0158) 2253ecd70b1SJoonyoung Shim #define HDMI_V_SYNC_LINE_AFT_PXL_1_1 HDMI_CORE_BASE(0x015C) 2263ecd70b1SJoonyoung Shim 2273ecd70b1SJoonyoung Shim #define HDMI_V_BLANK_F2_0 HDMI_CORE_BASE(0x0160) 2283ecd70b1SJoonyoung Shim #define HDMI_V_BLANK_F2_1 HDMI_CORE_BASE(0x0164) 2293ecd70b1SJoonyoung Shim #define HDMI_V_BLANK_F3_0 HDMI_CORE_BASE(0x0168) 2303ecd70b1SJoonyoung Shim #define HDMI_V_BLANK_F3_1 HDMI_CORE_BASE(0x016C) 2313ecd70b1SJoonyoung Shim #define HDMI_V_BLANK_F4_0 HDMI_CORE_BASE(0x0170) 2323ecd70b1SJoonyoung Shim #define HDMI_V_BLANK_F4_1 HDMI_CORE_BASE(0x0174) 2333ecd70b1SJoonyoung Shim #define HDMI_V_BLANK_F5_0 HDMI_CORE_BASE(0x0178) 2343ecd70b1SJoonyoung Shim #define HDMI_V_BLANK_F5_1 HDMI_CORE_BASE(0x017C) 2353ecd70b1SJoonyoung Shim 2363ecd70b1SJoonyoung Shim #define HDMI_V_SYNC_LINE_AFT_3_0 HDMI_CORE_BASE(0x0180) 2373ecd70b1SJoonyoung Shim #define HDMI_V_SYNC_LINE_AFT_3_1 HDMI_CORE_BASE(0x0184) 2383ecd70b1SJoonyoung Shim #define HDMI_V_SYNC_LINE_AFT_4_0 HDMI_CORE_BASE(0x0188) 2393ecd70b1SJoonyoung Shim #define HDMI_V_SYNC_LINE_AFT_4_1 HDMI_CORE_BASE(0x018C) 2403ecd70b1SJoonyoung Shim #define HDMI_V_SYNC_LINE_AFT_5_0 HDMI_CORE_BASE(0x0190) 2413ecd70b1SJoonyoung Shim #define HDMI_V_SYNC_LINE_AFT_5_1 HDMI_CORE_BASE(0x0194) 2423ecd70b1SJoonyoung Shim #define HDMI_V_SYNC_LINE_AFT_6_0 HDMI_CORE_BASE(0x0198) 2433ecd70b1SJoonyoung Shim #define HDMI_V_SYNC_LINE_AFT_6_1 HDMI_CORE_BASE(0x019C) 2443ecd70b1SJoonyoung Shim 2453ecd70b1SJoonyoung Shim #define HDMI_V_SYNC_LINE_AFT_PXL_3_0 HDMI_CORE_BASE(0x01A0) 2463ecd70b1SJoonyoung Shim #define HDMI_V_SYNC_LINE_AFT_PXL_3_1 HDMI_CORE_BASE(0x01A4) 2473ecd70b1SJoonyoung Shim #define HDMI_V_SYNC_LINE_AFT_PXL_4_0 HDMI_CORE_BASE(0x01A8) 2483ecd70b1SJoonyoung Shim #define HDMI_V_SYNC_LINE_AFT_PXL_4_1 HDMI_CORE_BASE(0x01AC) 2493ecd70b1SJoonyoung Shim #define HDMI_V_SYNC_LINE_AFT_PXL_5_0 HDMI_CORE_BASE(0x01B0) 2503ecd70b1SJoonyoung Shim #define HDMI_V_SYNC_LINE_AFT_PXL_5_1 HDMI_CORE_BASE(0x01B4) 2513ecd70b1SJoonyoung Shim #define HDMI_V_SYNC_LINE_AFT_PXL_6_0 HDMI_CORE_BASE(0x01B8) 2523ecd70b1SJoonyoung Shim #define HDMI_V_SYNC_LINE_AFT_PXL_6_1 HDMI_CORE_BASE(0x01BC) 2533ecd70b1SJoonyoung Shim 2543ecd70b1SJoonyoung Shim #define HDMI_VACT_SPACE_1_0 HDMI_CORE_BASE(0x01C0) 2553ecd70b1SJoonyoung Shim #define HDMI_VACT_SPACE_1_1 HDMI_CORE_BASE(0x01C4) 2563ecd70b1SJoonyoung Shim #define HDMI_VACT_SPACE_2_0 HDMI_CORE_BASE(0x01C8) 2573ecd70b1SJoonyoung Shim #define HDMI_VACT_SPACE_2_1 HDMI_CORE_BASE(0x01CC) 2583ecd70b1SJoonyoung Shim #define HDMI_VACT_SPACE_3_0 HDMI_CORE_BASE(0x01D0) 2593ecd70b1SJoonyoung Shim #define HDMI_VACT_SPACE_3_1 HDMI_CORE_BASE(0x01D4) 2603ecd70b1SJoonyoung Shim #define HDMI_VACT_SPACE_4_0 HDMI_CORE_BASE(0x01D8) 2613ecd70b1SJoonyoung Shim #define HDMI_VACT_SPACE_4_1 HDMI_CORE_BASE(0x01DC) 2623ecd70b1SJoonyoung Shim #define HDMI_VACT_SPACE_5_0 HDMI_CORE_BASE(0x01E0) 2633ecd70b1SJoonyoung Shim #define HDMI_VACT_SPACE_5_1 HDMI_CORE_BASE(0x01E4) 2643ecd70b1SJoonyoung Shim #define HDMI_VACT_SPACE_6_0 HDMI_CORE_BASE(0x01E8) 2653ecd70b1SJoonyoung Shim #define HDMI_VACT_SPACE_6_1 HDMI_CORE_BASE(0x01EC) 2663ecd70b1SJoonyoung Shim 2673ecd70b1SJoonyoung Shim #define HDMI_GCP_CON HDMI_CORE_BASE(0x0200) 2683ecd70b1SJoonyoung Shim #define HDMI_GCP_BYTE1 HDMI_CORE_BASE(0x0210) 2693ecd70b1SJoonyoung Shim #define HDMI_GCP_BYTE2 HDMI_CORE_BASE(0x0214) 2703ecd70b1SJoonyoung Shim #define HDMI_GCP_BYTE3 HDMI_CORE_BASE(0x0218) 2713ecd70b1SJoonyoung Shim 2723ecd70b1SJoonyoung Shim /* Audio related registers */ 2733ecd70b1SJoonyoung Shim #define HDMI_ASP_CON HDMI_CORE_BASE(0x0300) 2743ecd70b1SJoonyoung Shim #define HDMI_ASP_SP_FLAT HDMI_CORE_BASE(0x0304) 2753ecd70b1SJoonyoung Shim #define HDMI_ASP_CHCFG0 HDMI_CORE_BASE(0x0310) 2763ecd70b1SJoonyoung Shim #define HDMI_ASP_CHCFG1 HDMI_CORE_BASE(0x0314) 2773ecd70b1SJoonyoung Shim #define HDMI_ASP_CHCFG2 HDMI_CORE_BASE(0x0318) 2783ecd70b1SJoonyoung Shim #define HDMI_ASP_CHCFG3 HDMI_CORE_BASE(0x031C) 2793ecd70b1SJoonyoung Shim 280*633d00b3SAndrzej Hajda #define HDMI_V14_ACR_CON HDMI_CORE_BASE(0x0400) 2813ecd70b1SJoonyoung Shim #define HDMI_ACR_MCTS0 HDMI_CORE_BASE(0x0410) 2823ecd70b1SJoonyoung Shim #define HDMI_ACR_MCTS1 HDMI_CORE_BASE(0x0414) 2833ecd70b1SJoonyoung Shim #define HDMI_ACR_MCTS2 HDMI_CORE_BASE(0x0418) 2843e148bafSSeung-Woo Kim #define HDMI_ACR_CTS0 HDMI_CORE_BASE(0x0420) 2853e148bafSSeung-Woo Kim #define HDMI_ACR_CTS1 HDMI_CORE_BASE(0x0424) 2863e148bafSSeung-Woo Kim #define HDMI_ACR_CTS2 HDMI_CORE_BASE(0x0428) 2873ecd70b1SJoonyoung Shim #define HDMI_ACR_N0 HDMI_CORE_BASE(0x0430) 2883ecd70b1SJoonyoung Shim #define HDMI_ACR_N1 HDMI_CORE_BASE(0x0434) 2893ecd70b1SJoonyoung Shim #define HDMI_ACR_N2 HDMI_CORE_BASE(0x0438) 2903ecd70b1SJoonyoung Shim 2913ecd70b1SJoonyoung Shim /* Packet related registers */ 2923ecd70b1SJoonyoung Shim #define HDMI_ACP_CON HDMI_CORE_BASE(0x0500) 2933ecd70b1SJoonyoung Shim #define HDMI_ACP_TYPE HDMI_CORE_BASE(0x0514) 2943ecd70b1SJoonyoung Shim #define HDMI_ACP_DATA(n) HDMI_CORE_BASE(0x0520 + 4 * (n)) 2953ecd70b1SJoonyoung Shim 2963ecd70b1SJoonyoung Shim #define HDMI_ISRC_CON HDMI_CORE_BASE(0x0600) 2973ecd70b1SJoonyoung Shim #define HDMI_ISRC1_HEADER1 HDMI_CORE_BASE(0x0614) 2983ecd70b1SJoonyoung Shim #define HDMI_ISRC1_DATA(n) HDMI_CORE_BASE(0x0620 + 4 * (n)) 2993ecd70b1SJoonyoung Shim #define HDMI_ISRC2_DATA(n) HDMI_CORE_BASE(0x06A0 + 4 * (n)) 3003ecd70b1SJoonyoung Shim 3013ecd70b1SJoonyoung Shim #define HDMI_AVI_CON HDMI_CORE_BASE(0x0700) 3023ecd70b1SJoonyoung Shim #define HDMI_AVI_HEADER0 HDMI_CORE_BASE(0x0710) 3033ecd70b1SJoonyoung Shim #define HDMI_AVI_HEADER1 HDMI_CORE_BASE(0x0714) 3043ecd70b1SJoonyoung Shim #define HDMI_AVI_HEADER2 HDMI_CORE_BASE(0x0718) 3053ecd70b1SJoonyoung Shim #define HDMI_AVI_CHECK_SUM HDMI_CORE_BASE(0x071C) 306a144c2e9SRahul Sharma #define HDMI_AVI_BYTE(n) HDMI_CORE_BASE(0x0720 + 4 * (n-1)) 3073ecd70b1SJoonyoung Shim 3083ecd70b1SJoonyoung Shim #define HDMI_AUI_CON HDMI_CORE_BASE(0x0800) 3093ecd70b1SJoonyoung Shim #define HDMI_AUI_HEADER0 HDMI_CORE_BASE(0x0810) 3103ecd70b1SJoonyoung Shim #define HDMI_AUI_HEADER1 HDMI_CORE_BASE(0x0814) 3113ecd70b1SJoonyoung Shim #define HDMI_AUI_HEADER2 HDMI_CORE_BASE(0x0818) 3123ecd70b1SJoonyoung Shim #define HDMI_AUI_CHECK_SUM HDMI_CORE_BASE(0x081C) 313a144c2e9SRahul Sharma #define HDMI_AUI_BYTE(n) HDMI_CORE_BASE(0x0820 + 4 * (n-1)) 3143ecd70b1SJoonyoung Shim 3153ecd70b1SJoonyoung Shim #define HDMI_MPG_CON HDMI_CORE_BASE(0x0900) 3163ecd70b1SJoonyoung Shim #define HDMI_MPG_CHECK_SUM HDMI_CORE_BASE(0x091C) 3173ecd70b1SJoonyoung Shim #define HDMI_MPG_DATA(n) HDMI_CORE_BASE(0x0920 + 4 * (n)) 3183ecd70b1SJoonyoung Shim 3193ecd70b1SJoonyoung Shim #define HDMI_SPD_CON HDMI_CORE_BASE(0x0A00) 3203ecd70b1SJoonyoung Shim #define HDMI_SPD_HEADER0 HDMI_CORE_BASE(0x0A10) 3213ecd70b1SJoonyoung Shim #define HDMI_SPD_HEADER1 HDMI_CORE_BASE(0x0A14) 3223ecd70b1SJoonyoung Shim #define HDMI_SPD_HEADER2 HDMI_CORE_BASE(0x0A18) 3233ecd70b1SJoonyoung Shim #define HDMI_SPD_DATA(n) HDMI_CORE_BASE(0x0A20 + 4 * (n)) 3243ecd70b1SJoonyoung Shim 3253ecd70b1SJoonyoung Shim #define HDMI_GAMUT_CON HDMI_CORE_BASE(0x0B00) 3263ecd70b1SJoonyoung Shim #define HDMI_GAMUT_HEADER0 HDMI_CORE_BASE(0x0B10) 3273ecd70b1SJoonyoung Shim #define HDMI_GAMUT_HEADER1 HDMI_CORE_BASE(0x0B14) 3283ecd70b1SJoonyoung Shim #define HDMI_GAMUT_HEADER2 HDMI_CORE_BASE(0x0B18) 3293ecd70b1SJoonyoung Shim #define HDMI_GAMUT_METADATA(n) HDMI_CORE_BASE(0x0B20 + 4 * (n)) 3303ecd70b1SJoonyoung Shim 3313ecd70b1SJoonyoung Shim #define HDMI_VSI_CON HDMI_CORE_BASE(0x0C00) 3323ecd70b1SJoonyoung Shim #define HDMI_VSI_HEADER0 HDMI_CORE_BASE(0x0C10) 3333ecd70b1SJoonyoung Shim #define HDMI_VSI_HEADER1 HDMI_CORE_BASE(0x0C14) 3343ecd70b1SJoonyoung Shim #define HDMI_VSI_HEADER2 HDMI_CORE_BASE(0x0C18) 3353ecd70b1SJoonyoung Shim #define HDMI_VSI_DATA(n) HDMI_CORE_BASE(0x0C20 + 4 * (n)) 3363ecd70b1SJoonyoung Shim 3373ecd70b1SJoonyoung Shim #define HDMI_DC_CONTROL HDMI_CORE_BASE(0x0D00) 3383ecd70b1SJoonyoung Shim #define HDMI_VIDEO_PATTERN_GEN HDMI_CORE_BASE(0x0D04) 3393ecd70b1SJoonyoung Shim 3403ecd70b1SJoonyoung Shim #define HDMI_AN_SEED_SEL HDMI_CORE_BASE(0x0E48) 3413ecd70b1SJoonyoung Shim #define HDMI_AN_SEED_0 HDMI_CORE_BASE(0x0E58) 3423ecd70b1SJoonyoung Shim #define HDMI_AN_SEED_1 HDMI_CORE_BASE(0x0E5C) 3433ecd70b1SJoonyoung Shim #define HDMI_AN_SEED_2 HDMI_CORE_BASE(0x0E60) 3443ecd70b1SJoonyoung Shim #define HDMI_AN_SEED_3 HDMI_CORE_BASE(0x0E64) 3453ecd70b1SJoonyoung Shim 346a144c2e9SRahul Sharma /* AVI bit definition */ 347a144c2e9SRahul Sharma #define HDMI_AVI_CON_DO_NOT_TRANSMIT (0 << 1) 348a144c2e9SRahul Sharma #define HDMI_AVI_CON_EVERY_VSYNC (1 << 1) 349a144c2e9SRahul Sharma 350a144c2e9SRahul Sharma #define AVI_ACTIVE_FORMAT_VALID (1 << 4) 351a144c2e9SRahul Sharma #define AVI_UNDERSCANNED_DISPLAY_VALID (1 << 1) 352a144c2e9SRahul Sharma 353a144c2e9SRahul Sharma /* AUI bit definition */ 354a144c2e9SRahul Sharma #define HDMI_AUI_CON_NO_TRAN (0 << 0) 355a144c2e9SRahul Sharma 356a144c2e9SRahul Sharma /* VSI bit definition */ 357a144c2e9SRahul Sharma #define HDMI_VSI_CON_DO_NOT_TRANSMIT (0 << 0) 358a144c2e9SRahul Sharma 3593ecd70b1SJoonyoung Shim /* HDCP related registers */ 3603ecd70b1SJoonyoung Shim #define HDMI_HDCP_SHA1(n) HDMI_CORE_BASE(0x7000 + 4 * (n)) 3613ecd70b1SJoonyoung Shim #define HDMI_HDCP_KSV_LIST(n) HDMI_CORE_BASE(0x7050 + 4 * (n)) 3623ecd70b1SJoonyoung Shim 3633ecd70b1SJoonyoung Shim #define HDMI_HDCP_KSV_LIST_CON HDMI_CORE_BASE(0x7064) 3643ecd70b1SJoonyoung Shim #define HDMI_HDCP_SHA_RESULT HDMI_CORE_BASE(0x7070) 3653ecd70b1SJoonyoung Shim #define HDMI_HDCP_CTRL1 HDMI_CORE_BASE(0x7080) 3663ecd70b1SJoonyoung Shim #define HDMI_HDCP_CTRL2 HDMI_CORE_BASE(0x7084) 3673ecd70b1SJoonyoung Shim #define HDMI_HDCP_CHECK_RESULT HDMI_CORE_BASE(0x7090) 3683ecd70b1SJoonyoung Shim #define HDMI_HDCP_BKSV(n) HDMI_CORE_BASE(0x70A0 + 4 * (n)) 3693ecd70b1SJoonyoung Shim #define HDMI_HDCP_AKSV(n) HDMI_CORE_BASE(0x70C0 + 4 * (n)) 3703ecd70b1SJoonyoung Shim #define HDMI_HDCP_AN(n) HDMI_CORE_BASE(0x70E0 + 4 * (n)) 3713ecd70b1SJoonyoung Shim 3723ecd70b1SJoonyoung Shim #define HDMI_HDCP_BCAPS HDMI_CORE_BASE(0x7100) 3733ecd70b1SJoonyoung Shim #define HDMI_HDCP_BSTATUS_0 HDMI_CORE_BASE(0x7110) 3743ecd70b1SJoonyoung Shim #define HDMI_HDCP_BSTATUS_1 HDMI_CORE_BASE(0x7114) 3753ecd70b1SJoonyoung Shim #define HDMI_HDCP_RI_0 HDMI_CORE_BASE(0x7140) 3763ecd70b1SJoonyoung Shim #define HDMI_HDCP_RI_1 HDMI_CORE_BASE(0x7144) 3773ecd70b1SJoonyoung Shim #define HDMI_HDCP_I2C_INT HDMI_CORE_BASE(0x7180) 3783ecd70b1SJoonyoung Shim #define HDMI_HDCP_AN_INT HDMI_CORE_BASE(0x7190) 3793ecd70b1SJoonyoung Shim #define HDMI_HDCP_WDT_INT HDMI_CORE_BASE(0x71A0) 3803ecd70b1SJoonyoung Shim #define HDMI_HDCP_RI_INT HDMI_CORE_BASE(0x71B0) 3813ecd70b1SJoonyoung Shim #define HDMI_HDCP_RI_COMPARE_0 HDMI_CORE_BASE(0x71D0) 3823ecd70b1SJoonyoung Shim #define HDMI_HDCP_RI_COMPARE_1 HDMI_CORE_BASE(0x71D4) 3833ecd70b1SJoonyoung Shim #define HDMI_HDCP_FRAME_COUNT HDMI_CORE_BASE(0x71E0) 3843ecd70b1SJoonyoung Shim 3853ecd70b1SJoonyoung Shim #define HDMI_RGB_ROUND_EN HDMI_CORE_BASE(0xD500) 3863ecd70b1SJoonyoung Shim #define HDMI_VACT_SPACE_R_0 HDMI_CORE_BASE(0xD504) 3873ecd70b1SJoonyoung Shim #define HDMI_VACT_SPACE_R_1 HDMI_CORE_BASE(0xD508) 3883ecd70b1SJoonyoung Shim #define HDMI_VACT_SPACE_G_0 HDMI_CORE_BASE(0xD50C) 3893ecd70b1SJoonyoung Shim #define HDMI_VACT_SPACE_G_1 HDMI_CORE_BASE(0xD510) 3903ecd70b1SJoonyoung Shim #define HDMI_VACT_SPACE_B_0 HDMI_CORE_BASE(0xD514) 3913ecd70b1SJoonyoung Shim #define HDMI_VACT_SPACE_B_1 HDMI_CORE_BASE(0xD518) 3923ecd70b1SJoonyoung Shim 3933ecd70b1SJoonyoung Shim #define HDMI_BLUE_SCREEN_B_0 HDMI_CORE_BASE(0xD520) 3943ecd70b1SJoonyoung Shim #define HDMI_BLUE_SCREEN_B_1 HDMI_CORE_BASE(0xD524) 3953ecd70b1SJoonyoung Shim #define HDMI_BLUE_SCREEN_G_0 HDMI_CORE_BASE(0xD528) 3963ecd70b1SJoonyoung Shim #define HDMI_BLUE_SCREEN_G_1 HDMI_CORE_BASE(0xD52C) 3973ecd70b1SJoonyoung Shim #define HDMI_BLUE_SCREEN_R_0 HDMI_CORE_BASE(0xD530) 3983ecd70b1SJoonyoung Shim #define HDMI_BLUE_SCREEN_R_1 HDMI_CORE_BASE(0xD534) 3993ecd70b1SJoonyoung Shim 4003e148bafSSeung-Woo Kim /* HDMI I2S register */ 4013e148bafSSeung-Woo Kim #define HDMI_I2S_CLK_CON HDMI_I2S_BASE(0x000) 4023e148bafSSeung-Woo Kim #define HDMI_I2S_CON_1 HDMI_I2S_BASE(0x004) 4033e148bafSSeung-Woo Kim #define HDMI_I2S_CON_2 HDMI_I2S_BASE(0x008) 4043e148bafSSeung-Woo Kim #define HDMI_I2S_PIN_SEL_0 HDMI_I2S_BASE(0x00c) 4053e148bafSSeung-Woo Kim #define HDMI_I2S_PIN_SEL_1 HDMI_I2S_BASE(0x010) 4063e148bafSSeung-Woo Kim #define HDMI_I2S_PIN_SEL_2 HDMI_I2S_BASE(0x014) 4073e148bafSSeung-Woo Kim #define HDMI_I2S_PIN_SEL_3 HDMI_I2S_BASE(0x018) 4083e148bafSSeung-Woo Kim #define HDMI_I2S_DSD_CON HDMI_I2S_BASE(0x01c) 4093e148bafSSeung-Woo Kim #define HDMI_I2S_MUX_CON HDMI_I2S_BASE(0x020) 4103e148bafSSeung-Woo Kim #define HDMI_I2S_CH_ST_CON HDMI_I2S_BASE(0x024) 4113e148bafSSeung-Woo Kim #define HDMI_I2S_CH_ST_0 HDMI_I2S_BASE(0x028) 4123e148bafSSeung-Woo Kim #define HDMI_I2S_CH_ST_1 HDMI_I2S_BASE(0x02c) 4133e148bafSSeung-Woo Kim #define HDMI_I2S_CH_ST_2 HDMI_I2S_BASE(0x030) 4143e148bafSSeung-Woo Kim #define HDMI_I2S_CH_ST_3 HDMI_I2S_BASE(0x034) 4153e148bafSSeung-Woo Kim #define HDMI_I2S_CH_ST_4 HDMI_I2S_BASE(0x038) 4163e148bafSSeung-Woo Kim #define HDMI_I2S_CH_ST_SH_0 HDMI_I2S_BASE(0x03c) 4173e148bafSSeung-Woo Kim #define HDMI_I2S_CH_ST_SH_1 HDMI_I2S_BASE(0x040) 4183e148bafSSeung-Woo Kim #define HDMI_I2S_CH_ST_SH_2 HDMI_I2S_BASE(0x044) 4193e148bafSSeung-Woo Kim #define HDMI_I2S_CH_ST_SH_3 HDMI_I2S_BASE(0x048) 4203e148bafSSeung-Woo Kim #define HDMI_I2S_CH_ST_SH_4 HDMI_I2S_BASE(0x04c) 4213e148bafSSeung-Woo Kim #define HDMI_I2S_MUX_CH HDMI_I2S_BASE(0x054) 4223e148bafSSeung-Woo Kim #define HDMI_I2S_MUX_CUV HDMI_I2S_BASE(0x058) 4233e148bafSSeung-Woo Kim 4243e148bafSSeung-Woo Kim /* I2S bit definition */ 4253e148bafSSeung-Woo Kim 4263e148bafSSeung-Woo Kim /* I2S_CLK_CON */ 4273e148bafSSeung-Woo Kim #define HDMI_I2S_CLK_DIS (0) 4283e148bafSSeung-Woo Kim #define HDMI_I2S_CLK_EN (1) 4293e148bafSSeung-Woo Kim 4303e148bafSSeung-Woo Kim /* I2S_CON_1 */ 4313e148bafSSeung-Woo Kim #define HDMI_I2S_SCLK_FALLING_EDGE (0 << 1) 4323e148bafSSeung-Woo Kim #define HDMI_I2S_SCLK_RISING_EDGE (1 << 1) 4333e148bafSSeung-Woo Kim #define HDMI_I2S_L_CH_LOW_POL (0) 4343e148bafSSeung-Woo Kim #define HDMI_I2S_L_CH_HIGH_POL (1) 4353e148bafSSeung-Woo Kim 4363e148bafSSeung-Woo Kim /* I2S_CON_2 */ 4373e148bafSSeung-Woo Kim #define HDMI_I2S_MSB_FIRST_MODE (0 << 6) 4383e148bafSSeung-Woo Kim #define HDMI_I2S_LSB_FIRST_MODE (1 << 6) 4393e148bafSSeung-Woo Kim #define HDMI_I2S_BIT_CH_32FS (0 << 4) 4403e148bafSSeung-Woo Kim #define HDMI_I2S_BIT_CH_48FS (1 << 4) 4413e148bafSSeung-Woo Kim #define HDMI_I2S_BIT_CH_RESERVED (2 << 4) 4423e148bafSSeung-Woo Kim #define HDMI_I2S_SDATA_16BIT (1 << 2) 4433e148bafSSeung-Woo Kim #define HDMI_I2S_SDATA_20BIT (2 << 2) 4443e148bafSSeung-Woo Kim #define HDMI_I2S_SDATA_24BIT (3 << 2) 4453e148bafSSeung-Woo Kim #define HDMI_I2S_BASIC_FORMAT (0) 4463e148bafSSeung-Woo Kim #define HDMI_I2S_L_JUST_FORMAT (2) 4473e148bafSSeung-Woo Kim #define HDMI_I2S_R_JUST_FORMAT (3) 4483e148bafSSeung-Woo Kim #define HDMI_I2S_CON_2_CLR (~(0xFF)) 4493e148bafSSeung-Woo Kim #define HDMI_I2S_SET_BIT_CH(x) (((x) & 0x7) << 4) 4503e148bafSSeung-Woo Kim #define HDMI_I2S_SET_SDATA_BIT(x) (((x) & 0x7) << 2) 4513e148bafSSeung-Woo Kim 4523e148bafSSeung-Woo Kim /* I2S_PIN_SEL_0 */ 4533e148bafSSeung-Woo Kim #define HDMI_I2S_SEL_SCLK(x) (((x) & 0x7) << 4) 4543e148bafSSeung-Woo Kim #define HDMI_I2S_SEL_LRCK(x) ((x) & 0x7) 4553e148bafSSeung-Woo Kim 4563e148bafSSeung-Woo Kim /* I2S_PIN_SEL_1 */ 4573e148bafSSeung-Woo Kim #define HDMI_I2S_SEL_SDATA1(x) (((x) & 0x7) << 4) 4583e148bafSSeung-Woo Kim #define HDMI_I2S_SEL_SDATA2(x) ((x) & 0x7) 4593e148bafSSeung-Woo Kim 4603e148bafSSeung-Woo Kim /* I2S_PIN_SEL_2 */ 4613e148bafSSeung-Woo Kim #define HDMI_I2S_SEL_SDATA3(x) (((x) & 0x7) << 4) 4623e148bafSSeung-Woo Kim #define HDMI_I2S_SEL_SDATA2(x) ((x) & 0x7) 4633e148bafSSeung-Woo Kim 4643e148bafSSeung-Woo Kim /* I2S_PIN_SEL_3 */ 4653e148bafSSeung-Woo Kim #define HDMI_I2S_SEL_DSD(x) ((x) & 0x7) 4663e148bafSSeung-Woo Kim 4673e148bafSSeung-Woo Kim /* I2S_DSD_CON */ 4683e148bafSSeung-Woo Kim #define HDMI_I2S_DSD_CLK_RI_EDGE (1 << 1) 4693e148bafSSeung-Woo Kim #define HDMI_I2S_DSD_CLK_FA_EDGE (0 << 1) 4703e148bafSSeung-Woo Kim #define HDMI_I2S_DSD_ENABLE (1) 4713e148bafSSeung-Woo Kim #define HDMI_I2S_DSD_DISABLE (0) 4723e148bafSSeung-Woo Kim 4733e148bafSSeung-Woo Kim /* I2S_MUX_CON */ 4743e148bafSSeung-Woo Kim #define HDMI_I2S_NOISE_FILTER_ZERO (0 << 5) 4753e148bafSSeung-Woo Kim #define HDMI_I2S_NOISE_FILTER_2_STAGE (1 << 5) 4763e148bafSSeung-Woo Kim #define HDMI_I2S_NOISE_FILTER_3_STAGE (2 << 5) 4773e148bafSSeung-Woo Kim #define HDMI_I2S_NOISE_FILTER_4_STAGE (3 << 5) 4783e148bafSSeung-Woo Kim #define HDMI_I2S_NOISE_FILTER_5_STAGE (4 << 5) 4793e148bafSSeung-Woo Kim #define HDMI_I2S_IN_DISABLE (1 << 4) 4803e148bafSSeung-Woo Kim #define HDMI_I2S_IN_ENABLE (0 << 4) 4813e148bafSSeung-Woo Kim #define HDMI_I2S_AUD_SPDIF (0 << 2) 4823e148bafSSeung-Woo Kim #define HDMI_I2S_AUD_I2S (1 << 2) 4833e148bafSSeung-Woo Kim #define HDMI_I2S_AUD_DSD (2 << 2) 4843e148bafSSeung-Woo Kim #define HDMI_I2S_CUV_SPDIF_ENABLE (0 << 1) 4853e148bafSSeung-Woo Kim #define HDMI_I2S_CUV_I2S_ENABLE (1 << 1) 4863e148bafSSeung-Woo Kim #define HDMI_I2S_MUX_DISABLE (0) 4873e148bafSSeung-Woo Kim #define HDMI_I2S_MUX_ENABLE (1) 4883e148bafSSeung-Woo Kim #define HDMI_I2S_MUX_CON_CLR (~(0xFF)) 4893e148bafSSeung-Woo Kim 4903e148bafSSeung-Woo Kim /* I2S_CH_ST_CON */ 4913e148bafSSeung-Woo Kim #define HDMI_I2S_CH_STATUS_RELOAD (1) 4923e148bafSSeung-Woo Kim #define HDMI_I2S_CH_ST_CON_CLR (~(1)) 4933e148bafSSeung-Woo Kim 4943e148bafSSeung-Woo Kim /* I2S_CH_ST_0 / I2S_CH_ST_SH_0 */ 4953e148bafSSeung-Woo Kim #define HDMI_I2S_CH_STATUS_MODE_0 (0 << 6) 4963e148bafSSeung-Woo Kim #define HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH (0 << 3) 4973e148bafSSeung-Woo Kim #define HDMI_I2S_2AUD_CH_WITH_PREEMPH (1 << 3) 4983e148bafSSeung-Woo Kim #define HDMI_I2S_DEFAULT_EMPHASIS (0 << 3) 4993e148bafSSeung-Woo Kim #define HDMI_I2S_COPYRIGHT (0 << 2) 5003e148bafSSeung-Woo Kim #define HDMI_I2S_NO_COPYRIGHT (1 << 2) 5013e148bafSSeung-Woo Kim #define HDMI_I2S_LINEAR_PCM (0 << 1) 5023e148bafSSeung-Woo Kim #define HDMI_I2S_NO_LINEAR_PCM (1 << 1) 5033e148bafSSeung-Woo Kim #define HDMI_I2S_CONSUMER_FORMAT (0) 5043e148bafSSeung-Woo Kim #define HDMI_I2S_PROF_FORMAT (1) 5053e148bafSSeung-Woo Kim #define HDMI_I2S_CH_ST_0_CLR (~(0xFF)) 5063e148bafSSeung-Woo Kim 5073e148bafSSeung-Woo Kim /* I2S_CH_ST_1 / I2S_CH_ST_SH_1 */ 5083e148bafSSeung-Woo Kim #define HDMI_I2S_CD_PLAYER (0x00) 5093e148bafSSeung-Woo Kim #define HDMI_I2S_DAT_PLAYER (0x03) 5103e148bafSSeung-Woo Kim #define HDMI_I2S_DCC_PLAYER (0x43) 5113e148bafSSeung-Woo Kim #define HDMI_I2S_MINI_DISC_PLAYER (0x49) 5123e148bafSSeung-Woo Kim 5133e148bafSSeung-Woo Kim /* I2S_CH_ST_2 / I2S_CH_ST_SH_2 */ 5143e148bafSSeung-Woo Kim #define HDMI_I2S_CHANNEL_NUM_MASK (0xF << 4) 5153e148bafSSeung-Woo Kim #define HDMI_I2S_SOURCE_NUM_MASK (0xF) 5163e148bafSSeung-Woo Kim #define HDMI_I2S_SET_CHANNEL_NUM(x) (((x) & (0xF)) << 4) 5173e148bafSSeung-Woo Kim #define HDMI_I2S_SET_SOURCE_NUM(x) ((x) & (0xF)) 5183e148bafSSeung-Woo Kim 5193e148bafSSeung-Woo Kim /* I2S_CH_ST_3 / I2S_CH_ST_SH_3 */ 5203e148bafSSeung-Woo Kim #define HDMI_I2S_CLK_ACCUR_LEVEL_1 (1 << 4) 5213e148bafSSeung-Woo Kim #define HDMI_I2S_CLK_ACCUR_LEVEL_2 (0 << 4) 5223e148bafSSeung-Woo Kim #define HDMI_I2S_CLK_ACCUR_LEVEL_3 (2 << 4) 5233e148bafSSeung-Woo Kim #define HDMI_I2S_SMP_FREQ_44_1 (0x0) 5243e148bafSSeung-Woo Kim #define HDMI_I2S_SMP_FREQ_48 (0x2) 5253e148bafSSeung-Woo Kim #define HDMI_I2S_SMP_FREQ_32 (0x3) 5263e148bafSSeung-Woo Kim #define HDMI_I2S_SMP_FREQ_96 (0xA) 5273e148bafSSeung-Woo Kim #define HDMI_I2S_SET_SMP_FREQ(x) ((x) & (0xF)) 5283e148bafSSeung-Woo Kim 5293e148bafSSeung-Woo Kim /* I2S_CH_ST_4 / I2S_CH_ST_SH_4 */ 5303e148bafSSeung-Woo Kim #define HDMI_I2S_ORG_SMP_FREQ_44_1 (0xF << 4) 5313e148bafSSeung-Woo Kim #define HDMI_I2S_ORG_SMP_FREQ_88_2 (0x7 << 4) 5323e148bafSSeung-Woo Kim #define HDMI_I2S_ORG_SMP_FREQ_22_05 (0xB << 4) 5333e148bafSSeung-Woo Kim #define HDMI_I2S_ORG_SMP_FREQ_176_4 (0x3 << 4) 5343e148bafSSeung-Woo Kim #define HDMI_I2S_WORD_LEN_NOT_DEFINE (0x0 << 1) 5353e148bafSSeung-Woo Kim #define HDMI_I2S_WORD_LEN_MAX24_20BITS (0x1 << 1) 5363e148bafSSeung-Woo Kim #define HDMI_I2S_WORD_LEN_MAX24_22BITS (0x2 << 1) 5373e148bafSSeung-Woo Kim #define HDMI_I2S_WORD_LEN_MAX24_23BITS (0x4 << 1) 5383e148bafSSeung-Woo Kim #define HDMI_I2S_WORD_LEN_MAX24_24BITS (0x5 << 1) 5393e148bafSSeung-Woo Kim #define HDMI_I2S_WORD_LEN_MAX24_21BITS (0x6 << 1) 5403e148bafSSeung-Woo Kim #define HDMI_I2S_WORD_LEN_MAX20_16BITS (0x1 << 1) 5413e148bafSSeung-Woo Kim #define HDMI_I2S_WORD_LEN_MAX20_18BITS (0x2 << 1) 5423e148bafSSeung-Woo Kim #define HDMI_I2S_WORD_LEN_MAX20_19BITS (0x4 << 1) 5433e148bafSSeung-Woo Kim #define HDMI_I2S_WORD_LEN_MAX20_20BITS (0x5 << 1) 5443e148bafSSeung-Woo Kim #define HDMI_I2S_WORD_LEN_MAX20_17BITS (0x6 << 1) 5453e148bafSSeung-Woo Kim #define HDMI_I2S_WORD_LEN_MAX_24BITS (1) 5463e148bafSSeung-Woo Kim #define HDMI_I2S_WORD_LEN_MAX_20BITS (0) 5473e148bafSSeung-Woo Kim 5483e148bafSSeung-Woo Kim /* I2S_MUX_CH */ 5493e148bafSSeung-Woo Kim #define HDMI_I2S_CH3_R_EN (1 << 7) 5503e148bafSSeung-Woo Kim #define HDMI_I2S_CH3_L_EN (1 << 6) 5513e148bafSSeung-Woo Kim #define HDMI_I2S_CH3_EN (3 << 6) 5523e148bafSSeung-Woo Kim #define HDMI_I2S_CH2_R_EN (1 << 5) 5533e148bafSSeung-Woo Kim #define HDMI_I2S_CH2_L_EN (1 << 4) 5543e148bafSSeung-Woo Kim #define HDMI_I2S_CH2_EN (3 << 4) 5553e148bafSSeung-Woo Kim #define HDMI_I2S_CH1_R_EN (1 << 3) 5563e148bafSSeung-Woo Kim #define HDMI_I2S_CH1_L_EN (1 << 2) 5573e148bafSSeung-Woo Kim #define HDMI_I2S_CH1_EN (3 << 2) 5583e148bafSSeung-Woo Kim #define HDMI_I2S_CH0_R_EN (1 << 1) 5593e148bafSSeung-Woo Kim #define HDMI_I2S_CH0_L_EN (1) 5603e148bafSSeung-Woo Kim #define HDMI_I2S_CH0_EN (3) 5613e148bafSSeung-Woo Kim #define HDMI_I2S_CH_ALL_EN (0xFF) 5623e148bafSSeung-Woo Kim #define HDMI_I2S_MUX_CH_CLR (~HDMI_I2S_CH_ALL_EN) 5633e148bafSSeung-Woo Kim 5643e148bafSSeung-Woo Kim /* I2S_MUX_CUV */ 5653e148bafSSeung-Woo Kim #define HDMI_I2S_CUV_R_EN (1 << 1) 5663e148bafSSeung-Woo Kim #define HDMI_I2S_CUV_L_EN (1) 5673e148bafSSeung-Woo Kim #define HDMI_I2S_CUV_RL_EN (0x03) 5683e148bafSSeung-Woo Kim 5693e148bafSSeung-Woo Kim /* I2S_CUV_L_R */ 5703e148bafSSeung-Woo Kim #define HDMI_I2S_CUV_R_DATA_MASK (0x7 << 4) 5713e148bafSSeung-Woo Kim #define HDMI_I2S_CUV_L_DATA_MASK (0x7) 5723e148bafSSeung-Woo Kim 5733ecd70b1SJoonyoung Shim /* Timing generator registers */ 5743ecd70b1SJoonyoung Shim /* TG configure/status registers */ 5753ecd70b1SJoonyoung Shim #define HDMI_TG_VACT_ST3_L HDMI_TG_BASE(0x0068) 5763ecd70b1SJoonyoung Shim #define HDMI_TG_VACT_ST3_H HDMI_TG_BASE(0x006c) 5773ecd70b1SJoonyoung Shim #define HDMI_TG_VACT_ST4_L HDMI_TG_BASE(0x0070) 5783ecd70b1SJoonyoung Shim #define HDMI_TG_VACT_ST4_H HDMI_TG_BASE(0x0074) 5793ecd70b1SJoonyoung Shim #define HDMI_TG_3D HDMI_TG_BASE(0x00F0) 5803ecd70b1SJoonyoung Shim 581d5e9ca4cSRahul Sharma /* HDMI PHY Registers Offsets*/ 5826a296e20SShirish S #define HDMIPHY_POWER (0x74 >> 2) 5836a296e20SShirish S #define HDMIPHY_MODE_SET_DONE (0x7c >> 2) 5846a296e20SShirish S 5856a296e20SShirish S /* HDMI PHY Values */ 5866a296e20SShirish S #define HDMI_PHY_POWER_ON 0x80 5876a296e20SShirish S #define HDMI_PHY_POWER_OFF 0xff 588d5e9ca4cSRahul Sharma 589d5e9ca4cSRahul Sharma /* HDMI PHY Values */ 590d5e9ca4cSRahul Sharma #define HDMI_PHY_DISABLE_MODE_SET 0x80 591d5e9ca4cSRahul Sharma #define HDMI_PHY_ENABLE_MODE_SET 0x00 592d5e9ca4cSRahul Sharma 593049d34e9SRahul Sharma /* PMU Registers for PHY */ 594049d34e9SRahul Sharma #define PMU_HDMI_PHY_CONTROL 0x700 595049d34e9SRahul Sharma #define PMU_HDMI_PHY_ENABLE_BIT BIT(0) 596049d34e9SRahul Sharma 597d8408326SSeung-Woo Kim #endif /* SAMSUNG_REGS_HDMI_H */ 598