1 /* 2 * Copyright (C) 2011 Samsung Electronics Co.Ltd 3 * Authors: 4 * Seung-Woo Kim <sw0312.kim@samsung.com> 5 * Inki Dae <inki.dae@samsung.com> 6 * Joonyoung Shim <jy0922.shim@samsung.com> 7 * 8 * Based on drivers/media/video/s5p-tv/mixer_reg.c 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 * 15 */ 16 17 #include <drm/drmP.h> 18 19 #include "regs-mixer.h" 20 #include "regs-vp.h" 21 22 #include <linux/kernel.h> 23 #include <linux/ktime.h> 24 #include <linux/spinlock.h> 25 #include <linux/wait.h> 26 #include <linux/i2c.h> 27 #include <linux/platform_device.h> 28 #include <linux/interrupt.h> 29 #include <linux/irq.h> 30 #include <linux/delay.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/clk.h> 33 #include <linux/regulator/consumer.h> 34 #include <linux/of.h> 35 #include <linux/of_device.h> 36 #include <linux/component.h> 37 38 #include <drm/exynos_drm.h> 39 40 #include "exynos_drm_drv.h" 41 #include "exynos_drm_crtc.h" 42 #include "exynos_drm_fb.h" 43 #include "exynos_drm_plane.h" 44 45 #define MIXER_WIN_NR 3 46 #define VP_DEFAULT_WIN 2 47 48 /* 49 * Mixer color space conversion coefficient triplet. 50 * Used for CSC from RGB to YCbCr. 51 * Each coefficient is a 10-bit fixed point number with 52 * sign and no integer part, i.e. 53 * [0:8] = fractional part (representing a value y = x / 2^9) 54 * [9] = sign 55 * Negative values are encoded with two's complement. 56 */ 57 #define MXR_CSC_C(x) ((int)((x) * 512.0) & 0x3ff) 58 #define MXR_CSC_CT(a0, a1, a2) \ 59 ((MXR_CSC_C(a0) << 20) | (MXR_CSC_C(a1) << 10) | (MXR_CSC_C(a2) << 0)) 60 61 /* YCbCr value, used for mixer background color configuration. */ 62 #define MXR_YCBCR_VAL(y, cb, cr) (((y) << 16) | ((cb) << 8) | ((cr) << 0)) 63 64 /* The pixelformats that are natively supported by the mixer. */ 65 #define MXR_FORMAT_RGB565 4 66 #define MXR_FORMAT_ARGB1555 5 67 #define MXR_FORMAT_ARGB4444 6 68 #define MXR_FORMAT_ARGB8888 7 69 70 enum mixer_version_id { 71 MXR_VER_0_0_0_16, 72 MXR_VER_16_0_33_0, 73 MXR_VER_128_0_0_184, 74 }; 75 76 enum mixer_flag_bits { 77 MXR_BIT_POWERED, 78 MXR_BIT_VSYNC, 79 MXR_BIT_INTERLACE, 80 MXR_BIT_VP_ENABLED, 81 MXR_BIT_HAS_SCLK, 82 }; 83 84 static const uint32_t mixer_formats[] = { 85 DRM_FORMAT_XRGB4444, 86 DRM_FORMAT_ARGB4444, 87 DRM_FORMAT_XRGB1555, 88 DRM_FORMAT_ARGB1555, 89 DRM_FORMAT_RGB565, 90 DRM_FORMAT_XRGB8888, 91 DRM_FORMAT_ARGB8888, 92 }; 93 94 static const uint32_t vp_formats[] = { 95 DRM_FORMAT_NV12, 96 DRM_FORMAT_NV21, 97 }; 98 99 struct mixer_context { 100 struct platform_device *pdev; 101 struct device *dev; 102 struct drm_device *drm_dev; 103 struct exynos_drm_crtc *crtc; 104 struct exynos_drm_plane planes[MIXER_WIN_NR]; 105 unsigned long flags; 106 107 int irq; 108 void __iomem *mixer_regs; 109 void __iomem *vp_regs; 110 spinlock_t reg_slock; 111 struct clk *mixer; 112 struct clk *vp; 113 struct clk *hdmi; 114 struct clk *sclk_mixer; 115 struct clk *sclk_hdmi; 116 struct clk *mout_mixer; 117 enum mixer_version_id mxr_ver; 118 int scan_value; 119 }; 120 121 struct mixer_drv_data { 122 enum mixer_version_id version; 123 bool is_vp_enabled; 124 bool has_sclk; 125 }; 126 127 static const struct exynos_drm_plane_config plane_configs[MIXER_WIN_NR] = { 128 { 129 .zpos = 0, 130 .type = DRM_PLANE_TYPE_PRIMARY, 131 .pixel_formats = mixer_formats, 132 .num_pixel_formats = ARRAY_SIZE(mixer_formats), 133 .capabilities = EXYNOS_DRM_PLANE_CAP_DOUBLE | 134 EXYNOS_DRM_PLANE_CAP_ZPOS | 135 EXYNOS_DRM_PLANE_CAP_PIX_BLEND | 136 EXYNOS_DRM_PLANE_CAP_WIN_BLEND, 137 }, { 138 .zpos = 1, 139 .type = DRM_PLANE_TYPE_CURSOR, 140 .pixel_formats = mixer_formats, 141 .num_pixel_formats = ARRAY_SIZE(mixer_formats), 142 .capabilities = EXYNOS_DRM_PLANE_CAP_DOUBLE | 143 EXYNOS_DRM_PLANE_CAP_ZPOS | 144 EXYNOS_DRM_PLANE_CAP_PIX_BLEND | 145 EXYNOS_DRM_PLANE_CAP_WIN_BLEND, 146 }, { 147 .zpos = 2, 148 .type = DRM_PLANE_TYPE_OVERLAY, 149 .pixel_formats = vp_formats, 150 .num_pixel_formats = ARRAY_SIZE(vp_formats), 151 .capabilities = EXYNOS_DRM_PLANE_CAP_SCALE | 152 EXYNOS_DRM_PLANE_CAP_ZPOS | 153 EXYNOS_DRM_PLANE_CAP_TILE | 154 EXYNOS_DRM_PLANE_CAP_WIN_BLEND, 155 }, 156 }; 157 158 static const u8 filter_y_horiz_tap8[] = { 159 0, -1, -1, -1, -1, -1, -1, -1, 160 -1, -1, -1, -1, -1, 0, 0, 0, 161 0, 2, 4, 5, 6, 6, 6, 6, 162 6, 5, 5, 4, 3, 2, 1, 1, 163 0, -6, -12, -16, -18, -20, -21, -20, 164 -20, -18, -16, -13, -10, -8, -5, -2, 165 127, 126, 125, 121, 114, 107, 99, 89, 166 79, 68, 57, 46, 35, 25, 16, 8, 167 }; 168 169 static const u8 filter_y_vert_tap4[] = { 170 0, -3, -6, -8, -8, -8, -8, -7, 171 -6, -5, -4, -3, -2, -1, -1, 0, 172 127, 126, 124, 118, 111, 102, 92, 81, 173 70, 59, 48, 37, 27, 19, 11, 5, 174 0, 5, 11, 19, 27, 37, 48, 59, 175 70, 81, 92, 102, 111, 118, 124, 126, 176 0, 0, -1, -1, -2, -3, -4, -5, 177 -6, -7, -8, -8, -8, -8, -6, -3, 178 }; 179 180 static const u8 filter_cr_horiz_tap4[] = { 181 0, -3, -6, -8, -8, -8, -8, -7, 182 -6, -5, -4, -3, -2, -1, -1, 0, 183 127, 126, 124, 118, 111, 102, 92, 81, 184 70, 59, 48, 37, 27, 19, 11, 5, 185 }; 186 187 static inline u32 vp_reg_read(struct mixer_context *ctx, u32 reg_id) 188 { 189 return readl(ctx->vp_regs + reg_id); 190 } 191 192 static inline void vp_reg_write(struct mixer_context *ctx, u32 reg_id, 193 u32 val) 194 { 195 writel(val, ctx->vp_regs + reg_id); 196 } 197 198 static inline void vp_reg_writemask(struct mixer_context *ctx, u32 reg_id, 199 u32 val, u32 mask) 200 { 201 u32 old = vp_reg_read(ctx, reg_id); 202 203 val = (val & mask) | (old & ~mask); 204 writel(val, ctx->vp_regs + reg_id); 205 } 206 207 static inline u32 mixer_reg_read(struct mixer_context *ctx, u32 reg_id) 208 { 209 return readl(ctx->mixer_regs + reg_id); 210 } 211 212 static inline void mixer_reg_write(struct mixer_context *ctx, u32 reg_id, 213 u32 val) 214 { 215 writel(val, ctx->mixer_regs + reg_id); 216 } 217 218 static inline void mixer_reg_writemask(struct mixer_context *ctx, 219 u32 reg_id, u32 val, u32 mask) 220 { 221 u32 old = mixer_reg_read(ctx, reg_id); 222 223 val = (val & mask) | (old & ~mask); 224 writel(val, ctx->mixer_regs + reg_id); 225 } 226 227 static void mixer_regs_dump(struct mixer_context *ctx) 228 { 229 #define DUMPREG(reg_id) \ 230 do { \ 231 DRM_DEBUG_KMS(#reg_id " = %08x\n", \ 232 (u32)readl(ctx->mixer_regs + reg_id)); \ 233 } while (0) 234 235 DUMPREG(MXR_STATUS); 236 DUMPREG(MXR_CFG); 237 DUMPREG(MXR_INT_EN); 238 DUMPREG(MXR_INT_STATUS); 239 240 DUMPREG(MXR_LAYER_CFG); 241 DUMPREG(MXR_VIDEO_CFG); 242 243 DUMPREG(MXR_GRAPHIC0_CFG); 244 DUMPREG(MXR_GRAPHIC0_BASE); 245 DUMPREG(MXR_GRAPHIC0_SPAN); 246 DUMPREG(MXR_GRAPHIC0_WH); 247 DUMPREG(MXR_GRAPHIC0_SXY); 248 DUMPREG(MXR_GRAPHIC0_DXY); 249 250 DUMPREG(MXR_GRAPHIC1_CFG); 251 DUMPREG(MXR_GRAPHIC1_BASE); 252 DUMPREG(MXR_GRAPHIC1_SPAN); 253 DUMPREG(MXR_GRAPHIC1_WH); 254 DUMPREG(MXR_GRAPHIC1_SXY); 255 DUMPREG(MXR_GRAPHIC1_DXY); 256 #undef DUMPREG 257 } 258 259 static void vp_regs_dump(struct mixer_context *ctx) 260 { 261 #define DUMPREG(reg_id) \ 262 do { \ 263 DRM_DEBUG_KMS(#reg_id " = %08x\n", \ 264 (u32) readl(ctx->vp_regs + reg_id)); \ 265 } while (0) 266 267 DUMPREG(VP_ENABLE); 268 DUMPREG(VP_SRESET); 269 DUMPREG(VP_SHADOW_UPDATE); 270 DUMPREG(VP_FIELD_ID); 271 DUMPREG(VP_MODE); 272 DUMPREG(VP_IMG_SIZE_Y); 273 DUMPREG(VP_IMG_SIZE_C); 274 DUMPREG(VP_PER_RATE_CTRL); 275 DUMPREG(VP_TOP_Y_PTR); 276 DUMPREG(VP_BOT_Y_PTR); 277 DUMPREG(VP_TOP_C_PTR); 278 DUMPREG(VP_BOT_C_PTR); 279 DUMPREG(VP_ENDIAN_MODE); 280 DUMPREG(VP_SRC_H_POSITION); 281 DUMPREG(VP_SRC_V_POSITION); 282 DUMPREG(VP_SRC_WIDTH); 283 DUMPREG(VP_SRC_HEIGHT); 284 DUMPREG(VP_DST_H_POSITION); 285 DUMPREG(VP_DST_V_POSITION); 286 DUMPREG(VP_DST_WIDTH); 287 DUMPREG(VP_DST_HEIGHT); 288 DUMPREG(VP_H_RATIO); 289 DUMPREG(VP_V_RATIO); 290 291 #undef DUMPREG 292 } 293 294 static inline void vp_filter_set(struct mixer_context *ctx, 295 int reg_id, const u8 *data, unsigned int size) 296 { 297 /* assure 4-byte align */ 298 BUG_ON(size & 3); 299 for (; size; size -= 4, reg_id += 4, data += 4) { 300 u32 val = (data[0] << 24) | (data[1] << 16) | 301 (data[2] << 8) | data[3]; 302 vp_reg_write(ctx, reg_id, val); 303 } 304 } 305 306 static void vp_default_filter(struct mixer_context *ctx) 307 { 308 vp_filter_set(ctx, VP_POLY8_Y0_LL, 309 filter_y_horiz_tap8, sizeof(filter_y_horiz_tap8)); 310 vp_filter_set(ctx, VP_POLY4_Y0_LL, 311 filter_y_vert_tap4, sizeof(filter_y_vert_tap4)); 312 vp_filter_set(ctx, VP_POLY4_C0_LL, 313 filter_cr_horiz_tap4, sizeof(filter_cr_horiz_tap4)); 314 } 315 316 static void mixer_cfg_gfx_blend(struct mixer_context *ctx, unsigned int win, 317 unsigned int pixel_alpha, unsigned int alpha) 318 { 319 u32 win_alpha = alpha >> 8; 320 u32 val; 321 322 val = MXR_GRP_CFG_COLOR_KEY_DISABLE; /* no blank key */ 323 switch (pixel_alpha) { 324 case DRM_MODE_BLEND_PIXEL_NONE: 325 break; 326 case DRM_MODE_BLEND_COVERAGE: 327 val |= MXR_GRP_CFG_PIXEL_BLEND_EN; 328 break; 329 case DRM_MODE_BLEND_PREMULTI: 330 default: 331 val |= MXR_GRP_CFG_BLEND_PRE_MUL; 332 val |= MXR_GRP_CFG_PIXEL_BLEND_EN; 333 break; 334 } 335 336 if (alpha != DRM_BLEND_ALPHA_OPAQUE) { 337 val |= MXR_GRP_CFG_WIN_BLEND_EN; 338 val |= win_alpha; 339 } 340 mixer_reg_writemask(ctx, MXR_GRAPHIC_CFG(win), 341 val, MXR_GRP_CFG_MISC_MASK); 342 } 343 344 static void mixer_cfg_vp_blend(struct mixer_context *ctx, unsigned int alpha) 345 { 346 u32 win_alpha = alpha >> 8; 347 u32 val = 0; 348 349 if (alpha != DRM_BLEND_ALPHA_OPAQUE) { 350 val |= MXR_VID_CFG_BLEND_EN; 351 val |= win_alpha; 352 } 353 mixer_reg_write(ctx, MXR_VIDEO_CFG, val); 354 } 355 356 static bool mixer_is_synced(struct mixer_context *ctx) 357 { 358 u32 base, shadow; 359 360 if (ctx->mxr_ver == MXR_VER_16_0_33_0 || 361 ctx->mxr_ver == MXR_VER_128_0_0_184) 362 return !(mixer_reg_read(ctx, MXR_CFG) & 363 MXR_CFG_LAYER_UPDATE_COUNT_MASK); 364 365 if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags) && 366 vp_reg_read(ctx, VP_SHADOW_UPDATE)) 367 return false; 368 369 base = mixer_reg_read(ctx, MXR_CFG); 370 shadow = mixer_reg_read(ctx, MXR_CFG_S); 371 if (base != shadow) 372 return false; 373 374 base = mixer_reg_read(ctx, MXR_GRAPHIC_BASE(0)); 375 shadow = mixer_reg_read(ctx, MXR_GRAPHIC_BASE_S(0)); 376 if (base != shadow) 377 return false; 378 379 base = mixer_reg_read(ctx, MXR_GRAPHIC_BASE(1)); 380 shadow = mixer_reg_read(ctx, MXR_GRAPHIC_BASE_S(1)); 381 if (base != shadow) 382 return false; 383 384 return true; 385 } 386 387 static int mixer_wait_for_sync(struct mixer_context *ctx) 388 { 389 ktime_t timeout = ktime_add_us(ktime_get(), 100000); 390 391 while (!mixer_is_synced(ctx)) { 392 usleep_range(1000, 2000); 393 if (ktime_compare(ktime_get(), timeout) > 0) 394 return -ETIMEDOUT; 395 } 396 return 0; 397 } 398 399 static void mixer_disable_sync(struct mixer_context *ctx) 400 { 401 mixer_reg_writemask(ctx, MXR_STATUS, 0, MXR_STATUS_SYNC_ENABLE); 402 } 403 404 static void mixer_enable_sync(struct mixer_context *ctx) 405 { 406 if (ctx->mxr_ver == MXR_VER_16_0_33_0 || 407 ctx->mxr_ver == MXR_VER_128_0_0_184) 408 mixer_reg_writemask(ctx, MXR_CFG, ~0, MXR_CFG_LAYER_UPDATE); 409 mixer_reg_writemask(ctx, MXR_STATUS, ~0, MXR_STATUS_SYNC_ENABLE); 410 if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) 411 vp_reg_write(ctx, VP_SHADOW_UPDATE, VP_SHADOW_UPDATE_ENABLE); 412 } 413 414 static void mixer_cfg_scan(struct mixer_context *ctx, int width, int height) 415 { 416 u32 val; 417 418 /* choosing between interlace and progressive mode */ 419 val = test_bit(MXR_BIT_INTERLACE, &ctx->flags) ? 420 MXR_CFG_SCAN_INTERLACE : MXR_CFG_SCAN_PROGRESSIVE; 421 422 if (ctx->mxr_ver == MXR_VER_128_0_0_184) 423 mixer_reg_write(ctx, MXR_RESOLUTION, 424 MXR_MXR_RES_HEIGHT(height) | MXR_MXR_RES_WIDTH(width)); 425 else 426 val |= ctx->scan_value; 427 428 mixer_reg_writemask(ctx, MXR_CFG, val, MXR_CFG_SCAN_MASK); 429 } 430 431 static void mixer_cfg_rgb_fmt(struct mixer_context *ctx, struct drm_display_mode *mode) 432 { 433 enum hdmi_quantization_range range = drm_default_rgb_quant_range(mode); 434 u32 val; 435 436 if (mode->vdisplay < 720) { 437 val = MXR_CFG_RGB601; 438 } else { 439 val = MXR_CFG_RGB709; 440 441 /* Configure the BT.709 CSC matrix for full range RGB. */ 442 mixer_reg_write(ctx, MXR_CM_COEFF_Y, 443 MXR_CSC_CT( 0.184, 0.614, 0.063) | 444 MXR_CM_COEFF_RGB_FULL); 445 mixer_reg_write(ctx, MXR_CM_COEFF_CB, 446 MXR_CSC_CT(-0.102, -0.338, 0.440)); 447 mixer_reg_write(ctx, MXR_CM_COEFF_CR, 448 MXR_CSC_CT( 0.440, -0.399, -0.040)); 449 } 450 451 if (range == HDMI_QUANTIZATION_RANGE_FULL) 452 val |= MXR_CFG_QUANT_RANGE_FULL; 453 else 454 val |= MXR_CFG_QUANT_RANGE_LIMITED; 455 456 mixer_reg_writemask(ctx, MXR_CFG, val, MXR_CFG_RGB_FMT_MASK); 457 } 458 459 static void mixer_cfg_layer(struct mixer_context *ctx, unsigned int win, 460 unsigned int priority, bool enable) 461 { 462 u32 val = enable ? ~0 : 0; 463 464 switch (win) { 465 case 0: 466 mixer_reg_writemask(ctx, MXR_CFG, val, MXR_CFG_GRP0_ENABLE); 467 mixer_reg_writemask(ctx, MXR_LAYER_CFG, 468 MXR_LAYER_CFG_GRP0_VAL(priority), 469 MXR_LAYER_CFG_GRP0_MASK); 470 break; 471 case 1: 472 mixer_reg_writemask(ctx, MXR_CFG, val, MXR_CFG_GRP1_ENABLE); 473 mixer_reg_writemask(ctx, MXR_LAYER_CFG, 474 MXR_LAYER_CFG_GRP1_VAL(priority), 475 MXR_LAYER_CFG_GRP1_MASK); 476 477 break; 478 case VP_DEFAULT_WIN: 479 if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) { 480 vp_reg_writemask(ctx, VP_ENABLE, val, VP_ENABLE_ON); 481 mixer_reg_writemask(ctx, MXR_CFG, val, 482 MXR_CFG_VP_ENABLE); 483 mixer_reg_writemask(ctx, MXR_LAYER_CFG, 484 MXR_LAYER_CFG_VP_VAL(priority), 485 MXR_LAYER_CFG_VP_MASK); 486 } 487 break; 488 } 489 } 490 491 static void mixer_run(struct mixer_context *ctx) 492 { 493 mixer_reg_writemask(ctx, MXR_STATUS, ~0, MXR_STATUS_REG_RUN); 494 } 495 496 static void mixer_stop(struct mixer_context *ctx) 497 { 498 int timeout = 20; 499 500 mixer_reg_writemask(ctx, MXR_STATUS, 0, MXR_STATUS_REG_RUN); 501 502 while (!(mixer_reg_read(ctx, MXR_STATUS) & MXR_STATUS_REG_IDLE) && 503 --timeout) 504 usleep_range(10000, 12000); 505 } 506 507 static void mixer_commit(struct mixer_context *ctx) 508 { 509 struct drm_display_mode *mode = &ctx->crtc->base.state->adjusted_mode; 510 511 mixer_cfg_scan(ctx, mode->hdisplay, mode->vdisplay); 512 mixer_cfg_rgb_fmt(ctx, mode); 513 mixer_run(ctx); 514 } 515 516 static void vp_video_buffer(struct mixer_context *ctx, 517 struct exynos_drm_plane *plane) 518 { 519 struct exynos_drm_plane_state *state = 520 to_exynos_plane_state(plane->base.state); 521 struct drm_framebuffer *fb = state->base.fb; 522 unsigned int priority = state->base.normalized_zpos + 1; 523 unsigned long flags; 524 dma_addr_t luma_addr[2], chroma_addr[2]; 525 bool is_tiled, is_nv21; 526 u32 val; 527 528 is_nv21 = (fb->format->format == DRM_FORMAT_NV21); 529 is_tiled = (fb->modifier == DRM_FORMAT_MOD_SAMSUNG_64_32_TILE); 530 531 luma_addr[0] = exynos_drm_fb_dma_addr(fb, 0); 532 chroma_addr[0] = exynos_drm_fb_dma_addr(fb, 1); 533 534 if (test_bit(MXR_BIT_INTERLACE, &ctx->flags)) { 535 if (is_tiled) { 536 luma_addr[1] = luma_addr[0] + 0x40; 537 chroma_addr[1] = chroma_addr[0] + 0x40; 538 } else { 539 luma_addr[1] = luma_addr[0] + fb->pitches[0]; 540 chroma_addr[1] = chroma_addr[0] + fb->pitches[1]; 541 } 542 } else { 543 luma_addr[1] = 0; 544 chroma_addr[1] = 0; 545 } 546 547 spin_lock_irqsave(&ctx->reg_slock, flags); 548 549 /* interlace or progressive scan mode */ 550 val = (test_bit(MXR_BIT_INTERLACE, &ctx->flags) ? ~0 : 0); 551 vp_reg_writemask(ctx, VP_MODE, val, VP_MODE_LINE_SKIP); 552 553 /* setup format */ 554 val = (is_nv21 ? VP_MODE_NV21 : VP_MODE_NV12); 555 val |= (is_tiled ? VP_MODE_MEM_TILED : VP_MODE_MEM_LINEAR); 556 vp_reg_writemask(ctx, VP_MODE, val, VP_MODE_FMT_MASK); 557 558 /* setting size of input image */ 559 vp_reg_write(ctx, VP_IMG_SIZE_Y, VP_IMG_HSIZE(fb->pitches[0]) | 560 VP_IMG_VSIZE(fb->height)); 561 /* chroma plane for NV12/NV21 is half the height of the luma plane */ 562 vp_reg_write(ctx, VP_IMG_SIZE_C, VP_IMG_HSIZE(fb->pitches[1]) | 563 VP_IMG_VSIZE(fb->height / 2)); 564 565 vp_reg_write(ctx, VP_SRC_WIDTH, state->src.w); 566 vp_reg_write(ctx, VP_SRC_H_POSITION, 567 VP_SRC_H_POSITION_VAL(state->src.x)); 568 vp_reg_write(ctx, VP_DST_WIDTH, state->crtc.w); 569 vp_reg_write(ctx, VP_DST_H_POSITION, state->crtc.x); 570 571 if (test_bit(MXR_BIT_INTERLACE, &ctx->flags)) { 572 vp_reg_write(ctx, VP_SRC_HEIGHT, state->src.h / 2); 573 vp_reg_write(ctx, VP_SRC_V_POSITION, state->src.y / 2); 574 vp_reg_write(ctx, VP_DST_HEIGHT, state->crtc.h / 2); 575 vp_reg_write(ctx, VP_DST_V_POSITION, state->crtc.y / 2); 576 } else { 577 vp_reg_write(ctx, VP_SRC_HEIGHT, state->src.h); 578 vp_reg_write(ctx, VP_SRC_V_POSITION, state->src.y); 579 vp_reg_write(ctx, VP_DST_HEIGHT, state->crtc.h); 580 vp_reg_write(ctx, VP_DST_V_POSITION, state->crtc.y); 581 } 582 583 vp_reg_write(ctx, VP_H_RATIO, state->h_ratio); 584 vp_reg_write(ctx, VP_V_RATIO, state->v_ratio); 585 586 vp_reg_write(ctx, VP_ENDIAN_MODE, VP_ENDIAN_MODE_LITTLE); 587 588 /* set buffer address to vp */ 589 vp_reg_write(ctx, VP_TOP_Y_PTR, luma_addr[0]); 590 vp_reg_write(ctx, VP_BOT_Y_PTR, luma_addr[1]); 591 vp_reg_write(ctx, VP_TOP_C_PTR, chroma_addr[0]); 592 vp_reg_write(ctx, VP_BOT_C_PTR, chroma_addr[1]); 593 594 mixer_cfg_layer(ctx, plane->index, priority, true); 595 mixer_cfg_vp_blend(ctx, state->base.alpha); 596 597 spin_unlock_irqrestore(&ctx->reg_slock, flags); 598 599 mixer_regs_dump(ctx); 600 vp_regs_dump(ctx); 601 } 602 603 static void mixer_graph_buffer(struct mixer_context *ctx, 604 struct exynos_drm_plane *plane) 605 { 606 struct exynos_drm_plane_state *state = 607 to_exynos_plane_state(plane->base.state); 608 struct drm_framebuffer *fb = state->base.fb; 609 unsigned int priority = state->base.normalized_zpos + 1; 610 unsigned long flags; 611 unsigned int win = plane->index; 612 unsigned int x_ratio = 0, y_ratio = 0; 613 unsigned int dst_x_offset, dst_y_offset; 614 unsigned int pixel_alpha; 615 dma_addr_t dma_addr; 616 unsigned int fmt; 617 u32 val; 618 619 if (fb->format->has_alpha) 620 pixel_alpha = state->base.pixel_blend_mode; 621 else 622 pixel_alpha = DRM_MODE_BLEND_PIXEL_NONE; 623 624 switch (fb->format->format) { 625 case DRM_FORMAT_XRGB4444: 626 case DRM_FORMAT_ARGB4444: 627 fmt = MXR_FORMAT_ARGB4444; 628 break; 629 630 case DRM_FORMAT_XRGB1555: 631 case DRM_FORMAT_ARGB1555: 632 fmt = MXR_FORMAT_ARGB1555; 633 break; 634 635 case DRM_FORMAT_RGB565: 636 fmt = MXR_FORMAT_RGB565; 637 break; 638 639 case DRM_FORMAT_XRGB8888: 640 case DRM_FORMAT_ARGB8888: 641 default: 642 fmt = MXR_FORMAT_ARGB8888; 643 break; 644 } 645 646 /* ratio is already checked by common plane code */ 647 x_ratio = state->h_ratio == (1 << 15); 648 y_ratio = state->v_ratio == (1 << 15); 649 650 dst_x_offset = state->crtc.x; 651 dst_y_offset = state->crtc.y; 652 653 /* translate dma address base s.t. the source image offset is zero */ 654 dma_addr = exynos_drm_fb_dma_addr(fb, 0) 655 + (state->src.x * fb->format->cpp[0]) 656 + (state->src.y * fb->pitches[0]); 657 658 spin_lock_irqsave(&ctx->reg_slock, flags); 659 660 /* setup format */ 661 mixer_reg_writemask(ctx, MXR_GRAPHIC_CFG(win), 662 MXR_GRP_CFG_FORMAT_VAL(fmt), MXR_GRP_CFG_FORMAT_MASK); 663 664 /* setup geometry */ 665 mixer_reg_write(ctx, MXR_GRAPHIC_SPAN(win), 666 fb->pitches[0] / fb->format->cpp[0]); 667 668 val = MXR_GRP_WH_WIDTH(state->src.w); 669 val |= MXR_GRP_WH_HEIGHT(state->src.h); 670 val |= MXR_GRP_WH_H_SCALE(x_ratio); 671 val |= MXR_GRP_WH_V_SCALE(y_ratio); 672 mixer_reg_write(ctx, MXR_GRAPHIC_WH(win), val); 673 674 /* setup offsets in display image */ 675 val = MXR_GRP_DXY_DX(dst_x_offset); 676 val |= MXR_GRP_DXY_DY(dst_y_offset); 677 mixer_reg_write(ctx, MXR_GRAPHIC_DXY(win), val); 678 679 /* set buffer address to mixer */ 680 mixer_reg_write(ctx, MXR_GRAPHIC_BASE(win), dma_addr); 681 682 mixer_cfg_layer(ctx, win, priority, true); 683 mixer_cfg_gfx_blend(ctx, win, pixel_alpha, state->base.alpha); 684 685 spin_unlock_irqrestore(&ctx->reg_slock, flags); 686 687 mixer_regs_dump(ctx); 688 } 689 690 static void vp_win_reset(struct mixer_context *ctx) 691 { 692 unsigned int tries = 100; 693 694 vp_reg_write(ctx, VP_SRESET, VP_SRESET_PROCESSING); 695 while (--tries) { 696 /* waiting until VP_SRESET_PROCESSING is 0 */ 697 if (~vp_reg_read(ctx, VP_SRESET) & VP_SRESET_PROCESSING) 698 break; 699 mdelay(10); 700 } 701 WARN(tries == 0, "failed to reset Video Processor\n"); 702 } 703 704 static void mixer_win_reset(struct mixer_context *ctx) 705 { 706 unsigned long flags; 707 708 spin_lock_irqsave(&ctx->reg_slock, flags); 709 710 mixer_reg_writemask(ctx, MXR_CFG, MXR_CFG_DST_HDMI, MXR_CFG_DST_MASK); 711 712 /* set output in RGB888 mode */ 713 mixer_reg_writemask(ctx, MXR_CFG, MXR_CFG_OUT_RGB888, MXR_CFG_OUT_MASK); 714 715 /* 16 beat burst in DMA */ 716 mixer_reg_writemask(ctx, MXR_STATUS, MXR_STATUS_16_BURST, 717 MXR_STATUS_BURST_MASK); 718 719 /* reset default layer priority */ 720 mixer_reg_write(ctx, MXR_LAYER_CFG, 0); 721 722 /* set all background colors to RGB (0,0,0) */ 723 mixer_reg_write(ctx, MXR_BG_COLOR0, MXR_YCBCR_VAL(0, 128, 128)); 724 mixer_reg_write(ctx, MXR_BG_COLOR1, MXR_YCBCR_VAL(0, 128, 128)); 725 mixer_reg_write(ctx, MXR_BG_COLOR2, MXR_YCBCR_VAL(0, 128, 128)); 726 727 if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) { 728 /* configuration of Video Processor Registers */ 729 vp_win_reset(ctx); 730 vp_default_filter(ctx); 731 } 732 733 /* disable all layers */ 734 mixer_reg_writemask(ctx, MXR_CFG, 0, MXR_CFG_GRP0_ENABLE); 735 mixer_reg_writemask(ctx, MXR_CFG, 0, MXR_CFG_GRP1_ENABLE); 736 if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) 737 mixer_reg_writemask(ctx, MXR_CFG, 0, MXR_CFG_VP_ENABLE); 738 739 /* set all source image offsets to zero */ 740 mixer_reg_write(ctx, MXR_GRAPHIC_SXY(0), 0); 741 mixer_reg_write(ctx, MXR_GRAPHIC_SXY(1), 0); 742 743 spin_unlock_irqrestore(&ctx->reg_slock, flags); 744 } 745 746 static irqreturn_t mixer_irq_handler(int irq, void *arg) 747 { 748 struct mixer_context *ctx = arg; 749 u32 val; 750 751 spin_lock(&ctx->reg_slock); 752 753 /* read interrupt status for handling and clearing flags for VSYNC */ 754 val = mixer_reg_read(ctx, MXR_INT_STATUS); 755 756 /* handling VSYNC */ 757 if (val & MXR_INT_STATUS_VSYNC) { 758 /* vsync interrupt use different bit for read and clear */ 759 val |= MXR_INT_CLEAR_VSYNC; 760 val &= ~MXR_INT_STATUS_VSYNC; 761 762 /* interlace scan need to check shadow register */ 763 if (test_bit(MXR_BIT_INTERLACE, &ctx->flags) 764 && !mixer_is_synced(ctx)) 765 goto out; 766 767 drm_crtc_handle_vblank(&ctx->crtc->base); 768 } 769 770 out: 771 /* clear interrupts */ 772 mixer_reg_write(ctx, MXR_INT_STATUS, val); 773 774 spin_unlock(&ctx->reg_slock); 775 776 return IRQ_HANDLED; 777 } 778 779 static int mixer_resources_init(struct mixer_context *mixer_ctx) 780 { 781 struct device *dev = &mixer_ctx->pdev->dev; 782 struct resource *res; 783 int ret; 784 785 spin_lock_init(&mixer_ctx->reg_slock); 786 787 mixer_ctx->mixer = devm_clk_get(dev, "mixer"); 788 if (IS_ERR(mixer_ctx->mixer)) { 789 dev_err(dev, "failed to get clock 'mixer'\n"); 790 return -ENODEV; 791 } 792 793 mixer_ctx->hdmi = devm_clk_get(dev, "hdmi"); 794 if (IS_ERR(mixer_ctx->hdmi)) { 795 dev_err(dev, "failed to get clock 'hdmi'\n"); 796 return PTR_ERR(mixer_ctx->hdmi); 797 } 798 799 mixer_ctx->sclk_hdmi = devm_clk_get(dev, "sclk_hdmi"); 800 if (IS_ERR(mixer_ctx->sclk_hdmi)) { 801 dev_err(dev, "failed to get clock 'sclk_hdmi'\n"); 802 return -ENODEV; 803 } 804 res = platform_get_resource(mixer_ctx->pdev, IORESOURCE_MEM, 0); 805 if (res == NULL) { 806 dev_err(dev, "get memory resource failed.\n"); 807 return -ENXIO; 808 } 809 810 mixer_ctx->mixer_regs = devm_ioremap(dev, res->start, 811 resource_size(res)); 812 if (mixer_ctx->mixer_regs == NULL) { 813 dev_err(dev, "register mapping failed.\n"); 814 return -ENXIO; 815 } 816 817 res = platform_get_resource(mixer_ctx->pdev, IORESOURCE_IRQ, 0); 818 if (res == NULL) { 819 dev_err(dev, "get interrupt resource failed.\n"); 820 return -ENXIO; 821 } 822 823 ret = devm_request_irq(dev, res->start, mixer_irq_handler, 824 0, "drm_mixer", mixer_ctx); 825 if (ret) { 826 dev_err(dev, "request interrupt failed.\n"); 827 return ret; 828 } 829 mixer_ctx->irq = res->start; 830 831 return 0; 832 } 833 834 static int vp_resources_init(struct mixer_context *mixer_ctx) 835 { 836 struct device *dev = &mixer_ctx->pdev->dev; 837 struct resource *res; 838 839 mixer_ctx->vp = devm_clk_get(dev, "vp"); 840 if (IS_ERR(mixer_ctx->vp)) { 841 dev_err(dev, "failed to get clock 'vp'\n"); 842 return -ENODEV; 843 } 844 845 if (test_bit(MXR_BIT_HAS_SCLK, &mixer_ctx->flags)) { 846 mixer_ctx->sclk_mixer = devm_clk_get(dev, "sclk_mixer"); 847 if (IS_ERR(mixer_ctx->sclk_mixer)) { 848 dev_err(dev, "failed to get clock 'sclk_mixer'\n"); 849 return -ENODEV; 850 } 851 mixer_ctx->mout_mixer = devm_clk_get(dev, "mout_mixer"); 852 if (IS_ERR(mixer_ctx->mout_mixer)) { 853 dev_err(dev, "failed to get clock 'mout_mixer'\n"); 854 return -ENODEV; 855 } 856 857 if (mixer_ctx->sclk_hdmi && mixer_ctx->mout_mixer) 858 clk_set_parent(mixer_ctx->mout_mixer, 859 mixer_ctx->sclk_hdmi); 860 } 861 862 res = platform_get_resource(mixer_ctx->pdev, IORESOURCE_MEM, 1); 863 if (res == NULL) { 864 dev_err(dev, "get memory resource failed.\n"); 865 return -ENXIO; 866 } 867 868 mixer_ctx->vp_regs = devm_ioremap(dev, res->start, 869 resource_size(res)); 870 if (mixer_ctx->vp_regs == NULL) { 871 dev_err(dev, "register mapping failed.\n"); 872 return -ENXIO; 873 } 874 875 return 0; 876 } 877 878 static int mixer_initialize(struct mixer_context *mixer_ctx, 879 struct drm_device *drm_dev) 880 { 881 int ret; 882 883 mixer_ctx->drm_dev = drm_dev; 884 885 /* acquire resources: regs, irqs, clocks */ 886 ret = mixer_resources_init(mixer_ctx); 887 if (ret) { 888 DRM_ERROR("mixer_resources_init failed ret=%d\n", ret); 889 return ret; 890 } 891 892 if (test_bit(MXR_BIT_VP_ENABLED, &mixer_ctx->flags)) { 893 /* acquire vp resources: regs, irqs, clocks */ 894 ret = vp_resources_init(mixer_ctx); 895 if (ret) { 896 DRM_ERROR("vp_resources_init failed ret=%d\n", ret); 897 return ret; 898 } 899 } 900 901 return exynos_drm_register_dma(drm_dev, mixer_ctx->dev); 902 } 903 904 static void mixer_ctx_remove(struct mixer_context *mixer_ctx) 905 { 906 exynos_drm_unregister_dma(mixer_ctx->drm_dev, mixer_ctx->dev); 907 } 908 909 static int mixer_enable_vblank(struct exynos_drm_crtc *crtc) 910 { 911 struct mixer_context *mixer_ctx = crtc->ctx; 912 913 __set_bit(MXR_BIT_VSYNC, &mixer_ctx->flags); 914 if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags)) 915 return 0; 916 917 /* enable vsync interrupt */ 918 mixer_reg_writemask(mixer_ctx, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC); 919 mixer_reg_writemask(mixer_ctx, MXR_INT_EN, ~0, MXR_INT_EN_VSYNC); 920 921 return 0; 922 } 923 924 static void mixer_disable_vblank(struct exynos_drm_crtc *crtc) 925 { 926 struct mixer_context *mixer_ctx = crtc->ctx; 927 928 __clear_bit(MXR_BIT_VSYNC, &mixer_ctx->flags); 929 930 if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags)) 931 return; 932 933 /* disable vsync interrupt */ 934 mixer_reg_writemask(mixer_ctx, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC); 935 mixer_reg_writemask(mixer_ctx, MXR_INT_EN, 0, MXR_INT_EN_VSYNC); 936 } 937 938 static void mixer_atomic_begin(struct exynos_drm_crtc *crtc) 939 { 940 struct mixer_context *ctx = crtc->ctx; 941 942 if (!test_bit(MXR_BIT_POWERED, &ctx->flags)) 943 return; 944 945 if (mixer_wait_for_sync(ctx)) 946 dev_err(ctx->dev, "timeout waiting for VSYNC\n"); 947 mixer_disable_sync(ctx); 948 } 949 950 static void mixer_update_plane(struct exynos_drm_crtc *crtc, 951 struct exynos_drm_plane *plane) 952 { 953 struct mixer_context *mixer_ctx = crtc->ctx; 954 955 DRM_DEBUG_KMS("win: %d\n", plane->index); 956 957 if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags)) 958 return; 959 960 if (plane->index == VP_DEFAULT_WIN) 961 vp_video_buffer(mixer_ctx, plane); 962 else 963 mixer_graph_buffer(mixer_ctx, plane); 964 } 965 966 static void mixer_disable_plane(struct exynos_drm_crtc *crtc, 967 struct exynos_drm_plane *plane) 968 { 969 struct mixer_context *mixer_ctx = crtc->ctx; 970 unsigned long flags; 971 972 DRM_DEBUG_KMS("win: %d\n", plane->index); 973 974 if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags)) 975 return; 976 977 spin_lock_irqsave(&mixer_ctx->reg_slock, flags); 978 mixer_cfg_layer(mixer_ctx, plane->index, 0, false); 979 spin_unlock_irqrestore(&mixer_ctx->reg_slock, flags); 980 } 981 982 static void mixer_atomic_flush(struct exynos_drm_crtc *crtc) 983 { 984 struct mixer_context *mixer_ctx = crtc->ctx; 985 986 if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags)) 987 return; 988 989 mixer_enable_sync(mixer_ctx); 990 exynos_crtc_handle_event(crtc); 991 } 992 993 static void mixer_enable(struct exynos_drm_crtc *crtc) 994 { 995 struct mixer_context *ctx = crtc->ctx; 996 997 if (test_bit(MXR_BIT_POWERED, &ctx->flags)) 998 return; 999 1000 pm_runtime_get_sync(ctx->dev); 1001 1002 exynos_drm_pipe_clk_enable(crtc, true); 1003 1004 mixer_disable_sync(ctx); 1005 1006 mixer_reg_writemask(ctx, MXR_STATUS, ~0, MXR_STATUS_SOFT_RESET); 1007 1008 if (test_bit(MXR_BIT_VSYNC, &ctx->flags)) { 1009 mixer_reg_writemask(ctx, MXR_INT_STATUS, ~0, 1010 MXR_INT_CLEAR_VSYNC); 1011 mixer_reg_writemask(ctx, MXR_INT_EN, ~0, MXR_INT_EN_VSYNC); 1012 } 1013 mixer_win_reset(ctx); 1014 1015 mixer_commit(ctx); 1016 1017 mixer_enable_sync(ctx); 1018 1019 set_bit(MXR_BIT_POWERED, &ctx->flags); 1020 } 1021 1022 static void mixer_disable(struct exynos_drm_crtc *crtc) 1023 { 1024 struct mixer_context *ctx = crtc->ctx; 1025 int i; 1026 1027 if (!test_bit(MXR_BIT_POWERED, &ctx->flags)) 1028 return; 1029 1030 mixer_stop(ctx); 1031 mixer_regs_dump(ctx); 1032 1033 for (i = 0; i < MIXER_WIN_NR; i++) 1034 mixer_disable_plane(crtc, &ctx->planes[i]); 1035 1036 exynos_drm_pipe_clk_enable(crtc, false); 1037 1038 pm_runtime_put(ctx->dev); 1039 1040 clear_bit(MXR_BIT_POWERED, &ctx->flags); 1041 } 1042 1043 static int mixer_mode_valid(struct exynos_drm_crtc *crtc, 1044 const struct drm_display_mode *mode) 1045 { 1046 struct mixer_context *ctx = crtc->ctx; 1047 u32 w = mode->hdisplay, h = mode->vdisplay; 1048 1049 DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%d\n", w, h, 1050 mode->vrefresh, !!(mode->flags & DRM_MODE_FLAG_INTERLACE)); 1051 1052 if (ctx->mxr_ver == MXR_VER_128_0_0_184) 1053 return MODE_OK; 1054 1055 if ((w >= 464 && w <= 720 && h >= 261 && h <= 576) || 1056 (w >= 1024 && w <= 1280 && h >= 576 && h <= 720) || 1057 (w >= 1664 && w <= 1920 && h >= 936 && h <= 1080)) 1058 return MODE_OK; 1059 1060 if ((w == 1024 && h == 768) || 1061 (w == 1366 && h == 768) || 1062 (w == 1280 && h == 1024)) 1063 return MODE_OK; 1064 1065 return MODE_BAD; 1066 } 1067 1068 static bool mixer_mode_fixup(struct exynos_drm_crtc *crtc, 1069 const struct drm_display_mode *mode, 1070 struct drm_display_mode *adjusted_mode) 1071 { 1072 struct mixer_context *ctx = crtc->ctx; 1073 int width = mode->hdisplay, height = mode->vdisplay, i; 1074 1075 struct { 1076 int hdisplay, vdisplay, htotal, vtotal, scan_val; 1077 } static const modes[] = { 1078 { 720, 480, 858, 525, MXR_CFG_SCAN_NTSC | MXR_CFG_SCAN_SD }, 1079 { 720, 576, 864, 625, MXR_CFG_SCAN_PAL | MXR_CFG_SCAN_SD }, 1080 { 1280, 720, 1650, 750, MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD }, 1081 { 1920, 1080, 2200, 1125, MXR_CFG_SCAN_HD_1080 | 1082 MXR_CFG_SCAN_HD } 1083 }; 1084 1085 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1086 __set_bit(MXR_BIT_INTERLACE, &ctx->flags); 1087 else 1088 __clear_bit(MXR_BIT_INTERLACE, &ctx->flags); 1089 1090 if (ctx->mxr_ver == MXR_VER_128_0_0_184) 1091 return true; 1092 1093 for (i = 0; i < ARRAY_SIZE(modes); ++i) 1094 if (width <= modes[i].hdisplay && height <= modes[i].vdisplay) { 1095 ctx->scan_value = modes[i].scan_val; 1096 if (width < modes[i].hdisplay || 1097 height < modes[i].vdisplay) { 1098 adjusted_mode->hdisplay = modes[i].hdisplay; 1099 adjusted_mode->hsync_start = modes[i].hdisplay; 1100 adjusted_mode->hsync_end = modes[i].htotal; 1101 adjusted_mode->htotal = modes[i].htotal; 1102 adjusted_mode->vdisplay = modes[i].vdisplay; 1103 adjusted_mode->vsync_start = modes[i].vdisplay; 1104 adjusted_mode->vsync_end = modes[i].vtotal; 1105 adjusted_mode->vtotal = modes[i].vtotal; 1106 } 1107 1108 return true; 1109 } 1110 1111 return false; 1112 } 1113 1114 static const struct exynos_drm_crtc_ops mixer_crtc_ops = { 1115 .enable = mixer_enable, 1116 .disable = mixer_disable, 1117 .enable_vblank = mixer_enable_vblank, 1118 .disable_vblank = mixer_disable_vblank, 1119 .atomic_begin = mixer_atomic_begin, 1120 .update_plane = mixer_update_plane, 1121 .disable_plane = mixer_disable_plane, 1122 .atomic_flush = mixer_atomic_flush, 1123 .mode_valid = mixer_mode_valid, 1124 .mode_fixup = mixer_mode_fixup, 1125 }; 1126 1127 static const struct mixer_drv_data exynos5420_mxr_drv_data = { 1128 .version = MXR_VER_128_0_0_184, 1129 .is_vp_enabled = 0, 1130 }; 1131 1132 static const struct mixer_drv_data exynos5250_mxr_drv_data = { 1133 .version = MXR_VER_16_0_33_0, 1134 .is_vp_enabled = 0, 1135 }; 1136 1137 static const struct mixer_drv_data exynos4212_mxr_drv_data = { 1138 .version = MXR_VER_0_0_0_16, 1139 .is_vp_enabled = 1, 1140 }; 1141 1142 static const struct mixer_drv_data exynos4210_mxr_drv_data = { 1143 .version = MXR_VER_0_0_0_16, 1144 .is_vp_enabled = 1, 1145 .has_sclk = 1, 1146 }; 1147 1148 static const struct of_device_id mixer_match_types[] = { 1149 { 1150 .compatible = "samsung,exynos4210-mixer", 1151 .data = &exynos4210_mxr_drv_data, 1152 }, { 1153 .compatible = "samsung,exynos4212-mixer", 1154 .data = &exynos4212_mxr_drv_data, 1155 }, { 1156 .compatible = "samsung,exynos5-mixer", 1157 .data = &exynos5250_mxr_drv_data, 1158 }, { 1159 .compatible = "samsung,exynos5250-mixer", 1160 .data = &exynos5250_mxr_drv_data, 1161 }, { 1162 .compatible = "samsung,exynos5420-mixer", 1163 .data = &exynos5420_mxr_drv_data, 1164 }, { 1165 /* end node */ 1166 } 1167 }; 1168 MODULE_DEVICE_TABLE(of, mixer_match_types); 1169 1170 static int mixer_bind(struct device *dev, struct device *manager, void *data) 1171 { 1172 struct mixer_context *ctx = dev_get_drvdata(dev); 1173 struct drm_device *drm_dev = data; 1174 struct exynos_drm_plane *exynos_plane; 1175 unsigned int i; 1176 int ret; 1177 1178 ret = mixer_initialize(ctx, drm_dev); 1179 if (ret) 1180 return ret; 1181 1182 for (i = 0; i < MIXER_WIN_NR; i++) { 1183 if (i == VP_DEFAULT_WIN && !test_bit(MXR_BIT_VP_ENABLED, 1184 &ctx->flags)) 1185 continue; 1186 1187 ret = exynos_plane_init(drm_dev, &ctx->planes[i], i, 1188 &plane_configs[i]); 1189 if (ret) 1190 return ret; 1191 } 1192 1193 exynos_plane = &ctx->planes[DEFAULT_WIN]; 1194 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, 1195 EXYNOS_DISPLAY_TYPE_HDMI, &mixer_crtc_ops, ctx); 1196 if (IS_ERR(ctx->crtc)) { 1197 mixer_ctx_remove(ctx); 1198 ret = PTR_ERR(ctx->crtc); 1199 goto free_ctx; 1200 } 1201 1202 return 0; 1203 1204 free_ctx: 1205 devm_kfree(dev, ctx); 1206 return ret; 1207 } 1208 1209 static void mixer_unbind(struct device *dev, struct device *master, void *data) 1210 { 1211 struct mixer_context *ctx = dev_get_drvdata(dev); 1212 1213 mixer_ctx_remove(ctx); 1214 } 1215 1216 static const struct component_ops mixer_component_ops = { 1217 .bind = mixer_bind, 1218 .unbind = mixer_unbind, 1219 }; 1220 1221 static int mixer_probe(struct platform_device *pdev) 1222 { 1223 struct device *dev = &pdev->dev; 1224 const struct mixer_drv_data *drv; 1225 struct mixer_context *ctx; 1226 int ret; 1227 1228 ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL); 1229 if (!ctx) { 1230 DRM_ERROR("failed to alloc mixer context.\n"); 1231 return -ENOMEM; 1232 } 1233 1234 drv = of_device_get_match_data(dev); 1235 1236 ctx->pdev = pdev; 1237 ctx->dev = dev; 1238 ctx->mxr_ver = drv->version; 1239 1240 if (drv->is_vp_enabled) 1241 __set_bit(MXR_BIT_VP_ENABLED, &ctx->flags); 1242 if (drv->has_sclk) 1243 __set_bit(MXR_BIT_HAS_SCLK, &ctx->flags); 1244 1245 platform_set_drvdata(pdev, ctx); 1246 1247 ret = component_add(&pdev->dev, &mixer_component_ops); 1248 if (!ret) 1249 pm_runtime_enable(dev); 1250 1251 return ret; 1252 } 1253 1254 static int mixer_remove(struct platform_device *pdev) 1255 { 1256 pm_runtime_disable(&pdev->dev); 1257 1258 component_del(&pdev->dev, &mixer_component_ops); 1259 1260 return 0; 1261 } 1262 1263 static int __maybe_unused exynos_mixer_suspend(struct device *dev) 1264 { 1265 struct mixer_context *ctx = dev_get_drvdata(dev); 1266 1267 clk_disable_unprepare(ctx->hdmi); 1268 clk_disable_unprepare(ctx->mixer); 1269 if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) { 1270 clk_disable_unprepare(ctx->vp); 1271 if (test_bit(MXR_BIT_HAS_SCLK, &ctx->flags)) 1272 clk_disable_unprepare(ctx->sclk_mixer); 1273 } 1274 1275 return 0; 1276 } 1277 1278 static int __maybe_unused exynos_mixer_resume(struct device *dev) 1279 { 1280 struct mixer_context *ctx = dev_get_drvdata(dev); 1281 int ret; 1282 1283 ret = clk_prepare_enable(ctx->mixer); 1284 if (ret < 0) { 1285 DRM_ERROR("Failed to prepare_enable the mixer clk [%d]\n", ret); 1286 return ret; 1287 } 1288 ret = clk_prepare_enable(ctx->hdmi); 1289 if (ret < 0) { 1290 DRM_ERROR("Failed to prepare_enable the hdmi clk [%d]\n", ret); 1291 return ret; 1292 } 1293 if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) { 1294 ret = clk_prepare_enable(ctx->vp); 1295 if (ret < 0) { 1296 DRM_ERROR("Failed to prepare_enable the vp clk [%d]\n", 1297 ret); 1298 return ret; 1299 } 1300 if (test_bit(MXR_BIT_HAS_SCLK, &ctx->flags)) { 1301 ret = clk_prepare_enable(ctx->sclk_mixer); 1302 if (ret < 0) { 1303 DRM_ERROR("Failed to prepare_enable the " \ 1304 "sclk_mixer clk [%d]\n", 1305 ret); 1306 return ret; 1307 } 1308 } 1309 } 1310 1311 return 0; 1312 } 1313 1314 static const struct dev_pm_ops exynos_mixer_pm_ops = { 1315 SET_RUNTIME_PM_OPS(exynos_mixer_suspend, exynos_mixer_resume, NULL) 1316 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1317 pm_runtime_force_resume) 1318 }; 1319 1320 struct platform_driver mixer_driver = { 1321 .driver = { 1322 .name = "exynos-mixer", 1323 .owner = THIS_MODULE, 1324 .pm = &exynos_mixer_pm_ops, 1325 .of_match_table = mixer_match_types, 1326 }, 1327 .probe = mixer_probe, 1328 .remove = mixer_remove, 1329 }; 1330