1 /* 2 * Copyright (C) 2011 Samsung Electronics Co.Ltd 3 * Authors: 4 * Seung-Woo Kim <sw0312.kim@samsung.com> 5 * Inki Dae <inki.dae@samsung.com> 6 * Joonyoung Shim <jy0922.shim@samsung.com> 7 * 8 * Based on drivers/media/video/s5p-tv/hdmi_drv.c 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 * 15 */ 16 17 #include <drm/drmP.h> 18 #include <drm/drm_edid.h> 19 #include <drm/drm_crtc_helper.h> 20 #include <drm/drm_atomic_helper.h> 21 22 #include "regs-hdmi.h" 23 24 #include <linux/kernel.h> 25 #include <linux/spinlock.h> 26 #include <linux/wait.h> 27 #include <linux/i2c.h> 28 #include <linux/platform_device.h> 29 #include <linux/interrupt.h> 30 #include <linux/irq.h> 31 #include <linux/delay.h> 32 #include <linux/pm_runtime.h> 33 #include <linux/clk.h> 34 #include <linux/regulator/consumer.h> 35 #include <linux/io.h> 36 #include <linux/of.h> 37 #include <linux/of_address.h> 38 #include <linux/of_gpio.h> 39 #include <linux/hdmi.h> 40 #include <linux/component.h> 41 #include <linux/mfd/syscon.h> 42 #include <linux/regmap.h> 43 44 #include <drm/exynos_drm.h> 45 46 #include "exynos_drm_drv.h" 47 #include "exynos_drm_crtc.h" 48 #include "exynos_mixer.h" 49 50 #include <linux/gpio.h> 51 #include <media/s5p_hdmi.h> 52 53 #define ctx_from_connector(c) container_of(c, struct hdmi_context, connector) 54 55 #define HOTPLUG_DEBOUNCE_MS 1100 56 57 /* AVI header and aspect ratio */ 58 #define HDMI_AVI_VERSION 0x02 59 #define HDMI_AVI_LENGTH 0x0D 60 61 /* AUI header info */ 62 #define HDMI_AUI_VERSION 0x01 63 #define HDMI_AUI_LENGTH 0x0A 64 #define AVI_SAME_AS_PIC_ASPECT_RATIO 0x8 65 #define AVI_4_3_CENTER_RATIO 0x9 66 #define AVI_16_9_CENTER_RATIO 0xa 67 68 enum hdmi_type { 69 HDMI_TYPE13, 70 HDMI_TYPE14, 71 }; 72 73 struct hdmi_driver_data { 74 unsigned int type; 75 const struct hdmiphy_config *phy_confs; 76 unsigned int phy_conf_count; 77 unsigned int is_apb_phy:1; 78 }; 79 80 struct hdmi_resources { 81 struct clk *hdmi; 82 struct clk *sclk_hdmi; 83 struct clk *sclk_pixel; 84 struct clk *sclk_hdmiphy; 85 struct clk *mout_hdmi; 86 struct regulator_bulk_data *regul_bulk; 87 struct regulator *reg_hdmi_en; 88 int regul_count; 89 }; 90 91 struct hdmi_tg_regs { 92 u8 cmd[1]; 93 u8 h_fsz[2]; 94 u8 hact_st[2]; 95 u8 hact_sz[2]; 96 u8 v_fsz[2]; 97 u8 vsync[2]; 98 u8 vsync2[2]; 99 u8 vact_st[2]; 100 u8 vact_sz[2]; 101 u8 field_chg[2]; 102 u8 vact_st2[2]; 103 u8 vact_st3[2]; 104 u8 vact_st4[2]; 105 u8 vsync_top_hdmi[2]; 106 u8 vsync_bot_hdmi[2]; 107 u8 field_top_hdmi[2]; 108 u8 field_bot_hdmi[2]; 109 u8 tg_3d[1]; 110 }; 111 112 struct hdmi_v13_core_regs { 113 u8 h_blank[2]; 114 u8 v_blank[3]; 115 u8 h_v_line[3]; 116 u8 vsync_pol[1]; 117 u8 int_pro_mode[1]; 118 u8 v_blank_f[3]; 119 u8 h_sync_gen[3]; 120 u8 v_sync_gen1[3]; 121 u8 v_sync_gen2[3]; 122 u8 v_sync_gen3[3]; 123 }; 124 125 struct hdmi_v14_core_regs { 126 u8 h_blank[2]; 127 u8 v2_blank[2]; 128 u8 v1_blank[2]; 129 u8 v_line[2]; 130 u8 h_line[2]; 131 u8 hsync_pol[1]; 132 u8 vsync_pol[1]; 133 u8 int_pro_mode[1]; 134 u8 v_blank_f0[2]; 135 u8 v_blank_f1[2]; 136 u8 h_sync_start[2]; 137 u8 h_sync_end[2]; 138 u8 v_sync_line_bef_2[2]; 139 u8 v_sync_line_bef_1[2]; 140 u8 v_sync_line_aft_2[2]; 141 u8 v_sync_line_aft_1[2]; 142 u8 v_sync_line_aft_pxl_2[2]; 143 u8 v_sync_line_aft_pxl_1[2]; 144 u8 v_blank_f2[2]; /* for 3D mode */ 145 u8 v_blank_f3[2]; /* for 3D mode */ 146 u8 v_blank_f4[2]; /* for 3D mode */ 147 u8 v_blank_f5[2]; /* for 3D mode */ 148 u8 v_sync_line_aft_3[2]; 149 u8 v_sync_line_aft_4[2]; 150 u8 v_sync_line_aft_5[2]; 151 u8 v_sync_line_aft_6[2]; 152 u8 v_sync_line_aft_pxl_3[2]; 153 u8 v_sync_line_aft_pxl_4[2]; 154 u8 v_sync_line_aft_pxl_5[2]; 155 u8 v_sync_line_aft_pxl_6[2]; 156 u8 vact_space_1[2]; 157 u8 vact_space_2[2]; 158 u8 vact_space_3[2]; 159 u8 vact_space_4[2]; 160 u8 vact_space_5[2]; 161 u8 vact_space_6[2]; 162 }; 163 164 struct hdmi_v13_conf { 165 struct hdmi_v13_core_regs core; 166 struct hdmi_tg_regs tg; 167 }; 168 169 struct hdmi_v14_conf { 170 struct hdmi_v14_core_regs core; 171 struct hdmi_tg_regs tg; 172 }; 173 174 struct hdmi_conf_regs { 175 int pixel_clock; 176 int cea_video_id; 177 enum hdmi_picture_aspect aspect_ratio; 178 union { 179 struct hdmi_v13_conf v13_conf; 180 struct hdmi_v14_conf v14_conf; 181 } conf; 182 }; 183 184 struct hdmi_context { 185 struct exynos_drm_display display; 186 struct device *dev; 187 struct drm_device *drm_dev; 188 struct drm_connector connector; 189 struct drm_encoder *encoder; 190 bool hpd; 191 bool powered; 192 bool dvi_mode; 193 struct mutex hdmi_mutex; 194 195 void __iomem *regs; 196 int irq; 197 struct delayed_work hotplug_work; 198 199 struct i2c_adapter *ddc_adpt; 200 struct i2c_client *hdmiphy_port; 201 202 /* current hdmiphy conf regs */ 203 struct drm_display_mode current_mode; 204 struct hdmi_conf_regs mode_conf; 205 206 struct hdmi_resources res; 207 208 int hpd_gpio; 209 void __iomem *regs_hdmiphy; 210 const struct hdmiphy_config *phy_confs; 211 unsigned int phy_conf_count; 212 213 struct regmap *pmureg; 214 enum hdmi_type type; 215 }; 216 217 static inline struct hdmi_context *display_to_hdmi(struct exynos_drm_display *d) 218 { 219 return container_of(d, struct hdmi_context, display); 220 } 221 222 struct hdmiphy_config { 223 int pixel_clock; 224 u8 conf[32]; 225 }; 226 227 /* list of phy config settings */ 228 static const struct hdmiphy_config hdmiphy_v13_configs[] = { 229 { 230 .pixel_clock = 27000000, 231 .conf = { 232 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40, 233 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87, 234 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0, 235 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00, 236 }, 237 }, 238 { 239 .pixel_clock = 27027000, 240 .conf = { 241 0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64, 242 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87, 243 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0, 244 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00, 245 }, 246 }, 247 { 248 .pixel_clock = 74176000, 249 .conf = { 250 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xef, 0x5B, 251 0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3, 0x54, 0xb9, 252 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0, 253 0x22, 0x40, 0xa5, 0x26, 0x01, 0x00, 0x00, 0x00, 254 }, 255 }, 256 { 257 .pixel_clock = 74250000, 258 .conf = { 259 0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c, 0xf8, 0x40, 260 0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1, 0x54, 0xba, 261 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xe0, 262 0x22, 0x40, 0xa4, 0x26, 0x01, 0x00, 0x00, 0x00, 263 }, 264 }, 265 { 266 .pixel_clock = 148500000, 267 .conf = { 268 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xf8, 0x40, 269 0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1, 0x54, 0xba, 270 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0, 271 0x22, 0x40, 0xa4, 0x26, 0x02, 0x00, 0x00, 0x00, 272 }, 273 }, 274 }; 275 276 static const struct hdmiphy_config hdmiphy_v14_configs[] = { 277 { 278 .pixel_clock = 25200000, 279 .conf = { 280 0x01, 0x51, 0x2A, 0x75, 0x40, 0x01, 0x00, 0x08, 281 0x82, 0x80, 0xfc, 0xd8, 0x45, 0xa0, 0xac, 0x80, 282 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 283 0x54, 0xf4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 284 }, 285 }, 286 { 287 .pixel_clock = 27000000, 288 .conf = { 289 0x01, 0xd1, 0x22, 0x51, 0x40, 0x08, 0xfc, 0x20, 290 0x98, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80, 291 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 292 0x54, 0xe4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 293 }, 294 }, 295 { 296 .pixel_clock = 27027000, 297 .conf = { 298 0x01, 0xd1, 0x2d, 0x72, 0x40, 0x64, 0x12, 0x08, 299 0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80, 300 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 301 0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00, 302 }, 303 }, 304 { 305 .pixel_clock = 36000000, 306 .conf = { 307 0x01, 0x51, 0x2d, 0x55, 0x40, 0x01, 0x00, 0x08, 308 0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80, 309 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 310 0x54, 0xab, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 311 }, 312 }, 313 { 314 .pixel_clock = 40000000, 315 .conf = { 316 0x01, 0x51, 0x32, 0x55, 0x40, 0x01, 0x00, 0x08, 317 0x82, 0x80, 0x2c, 0xd9, 0x45, 0xa0, 0xac, 0x80, 318 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 319 0x54, 0x9a, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 320 }, 321 }, 322 { 323 .pixel_clock = 65000000, 324 .conf = { 325 0x01, 0xd1, 0x36, 0x34, 0x40, 0x1e, 0x0a, 0x08, 326 0x82, 0xa0, 0x45, 0xd9, 0x45, 0xa0, 0xac, 0x80, 327 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 328 0x54, 0xbd, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 329 }, 330 }, 331 { 332 .pixel_clock = 71000000, 333 .conf = { 334 0x01, 0xd1, 0x3b, 0x35, 0x40, 0x0c, 0x04, 0x08, 335 0x85, 0xa0, 0x63, 0xd9, 0x45, 0xa0, 0xac, 0x80, 336 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 337 0x54, 0xad, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 338 }, 339 }, 340 { 341 .pixel_clock = 73250000, 342 .conf = { 343 0x01, 0xd1, 0x3d, 0x35, 0x40, 0x18, 0x02, 0x08, 344 0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80, 345 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 346 0x54, 0xa8, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 347 }, 348 }, 349 { 350 .pixel_clock = 74176000, 351 .conf = { 352 0x01, 0xd1, 0x3e, 0x35, 0x40, 0x5b, 0xde, 0x08, 353 0x82, 0xa0, 0x73, 0xd9, 0x45, 0xa0, 0xac, 0x80, 354 0x56, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 355 0x54, 0xa6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 356 }, 357 }, 358 { 359 .pixel_clock = 74250000, 360 .conf = { 361 0x01, 0xd1, 0x1f, 0x10, 0x40, 0x40, 0xf8, 0x08, 362 0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80, 363 0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 364 0x54, 0xa5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00, 365 }, 366 }, 367 { 368 .pixel_clock = 83500000, 369 .conf = { 370 0x01, 0xd1, 0x23, 0x11, 0x40, 0x0c, 0xfb, 0x08, 371 0x85, 0xa0, 0xd1, 0xd8, 0x45, 0xa0, 0xac, 0x80, 372 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 373 0x54, 0x93, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 374 }, 375 }, 376 { 377 .pixel_clock = 106500000, 378 .conf = { 379 0x01, 0xd1, 0x2c, 0x12, 0x40, 0x0c, 0x09, 0x08, 380 0x84, 0xa0, 0x0a, 0xd9, 0x45, 0xa0, 0xac, 0x80, 381 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 382 0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 383 }, 384 }, 385 { 386 .pixel_clock = 108000000, 387 .conf = { 388 0x01, 0x51, 0x2d, 0x15, 0x40, 0x01, 0x00, 0x08, 389 0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80, 390 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 391 0x54, 0xc7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80, 392 }, 393 }, 394 { 395 .pixel_clock = 115500000, 396 .conf = { 397 0x01, 0xd1, 0x30, 0x12, 0x40, 0x40, 0x10, 0x08, 398 0x80, 0x80, 0x21, 0xd9, 0x45, 0xa0, 0xac, 0x80, 399 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 400 0x54, 0xaa, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80, 401 }, 402 }, 403 { 404 .pixel_clock = 119000000, 405 .conf = { 406 0x01, 0xd1, 0x32, 0x1a, 0x40, 0x30, 0xd8, 0x08, 407 0x04, 0xa0, 0x2a, 0xd9, 0x45, 0xa0, 0xac, 0x80, 408 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 409 0x54, 0x9d, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80, 410 }, 411 }, 412 { 413 .pixel_clock = 146250000, 414 .conf = { 415 0x01, 0xd1, 0x3d, 0x15, 0x40, 0x18, 0xfd, 0x08, 416 0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80, 417 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 418 0x54, 0x50, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80, 419 }, 420 }, 421 { 422 .pixel_clock = 148500000, 423 .conf = { 424 0x01, 0xd1, 0x1f, 0x00, 0x40, 0x40, 0xf8, 0x08, 425 0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80, 426 0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 427 0x54, 0x4b, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00, 428 }, 429 }, 430 }; 431 432 static const struct hdmiphy_config hdmiphy_5420_configs[] = { 433 { 434 .pixel_clock = 25200000, 435 .conf = { 436 0x01, 0x52, 0x3F, 0x55, 0x40, 0x01, 0x00, 0xC8, 437 0x82, 0xC8, 0xBD, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 438 0x06, 0x80, 0x01, 0x84, 0x05, 0x02, 0x24, 0x66, 439 0x54, 0xF4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 440 }, 441 }, 442 { 443 .pixel_clock = 27000000, 444 .conf = { 445 0x01, 0xD1, 0x22, 0x51, 0x40, 0x08, 0xFC, 0xE0, 446 0x98, 0xE8, 0xCB, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 447 0x06, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 448 0x54, 0xE4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 449 }, 450 }, 451 { 452 .pixel_clock = 27027000, 453 .conf = { 454 0x01, 0xD1, 0x2D, 0x72, 0x40, 0x64, 0x12, 0xC8, 455 0x43, 0xE8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80, 456 0x26, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 457 0x54, 0xE3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 458 }, 459 }, 460 { 461 .pixel_clock = 36000000, 462 .conf = { 463 0x01, 0x51, 0x2D, 0x55, 0x40, 0x40, 0x00, 0xC8, 464 0x02, 0xC8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80, 465 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 466 0x54, 0xAB, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 467 }, 468 }, 469 { 470 .pixel_clock = 40000000, 471 .conf = { 472 0x01, 0xD1, 0x21, 0x31, 0x40, 0x3C, 0x28, 0xC8, 473 0x87, 0xE8, 0xC8, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 474 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 475 0x54, 0x9A, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 476 }, 477 }, 478 { 479 .pixel_clock = 65000000, 480 .conf = { 481 0x01, 0xD1, 0x36, 0x34, 0x40, 0x0C, 0x04, 0xC8, 482 0x82, 0xE8, 0x45, 0xD9, 0x45, 0xA0, 0xAC, 0x80, 483 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 484 0x54, 0xBD, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 485 }, 486 }, 487 { 488 .pixel_clock = 71000000, 489 .conf = { 490 0x01, 0xD1, 0x3B, 0x35, 0x40, 0x0C, 0x04, 0xC8, 491 0x85, 0xE8, 0x63, 0xD9, 0x45, 0xA0, 0xAC, 0x80, 492 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 493 0x54, 0x57, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 494 }, 495 }, 496 { 497 .pixel_clock = 73250000, 498 .conf = { 499 0x01, 0xD1, 0x1F, 0x10, 0x40, 0x78, 0x8D, 0xC8, 500 0x81, 0xE8, 0xB7, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 501 0x56, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 502 0x54, 0xA8, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 503 }, 504 }, 505 { 506 .pixel_clock = 74176000, 507 .conf = { 508 0x01, 0xD1, 0x1F, 0x10, 0x40, 0x5B, 0xEF, 0xC8, 509 0x81, 0xE8, 0xB9, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 510 0x56, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 511 0x54, 0xA6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 512 }, 513 }, 514 { 515 .pixel_clock = 74250000, 516 .conf = { 517 0x01, 0xD1, 0x1F, 0x10, 0x40, 0x40, 0xF8, 0x08, 518 0x81, 0xE8, 0xBA, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 519 0x26, 0x80, 0x09, 0x84, 0x05, 0x22, 0x24, 0x66, 520 0x54, 0xA5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 521 }, 522 }, 523 { 524 .pixel_clock = 83500000, 525 .conf = { 526 0x01, 0xD1, 0x23, 0x11, 0x40, 0x0C, 0xFB, 0xC8, 527 0x85, 0xE8, 0xD1, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 528 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 529 0x54, 0x4A, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 530 }, 531 }, 532 { 533 .pixel_clock = 88750000, 534 .conf = { 535 0x01, 0xD1, 0x25, 0x11, 0x40, 0x18, 0xFF, 0xC8, 536 0x83, 0xE8, 0xDE, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 537 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 538 0x54, 0x45, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 539 }, 540 }, 541 { 542 .pixel_clock = 106500000, 543 .conf = { 544 0x01, 0xD1, 0x2C, 0x12, 0x40, 0x0C, 0x09, 0xC8, 545 0x84, 0xE8, 0x0A, 0xD9, 0x45, 0xA0, 0xAC, 0x80, 546 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 547 0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 548 }, 549 }, 550 { 551 .pixel_clock = 108000000, 552 .conf = { 553 0x01, 0x51, 0x2D, 0x15, 0x40, 0x01, 0x00, 0xC8, 554 0x82, 0xC8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80, 555 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 556 0x54, 0xC7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80, 557 }, 558 }, 559 { 560 .pixel_clock = 115500000, 561 .conf = { 562 0x01, 0xD1, 0x30, 0x14, 0x40, 0x0C, 0x03, 0xC8, 563 0x88, 0xE8, 0x21, 0xD9, 0x45, 0xA0, 0xAC, 0x80, 564 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 565 0x54, 0x6A, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 566 }, 567 }, 568 { 569 .pixel_clock = 146250000, 570 .conf = { 571 0x01, 0xD1, 0x3D, 0x15, 0x40, 0x18, 0xFD, 0xC8, 572 0x83, 0xE8, 0x6E, 0xD9, 0x45, 0xA0, 0xAC, 0x80, 573 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 574 0x54, 0x54, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 575 }, 576 }, 577 { 578 .pixel_clock = 148500000, 579 .conf = { 580 0x01, 0xD1, 0x1F, 0x00, 0x40, 0x40, 0xF8, 0x08, 581 0x81, 0xE8, 0xBA, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 582 0x26, 0x80, 0x09, 0x84, 0x05, 0x22, 0x24, 0x66, 583 0x54, 0x4B, 0x25, 0x03, 0x00, 0x80, 0x01, 0x80, 584 }, 585 }, 586 }; 587 588 static struct hdmi_driver_data exynos5420_hdmi_driver_data = { 589 .type = HDMI_TYPE14, 590 .phy_confs = hdmiphy_5420_configs, 591 .phy_conf_count = ARRAY_SIZE(hdmiphy_5420_configs), 592 .is_apb_phy = 1, 593 }; 594 595 static struct hdmi_driver_data exynos4212_hdmi_driver_data = { 596 .type = HDMI_TYPE14, 597 .phy_confs = hdmiphy_v14_configs, 598 .phy_conf_count = ARRAY_SIZE(hdmiphy_v14_configs), 599 .is_apb_phy = 0, 600 }; 601 602 static struct hdmi_driver_data exynos4210_hdmi_driver_data = { 603 .type = HDMI_TYPE13, 604 .phy_confs = hdmiphy_v13_configs, 605 .phy_conf_count = ARRAY_SIZE(hdmiphy_v13_configs), 606 .is_apb_phy = 0, 607 }; 608 609 static struct hdmi_driver_data exynos5_hdmi_driver_data = { 610 .type = HDMI_TYPE14, 611 .phy_confs = hdmiphy_v13_configs, 612 .phy_conf_count = ARRAY_SIZE(hdmiphy_v13_configs), 613 .is_apb_phy = 0, 614 }; 615 616 static inline u32 hdmi_reg_read(struct hdmi_context *hdata, u32 reg_id) 617 { 618 return readl(hdata->regs + reg_id); 619 } 620 621 static inline void hdmi_reg_writeb(struct hdmi_context *hdata, 622 u32 reg_id, u8 value) 623 { 624 writeb(value, hdata->regs + reg_id); 625 } 626 627 static inline void hdmi_reg_writemask(struct hdmi_context *hdata, 628 u32 reg_id, u32 value, u32 mask) 629 { 630 u32 old = readl(hdata->regs + reg_id); 631 value = (value & mask) | (old & ~mask); 632 writel(value, hdata->regs + reg_id); 633 } 634 635 static int hdmiphy_reg_writeb(struct hdmi_context *hdata, 636 u32 reg_offset, u8 value) 637 { 638 if (hdata->hdmiphy_port) { 639 u8 buffer[2]; 640 int ret; 641 642 buffer[0] = reg_offset; 643 buffer[1] = value; 644 645 ret = i2c_master_send(hdata->hdmiphy_port, buffer, 2); 646 if (ret == 2) 647 return 0; 648 return ret; 649 } else { 650 writeb(value, hdata->regs_hdmiphy + (reg_offset<<2)); 651 return 0; 652 } 653 } 654 655 static int hdmiphy_reg_write_buf(struct hdmi_context *hdata, 656 u32 reg_offset, const u8 *buf, u32 len) 657 { 658 if ((reg_offset + len) > 32) 659 return -EINVAL; 660 661 if (hdata->hdmiphy_port) { 662 int ret; 663 664 ret = i2c_master_send(hdata->hdmiphy_port, buf, len); 665 if (ret == len) 666 return 0; 667 return ret; 668 } else { 669 int i; 670 for (i = 0; i < len; i++) 671 writeb(buf[i], hdata->regs_hdmiphy + 672 ((reg_offset + i)<<2)); 673 return 0; 674 } 675 } 676 677 static void hdmi_v13_regs_dump(struct hdmi_context *hdata, char *prefix) 678 { 679 #define DUMPREG(reg_id) \ 680 DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \ 681 readl(hdata->regs + reg_id)) 682 DRM_DEBUG_KMS("%s: ---- CONTROL REGISTERS ----\n", prefix); 683 DUMPREG(HDMI_INTC_FLAG); 684 DUMPREG(HDMI_INTC_CON); 685 DUMPREG(HDMI_HPD_STATUS); 686 DUMPREG(HDMI_V13_PHY_RSTOUT); 687 DUMPREG(HDMI_V13_PHY_VPLL); 688 DUMPREG(HDMI_V13_PHY_CMU); 689 DUMPREG(HDMI_V13_CORE_RSTOUT); 690 691 DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix); 692 DUMPREG(HDMI_CON_0); 693 DUMPREG(HDMI_CON_1); 694 DUMPREG(HDMI_CON_2); 695 DUMPREG(HDMI_SYS_STATUS); 696 DUMPREG(HDMI_V13_PHY_STATUS); 697 DUMPREG(HDMI_STATUS_EN); 698 DUMPREG(HDMI_HPD); 699 DUMPREG(HDMI_MODE_SEL); 700 DUMPREG(HDMI_V13_HPD_GEN); 701 DUMPREG(HDMI_V13_DC_CONTROL); 702 DUMPREG(HDMI_V13_VIDEO_PATTERN_GEN); 703 704 DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix); 705 DUMPREG(HDMI_H_BLANK_0); 706 DUMPREG(HDMI_H_BLANK_1); 707 DUMPREG(HDMI_V13_V_BLANK_0); 708 DUMPREG(HDMI_V13_V_BLANK_1); 709 DUMPREG(HDMI_V13_V_BLANK_2); 710 DUMPREG(HDMI_V13_H_V_LINE_0); 711 DUMPREG(HDMI_V13_H_V_LINE_1); 712 DUMPREG(HDMI_V13_H_V_LINE_2); 713 DUMPREG(HDMI_VSYNC_POL); 714 DUMPREG(HDMI_INT_PRO_MODE); 715 DUMPREG(HDMI_V13_V_BLANK_F_0); 716 DUMPREG(HDMI_V13_V_BLANK_F_1); 717 DUMPREG(HDMI_V13_V_BLANK_F_2); 718 DUMPREG(HDMI_V13_H_SYNC_GEN_0); 719 DUMPREG(HDMI_V13_H_SYNC_GEN_1); 720 DUMPREG(HDMI_V13_H_SYNC_GEN_2); 721 DUMPREG(HDMI_V13_V_SYNC_GEN_1_0); 722 DUMPREG(HDMI_V13_V_SYNC_GEN_1_1); 723 DUMPREG(HDMI_V13_V_SYNC_GEN_1_2); 724 DUMPREG(HDMI_V13_V_SYNC_GEN_2_0); 725 DUMPREG(HDMI_V13_V_SYNC_GEN_2_1); 726 DUMPREG(HDMI_V13_V_SYNC_GEN_2_2); 727 DUMPREG(HDMI_V13_V_SYNC_GEN_3_0); 728 DUMPREG(HDMI_V13_V_SYNC_GEN_3_1); 729 DUMPREG(HDMI_V13_V_SYNC_GEN_3_2); 730 731 DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix); 732 DUMPREG(HDMI_TG_CMD); 733 DUMPREG(HDMI_TG_H_FSZ_L); 734 DUMPREG(HDMI_TG_H_FSZ_H); 735 DUMPREG(HDMI_TG_HACT_ST_L); 736 DUMPREG(HDMI_TG_HACT_ST_H); 737 DUMPREG(HDMI_TG_HACT_SZ_L); 738 DUMPREG(HDMI_TG_HACT_SZ_H); 739 DUMPREG(HDMI_TG_V_FSZ_L); 740 DUMPREG(HDMI_TG_V_FSZ_H); 741 DUMPREG(HDMI_TG_VSYNC_L); 742 DUMPREG(HDMI_TG_VSYNC_H); 743 DUMPREG(HDMI_TG_VSYNC2_L); 744 DUMPREG(HDMI_TG_VSYNC2_H); 745 DUMPREG(HDMI_TG_VACT_ST_L); 746 DUMPREG(HDMI_TG_VACT_ST_H); 747 DUMPREG(HDMI_TG_VACT_SZ_L); 748 DUMPREG(HDMI_TG_VACT_SZ_H); 749 DUMPREG(HDMI_TG_FIELD_CHG_L); 750 DUMPREG(HDMI_TG_FIELD_CHG_H); 751 DUMPREG(HDMI_TG_VACT_ST2_L); 752 DUMPREG(HDMI_TG_VACT_ST2_H); 753 DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L); 754 DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H); 755 DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L); 756 DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H); 757 DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L); 758 DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H); 759 DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L); 760 DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H); 761 #undef DUMPREG 762 } 763 764 static void hdmi_v14_regs_dump(struct hdmi_context *hdata, char *prefix) 765 { 766 int i; 767 768 #define DUMPREG(reg_id) \ 769 DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \ 770 readl(hdata->regs + reg_id)) 771 772 DRM_DEBUG_KMS("%s: ---- CONTROL REGISTERS ----\n", prefix); 773 DUMPREG(HDMI_INTC_CON); 774 DUMPREG(HDMI_INTC_FLAG); 775 DUMPREG(HDMI_HPD_STATUS); 776 DUMPREG(HDMI_INTC_CON_1); 777 DUMPREG(HDMI_INTC_FLAG_1); 778 DUMPREG(HDMI_PHY_STATUS_0); 779 DUMPREG(HDMI_PHY_STATUS_PLL); 780 DUMPREG(HDMI_PHY_CON_0); 781 DUMPREG(HDMI_PHY_RSTOUT); 782 DUMPREG(HDMI_PHY_VPLL); 783 DUMPREG(HDMI_PHY_CMU); 784 DUMPREG(HDMI_CORE_RSTOUT); 785 786 DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix); 787 DUMPREG(HDMI_CON_0); 788 DUMPREG(HDMI_CON_1); 789 DUMPREG(HDMI_CON_2); 790 DUMPREG(HDMI_SYS_STATUS); 791 DUMPREG(HDMI_PHY_STATUS_0); 792 DUMPREG(HDMI_STATUS_EN); 793 DUMPREG(HDMI_HPD); 794 DUMPREG(HDMI_MODE_SEL); 795 DUMPREG(HDMI_ENC_EN); 796 DUMPREG(HDMI_DC_CONTROL); 797 DUMPREG(HDMI_VIDEO_PATTERN_GEN); 798 799 DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix); 800 DUMPREG(HDMI_H_BLANK_0); 801 DUMPREG(HDMI_H_BLANK_1); 802 DUMPREG(HDMI_V2_BLANK_0); 803 DUMPREG(HDMI_V2_BLANK_1); 804 DUMPREG(HDMI_V1_BLANK_0); 805 DUMPREG(HDMI_V1_BLANK_1); 806 DUMPREG(HDMI_V_LINE_0); 807 DUMPREG(HDMI_V_LINE_1); 808 DUMPREG(HDMI_H_LINE_0); 809 DUMPREG(HDMI_H_LINE_1); 810 DUMPREG(HDMI_HSYNC_POL); 811 812 DUMPREG(HDMI_VSYNC_POL); 813 DUMPREG(HDMI_INT_PRO_MODE); 814 DUMPREG(HDMI_V_BLANK_F0_0); 815 DUMPREG(HDMI_V_BLANK_F0_1); 816 DUMPREG(HDMI_V_BLANK_F1_0); 817 DUMPREG(HDMI_V_BLANK_F1_1); 818 819 DUMPREG(HDMI_H_SYNC_START_0); 820 DUMPREG(HDMI_H_SYNC_START_1); 821 DUMPREG(HDMI_H_SYNC_END_0); 822 DUMPREG(HDMI_H_SYNC_END_1); 823 824 DUMPREG(HDMI_V_SYNC_LINE_BEF_2_0); 825 DUMPREG(HDMI_V_SYNC_LINE_BEF_2_1); 826 DUMPREG(HDMI_V_SYNC_LINE_BEF_1_0); 827 DUMPREG(HDMI_V_SYNC_LINE_BEF_1_1); 828 829 DUMPREG(HDMI_V_SYNC_LINE_AFT_2_0); 830 DUMPREG(HDMI_V_SYNC_LINE_AFT_2_1); 831 DUMPREG(HDMI_V_SYNC_LINE_AFT_1_0); 832 DUMPREG(HDMI_V_SYNC_LINE_AFT_1_1); 833 834 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_0); 835 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_1); 836 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_0); 837 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_1); 838 839 DUMPREG(HDMI_V_BLANK_F2_0); 840 DUMPREG(HDMI_V_BLANK_F2_1); 841 DUMPREG(HDMI_V_BLANK_F3_0); 842 DUMPREG(HDMI_V_BLANK_F3_1); 843 DUMPREG(HDMI_V_BLANK_F4_0); 844 DUMPREG(HDMI_V_BLANK_F4_1); 845 DUMPREG(HDMI_V_BLANK_F5_0); 846 DUMPREG(HDMI_V_BLANK_F5_1); 847 848 DUMPREG(HDMI_V_SYNC_LINE_AFT_3_0); 849 DUMPREG(HDMI_V_SYNC_LINE_AFT_3_1); 850 DUMPREG(HDMI_V_SYNC_LINE_AFT_4_0); 851 DUMPREG(HDMI_V_SYNC_LINE_AFT_4_1); 852 DUMPREG(HDMI_V_SYNC_LINE_AFT_5_0); 853 DUMPREG(HDMI_V_SYNC_LINE_AFT_5_1); 854 DUMPREG(HDMI_V_SYNC_LINE_AFT_6_0); 855 DUMPREG(HDMI_V_SYNC_LINE_AFT_6_1); 856 857 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_0); 858 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_1); 859 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_0); 860 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_1); 861 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_0); 862 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_1); 863 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_0); 864 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_1); 865 866 DUMPREG(HDMI_VACT_SPACE_1_0); 867 DUMPREG(HDMI_VACT_SPACE_1_1); 868 DUMPREG(HDMI_VACT_SPACE_2_0); 869 DUMPREG(HDMI_VACT_SPACE_2_1); 870 DUMPREG(HDMI_VACT_SPACE_3_0); 871 DUMPREG(HDMI_VACT_SPACE_3_1); 872 DUMPREG(HDMI_VACT_SPACE_4_0); 873 DUMPREG(HDMI_VACT_SPACE_4_1); 874 DUMPREG(HDMI_VACT_SPACE_5_0); 875 DUMPREG(HDMI_VACT_SPACE_5_1); 876 DUMPREG(HDMI_VACT_SPACE_6_0); 877 DUMPREG(HDMI_VACT_SPACE_6_1); 878 879 DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix); 880 DUMPREG(HDMI_TG_CMD); 881 DUMPREG(HDMI_TG_H_FSZ_L); 882 DUMPREG(HDMI_TG_H_FSZ_H); 883 DUMPREG(HDMI_TG_HACT_ST_L); 884 DUMPREG(HDMI_TG_HACT_ST_H); 885 DUMPREG(HDMI_TG_HACT_SZ_L); 886 DUMPREG(HDMI_TG_HACT_SZ_H); 887 DUMPREG(HDMI_TG_V_FSZ_L); 888 DUMPREG(HDMI_TG_V_FSZ_H); 889 DUMPREG(HDMI_TG_VSYNC_L); 890 DUMPREG(HDMI_TG_VSYNC_H); 891 DUMPREG(HDMI_TG_VSYNC2_L); 892 DUMPREG(HDMI_TG_VSYNC2_H); 893 DUMPREG(HDMI_TG_VACT_ST_L); 894 DUMPREG(HDMI_TG_VACT_ST_H); 895 DUMPREG(HDMI_TG_VACT_SZ_L); 896 DUMPREG(HDMI_TG_VACT_SZ_H); 897 DUMPREG(HDMI_TG_FIELD_CHG_L); 898 DUMPREG(HDMI_TG_FIELD_CHG_H); 899 DUMPREG(HDMI_TG_VACT_ST2_L); 900 DUMPREG(HDMI_TG_VACT_ST2_H); 901 DUMPREG(HDMI_TG_VACT_ST3_L); 902 DUMPREG(HDMI_TG_VACT_ST3_H); 903 DUMPREG(HDMI_TG_VACT_ST4_L); 904 DUMPREG(HDMI_TG_VACT_ST4_H); 905 DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L); 906 DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H); 907 DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L); 908 DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H); 909 DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L); 910 DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H); 911 DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L); 912 DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H); 913 DUMPREG(HDMI_TG_3D); 914 915 DRM_DEBUG_KMS("%s: ---- PACKET REGISTERS ----\n", prefix); 916 DUMPREG(HDMI_AVI_CON); 917 DUMPREG(HDMI_AVI_HEADER0); 918 DUMPREG(HDMI_AVI_HEADER1); 919 DUMPREG(HDMI_AVI_HEADER2); 920 DUMPREG(HDMI_AVI_CHECK_SUM); 921 DUMPREG(HDMI_VSI_CON); 922 DUMPREG(HDMI_VSI_HEADER0); 923 DUMPREG(HDMI_VSI_HEADER1); 924 DUMPREG(HDMI_VSI_HEADER2); 925 for (i = 0; i < 7; ++i) 926 DUMPREG(HDMI_VSI_DATA(i)); 927 928 #undef DUMPREG 929 } 930 931 static void hdmi_regs_dump(struct hdmi_context *hdata, char *prefix) 932 { 933 if (hdata->type == HDMI_TYPE13) 934 hdmi_v13_regs_dump(hdata, prefix); 935 else 936 hdmi_v14_regs_dump(hdata, prefix); 937 } 938 939 static u8 hdmi_chksum(struct hdmi_context *hdata, 940 u32 start, u8 len, u32 hdr_sum) 941 { 942 int i; 943 944 /* hdr_sum : header0 + header1 + header2 945 * start : start address of packet byte1 946 * len : packet bytes - 1 */ 947 for (i = 0; i < len; ++i) 948 hdr_sum += 0xff & hdmi_reg_read(hdata, start + i * 4); 949 950 /* return 2's complement of 8 bit hdr_sum */ 951 return (u8)(~(hdr_sum & 0xff) + 1); 952 } 953 954 static void hdmi_reg_infoframe(struct hdmi_context *hdata, 955 union hdmi_infoframe *infoframe) 956 { 957 u32 hdr_sum; 958 u8 chksum; 959 u32 mod; 960 u32 vic; 961 962 mod = hdmi_reg_read(hdata, HDMI_MODE_SEL); 963 if (hdata->dvi_mode) { 964 hdmi_reg_writeb(hdata, HDMI_VSI_CON, 965 HDMI_VSI_CON_DO_NOT_TRANSMIT); 966 hdmi_reg_writeb(hdata, HDMI_AVI_CON, 967 HDMI_AVI_CON_DO_NOT_TRANSMIT); 968 hdmi_reg_writeb(hdata, HDMI_AUI_CON, HDMI_AUI_CON_NO_TRAN); 969 return; 970 } 971 972 switch (infoframe->any.type) { 973 case HDMI_INFOFRAME_TYPE_AVI: 974 hdmi_reg_writeb(hdata, HDMI_AVI_CON, HDMI_AVI_CON_EVERY_VSYNC); 975 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER0, infoframe->any.type); 976 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER1, 977 infoframe->any.version); 978 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER2, infoframe->any.length); 979 hdr_sum = infoframe->any.type + infoframe->any.version + 980 infoframe->any.length; 981 982 /* Output format zero hardcoded ,RGB YBCR selection */ 983 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(1), 0 << 5 | 984 AVI_ACTIVE_FORMAT_VALID | 985 AVI_UNDERSCANNED_DISPLAY_VALID); 986 987 /* 988 * Set the aspect ratio as per the mode, mentioned in 989 * Table 9 AVI InfoFrame Data Byte 2 of CEA-861-D Standard 990 */ 991 switch (hdata->mode_conf.aspect_ratio) { 992 case HDMI_PICTURE_ASPECT_4_3: 993 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2), 994 hdata->mode_conf.aspect_ratio | 995 AVI_4_3_CENTER_RATIO); 996 break; 997 case HDMI_PICTURE_ASPECT_16_9: 998 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2), 999 hdata->mode_conf.aspect_ratio | 1000 AVI_16_9_CENTER_RATIO); 1001 break; 1002 case HDMI_PICTURE_ASPECT_NONE: 1003 default: 1004 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2), 1005 hdata->mode_conf.aspect_ratio | 1006 AVI_SAME_AS_PIC_ASPECT_RATIO); 1007 break; 1008 } 1009 1010 vic = hdata->mode_conf.cea_video_id; 1011 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(4), vic); 1012 1013 chksum = hdmi_chksum(hdata, HDMI_AVI_BYTE(1), 1014 infoframe->any.length, hdr_sum); 1015 DRM_DEBUG_KMS("AVI checksum = 0x%x\n", chksum); 1016 hdmi_reg_writeb(hdata, HDMI_AVI_CHECK_SUM, chksum); 1017 break; 1018 case HDMI_INFOFRAME_TYPE_AUDIO: 1019 hdmi_reg_writeb(hdata, HDMI_AUI_CON, 0x02); 1020 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER0, infoframe->any.type); 1021 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER1, 1022 infoframe->any.version); 1023 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER2, infoframe->any.length); 1024 hdr_sum = infoframe->any.type + infoframe->any.version + 1025 infoframe->any.length; 1026 chksum = hdmi_chksum(hdata, HDMI_AUI_BYTE(1), 1027 infoframe->any.length, hdr_sum); 1028 DRM_DEBUG_KMS("AUI checksum = 0x%x\n", chksum); 1029 hdmi_reg_writeb(hdata, HDMI_AUI_CHECK_SUM, chksum); 1030 break; 1031 default: 1032 break; 1033 } 1034 } 1035 1036 static enum drm_connector_status hdmi_detect(struct drm_connector *connector, 1037 bool force) 1038 { 1039 struct hdmi_context *hdata = ctx_from_connector(connector); 1040 1041 hdata->hpd = gpio_get_value(hdata->hpd_gpio); 1042 1043 return hdata->hpd ? connector_status_connected : 1044 connector_status_disconnected; 1045 } 1046 1047 static void hdmi_connector_destroy(struct drm_connector *connector) 1048 { 1049 drm_connector_unregister(connector); 1050 drm_connector_cleanup(connector); 1051 } 1052 1053 static struct drm_connector_funcs hdmi_connector_funcs = { 1054 .dpms = drm_atomic_helper_connector_dpms, 1055 .fill_modes = drm_helper_probe_single_connector_modes, 1056 .detect = hdmi_detect, 1057 .destroy = hdmi_connector_destroy, 1058 .reset = drm_atomic_helper_connector_reset, 1059 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1060 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1061 }; 1062 1063 static int hdmi_get_modes(struct drm_connector *connector) 1064 { 1065 struct hdmi_context *hdata = ctx_from_connector(connector); 1066 struct edid *edid; 1067 1068 if (!hdata->ddc_adpt) 1069 return -ENODEV; 1070 1071 edid = drm_get_edid(connector, hdata->ddc_adpt); 1072 if (!edid) 1073 return -ENODEV; 1074 1075 hdata->dvi_mode = !drm_detect_hdmi_monitor(edid); 1076 DRM_DEBUG_KMS("%s : width[%d] x height[%d]\n", 1077 (hdata->dvi_mode ? "dvi monitor" : "hdmi monitor"), 1078 edid->width_cm, edid->height_cm); 1079 1080 drm_mode_connector_update_edid_property(connector, edid); 1081 1082 return drm_add_edid_modes(connector, edid); 1083 } 1084 1085 static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock) 1086 { 1087 int i; 1088 1089 for (i = 0; i < hdata->phy_conf_count; i++) 1090 if (hdata->phy_confs[i].pixel_clock == pixel_clock) 1091 return i; 1092 1093 DRM_DEBUG_KMS("Could not find phy config for %d\n", pixel_clock); 1094 return -EINVAL; 1095 } 1096 1097 static int hdmi_mode_valid(struct drm_connector *connector, 1098 struct drm_display_mode *mode) 1099 { 1100 struct hdmi_context *hdata = ctx_from_connector(connector); 1101 int ret; 1102 1103 DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n", 1104 mode->hdisplay, mode->vdisplay, mode->vrefresh, 1105 (mode->flags & DRM_MODE_FLAG_INTERLACE) ? true : 1106 false, mode->clock * 1000); 1107 1108 ret = mixer_check_mode(mode); 1109 if (ret) 1110 return MODE_BAD; 1111 1112 ret = hdmi_find_phy_conf(hdata, mode->clock * 1000); 1113 if (ret < 0) 1114 return MODE_BAD; 1115 1116 return MODE_OK; 1117 } 1118 1119 static struct drm_encoder *hdmi_best_encoder(struct drm_connector *connector) 1120 { 1121 struct hdmi_context *hdata = ctx_from_connector(connector); 1122 1123 return hdata->encoder; 1124 } 1125 1126 static struct drm_connector_helper_funcs hdmi_connector_helper_funcs = { 1127 .get_modes = hdmi_get_modes, 1128 .mode_valid = hdmi_mode_valid, 1129 .best_encoder = hdmi_best_encoder, 1130 }; 1131 1132 static int hdmi_create_connector(struct exynos_drm_display *display, 1133 struct drm_encoder *encoder) 1134 { 1135 struct hdmi_context *hdata = display_to_hdmi(display); 1136 struct drm_connector *connector = &hdata->connector; 1137 int ret; 1138 1139 hdata->encoder = encoder; 1140 connector->interlace_allowed = true; 1141 connector->polled = DRM_CONNECTOR_POLL_HPD; 1142 1143 ret = drm_connector_init(hdata->drm_dev, connector, 1144 &hdmi_connector_funcs, DRM_MODE_CONNECTOR_HDMIA); 1145 if (ret) { 1146 DRM_ERROR("Failed to initialize connector with drm\n"); 1147 return ret; 1148 } 1149 1150 drm_connector_helper_add(connector, &hdmi_connector_helper_funcs); 1151 drm_connector_register(connector); 1152 drm_mode_connector_attach_encoder(connector, encoder); 1153 1154 return 0; 1155 } 1156 1157 static void hdmi_mode_fixup(struct exynos_drm_display *display, 1158 struct drm_connector *connector, 1159 const struct drm_display_mode *mode, 1160 struct drm_display_mode *adjusted_mode) 1161 { 1162 struct drm_display_mode *m; 1163 int mode_ok; 1164 1165 DRM_DEBUG_KMS("%s\n", __FILE__); 1166 1167 drm_mode_set_crtcinfo(adjusted_mode, 0); 1168 1169 mode_ok = hdmi_mode_valid(connector, adjusted_mode); 1170 1171 /* just return if user desired mode exists. */ 1172 if (mode_ok == MODE_OK) 1173 return; 1174 1175 /* 1176 * otherwise, find the most suitable mode among modes and change it 1177 * to adjusted_mode. 1178 */ 1179 list_for_each_entry(m, &connector->modes, head) { 1180 mode_ok = hdmi_mode_valid(connector, m); 1181 1182 if (mode_ok == MODE_OK) { 1183 DRM_INFO("desired mode doesn't exist so\n"); 1184 DRM_INFO("use the most suitable mode among modes.\n"); 1185 1186 DRM_DEBUG_KMS("Adjusted Mode: [%d]x[%d] [%d]Hz\n", 1187 m->hdisplay, m->vdisplay, m->vrefresh); 1188 1189 drm_mode_copy(adjusted_mode, m); 1190 break; 1191 } 1192 } 1193 } 1194 1195 static void hdmi_set_acr(u32 freq, u8 *acr) 1196 { 1197 u32 n, cts; 1198 1199 switch (freq) { 1200 case 32000: 1201 n = 4096; 1202 cts = 27000; 1203 break; 1204 case 44100: 1205 n = 6272; 1206 cts = 30000; 1207 break; 1208 case 88200: 1209 n = 12544; 1210 cts = 30000; 1211 break; 1212 case 176400: 1213 n = 25088; 1214 cts = 30000; 1215 break; 1216 case 48000: 1217 n = 6144; 1218 cts = 27000; 1219 break; 1220 case 96000: 1221 n = 12288; 1222 cts = 27000; 1223 break; 1224 case 192000: 1225 n = 24576; 1226 cts = 27000; 1227 break; 1228 default: 1229 n = 0; 1230 cts = 0; 1231 break; 1232 } 1233 1234 acr[1] = cts >> 16; 1235 acr[2] = cts >> 8 & 0xff; 1236 acr[3] = cts & 0xff; 1237 1238 acr[4] = n >> 16; 1239 acr[5] = n >> 8 & 0xff; 1240 acr[6] = n & 0xff; 1241 } 1242 1243 static void hdmi_reg_acr(struct hdmi_context *hdata, u8 *acr) 1244 { 1245 hdmi_reg_writeb(hdata, HDMI_ACR_N0, acr[6]); 1246 hdmi_reg_writeb(hdata, HDMI_ACR_N1, acr[5]); 1247 hdmi_reg_writeb(hdata, HDMI_ACR_N2, acr[4]); 1248 hdmi_reg_writeb(hdata, HDMI_ACR_MCTS0, acr[3]); 1249 hdmi_reg_writeb(hdata, HDMI_ACR_MCTS1, acr[2]); 1250 hdmi_reg_writeb(hdata, HDMI_ACR_MCTS2, acr[1]); 1251 hdmi_reg_writeb(hdata, HDMI_ACR_CTS0, acr[3]); 1252 hdmi_reg_writeb(hdata, HDMI_ACR_CTS1, acr[2]); 1253 hdmi_reg_writeb(hdata, HDMI_ACR_CTS2, acr[1]); 1254 1255 if (hdata->type == HDMI_TYPE13) 1256 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 4); 1257 else 1258 hdmi_reg_writeb(hdata, HDMI_ACR_CON, 4); 1259 } 1260 1261 static void hdmi_audio_init(struct hdmi_context *hdata) 1262 { 1263 u32 sample_rate, bits_per_sample; 1264 u32 data_num, bit_ch, sample_frq; 1265 u32 val; 1266 u8 acr[7]; 1267 1268 sample_rate = 44100; 1269 bits_per_sample = 16; 1270 1271 switch (bits_per_sample) { 1272 case 20: 1273 data_num = 2; 1274 bit_ch = 1; 1275 break; 1276 case 24: 1277 data_num = 3; 1278 bit_ch = 1; 1279 break; 1280 default: 1281 data_num = 1; 1282 bit_ch = 0; 1283 break; 1284 } 1285 1286 hdmi_set_acr(sample_rate, acr); 1287 hdmi_reg_acr(hdata, acr); 1288 1289 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CON, HDMI_I2S_IN_DISABLE 1290 | HDMI_I2S_AUD_I2S | HDMI_I2S_CUV_I2S_ENABLE 1291 | HDMI_I2S_MUX_ENABLE); 1292 1293 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CH, HDMI_I2S_CH0_EN 1294 | HDMI_I2S_CH1_EN | HDMI_I2S_CH2_EN); 1295 1296 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CUV, HDMI_I2S_CUV_RL_EN); 1297 1298 sample_frq = (sample_rate == 44100) ? 0 : 1299 (sample_rate == 48000) ? 2 : 1300 (sample_rate == 32000) ? 3 : 1301 (sample_rate == 96000) ? 0xa : 0x0; 1302 1303 hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_DIS); 1304 hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_EN); 1305 1306 val = hdmi_reg_read(hdata, HDMI_I2S_DSD_CON) | 0x01; 1307 hdmi_reg_writeb(hdata, HDMI_I2S_DSD_CON, val); 1308 1309 /* Configuration I2S input ports. Configure I2S_PIN_SEL_0~4 */ 1310 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_0, HDMI_I2S_SEL_SCLK(5) 1311 | HDMI_I2S_SEL_LRCK(6)); 1312 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_1, HDMI_I2S_SEL_SDATA1(1) 1313 | HDMI_I2S_SEL_SDATA2(4)); 1314 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_2, HDMI_I2S_SEL_SDATA3(1) 1315 | HDMI_I2S_SEL_SDATA2(2)); 1316 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_3, HDMI_I2S_SEL_DSD(0)); 1317 1318 /* I2S_CON_1 & 2 */ 1319 hdmi_reg_writeb(hdata, HDMI_I2S_CON_1, HDMI_I2S_SCLK_FALLING_EDGE 1320 | HDMI_I2S_L_CH_LOW_POL); 1321 hdmi_reg_writeb(hdata, HDMI_I2S_CON_2, HDMI_I2S_MSB_FIRST_MODE 1322 | HDMI_I2S_SET_BIT_CH(bit_ch) 1323 | HDMI_I2S_SET_SDATA_BIT(data_num) 1324 | HDMI_I2S_BASIC_FORMAT); 1325 1326 /* Configure register related to CUV information */ 1327 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_0, HDMI_I2S_CH_STATUS_MODE_0 1328 | HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH 1329 | HDMI_I2S_COPYRIGHT 1330 | HDMI_I2S_LINEAR_PCM 1331 | HDMI_I2S_CONSUMER_FORMAT); 1332 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_1, HDMI_I2S_CD_PLAYER); 1333 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_2, HDMI_I2S_SET_SOURCE_NUM(0)); 1334 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_3, HDMI_I2S_CLK_ACCUR_LEVEL_2 1335 | HDMI_I2S_SET_SMP_FREQ(sample_frq)); 1336 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_4, 1337 HDMI_I2S_ORG_SMP_FREQ_44_1 1338 | HDMI_I2S_WORD_LEN_MAX24_24BITS 1339 | HDMI_I2S_WORD_LEN_MAX_24BITS); 1340 1341 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_CON, HDMI_I2S_CH_STATUS_RELOAD); 1342 } 1343 1344 static void hdmi_audio_control(struct hdmi_context *hdata, bool onoff) 1345 { 1346 if (hdata->dvi_mode) 1347 return; 1348 1349 hdmi_reg_writeb(hdata, HDMI_AUI_CON, onoff ? 2 : 0); 1350 hdmi_reg_writemask(hdata, HDMI_CON_0, onoff ? 1351 HDMI_ASP_EN : HDMI_ASP_DIS, HDMI_ASP_MASK); 1352 } 1353 1354 static void hdmi_start(struct hdmi_context *hdata, bool start) 1355 { 1356 u32 val = start ? HDMI_TG_EN : 0; 1357 1358 if (hdata->current_mode.flags & DRM_MODE_FLAG_INTERLACE) 1359 val |= HDMI_FIELD_EN; 1360 1361 hdmi_reg_writemask(hdata, HDMI_CON_0, val, HDMI_EN); 1362 hdmi_reg_writemask(hdata, HDMI_TG_CMD, val, HDMI_TG_EN | HDMI_FIELD_EN); 1363 } 1364 1365 static void hdmi_conf_init(struct hdmi_context *hdata) 1366 { 1367 union hdmi_infoframe infoframe; 1368 1369 /* disable HPD interrupts from HDMI IP block, use GPIO instead */ 1370 hdmi_reg_writemask(hdata, HDMI_INTC_CON, 0, HDMI_INTC_EN_GLOBAL | 1371 HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG); 1372 1373 /* choose HDMI mode */ 1374 hdmi_reg_writemask(hdata, HDMI_MODE_SEL, 1375 HDMI_MODE_HDMI_EN, HDMI_MODE_MASK); 1376 /* Apply Video preable and Guard band in HDMI mode only */ 1377 hdmi_reg_writeb(hdata, HDMI_CON_2, 0); 1378 /* disable bluescreen */ 1379 hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_BLUE_SCR_EN); 1380 1381 if (hdata->dvi_mode) { 1382 /* choose DVI mode */ 1383 hdmi_reg_writemask(hdata, HDMI_MODE_SEL, 1384 HDMI_MODE_DVI_EN, HDMI_MODE_MASK); 1385 hdmi_reg_writeb(hdata, HDMI_CON_2, 1386 HDMI_VID_PREAMBLE_DIS | HDMI_GUARD_BAND_DIS); 1387 } 1388 1389 if (hdata->type == HDMI_TYPE13) { 1390 /* choose bluescreen (fecal) color */ 1391 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_0, 0x12); 1392 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_1, 0x34); 1393 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_2, 0x56); 1394 1395 /* enable AVI packet every vsync, fixes purple line problem */ 1396 hdmi_reg_writeb(hdata, HDMI_V13_AVI_CON, 0x02); 1397 /* force RGB, look to CEA-861-D, table 7 for more detail */ 1398 hdmi_reg_writeb(hdata, HDMI_V13_AVI_BYTE(0), 0 << 5); 1399 hdmi_reg_writemask(hdata, HDMI_CON_1, 0x10 << 5, 0x11 << 5); 1400 1401 hdmi_reg_writeb(hdata, HDMI_V13_SPD_CON, 0x02); 1402 hdmi_reg_writeb(hdata, HDMI_V13_AUI_CON, 0x02); 1403 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 0x04); 1404 } else { 1405 infoframe.any.type = HDMI_INFOFRAME_TYPE_AVI; 1406 infoframe.any.version = HDMI_AVI_VERSION; 1407 infoframe.any.length = HDMI_AVI_LENGTH; 1408 hdmi_reg_infoframe(hdata, &infoframe); 1409 1410 infoframe.any.type = HDMI_INFOFRAME_TYPE_AUDIO; 1411 infoframe.any.version = HDMI_AUI_VERSION; 1412 infoframe.any.length = HDMI_AUI_LENGTH; 1413 hdmi_reg_infoframe(hdata, &infoframe); 1414 1415 /* enable AVI packet every vsync, fixes purple line problem */ 1416 hdmi_reg_writemask(hdata, HDMI_CON_1, 2, 3 << 5); 1417 } 1418 } 1419 1420 static void hdmi_v13_mode_apply(struct hdmi_context *hdata) 1421 { 1422 const struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v13_conf.tg; 1423 const struct hdmi_v13_core_regs *core = 1424 &hdata->mode_conf.conf.v13_conf.core; 1425 int tries; 1426 1427 /* setting core registers */ 1428 hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]); 1429 hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]); 1430 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_0, core->v_blank[0]); 1431 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_1, core->v_blank[1]); 1432 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_2, core->v_blank[2]); 1433 hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_0, core->h_v_line[0]); 1434 hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_1, core->h_v_line[1]); 1435 hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_2, core->h_v_line[2]); 1436 hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]); 1437 hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]); 1438 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_0, core->v_blank_f[0]); 1439 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_1, core->v_blank_f[1]); 1440 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_2, core->v_blank_f[2]); 1441 hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_0, core->h_sync_gen[0]); 1442 hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_1, core->h_sync_gen[1]); 1443 hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_2, core->h_sync_gen[2]); 1444 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_0, core->v_sync_gen1[0]); 1445 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_1, core->v_sync_gen1[1]); 1446 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_2, core->v_sync_gen1[2]); 1447 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_0, core->v_sync_gen2[0]); 1448 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_1, core->v_sync_gen2[1]); 1449 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_2, core->v_sync_gen2[2]); 1450 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_0, core->v_sync_gen3[0]); 1451 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_1, core->v_sync_gen3[1]); 1452 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_2, core->v_sync_gen3[2]); 1453 /* Timing generator registers */ 1454 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz[0]); 1455 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz[1]); 1456 hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_L, tg->hact_st[0]); 1457 hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_H, tg->hact_st[1]); 1458 hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_L, tg->hact_sz[0]); 1459 hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_H, tg->hact_sz[1]); 1460 hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_L, tg->v_fsz[0]); 1461 hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_H, tg->v_fsz[1]); 1462 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_L, tg->vsync[0]); 1463 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_H, tg->vsync[1]); 1464 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_L, tg->vsync2[0]); 1465 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_H, tg->vsync2[1]); 1466 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_L, tg->vact_st[0]); 1467 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_H, tg->vact_st[1]); 1468 hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_L, tg->vact_sz[0]); 1469 hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_H, tg->vact_sz[1]); 1470 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_L, tg->field_chg[0]); 1471 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg[1]); 1472 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2[0]); 1473 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2[1]); 1474 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi[0]); 1475 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi[1]); 1476 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi[0]); 1477 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi[1]); 1478 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi[0]); 1479 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi[1]); 1480 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi[0]); 1481 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi[1]); 1482 1483 /* waiting for HDMIPHY's PLL to get to steady state */ 1484 for (tries = 100; tries; --tries) { 1485 u32 val = hdmi_reg_read(hdata, HDMI_V13_PHY_STATUS); 1486 if (val & HDMI_PHY_STATUS_READY) 1487 break; 1488 usleep_range(1000, 2000); 1489 } 1490 /* steady state not achieved */ 1491 if (tries == 0) { 1492 DRM_ERROR("hdmiphy's pll could not reach steady state.\n"); 1493 hdmi_regs_dump(hdata, "timing apply"); 1494 } 1495 1496 clk_disable_unprepare(hdata->res.sclk_hdmi); 1497 clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_hdmiphy); 1498 clk_prepare_enable(hdata->res.sclk_hdmi); 1499 1500 /* enable HDMI and timing generator */ 1501 hdmi_start(hdata, true); 1502 } 1503 1504 static void hdmi_v14_mode_apply(struct hdmi_context *hdata) 1505 { 1506 const struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v14_conf.tg; 1507 const struct hdmi_v14_core_regs *core = 1508 &hdata->mode_conf.conf.v14_conf.core; 1509 int tries; 1510 1511 /* setting core registers */ 1512 hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]); 1513 hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]); 1514 hdmi_reg_writeb(hdata, HDMI_V2_BLANK_0, core->v2_blank[0]); 1515 hdmi_reg_writeb(hdata, HDMI_V2_BLANK_1, core->v2_blank[1]); 1516 hdmi_reg_writeb(hdata, HDMI_V1_BLANK_0, core->v1_blank[0]); 1517 hdmi_reg_writeb(hdata, HDMI_V1_BLANK_1, core->v1_blank[1]); 1518 hdmi_reg_writeb(hdata, HDMI_V_LINE_0, core->v_line[0]); 1519 hdmi_reg_writeb(hdata, HDMI_V_LINE_1, core->v_line[1]); 1520 hdmi_reg_writeb(hdata, HDMI_H_LINE_0, core->h_line[0]); 1521 hdmi_reg_writeb(hdata, HDMI_H_LINE_1, core->h_line[1]); 1522 hdmi_reg_writeb(hdata, HDMI_HSYNC_POL, core->hsync_pol[0]); 1523 hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]); 1524 hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]); 1525 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F0_0, core->v_blank_f0[0]); 1526 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F0_1, core->v_blank_f0[1]); 1527 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F1_0, core->v_blank_f1[0]); 1528 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F1_1, core->v_blank_f1[1]); 1529 hdmi_reg_writeb(hdata, HDMI_H_SYNC_START_0, core->h_sync_start[0]); 1530 hdmi_reg_writeb(hdata, HDMI_H_SYNC_START_1, core->h_sync_start[1]); 1531 hdmi_reg_writeb(hdata, HDMI_H_SYNC_END_0, core->h_sync_end[0]); 1532 hdmi_reg_writeb(hdata, HDMI_H_SYNC_END_1, core->h_sync_end[1]); 1533 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_2_0, 1534 core->v_sync_line_bef_2[0]); 1535 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_2_1, 1536 core->v_sync_line_bef_2[1]); 1537 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_1_0, 1538 core->v_sync_line_bef_1[0]); 1539 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_1_1, 1540 core->v_sync_line_bef_1[1]); 1541 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_2_0, 1542 core->v_sync_line_aft_2[0]); 1543 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_2_1, 1544 core->v_sync_line_aft_2[1]); 1545 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_1_0, 1546 core->v_sync_line_aft_1[0]); 1547 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_1_1, 1548 core->v_sync_line_aft_1[1]); 1549 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_0, 1550 core->v_sync_line_aft_pxl_2[0]); 1551 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_1, 1552 core->v_sync_line_aft_pxl_2[1]); 1553 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_0, 1554 core->v_sync_line_aft_pxl_1[0]); 1555 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_1, 1556 core->v_sync_line_aft_pxl_1[1]); 1557 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F2_0, core->v_blank_f2[0]); 1558 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F2_1, core->v_blank_f2[1]); 1559 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F3_0, core->v_blank_f3[0]); 1560 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F3_1, core->v_blank_f3[1]); 1561 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F4_0, core->v_blank_f4[0]); 1562 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F4_1, core->v_blank_f4[1]); 1563 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F5_0, core->v_blank_f5[0]); 1564 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F5_1, core->v_blank_f5[1]); 1565 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_3_0, 1566 core->v_sync_line_aft_3[0]); 1567 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_3_1, 1568 core->v_sync_line_aft_3[1]); 1569 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_4_0, 1570 core->v_sync_line_aft_4[0]); 1571 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_4_1, 1572 core->v_sync_line_aft_4[1]); 1573 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_5_0, 1574 core->v_sync_line_aft_5[0]); 1575 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_5_1, 1576 core->v_sync_line_aft_5[1]); 1577 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_6_0, 1578 core->v_sync_line_aft_6[0]); 1579 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_6_1, 1580 core->v_sync_line_aft_6[1]); 1581 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_0, 1582 core->v_sync_line_aft_pxl_3[0]); 1583 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_1, 1584 core->v_sync_line_aft_pxl_3[1]); 1585 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_0, 1586 core->v_sync_line_aft_pxl_4[0]); 1587 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_1, 1588 core->v_sync_line_aft_pxl_4[1]); 1589 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_0, 1590 core->v_sync_line_aft_pxl_5[0]); 1591 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_1, 1592 core->v_sync_line_aft_pxl_5[1]); 1593 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_0, 1594 core->v_sync_line_aft_pxl_6[0]); 1595 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_1, 1596 core->v_sync_line_aft_pxl_6[1]); 1597 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_1_0, core->vact_space_1[0]); 1598 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_1_1, core->vact_space_1[1]); 1599 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_2_0, core->vact_space_2[0]); 1600 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_2_1, core->vact_space_2[1]); 1601 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_3_0, core->vact_space_3[0]); 1602 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_3_1, core->vact_space_3[1]); 1603 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_4_0, core->vact_space_4[0]); 1604 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_4_1, core->vact_space_4[1]); 1605 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_5_0, core->vact_space_5[0]); 1606 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_5_1, core->vact_space_5[1]); 1607 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_6_0, core->vact_space_6[0]); 1608 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_6_1, core->vact_space_6[1]); 1609 1610 /* Timing generator registers */ 1611 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz[0]); 1612 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz[1]); 1613 hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_L, tg->hact_st[0]); 1614 hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_H, tg->hact_st[1]); 1615 hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_L, tg->hact_sz[0]); 1616 hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_H, tg->hact_sz[1]); 1617 hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_L, tg->v_fsz[0]); 1618 hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_H, tg->v_fsz[1]); 1619 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_L, tg->vsync[0]); 1620 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_H, tg->vsync[1]); 1621 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_L, tg->vsync2[0]); 1622 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_H, tg->vsync2[1]); 1623 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_L, tg->vact_st[0]); 1624 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_H, tg->vact_st[1]); 1625 hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_L, tg->vact_sz[0]); 1626 hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_H, tg->vact_sz[1]); 1627 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_L, tg->field_chg[0]); 1628 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg[1]); 1629 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2[0]); 1630 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2[1]); 1631 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST3_L, tg->vact_st3[0]); 1632 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST3_H, tg->vact_st3[1]); 1633 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST4_L, tg->vact_st4[0]); 1634 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST4_H, tg->vact_st4[1]); 1635 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi[0]); 1636 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi[1]); 1637 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi[0]); 1638 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi[1]); 1639 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi[0]); 1640 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi[1]); 1641 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi[0]); 1642 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi[1]); 1643 hdmi_reg_writeb(hdata, HDMI_TG_3D, tg->tg_3d[0]); 1644 1645 /* waiting for HDMIPHY's PLL to get to steady state */ 1646 for (tries = 100; tries; --tries) { 1647 u32 val = hdmi_reg_read(hdata, HDMI_PHY_STATUS_0); 1648 if (val & HDMI_PHY_STATUS_READY) 1649 break; 1650 usleep_range(1000, 2000); 1651 } 1652 /* steady state not achieved */ 1653 if (tries == 0) { 1654 DRM_ERROR("hdmiphy's pll could not reach steady state.\n"); 1655 hdmi_regs_dump(hdata, "timing apply"); 1656 } 1657 1658 clk_disable_unprepare(hdata->res.sclk_hdmi); 1659 clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_hdmiphy); 1660 clk_prepare_enable(hdata->res.sclk_hdmi); 1661 1662 /* enable HDMI and timing generator */ 1663 hdmi_start(hdata, true); 1664 } 1665 1666 static void hdmi_mode_apply(struct hdmi_context *hdata) 1667 { 1668 if (hdata->type == HDMI_TYPE13) 1669 hdmi_v13_mode_apply(hdata); 1670 else 1671 hdmi_v14_mode_apply(hdata); 1672 } 1673 1674 static void hdmiphy_conf_reset(struct hdmi_context *hdata) 1675 { 1676 u32 reg; 1677 1678 clk_disable_unprepare(hdata->res.sclk_hdmi); 1679 clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_pixel); 1680 clk_prepare_enable(hdata->res.sclk_hdmi); 1681 1682 /* operation mode */ 1683 hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE, 1684 HDMI_PHY_ENABLE_MODE_SET); 1685 1686 if (hdata->type == HDMI_TYPE13) 1687 reg = HDMI_V13_PHY_RSTOUT; 1688 else 1689 reg = HDMI_PHY_RSTOUT; 1690 1691 /* reset hdmiphy */ 1692 hdmi_reg_writemask(hdata, reg, ~0, HDMI_PHY_SW_RSTOUT); 1693 usleep_range(10000, 12000); 1694 hdmi_reg_writemask(hdata, reg, 0, HDMI_PHY_SW_RSTOUT); 1695 usleep_range(10000, 12000); 1696 } 1697 1698 static void hdmiphy_poweron(struct hdmi_context *hdata) 1699 { 1700 if (hdata->type != HDMI_TYPE14) 1701 return; 1702 1703 DRM_DEBUG_KMS("\n"); 1704 1705 /* For PHY Mode Setting */ 1706 hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE, 1707 HDMI_PHY_ENABLE_MODE_SET); 1708 /* Phy Power On */ 1709 hdmiphy_reg_writeb(hdata, HDMIPHY_POWER, 1710 HDMI_PHY_POWER_ON); 1711 /* For PHY Mode Setting */ 1712 hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE, 1713 HDMI_PHY_DISABLE_MODE_SET); 1714 /* PHY SW Reset */ 1715 hdmiphy_conf_reset(hdata); 1716 } 1717 1718 static void hdmiphy_poweroff(struct hdmi_context *hdata) 1719 { 1720 if (hdata->type != HDMI_TYPE14) 1721 return; 1722 1723 DRM_DEBUG_KMS("\n"); 1724 1725 /* PHY SW Reset */ 1726 hdmiphy_conf_reset(hdata); 1727 /* For PHY Mode Setting */ 1728 hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE, 1729 HDMI_PHY_ENABLE_MODE_SET); 1730 1731 /* PHY Power Off */ 1732 hdmiphy_reg_writeb(hdata, HDMIPHY_POWER, 1733 HDMI_PHY_POWER_OFF); 1734 1735 /* For PHY Mode Setting */ 1736 hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE, 1737 HDMI_PHY_DISABLE_MODE_SET); 1738 } 1739 1740 static void hdmiphy_conf_apply(struct hdmi_context *hdata) 1741 { 1742 int ret; 1743 int i; 1744 1745 /* pixel clock */ 1746 i = hdmi_find_phy_conf(hdata, hdata->mode_conf.pixel_clock); 1747 if (i < 0) { 1748 DRM_ERROR("failed to find hdmiphy conf\n"); 1749 return; 1750 } 1751 1752 ret = hdmiphy_reg_write_buf(hdata, 0, hdata->phy_confs[i].conf, 32); 1753 if (ret) { 1754 DRM_ERROR("failed to configure hdmiphy\n"); 1755 return; 1756 } 1757 1758 usleep_range(10000, 12000); 1759 1760 ret = hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE, 1761 HDMI_PHY_DISABLE_MODE_SET); 1762 if (ret) { 1763 DRM_ERROR("failed to enable hdmiphy\n"); 1764 return; 1765 } 1766 1767 } 1768 1769 static void hdmi_conf_apply(struct hdmi_context *hdata) 1770 { 1771 hdmiphy_conf_reset(hdata); 1772 hdmiphy_conf_apply(hdata); 1773 1774 mutex_lock(&hdata->hdmi_mutex); 1775 hdmi_start(hdata, false); 1776 hdmi_conf_init(hdata); 1777 mutex_unlock(&hdata->hdmi_mutex); 1778 1779 hdmi_audio_init(hdata); 1780 1781 /* setting core registers */ 1782 hdmi_mode_apply(hdata); 1783 hdmi_audio_control(hdata, true); 1784 1785 hdmi_regs_dump(hdata, "start"); 1786 } 1787 1788 static void hdmi_set_reg(u8 *reg_pair, int num_bytes, u32 value) 1789 { 1790 int i; 1791 BUG_ON(num_bytes > 4); 1792 for (i = 0; i < num_bytes; i++) 1793 reg_pair[i] = (value >> (8 * i)) & 0xff; 1794 } 1795 1796 static void hdmi_v13_mode_set(struct hdmi_context *hdata, 1797 struct drm_display_mode *m) 1798 { 1799 struct hdmi_v13_core_regs *core = &hdata->mode_conf.conf.v13_conf.core; 1800 struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v13_conf.tg; 1801 unsigned int val; 1802 1803 hdata->mode_conf.cea_video_id = 1804 drm_match_cea_mode((struct drm_display_mode *)m); 1805 hdata->mode_conf.pixel_clock = m->clock * 1000; 1806 hdata->mode_conf.aspect_ratio = m->picture_aspect_ratio; 1807 1808 hdmi_set_reg(core->h_blank, 2, m->htotal - m->hdisplay); 1809 hdmi_set_reg(core->h_v_line, 3, (m->htotal << 12) | m->vtotal); 1810 1811 val = (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0; 1812 hdmi_set_reg(core->vsync_pol, 1, val); 1813 1814 val = (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0; 1815 hdmi_set_reg(core->int_pro_mode, 1, val); 1816 1817 val = (m->hsync_start - m->hdisplay - 2); 1818 val |= ((m->hsync_end - m->hdisplay - 2) << 10); 1819 val |= ((m->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0)<<20; 1820 hdmi_set_reg(core->h_sync_gen, 3, val); 1821 1822 /* 1823 * Quirk requirement for exynos HDMI IP design, 1824 * 2 pixels less than the actual calculation for hsync_start 1825 * and end. 1826 */ 1827 1828 /* Following values & calculations differ for different type of modes */ 1829 if (m->flags & DRM_MODE_FLAG_INTERLACE) { 1830 /* Interlaced Mode */ 1831 val = ((m->vsync_end - m->vdisplay) / 2); 1832 val |= ((m->vsync_start - m->vdisplay) / 2) << 12; 1833 hdmi_set_reg(core->v_sync_gen1, 3, val); 1834 1835 val = m->vtotal / 2; 1836 val |= ((m->vtotal - m->vdisplay) / 2) << 11; 1837 hdmi_set_reg(core->v_blank, 3, val); 1838 1839 val = (m->vtotal + 1840 ((m->vsync_end - m->vsync_start) * 4) + 5) / 2; 1841 val |= m->vtotal << 11; 1842 hdmi_set_reg(core->v_blank_f, 3, val); 1843 1844 val = ((m->vtotal / 2) + 7); 1845 val |= ((m->vtotal / 2) + 2) << 12; 1846 hdmi_set_reg(core->v_sync_gen2, 3, val); 1847 1848 val = ((m->htotal / 2) + (m->hsync_start - m->hdisplay)); 1849 val |= ((m->htotal / 2) + 1850 (m->hsync_start - m->hdisplay)) << 12; 1851 hdmi_set_reg(core->v_sync_gen3, 3, val); 1852 1853 hdmi_set_reg(tg->vact_st, 2, (m->vtotal - m->vdisplay) / 2); 1854 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay / 2); 1855 1856 hdmi_set_reg(tg->vact_st2, 2, 0x249);/* Reset value + 1*/ 1857 } else { 1858 /* Progressive Mode */ 1859 1860 val = m->vtotal; 1861 val |= (m->vtotal - m->vdisplay) << 11; 1862 hdmi_set_reg(core->v_blank, 3, val); 1863 1864 hdmi_set_reg(core->v_blank_f, 3, 0); 1865 1866 val = (m->vsync_end - m->vdisplay); 1867 val |= ((m->vsync_start - m->vdisplay) << 12); 1868 hdmi_set_reg(core->v_sync_gen1, 3, val); 1869 1870 hdmi_set_reg(core->v_sync_gen2, 3, 0x1001);/* Reset value */ 1871 hdmi_set_reg(core->v_sync_gen3, 3, 0x1001);/* Reset value */ 1872 hdmi_set_reg(tg->vact_st, 2, m->vtotal - m->vdisplay); 1873 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay); 1874 hdmi_set_reg(tg->vact_st2, 2, 0x248); /* Reset value */ 1875 } 1876 1877 /* Timing generator registers */ 1878 hdmi_set_reg(tg->cmd, 1, 0x0); 1879 hdmi_set_reg(tg->h_fsz, 2, m->htotal); 1880 hdmi_set_reg(tg->hact_st, 2, m->htotal - m->hdisplay); 1881 hdmi_set_reg(tg->hact_sz, 2, m->hdisplay); 1882 hdmi_set_reg(tg->v_fsz, 2, m->vtotal); 1883 hdmi_set_reg(tg->vsync, 2, 0x1); 1884 hdmi_set_reg(tg->vsync2, 2, 0x233); /* Reset value */ 1885 hdmi_set_reg(tg->field_chg, 2, 0x233); /* Reset value */ 1886 hdmi_set_reg(tg->vsync_top_hdmi, 2, 0x1); /* Reset value */ 1887 hdmi_set_reg(tg->vsync_bot_hdmi, 2, 0x233); /* Reset value */ 1888 hdmi_set_reg(tg->field_top_hdmi, 2, 0x1); /* Reset value */ 1889 hdmi_set_reg(tg->field_bot_hdmi, 2, 0x233); /* Reset value */ 1890 hdmi_set_reg(tg->tg_3d, 1, 0x0); /* Not used */ 1891 } 1892 1893 static void hdmi_v14_mode_set(struct hdmi_context *hdata, 1894 struct drm_display_mode *m) 1895 { 1896 struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v14_conf.tg; 1897 struct hdmi_v14_core_regs *core = 1898 &hdata->mode_conf.conf.v14_conf.core; 1899 1900 hdata->mode_conf.cea_video_id = 1901 drm_match_cea_mode((struct drm_display_mode *)m); 1902 hdata->mode_conf.pixel_clock = m->clock * 1000; 1903 hdata->mode_conf.aspect_ratio = m->picture_aspect_ratio; 1904 1905 hdmi_set_reg(core->h_blank, 2, m->htotal - m->hdisplay); 1906 hdmi_set_reg(core->v_line, 2, m->vtotal); 1907 hdmi_set_reg(core->h_line, 2, m->htotal); 1908 hdmi_set_reg(core->hsync_pol, 1, 1909 (m->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0); 1910 hdmi_set_reg(core->vsync_pol, 1, 1911 (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0); 1912 hdmi_set_reg(core->int_pro_mode, 1, 1913 (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0); 1914 1915 /* 1916 * Quirk requirement for exynos 5 HDMI IP design, 1917 * 2 pixels less than the actual calculation for hsync_start 1918 * and end. 1919 */ 1920 1921 /* Following values & calculations differ for different type of modes */ 1922 if (m->flags & DRM_MODE_FLAG_INTERLACE) { 1923 /* Interlaced Mode */ 1924 hdmi_set_reg(core->v_sync_line_bef_2, 2, 1925 (m->vsync_end - m->vdisplay) / 2); 1926 hdmi_set_reg(core->v_sync_line_bef_1, 2, 1927 (m->vsync_start - m->vdisplay) / 2); 1928 hdmi_set_reg(core->v2_blank, 2, m->vtotal / 2); 1929 hdmi_set_reg(core->v1_blank, 2, (m->vtotal - m->vdisplay) / 2); 1930 hdmi_set_reg(core->v_blank_f0, 2, m->vtotal - m->vdisplay / 2); 1931 hdmi_set_reg(core->v_blank_f1, 2, m->vtotal); 1932 hdmi_set_reg(core->v_sync_line_aft_2, 2, (m->vtotal / 2) + 7); 1933 hdmi_set_reg(core->v_sync_line_aft_1, 2, (m->vtotal / 2) + 2); 1934 hdmi_set_reg(core->v_sync_line_aft_pxl_2, 2, 1935 (m->htotal / 2) + (m->hsync_start - m->hdisplay)); 1936 hdmi_set_reg(core->v_sync_line_aft_pxl_1, 2, 1937 (m->htotal / 2) + (m->hsync_start - m->hdisplay)); 1938 hdmi_set_reg(tg->vact_st, 2, (m->vtotal - m->vdisplay) / 2); 1939 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay / 2); 1940 hdmi_set_reg(tg->vact_st2, 2, m->vtotal - m->vdisplay / 2); 1941 hdmi_set_reg(tg->vsync2, 2, (m->vtotal / 2) + 1); 1942 hdmi_set_reg(tg->vsync_bot_hdmi, 2, (m->vtotal / 2) + 1); 1943 hdmi_set_reg(tg->field_bot_hdmi, 2, (m->vtotal / 2) + 1); 1944 hdmi_set_reg(tg->vact_st3, 2, 0x0); 1945 hdmi_set_reg(tg->vact_st4, 2, 0x0); 1946 } else { 1947 /* Progressive Mode */ 1948 hdmi_set_reg(core->v_sync_line_bef_2, 2, 1949 m->vsync_end - m->vdisplay); 1950 hdmi_set_reg(core->v_sync_line_bef_1, 2, 1951 m->vsync_start - m->vdisplay); 1952 hdmi_set_reg(core->v2_blank, 2, m->vtotal); 1953 hdmi_set_reg(core->v1_blank, 2, m->vtotal - m->vdisplay); 1954 hdmi_set_reg(core->v_blank_f0, 2, 0xffff); 1955 hdmi_set_reg(core->v_blank_f1, 2, 0xffff); 1956 hdmi_set_reg(core->v_sync_line_aft_2, 2, 0xffff); 1957 hdmi_set_reg(core->v_sync_line_aft_1, 2, 0xffff); 1958 hdmi_set_reg(core->v_sync_line_aft_pxl_2, 2, 0xffff); 1959 hdmi_set_reg(core->v_sync_line_aft_pxl_1, 2, 0xffff); 1960 hdmi_set_reg(tg->vact_st, 2, m->vtotal - m->vdisplay); 1961 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay); 1962 hdmi_set_reg(tg->vact_st2, 2, 0x248); /* Reset value */ 1963 hdmi_set_reg(tg->vact_st3, 2, 0x47b); /* Reset value */ 1964 hdmi_set_reg(tg->vact_st4, 2, 0x6ae); /* Reset value */ 1965 hdmi_set_reg(tg->vsync2, 2, 0x233); /* Reset value */ 1966 hdmi_set_reg(tg->vsync_bot_hdmi, 2, 0x233); /* Reset value */ 1967 hdmi_set_reg(tg->field_bot_hdmi, 2, 0x233); /* Reset value */ 1968 } 1969 1970 /* Following values & calculations are same irrespective of mode type */ 1971 hdmi_set_reg(core->h_sync_start, 2, m->hsync_start - m->hdisplay - 2); 1972 hdmi_set_reg(core->h_sync_end, 2, m->hsync_end - m->hdisplay - 2); 1973 hdmi_set_reg(core->vact_space_1, 2, 0xffff); 1974 hdmi_set_reg(core->vact_space_2, 2, 0xffff); 1975 hdmi_set_reg(core->vact_space_3, 2, 0xffff); 1976 hdmi_set_reg(core->vact_space_4, 2, 0xffff); 1977 hdmi_set_reg(core->vact_space_5, 2, 0xffff); 1978 hdmi_set_reg(core->vact_space_6, 2, 0xffff); 1979 hdmi_set_reg(core->v_blank_f2, 2, 0xffff); 1980 hdmi_set_reg(core->v_blank_f3, 2, 0xffff); 1981 hdmi_set_reg(core->v_blank_f4, 2, 0xffff); 1982 hdmi_set_reg(core->v_blank_f5, 2, 0xffff); 1983 hdmi_set_reg(core->v_sync_line_aft_3, 2, 0xffff); 1984 hdmi_set_reg(core->v_sync_line_aft_4, 2, 0xffff); 1985 hdmi_set_reg(core->v_sync_line_aft_5, 2, 0xffff); 1986 hdmi_set_reg(core->v_sync_line_aft_6, 2, 0xffff); 1987 hdmi_set_reg(core->v_sync_line_aft_pxl_3, 2, 0xffff); 1988 hdmi_set_reg(core->v_sync_line_aft_pxl_4, 2, 0xffff); 1989 hdmi_set_reg(core->v_sync_line_aft_pxl_5, 2, 0xffff); 1990 hdmi_set_reg(core->v_sync_line_aft_pxl_6, 2, 0xffff); 1991 1992 /* Timing generator registers */ 1993 hdmi_set_reg(tg->cmd, 1, 0x0); 1994 hdmi_set_reg(tg->h_fsz, 2, m->htotal); 1995 hdmi_set_reg(tg->hact_st, 2, m->htotal - m->hdisplay); 1996 hdmi_set_reg(tg->hact_sz, 2, m->hdisplay); 1997 hdmi_set_reg(tg->v_fsz, 2, m->vtotal); 1998 hdmi_set_reg(tg->vsync, 2, 0x1); 1999 hdmi_set_reg(tg->field_chg, 2, 0x233); /* Reset value */ 2000 hdmi_set_reg(tg->vsync_top_hdmi, 2, 0x1); /* Reset value */ 2001 hdmi_set_reg(tg->field_top_hdmi, 2, 0x1); /* Reset value */ 2002 hdmi_set_reg(tg->tg_3d, 1, 0x0); 2003 } 2004 2005 static void hdmi_mode_set(struct exynos_drm_display *display, 2006 struct drm_display_mode *mode) 2007 { 2008 struct hdmi_context *hdata = display_to_hdmi(display); 2009 struct drm_display_mode *m = mode; 2010 2011 DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%s\n", 2012 m->hdisplay, m->vdisplay, 2013 m->vrefresh, (m->flags & DRM_MODE_FLAG_INTERLACE) ? 2014 "INTERLACED" : "PROGRESSIVE"); 2015 2016 /* preserve mode information for later use. */ 2017 drm_mode_copy(&hdata->current_mode, mode); 2018 2019 if (hdata->type == HDMI_TYPE13) 2020 hdmi_v13_mode_set(hdata, mode); 2021 else 2022 hdmi_v14_mode_set(hdata, mode); 2023 } 2024 2025 static void hdmi_commit(struct exynos_drm_display *display) 2026 { 2027 struct hdmi_context *hdata = display_to_hdmi(display); 2028 2029 mutex_lock(&hdata->hdmi_mutex); 2030 if (!hdata->powered) { 2031 mutex_unlock(&hdata->hdmi_mutex); 2032 return; 2033 } 2034 mutex_unlock(&hdata->hdmi_mutex); 2035 2036 hdmi_conf_apply(hdata); 2037 } 2038 2039 static void hdmi_poweron(struct hdmi_context *hdata) 2040 { 2041 struct hdmi_resources *res = &hdata->res; 2042 2043 mutex_lock(&hdata->hdmi_mutex); 2044 if (hdata->powered) { 2045 mutex_unlock(&hdata->hdmi_mutex); 2046 return; 2047 } 2048 2049 hdata->powered = true; 2050 2051 mutex_unlock(&hdata->hdmi_mutex); 2052 2053 pm_runtime_get_sync(hdata->dev); 2054 2055 if (regulator_bulk_enable(res->regul_count, res->regul_bulk)) 2056 DRM_DEBUG_KMS("failed to enable regulator bulk\n"); 2057 2058 /* set pmu hdmiphy control bit to enable hdmiphy */ 2059 regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL, 2060 PMU_HDMI_PHY_ENABLE_BIT, 1); 2061 2062 clk_prepare_enable(res->hdmi); 2063 clk_prepare_enable(res->sclk_hdmi); 2064 2065 hdmiphy_poweron(hdata); 2066 hdmi_commit(&hdata->display); 2067 } 2068 2069 static void hdmi_poweroff(struct hdmi_context *hdata) 2070 { 2071 struct hdmi_resources *res = &hdata->res; 2072 2073 mutex_lock(&hdata->hdmi_mutex); 2074 if (!hdata->powered) 2075 goto out; 2076 mutex_unlock(&hdata->hdmi_mutex); 2077 2078 /* HDMI System Disable */ 2079 hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_EN); 2080 2081 hdmiphy_poweroff(hdata); 2082 2083 cancel_delayed_work(&hdata->hotplug_work); 2084 2085 clk_disable_unprepare(res->sclk_hdmi); 2086 clk_disable_unprepare(res->hdmi); 2087 2088 /* reset pmu hdmiphy control bit to disable hdmiphy */ 2089 regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL, 2090 PMU_HDMI_PHY_ENABLE_BIT, 0); 2091 2092 regulator_bulk_disable(res->regul_count, res->regul_bulk); 2093 2094 pm_runtime_put_sync(hdata->dev); 2095 2096 mutex_lock(&hdata->hdmi_mutex); 2097 hdata->powered = false; 2098 2099 out: 2100 mutex_unlock(&hdata->hdmi_mutex); 2101 } 2102 2103 static void hdmi_dpms(struct exynos_drm_display *display, int mode) 2104 { 2105 struct hdmi_context *hdata = display_to_hdmi(display); 2106 struct drm_encoder *encoder = hdata->encoder; 2107 struct drm_crtc *crtc = encoder->crtc; 2108 const struct drm_crtc_helper_funcs *funcs = NULL; 2109 2110 DRM_DEBUG_KMS("mode %d\n", mode); 2111 2112 switch (mode) { 2113 case DRM_MODE_DPMS_ON: 2114 hdmi_poweron(hdata); 2115 break; 2116 case DRM_MODE_DPMS_STANDBY: 2117 case DRM_MODE_DPMS_SUSPEND: 2118 case DRM_MODE_DPMS_OFF: 2119 /* 2120 * The SFRs of VP and Mixer are updated by Vertical Sync of 2121 * Timing generator which is a part of HDMI so the sequence 2122 * to disable TV Subsystem should be as following, 2123 * VP -> Mixer -> HDMI 2124 * 2125 * Below codes will try to disable Mixer and VP(if used) 2126 * prior to disabling HDMI. 2127 */ 2128 if (crtc) 2129 funcs = crtc->helper_private; 2130 if (funcs && funcs->disable) 2131 (*funcs->disable)(crtc); 2132 2133 hdmi_poweroff(hdata); 2134 break; 2135 default: 2136 DRM_DEBUG_KMS("unknown dpms mode: %d\n", mode); 2137 break; 2138 } 2139 } 2140 2141 static struct exynos_drm_display_ops hdmi_display_ops = { 2142 .create_connector = hdmi_create_connector, 2143 .mode_fixup = hdmi_mode_fixup, 2144 .mode_set = hdmi_mode_set, 2145 .dpms = hdmi_dpms, 2146 .commit = hdmi_commit, 2147 }; 2148 2149 static void hdmi_hotplug_work_func(struct work_struct *work) 2150 { 2151 struct hdmi_context *hdata; 2152 2153 hdata = container_of(work, struct hdmi_context, hotplug_work.work); 2154 2155 mutex_lock(&hdata->hdmi_mutex); 2156 hdata->hpd = gpio_get_value(hdata->hpd_gpio); 2157 mutex_unlock(&hdata->hdmi_mutex); 2158 2159 if (hdata->drm_dev) 2160 drm_helper_hpd_irq_event(hdata->drm_dev); 2161 } 2162 2163 static irqreturn_t hdmi_irq_thread(int irq, void *arg) 2164 { 2165 struct hdmi_context *hdata = arg; 2166 2167 mod_delayed_work(system_wq, &hdata->hotplug_work, 2168 msecs_to_jiffies(HOTPLUG_DEBOUNCE_MS)); 2169 2170 return IRQ_HANDLED; 2171 } 2172 2173 static int hdmi_resources_init(struct hdmi_context *hdata) 2174 { 2175 struct device *dev = hdata->dev; 2176 struct hdmi_resources *res = &hdata->res; 2177 static char *supply[] = { 2178 "vdd", 2179 "vdd_osc", 2180 "vdd_pll", 2181 }; 2182 int i, ret; 2183 2184 DRM_DEBUG_KMS("HDMI resource init\n"); 2185 2186 /* get clocks, power */ 2187 res->hdmi = devm_clk_get(dev, "hdmi"); 2188 if (IS_ERR(res->hdmi)) { 2189 DRM_ERROR("failed to get clock 'hdmi'\n"); 2190 ret = PTR_ERR(res->hdmi); 2191 goto fail; 2192 } 2193 res->sclk_hdmi = devm_clk_get(dev, "sclk_hdmi"); 2194 if (IS_ERR(res->sclk_hdmi)) { 2195 DRM_ERROR("failed to get clock 'sclk_hdmi'\n"); 2196 ret = PTR_ERR(res->sclk_hdmi); 2197 goto fail; 2198 } 2199 res->sclk_pixel = devm_clk_get(dev, "sclk_pixel"); 2200 if (IS_ERR(res->sclk_pixel)) { 2201 DRM_ERROR("failed to get clock 'sclk_pixel'\n"); 2202 ret = PTR_ERR(res->sclk_pixel); 2203 goto fail; 2204 } 2205 res->sclk_hdmiphy = devm_clk_get(dev, "sclk_hdmiphy"); 2206 if (IS_ERR(res->sclk_hdmiphy)) { 2207 DRM_ERROR("failed to get clock 'sclk_hdmiphy'\n"); 2208 ret = PTR_ERR(res->sclk_hdmiphy); 2209 goto fail; 2210 } 2211 res->mout_hdmi = devm_clk_get(dev, "mout_hdmi"); 2212 if (IS_ERR(res->mout_hdmi)) { 2213 DRM_ERROR("failed to get clock 'mout_hdmi'\n"); 2214 ret = PTR_ERR(res->mout_hdmi); 2215 goto fail; 2216 } 2217 2218 clk_set_parent(res->mout_hdmi, res->sclk_pixel); 2219 2220 res->regul_bulk = devm_kzalloc(dev, ARRAY_SIZE(supply) * 2221 sizeof(res->regul_bulk[0]), GFP_KERNEL); 2222 if (!res->regul_bulk) { 2223 ret = -ENOMEM; 2224 goto fail; 2225 } 2226 for (i = 0; i < ARRAY_SIZE(supply); ++i) { 2227 res->regul_bulk[i].supply = supply[i]; 2228 res->regul_bulk[i].consumer = NULL; 2229 } 2230 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(supply), res->regul_bulk); 2231 if (ret) { 2232 DRM_ERROR("failed to get regulators\n"); 2233 return ret; 2234 } 2235 res->regul_count = ARRAY_SIZE(supply); 2236 2237 res->reg_hdmi_en = devm_regulator_get(dev, "hdmi-en"); 2238 if (IS_ERR(res->reg_hdmi_en) && PTR_ERR(res->reg_hdmi_en) != -ENOENT) { 2239 DRM_ERROR("failed to get hdmi-en regulator\n"); 2240 return PTR_ERR(res->reg_hdmi_en); 2241 } 2242 if (!IS_ERR(res->reg_hdmi_en)) { 2243 ret = regulator_enable(res->reg_hdmi_en); 2244 if (ret) { 2245 DRM_ERROR("failed to enable hdmi-en regulator\n"); 2246 return ret; 2247 } 2248 } else 2249 res->reg_hdmi_en = NULL; 2250 2251 return ret; 2252 fail: 2253 DRM_ERROR("HDMI resource init - failed\n"); 2254 return ret; 2255 } 2256 2257 static struct s5p_hdmi_platform_data *drm_hdmi_dt_parse_pdata 2258 (struct device *dev) 2259 { 2260 struct device_node *np = dev->of_node; 2261 struct s5p_hdmi_platform_data *pd; 2262 u32 value; 2263 2264 pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL); 2265 if (!pd) 2266 goto err_data; 2267 2268 if (!of_find_property(np, "hpd-gpio", &value)) { 2269 DRM_ERROR("no hpd gpio property found\n"); 2270 goto err_data; 2271 } 2272 2273 pd->hpd_gpio = of_get_named_gpio(np, "hpd-gpio", 0); 2274 2275 return pd; 2276 2277 err_data: 2278 return NULL; 2279 } 2280 2281 static struct of_device_id hdmi_match_types[] = { 2282 { 2283 .compatible = "samsung,exynos5-hdmi", 2284 .data = &exynos5_hdmi_driver_data, 2285 }, { 2286 .compatible = "samsung,exynos4210-hdmi", 2287 .data = &exynos4210_hdmi_driver_data, 2288 }, { 2289 .compatible = "samsung,exynos4212-hdmi", 2290 .data = &exynos4212_hdmi_driver_data, 2291 }, { 2292 .compatible = "samsung,exynos5420-hdmi", 2293 .data = &exynos5420_hdmi_driver_data, 2294 }, { 2295 /* end node */ 2296 } 2297 }; 2298 MODULE_DEVICE_TABLE (of, hdmi_match_types); 2299 2300 static int hdmi_bind(struct device *dev, struct device *master, void *data) 2301 { 2302 struct drm_device *drm_dev = data; 2303 struct hdmi_context *hdata = dev_get_drvdata(dev); 2304 2305 hdata->drm_dev = drm_dev; 2306 2307 return exynos_drm_create_enc_conn(drm_dev, &hdata->display); 2308 } 2309 2310 static void hdmi_unbind(struct device *dev, struct device *master, void *data) 2311 { 2312 } 2313 2314 static const struct component_ops hdmi_component_ops = { 2315 .bind = hdmi_bind, 2316 .unbind = hdmi_unbind, 2317 }; 2318 2319 static struct device_node *hdmi_legacy_ddc_dt_binding(struct device *dev) 2320 { 2321 const char *compatible_str = "samsung,exynos4210-hdmiddc"; 2322 struct device_node *np; 2323 2324 np = of_find_compatible_node(NULL, NULL, compatible_str); 2325 if (np) 2326 return of_get_next_parent(np); 2327 2328 return NULL; 2329 } 2330 2331 static struct device_node *hdmi_legacy_phy_dt_binding(struct device *dev) 2332 { 2333 const char *compatible_str = "samsung,exynos4212-hdmiphy"; 2334 2335 return of_find_compatible_node(NULL, NULL, compatible_str); 2336 } 2337 2338 static int hdmi_probe(struct platform_device *pdev) 2339 { 2340 struct device_node *ddc_node, *phy_node; 2341 struct s5p_hdmi_platform_data *pdata; 2342 struct hdmi_driver_data *drv_data; 2343 const struct of_device_id *match; 2344 struct device *dev = &pdev->dev; 2345 struct hdmi_context *hdata; 2346 struct resource *res; 2347 int ret; 2348 2349 if (!dev->of_node) 2350 return -ENODEV; 2351 2352 pdata = drm_hdmi_dt_parse_pdata(dev); 2353 if (!pdata) 2354 return -EINVAL; 2355 2356 hdata = devm_kzalloc(dev, sizeof(struct hdmi_context), GFP_KERNEL); 2357 if (!hdata) 2358 return -ENOMEM; 2359 2360 hdata->display.type = EXYNOS_DISPLAY_TYPE_HDMI; 2361 hdata->display.ops = &hdmi_display_ops; 2362 2363 mutex_init(&hdata->hdmi_mutex); 2364 2365 platform_set_drvdata(pdev, hdata); 2366 2367 match = of_match_node(hdmi_match_types, dev->of_node); 2368 if (!match) 2369 return -ENODEV; 2370 2371 drv_data = (struct hdmi_driver_data *)match->data; 2372 hdata->type = drv_data->type; 2373 hdata->phy_confs = drv_data->phy_confs; 2374 hdata->phy_conf_count = drv_data->phy_conf_count; 2375 2376 hdata->hpd_gpio = pdata->hpd_gpio; 2377 hdata->dev = dev; 2378 2379 ret = hdmi_resources_init(hdata); 2380 if (ret) { 2381 DRM_ERROR("hdmi_resources_init failed\n"); 2382 return ret; 2383 } 2384 2385 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2386 hdata->regs = devm_ioremap_resource(dev, res); 2387 if (IS_ERR(hdata->regs)) { 2388 ret = PTR_ERR(hdata->regs); 2389 return ret; 2390 } 2391 2392 ret = devm_gpio_request(dev, hdata->hpd_gpio, "HPD"); 2393 if (ret) { 2394 DRM_ERROR("failed to request HPD gpio\n"); 2395 return ret; 2396 } 2397 2398 ddc_node = hdmi_legacy_ddc_dt_binding(dev); 2399 if (ddc_node) 2400 goto out_get_ddc_adpt; 2401 2402 /* DDC i2c driver */ 2403 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0); 2404 if (!ddc_node) { 2405 DRM_ERROR("Failed to find ddc node in device tree\n"); 2406 return -ENODEV; 2407 } 2408 2409 out_get_ddc_adpt: 2410 hdata->ddc_adpt = of_find_i2c_adapter_by_node(ddc_node); 2411 if (!hdata->ddc_adpt) { 2412 DRM_ERROR("Failed to get ddc i2c adapter by node\n"); 2413 return -EPROBE_DEFER; 2414 } 2415 2416 phy_node = hdmi_legacy_phy_dt_binding(dev); 2417 if (phy_node) 2418 goto out_get_phy_port; 2419 2420 /* hdmiphy i2c driver */ 2421 phy_node = of_parse_phandle(dev->of_node, "phy", 0); 2422 if (!phy_node) { 2423 DRM_ERROR("Failed to find hdmiphy node in device tree\n"); 2424 ret = -ENODEV; 2425 goto err_ddc; 2426 } 2427 2428 out_get_phy_port: 2429 if (drv_data->is_apb_phy) { 2430 hdata->regs_hdmiphy = of_iomap(phy_node, 0); 2431 if (!hdata->regs_hdmiphy) { 2432 DRM_ERROR("failed to ioremap hdmi phy\n"); 2433 ret = -ENOMEM; 2434 goto err_ddc; 2435 } 2436 } else { 2437 hdata->hdmiphy_port = of_find_i2c_device_by_node(phy_node); 2438 if (!hdata->hdmiphy_port) { 2439 DRM_ERROR("Failed to get hdmi phy i2c client\n"); 2440 ret = -EPROBE_DEFER; 2441 goto err_ddc; 2442 } 2443 } 2444 2445 hdata->irq = gpio_to_irq(hdata->hpd_gpio); 2446 if (hdata->irq < 0) { 2447 DRM_ERROR("failed to get GPIO irq\n"); 2448 ret = hdata->irq; 2449 goto err_hdmiphy; 2450 } 2451 2452 hdata->hpd = gpio_get_value(hdata->hpd_gpio); 2453 2454 INIT_DELAYED_WORK(&hdata->hotplug_work, hdmi_hotplug_work_func); 2455 2456 ret = devm_request_threaded_irq(dev, hdata->irq, NULL, 2457 hdmi_irq_thread, IRQF_TRIGGER_RISING | 2458 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 2459 "hdmi", hdata); 2460 if (ret) { 2461 DRM_ERROR("failed to register hdmi interrupt\n"); 2462 goto err_hdmiphy; 2463 } 2464 2465 hdata->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node, 2466 "samsung,syscon-phandle"); 2467 if (IS_ERR(hdata->pmureg)) { 2468 DRM_ERROR("syscon regmap lookup failed.\n"); 2469 ret = -EPROBE_DEFER; 2470 goto err_hdmiphy; 2471 } 2472 2473 pm_runtime_enable(dev); 2474 2475 ret = component_add(&pdev->dev, &hdmi_component_ops); 2476 if (ret) 2477 goto err_disable_pm_runtime; 2478 2479 return ret; 2480 2481 err_disable_pm_runtime: 2482 pm_runtime_disable(dev); 2483 2484 err_hdmiphy: 2485 if (hdata->hdmiphy_port) 2486 put_device(&hdata->hdmiphy_port->dev); 2487 err_ddc: 2488 put_device(&hdata->ddc_adpt->dev); 2489 2490 return ret; 2491 } 2492 2493 static int hdmi_remove(struct platform_device *pdev) 2494 { 2495 struct hdmi_context *hdata = platform_get_drvdata(pdev); 2496 2497 cancel_delayed_work_sync(&hdata->hotplug_work); 2498 2499 if (hdata->res.reg_hdmi_en) 2500 regulator_disable(hdata->res.reg_hdmi_en); 2501 2502 if (hdata->hdmiphy_port) 2503 put_device(&hdata->hdmiphy_port->dev); 2504 put_device(&hdata->ddc_adpt->dev); 2505 2506 pm_runtime_disable(&pdev->dev); 2507 component_del(&pdev->dev, &hdmi_component_ops); 2508 2509 return 0; 2510 } 2511 2512 struct platform_driver hdmi_driver = { 2513 .probe = hdmi_probe, 2514 .remove = hdmi_remove, 2515 .driver = { 2516 .name = "exynos-hdmi", 2517 .owner = THIS_MODULE, 2518 .of_match_table = hdmi_match_types, 2519 }, 2520 }; 2521