1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Samsung Electronics Co.Ltd 4 * Authors: 5 * Hyungwon Hwang <human.hwang@samsung.com> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/component.h> 10 #include <linux/delay.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/module.h> 13 #include <linux/mutex.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/of_graph.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/regmap.h> 20 21 #include <video/of_videomode.h> 22 #include <video/videomode.h> 23 24 #include <drm/drm_bridge.h> 25 #include <drm/drm_encoder.h> 26 #include <drm/drm_print.h> 27 28 #include "exynos_drm_drv.h" 29 30 /* Sysreg registers for MIC */ 31 #define DSD_CFG_MUX 0x1004 32 #define MIC0_RGB_MUX (1 << 0) 33 #define MIC0_I80_MUX (1 << 1) 34 #define MIC0_ON_MUX (1 << 5) 35 36 /* MIC registers */ 37 #define MIC_OP 0x0 38 #define MIC_IP_VER 0x0004 39 #define MIC_V_TIMING_0 0x0008 40 #define MIC_V_TIMING_1 0x000C 41 #define MIC_IMG_SIZE 0x0010 42 #define MIC_INPUT_TIMING_0 0x0014 43 #define MIC_INPUT_TIMING_1 0x0018 44 #define MIC_2D_OUTPUT_TIMING_0 0x001C 45 #define MIC_2D_OUTPUT_TIMING_1 0x0020 46 #define MIC_2D_OUTPUT_TIMING_2 0x0024 47 #define MIC_3D_OUTPUT_TIMING_0 0x0028 48 #define MIC_3D_OUTPUT_TIMING_1 0x002C 49 #define MIC_3D_OUTPUT_TIMING_2 0x0030 50 #define MIC_CORE_PARA_0 0x0034 51 #define MIC_CORE_PARA_1 0x0038 52 #define MIC_CTC_CTRL 0x0040 53 #define MIC_RD_DATA 0x0044 54 55 #define MIC_UPD_REG (1 << 31) 56 #define MIC_ON_REG (1 << 30) 57 #define MIC_TD_ON_REG (1 << 29) 58 #define MIC_BS_CHG_OUT (1 << 16) 59 #define MIC_VIDEO_TYPE(x) (((x) & 0xf) << 12) 60 #define MIC_PSR_EN (1 << 5) 61 #define MIC_SW_RST (1 << 4) 62 #define MIC_ALL_RST (1 << 3) 63 #define MIC_CORE_VER_CONTROL (1 << 2) 64 #define MIC_MODE_SEL_COMMAND_MODE (1 << 1) 65 #define MIC_MODE_SEL_MASK (1 << 1) 66 #define MIC_CORE_EN (1 << 0) 67 68 #define MIC_V_PULSE_WIDTH(x) (((x) & 0x3fff) << 16) 69 #define MIC_V_PERIOD_LINE(x) ((x) & 0x3fff) 70 71 #define MIC_VBP_SIZE(x) (((x) & 0x3fff) << 16) 72 #define MIC_VFP_SIZE(x) ((x) & 0x3fff) 73 74 #define MIC_IMG_V_SIZE(x) (((x) & 0x3fff) << 16) 75 #define MIC_IMG_H_SIZE(x) ((x) & 0x3fff) 76 77 #define MIC_H_PULSE_WIDTH_IN(x) (((x) & 0x3fff) << 16) 78 #define MIC_H_PERIOD_PIXEL_IN(x) ((x) & 0x3fff) 79 80 #define MIC_HBP_SIZE_IN(x) (((x) & 0x3fff) << 16) 81 #define MIC_HFP_SIZE_IN(x) ((x) & 0x3fff) 82 83 #define MIC_H_PULSE_WIDTH_2D(x) (((x) & 0x3fff) << 16) 84 #define MIC_H_PERIOD_PIXEL_2D(x) ((x) & 0x3fff) 85 86 #define MIC_HBP_SIZE_2D(x) (((x) & 0x3fff) << 16) 87 #define MIC_HFP_SIZE_2D(x) ((x) & 0x3fff) 88 89 #define MIC_BS_SIZE_2D(x) ((x) & 0x3fff) 90 91 static const char *const clk_names[] = { "pclk_mic0", "sclk_rgb_vclk_to_mic0" }; 92 #define NUM_CLKS ARRAY_SIZE(clk_names) 93 static DEFINE_MUTEX(mic_mutex); 94 95 struct exynos_mic { 96 struct device *dev; 97 void __iomem *reg; 98 struct regmap *sysreg; 99 struct clk *clks[NUM_CLKS]; 100 101 bool i80_mode; 102 struct videomode vm; 103 struct drm_encoder *encoder; 104 struct drm_bridge bridge; 105 struct drm_bridge *next_bridge; 106 107 bool enabled; 108 }; 109 110 static void mic_set_path(struct exynos_mic *mic, bool enable) 111 { 112 int ret; 113 unsigned int val; 114 115 ret = regmap_read(mic->sysreg, DSD_CFG_MUX, &val); 116 if (ret) { 117 DRM_DEV_ERROR(mic->dev, 118 "mic: Failed to read system register\n"); 119 return; 120 } 121 122 if (enable) { 123 if (mic->i80_mode) 124 val |= MIC0_I80_MUX; 125 else 126 val |= MIC0_RGB_MUX; 127 128 val |= MIC0_ON_MUX; 129 } else 130 val &= ~(MIC0_RGB_MUX | MIC0_I80_MUX | MIC0_ON_MUX); 131 132 ret = regmap_write(mic->sysreg, DSD_CFG_MUX, val); 133 if (ret) 134 DRM_DEV_ERROR(mic->dev, 135 "mic: Failed to read system register\n"); 136 } 137 138 static int mic_sw_reset(struct exynos_mic *mic) 139 { 140 unsigned int retry = 100; 141 int ret; 142 143 writel(MIC_SW_RST, mic->reg + MIC_OP); 144 145 while (retry-- > 0) { 146 ret = readl(mic->reg + MIC_OP); 147 if (!(ret & MIC_SW_RST)) 148 return 0; 149 150 udelay(10); 151 } 152 153 return -ETIMEDOUT; 154 } 155 156 static void mic_set_porch_timing(struct exynos_mic *mic) 157 { 158 struct videomode vm = mic->vm; 159 u32 reg; 160 161 reg = MIC_V_PULSE_WIDTH(vm.vsync_len) + 162 MIC_V_PERIOD_LINE(vm.vsync_len + vm.vactive + 163 vm.vback_porch + vm.vfront_porch); 164 writel(reg, mic->reg + MIC_V_TIMING_0); 165 166 reg = MIC_VBP_SIZE(vm.vback_porch) + 167 MIC_VFP_SIZE(vm.vfront_porch); 168 writel(reg, mic->reg + MIC_V_TIMING_1); 169 170 reg = MIC_V_PULSE_WIDTH(vm.hsync_len) + 171 MIC_V_PERIOD_LINE(vm.hsync_len + vm.hactive + 172 vm.hback_porch + vm.hfront_porch); 173 writel(reg, mic->reg + MIC_INPUT_TIMING_0); 174 175 reg = MIC_VBP_SIZE(vm.hback_porch) + 176 MIC_VFP_SIZE(vm.hfront_porch); 177 writel(reg, mic->reg + MIC_INPUT_TIMING_1); 178 } 179 180 static void mic_set_img_size(struct exynos_mic *mic) 181 { 182 struct videomode *vm = &mic->vm; 183 u32 reg; 184 185 reg = MIC_IMG_H_SIZE(vm->hactive) + 186 MIC_IMG_V_SIZE(vm->vactive); 187 188 writel(reg, mic->reg + MIC_IMG_SIZE); 189 } 190 191 static void mic_set_output_timing(struct exynos_mic *mic) 192 { 193 struct videomode vm = mic->vm; 194 u32 reg, bs_size_2d; 195 196 DRM_DEV_DEBUG(mic->dev, "w: %u, h: %u\n", vm.hactive, vm.vactive); 197 bs_size_2d = ((vm.hactive >> 2) << 1) + (vm.vactive % 4); 198 reg = MIC_BS_SIZE_2D(bs_size_2d); 199 writel(reg, mic->reg + MIC_2D_OUTPUT_TIMING_2); 200 201 if (!mic->i80_mode) { 202 reg = MIC_H_PULSE_WIDTH_2D(vm.hsync_len) + 203 MIC_H_PERIOD_PIXEL_2D(vm.hsync_len + bs_size_2d + 204 vm.hback_porch + vm.hfront_porch); 205 writel(reg, mic->reg + MIC_2D_OUTPUT_TIMING_0); 206 207 reg = MIC_HBP_SIZE_2D(vm.hback_porch) + 208 MIC_H_PERIOD_PIXEL_2D(vm.hfront_porch); 209 writel(reg, mic->reg + MIC_2D_OUTPUT_TIMING_1); 210 } 211 } 212 213 static void mic_set_reg_on(struct exynos_mic *mic, bool enable) 214 { 215 u32 reg = readl(mic->reg + MIC_OP); 216 217 if (enable) { 218 reg &= ~(MIC_MODE_SEL_MASK | MIC_CORE_VER_CONTROL | MIC_PSR_EN); 219 reg |= (MIC_CORE_EN | MIC_BS_CHG_OUT | MIC_ON_REG); 220 221 reg &= ~MIC_MODE_SEL_COMMAND_MODE; 222 if (mic->i80_mode) 223 reg |= MIC_MODE_SEL_COMMAND_MODE; 224 } else { 225 reg &= ~MIC_CORE_EN; 226 } 227 228 reg |= MIC_UPD_REG; 229 writel(reg, mic->reg + MIC_OP); 230 } 231 232 static void mic_disable(struct drm_bridge *bridge) { } 233 234 static void mic_post_disable(struct drm_bridge *bridge) 235 { 236 struct exynos_mic *mic = bridge->driver_private; 237 238 mutex_lock(&mic_mutex); 239 if (!mic->enabled) 240 goto already_disabled; 241 242 mic_set_path(mic, 0); 243 244 pm_runtime_put(mic->dev); 245 mic->enabled = 0; 246 247 already_disabled: 248 mutex_unlock(&mic_mutex); 249 } 250 251 static void mic_mode_set(struct drm_bridge *bridge, 252 const struct drm_display_mode *mode, 253 const struct drm_display_mode *adjusted_mode) 254 { 255 struct exynos_mic *mic = bridge->driver_private; 256 257 mutex_lock(&mic_mutex); 258 drm_display_mode_to_videomode(mode, &mic->vm); 259 mic->i80_mode = to_exynos_crtc(bridge->encoder->crtc)->i80_mode; 260 mutex_unlock(&mic_mutex); 261 } 262 263 static void mic_pre_enable(struct drm_bridge *bridge) 264 { 265 struct exynos_mic *mic = bridge->driver_private; 266 int ret; 267 268 mutex_lock(&mic_mutex); 269 if (mic->enabled) 270 goto unlock; 271 272 ret = pm_runtime_resume_and_get(mic->dev); 273 if (ret < 0) 274 goto unlock; 275 276 mic_set_path(mic, 1); 277 278 ret = mic_sw_reset(mic); 279 if (ret) { 280 DRM_DEV_ERROR(mic->dev, "Failed to reset\n"); 281 goto turn_off; 282 } 283 284 if (!mic->i80_mode) 285 mic_set_porch_timing(mic); 286 mic_set_img_size(mic); 287 mic_set_output_timing(mic); 288 mic_set_reg_on(mic, 1); 289 mic->enabled = 1; 290 mutex_unlock(&mic_mutex); 291 292 return; 293 294 turn_off: 295 pm_runtime_put(mic->dev); 296 unlock: 297 mutex_unlock(&mic_mutex); 298 } 299 300 static void mic_enable(struct drm_bridge *bridge) { } 301 302 static int mic_attach(struct drm_bridge *bridge, 303 enum drm_bridge_attach_flags flags) 304 { 305 struct exynos_mic *mic = bridge->driver_private; 306 307 return drm_bridge_attach(bridge->encoder, mic->next_bridge, 308 &mic->bridge, flags); 309 } 310 311 static const struct drm_bridge_funcs mic_bridge_funcs = { 312 .disable = mic_disable, 313 .post_disable = mic_post_disable, 314 .mode_set = mic_mode_set, 315 .pre_enable = mic_pre_enable, 316 .enable = mic_enable, 317 .attach = mic_attach, 318 }; 319 320 static int exynos_mic_bind(struct device *dev, struct device *master, 321 void *data) 322 { 323 struct exynos_mic *mic = dev_get_drvdata(dev); 324 325 mic->bridge.driver_private = mic; 326 327 return 0; 328 } 329 330 static void exynos_mic_unbind(struct device *dev, struct device *master, 331 void *data) 332 { 333 struct exynos_mic *mic = dev_get_drvdata(dev); 334 335 mutex_lock(&mic_mutex); 336 if (!mic->enabled) 337 goto already_disabled; 338 339 pm_runtime_put(mic->dev); 340 341 already_disabled: 342 mutex_unlock(&mic_mutex); 343 } 344 345 static const struct component_ops exynos_mic_component_ops = { 346 .bind = exynos_mic_bind, 347 .unbind = exynos_mic_unbind, 348 }; 349 350 #ifdef CONFIG_PM 351 static int exynos_mic_suspend(struct device *dev) 352 { 353 struct exynos_mic *mic = dev_get_drvdata(dev); 354 int i; 355 356 for (i = NUM_CLKS - 1; i > -1; i--) 357 clk_disable_unprepare(mic->clks[i]); 358 359 return 0; 360 } 361 362 static int exynos_mic_resume(struct device *dev) 363 { 364 struct exynos_mic *mic = dev_get_drvdata(dev); 365 int ret, i; 366 367 for (i = 0; i < NUM_CLKS; i++) { 368 ret = clk_prepare_enable(mic->clks[i]); 369 if (ret < 0) { 370 DRM_DEV_ERROR(dev, "Failed to enable clock (%s)\n", 371 clk_names[i]); 372 while (--i > -1) 373 clk_disable_unprepare(mic->clks[i]); 374 return ret; 375 } 376 } 377 return 0; 378 } 379 #endif 380 381 static const struct dev_pm_ops exynos_mic_pm_ops = { 382 SET_RUNTIME_PM_OPS(exynos_mic_suspend, exynos_mic_resume, NULL) 383 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 384 pm_runtime_force_resume) 385 }; 386 387 static int exynos_mic_probe(struct platform_device *pdev) 388 { 389 struct device *dev = &pdev->dev; 390 struct exynos_mic *mic; 391 struct device_node *remote; 392 struct resource res; 393 int ret, i; 394 395 mic = devm_kzalloc(dev, sizeof(*mic), GFP_KERNEL); 396 if (!mic) { 397 DRM_DEV_ERROR(dev, 398 "mic: Failed to allocate memory for MIC object\n"); 399 ret = -ENOMEM; 400 goto err; 401 } 402 403 mic->dev = dev; 404 405 ret = of_address_to_resource(dev->of_node, 0, &res); 406 if (ret) { 407 DRM_DEV_ERROR(dev, "mic: Failed to get mem region for MIC\n"); 408 goto err; 409 } 410 mic->reg = devm_ioremap(dev, res.start, resource_size(&res)); 411 if (!mic->reg) { 412 DRM_DEV_ERROR(dev, "mic: Failed to remap for MIC\n"); 413 ret = -ENOMEM; 414 goto err; 415 } 416 417 mic->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node, 418 "samsung,disp-syscon"); 419 if (IS_ERR(mic->sysreg)) { 420 DRM_DEV_ERROR(dev, "mic: Failed to get system register.\n"); 421 ret = PTR_ERR(mic->sysreg); 422 goto err; 423 } 424 425 for (i = 0; i < NUM_CLKS; i++) { 426 mic->clks[i] = devm_clk_get(dev, clk_names[i]); 427 if (IS_ERR(mic->clks[i])) { 428 DRM_DEV_ERROR(dev, "mic: Failed to get clock (%s)\n", 429 clk_names[i]); 430 ret = PTR_ERR(mic->clks[i]); 431 goto err; 432 } 433 } 434 435 remote = of_graph_get_remote_node(dev->of_node, 1, 0); 436 mic->next_bridge = of_drm_find_bridge(remote); 437 if (IS_ERR(mic->next_bridge)) { 438 DRM_DEV_ERROR(dev, "mic: Failed to find next bridge\n"); 439 ret = PTR_ERR(mic->next_bridge); 440 goto err; 441 } 442 443 of_node_put(remote); 444 445 platform_set_drvdata(pdev, mic); 446 447 mic->bridge.funcs = &mic_bridge_funcs; 448 mic->bridge.of_node = dev->of_node; 449 450 drm_bridge_add(&mic->bridge); 451 452 pm_runtime_enable(dev); 453 454 ret = component_add(dev, &exynos_mic_component_ops); 455 if (ret) 456 goto err_pm; 457 458 DRM_DEV_DEBUG_KMS(dev, "MIC has been probed\n"); 459 460 return 0; 461 462 err_pm: 463 pm_runtime_disable(dev); 464 err: 465 return ret; 466 } 467 468 static int exynos_mic_remove(struct platform_device *pdev) 469 { 470 struct exynos_mic *mic = platform_get_drvdata(pdev); 471 472 component_del(&pdev->dev, &exynos_mic_component_ops); 473 pm_runtime_disable(&pdev->dev); 474 475 drm_bridge_remove(&mic->bridge); 476 477 return 0; 478 } 479 480 static const struct of_device_id exynos_mic_of_match[] = { 481 { .compatible = "samsung,exynos5433-mic" }, 482 { } 483 }; 484 MODULE_DEVICE_TABLE(of, exynos_mic_of_match); 485 486 struct platform_driver mic_driver = { 487 .probe = exynos_mic_probe, 488 .remove = exynos_mic_remove, 489 .driver = { 490 .name = "exynos-mic", 491 .pm = &exynos_mic_pm_ops, 492 .owner = THIS_MODULE, 493 .of_match_table = exynos_mic_of_match, 494 }, 495 }; 496