1 /* exynos_drm_fimd.c 2 * 3 * Copyright (C) 2011 Samsung Electronics Co.Ltd 4 * Authors: 5 * Joonyoung Shim <jy0922.shim@samsung.com> 6 * Inki Dae <inki.dae@samsung.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 */ 14 #include <drm/drmP.h> 15 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/platform_device.h> 19 #include <linux/clk.h> 20 #include <linux/of_device.h> 21 #include <linux/pm_runtime.h> 22 23 #include <video/samsung_fimd.h> 24 #include <drm/exynos_drm.h> 25 26 #include "exynos_drm_drv.h" 27 #include "exynos_drm_fbdev.h" 28 #include "exynos_drm_crtc.h" 29 #include "exynos_drm_iommu.h" 30 31 /* 32 * FIMD is stand for Fully Interactive Mobile Display and 33 * as a display controller, it transfers contents drawn on memory 34 * to a LCD Panel through Display Interfaces such as RGB or 35 * CPU Interface. 36 */ 37 38 /* position control register for hardware window 0, 2 ~ 4.*/ 39 #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16) 40 #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16) 41 /* size control register for hardware window 0. */ 42 #define VIDOSD_C_SIZE_W0 (VIDOSD_BASE + 0x08) 43 /* alpha control register for hardware window 1 ~ 4. */ 44 #define VIDOSD_C(win) (VIDOSD_BASE + 0x18 + (win) * 16) 45 /* size control register for hardware window 1 ~ 4. */ 46 #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16) 47 48 #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8) 49 #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8) 50 #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4) 51 52 /* color key control register for hardware window 1 ~ 4. */ 53 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + (x * 8)) 54 /* color key value register for hardware window 1 ~ 4. */ 55 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + (x * 8)) 56 57 /* FIMD has totally five hardware windows. */ 58 #define WINDOWS_NR 5 59 60 #define get_fimd_context(dev) platform_get_drvdata(to_platform_device(dev)) 61 62 struct fimd_driver_data { 63 unsigned int timing_base; 64 }; 65 66 static struct fimd_driver_data exynos4_fimd_driver_data = { 67 .timing_base = 0x0, 68 }; 69 70 static struct fimd_driver_data exynos5_fimd_driver_data = { 71 .timing_base = 0x20000, 72 }; 73 74 struct fimd_win_data { 75 unsigned int offset_x; 76 unsigned int offset_y; 77 unsigned int ovl_width; 78 unsigned int ovl_height; 79 unsigned int fb_width; 80 unsigned int fb_height; 81 unsigned int bpp; 82 dma_addr_t dma_addr; 83 unsigned int buf_offsize; 84 unsigned int line_size; /* bytes */ 85 bool enabled; 86 bool resume; 87 }; 88 89 struct fimd_context { 90 struct exynos_drm_subdrv subdrv; 91 int irq; 92 struct drm_crtc *crtc; 93 struct clk *bus_clk; 94 struct clk *lcd_clk; 95 void __iomem *regs; 96 struct fimd_win_data win_data[WINDOWS_NR]; 97 unsigned int clkdiv; 98 unsigned int default_win; 99 unsigned long irq_flags; 100 u32 vidcon0; 101 u32 vidcon1; 102 bool suspended; 103 struct mutex lock; 104 wait_queue_head_t wait_vsync_queue; 105 atomic_t wait_vsync_event; 106 107 struct exynos_drm_panel_info *panel; 108 }; 109 110 #ifdef CONFIG_OF 111 static const struct of_device_id fimd_driver_dt_match[] = { 112 { .compatible = "samsung,exynos4-fimd", 113 .data = &exynos4_fimd_driver_data }, 114 { .compatible = "samsung,exynos5-fimd", 115 .data = &exynos5_fimd_driver_data }, 116 {}, 117 }; 118 MODULE_DEVICE_TABLE(of, fimd_driver_dt_match); 119 #endif 120 121 static inline struct fimd_driver_data *drm_fimd_get_driver_data( 122 struct platform_device *pdev) 123 { 124 #ifdef CONFIG_OF 125 const struct of_device_id *of_id = 126 of_match_device(fimd_driver_dt_match, &pdev->dev); 127 128 if (of_id) 129 return (struct fimd_driver_data *)of_id->data; 130 #endif 131 132 return (struct fimd_driver_data *) 133 platform_get_device_id(pdev)->driver_data; 134 } 135 136 static bool fimd_display_is_connected(struct device *dev) 137 { 138 DRM_DEBUG_KMS("%s\n", __FILE__); 139 140 /* TODO. */ 141 142 return true; 143 } 144 145 static void *fimd_get_panel(struct device *dev) 146 { 147 struct fimd_context *ctx = get_fimd_context(dev); 148 149 DRM_DEBUG_KMS("%s\n", __FILE__); 150 151 return ctx->panel; 152 } 153 154 static int fimd_check_timing(struct device *dev, void *timing) 155 { 156 DRM_DEBUG_KMS("%s\n", __FILE__); 157 158 /* TODO. */ 159 160 return 0; 161 } 162 163 static int fimd_display_power_on(struct device *dev, int mode) 164 { 165 DRM_DEBUG_KMS("%s\n", __FILE__); 166 167 /* TODO */ 168 169 return 0; 170 } 171 172 static struct exynos_drm_display_ops fimd_display_ops = { 173 .type = EXYNOS_DISPLAY_TYPE_LCD, 174 .is_connected = fimd_display_is_connected, 175 .get_panel = fimd_get_panel, 176 .check_timing = fimd_check_timing, 177 .power_on = fimd_display_power_on, 178 }; 179 180 static void fimd_dpms(struct device *subdrv_dev, int mode) 181 { 182 struct fimd_context *ctx = get_fimd_context(subdrv_dev); 183 184 DRM_DEBUG_KMS("%s, %d\n", __FILE__, mode); 185 186 mutex_lock(&ctx->lock); 187 188 switch (mode) { 189 case DRM_MODE_DPMS_ON: 190 /* 191 * enable fimd hardware only if suspended status. 192 * 193 * P.S. fimd_dpms function would be called at booting time so 194 * clk_enable could be called double time. 195 */ 196 if (ctx->suspended) 197 pm_runtime_get_sync(subdrv_dev); 198 break; 199 case DRM_MODE_DPMS_STANDBY: 200 case DRM_MODE_DPMS_SUSPEND: 201 case DRM_MODE_DPMS_OFF: 202 if (!ctx->suspended) 203 pm_runtime_put_sync(subdrv_dev); 204 break; 205 default: 206 DRM_DEBUG_KMS("unspecified mode %d\n", mode); 207 break; 208 } 209 210 mutex_unlock(&ctx->lock); 211 } 212 213 static void fimd_apply(struct device *subdrv_dev) 214 { 215 struct fimd_context *ctx = get_fimd_context(subdrv_dev); 216 struct exynos_drm_manager *mgr = ctx->subdrv.manager; 217 struct exynos_drm_manager_ops *mgr_ops = mgr->ops; 218 struct exynos_drm_overlay_ops *ovl_ops = mgr->overlay_ops; 219 struct fimd_win_data *win_data; 220 int i; 221 222 DRM_DEBUG_KMS("%s\n", __FILE__); 223 224 for (i = 0; i < WINDOWS_NR; i++) { 225 win_data = &ctx->win_data[i]; 226 if (win_data->enabled && (ovl_ops && ovl_ops->commit)) 227 ovl_ops->commit(subdrv_dev, i); 228 } 229 230 if (mgr_ops && mgr_ops->commit) 231 mgr_ops->commit(subdrv_dev); 232 } 233 234 static void fimd_commit(struct device *dev) 235 { 236 struct fimd_context *ctx = get_fimd_context(dev); 237 struct exynos_drm_panel_info *panel = ctx->panel; 238 struct fb_videomode *timing = &panel->timing; 239 struct fimd_driver_data *driver_data; 240 struct platform_device *pdev = to_platform_device(dev); 241 u32 val; 242 243 driver_data = drm_fimd_get_driver_data(pdev); 244 if (ctx->suspended) 245 return; 246 247 DRM_DEBUG_KMS("%s\n", __FILE__); 248 249 /* setup polarity values from machine code. */ 250 writel(ctx->vidcon1, ctx->regs + driver_data->timing_base + VIDCON1); 251 252 /* setup vertical timing values. */ 253 val = VIDTCON0_VBPD(timing->upper_margin - 1) | 254 VIDTCON0_VFPD(timing->lower_margin - 1) | 255 VIDTCON0_VSPW(timing->vsync_len - 1); 256 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0); 257 258 /* setup horizontal timing values. */ 259 val = VIDTCON1_HBPD(timing->left_margin - 1) | 260 VIDTCON1_HFPD(timing->right_margin - 1) | 261 VIDTCON1_HSPW(timing->hsync_len - 1); 262 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1); 263 264 /* setup horizontal and vertical display size. */ 265 val = VIDTCON2_LINEVAL(timing->yres - 1) | 266 VIDTCON2_HOZVAL(timing->xres - 1) | 267 VIDTCON2_LINEVAL_E(timing->yres - 1) | 268 VIDTCON2_HOZVAL_E(timing->xres - 1); 269 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2); 270 271 /* setup clock source, clock divider, enable dma. */ 272 val = ctx->vidcon0; 273 val &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR); 274 275 if (ctx->clkdiv > 1) 276 val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR; 277 else 278 val &= ~VIDCON0_CLKDIR; /* 1:1 clock */ 279 280 /* 281 * fields of register with prefix '_F' would be updated 282 * at vsync(same as dma start) 283 */ 284 val |= VIDCON0_ENVID | VIDCON0_ENVID_F; 285 writel(val, ctx->regs + VIDCON0); 286 } 287 288 static int fimd_enable_vblank(struct device *dev) 289 { 290 struct fimd_context *ctx = get_fimd_context(dev); 291 u32 val; 292 293 DRM_DEBUG_KMS("%s\n", __FILE__); 294 295 if (ctx->suspended) 296 return -EPERM; 297 298 if (!test_and_set_bit(0, &ctx->irq_flags)) { 299 val = readl(ctx->regs + VIDINTCON0); 300 301 val |= VIDINTCON0_INT_ENABLE; 302 val |= VIDINTCON0_INT_FRAME; 303 304 val &= ~VIDINTCON0_FRAMESEL0_MASK; 305 val |= VIDINTCON0_FRAMESEL0_VSYNC; 306 val &= ~VIDINTCON0_FRAMESEL1_MASK; 307 val |= VIDINTCON0_FRAMESEL1_NONE; 308 309 writel(val, ctx->regs + VIDINTCON0); 310 } 311 312 return 0; 313 } 314 315 static void fimd_disable_vblank(struct device *dev) 316 { 317 struct fimd_context *ctx = get_fimd_context(dev); 318 u32 val; 319 320 DRM_DEBUG_KMS("%s\n", __FILE__); 321 322 if (ctx->suspended) 323 return; 324 325 if (test_and_clear_bit(0, &ctx->irq_flags)) { 326 val = readl(ctx->regs + VIDINTCON0); 327 328 val &= ~VIDINTCON0_INT_FRAME; 329 val &= ~VIDINTCON0_INT_ENABLE; 330 331 writel(val, ctx->regs + VIDINTCON0); 332 } 333 } 334 335 static void fimd_wait_for_vblank(struct device *dev) 336 { 337 struct fimd_context *ctx = get_fimd_context(dev); 338 339 if (ctx->suspended) 340 return; 341 342 atomic_set(&ctx->wait_vsync_event, 1); 343 344 /* 345 * wait for FIMD to signal VSYNC interrupt or return after 346 * timeout which is set to 50ms (refresh rate of 20). 347 */ 348 if (!wait_event_timeout(ctx->wait_vsync_queue, 349 !atomic_read(&ctx->wait_vsync_event), 350 DRM_HZ/20)) 351 DRM_DEBUG_KMS("vblank wait timed out.\n"); 352 } 353 354 static struct exynos_drm_manager_ops fimd_manager_ops = { 355 .dpms = fimd_dpms, 356 .apply = fimd_apply, 357 .commit = fimd_commit, 358 .enable_vblank = fimd_enable_vblank, 359 .disable_vblank = fimd_disable_vblank, 360 .wait_for_vblank = fimd_wait_for_vblank, 361 }; 362 363 static void fimd_win_mode_set(struct device *dev, 364 struct exynos_drm_overlay *overlay) 365 { 366 struct fimd_context *ctx = get_fimd_context(dev); 367 struct fimd_win_data *win_data; 368 int win; 369 unsigned long offset; 370 371 DRM_DEBUG_KMS("%s\n", __FILE__); 372 373 if (!overlay) { 374 dev_err(dev, "overlay is NULL\n"); 375 return; 376 } 377 378 win = overlay->zpos; 379 if (win == DEFAULT_ZPOS) 380 win = ctx->default_win; 381 382 if (win < 0 || win > WINDOWS_NR) 383 return; 384 385 offset = overlay->fb_x * (overlay->bpp >> 3); 386 offset += overlay->fb_y * overlay->pitch; 387 388 DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, overlay->pitch); 389 390 win_data = &ctx->win_data[win]; 391 392 win_data->offset_x = overlay->crtc_x; 393 win_data->offset_y = overlay->crtc_y; 394 win_data->ovl_width = overlay->crtc_width; 395 win_data->ovl_height = overlay->crtc_height; 396 win_data->fb_width = overlay->fb_width; 397 win_data->fb_height = overlay->fb_height; 398 win_data->dma_addr = overlay->dma_addr[0] + offset; 399 win_data->bpp = overlay->bpp; 400 win_data->buf_offsize = (overlay->fb_width - overlay->crtc_width) * 401 (overlay->bpp >> 3); 402 win_data->line_size = overlay->crtc_width * (overlay->bpp >> 3); 403 404 DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n", 405 win_data->offset_x, win_data->offset_y); 406 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", 407 win_data->ovl_width, win_data->ovl_height); 408 DRM_DEBUG_KMS("paddr = 0x%lx\n", (unsigned long)win_data->dma_addr); 409 DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n", 410 overlay->fb_width, overlay->crtc_width); 411 } 412 413 static void fimd_win_set_pixfmt(struct device *dev, unsigned int win) 414 { 415 struct fimd_context *ctx = get_fimd_context(dev); 416 struct fimd_win_data *win_data = &ctx->win_data[win]; 417 unsigned long val; 418 419 DRM_DEBUG_KMS("%s\n", __FILE__); 420 421 val = WINCONx_ENWIN; 422 423 switch (win_data->bpp) { 424 case 1: 425 val |= WINCON0_BPPMODE_1BPP; 426 val |= WINCONx_BITSWP; 427 val |= WINCONx_BURSTLEN_4WORD; 428 break; 429 case 2: 430 val |= WINCON0_BPPMODE_2BPP; 431 val |= WINCONx_BITSWP; 432 val |= WINCONx_BURSTLEN_8WORD; 433 break; 434 case 4: 435 val |= WINCON0_BPPMODE_4BPP; 436 val |= WINCONx_BITSWP; 437 val |= WINCONx_BURSTLEN_8WORD; 438 break; 439 case 8: 440 val |= WINCON0_BPPMODE_8BPP_PALETTE; 441 val |= WINCONx_BURSTLEN_8WORD; 442 val |= WINCONx_BYTSWP; 443 break; 444 case 16: 445 val |= WINCON0_BPPMODE_16BPP_565; 446 val |= WINCONx_HAWSWP; 447 val |= WINCONx_BURSTLEN_16WORD; 448 break; 449 case 24: 450 val |= WINCON0_BPPMODE_24BPP_888; 451 val |= WINCONx_WSWP; 452 val |= WINCONx_BURSTLEN_16WORD; 453 break; 454 case 32: 455 val |= WINCON1_BPPMODE_28BPP_A4888 456 | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL; 457 val |= WINCONx_WSWP; 458 val |= WINCONx_BURSTLEN_16WORD; 459 break; 460 default: 461 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n"); 462 463 val |= WINCON0_BPPMODE_24BPP_888; 464 val |= WINCONx_WSWP; 465 val |= WINCONx_BURSTLEN_16WORD; 466 break; 467 } 468 469 DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp); 470 471 writel(val, ctx->regs + WINCON(win)); 472 } 473 474 static void fimd_win_set_colkey(struct device *dev, unsigned int win) 475 { 476 struct fimd_context *ctx = get_fimd_context(dev); 477 unsigned int keycon0 = 0, keycon1 = 0; 478 479 DRM_DEBUG_KMS("%s\n", __FILE__); 480 481 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F | 482 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0); 483 484 keycon1 = WxKEYCON1_COLVAL(0xffffffff); 485 486 writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); 487 writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); 488 } 489 490 static void fimd_win_commit(struct device *dev, int zpos) 491 { 492 struct fimd_context *ctx = get_fimd_context(dev); 493 struct fimd_win_data *win_data; 494 int win = zpos; 495 unsigned long val, alpha, size; 496 unsigned int last_x; 497 unsigned int last_y; 498 499 DRM_DEBUG_KMS("%s\n", __FILE__); 500 501 if (ctx->suspended) 502 return; 503 504 if (win == DEFAULT_ZPOS) 505 win = ctx->default_win; 506 507 if (win < 0 || win > WINDOWS_NR) 508 return; 509 510 win_data = &ctx->win_data[win]; 511 512 /* 513 * SHADOWCON register is used for enabling timing. 514 * 515 * for example, once only width value of a register is set, 516 * if the dma is started then fimd hardware could malfunction so 517 * with protect window setting, the register fields with prefix '_F' 518 * wouldn't be updated at vsync also but updated once unprotect window 519 * is set. 520 */ 521 522 /* protect windows */ 523 val = readl(ctx->regs + SHADOWCON); 524 val |= SHADOWCON_WINx_PROTECT(win); 525 writel(val, ctx->regs + SHADOWCON); 526 527 /* buffer start address */ 528 val = (unsigned long)win_data->dma_addr; 529 writel(val, ctx->regs + VIDWx_BUF_START(win, 0)); 530 531 /* buffer end address */ 532 size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3); 533 val = (unsigned long)(win_data->dma_addr + size); 534 writel(val, ctx->regs + VIDWx_BUF_END(win, 0)); 535 536 DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n", 537 (unsigned long)win_data->dma_addr, val, size); 538 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", 539 win_data->ovl_width, win_data->ovl_height); 540 541 /* buffer size */ 542 val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) | 543 VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size) | 544 VIDW_BUF_SIZE_OFFSET_E(win_data->buf_offsize) | 545 VIDW_BUF_SIZE_PAGEWIDTH_E(win_data->line_size); 546 writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0)); 547 548 /* OSD position */ 549 val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) | 550 VIDOSDxA_TOPLEFT_Y(win_data->offset_y) | 551 VIDOSDxA_TOPLEFT_X_E(win_data->offset_x) | 552 VIDOSDxA_TOPLEFT_Y_E(win_data->offset_y); 553 writel(val, ctx->regs + VIDOSD_A(win)); 554 555 last_x = win_data->offset_x + win_data->ovl_width; 556 if (last_x) 557 last_x--; 558 last_y = win_data->offset_y + win_data->ovl_height; 559 if (last_y) 560 last_y--; 561 562 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) | 563 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y); 564 565 writel(val, ctx->regs + VIDOSD_B(win)); 566 567 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n", 568 win_data->offset_x, win_data->offset_y, last_x, last_y); 569 570 /* hardware window 0 doesn't support alpha channel. */ 571 if (win != 0) { 572 /* OSD alpha */ 573 alpha = VIDISD14C_ALPHA1_R(0xf) | 574 VIDISD14C_ALPHA1_G(0xf) | 575 VIDISD14C_ALPHA1_B(0xf); 576 577 writel(alpha, ctx->regs + VIDOSD_C(win)); 578 } 579 580 /* OSD size */ 581 if (win != 3 && win != 4) { 582 u32 offset = VIDOSD_D(win); 583 if (win == 0) 584 offset = VIDOSD_C_SIZE_W0; 585 val = win_data->ovl_width * win_data->ovl_height; 586 writel(val, ctx->regs + offset); 587 588 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val); 589 } 590 591 fimd_win_set_pixfmt(dev, win); 592 593 /* hardware window 0 doesn't support color key. */ 594 if (win != 0) 595 fimd_win_set_colkey(dev, win); 596 597 /* wincon */ 598 val = readl(ctx->regs + WINCON(win)); 599 val |= WINCONx_ENWIN; 600 writel(val, ctx->regs + WINCON(win)); 601 602 /* Enable DMA channel and unprotect windows */ 603 val = readl(ctx->regs + SHADOWCON); 604 val |= SHADOWCON_CHx_ENABLE(win); 605 val &= ~SHADOWCON_WINx_PROTECT(win); 606 writel(val, ctx->regs + SHADOWCON); 607 608 win_data->enabled = true; 609 } 610 611 static void fimd_win_disable(struct device *dev, int zpos) 612 { 613 struct fimd_context *ctx = get_fimd_context(dev); 614 struct fimd_win_data *win_data; 615 int win = zpos; 616 u32 val; 617 618 DRM_DEBUG_KMS("%s\n", __FILE__); 619 620 if (win == DEFAULT_ZPOS) 621 win = ctx->default_win; 622 623 if (win < 0 || win > WINDOWS_NR) 624 return; 625 626 win_data = &ctx->win_data[win]; 627 628 if (ctx->suspended) { 629 /* do not resume this window*/ 630 win_data->resume = false; 631 return; 632 } 633 634 /* protect windows */ 635 val = readl(ctx->regs + SHADOWCON); 636 val |= SHADOWCON_WINx_PROTECT(win); 637 writel(val, ctx->regs + SHADOWCON); 638 639 /* wincon */ 640 val = readl(ctx->regs + WINCON(win)); 641 val &= ~WINCONx_ENWIN; 642 writel(val, ctx->regs + WINCON(win)); 643 644 /* unprotect windows */ 645 val = readl(ctx->regs + SHADOWCON); 646 val &= ~SHADOWCON_CHx_ENABLE(win); 647 val &= ~SHADOWCON_WINx_PROTECT(win); 648 writel(val, ctx->regs + SHADOWCON); 649 650 win_data->enabled = false; 651 } 652 653 static struct exynos_drm_overlay_ops fimd_overlay_ops = { 654 .mode_set = fimd_win_mode_set, 655 .commit = fimd_win_commit, 656 .disable = fimd_win_disable, 657 }; 658 659 static struct exynos_drm_manager fimd_manager = { 660 .pipe = -1, 661 .ops = &fimd_manager_ops, 662 .overlay_ops = &fimd_overlay_ops, 663 .display_ops = &fimd_display_ops, 664 }; 665 666 static irqreturn_t fimd_irq_handler(int irq, void *dev_id) 667 { 668 struct fimd_context *ctx = (struct fimd_context *)dev_id; 669 struct exynos_drm_subdrv *subdrv = &ctx->subdrv; 670 struct drm_device *drm_dev = subdrv->drm_dev; 671 struct exynos_drm_manager *manager = subdrv->manager; 672 u32 val; 673 674 val = readl(ctx->regs + VIDINTCON1); 675 676 if (val & VIDINTCON1_INT_FRAME) 677 /* VSYNC interrupt */ 678 writel(VIDINTCON1_INT_FRAME, ctx->regs + VIDINTCON1); 679 680 /* check the crtc is detached already from encoder */ 681 if (manager->pipe < 0) 682 goto out; 683 684 drm_handle_vblank(drm_dev, manager->pipe); 685 exynos_drm_crtc_finish_pageflip(drm_dev, manager->pipe); 686 687 /* set wait vsync event to zero and wake up queue. */ 688 if (atomic_read(&ctx->wait_vsync_event)) { 689 atomic_set(&ctx->wait_vsync_event, 0); 690 DRM_WAKEUP(&ctx->wait_vsync_queue); 691 } 692 out: 693 return IRQ_HANDLED; 694 } 695 696 static int fimd_subdrv_probe(struct drm_device *drm_dev, struct device *dev) 697 { 698 DRM_DEBUG_KMS("%s\n", __FILE__); 699 700 /* 701 * enable drm irq mode. 702 * - with irq_enabled = 1, we can use the vblank feature. 703 * 704 * P.S. note that we wouldn't use drm irq handler but 705 * just specific driver own one instead because 706 * drm framework supports only one irq handler. 707 */ 708 drm_dev->irq_enabled = 1; 709 710 /* 711 * with vblank_disable_allowed = 1, vblank interrupt will be disabled 712 * by drm timer once a current process gives up ownership of 713 * vblank event.(after drm_vblank_put function is called) 714 */ 715 drm_dev->vblank_disable_allowed = 1; 716 717 /* attach this sub driver to iommu mapping if supported. */ 718 if (is_drm_iommu_supported(drm_dev)) 719 drm_iommu_attach_device(drm_dev, dev); 720 721 return 0; 722 } 723 724 static void fimd_subdrv_remove(struct drm_device *drm_dev, struct device *dev) 725 { 726 DRM_DEBUG_KMS("%s\n", __FILE__); 727 728 /* detach this sub driver from iommu mapping if supported. */ 729 if (is_drm_iommu_supported(drm_dev)) 730 drm_iommu_detach_device(drm_dev, dev); 731 } 732 733 static int fimd_calc_clkdiv(struct fimd_context *ctx, 734 struct fb_videomode *timing) 735 { 736 unsigned long clk = clk_get_rate(ctx->lcd_clk); 737 u32 retrace; 738 u32 clkdiv; 739 u32 best_framerate = 0; 740 u32 framerate; 741 742 DRM_DEBUG_KMS("%s\n", __FILE__); 743 744 retrace = timing->left_margin + timing->hsync_len + 745 timing->right_margin + timing->xres; 746 retrace *= timing->upper_margin + timing->vsync_len + 747 timing->lower_margin + timing->yres; 748 749 /* default framerate is 60Hz */ 750 if (!timing->refresh) 751 timing->refresh = 60; 752 753 clk /= retrace; 754 755 for (clkdiv = 1; clkdiv < 0x100; clkdiv++) { 756 int tmp; 757 758 /* get best framerate */ 759 framerate = clk / clkdiv; 760 tmp = timing->refresh - framerate; 761 if (tmp < 0) { 762 best_framerate = framerate; 763 continue; 764 } else { 765 if (!best_framerate) 766 best_framerate = framerate; 767 else if (tmp < (best_framerate - framerate)) 768 best_framerate = framerate; 769 break; 770 } 771 } 772 773 return clkdiv; 774 } 775 776 static void fimd_clear_win(struct fimd_context *ctx, int win) 777 { 778 u32 val; 779 780 DRM_DEBUG_KMS("%s\n", __FILE__); 781 782 writel(0, ctx->regs + WINCON(win)); 783 writel(0, ctx->regs + VIDOSD_A(win)); 784 writel(0, ctx->regs + VIDOSD_B(win)); 785 writel(0, ctx->regs + VIDOSD_C(win)); 786 787 if (win == 1 || win == 2) 788 writel(0, ctx->regs + VIDOSD_D(win)); 789 790 val = readl(ctx->regs + SHADOWCON); 791 val &= ~SHADOWCON_WINx_PROTECT(win); 792 writel(val, ctx->regs + SHADOWCON); 793 } 794 795 static int fimd_clock(struct fimd_context *ctx, bool enable) 796 { 797 DRM_DEBUG_KMS("%s\n", __FILE__); 798 799 if (enable) { 800 int ret; 801 802 ret = clk_enable(ctx->bus_clk); 803 if (ret < 0) 804 return ret; 805 806 ret = clk_enable(ctx->lcd_clk); 807 if (ret < 0) { 808 clk_disable(ctx->bus_clk); 809 return ret; 810 } 811 } else { 812 clk_disable(ctx->lcd_clk); 813 clk_disable(ctx->bus_clk); 814 } 815 816 return 0; 817 } 818 819 static void fimd_window_suspend(struct device *dev) 820 { 821 struct fimd_context *ctx = get_fimd_context(dev); 822 struct fimd_win_data *win_data; 823 int i; 824 825 for (i = 0; i < WINDOWS_NR; i++) { 826 win_data = &ctx->win_data[i]; 827 win_data->resume = win_data->enabled; 828 fimd_win_disable(dev, i); 829 } 830 fimd_wait_for_vblank(dev); 831 } 832 833 static void fimd_window_resume(struct device *dev) 834 { 835 struct fimd_context *ctx = get_fimd_context(dev); 836 struct fimd_win_data *win_data; 837 int i; 838 839 for (i = 0; i < WINDOWS_NR; i++) { 840 win_data = &ctx->win_data[i]; 841 win_data->enabled = win_data->resume; 842 win_data->resume = false; 843 } 844 } 845 846 static int fimd_activate(struct fimd_context *ctx, bool enable) 847 { 848 struct device *dev = ctx->subdrv.dev; 849 if (enable) { 850 int ret; 851 852 ret = fimd_clock(ctx, true); 853 if (ret < 0) 854 return ret; 855 856 ctx->suspended = false; 857 858 /* if vblank was enabled status, enable it again. */ 859 if (test_and_clear_bit(0, &ctx->irq_flags)) 860 fimd_enable_vblank(dev); 861 862 fimd_window_resume(dev); 863 } else { 864 fimd_window_suspend(dev); 865 866 fimd_clock(ctx, false); 867 ctx->suspended = true; 868 } 869 870 return 0; 871 } 872 873 static int fimd_probe(struct platform_device *pdev) 874 { 875 struct device *dev = &pdev->dev; 876 struct fimd_context *ctx; 877 struct exynos_drm_subdrv *subdrv; 878 struct exynos_drm_fimd_pdata *pdata; 879 struct exynos_drm_panel_info *panel; 880 struct resource *res; 881 int win; 882 int ret = -EINVAL; 883 884 DRM_DEBUG_KMS("%s\n", __FILE__); 885 886 pdata = pdev->dev.platform_data; 887 if (!pdata) { 888 dev_err(dev, "no platform data specified\n"); 889 return -EINVAL; 890 } 891 892 panel = &pdata->panel; 893 if (!panel) { 894 dev_err(dev, "panel is null.\n"); 895 return -EINVAL; 896 } 897 898 ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL); 899 if (!ctx) 900 return -ENOMEM; 901 902 ctx->bus_clk = devm_clk_get(dev, "fimd"); 903 if (IS_ERR(ctx->bus_clk)) { 904 dev_err(dev, "failed to get bus clock\n"); 905 return PTR_ERR(ctx->bus_clk); 906 } 907 908 ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd"); 909 if (IS_ERR(ctx->lcd_clk)) { 910 dev_err(dev, "failed to get lcd clock\n"); 911 return PTR_ERR(ctx->lcd_clk); 912 } 913 914 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 915 916 ctx->regs = devm_request_and_ioremap(&pdev->dev, res); 917 if (!ctx->regs) { 918 dev_err(dev, "failed to map registers\n"); 919 return -ENXIO; 920 } 921 922 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 923 if (!res) { 924 dev_err(dev, "irq request failed.\n"); 925 return -ENXIO; 926 } 927 928 ctx->irq = res->start; 929 930 ret = devm_request_irq(&pdev->dev, ctx->irq, fimd_irq_handler, 931 0, "drm_fimd", ctx); 932 if (ret) { 933 dev_err(dev, "irq request failed.\n"); 934 return ret; 935 } 936 937 ctx->vidcon0 = pdata->vidcon0; 938 ctx->vidcon1 = pdata->vidcon1; 939 ctx->default_win = pdata->default_win; 940 ctx->panel = panel; 941 DRM_INIT_WAITQUEUE(&ctx->wait_vsync_queue); 942 atomic_set(&ctx->wait_vsync_event, 0); 943 944 subdrv = &ctx->subdrv; 945 946 subdrv->dev = dev; 947 subdrv->manager = &fimd_manager; 948 subdrv->probe = fimd_subdrv_probe; 949 subdrv->remove = fimd_subdrv_remove; 950 951 mutex_init(&ctx->lock); 952 953 platform_set_drvdata(pdev, ctx); 954 955 pm_runtime_enable(dev); 956 pm_runtime_get_sync(dev); 957 958 ctx->clkdiv = fimd_calc_clkdiv(ctx, &panel->timing); 959 panel->timing.pixclock = clk_get_rate(ctx->lcd_clk) / ctx->clkdiv; 960 961 DRM_DEBUG_KMS("pixel clock = %d, clkdiv = %d\n", 962 panel->timing.pixclock, ctx->clkdiv); 963 964 for (win = 0; win < WINDOWS_NR; win++) 965 fimd_clear_win(ctx, win); 966 967 exynos_drm_subdrv_register(subdrv); 968 969 return 0; 970 } 971 972 static int fimd_remove(struct platform_device *pdev) 973 { 974 struct device *dev = &pdev->dev; 975 struct fimd_context *ctx = platform_get_drvdata(pdev); 976 977 DRM_DEBUG_KMS("%s\n", __FILE__); 978 979 exynos_drm_subdrv_unregister(&ctx->subdrv); 980 981 if (ctx->suspended) 982 goto out; 983 984 clk_disable(ctx->lcd_clk); 985 clk_disable(ctx->bus_clk); 986 987 pm_runtime_set_suspended(dev); 988 pm_runtime_put_sync(dev); 989 990 out: 991 pm_runtime_disable(dev); 992 993 return 0; 994 } 995 996 #ifdef CONFIG_PM_SLEEP 997 static int fimd_suspend(struct device *dev) 998 { 999 struct fimd_context *ctx = get_fimd_context(dev); 1000 1001 /* 1002 * do not use pm_runtime_suspend(). if pm_runtime_suspend() is 1003 * called here, an error would be returned by that interface 1004 * because the usage_count of pm runtime is more than 1. 1005 */ 1006 if (!pm_runtime_suspended(dev)) 1007 return fimd_activate(ctx, false); 1008 1009 return 0; 1010 } 1011 1012 static int fimd_resume(struct device *dev) 1013 { 1014 struct fimd_context *ctx = get_fimd_context(dev); 1015 1016 /* 1017 * if entered to sleep when lcd panel was on, the usage_count 1018 * of pm runtime would still be 1 so in this case, fimd driver 1019 * should be on directly not drawing on pm runtime interface. 1020 */ 1021 if (!pm_runtime_suspended(dev)) { 1022 int ret; 1023 1024 ret = fimd_activate(ctx, true); 1025 if (ret < 0) 1026 return ret; 1027 1028 /* 1029 * in case of dpms on(standby), fimd_apply function will 1030 * be called by encoder's dpms callback to update fimd's 1031 * registers but in case of sleep wakeup, it's not. 1032 * so fimd_apply function should be called at here. 1033 */ 1034 fimd_apply(dev); 1035 } 1036 1037 return 0; 1038 } 1039 #endif 1040 1041 #ifdef CONFIG_PM_RUNTIME 1042 static int fimd_runtime_suspend(struct device *dev) 1043 { 1044 struct fimd_context *ctx = get_fimd_context(dev); 1045 1046 DRM_DEBUG_KMS("%s\n", __FILE__); 1047 1048 return fimd_activate(ctx, false); 1049 } 1050 1051 static int fimd_runtime_resume(struct device *dev) 1052 { 1053 struct fimd_context *ctx = get_fimd_context(dev); 1054 1055 DRM_DEBUG_KMS("%s\n", __FILE__); 1056 1057 return fimd_activate(ctx, true); 1058 } 1059 #endif 1060 1061 static struct platform_device_id fimd_driver_ids[] = { 1062 { 1063 .name = "exynos4-fb", 1064 .driver_data = (unsigned long)&exynos4_fimd_driver_data, 1065 }, { 1066 .name = "exynos5-fb", 1067 .driver_data = (unsigned long)&exynos5_fimd_driver_data, 1068 }, 1069 {}, 1070 }; 1071 MODULE_DEVICE_TABLE(platform, fimd_driver_ids); 1072 1073 static const struct dev_pm_ops fimd_pm_ops = { 1074 SET_SYSTEM_SLEEP_PM_OPS(fimd_suspend, fimd_resume) 1075 SET_RUNTIME_PM_OPS(fimd_runtime_suspend, fimd_runtime_resume, NULL) 1076 }; 1077 1078 struct platform_driver fimd_driver = { 1079 .probe = fimd_probe, 1080 .remove = fimd_remove, 1081 .id_table = fimd_driver_ids, 1082 .driver = { 1083 .name = "exynos4-fb", 1084 .owner = THIS_MODULE, 1085 .pm = &fimd_pm_ops, 1086 .of_match_table = of_match_ptr(fimd_driver_dt_match), 1087 }, 1088 }; 1089