1 /* 2 * Copyright (C) 2012 Samsung Electronics Co.Ltd 3 * Authors: 4 * Eunchul Kim <chulspro.kim@samsung.com> 5 * Jinyoung Jeon <jy0.jeon@samsung.com> 6 * Sangmin Lee <lsmin.lee@samsung.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 */ 14 #include <linux/kernel.h> 15 #include <linux/platform_device.h> 16 #include <linux/mfd/syscon.h> 17 #include <linux/regmap.h> 18 #include <linux/clk.h> 19 #include <linux/pm_runtime.h> 20 21 #include <drm/drmP.h> 22 #include <drm/exynos_drm.h> 23 #include "regs-fimc.h" 24 #include "exynos_drm_ipp.h" 25 #include "exynos_drm_fimc.h" 26 27 /* 28 * FIMC stands for Fully Interactive Mobile Camera and 29 * supports image scaler/rotator and input/output DMA operations. 30 * input DMA reads image data from the memory. 31 * output DMA writes image data to memory. 32 * FIMC supports image rotation and image effect functions. 33 * 34 * M2M operation : supports crop/scale/rotation/csc so on. 35 * Memory ----> FIMC H/W ----> Memory. 36 * Writeback operation : supports cloned screen with FIMD. 37 * FIMD ----> FIMC H/W ----> Memory. 38 * Output operation : supports direct display using local path. 39 * Memory ----> FIMC H/W ----> FIMD. 40 */ 41 42 /* 43 * TODO 44 * 1. check suspend/resume api if needed. 45 * 2. need to check use case platform_device_id. 46 * 3. check src/dst size with, height. 47 * 4. added check_prepare api for right register. 48 * 5. need to add supported list in prop_list. 49 * 6. check prescaler/scaler optimization. 50 */ 51 52 #define FIMC_MAX_DEVS 4 53 #define FIMC_MAX_SRC 2 54 #define FIMC_MAX_DST 32 55 #define FIMC_SHFACTOR 10 56 #define FIMC_BUF_STOP 1 57 #define FIMC_BUF_START 2 58 #define FIMC_REG_SZ 32 59 #define FIMC_WIDTH_ITU_709 1280 60 #define FIMC_REFRESH_MAX 60 61 #define FIMC_REFRESH_MIN 12 62 #define FIMC_CROP_MAX 8192 63 #define FIMC_CROP_MIN 32 64 #define FIMC_SCALE_MAX 4224 65 #define FIMC_SCALE_MIN 32 66 67 #define get_fimc_context(dev) platform_get_drvdata(to_platform_device(dev)) 68 #define get_ctx_from_ippdrv(ippdrv) container_of(ippdrv,\ 69 struct fimc_context, ippdrv); 70 #define fimc_read(offset) readl(ctx->regs + (offset)) 71 #define fimc_write(cfg, offset) writel(cfg, ctx->regs + (offset)) 72 73 enum fimc_wb { 74 FIMC_WB_NONE, 75 FIMC_WB_A, 76 FIMC_WB_B, 77 }; 78 79 enum { 80 FIMC_CLK_LCLK, 81 FIMC_CLK_GATE, 82 FIMC_CLK_WB_A, 83 FIMC_CLK_WB_B, 84 FIMC_CLK_MUX, 85 FIMC_CLK_PARENT, 86 FIMC_CLKS_MAX 87 }; 88 89 static const char * const fimc_clock_names[] = { 90 [FIMC_CLK_LCLK] = "sclk_fimc", 91 [FIMC_CLK_GATE] = "fimc", 92 [FIMC_CLK_WB_A] = "pxl_async0", 93 [FIMC_CLK_WB_B] = "pxl_async1", 94 [FIMC_CLK_MUX] = "mux", 95 [FIMC_CLK_PARENT] = "parent", 96 }; 97 98 #define FIMC_DEFAULT_LCLK_FREQUENCY 133000000UL 99 100 /* 101 * A structure of scaler. 102 * 103 * @range: narrow, wide. 104 * @bypass: unused scaler path. 105 * @up_h: horizontal scale up. 106 * @up_v: vertical scale up. 107 * @hratio: horizontal ratio. 108 * @vratio: vertical ratio. 109 */ 110 struct fimc_scaler { 111 bool range; 112 bool bypass; 113 bool up_h; 114 bool up_v; 115 u32 hratio; 116 u32 vratio; 117 }; 118 119 /* 120 * A structure of scaler capability. 121 * 122 * find user manual table 43-1. 123 * @in_hori: scaler input horizontal size. 124 * @bypass: scaler bypass mode. 125 * @dst_h_wo_rot: target horizontal size without output rotation. 126 * @dst_h_rot: target horizontal size with output rotation. 127 * @rl_w_wo_rot: real width without input rotation. 128 * @rl_h_rot: real height without output rotation. 129 */ 130 struct fimc_capability { 131 /* scaler */ 132 u32 in_hori; 133 u32 bypass; 134 /* output rotator */ 135 u32 dst_h_wo_rot; 136 u32 dst_h_rot; 137 /* input rotator */ 138 u32 rl_w_wo_rot; 139 u32 rl_h_rot; 140 }; 141 142 /* 143 * A structure of fimc context. 144 * 145 * @ippdrv: prepare initialization using ippdrv. 146 * @regs_res: register resources. 147 * @regs: memory mapped io registers. 148 * @lock: locking of operations. 149 * @clocks: fimc clocks. 150 * @clk_frequency: LCLK clock frequency. 151 * @sysreg: handle to SYSREG block regmap. 152 * @sc: scaler infomations. 153 * @pol: porarity of writeback. 154 * @id: fimc id. 155 * @irq: irq number. 156 * @suspended: qos operations. 157 */ 158 struct fimc_context { 159 struct exynos_drm_ippdrv ippdrv; 160 struct resource *regs_res; 161 void __iomem *regs; 162 struct mutex lock; 163 struct clk *clocks[FIMC_CLKS_MAX]; 164 u32 clk_frequency; 165 struct regmap *sysreg; 166 struct fimc_scaler sc; 167 struct exynos_drm_ipp_pol pol; 168 int id; 169 int irq; 170 bool suspended; 171 }; 172 173 static void fimc_sw_reset(struct fimc_context *ctx) 174 { 175 u32 cfg; 176 177 /* stop dma operation */ 178 cfg = fimc_read(EXYNOS_CISTATUS); 179 if (EXYNOS_CISTATUS_GET_ENVID_STATUS(cfg)) { 180 cfg = fimc_read(EXYNOS_MSCTRL); 181 cfg &= ~EXYNOS_MSCTRL_ENVID; 182 fimc_write(cfg, EXYNOS_MSCTRL); 183 } 184 185 cfg = fimc_read(EXYNOS_CISRCFMT); 186 cfg |= EXYNOS_CISRCFMT_ITU601_8BIT; 187 fimc_write(cfg, EXYNOS_CISRCFMT); 188 189 /* disable image capture */ 190 cfg = fimc_read(EXYNOS_CIIMGCPT); 191 cfg &= ~(EXYNOS_CIIMGCPT_IMGCPTEN_SC | EXYNOS_CIIMGCPT_IMGCPTEN); 192 fimc_write(cfg, EXYNOS_CIIMGCPT); 193 194 /* s/w reset */ 195 cfg = fimc_read(EXYNOS_CIGCTRL); 196 cfg |= (EXYNOS_CIGCTRL_SWRST); 197 fimc_write(cfg, EXYNOS_CIGCTRL); 198 199 /* s/w reset complete */ 200 cfg = fimc_read(EXYNOS_CIGCTRL); 201 cfg &= ~EXYNOS_CIGCTRL_SWRST; 202 fimc_write(cfg, EXYNOS_CIGCTRL); 203 204 /* reset sequence */ 205 fimc_write(0x0, EXYNOS_CIFCNTSEQ); 206 } 207 208 static int fimc_set_camblk_fimd0_wb(struct fimc_context *ctx) 209 { 210 return regmap_update_bits(ctx->sysreg, SYSREG_CAMERA_BLK, 211 SYSREG_FIMD0WB_DEST_MASK, 212 ctx->id << SYSREG_FIMD0WB_DEST_SHIFT); 213 } 214 215 static void fimc_set_type_ctrl(struct fimc_context *ctx, enum fimc_wb wb) 216 { 217 u32 cfg; 218 219 DRM_DEBUG_KMS("wb[%d]\n", wb); 220 221 cfg = fimc_read(EXYNOS_CIGCTRL); 222 cfg &= ~(EXYNOS_CIGCTRL_TESTPATTERN_MASK | 223 EXYNOS_CIGCTRL_SELCAM_ITU_MASK | 224 EXYNOS_CIGCTRL_SELCAM_MIPI_MASK | 225 EXYNOS_CIGCTRL_SELCAM_FIMC_MASK | 226 EXYNOS_CIGCTRL_SELWB_CAMIF_MASK | 227 EXYNOS_CIGCTRL_SELWRITEBACK_MASK); 228 229 switch (wb) { 230 case FIMC_WB_A: 231 cfg |= (EXYNOS_CIGCTRL_SELWRITEBACK_A | 232 EXYNOS_CIGCTRL_SELWB_CAMIF_WRITEBACK); 233 break; 234 case FIMC_WB_B: 235 cfg |= (EXYNOS_CIGCTRL_SELWRITEBACK_B | 236 EXYNOS_CIGCTRL_SELWB_CAMIF_WRITEBACK); 237 break; 238 case FIMC_WB_NONE: 239 default: 240 cfg |= (EXYNOS_CIGCTRL_SELCAM_ITU_A | 241 EXYNOS_CIGCTRL_SELWRITEBACK_A | 242 EXYNOS_CIGCTRL_SELCAM_MIPI_A | 243 EXYNOS_CIGCTRL_SELCAM_FIMC_ITU); 244 break; 245 } 246 247 fimc_write(cfg, EXYNOS_CIGCTRL); 248 } 249 250 static void fimc_set_polarity(struct fimc_context *ctx, 251 struct exynos_drm_ipp_pol *pol) 252 { 253 u32 cfg; 254 255 DRM_DEBUG_KMS("inv_pclk[%d]inv_vsync[%d]\n", 256 pol->inv_pclk, pol->inv_vsync); 257 DRM_DEBUG_KMS("inv_href[%d]inv_hsync[%d]\n", 258 pol->inv_href, pol->inv_hsync); 259 260 cfg = fimc_read(EXYNOS_CIGCTRL); 261 cfg &= ~(EXYNOS_CIGCTRL_INVPOLPCLK | EXYNOS_CIGCTRL_INVPOLVSYNC | 262 EXYNOS_CIGCTRL_INVPOLHREF | EXYNOS_CIGCTRL_INVPOLHSYNC); 263 264 if (pol->inv_pclk) 265 cfg |= EXYNOS_CIGCTRL_INVPOLPCLK; 266 if (pol->inv_vsync) 267 cfg |= EXYNOS_CIGCTRL_INVPOLVSYNC; 268 if (pol->inv_href) 269 cfg |= EXYNOS_CIGCTRL_INVPOLHREF; 270 if (pol->inv_hsync) 271 cfg |= EXYNOS_CIGCTRL_INVPOLHSYNC; 272 273 fimc_write(cfg, EXYNOS_CIGCTRL); 274 } 275 276 static void fimc_handle_jpeg(struct fimc_context *ctx, bool enable) 277 { 278 u32 cfg; 279 280 DRM_DEBUG_KMS("enable[%d]\n", enable); 281 282 cfg = fimc_read(EXYNOS_CIGCTRL); 283 if (enable) 284 cfg |= EXYNOS_CIGCTRL_CAM_JPEG; 285 else 286 cfg &= ~EXYNOS_CIGCTRL_CAM_JPEG; 287 288 fimc_write(cfg, EXYNOS_CIGCTRL); 289 } 290 291 static void fimc_handle_irq(struct fimc_context *ctx, bool enable, 292 bool overflow, bool level) 293 { 294 u32 cfg; 295 296 DRM_DEBUG_KMS("enable[%d]overflow[%d]level[%d]\n", 297 enable, overflow, level); 298 299 cfg = fimc_read(EXYNOS_CIGCTRL); 300 if (enable) { 301 cfg &= ~(EXYNOS_CIGCTRL_IRQ_OVFEN | EXYNOS_CIGCTRL_IRQ_LEVEL); 302 cfg |= EXYNOS_CIGCTRL_IRQ_ENABLE; 303 if (overflow) 304 cfg |= EXYNOS_CIGCTRL_IRQ_OVFEN; 305 if (level) 306 cfg |= EXYNOS_CIGCTRL_IRQ_LEVEL; 307 } else 308 cfg &= ~(EXYNOS_CIGCTRL_IRQ_OVFEN | EXYNOS_CIGCTRL_IRQ_ENABLE); 309 310 fimc_write(cfg, EXYNOS_CIGCTRL); 311 } 312 313 static void fimc_clear_irq(struct fimc_context *ctx) 314 { 315 u32 cfg; 316 317 cfg = fimc_read(EXYNOS_CIGCTRL); 318 cfg |= EXYNOS_CIGCTRL_IRQ_CLR; 319 fimc_write(cfg, EXYNOS_CIGCTRL); 320 } 321 322 static bool fimc_check_ovf(struct fimc_context *ctx) 323 { 324 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 325 u32 cfg, status, flag; 326 327 status = fimc_read(EXYNOS_CISTATUS); 328 flag = EXYNOS_CISTATUS_OVFIY | EXYNOS_CISTATUS_OVFICB | 329 EXYNOS_CISTATUS_OVFICR; 330 331 DRM_DEBUG_KMS("flag[0x%x]\n", flag); 332 333 if (status & flag) { 334 cfg = fimc_read(EXYNOS_CIWDOFST); 335 cfg |= (EXYNOS_CIWDOFST_CLROVFIY | EXYNOS_CIWDOFST_CLROVFICB | 336 EXYNOS_CIWDOFST_CLROVFICR); 337 338 fimc_write(cfg, EXYNOS_CIWDOFST); 339 340 cfg = fimc_read(EXYNOS_CIWDOFST); 341 cfg &= ~(EXYNOS_CIWDOFST_CLROVFIY | EXYNOS_CIWDOFST_CLROVFICB | 342 EXYNOS_CIWDOFST_CLROVFICR); 343 344 fimc_write(cfg, EXYNOS_CIWDOFST); 345 346 dev_err(ippdrv->dev, "occured overflow at %d, status 0x%x.\n", 347 ctx->id, status); 348 return true; 349 } 350 351 return false; 352 } 353 354 static bool fimc_check_frame_end(struct fimc_context *ctx) 355 { 356 u32 cfg; 357 358 cfg = fimc_read(EXYNOS_CISTATUS); 359 360 DRM_DEBUG_KMS("cfg[0x%x]\n", cfg); 361 362 if (!(cfg & EXYNOS_CISTATUS_FRAMEEND)) 363 return false; 364 365 cfg &= ~(EXYNOS_CISTATUS_FRAMEEND); 366 fimc_write(cfg, EXYNOS_CISTATUS); 367 368 return true; 369 } 370 371 static int fimc_get_buf_id(struct fimc_context *ctx) 372 { 373 u32 cfg; 374 int frame_cnt, buf_id; 375 376 cfg = fimc_read(EXYNOS_CISTATUS2); 377 frame_cnt = EXYNOS_CISTATUS2_GET_FRAMECOUNT_BEFORE(cfg); 378 379 if (frame_cnt == 0) 380 frame_cnt = EXYNOS_CISTATUS2_GET_FRAMECOUNT_PRESENT(cfg); 381 382 DRM_DEBUG_KMS("present[%d]before[%d]\n", 383 EXYNOS_CISTATUS2_GET_FRAMECOUNT_PRESENT(cfg), 384 EXYNOS_CISTATUS2_GET_FRAMECOUNT_BEFORE(cfg)); 385 386 if (frame_cnt == 0) { 387 DRM_ERROR("failed to get frame count.\n"); 388 return -EIO; 389 } 390 391 buf_id = frame_cnt - 1; 392 DRM_DEBUG_KMS("buf_id[%d]\n", buf_id); 393 394 return buf_id; 395 } 396 397 static void fimc_handle_lastend(struct fimc_context *ctx, bool enable) 398 { 399 u32 cfg; 400 401 DRM_DEBUG_KMS("enable[%d]\n", enable); 402 403 cfg = fimc_read(EXYNOS_CIOCTRL); 404 if (enable) 405 cfg |= EXYNOS_CIOCTRL_LASTENDEN; 406 else 407 cfg &= ~EXYNOS_CIOCTRL_LASTENDEN; 408 409 fimc_write(cfg, EXYNOS_CIOCTRL); 410 } 411 412 413 static int fimc_src_set_fmt_order(struct fimc_context *ctx, u32 fmt) 414 { 415 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 416 u32 cfg; 417 418 DRM_DEBUG_KMS("fmt[0x%x]\n", fmt); 419 420 /* RGB */ 421 cfg = fimc_read(EXYNOS_CISCCTRL); 422 cfg &= ~EXYNOS_CISCCTRL_INRGB_FMT_RGB_MASK; 423 424 switch (fmt) { 425 case DRM_FORMAT_RGB565: 426 cfg |= EXYNOS_CISCCTRL_INRGB_FMT_RGB565; 427 fimc_write(cfg, EXYNOS_CISCCTRL); 428 return 0; 429 case DRM_FORMAT_RGB888: 430 case DRM_FORMAT_XRGB8888: 431 cfg |= EXYNOS_CISCCTRL_INRGB_FMT_RGB888; 432 fimc_write(cfg, EXYNOS_CISCCTRL); 433 return 0; 434 default: 435 /* bypass */ 436 break; 437 } 438 439 /* YUV */ 440 cfg = fimc_read(EXYNOS_MSCTRL); 441 cfg &= ~(EXYNOS_MSCTRL_ORDER2P_SHIFT_MASK | 442 EXYNOS_MSCTRL_C_INT_IN_2PLANE | 443 EXYNOS_MSCTRL_ORDER422_YCBYCR); 444 445 switch (fmt) { 446 case DRM_FORMAT_YUYV: 447 cfg |= EXYNOS_MSCTRL_ORDER422_YCBYCR; 448 break; 449 case DRM_FORMAT_YVYU: 450 cfg |= EXYNOS_MSCTRL_ORDER422_YCRYCB; 451 break; 452 case DRM_FORMAT_UYVY: 453 cfg |= EXYNOS_MSCTRL_ORDER422_CBYCRY; 454 break; 455 case DRM_FORMAT_VYUY: 456 case DRM_FORMAT_YUV444: 457 cfg |= EXYNOS_MSCTRL_ORDER422_CRYCBY; 458 break; 459 case DRM_FORMAT_NV21: 460 case DRM_FORMAT_NV61: 461 cfg |= (EXYNOS_MSCTRL_ORDER2P_LSB_CRCB | 462 EXYNOS_MSCTRL_C_INT_IN_2PLANE); 463 break; 464 case DRM_FORMAT_YUV422: 465 case DRM_FORMAT_YUV420: 466 case DRM_FORMAT_YVU420: 467 cfg |= EXYNOS_MSCTRL_C_INT_IN_3PLANE; 468 break; 469 case DRM_FORMAT_NV12: 470 case DRM_FORMAT_NV12MT: 471 case DRM_FORMAT_NV16: 472 cfg |= (EXYNOS_MSCTRL_ORDER2P_LSB_CBCR | 473 EXYNOS_MSCTRL_C_INT_IN_2PLANE); 474 break; 475 default: 476 dev_err(ippdrv->dev, "inavlid source yuv order 0x%x.\n", fmt); 477 return -EINVAL; 478 } 479 480 fimc_write(cfg, EXYNOS_MSCTRL); 481 482 return 0; 483 } 484 485 static int fimc_src_set_fmt(struct device *dev, u32 fmt) 486 { 487 struct fimc_context *ctx = get_fimc_context(dev); 488 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 489 u32 cfg; 490 491 DRM_DEBUG_KMS("fmt[0x%x]\n", fmt); 492 493 cfg = fimc_read(EXYNOS_MSCTRL); 494 cfg &= ~EXYNOS_MSCTRL_INFORMAT_RGB; 495 496 switch (fmt) { 497 case DRM_FORMAT_RGB565: 498 case DRM_FORMAT_RGB888: 499 case DRM_FORMAT_XRGB8888: 500 cfg |= EXYNOS_MSCTRL_INFORMAT_RGB; 501 break; 502 case DRM_FORMAT_YUV444: 503 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR420; 504 break; 505 case DRM_FORMAT_YUYV: 506 case DRM_FORMAT_YVYU: 507 case DRM_FORMAT_UYVY: 508 case DRM_FORMAT_VYUY: 509 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR422_1PLANE; 510 break; 511 case DRM_FORMAT_NV16: 512 case DRM_FORMAT_NV61: 513 case DRM_FORMAT_YUV422: 514 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR422; 515 break; 516 case DRM_FORMAT_YUV420: 517 case DRM_FORMAT_YVU420: 518 case DRM_FORMAT_NV12: 519 case DRM_FORMAT_NV21: 520 case DRM_FORMAT_NV12MT: 521 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR420; 522 break; 523 default: 524 dev_err(ippdrv->dev, "inavlid source format 0x%x.\n", fmt); 525 return -EINVAL; 526 } 527 528 fimc_write(cfg, EXYNOS_MSCTRL); 529 530 cfg = fimc_read(EXYNOS_CIDMAPARAM); 531 cfg &= ~EXYNOS_CIDMAPARAM_R_MODE_MASK; 532 533 if (fmt == DRM_FORMAT_NV12MT) 534 cfg |= EXYNOS_CIDMAPARAM_R_MODE_64X32; 535 else 536 cfg |= EXYNOS_CIDMAPARAM_R_MODE_LINEAR; 537 538 fimc_write(cfg, EXYNOS_CIDMAPARAM); 539 540 return fimc_src_set_fmt_order(ctx, fmt); 541 } 542 543 static int fimc_src_set_transf(struct device *dev, 544 enum drm_exynos_degree degree, 545 enum drm_exynos_flip flip, bool *swap) 546 { 547 struct fimc_context *ctx = get_fimc_context(dev); 548 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 549 u32 cfg1, cfg2; 550 551 DRM_DEBUG_KMS("degree[%d]flip[0x%x]\n", degree, flip); 552 553 cfg1 = fimc_read(EXYNOS_MSCTRL); 554 cfg1 &= ~(EXYNOS_MSCTRL_FLIP_X_MIRROR | 555 EXYNOS_MSCTRL_FLIP_Y_MIRROR); 556 557 cfg2 = fimc_read(EXYNOS_CITRGFMT); 558 cfg2 &= ~EXYNOS_CITRGFMT_INROT90_CLOCKWISE; 559 560 switch (degree) { 561 case EXYNOS_DRM_DEGREE_0: 562 if (flip & EXYNOS_DRM_FLIP_VERTICAL) 563 cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR; 564 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) 565 cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR; 566 break; 567 case EXYNOS_DRM_DEGREE_90: 568 cfg2 |= EXYNOS_CITRGFMT_INROT90_CLOCKWISE; 569 if (flip & EXYNOS_DRM_FLIP_VERTICAL) 570 cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR; 571 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) 572 cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR; 573 break; 574 case EXYNOS_DRM_DEGREE_180: 575 cfg1 |= (EXYNOS_MSCTRL_FLIP_X_MIRROR | 576 EXYNOS_MSCTRL_FLIP_Y_MIRROR); 577 if (flip & EXYNOS_DRM_FLIP_VERTICAL) 578 cfg1 &= ~EXYNOS_MSCTRL_FLIP_X_MIRROR; 579 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) 580 cfg1 &= ~EXYNOS_MSCTRL_FLIP_Y_MIRROR; 581 break; 582 case EXYNOS_DRM_DEGREE_270: 583 cfg1 |= (EXYNOS_MSCTRL_FLIP_X_MIRROR | 584 EXYNOS_MSCTRL_FLIP_Y_MIRROR); 585 cfg2 |= EXYNOS_CITRGFMT_INROT90_CLOCKWISE; 586 if (flip & EXYNOS_DRM_FLIP_VERTICAL) 587 cfg1 &= ~EXYNOS_MSCTRL_FLIP_X_MIRROR; 588 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) 589 cfg1 &= ~EXYNOS_MSCTRL_FLIP_Y_MIRROR; 590 break; 591 default: 592 dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree); 593 return -EINVAL; 594 } 595 596 fimc_write(cfg1, EXYNOS_MSCTRL); 597 fimc_write(cfg2, EXYNOS_CITRGFMT); 598 *swap = (cfg2 & EXYNOS_CITRGFMT_INROT90_CLOCKWISE) ? 1 : 0; 599 600 return 0; 601 } 602 603 static int fimc_set_window(struct fimc_context *ctx, 604 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz) 605 { 606 u32 cfg, h1, h2, v1, v2; 607 608 /* cropped image */ 609 h1 = pos->x; 610 h2 = sz->hsize - pos->w - pos->x; 611 v1 = pos->y; 612 v2 = sz->vsize - pos->h - pos->y; 613 614 DRM_DEBUG_KMS("x[%d]y[%d]w[%d]h[%d]hsize[%d]vsize[%d]\n", 615 pos->x, pos->y, pos->w, pos->h, sz->hsize, sz->vsize); 616 DRM_DEBUG_KMS("h1[%d]h2[%d]v1[%d]v2[%d]\n", h1, h2, v1, v2); 617 618 /* 619 * set window offset 1, 2 size 620 * check figure 43-21 in user manual 621 */ 622 cfg = fimc_read(EXYNOS_CIWDOFST); 623 cfg &= ~(EXYNOS_CIWDOFST_WINHOROFST_MASK | 624 EXYNOS_CIWDOFST_WINVEROFST_MASK); 625 cfg |= (EXYNOS_CIWDOFST_WINHOROFST(h1) | 626 EXYNOS_CIWDOFST_WINVEROFST(v1)); 627 cfg |= EXYNOS_CIWDOFST_WINOFSEN; 628 fimc_write(cfg, EXYNOS_CIWDOFST); 629 630 cfg = (EXYNOS_CIWDOFST2_WINHOROFST2(h2) | 631 EXYNOS_CIWDOFST2_WINVEROFST2(v2)); 632 fimc_write(cfg, EXYNOS_CIWDOFST2); 633 634 return 0; 635 } 636 637 static int fimc_src_set_size(struct device *dev, int swap, 638 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz) 639 { 640 struct fimc_context *ctx = get_fimc_context(dev); 641 struct drm_exynos_pos img_pos = *pos; 642 struct drm_exynos_sz img_sz = *sz; 643 u32 cfg; 644 645 DRM_DEBUG_KMS("swap[%d]hsize[%d]vsize[%d]\n", 646 swap, sz->hsize, sz->vsize); 647 648 /* original size */ 649 cfg = (EXYNOS_ORGISIZE_HORIZONTAL(img_sz.hsize) | 650 EXYNOS_ORGISIZE_VERTICAL(img_sz.vsize)); 651 652 fimc_write(cfg, EXYNOS_ORGISIZE); 653 654 DRM_DEBUG_KMS("x[%d]y[%d]w[%d]h[%d]\n", pos->x, pos->y, pos->w, pos->h); 655 656 if (swap) { 657 img_pos.w = pos->h; 658 img_pos.h = pos->w; 659 img_sz.hsize = sz->vsize; 660 img_sz.vsize = sz->hsize; 661 } 662 663 /* set input DMA image size */ 664 cfg = fimc_read(EXYNOS_CIREAL_ISIZE); 665 cfg &= ~(EXYNOS_CIREAL_ISIZE_HEIGHT_MASK | 666 EXYNOS_CIREAL_ISIZE_WIDTH_MASK); 667 cfg |= (EXYNOS_CIREAL_ISIZE_WIDTH(img_pos.w) | 668 EXYNOS_CIREAL_ISIZE_HEIGHT(img_pos.h)); 669 fimc_write(cfg, EXYNOS_CIREAL_ISIZE); 670 671 /* 672 * set input FIFO image size 673 * for now, we support only ITU601 8 bit mode 674 */ 675 cfg = (EXYNOS_CISRCFMT_ITU601_8BIT | 676 EXYNOS_CISRCFMT_SOURCEHSIZE(img_sz.hsize) | 677 EXYNOS_CISRCFMT_SOURCEVSIZE(img_sz.vsize)); 678 fimc_write(cfg, EXYNOS_CISRCFMT); 679 680 /* offset Y(RGB), Cb, Cr */ 681 cfg = (EXYNOS_CIIYOFF_HORIZONTAL(img_pos.x) | 682 EXYNOS_CIIYOFF_VERTICAL(img_pos.y)); 683 fimc_write(cfg, EXYNOS_CIIYOFF); 684 cfg = (EXYNOS_CIICBOFF_HORIZONTAL(img_pos.x) | 685 EXYNOS_CIICBOFF_VERTICAL(img_pos.y)); 686 fimc_write(cfg, EXYNOS_CIICBOFF); 687 cfg = (EXYNOS_CIICROFF_HORIZONTAL(img_pos.x) | 688 EXYNOS_CIICROFF_VERTICAL(img_pos.y)); 689 fimc_write(cfg, EXYNOS_CIICROFF); 690 691 return fimc_set_window(ctx, &img_pos, &img_sz); 692 } 693 694 static int fimc_src_set_addr(struct device *dev, 695 struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id, 696 enum drm_exynos_ipp_buf_type buf_type) 697 { 698 struct fimc_context *ctx = get_fimc_context(dev); 699 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 700 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node; 701 struct drm_exynos_ipp_property *property; 702 struct drm_exynos_ipp_config *config; 703 704 if (!c_node) { 705 DRM_ERROR("failed to get c_node.\n"); 706 return -EINVAL; 707 } 708 709 property = &c_node->property; 710 711 DRM_DEBUG_KMS("prop_id[%d]buf_id[%d]buf_type[%d]\n", 712 property->prop_id, buf_id, buf_type); 713 714 if (buf_id > FIMC_MAX_SRC) { 715 dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id); 716 return -ENOMEM; 717 } 718 719 /* address register set */ 720 switch (buf_type) { 721 case IPP_BUF_ENQUEUE: 722 config = &property->config[EXYNOS_DRM_OPS_SRC]; 723 fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_Y], 724 EXYNOS_CIIYSA(buf_id)); 725 726 if (config->fmt == DRM_FORMAT_YVU420) { 727 fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR], 728 EXYNOS_CIICBSA(buf_id)); 729 fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB], 730 EXYNOS_CIICRSA(buf_id)); 731 } else { 732 fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB], 733 EXYNOS_CIICBSA(buf_id)); 734 fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR], 735 EXYNOS_CIICRSA(buf_id)); 736 } 737 break; 738 case IPP_BUF_DEQUEUE: 739 fimc_write(0x0, EXYNOS_CIIYSA(buf_id)); 740 fimc_write(0x0, EXYNOS_CIICBSA(buf_id)); 741 fimc_write(0x0, EXYNOS_CIICRSA(buf_id)); 742 break; 743 default: 744 /* bypass */ 745 break; 746 } 747 748 return 0; 749 } 750 751 static struct exynos_drm_ipp_ops fimc_src_ops = { 752 .set_fmt = fimc_src_set_fmt, 753 .set_transf = fimc_src_set_transf, 754 .set_size = fimc_src_set_size, 755 .set_addr = fimc_src_set_addr, 756 }; 757 758 static int fimc_dst_set_fmt_order(struct fimc_context *ctx, u32 fmt) 759 { 760 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 761 u32 cfg; 762 763 DRM_DEBUG_KMS("fmt[0x%x]\n", fmt); 764 765 /* RGB */ 766 cfg = fimc_read(EXYNOS_CISCCTRL); 767 cfg &= ~EXYNOS_CISCCTRL_OUTRGB_FMT_RGB_MASK; 768 769 switch (fmt) { 770 case DRM_FORMAT_RGB565: 771 cfg |= EXYNOS_CISCCTRL_OUTRGB_FMT_RGB565; 772 fimc_write(cfg, EXYNOS_CISCCTRL); 773 return 0; 774 case DRM_FORMAT_RGB888: 775 cfg |= EXYNOS_CISCCTRL_OUTRGB_FMT_RGB888; 776 fimc_write(cfg, EXYNOS_CISCCTRL); 777 return 0; 778 case DRM_FORMAT_XRGB8888: 779 cfg |= (EXYNOS_CISCCTRL_OUTRGB_FMT_RGB888 | 780 EXYNOS_CISCCTRL_EXTRGB_EXTENSION); 781 fimc_write(cfg, EXYNOS_CISCCTRL); 782 break; 783 default: 784 /* bypass */ 785 break; 786 } 787 788 /* YUV */ 789 cfg = fimc_read(EXYNOS_CIOCTRL); 790 cfg &= ~(EXYNOS_CIOCTRL_ORDER2P_MASK | 791 EXYNOS_CIOCTRL_ORDER422_MASK | 792 EXYNOS_CIOCTRL_YCBCR_PLANE_MASK); 793 794 switch (fmt) { 795 case DRM_FORMAT_XRGB8888: 796 cfg |= EXYNOS_CIOCTRL_ALPHA_OUT; 797 break; 798 case DRM_FORMAT_YUYV: 799 cfg |= EXYNOS_CIOCTRL_ORDER422_YCBYCR; 800 break; 801 case DRM_FORMAT_YVYU: 802 cfg |= EXYNOS_CIOCTRL_ORDER422_YCRYCB; 803 break; 804 case DRM_FORMAT_UYVY: 805 cfg |= EXYNOS_CIOCTRL_ORDER422_CBYCRY; 806 break; 807 case DRM_FORMAT_VYUY: 808 cfg |= EXYNOS_CIOCTRL_ORDER422_CRYCBY; 809 break; 810 case DRM_FORMAT_NV21: 811 case DRM_FORMAT_NV61: 812 cfg |= EXYNOS_CIOCTRL_ORDER2P_LSB_CRCB; 813 cfg |= EXYNOS_CIOCTRL_YCBCR_2PLANE; 814 break; 815 case DRM_FORMAT_YUV422: 816 case DRM_FORMAT_YUV420: 817 case DRM_FORMAT_YVU420: 818 cfg |= EXYNOS_CIOCTRL_YCBCR_3PLANE; 819 break; 820 case DRM_FORMAT_NV12: 821 case DRM_FORMAT_NV12MT: 822 case DRM_FORMAT_NV16: 823 cfg |= EXYNOS_CIOCTRL_ORDER2P_LSB_CBCR; 824 cfg |= EXYNOS_CIOCTRL_YCBCR_2PLANE; 825 break; 826 default: 827 dev_err(ippdrv->dev, "inavlid target yuv order 0x%x.\n", fmt); 828 return -EINVAL; 829 } 830 831 fimc_write(cfg, EXYNOS_CIOCTRL); 832 833 return 0; 834 } 835 836 static int fimc_dst_set_fmt(struct device *dev, u32 fmt) 837 { 838 struct fimc_context *ctx = get_fimc_context(dev); 839 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 840 u32 cfg; 841 842 DRM_DEBUG_KMS("fmt[0x%x]\n", fmt); 843 844 cfg = fimc_read(EXYNOS_CIEXTEN); 845 846 if (fmt == DRM_FORMAT_AYUV) { 847 cfg |= EXYNOS_CIEXTEN_YUV444_OUT; 848 fimc_write(cfg, EXYNOS_CIEXTEN); 849 } else { 850 cfg &= ~EXYNOS_CIEXTEN_YUV444_OUT; 851 fimc_write(cfg, EXYNOS_CIEXTEN); 852 853 cfg = fimc_read(EXYNOS_CITRGFMT); 854 cfg &= ~EXYNOS_CITRGFMT_OUTFORMAT_MASK; 855 856 switch (fmt) { 857 case DRM_FORMAT_RGB565: 858 case DRM_FORMAT_RGB888: 859 case DRM_FORMAT_XRGB8888: 860 cfg |= EXYNOS_CITRGFMT_OUTFORMAT_RGB; 861 break; 862 case DRM_FORMAT_YUYV: 863 case DRM_FORMAT_YVYU: 864 case DRM_FORMAT_UYVY: 865 case DRM_FORMAT_VYUY: 866 cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422_1PLANE; 867 break; 868 case DRM_FORMAT_NV16: 869 case DRM_FORMAT_NV61: 870 case DRM_FORMAT_YUV422: 871 cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422; 872 break; 873 case DRM_FORMAT_YUV420: 874 case DRM_FORMAT_YVU420: 875 case DRM_FORMAT_NV12: 876 case DRM_FORMAT_NV12MT: 877 case DRM_FORMAT_NV21: 878 cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR420; 879 break; 880 default: 881 dev_err(ippdrv->dev, "inavlid target format 0x%x.\n", 882 fmt); 883 return -EINVAL; 884 } 885 886 fimc_write(cfg, EXYNOS_CITRGFMT); 887 } 888 889 cfg = fimc_read(EXYNOS_CIDMAPARAM); 890 cfg &= ~EXYNOS_CIDMAPARAM_W_MODE_MASK; 891 892 if (fmt == DRM_FORMAT_NV12MT) 893 cfg |= EXYNOS_CIDMAPARAM_W_MODE_64X32; 894 else 895 cfg |= EXYNOS_CIDMAPARAM_W_MODE_LINEAR; 896 897 fimc_write(cfg, EXYNOS_CIDMAPARAM); 898 899 return fimc_dst_set_fmt_order(ctx, fmt); 900 } 901 902 static int fimc_dst_set_transf(struct device *dev, 903 enum drm_exynos_degree degree, 904 enum drm_exynos_flip flip, bool *swap) 905 { 906 struct fimc_context *ctx = get_fimc_context(dev); 907 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 908 u32 cfg; 909 910 DRM_DEBUG_KMS("degree[%d]flip[0x%x]\n", degree, flip); 911 912 cfg = fimc_read(EXYNOS_CITRGFMT); 913 cfg &= ~EXYNOS_CITRGFMT_FLIP_MASK; 914 cfg &= ~EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE; 915 916 switch (degree) { 917 case EXYNOS_DRM_DEGREE_0: 918 if (flip & EXYNOS_DRM_FLIP_VERTICAL) 919 cfg |= EXYNOS_CITRGFMT_FLIP_X_MIRROR; 920 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) 921 cfg |= EXYNOS_CITRGFMT_FLIP_Y_MIRROR; 922 break; 923 case EXYNOS_DRM_DEGREE_90: 924 cfg |= EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE; 925 if (flip & EXYNOS_DRM_FLIP_VERTICAL) 926 cfg |= EXYNOS_CITRGFMT_FLIP_X_MIRROR; 927 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) 928 cfg |= EXYNOS_CITRGFMT_FLIP_Y_MIRROR; 929 break; 930 case EXYNOS_DRM_DEGREE_180: 931 cfg |= (EXYNOS_CITRGFMT_FLIP_X_MIRROR | 932 EXYNOS_CITRGFMT_FLIP_Y_MIRROR); 933 if (flip & EXYNOS_DRM_FLIP_VERTICAL) 934 cfg &= ~EXYNOS_CITRGFMT_FLIP_X_MIRROR; 935 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) 936 cfg &= ~EXYNOS_CITRGFMT_FLIP_Y_MIRROR; 937 break; 938 case EXYNOS_DRM_DEGREE_270: 939 cfg |= (EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE | 940 EXYNOS_CITRGFMT_FLIP_X_MIRROR | 941 EXYNOS_CITRGFMT_FLIP_Y_MIRROR); 942 if (flip & EXYNOS_DRM_FLIP_VERTICAL) 943 cfg &= ~EXYNOS_CITRGFMT_FLIP_X_MIRROR; 944 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) 945 cfg &= ~EXYNOS_CITRGFMT_FLIP_Y_MIRROR; 946 break; 947 default: 948 dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree); 949 return -EINVAL; 950 } 951 952 fimc_write(cfg, EXYNOS_CITRGFMT); 953 *swap = (cfg & EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE) ? 1 : 0; 954 955 return 0; 956 } 957 958 static int fimc_get_ratio_shift(u32 src, u32 dst, u32 *ratio, u32 *shift) 959 { 960 DRM_DEBUG_KMS("src[%d]dst[%d]\n", src, dst); 961 962 if (src >= dst * 64) { 963 DRM_ERROR("failed to make ratio and shift.\n"); 964 return -EINVAL; 965 } else if (src >= dst * 32) { 966 *ratio = 32; 967 *shift = 5; 968 } else if (src >= dst * 16) { 969 *ratio = 16; 970 *shift = 4; 971 } else if (src >= dst * 8) { 972 *ratio = 8; 973 *shift = 3; 974 } else if (src >= dst * 4) { 975 *ratio = 4; 976 *shift = 2; 977 } else if (src >= dst * 2) { 978 *ratio = 2; 979 *shift = 1; 980 } else { 981 *ratio = 1; 982 *shift = 0; 983 } 984 985 return 0; 986 } 987 988 static int fimc_set_prescaler(struct fimc_context *ctx, struct fimc_scaler *sc, 989 struct drm_exynos_pos *src, struct drm_exynos_pos *dst) 990 { 991 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 992 u32 cfg, cfg_ext, shfactor; 993 u32 pre_dst_width, pre_dst_height; 994 u32 pre_hratio, hfactor, pre_vratio, vfactor; 995 int ret = 0; 996 u32 src_w, src_h, dst_w, dst_h; 997 998 cfg_ext = fimc_read(EXYNOS_CITRGFMT); 999 if (cfg_ext & EXYNOS_CITRGFMT_INROT90_CLOCKWISE) { 1000 src_w = src->h; 1001 src_h = src->w; 1002 } else { 1003 src_w = src->w; 1004 src_h = src->h; 1005 } 1006 1007 if (cfg_ext & EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE) { 1008 dst_w = dst->h; 1009 dst_h = dst->w; 1010 } else { 1011 dst_w = dst->w; 1012 dst_h = dst->h; 1013 } 1014 1015 ret = fimc_get_ratio_shift(src_w, dst_w, &pre_hratio, &hfactor); 1016 if (ret) { 1017 dev_err(ippdrv->dev, "failed to get ratio horizontal.\n"); 1018 return ret; 1019 } 1020 1021 ret = fimc_get_ratio_shift(src_h, dst_h, &pre_vratio, &vfactor); 1022 if (ret) { 1023 dev_err(ippdrv->dev, "failed to get ratio vertical.\n"); 1024 return ret; 1025 } 1026 1027 pre_dst_width = src_w / pre_hratio; 1028 pre_dst_height = src_h / pre_vratio; 1029 DRM_DEBUG_KMS("pre_dst_width[%d]pre_dst_height[%d]\n", 1030 pre_dst_width, pre_dst_height); 1031 DRM_DEBUG_KMS("pre_hratio[%d]hfactor[%d]pre_vratio[%d]vfactor[%d]\n", 1032 pre_hratio, hfactor, pre_vratio, vfactor); 1033 1034 sc->hratio = (src_w << 14) / (dst_w << hfactor); 1035 sc->vratio = (src_h << 14) / (dst_h << vfactor); 1036 sc->up_h = (dst_w >= src_w) ? true : false; 1037 sc->up_v = (dst_h >= src_h) ? true : false; 1038 DRM_DEBUG_KMS("hratio[%d]vratio[%d]up_h[%d]up_v[%d]\n", 1039 sc->hratio, sc->vratio, sc->up_h, sc->up_v); 1040 1041 shfactor = FIMC_SHFACTOR - (hfactor + vfactor); 1042 DRM_DEBUG_KMS("shfactor[%d]\n", shfactor); 1043 1044 cfg = (EXYNOS_CISCPRERATIO_SHFACTOR(shfactor) | 1045 EXYNOS_CISCPRERATIO_PREHORRATIO(pre_hratio) | 1046 EXYNOS_CISCPRERATIO_PREVERRATIO(pre_vratio)); 1047 fimc_write(cfg, EXYNOS_CISCPRERATIO); 1048 1049 cfg = (EXYNOS_CISCPREDST_PREDSTWIDTH(pre_dst_width) | 1050 EXYNOS_CISCPREDST_PREDSTHEIGHT(pre_dst_height)); 1051 fimc_write(cfg, EXYNOS_CISCPREDST); 1052 1053 return ret; 1054 } 1055 1056 static void fimc_set_scaler(struct fimc_context *ctx, struct fimc_scaler *sc) 1057 { 1058 u32 cfg, cfg_ext; 1059 1060 DRM_DEBUG_KMS("range[%d]bypass[%d]up_h[%d]up_v[%d]\n", 1061 sc->range, sc->bypass, sc->up_h, sc->up_v); 1062 DRM_DEBUG_KMS("hratio[%d]vratio[%d]\n", 1063 sc->hratio, sc->vratio); 1064 1065 cfg = fimc_read(EXYNOS_CISCCTRL); 1066 cfg &= ~(EXYNOS_CISCCTRL_SCALERBYPASS | 1067 EXYNOS_CISCCTRL_SCALEUP_H | EXYNOS_CISCCTRL_SCALEUP_V | 1068 EXYNOS_CISCCTRL_MAIN_V_RATIO_MASK | 1069 EXYNOS_CISCCTRL_MAIN_H_RATIO_MASK | 1070 EXYNOS_CISCCTRL_CSCR2Y_WIDE | 1071 EXYNOS_CISCCTRL_CSCY2R_WIDE); 1072 1073 if (sc->range) 1074 cfg |= (EXYNOS_CISCCTRL_CSCR2Y_WIDE | 1075 EXYNOS_CISCCTRL_CSCY2R_WIDE); 1076 if (sc->bypass) 1077 cfg |= EXYNOS_CISCCTRL_SCALERBYPASS; 1078 if (sc->up_h) 1079 cfg |= EXYNOS_CISCCTRL_SCALEUP_H; 1080 if (sc->up_v) 1081 cfg |= EXYNOS_CISCCTRL_SCALEUP_V; 1082 1083 cfg |= (EXYNOS_CISCCTRL_MAINHORRATIO((sc->hratio >> 6)) | 1084 EXYNOS_CISCCTRL_MAINVERRATIO((sc->vratio >> 6))); 1085 fimc_write(cfg, EXYNOS_CISCCTRL); 1086 1087 cfg_ext = fimc_read(EXYNOS_CIEXTEN); 1088 cfg_ext &= ~EXYNOS_CIEXTEN_MAINHORRATIO_EXT_MASK; 1089 cfg_ext &= ~EXYNOS_CIEXTEN_MAINVERRATIO_EXT_MASK; 1090 cfg_ext |= (EXYNOS_CIEXTEN_MAINHORRATIO_EXT(sc->hratio) | 1091 EXYNOS_CIEXTEN_MAINVERRATIO_EXT(sc->vratio)); 1092 fimc_write(cfg_ext, EXYNOS_CIEXTEN); 1093 } 1094 1095 static int fimc_dst_set_size(struct device *dev, int swap, 1096 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz) 1097 { 1098 struct fimc_context *ctx = get_fimc_context(dev); 1099 struct drm_exynos_pos img_pos = *pos; 1100 struct drm_exynos_sz img_sz = *sz; 1101 u32 cfg; 1102 1103 DRM_DEBUG_KMS("swap[%d]hsize[%d]vsize[%d]\n", 1104 swap, sz->hsize, sz->vsize); 1105 1106 /* original size */ 1107 cfg = (EXYNOS_ORGOSIZE_HORIZONTAL(img_sz.hsize) | 1108 EXYNOS_ORGOSIZE_VERTICAL(img_sz.vsize)); 1109 1110 fimc_write(cfg, EXYNOS_ORGOSIZE); 1111 1112 DRM_DEBUG_KMS("x[%d]y[%d]w[%d]h[%d]\n", pos->x, pos->y, pos->w, pos->h); 1113 1114 /* CSC ITU */ 1115 cfg = fimc_read(EXYNOS_CIGCTRL); 1116 cfg &= ~EXYNOS_CIGCTRL_CSC_MASK; 1117 1118 if (sz->hsize >= FIMC_WIDTH_ITU_709) 1119 cfg |= EXYNOS_CIGCTRL_CSC_ITU709; 1120 else 1121 cfg |= EXYNOS_CIGCTRL_CSC_ITU601; 1122 1123 fimc_write(cfg, EXYNOS_CIGCTRL); 1124 1125 if (swap) { 1126 img_pos.w = pos->h; 1127 img_pos.h = pos->w; 1128 img_sz.hsize = sz->vsize; 1129 img_sz.vsize = sz->hsize; 1130 } 1131 1132 /* target image size */ 1133 cfg = fimc_read(EXYNOS_CITRGFMT); 1134 cfg &= ~(EXYNOS_CITRGFMT_TARGETH_MASK | 1135 EXYNOS_CITRGFMT_TARGETV_MASK); 1136 cfg |= (EXYNOS_CITRGFMT_TARGETHSIZE(img_pos.w) | 1137 EXYNOS_CITRGFMT_TARGETVSIZE(img_pos.h)); 1138 fimc_write(cfg, EXYNOS_CITRGFMT); 1139 1140 /* target area */ 1141 cfg = EXYNOS_CITAREA_TARGET_AREA(img_pos.w * img_pos.h); 1142 fimc_write(cfg, EXYNOS_CITAREA); 1143 1144 /* offset Y(RGB), Cb, Cr */ 1145 cfg = (EXYNOS_CIOYOFF_HORIZONTAL(img_pos.x) | 1146 EXYNOS_CIOYOFF_VERTICAL(img_pos.y)); 1147 fimc_write(cfg, EXYNOS_CIOYOFF); 1148 cfg = (EXYNOS_CIOCBOFF_HORIZONTAL(img_pos.x) | 1149 EXYNOS_CIOCBOFF_VERTICAL(img_pos.y)); 1150 fimc_write(cfg, EXYNOS_CIOCBOFF); 1151 cfg = (EXYNOS_CIOCROFF_HORIZONTAL(img_pos.x) | 1152 EXYNOS_CIOCROFF_VERTICAL(img_pos.y)); 1153 fimc_write(cfg, EXYNOS_CIOCROFF); 1154 1155 return 0; 1156 } 1157 1158 static int fimc_dst_get_buf_seq(struct fimc_context *ctx) 1159 { 1160 u32 cfg, i, buf_num = 0; 1161 u32 mask = 0x00000001; 1162 1163 cfg = fimc_read(EXYNOS_CIFCNTSEQ); 1164 1165 for (i = 0; i < FIMC_REG_SZ; i++) 1166 if (cfg & (mask << i)) 1167 buf_num++; 1168 1169 DRM_DEBUG_KMS("buf_num[%d]\n", buf_num); 1170 1171 return buf_num; 1172 } 1173 1174 static int fimc_dst_set_buf_seq(struct fimc_context *ctx, u32 buf_id, 1175 enum drm_exynos_ipp_buf_type buf_type) 1176 { 1177 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 1178 bool enable; 1179 u32 cfg; 1180 u32 mask = 0x00000001 << buf_id; 1181 int ret = 0; 1182 1183 DRM_DEBUG_KMS("buf_id[%d]buf_type[%d]\n", buf_id, buf_type); 1184 1185 mutex_lock(&ctx->lock); 1186 1187 /* mask register set */ 1188 cfg = fimc_read(EXYNOS_CIFCNTSEQ); 1189 1190 switch (buf_type) { 1191 case IPP_BUF_ENQUEUE: 1192 enable = true; 1193 break; 1194 case IPP_BUF_DEQUEUE: 1195 enable = false; 1196 break; 1197 default: 1198 dev_err(ippdrv->dev, "invalid buf ctrl parameter.\n"); 1199 ret = -EINVAL; 1200 goto err_unlock; 1201 } 1202 1203 /* sequence id */ 1204 cfg &= ~mask; 1205 cfg |= (enable << buf_id); 1206 fimc_write(cfg, EXYNOS_CIFCNTSEQ); 1207 1208 /* interrupt enable */ 1209 if (buf_type == IPP_BUF_ENQUEUE && 1210 fimc_dst_get_buf_seq(ctx) >= FIMC_BUF_START) 1211 fimc_handle_irq(ctx, true, false, true); 1212 1213 /* interrupt disable */ 1214 if (buf_type == IPP_BUF_DEQUEUE && 1215 fimc_dst_get_buf_seq(ctx) <= FIMC_BUF_STOP) 1216 fimc_handle_irq(ctx, false, false, true); 1217 1218 err_unlock: 1219 mutex_unlock(&ctx->lock); 1220 return ret; 1221 } 1222 1223 static int fimc_dst_set_addr(struct device *dev, 1224 struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id, 1225 enum drm_exynos_ipp_buf_type buf_type) 1226 { 1227 struct fimc_context *ctx = get_fimc_context(dev); 1228 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 1229 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node; 1230 struct drm_exynos_ipp_property *property; 1231 struct drm_exynos_ipp_config *config; 1232 1233 if (!c_node) { 1234 DRM_ERROR("failed to get c_node.\n"); 1235 return -EINVAL; 1236 } 1237 1238 property = &c_node->property; 1239 1240 DRM_DEBUG_KMS("prop_id[%d]buf_id[%d]buf_type[%d]\n", 1241 property->prop_id, buf_id, buf_type); 1242 1243 if (buf_id > FIMC_MAX_DST) { 1244 dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id); 1245 return -ENOMEM; 1246 } 1247 1248 /* address register set */ 1249 switch (buf_type) { 1250 case IPP_BUF_ENQUEUE: 1251 config = &property->config[EXYNOS_DRM_OPS_DST]; 1252 1253 fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_Y], 1254 EXYNOS_CIOYSA(buf_id)); 1255 1256 if (config->fmt == DRM_FORMAT_YVU420) { 1257 fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR], 1258 EXYNOS_CIOCBSA(buf_id)); 1259 fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB], 1260 EXYNOS_CIOCRSA(buf_id)); 1261 } else { 1262 fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB], 1263 EXYNOS_CIOCBSA(buf_id)); 1264 fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR], 1265 EXYNOS_CIOCRSA(buf_id)); 1266 } 1267 break; 1268 case IPP_BUF_DEQUEUE: 1269 fimc_write(0x0, EXYNOS_CIOYSA(buf_id)); 1270 fimc_write(0x0, EXYNOS_CIOCBSA(buf_id)); 1271 fimc_write(0x0, EXYNOS_CIOCRSA(buf_id)); 1272 break; 1273 default: 1274 /* bypass */ 1275 break; 1276 } 1277 1278 return fimc_dst_set_buf_seq(ctx, buf_id, buf_type); 1279 } 1280 1281 static struct exynos_drm_ipp_ops fimc_dst_ops = { 1282 .set_fmt = fimc_dst_set_fmt, 1283 .set_transf = fimc_dst_set_transf, 1284 .set_size = fimc_dst_set_size, 1285 .set_addr = fimc_dst_set_addr, 1286 }; 1287 1288 static int fimc_clk_ctrl(struct fimc_context *ctx, bool enable) 1289 { 1290 DRM_DEBUG_KMS("enable[%d]\n", enable); 1291 1292 if (enable) { 1293 clk_prepare_enable(ctx->clocks[FIMC_CLK_GATE]); 1294 clk_prepare_enable(ctx->clocks[FIMC_CLK_WB_A]); 1295 ctx->suspended = false; 1296 } else { 1297 clk_disable_unprepare(ctx->clocks[FIMC_CLK_GATE]); 1298 clk_disable_unprepare(ctx->clocks[FIMC_CLK_WB_A]); 1299 ctx->suspended = true; 1300 } 1301 1302 return 0; 1303 } 1304 1305 static irqreturn_t fimc_irq_handler(int irq, void *dev_id) 1306 { 1307 struct fimc_context *ctx = dev_id; 1308 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 1309 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node; 1310 struct drm_exynos_ipp_event_work *event_work = 1311 c_node->event_work; 1312 int buf_id; 1313 1314 DRM_DEBUG_KMS("fimc id[%d]\n", ctx->id); 1315 1316 fimc_clear_irq(ctx); 1317 if (fimc_check_ovf(ctx)) 1318 return IRQ_NONE; 1319 1320 if (!fimc_check_frame_end(ctx)) 1321 return IRQ_NONE; 1322 1323 buf_id = fimc_get_buf_id(ctx); 1324 if (buf_id < 0) 1325 return IRQ_HANDLED; 1326 1327 DRM_DEBUG_KMS("buf_id[%d]\n", buf_id); 1328 1329 if (fimc_dst_set_buf_seq(ctx, buf_id, IPP_BUF_DEQUEUE) < 0) { 1330 DRM_ERROR("failed to dequeue.\n"); 1331 return IRQ_HANDLED; 1332 } 1333 1334 event_work->ippdrv = ippdrv; 1335 event_work->buf_id[EXYNOS_DRM_OPS_DST] = buf_id; 1336 queue_work(ippdrv->event_workq, (struct work_struct *)event_work); 1337 1338 return IRQ_HANDLED; 1339 } 1340 1341 static int fimc_init_prop_list(struct exynos_drm_ippdrv *ippdrv) 1342 { 1343 struct drm_exynos_ipp_prop_list *prop_list; 1344 1345 prop_list = devm_kzalloc(ippdrv->dev, sizeof(*prop_list), GFP_KERNEL); 1346 if (!prop_list) { 1347 DRM_ERROR("failed to alloc property list.\n"); 1348 return -ENOMEM; 1349 } 1350 1351 prop_list->version = 1; 1352 prop_list->writeback = 1; 1353 prop_list->refresh_min = FIMC_REFRESH_MIN; 1354 prop_list->refresh_max = FIMC_REFRESH_MAX; 1355 prop_list->flip = (1 << EXYNOS_DRM_FLIP_NONE) | 1356 (1 << EXYNOS_DRM_FLIP_VERTICAL) | 1357 (1 << EXYNOS_DRM_FLIP_HORIZONTAL); 1358 prop_list->degree = (1 << EXYNOS_DRM_DEGREE_0) | 1359 (1 << EXYNOS_DRM_DEGREE_90) | 1360 (1 << EXYNOS_DRM_DEGREE_180) | 1361 (1 << EXYNOS_DRM_DEGREE_270); 1362 prop_list->csc = 1; 1363 prop_list->crop = 1; 1364 prop_list->crop_max.hsize = FIMC_CROP_MAX; 1365 prop_list->crop_max.vsize = FIMC_CROP_MAX; 1366 prop_list->crop_min.hsize = FIMC_CROP_MIN; 1367 prop_list->crop_min.vsize = FIMC_CROP_MIN; 1368 prop_list->scale = 1; 1369 prop_list->scale_max.hsize = FIMC_SCALE_MAX; 1370 prop_list->scale_max.vsize = FIMC_SCALE_MAX; 1371 prop_list->scale_min.hsize = FIMC_SCALE_MIN; 1372 prop_list->scale_min.vsize = FIMC_SCALE_MIN; 1373 1374 ippdrv->prop_list = prop_list; 1375 1376 return 0; 1377 } 1378 1379 static inline bool fimc_check_drm_flip(enum drm_exynos_flip flip) 1380 { 1381 switch (flip) { 1382 case EXYNOS_DRM_FLIP_NONE: 1383 case EXYNOS_DRM_FLIP_VERTICAL: 1384 case EXYNOS_DRM_FLIP_HORIZONTAL: 1385 case EXYNOS_DRM_FLIP_BOTH: 1386 return true; 1387 default: 1388 DRM_DEBUG_KMS("invalid flip\n"); 1389 return false; 1390 } 1391 } 1392 1393 static int fimc_ippdrv_check_property(struct device *dev, 1394 struct drm_exynos_ipp_property *property) 1395 { 1396 struct fimc_context *ctx = get_fimc_context(dev); 1397 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 1398 struct drm_exynos_ipp_prop_list *pp = ippdrv->prop_list; 1399 struct drm_exynos_ipp_config *config; 1400 struct drm_exynos_pos *pos; 1401 struct drm_exynos_sz *sz; 1402 bool swap; 1403 int i; 1404 1405 for_each_ipp_ops(i) { 1406 if ((i == EXYNOS_DRM_OPS_SRC) && 1407 (property->cmd == IPP_CMD_WB)) 1408 continue; 1409 1410 config = &property->config[i]; 1411 pos = &config->pos; 1412 sz = &config->sz; 1413 1414 /* check for flip */ 1415 if (!fimc_check_drm_flip(config->flip)) { 1416 DRM_ERROR("invalid flip.\n"); 1417 goto err_property; 1418 } 1419 1420 /* check for degree */ 1421 switch (config->degree) { 1422 case EXYNOS_DRM_DEGREE_90: 1423 case EXYNOS_DRM_DEGREE_270: 1424 swap = true; 1425 break; 1426 case EXYNOS_DRM_DEGREE_0: 1427 case EXYNOS_DRM_DEGREE_180: 1428 swap = false; 1429 break; 1430 default: 1431 DRM_ERROR("invalid degree.\n"); 1432 goto err_property; 1433 } 1434 1435 /* check for buffer bound */ 1436 if ((pos->x + pos->w > sz->hsize) || 1437 (pos->y + pos->h > sz->vsize)) { 1438 DRM_ERROR("out of buf bound.\n"); 1439 goto err_property; 1440 } 1441 1442 /* check for crop */ 1443 if ((i == EXYNOS_DRM_OPS_SRC) && (pp->crop)) { 1444 if (swap) { 1445 if ((pos->h < pp->crop_min.hsize) || 1446 (sz->vsize > pp->crop_max.hsize) || 1447 (pos->w < pp->crop_min.vsize) || 1448 (sz->hsize > pp->crop_max.vsize)) { 1449 DRM_ERROR("out of crop size.\n"); 1450 goto err_property; 1451 } 1452 } else { 1453 if ((pos->w < pp->crop_min.hsize) || 1454 (sz->hsize > pp->crop_max.hsize) || 1455 (pos->h < pp->crop_min.vsize) || 1456 (sz->vsize > pp->crop_max.vsize)) { 1457 DRM_ERROR("out of crop size.\n"); 1458 goto err_property; 1459 } 1460 } 1461 } 1462 1463 /* check for scale */ 1464 if ((i == EXYNOS_DRM_OPS_DST) && (pp->scale)) { 1465 if (swap) { 1466 if ((pos->h < pp->scale_min.hsize) || 1467 (sz->vsize > pp->scale_max.hsize) || 1468 (pos->w < pp->scale_min.vsize) || 1469 (sz->hsize > pp->scale_max.vsize)) { 1470 DRM_ERROR("out of scale size.\n"); 1471 goto err_property; 1472 } 1473 } else { 1474 if ((pos->w < pp->scale_min.hsize) || 1475 (sz->hsize > pp->scale_max.hsize) || 1476 (pos->h < pp->scale_min.vsize) || 1477 (sz->vsize > pp->scale_max.vsize)) { 1478 DRM_ERROR("out of scale size.\n"); 1479 goto err_property; 1480 } 1481 } 1482 } 1483 } 1484 1485 return 0; 1486 1487 err_property: 1488 for_each_ipp_ops(i) { 1489 if ((i == EXYNOS_DRM_OPS_SRC) && 1490 (property->cmd == IPP_CMD_WB)) 1491 continue; 1492 1493 config = &property->config[i]; 1494 pos = &config->pos; 1495 sz = &config->sz; 1496 1497 DRM_ERROR("[%s]f[%d]r[%d]pos[%d %d %d %d]sz[%d %d]\n", 1498 i ? "dst" : "src", config->flip, config->degree, 1499 pos->x, pos->y, pos->w, pos->h, 1500 sz->hsize, sz->vsize); 1501 } 1502 1503 return -EINVAL; 1504 } 1505 1506 static void fimc_clear_addr(struct fimc_context *ctx) 1507 { 1508 int i; 1509 1510 for (i = 0; i < FIMC_MAX_SRC; i++) { 1511 fimc_write(0, EXYNOS_CIIYSA(i)); 1512 fimc_write(0, EXYNOS_CIICBSA(i)); 1513 fimc_write(0, EXYNOS_CIICRSA(i)); 1514 } 1515 1516 for (i = 0; i < FIMC_MAX_DST; i++) { 1517 fimc_write(0, EXYNOS_CIOYSA(i)); 1518 fimc_write(0, EXYNOS_CIOCBSA(i)); 1519 fimc_write(0, EXYNOS_CIOCRSA(i)); 1520 } 1521 } 1522 1523 static int fimc_ippdrv_reset(struct device *dev) 1524 { 1525 struct fimc_context *ctx = get_fimc_context(dev); 1526 1527 /* reset h/w block */ 1528 fimc_sw_reset(ctx); 1529 1530 /* reset scaler capability */ 1531 memset(&ctx->sc, 0x0, sizeof(ctx->sc)); 1532 1533 fimc_clear_addr(ctx); 1534 1535 return 0; 1536 } 1537 1538 static int fimc_ippdrv_start(struct device *dev, enum drm_exynos_ipp_cmd cmd) 1539 { 1540 struct fimc_context *ctx = get_fimc_context(dev); 1541 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 1542 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node; 1543 struct drm_exynos_ipp_property *property; 1544 struct drm_exynos_ipp_config *config; 1545 struct drm_exynos_pos img_pos[EXYNOS_DRM_OPS_MAX]; 1546 struct drm_exynos_ipp_set_wb set_wb; 1547 int ret, i; 1548 u32 cfg0, cfg1; 1549 1550 DRM_DEBUG_KMS("cmd[%d]\n", cmd); 1551 1552 if (!c_node) { 1553 DRM_ERROR("failed to get c_node.\n"); 1554 return -EINVAL; 1555 } 1556 1557 property = &c_node->property; 1558 1559 fimc_handle_irq(ctx, true, false, true); 1560 1561 for_each_ipp_ops(i) { 1562 config = &property->config[i]; 1563 img_pos[i] = config->pos; 1564 } 1565 1566 ret = fimc_set_prescaler(ctx, &ctx->sc, 1567 &img_pos[EXYNOS_DRM_OPS_SRC], 1568 &img_pos[EXYNOS_DRM_OPS_DST]); 1569 if (ret) { 1570 dev_err(dev, "failed to set precalser.\n"); 1571 return ret; 1572 } 1573 1574 /* If set ture, we can save jpeg about screen */ 1575 fimc_handle_jpeg(ctx, false); 1576 fimc_set_scaler(ctx, &ctx->sc); 1577 fimc_set_polarity(ctx, &ctx->pol); 1578 1579 switch (cmd) { 1580 case IPP_CMD_M2M: 1581 fimc_set_type_ctrl(ctx, FIMC_WB_NONE); 1582 fimc_handle_lastend(ctx, false); 1583 1584 /* setup dma */ 1585 cfg0 = fimc_read(EXYNOS_MSCTRL); 1586 cfg0 &= ~EXYNOS_MSCTRL_INPUT_MASK; 1587 cfg0 |= EXYNOS_MSCTRL_INPUT_MEMORY; 1588 fimc_write(cfg0, EXYNOS_MSCTRL); 1589 break; 1590 case IPP_CMD_WB: 1591 fimc_set_type_ctrl(ctx, FIMC_WB_A); 1592 fimc_handle_lastend(ctx, true); 1593 1594 /* setup FIMD */ 1595 ret = fimc_set_camblk_fimd0_wb(ctx); 1596 if (ret < 0) { 1597 dev_err(dev, "camblk setup failed.\n"); 1598 return ret; 1599 } 1600 1601 set_wb.enable = 1; 1602 set_wb.refresh = property->refresh_rate; 1603 exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb); 1604 break; 1605 case IPP_CMD_OUTPUT: 1606 default: 1607 ret = -EINVAL; 1608 dev_err(dev, "invalid operations.\n"); 1609 return ret; 1610 } 1611 1612 /* Reset status */ 1613 fimc_write(0x0, EXYNOS_CISTATUS); 1614 1615 cfg0 = fimc_read(EXYNOS_CIIMGCPT); 1616 cfg0 &= ~EXYNOS_CIIMGCPT_IMGCPTEN_SC; 1617 cfg0 |= EXYNOS_CIIMGCPT_IMGCPTEN_SC; 1618 1619 /* Scaler */ 1620 cfg1 = fimc_read(EXYNOS_CISCCTRL); 1621 cfg1 &= ~EXYNOS_CISCCTRL_SCAN_MASK; 1622 cfg1 |= (EXYNOS_CISCCTRL_PROGRESSIVE | 1623 EXYNOS_CISCCTRL_SCALERSTART); 1624 1625 fimc_write(cfg1, EXYNOS_CISCCTRL); 1626 1627 /* Enable image capture*/ 1628 cfg0 |= EXYNOS_CIIMGCPT_IMGCPTEN; 1629 fimc_write(cfg0, EXYNOS_CIIMGCPT); 1630 1631 /* Disable frame end irq */ 1632 cfg0 = fimc_read(EXYNOS_CIGCTRL); 1633 cfg0 &= ~EXYNOS_CIGCTRL_IRQ_END_DISABLE; 1634 fimc_write(cfg0, EXYNOS_CIGCTRL); 1635 1636 cfg0 = fimc_read(EXYNOS_CIOCTRL); 1637 cfg0 &= ~EXYNOS_CIOCTRL_WEAVE_MASK; 1638 fimc_write(cfg0, EXYNOS_CIOCTRL); 1639 1640 if (cmd == IPP_CMD_M2M) { 1641 cfg0 = fimc_read(EXYNOS_MSCTRL); 1642 cfg0 |= EXYNOS_MSCTRL_ENVID; 1643 fimc_write(cfg0, EXYNOS_MSCTRL); 1644 1645 cfg0 = fimc_read(EXYNOS_MSCTRL); 1646 cfg0 |= EXYNOS_MSCTRL_ENVID; 1647 fimc_write(cfg0, EXYNOS_MSCTRL); 1648 } 1649 1650 return 0; 1651 } 1652 1653 static void fimc_ippdrv_stop(struct device *dev, enum drm_exynos_ipp_cmd cmd) 1654 { 1655 struct fimc_context *ctx = get_fimc_context(dev); 1656 struct drm_exynos_ipp_set_wb set_wb = {0, 0}; 1657 u32 cfg; 1658 1659 DRM_DEBUG_KMS("cmd[%d]\n", cmd); 1660 1661 switch (cmd) { 1662 case IPP_CMD_M2M: 1663 /* Source clear */ 1664 cfg = fimc_read(EXYNOS_MSCTRL); 1665 cfg &= ~EXYNOS_MSCTRL_INPUT_MASK; 1666 cfg &= ~EXYNOS_MSCTRL_ENVID; 1667 fimc_write(cfg, EXYNOS_MSCTRL); 1668 break; 1669 case IPP_CMD_WB: 1670 exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb); 1671 break; 1672 case IPP_CMD_OUTPUT: 1673 default: 1674 dev_err(dev, "invalid operations.\n"); 1675 break; 1676 } 1677 1678 fimc_handle_irq(ctx, false, false, true); 1679 1680 /* reset sequence */ 1681 fimc_write(0x0, EXYNOS_CIFCNTSEQ); 1682 1683 /* Scaler disable */ 1684 cfg = fimc_read(EXYNOS_CISCCTRL); 1685 cfg &= ~EXYNOS_CISCCTRL_SCALERSTART; 1686 fimc_write(cfg, EXYNOS_CISCCTRL); 1687 1688 /* Disable image capture */ 1689 cfg = fimc_read(EXYNOS_CIIMGCPT); 1690 cfg &= ~(EXYNOS_CIIMGCPT_IMGCPTEN_SC | EXYNOS_CIIMGCPT_IMGCPTEN); 1691 fimc_write(cfg, EXYNOS_CIIMGCPT); 1692 1693 /* Enable frame end irq */ 1694 cfg = fimc_read(EXYNOS_CIGCTRL); 1695 cfg |= EXYNOS_CIGCTRL_IRQ_END_DISABLE; 1696 fimc_write(cfg, EXYNOS_CIGCTRL); 1697 } 1698 1699 static void fimc_put_clocks(struct fimc_context *ctx) 1700 { 1701 int i; 1702 1703 for (i = 0; i < FIMC_CLKS_MAX; i++) { 1704 if (IS_ERR(ctx->clocks[i])) 1705 continue; 1706 clk_put(ctx->clocks[i]); 1707 ctx->clocks[i] = ERR_PTR(-EINVAL); 1708 } 1709 } 1710 1711 static int fimc_setup_clocks(struct fimc_context *ctx) 1712 { 1713 struct device *fimc_dev = ctx->ippdrv.dev; 1714 struct device *dev; 1715 int ret, i; 1716 1717 for (i = 0; i < FIMC_CLKS_MAX; i++) 1718 ctx->clocks[i] = ERR_PTR(-EINVAL); 1719 1720 for (i = 0; i < FIMC_CLKS_MAX; i++) { 1721 if (i == FIMC_CLK_WB_A || i == FIMC_CLK_WB_B) 1722 dev = fimc_dev->parent; 1723 else 1724 dev = fimc_dev; 1725 1726 ctx->clocks[i] = clk_get(dev, fimc_clock_names[i]); 1727 if (IS_ERR(ctx->clocks[i])) { 1728 if (i >= FIMC_CLK_MUX) 1729 break; 1730 ret = PTR_ERR(ctx->clocks[i]); 1731 dev_err(fimc_dev, "failed to get clock: %s\n", 1732 fimc_clock_names[i]); 1733 goto e_clk_free; 1734 } 1735 } 1736 1737 /* Optional FIMC LCLK parent clock setting */ 1738 if (!IS_ERR(ctx->clocks[FIMC_CLK_PARENT])) { 1739 ret = clk_set_parent(ctx->clocks[FIMC_CLK_MUX], 1740 ctx->clocks[FIMC_CLK_PARENT]); 1741 if (ret < 0) { 1742 dev_err(fimc_dev, "failed to set parent.\n"); 1743 goto e_clk_free; 1744 } 1745 } 1746 1747 ret = clk_set_rate(ctx->clocks[FIMC_CLK_LCLK], ctx->clk_frequency); 1748 if (ret < 0) 1749 goto e_clk_free; 1750 1751 ret = clk_prepare_enable(ctx->clocks[FIMC_CLK_LCLK]); 1752 if (!ret) 1753 return ret; 1754 e_clk_free: 1755 fimc_put_clocks(ctx); 1756 return ret; 1757 } 1758 1759 static int fimc_parse_dt(struct fimc_context *ctx) 1760 { 1761 struct device_node *node = ctx->ippdrv.dev->of_node; 1762 1763 /* Handle only devices that support the LCD Writeback data path */ 1764 if (!of_property_read_bool(node, "samsung,lcd-wb")) 1765 return -ENODEV; 1766 1767 if (of_property_read_u32(node, "clock-frequency", 1768 &ctx->clk_frequency)) 1769 ctx->clk_frequency = FIMC_DEFAULT_LCLK_FREQUENCY; 1770 1771 ctx->id = of_alias_get_id(node, "fimc"); 1772 1773 if (ctx->id < 0) { 1774 dev_err(ctx->ippdrv.dev, "failed to get node alias id.\n"); 1775 return -EINVAL; 1776 } 1777 1778 return 0; 1779 } 1780 1781 static int fimc_probe(struct platform_device *pdev) 1782 { 1783 struct device *dev = &pdev->dev; 1784 struct fimc_context *ctx; 1785 struct resource *res; 1786 struct exynos_drm_ippdrv *ippdrv; 1787 int ret; 1788 1789 if (!dev->of_node) { 1790 dev_err(dev, "device tree node not found.\n"); 1791 return -ENODEV; 1792 } 1793 1794 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 1795 if (!ctx) 1796 return -ENOMEM; 1797 1798 ctx->ippdrv.dev = dev; 1799 1800 ret = fimc_parse_dt(ctx); 1801 if (ret < 0) 1802 return ret; 1803 1804 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node, 1805 "samsung,sysreg"); 1806 if (IS_ERR(ctx->sysreg)) { 1807 dev_err(dev, "syscon regmap lookup failed.\n"); 1808 return PTR_ERR(ctx->sysreg); 1809 } 1810 1811 /* resource memory */ 1812 ctx->regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1813 ctx->regs = devm_ioremap_resource(dev, ctx->regs_res); 1814 if (IS_ERR(ctx->regs)) 1815 return PTR_ERR(ctx->regs); 1816 1817 /* resource irq */ 1818 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1819 if (!res) { 1820 dev_err(dev, "failed to request irq resource.\n"); 1821 return -ENOENT; 1822 } 1823 1824 ctx->irq = res->start; 1825 ret = devm_request_threaded_irq(dev, ctx->irq, NULL, fimc_irq_handler, 1826 IRQF_ONESHOT, "drm_fimc", ctx); 1827 if (ret < 0) { 1828 dev_err(dev, "failed to request irq.\n"); 1829 return ret; 1830 } 1831 1832 ret = fimc_setup_clocks(ctx); 1833 if (ret < 0) 1834 return ret; 1835 1836 ippdrv = &ctx->ippdrv; 1837 ippdrv->ops[EXYNOS_DRM_OPS_SRC] = &fimc_src_ops; 1838 ippdrv->ops[EXYNOS_DRM_OPS_DST] = &fimc_dst_ops; 1839 ippdrv->check_property = fimc_ippdrv_check_property; 1840 ippdrv->reset = fimc_ippdrv_reset; 1841 ippdrv->start = fimc_ippdrv_start; 1842 ippdrv->stop = fimc_ippdrv_stop; 1843 ret = fimc_init_prop_list(ippdrv); 1844 if (ret < 0) { 1845 dev_err(dev, "failed to init property list.\n"); 1846 goto err_put_clk; 1847 } 1848 1849 DRM_DEBUG_KMS("id[%d]ippdrv[0x%x]\n", ctx->id, (int)ippdrv); 1850 1851 mutex_init(&ctx->lock); 1852 platform_set_drvdata(pdev, ctx); 1853 1854 pm_runtime_set_active(dev); 1855 pm_runtime_enable(dev); 1856 1857 ret = exynos_drm_ippdrv_register(ippdrv); 1858 if (ret < 0) { 1859 dev_err(dev, "failed to register drm fimc device.\n"); 1860 goto err_pm_dis; 1861 } 1862 1863 dev_info(dev, "drm fimc registered successfully.\n"); 1864 1865 return 0; 1866 1867 err_pm_dis: 1868 pm_runtime_disable(dev); 1869 err_put_clk: 1870 fimc_put_clocks(ctx); 1871 1872 return ret; 1873 } 1874 1875 static int fimc_remove(struct platform_device *pdev) 1876 { 1877 struct device *dev = &pdev->dev; 1878 struct fimc_context *ctx = get_fimc_context(dev); 1879 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 1880 1881 exynos_drm_ippdrv_unregister(ippdrv); 1882 mutex_destroy(&ctx->lock); 1883 1884 fimc_put_clocks(ctx); 1885 pm_runtime_set_suspended(dev); 1886 pm_runtime_disable(dev); 1887 1888 return 0; 1889 } 1890 1891 #ifdef CONFIG_PM_SLEEP 1892 static int fimc_suspend(struct device *dev) 1893 { 1894 struct fimc_context *ctx = get_fimc_context(dev); 1895 1896 DRM_DEBUG_KMS("id[%d]\n", ctx->id); 1897 1898 if (pm_runtime_suspended(dev)) 1899 return 0; 1900 1901 return fimc_clk_ctrl(ctx, false); 1902 } 1903 1904 static int fimc_resume(struct device *dev) 1905 { 1906 struct fimc_context *ctx = get_fimc_context(dev); 1907 1908 DRM_DEBUG_KMS("id[%d]\n", ctx->id); 1909 1910 if (!pm_runtime_suspended(dev)) 1911 return fimc_clk_ctrl(ctx, true); 1912 1913 return 0; 1914 } 1915 #endif 1916 1917 #ifdef CONFIG_PM_RUNTIME 1918 static int fimc_runtime_suspend(struct device *dev) 1919 { 1920 struct fimc_context *ctx = get_fimc_context(dev); 1921 1922 DRM_DEBUG_KMS("id[%d]\n", ctx->id); 1923 1924 return fimc_clk_ctrl(ctx, false); 1925 } 1926 1927 static int fimc_runtime_resume(struct device *dev) 1928 { 1929 struct fimc_context *ctx = get_fimc_context(dev); 1930 1931 DRM_DEBUG_KMS("id[%d]\n", ctx->id); 1932 1933 return fimc_clk_ctrl(ctx, true); 1934 } 1935 #endif 1936 1937 static const struct dev_pm_ops fimc_pm_ops = { 1938 SET_SYSTEM_SLEEP_PM_OPS(fimc_suspend, fimc_resume) 1939 SET_RUNTIME_PM_OPS(fimc_runtime_suspend, fimc_runtime_resume, NULL) 1940 }; 1941 1942 static const struct of_device_id fimc_of_match[] = { 1943 { .compatible = "samsung,exynos4210-fimc" }, 1944 { .compatible = "samsung,exynos4212-fimc" }, 1945 { }, 1946 }; 1947 1948 struct platform_driver fimc_driver = { 1949 .probe = fimc_probe, 1950 .remove = fimc_remove, 1951 .driver = { 1952 .of_match_table = fimc_of_match, 1953 .name = "exynos-drm-fimc", 1954 .owner = THIS_MODULE, 1955 .pm = &fimc_pm_ops, 1956 }, 1957 }; 1958 1959