1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Samsung SoC MIPI DSI Master driver. 4 * 5 * Copyright (c) 2014 Samsung Electronics Co., Ltd 6 * 7 * Contacts: Tomasz Figa <t.figa@samsung.com> 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/component.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/irq.h> 15 #include <linux/of_device.h> 16 #include <linux/of_graph.h> 17 #include <linux/phy/phy.h> 18 #include <linux/regulator/consumer.h> 19 20 #include <asm/unaligned.h> 21 22 #include <video/mipi_display.h> 23 #include <video/videomode.h> 24 25 #include <drm/drm_atomic_helper.h> 26 #include <drm/drm_bridge.h> 27 #include <drm/drm_mipi_dsi.h> 28 #include <drm/drm_panel.h> 29 #include <drm/drm_print.h> 30 #include <drm/drm_probe_helper.h> 31 #include <drm/drm_simple_kms_helper.h> 32 33 #include "exynos_drm_crtc.h" 34 #include "exynos_drm_drv.h" 35 36 /* returns true iff both arguments logically differs */ 37 #define NEQV(a, b) (!(a) ^ !(b)) 38 39 /* DSIM_STATUS */ 40 #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0) 41 #define DSIM_STOP_STATE_CLK (1 << 8) 42 #define DSIM_TX_READY_HS_CLK (1 << 10) 43 #define DSIM_PLL_STABLE (1 << 31) 44 45 /* DSIM_SWRST */ 46 #define DSIM_FUNCRST (1 << 16) 47 #define DSIM_SWRST (1 << 0) 48 49 /* DSIM_TIMEOUT */ 50 #define DSIM_LPDR_TIMEOUT(x) ((x) << 0) 51 #define DSIM_BTA_TIMEOUT(x) ((x) << 16) 52 53 /* DSIM_CLKCTRL */ 54 #define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << 0) 55 #define DSIM_ESC_PRESCALER_MASK (0xffff << 0) 56 #define DSIM_LANE_ESC_CLK_EN_CLK (1 << 19) 57 #define DSIM_LANE_ESC_CLK_EN_DATA(x) (((x) & 0xf) << 20) 58 #define DSIM_LANE_ESC_CLK_EN_DATA_MASK (0xf << 20) 59 #define DSIM_BYTE_CLKEN (1 << 24) 60 #define DSIM_BYTE_CLK_SRC(x) (((x) & 0x3) << 25) 61 #define DSIM_BYTE_CLK_SRC_MASK (0x3 << 25) 62 #define DSIM_PLL_BYPASS (1 << 27) 63 #define DSIM_ESC_CLKEN (1 << 28) 64 #define DSIM_TX_REQUEST_HSCLK (1 << 31) 65 66 /* DSIM_CONFIG */ 67 #define DSIM_LANE_EN_CLK (1 << 0) 68 #define DSIM_LANE_EN(x) (((x) & 0xf) << 1) 69 #define DSIM_NUM_OF_DATA_LANE(x) (((x) & 0x3) << 5) 70 #define DSIM_SUB_PIX_FORMAT(x) (((x) & 0x7) << 8) 71 #define DSIM_MAIN_PIX_FORMAT_MASK (0x7 << 12) 72 #define DSIM_MAIN_PIX_FORMAT_RGB888 (0x7 << 12) 73 #define DSIM_MAIN_PIX_FORMAT_RGB666 (0x6 << 12) 74 #define DSIM_MAIN_PIX_FORMAT_RGB666_P (0x5 << 12) 75 #define DSIM_MAIN_PIX_FORMAT_RGB565 (0x4 << 12) 76 #define DSIM_SUB_VC (((x) & 0x3) << 16) 77 #define DSIM_MAIN_VC (((x) & 0x3) << 18) 78 #define DSIM_HSA_MODE (1 << 20) 79 #define DSIM_HBP_MODE (1 << 21) 80 #define DSIM_HFP_MODE (1 << 22) 81 #define DSIM_HSE_MODE (1 << 23) 82 #define DSIM_AUTO_MODE (1 << 24) 83 #define DSIM_VIDEO_MODE (1 << 25) 84 #define DSIM_BURST_MODE (1 << 26) 85 #define DSIM_SYNC_INFORM (1 << 27) 86 #define DSIM_EOT_DISABLE (1 << 28) 87 #define DSIM_MFLUSH_VS (1 << 29) 88 /* This flag is valid only for exynos3250/3472/5260/5430 */ 89 #define DSIM_CLKLANE_STOP (1 << 30) 90 91 /* DSIM_ESCMODE */ 92 #define DSIM_TX_TRIGGER_RST (1 << 4) 93 #define DSIM_TX_LPDT_LP (1 << 6) 94 #define DSIM_CMD_LPDT_LP (1 << 7) 95 #define DSIM_FORCE_BTA (1 << 16) 96 #define DSIM_FORCE_STOP_STATE (1 << 20) 97 #define DSIM_STOP_STATE_CNT(x) (((x) & 0x7ff) << 21) 98 #define DSIM_STOP_STATE_CNT_MASK (0x7ff << 21) 99 100 /* DSIM_MDRESOL */ 101 #define DSIM_MAIN_STAND_BY (1 << 31) 102 #define DSIM_MAIN_VRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 16) 103 #define DSIM_MAIN_HRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 0) 104 105 /* DSIM_MVPORCH */ 106 #define DSIM_CMD_ALLOW(x) ((x) << 28) 107 #define DSIM_STABLE_VFP(x) ((x) << 16) 108 #define DSIM_MAIN_VBP(x) ((x) << 0) 109 #define DSIM_CMD_ALLOW_MASK (0xf << 28) 110 #define DSIM_STABLE_VFP_MASK (0x7ff << 16) 111 #define DSIM_MAIN_VBP_MASK (0x7ff << 0) 112 113 /* DSIM_MHPORCH */ 114 #define DSIM_MAIN_HFP(x) ((x) << 16) 115 #define DSIM_MAIN_HBP(x) ((x) << 0) 116 #define DSIM_MAIN_HFP_MASK ((0xffff) << 16) 117 #define DSIM_MAIN_HBP_MASK ((0xffff) << 0) 118 119 /* DSIM_MSYNC */ 120 #define DSIM_MAIN_VSA(x) ((x) << 22) 121 #define DSIM_MAIN_HSA(x) ((x) << 0) 122 #define DSIM_MAIN_VSA_MASK ((0x3ff) << 22) 123 #define DSIM_MAIN_HSA_MASK ((0xffff) << 0) 124 125 /* DSIM_SDRESOL */ 126 #define DSIM_SUB_STANDY(x) ((x) << 31) 127 #define DSIM_SUB_VRESOL(x) ((x) << 16) 128 #define DSIM_SUB_HRESOL(x) ((x) << 0) 129 #define DSIM_SUB_STANDY_MASK ((0x1) << 31) 130 #define DSIM_SUB_VRESOL_MASK ((0x7ff) << 16) 131 #define DSIM_SUB_HRESOL_MASK ((0x7ff) << 0) 132 133 /* DSIM_INTSRC */ 134 #define DSIM_INT_PLL_STABLE (1 << 31) 135 #define DSIM_INT_SW_RST_RELEASE (1 << 30) 136 #define DSIM_INT_SFR_FIFO_EMPTY (1 << 29) 137 #define DSIM_INT_SFR_HDR_FIFO_EMPTY (1 << 28) 138 #define DSIM_INT_BTA (1 << 25) 139 #define DSIM_INT_FRAME_DONE (1 << 24) 140 #define DSIM_INT_RX_TIMEOUT (1 << 21) 141 #define DSIM_INT_BTA_TIMEOUT (1 << 20) 142 #define DSIM_INT_RX_DONE (1 << 18) 143 #define DSIM_INT_RX_TE (1 << 17) 144 #define DSIM_INT_RX_ACK (1 << 16) 145 #define DSIM_INT_RX_ECC_ERR (1 << 15) 146 #define DSIM_INT_RX_CRC_ERR (1 << 14) 147 148 /* DSIM_FIFOCTRL */ 149 #define DSIM_RX_DATA_FULL (1 << 25) 150 #define DSIM_RX_DATA_EMPTY (1 << 24) 151 #define DSIM_SFR_HEADER_FULL (1 << 23) 152 #define DSIM_SFR_HEADER_EMPTY (1 << 22) 153 #define DSIM_SFR_PAYLOAD_FULL (1 << 21) 154 #define DSIM_SFR_PAYLOAD_EMPTY (1 << 20) 155 #define DSIM_I80_HEADER_FULL (1 << 19) 156 #define DSIM_I80_HEADER_EMPTY (1 << 18) 157 #define DSIM_I80_PAYLOAD_FULL (1 << 17) 158 #define DSIM_I80_PAYLOAD_EMPTY (1 << 16) 159 #define DSIM_SD_HEADER_FULL (1 << 15) 160 #define DSIM_SD_HEADER_EMPTY (1 << 14) 161 #define DSIM_SD_PAYLOAD_FULL (1 << 13) 162 #define DSIM_SD_PAYLOAD_EMPTY (1 << 12) 163 #define DSIM_MD_HEADER_FULL (1 << 11) 164 #define DSIM_MD_HEADER_EMPTY (1 << 10) 165 #define DSIM_MD_PAYLOAD_FULL (1 << 9) 166 #define DSIM_MD_PAYLOAD_EMPTY (1 << 8) 167 #define DSIM_RX_FIFO (1 << 4) 168 #define DSIM_SFR_FIFO (1 << 3) 169 #define DSIM_I80_FIFO (1 << 2) 170 #define DSIM_SD_FIFO (1 << 1) 171 #define DSIM_MD_FIFO (1 << 0) 172 173 /* DSIM_PHYACCHR */ 174 #define DSIM_AFC_EN (1 << 14) 175 #define DSIM_AFC_CTL(x) (((x) & 0x7) << 5) 176 177 /* DSIM_PLLCTRL */ 178 #define DSIM_FREQ_BAND(x) ((x) << 24) 179 #define DSIM_PLL_EN (1 << 23) 180 #define DSIM_PLL_P(x) ((x) << 13) 181 #define DSIM_PLL_M(x) ((x) << 4) 182 #define DSIM_PLL_S(x) ((x) << 1) 183 184 /* DSIM_PHYCTRL */ 185 #define DSIM_PHYCTRL_ULPS_EXIT(x) (((x) & 0x1ff) << 0) 186 #define DSIM_PHYCTRL_B_DPHYCTL_VREG_LP (1 << 30) 187 #define DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP (1 << 14) 188 189 /* DSIM_PHYTIMING */ 190 #define DSIM_PHYTIMING_LPX(x) ((x) << 8) 191 #define DSIM_PHYTIMING_HS_EXIT(x) ((x) << 0) 192 193 /* DSIM_PHYTIMING1 */ 194 #define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24) 195 #define DSIM_PHYTIMING1_CLK_ZERO(x) ((x) << 16) 196 #define DSIM_PHYTIMING1_CLK_POST(x) ((x) << 8) 197 #define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) << 0) 198 199 /* DSIM_PHYTIMING2 */ 200 #define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) << 16) 201 #define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8) 202 #define DSIM_PHYTIMING2_HS_TRAIL(x) ((x) << 0) 203 204 #define DSI_MAX_BUS_WIDTH 4 205 #define DSI_NUM_VIRTUAL_CHANNELS 4 206 #define DSI_TX_FIFO_SIZE 2048 207 #define DSI_RX_FIFO_SIZE 256 208 #define DSI_XFER_TIMEOUT_MS 100 209 #define DSI_RX_FIFO_EMPTY 0x30800002 210 211 #define OLD_SCLK_MIPI_CLK_NAME "pll_clk" 212 213 static const char *const clk_names[5] = { "bus_clk", "sclk_mipi", 214 "phyclk_mipidphy0_bitclkdiv8", "phyclk_mipidphy0_rxclkesc0", 215 "sclk_rgb_vclk_to_dsim0" }; 216 217 enum exynos_dsi_transfer_type { 218 EXYNOS_DSI_TX, 219 EXYNOS_DSI_RX, 220 }; 221 222 struct exynos_dsi_transfer { 223 struct list_head list; 224 struct completion completed; 225 int result; 226 struct mipi_dsi_packet packet; 227 u16 flags; 228 u16 tx_done; 229 230 u8 *rx_payload; 231 u16 rx_len; 232 u16 rx_done; 233 }; 234 235 #define DSIM_STATE_ENABLED BIT(0) 236 #define DSIM_STATE_INITIALIZED BIT(1) 237 #define DSIM_STATE_CMD_LPM BIT(2) 238 #define DSIM_STATE_VIDOUT_AVAILABLE BIT(3) 239 240 struct exynos_dsi_driver_data { 241 const unsigned int *reg_ofs; 242 unsigned int plltmr_reg; 243 unsigned int has_freqband:1; 244 unsigned int has_clklane_stop:1; 245 unsigned int num_clks; 246 unsigned int max_freq; 247 unsigned int wait_for_reset; 248 unsigned int num_bits_resol; 249 const unsigned int *reg_values; 250 }; 251 252 struct exynos_dsi { 253 struct drm_encoder encoder; 254 struct mipi_dsi_host dsi_host; 255 struct drm_bridge bridge; 256 struct drm_bridge *out_bridge; 257 struct device *dev; 258 struct drm_display_mode mode; 259 260 void __iomem *reg_base; 261 struct phy *phy; 262 struct clk **clks; 263 struct regulator_bulk_data supplies[2]; 264 int irq; 265 struct gpio_desc *te_gpio; 266 267 u32 pll_clk_rate; 268 u32 burst_clk_rate; 269 u32 esc_clk_rate; 270 u32 lanes; 271 u32 mode_flags; 272 u32 format; 273 274 int state; 275 struct drm_property *brightness; 276 struct completion completed; 277 278 spinlock_t transfer_lock; /* protects transfer_list */ 279 struct list_head transfer_list; 280 281 const struct exynos_dsi_driver_data *driver_data; 282 }; 283 284 #define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host) 285 286 static inline struct exynos_dsi *bridge_to_dsi(struct drm_bridge *b) 287 { 288 return container_of(b, struct exynos_dsi, bridge); 289 } 290 291 enum reg_idx { 292 DSIM_STATUS_REG, /* Status register */ 293 DSIM_SWRST_REG, /* Software reset register */ 294 DSIM_CLKCTRL_REG, /* Clock control register */ 295 DSIM_TIMEOUT_REG, /* Time out register */ 296 DSIM_CONFIG_REG, /* Configuration register */ 297 DSIM_ESCMODE_REG, /* Escape mode register */ 298 DSIM_MDRESOL_REG, 299 DSIM_MVPORCH_REG, /* Main display Vporch register */ 300 DSIM_MHPORCH_REG, /* Main display Hporch register */ 301 DSIM_MSYNC_REG, /* Main display sync area register */ 302 DSIM_INTSRC_REG, /* Interrupt source register */ 303 DSIM_INTMSK_REG, /* Interrupt mask register */ 304 DSIM_PKTHDR_REG, /* Packet Header FIFO register */ 305 DSIM_PAYLOAD_REG, /* Payload FIFO register */ 306 DSIM_RXFIFO_REG, /* Read FIFO register */ 307 DSIM_FIFOCTRL_REG, /* FIFO status and control register */ 308 DSIM_PLLCTRL_REG, /* PLL control register */ 309 DSIM_PHYCTRL_REG, 310 DSIM_PHYTIMING_REG, 311 DSIM_PHYTIMING1_REG, 312 DSIM_PHYTIMING2_REG, 313 NUM_REGS 314 }; 315 316 static inline void exynos_dsi_write(struct exynos_dsi *dsi, enum reg_idx idx, 317 u32 val) 318 { 319 320 writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]); 321 } 322 323 static inline u32 exynos_dsi_read(struct exynos_dsi *dsi, enum reg_idx idx) 324 { 325 return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]); 326 } 327 328 static const unsigned int exynos_reg_ofs[] = { 329 [DSIM_STATUS_REG] = 0x00, 330 [DSIM_SWRST_REG] = 0x04, 331 [DSIM_CLKCTRL_REG] = 0x08, 332 [DSIM_TIMEOUT_REG] = 0x0c, 333 [DSIM_CONFIG_REG] = 0x10, 334 [DSIM_ESCMODE_REG] = 0x14, 335 [DSIM_MDRESOL_REG] = 0x18, 336 [DSIM_MVPORCH_REG] = 0x1c, 337 [DSIM_MHPORCH_REG] = 0x20, 338 [DSIM_MSYNC_REG] = 0x24, 339 [DSIM_INTSRC_REG] = 0x2c, 340 [DSIM_INTMSK_REG] = 0x30, 341 [DSIM_PKTHDR_REG] = 0x34, 342 [DSIM_PAYLOAD_REG] = 0x38, 343 [DSIM_RXFIFO_REG] = 0x3c, 344 [DSIM_FIFOCTRL_REG] = 0x44, 345 [DSIM_PLLCTRL_REG] = 0x4c, 346 [DSIM_PHYCTRL_REG] = 0x5c, 347 [DSIM_PHYTIMING_REG] = 0x64, 348 [DSIM_PHYTIMING1_REG] = 0x68, 349 [DSIM_PHYTIMING2_REG] = 0x6c, 350 }; 351 352 static const unsigned int exynos5433_reg_ofs[] = { 353 [DSIM_STATUS_REG] = 0x04, 354 [DSIM_SWRST_REG] = 0x0C, 355 [DSIM_CLKCTRL_REG] = 0x10, 356 [DSIM_TIMEOUT_REG] = 0x14, 357 [DSIM_CONFIG_REG] = 0x18, 358 [DSIM_ESCMODE_REG] = 0x1C, 359 [DSIM_MDRESOL_REG] = 0x20, 360 [DSIM_MVPORCH_REG] = 0x24, 361 [DSIM_MHPORCH_REG] = 0x28, 362 [DSIM_MSYNC_REG] = 0x2C, 363 [DSIM_INTSRC_REG] = 0x34, 364 [DSIM_INTMSK_REG] = 0x38, 365 [DSIM_PKTHDR_REG] = 0x3C, 366 [DSIM_PAYLOAD_REG] = 0x40, 367 [DSIM_RXFIFO_REG] = 0x44, 368 [DSIM_FIFOCTRL_REG] = 0x4C, 369 [DSIM_PLLCTRL_REG] = 0x94, 370 [DSIM_PHYCTRL_REG] = 0xA4, 371 [DSIM_PHYTIMING_REG] = 0xB4, 372 [DSIM_PHYTIMING1_REG] = 0xB8, 373 [DSIM_PHYTIMING2_REG] = 0xBC, 374 }; 375 376 enum reg_value_idx { 377 RESET_TYPE, 378 PLL_TIMER, 379 STOP_STATE_CNT, 380 PHYCTRL_ULPS_EXIT, 381 PHYCTRL_VREG_LP, 382 PHYCTRL_SLEW_UP, 383 PHYTIMING_LPX, 384 PHYTIMING_HS_EXIT, 385 PHYTIMING_CLK_PREPARE, 386 PHYTIMING_CLK_ZERO, 387 PHYTIMING_CLK_POST, 388 PHYTIMING_CLK_TRAIL, 389 PHYTIMING_HS_PREPARE, 390 PHYTIMING_HS_ZERO, 391 PHYTIMING_HS_TRAIL 392 }; 393 394 static const unsigned int reg_values[] = { 395 [RESET_TYPE] = DSIM_SWRST, 396 [PLL_TIMER] = 500, 397 [STOP_STATE_CNT] = 0xf, 398 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af), 399 [PHYCTRL_VREG_LP] = 0, 400 [PHYCTRL_SLEW_UP] = 0, 401 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06), 402 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b), 403 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07), 404 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27), 405 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d), 406 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08), 407 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09), 408 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d), 409 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b), 410 }; 411 412 static const unsigned int exynos5422_reg_values[] = { 413 [RESET_TYPE] = DSIM_SWRST, 414 [PLL_TIMER] = 500, 415 [STOP_STATE_CNT] = 0xf, 416 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf), 417 [PHYCTRL_VREG_LP] = 0, 418 [PHYCTRL_SLEW_UP] = 0, 419 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x08), 420 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0d), 421 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09), 422 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x30), 423 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e), 424 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x0a), 425 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0c), 426 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x11), 427 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0d), 428 }; 429 430 static const unsigned int exynos5433_reg_values[] = { 431 [RESET_TYPE] = DSIM_FUNCRST, 432 [PLL_TIMER] = 22200, 433 [STOP_STATE_CNT] = 0xa, 434 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x190), 435 [PHYCTRL_VREG_LP] = DSIM_PHYCTRL_B_DPHYCTL_VREG_LP, 436 [PHYCTRL_SLEW_UP] = DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP, 437 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07), 438 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c), 439 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09), 440 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2d), 441 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e), 442 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09), 443 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0b), 444 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x10), 445 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c), 446 }; 447 448 static const struct exynos_dsi_driver_data exynos3_dsi_driver_data = { 449 .reg_ofs = exynos_reg_ofs, 450 .plltmr_reg = 0x50, 451 .has_freqband = 1, 452 .has_clklane_stop = 1, 453 .num_clks = 2, 454 .max_freq = 1000, 455 .wait_for_reset = 1, 456 .num_bits_resol = 11, 457 .reg_values = reg_values, 458 }; 459 460 static const struct exynos_dsi_driver_data exynos4_dsi_driver_data = { 461 .reg_ofs = exynos_reg_ofs, 462 .plltmr_reg = 0x50, 463 .has_freqband = 1, 464 .has_clklane_stop = 1, 465 .num_clks = 2, 466 .max_freq = 1000, 467 .wait_for_reset = 1, 468 .num_bits_resol = 11, 469 .reg_values = reg_values, 470 }; 471 472 static const struct exynos_dsi_driver_data exynos5_dsi_driver_data = { 473 .reg_ofs = exynos_reg_ofs, 474 .plltmr_reg = 0x58, 475 .num_clks = 2, 476 .max_freq = 1000, 477 .wait_for_reset = 1, 478 .num_bits_resol = 11, 479 .reg_values = reg_values, 480 }; 481 482 static const struct exynos_dsi_driver_data exynos5433_dsi_driver_data = { 483 .reg_ofs = exynos5433_reg_ofs, 484 .plltmr_reg = 0xa0, 485 .has_clklane_stop = 1, 486 .num_clks = 5, 487 .max_freq = 1500, 488 .wait_for_reset = 0, 489 .num_bits_resol = 12, 490 .reg_values = exynos5433_reg_values, 491 }; 492 493 static const struct exynos_dsi_driver_data exynos5422_dsi_driver_data = { 494 .reg_ofs = exynos5433_reg_ofs, 495 .plltmr_reg = 0xa0, 496 .has_clklane_stop = 1, 497 .num_clks = 2, 498 .max_freq = 1500, 499 .wait_for_reset = 1, 500 .num_bits_resol = 12, 501 .reg_values = exynos5422_reg_values, 502 }; 503 504 static const struct of_device_id exynos_dsi_of_match[] = { 505 { .compatible = "samsung,exynos3250-mipi-dsi", 506 .data = &exynos3_dsi_driver_data }, 507 { .compatible = "samsung,exynos4210-mipi-dsi", 508 .data = &exynos4_dsi_driver_data }, 509 { .compatible = "samsung,exynos5410-mipi-dsi", 510 .data = &exynos5_dsi_driver_data }, 511 { .compatible = "samsung,exynos5422-mipi-dsi", 512 .data = &exynos5422_dsi_driver_data }, 513 { .compatible = "samsung,exynos5433-mipi-dsi", 514 .data = &exynos5433_dsi_driver_data }, 515 { } 516 }; 517 518 static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi) 519 { 520 if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300))) 521 return; 522 523 dev_err(dsi->dev, "timeout waiting for reset\n"); 524 } 525 526 static void exynos_dsi_reset(struct exynos_dsi *dsi) 527 { 528 u32 reset_val = dsi->driver_data->reg_values[RESET_TYPE]; 529 530 reinit_completion(&dsi->completed); 531 exynos_dsi_write(dsi, DSIM_SWRST_REG, reset_val); 532 } 533 534 #ifndef MHZ 535 #define MHZ (1000*1000) 536 #endif 537 538 static unsigned long exynos_dsi_pll_find_pms(struct exynos_dsi *dsi, 539 unsigned long fin, unsigned long fout, u8 *p, u16 *m, u8 *s) 540 { 541 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 542 unsigned long best_freq = 0; 543 u32 min_delta = 0xffffffff; 544 u8 p_min, p_max; 545 u8 _p, best_p; 546 u16 _m, best_m; 547 u8 _s, best_s; 548 549 p_min = DIV_ROUND_UP(fin, (12 * MHZ)); 550 p_max = fin / (6 * MHZ); 551 552 for (_p = p_min; _p <= p_max; ++_p) { 553 for (_s = 0; _s <= 5; ++_s) { 554 u64 tmp; 555 u32 delta; 556 557 tmp = (u64)fout * (_p << _s); 558 do_div(tmp, fin); 559 _m = tmp; 560 if (_m < 41 || _m > 125) 561 continue; 562 563 tmp = (u64)_m * fin; 564 do_div(tmp, _p); 565 if (tmp < 500 * MHZ || 566 tmp > driver_data->max_freq * MHZ) 567 continue; 568 569 tmp = (u64)_m * fin; 570 do_div(tmp, _p << _s); 571 572 delta = abs(fout - tmp); 573 if (delta < min_delta) { 574 best_p = _p; 575 best_m = _m; 576 best_s = _s; 577 min_delta = delta; 578 best_freq = tmp; 579 } 580 } 581 } 582 583 if (best_freq) { 584 *p = best_p; 585 *m = best_m; 586 *s = best_s; 587 } 588 589 return best_freq; 590 } 591 592 static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi, 593 unsigned long freq) 594 { 595 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 596 unsigned long fin, fout; 597 int timeout; 598 u8 p, s; 599 u16 m; 600 u32 reg; 601 602 fin = dsi->pll_clk_rate; 603 fout = exynos_dsi_pll_find_pms(dsi, fin, freq, &p, &m, &s); 604 if (!fout) { 605 dev_err(dsi->dev, 606 "failed to find PLL PMS for requested frequency\n"); 607 return 0; 608 } 609 dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s); 610 611 writel(driver_data->reg_values[PLL_TIMER], 612 dsi->reg_base + driver_data->plltmr_reg); 613 614 reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s); 615 616 if (driver_data->has_freqband) { 617 static const unsigned long freq_bands[] = { 618 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ, 619 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ, 620 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ, 621 770 * MHZ, 870 * MHZ, 950 * MHZ, 622 }; 623 int band; 624 625 for (band = 0; band < ARRAY_SIZE(freq_bands); ++band) 626 if (fout < freq_bands[band]) 627 break; 628 629 dev_dbg(dsi->dev, "band %d\n", band); 630 631 reg |= DSIM_FREQ_BAND(band); 632 } 633 634 exynos_dsi_write(dsi, DSIM_PLLCTRL_REG, reg); 635 636 timeout = 1000; 637 do { 638 if (timeout-- == 0) { 639 dev_err(dsi->dev, "PLL failed to stabilize\n"); 640 return 0; 641 } 642 reg = exynos_dsi_read(dsi, DSIM_STATUS_REG); 643 } while ((reg & DSIM_PLL_STABLE) == 0); 644 645 return fout; 646 } 647 648 static int exynos_dsi_enable_clock(struct exynos_dsi *dsi) 649 { 650 unsigned long hs_clk, byte_clk, esc_clk; 651 unsigned long esc_div; 652 u32 reg; 653 654 hs_clk = exynos_dsi_set_pll(dsi, dsi->burst_clk_rate); 655 if (!hs_clk) { 656 dev_err(dsi->dev, "failed to configure DSI PLL\n"); 657 return -EFAULT; 658 } 659 660 byte_clk = hs_clk / 8; 661 esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate); 662 esc_clk = byte_clk / esc_div; 663 664 if (esc_clk > 20 * MHZ) { 665 ++esc_div; 666 esc_clk = byte_clk / esc_div; 667 } 668 669 dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n", 670 hs_clk, byte_clk, esc_clk); 671 672 reg = exynos_dsi_read(dsi, DSIM_CLKCTRL_REG); 673 reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK 674 | DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS 675 | DSIM_BYTE_CLK_SRC_MASK); 676 reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN 677 | DSIM_ESC_PRESCALER(esc_div) 678 | DSIM_LANE_ESC_CLK_EN_CLK 679 | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1) 680 | DSIM_BYTE_CLK_SRC(0) 681 | DSIM_TX_REQUEST_HSCLK; 682 exynos_dsi_write(dsi, DSIM_CLKCTRL_REG, reg); 683 684 return 0; 685 } 686 687 static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi) 688 { 689 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 690 const unsigned int *reg_values = driver_data->reg_values; 691 u32 reg; 692 693 if (driver_data->has_freqband) 694 return; 695 696 /* B D-PHY: D-PHY Master & Slave Analog Block control */ 697 reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] | 698 reg_values[PHYCTRL_SLEW_UP]; 699 exynos_dsi_write(dsi, DSIM_PHYCTRL_REG, reg); 700 701 /* 702 * T LPX: Transmitted length of any Low-Power state period 703 * T HS-EXIT: Time that the transmitter drives LP-11 following a HS 704 * burst 705 */ 706 reg = reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT]; 707 exynos_dsi_write(dsi, DSIM_PHYTIMING_REG, reg); 708 709 /* 710 * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00 711 * Line state immediately before the HS-0 Line state starting the 712 * HS transmission 713 * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to 714 * transmitting the Clock. 715 * T CLK_POST: Time that the transmitter continues to send HS clock 716 * after the last associated Data Lane has transitioned to LP Mode 717 * Interval is defined as the period from the end of T HS-TRAIL to 718 * the beginning of T CLK-TRAIL 719 * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after 720 * the last payload clock bit of a HS transmission burst 721 */ 722 reg = reg_values[PHYTIMING_CLK_PREPARE] | 723 reg_values[PHYTIMING_CLK_ZERO] | 724 reg_values[PHYTIMING_CLK_POST] | 725 reg_values[PHYTIMING_CLK_TRAIL]; 726 727 exynos_dsi_write(dsi, DSIM_PHYTIMING1_REG, reg); 728 729 /* 730 * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00 731 * Line state immediately before the HS-0 Line state starting the 732 * HS transmission 733 * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to 734 * transmitting the Sync sequence. 735 * T HS-TRAIL: Time that the transmitter drives the flipped differential 736 * state after last payload data bit of a HS transmission burst 737 */ 738 reg = reg_values[PHYTIMING_HS_PREPARE] | reg_values[PHYTIMING_HS_ZERO] | 739 reg_values[PHYTIMING_HS_TRAIL]; 740 exynos_dsi_write(dsi, DSIM_PHYTIMING2_REG, reg); 741 } 742 743 static void exynos_dsi_disable_clock(struct exynos_dsi *dsi) 744 { 745 u32 reg; 746 747 reg = exynos_dsi_read(dsi, DSIM_CLKCTRL_REG); 748 reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK 749 | DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN); 750 exynos_dsi_write(dsi, DSIM_CLKCTRL_REG, reg); 751 752 reg = exynos_dsi_read(dsi, DSIM_PLLCTRL_REG); 753 reg &= ~DSIM_PLL_EN; 754 exynos_dsi_write(dsi, DSIM_PLLCTRL_REG, reg); 755 } 756 757 static void exynos_dsi_enable_lane(struct exynos_dsi *dsi, u32 lane) 758 { 759 u32 reg = exynos_dsi_read(dsi, DSIM_CONFIG_REG); 760 reg |= (DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1) | DSIM_LANE_EN_CLK | 761 DSIM_LANE_EN(lane)); 762 exynos_dsi_write(dsi, DSIM_CONFIG_REG, reg); 763 } 764 765 static int exynos_dsi_init_link(struct exynos_dsi *dsi) 766 { 767 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 768 int timeout; 769 u32 reg; 770 u32 lanes_mask; 771 772 /* Initialize FIFO pointers */ 773 reg = exynos_dsi_read(dsi, DSIM_FIFOCTRL_REG); 774 reg &= ~0x1f; 775 exynos_dsi_write(dsi, DSIM_FIFOCTRL_REG, reg); 776 777 usleep_range(9000, 11000); 778 779 reg |= 0x1f; 780 exynos_dsi_write(dsi, DSIM_FIFOCTRL_REG, reg); 781 usleep_range(9000, 11000); 782 783 /* DSI configuration */ 784 reg = 0; 785 786 /* 787 * The first bit of mode_flags specifies display configuration. 788 * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video 789 * mode, otherwise it will support command mode. 790 */ 791 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 792 reg |= DSIM_VIDEO_MODE; 793 794 /* 795 * The user manual describes that following bits are ignored in 796 * command mode. 797 */ 798 if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH)) 799 reg |= DSIM_MFLUSH_VS; 800 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 801 reg |= DSIM_SYNC_INFORM; 802 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 803 reg |= DSIM_BURST_MODE; 804 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT) 805 reg |= DSIM_AUTO_MODE; 806 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE) 807 reg |= DSIM_HSE_MODE; 808 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HFP)) 809 reg |= DSIM_HFP_MODE; 810 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HBP)) 811 reg |= DSIM_HBP_MODE; 812 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HSA)) 813 reg |= DSIM_HSA_MODE; 814 } 815 816 if (!(dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET)) 817 reg |= DSIM_EOT_DISABLE; 818 819 switch (dsi->format) { 820 case MIPI_DSI_FMT_RGB888: 821 reg |= DSIM_MAIN_PIX_FORMAT_RGB888; 822 break; 823 case MIPI_DSI_FMT_RGB666: 824 reg |= DSIM_MAIN_PIX_FORMAT_RGB666; 825 break; 826 case MIPI_DSI_FMT_RGB666_PACKED: 827 reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P; 828 break; 829 case MIPI_DSI_FMT_RGB565: 830 reg |= DSIM_MAIN_PIX_FORMAT_RGB565; 831 break; 832 default: 833 dev_err(dsi->dev, "invalid pixel format\n"); 834 return -EINVAL; 835 } 836 837 /* 838 * Use non-continuous clock mode if the periparal wants and 839 * host controller supports 840 * 841 * In non-continous clock mode, host controller will turn off 842 * the HS clock between high-speed transmissions to reduce 843 * power consumption. 844 */ 845 if (driver_data->has_clklane_stop && 846 dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { 847 reg |= DSIM_CLKLANE_STOP; 848 } 849 exynos_dsi_write(dsi, DSIM_CONFIG_REG, reg); 850 851 lanes_mask = BIT(dsi->lanes) - 1; 852 exynos_dsi_enable_lane(dsi, lanes_mask); 853 854 /* Check clock and data lane state are stop state */ 855 timeout = 100; 856 do { 857 if (timeout-- == 0) { 858 dev_err(dsi->dev, "waiting for bus lanes timed out\n"); 859 return -EFAULT; 860 } 861 862 reg = exynos_dsi_read(dsi, DSIM_STATUS_REG); 863 if ((reg & DSIM_STOP_STATE_DAT(lanes_mask)) 864 != DSIM_STOP_STATE_DAT(lanes_mask)) 865 continue; 866 } while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK))); 867 868 reg = exynos_dsi_read(dsi, DSIM_ESCMODE_REG); 869 reg &= ~DSIM_STOP_STATE_CNT_MASK; 870 reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]); 871 exynos_dsi_write(dsi, DSIM_ESCMODE_REG, reg); 872 873 reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff); 874 exynos_dsi_write(dsi, DSIM_TIMEOUT_REG, reg); 875 876 return 0; 877 } 878 879 static void exynos_dsi_set_display_mode(struct exynos_dsi *dsi) 880 { 881 struct drm_display_mode *m = &dsi->mode; 882 unsigned int num_bits_resol = dsi->driver_data->num_bits_resol; 883 u32 reg; 884 885 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 886 reg = DSIM_CMD_ALLOW(0xf) 887 | DSIM_STABLE_VFP(m->vsync_start - m->vdisplay) 888 | DSIM_MAIN_VBP(m->vtotal - m->vsync_end); 889 exynos_dsi_write(dsi, DSIM_MVPORCH_REG, reg); 890 891 reg = DSIM_MAIN_HFP(m->hsync_start - m->hdisplay) 892 | DSIM_MAIN_HBP(m->htotal - m->hsync_end); 893 exynos_dsi_write(dsi, DSIM_MHPORCH_REG, reg); 894 895 reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start) 896 | DSIM_MAIN_HSA(m->hsync_end - m->hsync_start); 897 exynos_dsi_write(dsi, DSIM_MSYNC_REG, reg); 898 } 899 reg = DSIM_MAIN_HRESOL(m->hdisplay, num_bits_resol) | 900 DSIM_MAIN_VRESOL(m->vdisplay, num_bits_resol); 901 902 exynos_dsi_write(dsi, DSIM_MDRESOL_REG, reg); 903 904 dev_dbg(dsi->dev, "LCD size = %dx%d\n", m->hdisplay, m->vdisplay); 905 } 906 907 static void exynos_dsi_set_display_enable(struct exynos_dsi *dsi, bool enable) 908 { 909 u32 reg; 910 911 reg = exynos_dsi_read(dsi, DSIM_MDRESOL_REG); 912 if (enable) 913 reg |= DSIM_MAIN_STAND_BY; 914 else 915 reg &= ~DSIM_MAIN_STAND_BY; 916 exynos_dsi_write(dsi, DSIM_MDRESOL_REG, reg); 917 } 918 919 static int exynos_dsi_wait_for_hdr_fifo(struct exynos_dsi *dsi) 920 { 921 int timeout = 2000; 922 923 do { 924 u32 reg = exynos_dsi_read(dsi, DSIM_FIFOCTRL_REG); 925 926 if (!(reg & DSIM_SFR_HEADER_FULL)) 927 return 0; 928 929 if (!cond_resched()) 930 usleep_range(950, 1050); 931 } while (--timeout); 932 933 return -ETIMEDOUT; 934 } 935 936 static void exynos_dsi_set_cmd_lpm(struct exynos_dsi *dsi, bool lpm) 937 { 938 u32 v = exynos_dsi_read(dsi, DSIM_ESCMODE_REG); 939 940 if (lpm) 941 v |= DSIM_CMD_LPDT_LP; 942 else 943 v &= ~DSIM_CMD_LPDT_LP; 944 945 exynos_dsi_write(dsi, DSIM_ESCMODE_REG, v); 946 } 947 948 static void exynos_dsi_force_bta(struct exynos_dsi *dsi) 949 { 950 u32 v = exynos_dsi_read(dsi, DSIM_ESCMODE_REG); 951 v |= DSIM_FORCE_BTA; 952 exynos_dsi_write(dsi, DSIM_ESCMODE_REG, v); 953 } 954 955 static void exynos_dsi_send_to_fifo(struct exynos_dsi *dsi, 956 struct exynos_dsi_transfer *xfer) 957 { 958 struct device *dev = dsi->dev; 959 struct mipi_dsi_packet *pkt = &xfer->packet; 960 const u8 *payload = pkt->payload + xfer->tx_done; 961 u16 length = pkt->payload_length - xfer->tx_done; 962 bool first = !xfer->tx_done; 963 u32 reg; 964 965 dev_dbg(dev, "< xfer %pK: tx len %u, done %u, rx len %u, done %u\n", 966 xfer, length, xfer->tx_done, xfer->rx_len, xfer->rx_done); 967 968 if (length > DSI_TX_FIFO_SIZE) 969 length = DSI_TX_FIFO_SIZE; 970 971 xfer->tx_done += length; 972 973 /* Send payload */ 974 while (length >= 4) { 975 reg = get_unaligned_le32(payload); 976 exynos_dsi_write(dsi, DSIM_PAYLOAD_REG, reg); 977 payload += 4; 978 length -= 4; 979 } 980 981 reg = 0; 982 switch (length) { 983 case 3: 984 reg |= payload[2] << 16; 985 fallthrough; 986 case 2: 987 reg |= payload[1] << 8; 988 fallthrough; 989 case 1: 990 reg |= payload[0]; 991 exynos_dsi_write(dsi, DSIM_PAYLOAD_REG, reg); 992 break; 993 } 994 995 /* Send packet header */ 996 if (!first) 997 return; 998 999 reg = get_unaligned_le32(pkt->header); 1000 if (exynos_dsi_wait_for_hdr_fifo(dsi)) { 1001 dev_err(dev, "waiting for header FIFO timed out\n"); 1002 return; 1003 } 1004 1005 if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM, 1006 dsi->state & DSIM_STATE_CMD_LPM)) { 1007 exynos_dsi_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM); 1008 dsi->state ^= DSIM_STATE_CMD_LPM; 1009 } 1010 1011 exynos_dsi_write(dsi, DSIM_PKTHDR_REG, reg); 1012 1013 if (xfer->flags & MIPI_DSI_MSG_REQ_ACK) 1014 exynos_dsi_force_bta(dsi); 1015 } 1016 1017 static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi, 1018 struct exynos_dsi_transfer *xfer) 1019 { 1020 u8 *payload = xfer->rx_payload + xfer->rx_done; 1021 bool first = !xfer->rx_done; 1022 struct device *dev = dsi->dev; 1023 u16 length; 1024 u32 reg; 1025 1026 if (first) { 1027 reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG); 1028 1029 switch (reg & 0x3f) { 1030 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 1031 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 1032 if (xfer->rx_len >= 2) { 1033 payload[1] = reg >> 16; 1034 ++xfer->rx_done; 1035 } 1036 fallthrough; 1037 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 1038 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 1039 payload[0] = reg >> 8; 1040 ++xfer->rx_done; 1041 xfer->rx_len = xfer->rx_done; 1042 xfer->result = 0; 1043 goto clear_fifo; 1044 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 1045 dev_err(dev, "DSI Error Report: 0x%04x\n", 1046 (reg >> 8) & 0xffff); 1047 xfer->result = 0; 1048 goto clear_fifo; 1049 } 1050 1051 length = (reg >> 8) & 0xffff; 1052 if (length > xfer->rx_len) { 1053 dev_err(dev, 1054 "response too long (%u > %u bytes), stripping\n", 1055 xfer->rx_len, length); 1056 length = xfer->rx_len; 1057 } else if (length < xfer->rx_len) 1058 xfer->rx_len = length; 1059 } 1060 1061 length = xfer->rx_len - xfer->rx_done; 1062 xfer->rx_done += length; 1063 1064 /* Receive payload */ 1065 while (length >= 4) { 1066 reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG); 1067 payload[0] = (reg >> 0) & 0xff; 1068 payload[1] = (reg >> 8) & 0xff; 1069 payload[2] = (reg >> 16) & 0xff; 1070 payload[3] = (reg >> 24) & 0xff; 1071 payload += 4; 1072 length -= 4; 1073 } 1074 1075 if (length) { 1076 reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG); 1077 switch (length) { 1078 case 3: 1079 payload[2] = (reg >> 16) & 0xff; 1080 fallthrough; 1081 case 2: 1082 payload[1] = (reg >> 8) & 0xff; 1083 fallthrough; 1084 case 1: 1085 payload[0] = reg & 0xff; 1086 } 1087 } 1088 1089 if (xfer->rx_done == xfer->rx_len) 1090 xfer->result = 0; 1091 1092 clear_fifo: 1093 length = DSI_RX_FIFO_SIZE / 4; 1094 do { 1095 reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG); 1096 if (reg == DSI_RX_FIFO_EMPTY) 1097 break; 1098 } while (--length); 1099 } 1100 1101 static void exynos_dsi_transfer_start(struct exynos_dsi *dsi) 1102 { 1103 unsigned long flags; 1104 struct exynos_dsi_transfer *xfer; 1105 bool start = false; 1106 1107 again: 1108 spin_lock_irqsave(&dsi->transfer_lock, flags); 1109 1110 if (list_empty(&dsi->transfer_list)) { 1111 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1112 return; 1113 } 1114 1115 xfer = list_first_entry(&dsi->transfer_list, 1116 struct exynos_dsi_transfer, list); 1117 1118 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1119 1120 if (xfer->packet.payload_length && 1121 xfer->tx_done == xfer->packet.payload_length) 1122 /* waiting for RX */ 1123 return; 1124 1125 exynos_dsi_send_to_fifo(dsi, xfer); 1126 1127 if (xfer->packet.payload_length || xfer->rx_len) 1128 return; 1129 1130 xfer->result = 0; 1131 complete(&xfer->completed); 1132 1133 spin_lock_irqsave(&dsi->transfer_lock, flags); 1134 1135 list_del_init(&xfer->list); 1136 start = !list_empty(&dsi->transfer_list); 1137 1138 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1139 1140 if (start) 1141 goto again; 1142 } 1143 1144 static bool exynos_dsi_transfer_finish(struct exynos_dsi *dsi) 1145 { 1146 struct exynos_dsi_transfer *xfer; 1147 unsigned long flags; 1148 bool start = true; 1149 1150 spin_lock_irqsave(&dsi->transfer_lock, flags); 1151 1152 if (list_empty(&dsi->transfer_list)) { 1153 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1154 return false; 1155 } 1156 1157 xfer = list_first_entry(&dsi->transfer_list, 1158 struct exynos_dsi_transfer, list); 1159 1160 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1161 1162 dev_dbg(dsi->dev, 1163 "> xfer %pK, tx_len %zu, tx_done %u, rx_len %u, rx_done %u\n", 1164 xfer, xfer->packet.payload_length, xfer->tx_done, xfer->rx_len, 1165 xfer->rx_done); 1166 1167 if (xfer->tx_done != xfer->packet.payload_length) 1168 return true; 1169 1170 if (xfer->rx_done != xfer->rx_len) 1171 exynos_dsi_read_from_fifo(dsi, xfer); 1172 1173 if (xfer->rx_done != xfer->rx_len) 1174 return true; 1175 1176 spin_lock_irqsave(&dsi->transfer_lock, flags); 1177 1178 list_del_init(&xfer->list); 1179 start = !list_empty(&dsi->transfer_list); 1180 1181 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1182 1183 if (!xfer->rx_len) 1184 xfer->result = 0; 1185 complete(&xfer->completed); 1186 1187 return start; 1188 } 1189 1190 static void exynos_dsi_remove_transfer(struct exynos_dsi *dsi, 1191 struct exynos_dsi_transfer *xfer) 1192 { 1193 unsigned long flags; 1194 bool start; 1195 1196 spin_lock_irqsave(&dsi->transfer_lock, flags); 1197 1198 if (!list_empty(&dsi->transfer_list) && 1199 xfer == list_first_entry(&dsi->transfer_list, 1200 struct exynos_dsi_transfer, list)) { 1201 list_del_init(&xfer->list); 1202 start = !list_empty(&dsi->transfer_list); 1203 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1204 if (start) 1205 exynos_dsi_transfer_start(dsi); 1206 return; 1207 } 1208 1209 list_del_init(&xfer->list); 1210 1211 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1212 } 1213 1214 static int exynos_dsi_transfer(struct exynos_dsi *dsi, 1215 struct exynos_dsi_transfer *xfer) 1216 { 1217 unsigned long flags; 1218 bool stopped; 1219 1220 xfer->tx_done = 0; 1221 xfer->rx_done = 0; 1222 xfer->result = -ETIMEDOUT; 1223 init_completion(&xfer->completed); 1224 1225 spin_lock_irqsave(&dsi->transfer_lock, flags); 1226 1227 stopped = list_empty(&dsi->transfer_list); 1228 list_add_tail(&xfer->list, &dsi->transfer_list); 1229 1230 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1231 1232 if (stopped) 1233 exynos_dsi_transfer_start(dsi); 1234 1235 wait_for_completion_timeout(&xfer->completed, 1236 msecs_to_jiffies(DSI_XFER_TIMEOUT_MS)); 1237 if (xfer->result == -ETIMEDOUT) { 1238 struct mipi_dsi_packet *pkt = &xfer->packet; 1239 exynos_dsi_remove_transfer(dsi, xfer); 1240 dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 4, pkt->header, 1241 (int)pkt->payload_length, pkt->payload); 1242 return -ETIMEDOUT; 1243 } 1244 1245 /* Also covers hardware timeout condition */ 1246 return xfer->result; 1247 } 1248 1249 static irqreturn_t exynos_dsi_irq(int irq, void *dev_id) 1250 { 1251 struct exynos_dsi *dsi = dev_id; 1252 u32 status; 1253 1254 status = exynos_dsi_read(dsi, DSIM_INTSRC_REG); 1255 if (!status) { 1256 static unsigned long int j; 1257 if (printk_timed_ratelimit(&j, 500)) 1258 dev_warn(dsi->dev, "spurious interrupt\n"); 1259 return IRQ_HANDLED; 1260 } 1261 exynos_dsi_write(dsi, DSIM_INTSRC_REG, status); 1262 1263 if (status & DSIM_INT_SW_RST_RELEASE) { 1264 u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY | 1265 DSIM_INT_SFR_HDR_FIFO_EMPTY | DSIM_INT_RX_ECC_ERR | 1266 DSIM_INT_SW_RST_RELEASE); 1267 exynos_dsi_write(dsi, DSIM_INTMSK_REG, mask); 1268 complete(&dsi->completed); 1269 return IRQ_HANDLED; 1270 } 1271 1272 if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY | 1273 DSIM_INT_PLL_STABLE))) 1274 return IRQ_HANDLED; 1275 1276 if (exynos_dsi_transfer_finish(dsi)) 1277 exynos_dsi_transfer_start(dsi); 1278 1279 return IRQ_HANDLED; 1280 } 1281 1282 static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id) 1283 { 1284 struct exynos_dsi *dsi = (struct exynos_dsi *)dev_id; 1285 struct drm_encoder *encoder = &dsi->encoder; 1286 1287 if (dsi->state & DSIM_STATE_VIDOUT_AVAILABLE) 1288 exynos_drm_crtc_te_handler(encoder->crtc); 1289 1290 return IRQ_HANDLED; 1291 } 1292 1293 static void exynos_dsi_enable_irq(struct exynos_dsi *dsi) 1294 { 1295 enable_irq(dsi->irq); 1296 1297 if (dsi->te_gpio) 1298 enable_irq(gpiod_to_irq(dsi->te_gpio)); 1299 } 1300 1301 static void exynos_dsi_disable_irq(struct exynos_dsi *dsi) 1302 { 1303 if (dsi->te_gpio) 1304 disable_irq(gpiod_to_irq(dsi->te_gpio)); 1305 1306 disable_irq(dsi->irq); 1307 } 1308 1309 static int exynos_dsi_init(struct exynos_dsi *dsi) 1310 { 1311 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 1312 1313 exynos_dsi_reset(dsi); 1314 exynos_dsi_enable_irq(dsi); 1315 1316 if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST) 1317 exynos_dsi_enable_lane(dsi, BIT(dsi->lanes) - 1); 1318 1319 exynos_dsi_enable_clock(dsi); 1320 if (driver_data->wait_for_reset) 1321 exynos_dsi_wait_for_reset(dsi); 1322 exynos_dsi_set_phy_ctrl(dsi); 1323 exynos_dsi_init_link(dsi); 1324 1325 return 0; 1326 } 1327 1328 static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi, 1329 struct device *panel) 1330 { 1331 int ret; 1332 int te_gpio_irq; 1333 1334 dsi->te_gpio = gpiod_get_optional(panel, "te", GPIOD_IN); 1335 if (!dsi->te_gpio) { 1336 return 0; 1337 } else if (IS_ERR(dsi->te_gpio)) { 1338 dev_err(dsi->dev, "gpio request failed with %ld\n", 1339 PTR_ERR(dsi->te_gpio)); 1340 return PTR_ERR(dsi->te_gpio); 1341 } 1342 1343 te_gpio_irq = gpiod_to_irq(dsi->te_gpio); 1344 1345 ret = request_threaded_irq(te_gpio_irq, exynos_dsi_te_irq_handler, NULL, 1346 IRQF_TRIGGER_RISING | IRQF_NO_AUTOEN, "TE", dsi); 1347 if (ret) { 1348 dev_err(dsi->dev, "request interrupt failed with %d\n", ret); 1349 gpiod_put(dsi->te_gpio); 1350 return ret; 1351 } 1352 1353 return 0; 1354 } 1355 1356 static void exynos_dsi_unregister_te_irq(struct exynos_dsi *dsi) 1357 { 1358 if (dsi->te_gpio) { 1359 free_irq(gpiod_to_irq(dsi->te_gpio), dsi); 1360 gpiod_put(dsi->te_gpio); 1361 } 1362 } 1363 1364 static void exynos_dsi_atomic_pre_enable(struct drm_bridge *bridge, 1365 struct drm_bridge_state *old_bridge_state) 1366 { 1367 struct exynos_dsi *dsi = bridge_to_dsi(bridge); 1368 int ret; 1369 1370 if (dsi->state & DSIM_STATE_ENABLED) 1371 return; 1372 1373 ret = pm_runtime_resume_and_get(dsi->dev); 1374 if (ret < 0) { 1375 dev_err(dsi->dev, "failed to enable DSI device.\n"); 1376 return; 1377 } 1378 1379 dsi->state |= DSIM_STATE_ENABLED; 1380 } 1381 1382 static void exynos_dsi_atomic_enable(struct drm_bridge *bridge, 1383 struct drm_bridge_state *old_bridge_state) 1384 { 1385 struct exynos_dsi *dsi = bridge_to_dsi(bridge); 1386 1387 exynos_dsi_set_display_mode(dsi); 1388 exynos_dsi_set_display_enable(dsi, true); 1389 1390 dsi->state |= DSIM_STATE_VIDOUT_AVAILABLE; 1391 1392 return; 1393 } 1394 1395 static void exynos_dsi_atomic_disable(struct drm_bridge *bridge, 1396 struct drm_bridge_state *old_bridge_state) 1397 { 1398 struct exynos_dsi *dsi = bridge_to_dsi(bridge); 1399 1400 if (!(dsi->state & DSIM_STATE_ENABLED)) 1401 return; 1402 1403 dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE; 1404 } 1405 1406 static void exynos_dsi_atomic_post_disable(struct drm_bridge *bridge, 1407 struct drm_bridge_state *old_bridge_state) 1408 { 1409 struct exynos_dsi *dsi = bridge_to_dsi(bridge); 1410 1411 exynos_dsi_set_display_enable(dsi, false); 1412 1413 dsi->state &= ~DSIM_STATE_ENABLED; 1414 pm_runtime_put_sync(dsi->dev); 1415 } 1416 1417 static void exynos_dsi_mode_set(struct drm_bridge *bridge, 1418 const struct drm_display_mode *mode, 1419 const struct drm_display_mode *adjusted_mode) 1420 { 1421 struct exynos_dsi *dsi = bridge_to_dsi(bridge); 1422 1423 drm_mode_copy(&dsi->mode, adjusted_mode); 1424 } 1425 1426 static int exynos_dsi_attach(struct drm_bridge *bridge, 1427 enum drm_bridge_attach_flags flags) 1428 { 1429 struct exynos_dsi *dsi = bridge_to_dsi(bridge); 1430 1431 return drm_bridge_attach(bridge->encoder, dsi->out_bridge, NULL, flags); 1432 } 1433 1434 static const struct drm_bridge_funcs exynos_dsi_bridge_funcs = { 1435 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 1436 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 1437 .atomic_reset = drm_atomic_helper_bridge_reset, 1438 .atomic_pre_enable = exynos_dsi_atomic_pre_enable, 1439 .atomic_enable = exynos_dsi_atomic_enable, 1440 .atomic_disable = exynos_dsi_atomic_disable, 1441 .atomic_post_disable = exynos_dsi_atomic_post_disable, 1442 .mode_set = exynos_dsi_mode_set, 1443 .attach = exynos_dsi_attach, 1444 }; 1445 1446 MODULE_DEVICE_TABLE(of, exynos_dsi_of_match); 1447 1448 static int exynos_dsi_host_attach(struct mipi_dsi_host *host, 1449 struct mipi_dsi_device *device) 1450 { 1451 struct exynos_dsi *dsi = host_to_dsi(host); 1452 struct device *dev = dsi->dev; 1453 struct drm_encoder *encoder = &dsi->encoder; 1454 struct drm_device *drm = encoder->dev; 1455 struct drm_panel *panel; 1456 int ret; 1457 1458 panel = of_drm_find_panel(device->dev.of_node); 1459 if (!IS_ERR(panel)) { 1460 dsi->out_bridge = devm_drm_panel_bridge_add(dev, panel); 1461 } else { 1462 dsi->out_bridge = of_drm_find_bridge(device->dev.of_node); 1463 if (!dsi->out_bridge) 1464 dsi->out_bridge = ERR_PTR(-EINVAL); 1465 } 1466 1467 if (IS_ERR(dsi->out_bridge)) { 1468 ret = PTR_ERR(dsi->out_bridge); 1469 DRM_DEV_ERROR(dev, "failed to find the bridge: %d\n", ret); 1470 return ret; 1471 } 1472 1473 DRM_DEV_INFO(dev, "Attached %s device\n", device->name); 1474 1475 drm_bridge_add(&dsi->bridge); 1476 1477 drm_bridge_attach(encoder, &dsi->bridge, NULL, 0); 1478 1479 /* 1480 * This is a temporary solution and should be made by more generic way. 1481 * 1482 * If attached panel device is for command mode one, dsi should register 1483 * TE interrupt handler. 1484 */ 1485 if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO)) { 1486 ret = exynos_dsi_register_te_irq(dsi, &device->dev); 1487 if (ret) 1488 return ret; 1489 } 1490 1491 mutex_lock(&drm->mode_config.mutex); 1492 1493 dsi->lanes = device->lanes; 1494 dsi->format = device->format; 1495 dsi->mode_flags = device->mode_flags; 1496 exynos_drm_crtc_get_by_type(drm, EXYNOS_DISPLAY_TYPE_LCD)->i80_mode = 1497 !(dsi->mode_flags & MIPI_DSI_MODE_VIDEO); 1498 1499 mutex_unlock(&drm->mode_config.mutex); 1500 1501 if (drm->mode_config.poll_enabled) 1502 drm_kms_helper_hotplug_event(drm); 1503 1504 return 0; 1505 } 1506 1507 static int exynos_dsi_host_detach(struct mipi_dsi_host *host, 1508 struct mipi_dsi_device *device) 1509 { 1510 struct exynos_dsi *dsi = host_to_dsi(host); 1511 struct drm_device *drm = dsi->encoder.dev; 1512 1513 if (dsi->out_bridge->funcs->detach) 1514 dsi->out_bridge->funcs->detach(dsi->out_bridge); 1515 dsi->out_bridge = NULL; 1516 1517 if (drm->mode_config.poll_enabled) 1518 drm_kms_helper_hotplug_event(drm); 1519 1520 exynos_dsi_unregister_te_irq(dsi); 1521 1522 drm_bridge_remove(&dsi->bridge); 1523 1524 return 0; 1525 } 1526 1527 static ssize_t exynos_dsi_host_transfer(struct mipi_dsi_host *host, 1528 const struct mipi_dsi_msg *msg) 1529 { 1530 struct exynos_dsi *dsi = host_to_dsi(host); 1531 struct exynos_dsi_transfer xfer; 1532 int ret; 1533 1534 if (!(dsi->state & DSIM_STATE_ENABLED)) 1535 return -EINVAL; 1536 1537 if (!(dsi->state & DSIM_STATE_INITIALIZED)) { 1538 ret = exynos_dsi_init(dsi); 1539 if (ret) 1540 return ret; 1541 dsi->state |= DSIM_STATE_INITIALIZED; 1542 } 1543 1544 ret = mipi_dsi_create_packet(&xfer.packet, msg); 1545 if (ret < 0) 1546 return ret; 1547 1548 xfer.rx_len = msg->rx_len; 1549 xfer.rx_payload = msg->rx_buf; 1550 xfer.flags = msg->flags; 1551 1552 ret = exynos_dsi_transfer(dsi, &xfer); 1553 return (ret < 0) ? ret : xfer.rx_done; 1554 } 1555 1556 static const struct mipi_dsi_host_ops exynos_dsi_ops = { 1557 .attach = exynos_dsi_host_attach, 1558 .detach = exynos_dsi_host_detach, 1559 .transfer = exynos_dsi_host_transfer, 1560 }; 1561 1562 static int exynos_dsi_of_read_u32(const struct device_node *np, 1563 const char *propname, u32 *out_value) 1564 { 1565 int ret = of_property_read_u32(np, propname, out_value); 1566 1567 if (ret < 0) 1568 pr_err("%pOF: failed to get '%s' property\n", np, propname); 1569 1570 return ret; 1571 } 1572 1573 static int exynos_dsi_parse_dt(struct exynos_dsi *dsi) 1574 { 1575 struct device *dev = dsi->dev; 1576 struct device_node *node = dev->of_node; 1577 int ret; 1578 1579 ret = exynos_dsi_of_read_u32(node, "samsung,pll-clock-frequency", 1580 &dsi->pll_clk_rate); 1581 if (ret < 0) 1582 return ret; 1583 1584 ret = exynos_dsi_of_read_u32(node, "samsung,burst-clock-frequency", 1585 &dsi->burst_clk_rate); 1586 if (ret < 0) 1587 return ret; 1588 1589 ret = exynos_dsi_of_read_u32(node, "samsung,esc-clock-frequency", 1590 &dsi->esc_clk_rate); 1591 if (ret < 0) 1592 return ret; 1593 1594 return 0; 1595 } 1596 1597 static int exynos_dsi_bind(struct device *dev, struct device *master, 1598 void *data) 1599 { 1600 struct exynos_dsi *dsi = dev_get_drvdata(dev); 1601 struct drm_encoder *encoder = &dsi->encoder; 1602 struct drm_device *drm_dev = data; 1603 int ret; 1604 1605 drm_simple_encoder_init(drm_dev, encoder, DRM_MODE_ENCODER_TMDS); 1606 1607 ret = exynos_drm_set_possible_crtcs(encoder, EXYNOS_DISPLAY_TYPE_LCD); 1608 if (ret < 0) 1609 return ret; 1610 1611 return mipi_dsi_host_register(&dsi->dsi_host); 1612 } 1613 1614 static void exynos_dsi_unbind(struct device *dev, struct device *master, 1615 void *data) 1616 { 1617 struct exynos_dsi *dsi = dev_get_drvdata(dev); 1618 1619 exynos_dsi_atomic_disable(&dsi->bridge, NULL); 1620 1621 mipi_dsi_host_unregister(&dsi->dsi_host); 1622 } 1623 1624 static const struct component_ops exynos_dsi_component_ops = { 1625 .bind = exynos_dsi_bind, 1626 .unbind = exynos_dsi_unbind, 1627 }; 1628 1629 static int exynos_dsi_probe(struct platform_device *pdev) 1630 { 1631 struct device *dev = &pdev->dev; 1632 struct exynos_dsi *dsi; 1633 int ret, i; 1634 1635 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 1636 if (!dsi) 1637 return -ENOMEM; 1638 1639 init_completion(&dsi->completed); 1640 spin_lock_init(&dsi->transfer_lock); 1641 INIT_LIST_HEAD(&dsi->transfer_list); 1642 1643 dsi->dsi_host.ops = &exynos_dsi_ops; 1644 dsi->dsi_host.dev = dev; 1645 1646 dsi->dev = dev; 1647 dsi->driver_data = of_device_get_match_data(dev); 1648 1649 dsi->supplies[0].supply = "vddcore"; 1650 dsi->supplies[1].supply = "vddio"; 1651 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies), 1652 dsi->supplies); 1653 if (ret) 1654 return dev_err_probe(dev, ret, "failed to get regulators\n"); 1655 1656 dsi->clks = devm_kcalloc(dev, 1657 dsi->driver_data->num_clks, sizeof(*dsi->clks), 1658 GFP_KERNEL); 1659 if (!dsi->clks) 1660 return -ENOMEM; 1661 1662 for (i = 0; i < dsi->driver_data->num_clks; i++) { 1663 dsi->clks[i] = devm_clk_get(dev, clk_names[i]); 1664 if (IS_ERR(dsi->clks[i])) { 1665 if (strcmp(clk_names[i], "sclk_mipi") == 0) { 1666 dsi->clks[i] = devm_clk_get(dev, 1667 OLD_SCLK_MIPI_CLK_NAME); 1668 if (!IS_ERR(dsi->clks[i])) 1669 continue; 1670 } 1671 1672 dev_info(dev, "failed to get the clock: %s\n", 1673 clk_names[i]); 1674 return PTR_ERR(dsi->clks[i]); 1675 } 1676 } 1677 1678 dsi->reg_base = devm_platform_ioremap_resource(pdev, 0); 1679 if (IS_ERR(dsi->reg_base)) 1680 return PTR_ERR(dsi->reg_base); 1681 1682 dsi->phy = devm_phy_get(dev, "dsim"); 1683 if (IS_ERR(dsi->phy)) { 1684 dev_info(dev, "failed to get dsim phy\n"); 1685 return PTR_ERR(dsi->phy); 1686 } 1687 1688 dsi->irq = platform_get_irq(pdev, 0); 1689 if (dsi->irq < 0) 1690 return dsi->irq; 1691 1692 ret = devm_request_threaded_irq(dev, dsi->irq, NULL, 1693 exynos_dsi_irq, 1694 IRQF_ONESHOT | IRQF_NO_AUTOEN, 1695 dev_name(dev), dsi); 1696 if (ret) { 1697 dev_err(dev, "failed to request dsi irq\n"); 1698 return ret; 1699 } 1700 1701 ret = exynos_dsi_parse_dt(dsi); 1702 if (ret) 1703 return ret; 1704 1705 platform_set_drvdata(pdev, dsi); 1706 1707 pm_runtime_enable(dev); 1708 1709 dsi->bridge.funcs = &exynos_dsi_bridge_funcs; 1710 dsi->bridge.of_node = dev->of_node; 1711 dsi->bridge.type = DRM_MODE_CONNECTOR_DSI; 1712 1713 ret = component_add(dev, &exynos_dsi_component_ops); 1714 if (ret) 1715 goto err_disable_runtime; 1716 1717 return 0; 1718 1719 err_disable_runtime: 1720 pm_runtime_disable(dev); 1721 1722 return ret; 1723 } 1724 1725 static int exynos_dsi_remove(struct platform_device *pdev) 1726 { 1727 pm_runtime_disable(&pdev->dev); 1728 1729 component_del(&pdev->dev, &exynos_dsi_component_ops); 1730 1731 return 0; 1732 } 1733 1734 static int __maybe_unused exynos_dsi_suspend(struct device *dev) 1735 { 1736 struct exynos_dsi *dsi = dev_get_drvdata(dev); 1737 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 1738 int ret, i; 1739 1740 usleep_range(10000, 20000); 1741 1742 if (dsi->state & DSIM_STATE_INITIALIZED) { 1743 dsi->state &= ~DSIM_STATE_INITIALIZED; 1744 1745 exynos_dsi_disable_clock(dsi); 1746 1747 exynos_dsi_disable_irq(dsi); 1748 } 1749 1750 dsi->state &= ~DSIM_STATE_CMD_LPM; 1751 1752 phy_power_off(dsi->phy); 1753 1754 for (i = driver_data->num_clks - 1; i > -1; i--) 1755 clk_disable_unprepare(dsi->clks[i]); 1756 1757 ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 1758 if (ret < 0) 1759 dev_err(dsi->dev, "cannot disable regulators %d\n", ret); 1760 1761 return 0; 1762 } 1763 1764 static int __maybe_unused exynos_dsi_resume(struct device *dev) 1765 { 1766 struct exynos_dsi *dsi = dev_get_drvdata(dev); 1767 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 1768 int ret, i; 1769 1770 ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 1771 if (ret < 0) { 1772 dev_err(dsi->dev, "cannot enable regulators %d\n", ret); 1773 return ret; 1774 } 1775 1776 for (i = 0; i < driver_data->num_clks; i++) { 1777 ret = clk_prepare_enable(dsi->clks[i]); 1778 if (ret < 0) 1779 goto err_clk; 1780 } 1781 1782 ret = phy_power_on(dsi->phy); 1783 if (ret < 0) { 1784 dev_err(dsi->dev, "cannot enable phy %d\n", ret); 1785 goto err_clk; 1786 } 1787 1788 return 0; 1789 1790 err_clk: 1791 while (--i > -1) 1792 clk_disable_unprepare(dsi->clks[i]); 1793 regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 1794 1795 return ret; 1796 } 1797 1798 static const struct dev_pm_ops exynos_dsi_pm_ops = { 1799 SET_RUNTIME_PM_OPS(exynos_dsi_suspend, exynos_dsi_resume, NULL) 1800 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1801 pm_runtime_force_resume) 1802 }; 1803 1804 struct platform_driver dsi_driver = { 1805 .probe = exynos_dsi_probe, 1806 .remove = exynos_dsi_remove, 1807 .driver = { 1808 .name = "exynos-dsi", 1809 .owner = THIS_MODULE, 1810 .pm = &exynos_dsi_pm_ops, 1811 .of_match_table = exynos_dsi_of_match, 1812 }, 1813 }; 1814 1815 MODULE_AUTHOR("Tomasz Figa <t.figa@samsung.com>"); 1816 MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>"); 1817 MODULE_DESCRIPTION("Samsung SoC MIPI DSI Master"); 1818 MODULE_LICENSE("GPL v2"); 1819