1 /* 2 * Samsung SoC MIPI DSI Master driver. 3 * 4 * Copyright (c) 2014 Samsung Electronics Co., Ltd 5 * 6 * Contacts: Tomasz Figa <t.figa@samsung.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <drm/drmP.h> 14 #include <drm/drm_crtc_helper.h> 15 #include <drm/drm_mipi_dsi.h> 16 #include <drm/drm_panel.h> 17 #include <drm/drm_atomic_helper.h> 18 19 #include <linux/clk.h> 20 #include <linux/gpio/consumer.h> 21 #include <linux/irq.h> 22 #include <linux/of_device.h> 23 #include <linux/of_gpio.h> 24 #include <linux/of_graph.h> 25 #include <linux/phy/phy.h> 26 #include <linux/regulator/consumer.h> 27 #include <linux/component.h> 28 29 #include <video/mipi_display.h> 30 #include <video/videomode.h> 31 32 #include "exynos_drm_crtc.h" 33 #include "exynos_drm_drv.h" 34 35 /* returns true iff both arguments logically differs */ 36 #define NEQV(a, b) (!(a) ^ !(b)) 37 38 /* DSIM_STATUS */ 39 #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0) 40 #define DSIM_STOP_STATE_CLK (1 << 8) 41 #define DSIM_TX_READY_HS_CLK (1 << 10) 42 #define DSIM_PLL_STABLE (1 << 31) 43 44 /* DSIM_SWRST */ 45 #define DSIM_FUNCRST (1 << 16) 46 #define DSIM_SWRST (1 << 0) 47 48 /* DSIM_TIMEOUT */ 49 #define DSIM_LPDR_TIMEOUT(x) ((x) << 0) 50 #define DSIM_BTA_TIMEOUT(x) ((x) << 16) 51 52 /* DSIM_CLKCTRL */ 53 #define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << 0) 54 #define DSIM_ESC_PRESCALER_MASK (0xffff << 0) 55 #define DSIM_LANE_ESC_CLK_EN_CLK (1 << 19) 56 #define DSIM_LANE_ESC_CLK_EN_DATA(x) (((x) & 0xf) << 20) 57 #define DSIM_LANE_ESC_CLK_EN_DATA_MASK (0xf << 20) 58 #define DSIM_BYTE_CLKEN (1 << 24) 59 #define DSIM_BYTE_CLK_SRC(x) (((x) & 0x3) << 25) 60 #define DSIM_BYTE_CLK_SRC_MASK (0x3 << 25) 61 #define DSIM_PLL_BYPASS (1 << 27) 62 #define DSIM_ESC_CLKEN (1 << 28) 63 #define DSIM_TX_REQUEST_HSCLK (1 << 31) 64 65 /* DSIM_CONFIG */ 66 #define DSIM_LANE_EN_CLK (1 << 0) 67 #define DSIM_LANE_EN(x) (((x) & 0xf) << 1) 68 #define DSIM_NUM_OF_DATA_LANE(x) (((x) & 0x3) << 5) 69 #define DSIM_SUB_PIX_FORMAT(x) (((x) & 0x7) << 8) 70 #define DSIM_MAIN_PIX_FORMAT_MASK (0x7 << 12) 71 #define DSIM_MAIN_PIX_FORMAT_RGB888 (0x7 << 12) 72 #define DSIM_MAIN_PIX_FORMAT_RGB666 (0x6 << 12) 73 #define DSIM_MAIN_PIX_FORMAT_RGB666_P (0x5 << 12) 74 #define DSIM_MAIN_PIX_FORMAT_RGB565 (0x4 << 12) 75 #define DSIM_SUB_VC (((x) & 0x3) << 16) 76 #define DSIM_MAIN_VC (((x) & 0x3) << 18) 77 #define DSIM_HSA_MODE (1 << 20) 78 #define DSIM_HBP_MODE (1 << 21) 79 #define DSIM_HFP_MODE (1 << 22) 80 #define DSIM_HSE_MODE (1 << 23) 81 #define DSIM_AUTO_MODE (1 << 24) 82 #define DSIM_VIDEO_MODE (1 << 25) 83 #define DSIM_BURST_MODE (1 << 26) 84 #define DSIM_SYNC_INFORM (1 << 27) 85 #define DSIM_EOT_DISABLE (1 << 28) 86 #define DSIM_MFLUSH_VS (1 << 29) 87 /* This flag is valid only for exynos3250/3472/4415/5260/5430 */ 88 #define DSIM_CLKLANE_STOP (1 << 30) 89 90 /* DSIM_ESCMODE */ 91 #define DSIM_TX_TRIGGER_RST (1 << 4) 92 #define DSIM_TX_LPDT_LP (1 << 6) 93 #define DSIM_CMD_LPDT_LP (1 << 7) 94 #define DSIM_FORCE_BTA (1 << 16) 95 #define DSIM_FORCE_STOP_STATE (1 << 20) 96 #define DSIM_STOP_STATE_CNT(x) (((x) & 0x7ff) << 21) 97 #define DSIM_STOP_STATE_CNT_MASK (0x7ff << 21) 98 99 /* DSIM_MDRESOL */ 100 #define DSIM_MAIN_STAND_BY (1 << 31) 101 #define DSIM_MAIN_VRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 16) 102 #define DSIM_MAIN_HRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 0) 103 104 /* DSIM_MVPORCH */ 105 #define DSIM_CMD_ALLOW(x) ((x) << 28) 106 #define DSIM_STABLE_VFP(x) ((x) << 16) 107 #define DSIM_MAIN_VBP(x) ((x) << 0) 108 #define DSIM_CMD_ALLOW_MASK (0xf << 28) 109 #define DSIM_STABLE_VFP_MASK (0x7ff << 16) 110 #define DSIM_MAIN_VBP_MASK (0x7ff << 0) 111 112 /* DSIM_MHPORCH */ 113 #define DSIM_MAIN_HFP(x) ((x) << 16) 114 #define DSIM_MAIN_HBP(x) ((x) << 0) 115 #define DSIM_MAIN_HFP_MASK ((0xffff) << 16) 116 #define DSIM_MAIN_HBP_MASK ((0xffff) << 0) 117 118 /* DSIM_MSYNC */ 119 #define DSIM_MAIN_VSA(x) ((x) << 22) 120 #define DSIM_MAIN_HSA(x) ((x) << 0) 121 #define DSIM_MAIN_VSA_MASK ((0x3ff) << 22) 122 #define DSIM_MAIN_HSA_MASK ((0xffff) << 0) 123 124 /* DSIM_SDRESOL */ 125 #define DSIM_SUB_STANDY(x) ((x) << 31) 126 #define DSIM_SUB_VRESOL(x) ((x) << 16) 127 #define DSIM_SUB_HRESOL(x) ((x) << 0) 128 #define DSIM_SUB_STANDY_MASK ((0x1) << 31) 129 #define DSIM_SUB_VRESOL_MASK ((0x7ff) << 16) 130 #define DSIM_SUB_HRESOL_MASK ((0x7ff) << 0) 131 132 /* DSIM_INTSRC */ 133 #define DSIM_INT_PLL_STABLE (1 << 31) 134 #define DSIM_INT_SW_RST_RELEASE (1 << 30) 135 #define DSIM_INT_SFR_FIFO_EMPTY (1 << 29) 136 #define DSIM_INT_SFR_HDR_FIFO_EMPTY (1 << 28) 137 #define DSIM_INT_BTA (1 << 25) 138 #define DSIM_INT_FRAME_DONE (1 << 24) 139 #define DSIM_INT_RX_TIMEOUT (1 << 21) 140 #define DSIM_INT_BTA_TIMEOUT (1 << 20) 141 #define DSIM_INT_RX_DONE (1 << 18) 142 #define DSIM_INT_RX_TE (1 << 17) 143 #define DSIM_INT_RX_ACK (1 << 16) 144 #define DSIM_INT_RX_ECC_ERR (1 << 15) 145 #define DSIM_INT_RX_CRC_ERR (1 << 14) 146 147 /* DSIM_FIFOCTRL */ 148 #define DSIM_RX_DATA_FULL (1 << 25) 149 #define DSIM_RX_DATA_EMPTY (1 << 24) 150 #define DSIM_SFR_HEADER_FULL (1 << 23) 151 #define DSIM_SFR_HEADER_EMPTY (1 << 22) 152 #define DSIM_SFR_PAYLOAD_FULL (1 << 21) 153 #define DSIM_SFR_PAYLOAD_EMPTY (1 << 20) 154 #define DSIM_I80_HEADER_FULL (1 << 19) 155 #define DSIM_I80_HEADER_EMPTY (1 << 18) 156 #define DSIM_I80_PAYLOAD_FULL (1 << 17) 157 #define DSIM_I80_PAYLOAD_EMPTY (1 << 16) 158 #define DSIM_SD_HEADER_FULL (1 << 15) 159 #define DSIM_SD_HEADER_EMPTY (1 << 14) 160 #define DSIM_SD_PAYLOAD_FULL (1 << 13) 161 #define DSIM_SD_PAYLOAD_EMPTY (1 << 12) 162 #define DSIM_MD_HEADER_FULL (1 << 11) 163 #define DSIM_MD_HEADER_EMPTY (1 << 10) 164 #define DSIM_MD_PAYLOAD_FULL (1 << 9) 165 #define DSIM_MD_PAYLOAD_EMPTY (1 << 8) 166 #define DSIM_RX_FIFO (1 << 4) 167 #define DSIM_SFR_FIFO (1 << 3) 168 #define DSIM_I80_FIFO (1 << 2) 169 #define DSIM_SD_FIFO (1 << 1) 170 #define DSIM_MD_FIFO (1 << 0) 171 172 /* DSIM_PHYACCHR */ 173 #define DSIM_AFC_EN (1 << 14) 174 #define DSIM_AFC_CTL(x) (((x) & 0x7) << 5) 175 176 /* DSIM_PLLCTRL */ 177 #define DSIM_FREQ_BAND(x) ((x) << 24) 178 #define DSIM_PLL_EN (1 << 23) 179 #define DSIM_PLL_P(x) ((x) << 13) 180 #define DSIM_PLL_M(x) ((x) << 4) 181 #define DSIM_PLL_S(x) ((x) << 1) 182 183 /* DSIM_PHYCTRL */ 184 #define DSIM_PHYCTRL_ULPS_EXIT(x) (((x) & 0x1ff) << 0) 185 #define DSIM_PHYCTRL_B_DPHYCTL_VREG_LP (1 << 30) 186 #define DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP (1 << 14) 187 188 /* DSIM_PHYTIMING */ 189 #define DSIM_PHYTIMING_LPX(x) ((x) << 8) 190 #define DSIM_PHYTIMING_HS_EXIT(x) ((x) << 0) 191 192 /* DSIM_PHYTIMING1 */ 193 #define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24) 194 #define DSIM_PHYTIMING1_CLK_ZERO(x) ((x) << 16) 195 #define DSIM_PHYTIMING1_CLK_POST(x) ((x) << 8) 196 #define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) << 0) 197 198 /* DSIM_PHYTIMING2 */ 199 #define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) << 16) 200 #define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8) 201 #define DSIM_PHYTIMING2_HS_TRAIL(x) ((x) << 0) 202 203 #define DSI_MAX_BUS_WIDTH 4 204 #define DSI_NUM_VIRTUAL_CHANNELS 4 205 #define DSI_TX_FIFO_SIZE 2048 206 #define DSI_RX_FIFO_SIZE 256 207 #define DSI_XFER_TIMEOUT_MS 100 208 #define DSI_RX_FIFO_EMPTY 0x30800002 209 210 #define OLD_SCLK_MIPI_CLK_NAME "pll_clk" 211 212 #define REG_ADDR(dsi, reg_idx) ((dsi)->reg_base + \ 213 dsi->driver_data->reg_ofs[(reg_idx)]) 214 #define DSI_WRITE(dsi, reg_idx, val) writel((val), \ 215 REG_ADDR((dsi), (reg_idx))) 216 #define DSI_READ(dsi, reg_idx) readl(REG_ADDR((dsi), (reg_idx))) 217 218 static char *clk_names[5] = { "bus_clk", "sclk_mipi", 219 "phyclk_mipidphy0_bitclkdiv8", "phyclk_mipidphy0_rxclkesc0", 220 "sclk_rgb_vclk_to_dsim0" }; 221 222 enum exynos_dsi_transfer_type { 223 EXYNOS_DSI_TX, 224 EXYNOS_DSI_RX, 225 }; 226 227 struct exynos_dsi_transfer { 228 struct list_head list; 229 struct completion completed; 230 int result; 231 u8 data_id; 232 u8 data[2]; 233 u16 flags; 234 235 const u8 *tx_payload; 236 u16 tx_len; 237 u16 tx_done; 238 239 u8 *rx_payload; 240 u16 rx_len; 241 u16 rx_done; 242 }; 243 244 #define DSIM_STATE_ENABLED BIT(0) 245 #define DSIM_STATE_INITIALIZED BIT(1) 246 #define DSIM_STATE_CMD_LPM BIT(2) 247 #define DSIM_STATE_VIDOUT_AVAILABLE BIT(3) 248 249 struct exynos_dsi_driver_data { 250 unsigned int *reg_ofs; 251 unsigned int plltmr_reg; 252 unsigned int has_freqband:1; 253 unsigned int has_clklane_stop:1; 254 unsigned int num_clks; 255 unsigned int max_freq; 256 unsigned int wait_for_reset; 257 unsigned int num_bits_resol; 258 unsigned int *reg_values; 259 }; 260 261 struct exynos_dsi { 262 struct drm_encoder encoder; 263 struct mipi_dsi_host dsi_host; 264 struct drm_connector connector; 265 struct device_node *panel_node; 266 struct drm_panel *panel; 267 struct device *dev; 268 269 void __iomem *reg_base; 270 struct phy *phy; 271 struct clk **clks; 272 struct regulator_bulk_data supplies[2]; 273 int irq; 274 int te_gpio; 275 276 u32 pll_clk_rate; 277 u32 burst_clk_rate; 278 u32 esc_clk_rate; 279 u32 lanes; 280 u32 mode_flags; 281 u32 format; 282 struct videomode vm; 283 284 int state; 285 struct drm_property *brightness; 286 struct completion completed; 287 288 spinlock_t transfer_lock; /* protects transfer_list */ 289 struct list_head transfer_list; 290 291 struct exynos_dsi_driver_data *driver_data; 292 struct device_node *bridge_node; 293 }; 294 295 #define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host) 296 #define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector) 297 298 static inline struct exynos_dsi *encoder_to_dsi(struct drm_encoder *e) 299 { 300 return container_of(e, struct exynos_dsi, encoder); 301 } 302 303 enum reg_idx { 304 DSIM_STATUS_REG, /* Status register */ 305 DSIM_SWRST_REG, /* Software reset register */ 306 DSIM_CLKCTRL_REG, /* Clock control register */ 307 DSIM_TIMEOUT_REG, /* Time out register */ 308 DSIM_CONFIG_REG, /* Configuration register */ 309 DSIM_ESCMODE_REG, /* Escape mode register */ 310 DSIM_MDRESOL_REG, 311 DSIM_MVPORCH_REG, /* Main display Vporch register */ 312 DSIM_MHPORCH_REG, /* Main display Hporch register */ 313 DSIM_MSYNC_REG, /* Main display sync area register */ 314 DSIM_INTSRC_REG, /* Interrupt source register */ 315 DSIM_INTMSK_REG, /* Interrupt mask register */ 316 DSIM_PKTHDR_REG, /* Packet Header FIFO register */ 317 DSIM_PAYLOAD_REG, /* Payload FIFO register */ 318 DSIM_RXFIFO_REG, /* Read FIFO register */ 319 DSIM_FIFOCTRL_REG, /* FIFO status and control register */ 320 DSIM_PLLCTRL_REG, /* PLL control register */ 321 DSIM_PHYCTRL_REG, 322 DSIM_PHYTIMING_REG, 323 DSIM_PHYTIMING1_REG, 324 DSIM_PHYTIMING2_REG, 325 NUM_REGS 326 }; 327 static unsigned int exynos_reg_ofs[] = { 328 [DSIM_STATUS_REG] = 0x00, 329 [DSIM_SWRST_REG] = 0x04, 330 [DSIM_CLKCTRL_REG] = 0x08, 331 [DSIM_TIMEOUT_REG] = 0x0c, 332 [DSIM_CONFIG_REG] = 0x10, 333 [DSIM_ESCMODE_REG] = 0x14, 334 [DSIM_MDRESOL_REG] = 0x18, 335 [DSIM_MVPORCH_REG] = 0x1c, 336 [DSIM_MHPORCH_REG] = 0x20, 337 [DSIM_MSYNC_REG] = 0x24, 338 [DSIM_INTSRC_REG] = 0x2c, 339 [DSIM_INTMSK_REG] = 0x30, 340 [DSIM_PKTHDR_REG] = 0x34, 341 [DSIM_PAYLOAD_REG] = 0x38, 342 [DSIM_RXFIFO_REG] = 0x3c, 343 [DSIM_FIFOCTRL_REG] = 0x44, 344 [DSIM_PLLCTRL_REG] = 0x4c, 345 [DSIM_PHYCTRL_REG] = 0x5c, 346 [DSIM_PHYTIMING_REG] = 0x64, 347 [DSIM_PHYTIMING1_REG] = 0x68, 348 [DSIM_PHYTIMING2_REG] = 0x6c, 349 }; 350 351 static unsigned int exynos5433_reg_ofs[] = { 352 [DSIM_STATUS_REG] = 0x04, 353 [DSIM_SWRST_REG] = 0x0C, 354 [DSIM_CLKCTRL_REG] = 0x10, 355 [DSIM_TIMEOUT_REG] = 0x14, 356 [DSIM_CONFIG_REG] = 0x18, 357 [DSIM_ESCMODE_REG] = 0x1C, 358 [DSIM_MDRESOL_REG] = 0x20, 359 [DSIM_MVPORCH_REG] = 0x24, 360 [DSIM_MHPORCH_REG] = 0x28, 361 [DSIM_MSYNC_REG] = 0x2C, 362 [DSIM_INTSRC_REG] = 0x34, 363 [DSIM_INTMSK_REG] = 0x38, 364 [DSIM_PKTHDR_REG] = 0x3C, 365 [DSIM_PAYLOAD_REG] = 0x40, 366 [DSIM_RXFIFO_REG] = 0x44, 367 [DSIM_FIFOCTRL_REG] = 0x4C, 368 [DSIM_PLLCTRL_REG] = 0x94, 369 [DSIM_PHYCTRL_REG] = 0xA4, 370 [DSIM_PHYTIMING_REG] = 0xB4, 371 [DSIM_PHYTIMING1_REG] = 0xB8, 372 [DSIM_PHYTIMING2_REG] = 0xBC, 373 }; 374 375 enum reg_value_idx { 376 RESET_TYPE, 377 PLL_TIMER, 378 STOP_STATE_CNT, 379 PHYCTRL_ULPS_EXIT, 380 PHYCTRL_VREG_LP, 381 PHYCTRL_SLEW_UP, 382 PHYTIMING_LPX, 383 PHYTIMING_HS_EXIT, 384 PHYTIMING_CLK_PREPARE, 385 PHYTIMING_CLK_ZERO, 386 PHYTIMING_CLK_POST, 387 PHYTIMING_CLK_TRAIL, 388 PHYTIMING_HS_PREPARE, 389 PHYTIMING_HS_ZERO, 390 PHYTIMING_HS_TRAIL 391 }; 392 393 static unsigned int reg_values[] = { 394 [RESET_TYPE] = DSIM_SWRST, 395 [PLL_TIMER] = 500, 396 [STOP_STATE_CNT] = 0xf, 397 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af), 398 [PHYCTRL_VREG_LP] = 0, 399 [PHYCTRL_SLEW_UP] = 0, 400 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06), 401 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b), 402 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07), 403 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27), 404 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d), 405 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08), 406 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09), 407 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d), 408 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b), 409 }; 410 411 static unsigned int exynos5433_reg_values[] = { 412 [RESET_TYPE] = DSIM_FUNCRST, 413 [PLL_TIMER] = 22200, 414 [STOP_STATE_CNT] = 0xa, 415 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x190), 416 [PHYCTRL_VREG_LP] = DSIM_PHYCTRL_B_DPHYCTL_VREG_LP, 417 [PHYCTRL_SLEW_UP] = DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP, 418 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07), 419 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c), 420 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09), 421 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2d), 422 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e), 423 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09), 424 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0b), 425 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x10), 426 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c), 427 }; 428 429 static struct exynos_dsi_driver_data exynos3_dsi_driver_data = { 430 .reg_ofs = exynos_reg_ofs, 431 .plltmr_reg = 0x50, 432 .has_freqband = 1, 433 .has_clklane_stop = 1, 434 .num_clks = 2, 435 .max_freq = 1000, 436 .wait_for_reset = 1, 437 .num_bits_resol = 11, 438 .reg_values = reg_values, 439 }; 440 441 static struct exynos_dsi_driver_data exynos4_dsi_driver_data = { 442 .reg_ofs = exynos_reg_ofs, 443 .plltmr_reg = 0x50, 444 .has_freqband = 1, 445 .has_clklane_stop = 1, 446 .num_clks = 2, 447 .max_freq = 1000, 448 .wait_for_reset = 1, 449 .num_bits_resol = 11, 450 .reg_values = reg_values, 451 }; 452 453 static struct exynos_dsi_driver_data exynos4415_dsi_driver_data = { 454 .reg_ofs = exynos_reg_ofs, 455 .plltmr_reg = 0x58, 456 .has_clklane_stop = 1, 457 .num_clks = 2, 458 .max_freq = 1000, 459 .wait_for_reset = 1, 460 .num_bits_resol = 11, 461 .reg_values = reg_values, 462 }; 463 464 static struct exynos_dsi_driver_data exynos5_dsi_driver_data = { 465 .reg_ofs = exynos_reg_ofs, 466 .plltmr_reg = 0x58, 467 .num_clks = 2, 468 .max_freq = 1000, 469 .wait_for_reset = 1, 470 .num_bits_resol = 11, 471 .reg_values = reg_values, 472 }; 473 474 static struct exynos_dsi_driver_data exynos5433_dsi_driver_data = { 475 .reg_ofs = exynos5433_reg_ofs, 476 .plltmr_reg = 0xa0, 477 .has_clklane_stop = 1, 478 .num_clks = 5, 479 .max_freq = 1500, 480 .wait_for_reset = 0, 481 .num_bits_resol = 12, 482 .reg_values = exynos5433_reg_values, 483 }; 484 485 static struct of_device_id exynos_dsi_of_match[] = { 486 { .compatible = "samsung,exynos3250-mipi-dsi", 487 .data = &exynos3_dsi_driver_data }, 488 { .compatible = "samsung,exynos4210-mipi-dsi", 489 .data = &exynos4_dsi_driver_data }, 490 { .compatible = "samsung,exynos4415-mipi-dsi", 491 .data = &exynos4415_dsi_driver_data }, 492 { .compatible = "samsung,exynos5410-mipi-dsi", 493 .data = &exynos5_dsi_driver_data }, 494 { .compatible = "samsung,exynos5433-mipi-dsi", 495 .data = &exynos5433_dsi_driver_data }, 496 { } 497 }; 498 499 static inline struct exynos_dsi_driver_data *exynos_dsi_get_driver_data( 500 struct platform_device *pdev) 501 { 502 const struct of_device_id *of_id = 503 of_match_device(exynos_dsi_of_match, &pdev->dev); 504 505 return (struct exynos_dsi_driver_data *)of_id->data; 506 } 507 508 static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi) 509 { 510 if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300))) 511 return; 512 513 dev_err(dsi->dev, "timeout waiting for reset\n"); 514 } 515 516 static void exynos_dsi_reset(struct exynos_dsi *dsi) 517 { 518 struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 519 520 reinit_completion(&dsi->completed); 521 DSI_WRITE(dsi, DSIM_SWRST_REG, driver_data->reg_values[RESET_TYPE]); 522 } 523 524 #ifndef MHZ 525 #define MHZ (1000*1000) 526 #endif 527 528 static unsigned long exynos_dsi_pll_find_pms(struct exynos_dsi *dsi, 529 unsigned long fin, unsigned long fout, u8 *p, u16 *m, u8 *s) 530 { 531 struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 532 unsigned long best_freq = 0; 533 u32 min_delta = 0xffffffff; 534 u8 p_min, p_max; 535 u8 _p, uninitialized_var(best_p); 536 u16 _m, uninitialized_var(best_m); 537 u8 _s, uninitialized_var(best_s); 538 539 p_min = DIV_ROUND_UP(fin, (12 * MHZ)); 540 p_max = fin / (6 * MHZ); 541 542 for (_p = p_min; _p <= p_max; ++_p) { 543 for (_s = 0; _s <= 5; ++_s) { 544 u64 tmp; 545 u32 delta; 546 547 tmp = (u64)fout * (_p << _s); 548 do_div(tmp, fin); 549 _m = tmp; 550 if (_m < 41 || _m > 125) 551 continue; 552 553 tmp = (u64)_m * fin; 554 do_div(tmp, _p); 555 if (tmp < 500 * MHZ || 556 tmp > driver_data->max_freq * MHZ) 557 continue; 558 559 tmp = (u64)_m * fin; 560 do_div(tmp, _p << _s); 561 562 delta = abs(fout - tmp); 563 if (delta < min_delta) { 564 best_p = _p; 565 best_m = _m; 566 best_s = _s; 567 min_delta = delta; 568 best_freq = tmp; 569 } 570 } 571 } 572 573 if (best_freq) { 574 *p = best_p; 575 *m = best_m; 576 *s = best_s; 577 } 578 579 return best_freq; 580 } 581 582 static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi, 583 unsigned long freq) 584 { 585 struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 586 unsigned long fin, fout; 587 int timeout; 588 u8 p, s; 589 u16 m; 590 u32 reg; 591 592 fin = dsi->pll_clk_rate; 593 fout = exynos_dsi_pll_find_pms(dsi, fin, freq, &p, &m, &s); 594 if (!fout) { 595 dev_err(dsi->dev, 596 "failed to find PLL PMS for requested frequency\n"); 597 return 0; 598 } 599 dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s); 600 601 writel(driver_data->reg_values[PLL_TIMER], 602 dsi->reg_base + driver_data->plltmr_reg); 603 604 reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s); 605 606 if (driver_data->has_freqband) { 607 static const unsigned long freq_bands[] = { 608 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ, 609 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ, 610 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ, 611 770 * MHZ, 870 * MHZ, 950 * MHZ, 612 }; 613 int band; 614 615 for (band = 0; band < ARRAY_SIZE(freq_bands); ++band) 616 if (fout < freq_bands[band]) 617 break; 618 619 dev_dbg(dsi->dev, "band %d\n", band); 620 621 reg |= DSIM_FREQ_BAND(band); 622 } 623 624 DSI_WRITE(dsi, DSIM_PLLCTRL_REG, reg); 625 626 timeout = 1000; 627 do { 628 if (timeout-- == 0) { 629 dev_err(dsi->dev, "PLL failed to stabilize\n"); 630 return 0; 631 } 632 reg = DSI_READ(dsi, DSIM_STATUS_REG); 633 } while ((reg & DSIM_PLL_STABLE) == 0); 634 635 return fout; 636 } 637 638 static int exynos_dsi_enable_clock(struct exynos_dsi *dsi) 639 { 640 unsigned long hs_clk, byte_clk, esc_clk; 641 unsigned long esc_div; 642 u32 reg; 643 644 hs_clk = exynos_dsi_set_pll(dsi, dsi->burst_clk_rate); 645 if (!hs_clk) { 646 dev_err(dsi->dev, "failed to configure DSI PLL\n"); 647 return -EFAULT; 648 } 649 650 byte_clk = hs_clk / 8; 651 esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate); 652 esc_clk = byte_clk / esc_div; 653 654 if (esc_clk > 20 * MHZ) { 655 ++esc_div; 656 esc_clk = byte_clk / esc_div; 657 } 658 659 dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n", 660 hs_clk, byte_clk, esc_clk); 661 662 reg = DSI_READ(dsi, DSIM_CLKCTRL_REG); 663 reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK 664 | DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS 665 | DSIM_BYTE_CLK_SRC_MASK); 666 reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN 667 | DSIM_ESC_PRESCALER(esc_div) 668 | DSIM_LANE_ESC_CLK_EN_CLK 669 | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1) 670 | DSIM_BYTE_CLK_SRC(0) 671 | DSIM_TX_REQUEST_HSCLK; 672 DSI_WRITE(dsi, DSIM_CLKCTRL_REG, reg); 673 674 return 0; 675 } 676 677 static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi) 678 { 679 struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 680 unsigned int *reg_values = driver_data->reg_values; 681 u32 reg; 682 683 if (driver_data->has_freqband) 684 return; 685 686 /* B D-PHY: D-PHY Master & Slave Analog Block control */ 687 reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] | 688 reg_values[PHYCTRL_SLEW_UP]; 689 DSI_WRITE(dsi, DSIM_PHYCTRL_REG, reg); 690 691 /* 692 * T LPX: Transmitted length of any Low-Power state period 693 * T HS-EXIT: Time that the transmitter drives LP-11 following a HS 694 * burst 695 */ 696 reg = reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT]; 697 DSI_WRITE(dsi, DSIM_PHYTIMING_REG, reg); 698 699 /* 700 * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00 701 * Line state immediately before the HS-0 Line state starting the 702 * HS transmission 703 * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to 704 * transmitting the Clock. 705 * T CLK_POST: Time that the transmitter continues to send HS clock 706 * after the last associated Data Lane has transitioned to LP Mode 707 * Interval is defined as the period from the end of T HS-TRAIL to 708 * the beginning of T CLK-TRAIL 709 * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after 710 * the last payload clock bit of a HS transmission burst 711 */ 712 reg = reg_values[PHYTIMING_CLK_PREPARE] | 713 reg_values[PHYTIMING_CLK_ZERO] | 714 reg_values[PHYTIMING_CLK_POST] | 715 reg_values[PHYTIMING_CLK_TRAIL]; 716 717 DSI_WRITE(dsi, DSIM_PHYTIMING1_REG, reg); 718 719 /* 720 * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00 721 * Line state immediately before the HS-0 Line state starting the 722 * HS transmission 723 * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to 724 * transmitting the Sync sequence. 725 * T HS-TRAIL: Time that the transmitter drives the flipped differential 726 * state after last payload data bit of a HS transmission burst 727 */ 728 reg = reg_values[PHYTIMING_HS_PREPARE] | reg_values[PHYTIMING_HS_ZERO] | 729 reg_values[PHYTIMING_HS_TRAIL]; 730 DSI_WRITE(dsi, DSIM_PHYTIMING2_REG, reg); 731 } 732 733 static void exynos_dsi_disable_clock(struct exynos_dsi *dsi) 734 { 735 u32 reg; 736 737 reg = DSI_READ(dsi, DSIM_CLKCTRL_REG); 738 reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK 739 | DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN); 740 DSI_WRITE(dsi, DSIM_CLKCTRL_REG, reg); 741 742 reg = DSI_READ(dsi, DSIM_PLLCTRL_REG); 743 reg &= ~DSIM_PLL_EN; 744 DSI_WRITE(dsi, DSIM_PLLCTRL_REG, reg); 745 } 746 747 static void exynos_dsi_enable_lane(struct exynos_dsi *dsi, u32 lane) 748 { 749 u32 reg = DSI_READ(dsi, DSIM_CONFIG_REG); 750 reg |= (DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1) | DSIM_LANE_EN_CLK | 751 DSIM_LANE_EN(lane)); 752 DSI_WRITE(dsi, DSIM_CONFIG_REG, reg); 753 } 754 755 static int exynos_dsi_init_link(struct exynos_dsi *dsi) 756 { 757 struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 758 int timeout; 759 u32 reg; 760 u32 lanes_mask; 761 762 /* Initialize FIFO pointers */ 763 reg = DSI_READ(dsi, DSIM_FIFOCTRL_REG); 764 reg &= ~0x1f; 765 DSI_WRITE(dsi, DSIM_FIFOCTRL_REG, reg); 766 767 usleep_range(9000, 11000); 768 769 reg |= 0x1f; 770 DSI_WRITE(dsi, DSIM_FIFOCTRL_REG, reg); 771 usleep_range(9000, 11000); 772 773 /* DSI configuration */ 774 reg = 0; 775 776 /* 777 * The first bit of mode_flags specifies display configuration. 778 * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video 779 * mode, otherwise it will support command mode. 780 */ 781 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 782 reg |= DSIM_VIDEO_MODE; 783 784 /* 785 * The user manual describes that following bits are ignored in 786 * command mode. 787 */ 788 if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH)) 789 reg |= DSIM_MFLUSH_VS; 790 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 791 reg |= DSIM_SYNC_INFORM; 792 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 793 reg |= DSIM_BURST_MODE; 794 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT) 795 reg |= DSIM_AUTO_MODE; 796 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE) 797 reg |= DSIM_HSE_MODE; 798 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP)) 799 reg |= DSIM_HFP_MODE; 800 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP)) 801 reg |= DSIM_HBP_MODE; 802 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSA)) 803 reg |= DSIM_HSA_MODE; 804 } 805 806 if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET)) 807 reg |= DSIM_EOT_DISABLE; 808 809 switch (dsi->format) { 810 case MIPI_DSI_FMT_RGB888: 811 reg |= DSIM_MAIN_PIX_FORMAT_RGB888; 812 break; 813 case MIPI_DSI_FMT_RGB666: 814 reg |= DSIM_MAIN_PIX_FORMAT_RGB666; 815 break; 816 case MIPI_DSI_FMT_RGB666_PACKED: 817 reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P; 818 break; 819 case MIPI_DSI_FMT_RGB565: 820 reg |= DSIM_MAIN_PIX_FORMAT_RGB565; 821 break; 822 default: 823 dev_err(dsi->dev, "invalid pixel format\n"); 824 return -EINVAL; 825 } 826 827 /* 828 * Use non-continuous clock mode if the periparal wants and 829 * host controller supports 830 * 831 * In non-continous clock mode, host controller will turn off 832 * the HS clock between high-speed transmissions to reduce 833 * power consumption. 834 */ 835 if (driver_data->has_clklane_stop && 836 dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { 837 reg |= DSIM_CLKLANE_STOP; 838 } 839 DSI_WRITE(dsi, DSIM_CONFIG_REG, reg); 840 841 lanes_mask = BIT(dsi->lanes) - 1; 842 exynos_dsi_enable_lane(dsi, lanes_mask); 843 844 /* Check clock and data lane state are stop state */ 845 timeout = 100; 846 do { 847 if (timeout-- == 0) { 848 dev_err(dsi->dev, "waiting for bus lanes timed out\n"); 849 return -EFAULT; 850 } 851 852 reg = DSI_READ(dsi, DSIM_STATUS_REG); 853 if ((reg & DSIM_STOP_STATE_DAT(lanes_mask)) 854 != DSIM_STOP_STATE_DAT(lanes_mask)) 855 continue; 856 } while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK))); 857 858 reg = DSI_READ(dsi, DSIM_ESCMODE_REG); 859 reg &= ~DSIM_STOP_STATE_CNT_MASK; 860 reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]); 861 DSI_WRITE(dsi, DSIM_ESCMODE_REG, reg); 862 863 reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff); 864 DSI_WRITE(dsi, DSIM_TIMEOUT_REG, reg); 865 866 return 0; 867 } 868 869 static void exynos_dsi_set_display_mode(struct exynos_dsi *dsi) 870 { 871 struct videomode *vm = &dsi->vm; 872 unsigned int num_bits_resol = dsi->driver_data->num_bits_resol; 873 u32 reg; 874 875 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 876 reg = DSIM_CMD_ALLOW(0xf) 877 | DSIM_STABLE_VFP(vm->vfront_porch) 878 | DSIM_MAIN_VBP(vm->vback_porch); 879 DSI_WRITE(dsi, DSIM_MVPORCH_REG, reg); 880 881 reg = DSIM_MAIN_HFP(vm->hfront_porch) 882 | DSIM_MAIN_HBP(vm->hback_porch); 883 DSI_WRITE(dsi, DSIM_MHPORCH_REG, reg); 884 885 reg = DSIM_MAIN_VSA(vm->vsync_len) 886 | DSIM_MAIN_HSA(vm->hsync_len); 887 DSI_WRITE(dsi, DSIM_MSYNC_REG, reg); 888 } 889 reg = DSIM_MAIN_HRESOL(vm->hactive, num_bits_resol) | 890 DSIM_MAIN_VRESOL(vm->vactive, num_bits_resol); 891 892 DSI_WRITE(dsi, DSIM_MDRESOL_REG, reg); 893 894 dev_dbg(dsi->dev, "LCD size = %dx%d\n", vm->hactive, vm->vactive); 895 } 896 897 static void exynos_dsi_set_display_enable(struct exynos_dsi *dsi, bool enable) 898 { 899 u32 reg; 900 901 reg = DSI_READ(dsi, DSIM_MDRESOL_REG); 902 if (enable) 903 reg |= DSIM_MAIN_STAND_BY; 904 else 905 reg &= ~DSIM_MAIN_STAND_BY; 906 DSI_WRITE(dsi, DSIM_MDRESOL_REG, reg); 907 } 908 909 static int exynos_dsi_wait_for_hdr_fifo(struct exynos_dsi *dsi) 910 { 911 int timeout = 2000; 912 913 do { 914 u32 reg = DSI_READ(dsi, DSIM_FIFOCTRL_REG); 915 916 if (!(reg & DSIM_SFR_HEADER_FULL)) 917 return 0; 918 919 if (!cond_resched()) 920 usleep_range(950, 1050); 921 } while (--timeout); 922 923 return -ETIMEDOUT; 924 } 925 926 static void exynos_dsi_set_cmd_lpm(struct exynos_dsi *dsi, bool lpm) 927 { 928 u32 v = DSI_READ(dsi, DSIM_ESCMODE_REG); 929 930 if (lpm) 931 v |= DSIM_CMD_LPDT_LP; 932 else 933 v &= ~DSIM_CMD_LPDT_LP; 934 935 DSI_WRITE(dsi, DSIM_ESCMODE_REG, v); 936 } 937 938 static void exynos_dsi_force_bta(struct exynos_dsi *dsi) 939 { 940 u32 v = DSI_READ(dsi, DSIM_ESCMODE_REG); 941 v |= DSIM_FORCE_BTA; 942 DSI_WRITE(dsi, DSIM_ESCMODE_REG, v); 943 } 944 945 static void exynos_dsi_send_to_fifo(struct exynos_dsi *dsi, 946 struct exynos_dsi_transfer *xfer) 947 { 948 struct device *dev = dsi->dev; 949 const u8 *payload = xfer->tx_payload + xfer->tx_done; 950 u16 length = xfer->tx_len - xfer->tx_done; 951 bool first = !xfer->tx_done; 952 u32 reg; 953 954 dev_dbg(dev, "< xfer %p: tx len %u, done %u, rx len %u, done %u\n", 955 xfer, xfer->tx_len, xfer->tx_done, xfer->rx_len, xfer->rx_done); 956 957 if (length > DSI_TX_FIFO_SIZE) 958 length = DSI_TX_FIFO_SIZE; 959 960 xfer->tx_done += length; 961 962 /* Send payload */ 963 while (length >= 4) { 964 reg = (payload[3] << 24) | (payload[2] << 16) 965 | (payload[1] << 8) | payload[0]; 966 DSI_WRITE(dsi, DSIM_PAYLOAD_REG, reg); 967 payload += 4; 968 length -= 4; 969 } 970 971 reg = 0; 972 switch (length) { 973 case 3: 974 reg |= payload[2] << 16; 975 /* Fall through */ 976 case 2: 977 reg |= payload[1] << 8; 978 /* Fall through */ 979 case 1: 980 reg |= payload[0]; 981 DSI_WRITE(dsi, DSIM_PAYLOAD_REG, reg); 982 break; 983 case 0: 984 /* Do nothing */ 985 break; 986 } 987 988 /* Send packet header */ 989 if (!first) 990 return; 991 992 reg = (xfer->data[1] << 16) | (xfer->data[0] << 8) | xfer->data_id; 993 if (exynos_dsi_wait_for_hdr_fifo(dsi)) { 994 dev_err(dev, "waiting for header FIFO timed out\n"); 995 return; 996 } 997 998 if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM, 999 dsi->state & DSIM_STATE_CMD_LPM)) { 1000 exynos_dsi_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM); 1001 dsi->state ^= DSIM_STATE_CMD_LPM; 1002 } 1003 1004 DSI_WRITE(dsi, DSIM_PKTHDR_REG, reg); 1005 1006 if (xfer->flags & MIPI_DSI_MSG_REQ_ACK) 1007 exynos_dsi_force_bta(dsi); 1008 } 1009 1010 static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi, 1011 struct exynos_dsi_transfer *xfer) 1012 { 1013 u8 *payload = xfer->rx_payload + xfer->rx_done; 1014 bool first = !xfer->rx_done; 1015 struct device *dev = dsi->dev; 1016 u16 length; 1017 u32 reg; 1018 1019 if (first) { 1020 reg = DSI_READ(dsi, DSIM_RXFIFO_REG); 1021 1022 switch (reg & 0x3f) { 1023 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 1024 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 1025 if (xfer->rx_len >= 2) { 1026 payload[1] = reg >> 16; 1027 ++xfer->rx_done; 1028 } 1029 /* Fall through */ 1030 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 1031 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 1032 payload[0] = reg >> 8; 1033 ++xfer->rx_done; 1034 xfer->rx_len = xfer->rx_done; 1035 xfer->result = 0; 1036 goto clear_fifo; 1037 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 1038 dev_err(dev, "DSI Error Report: 0x%04x\n", 1039 (reg >> 8) & 0xffff); 1040 xfer->result = 0; 1041 goto clear_fifo; 1042 } 1043 1044 length = (reg >> 8) & 0xffff; 1045 if (length > xfer->rx_len) { 1046 dev_err(dev, 1047 "response too long (%u > %u bytes), stripping\n", 1048 xfer->rx_len, length); 1049 length = xfer->rx_len; 1050 } else if (length < xfer->rx_len) 1051 xfer->rx_len = length; 1052 } 1053 1054 length = xfer->rx_len - xfer->rx_done; 1055 xfer->rx_done += length; 1056 1057 /* Receive payload */ 1058 while (length >= 4) { 1059 reg = DSI_READ(dsi, DSIM_RXFIFO_REG); 1060 payload[0] = (reg >> 0) & 0xff; 1061 payload[1] = (reg >> 8) & 0xff; 1062 payload[2] = (reg >> 16) & 0xff; 1063 payload[3] = (reg >> 24) & 0xff; 1064 payload += 4; 1065 length -= 4; 1066 } 1067 1068 if (length) { 1069 reg = DSI_READ(dsi, DSIM_RXFIFO_REG); 1070 switch (length) { 1071 case 3: 1072 payload[2] = (reg >> 16) & 0xff; 1073 /* Fall through */ 1074 case 2: 1075 payload[1] = (reg >> 8) & 0xff; 1076 /* Fall through */ 1077 case 1: 1078 payload[0] = reg & 0xff; 1079 } 1080 } 1081 1082 if (xfer->rx_done == xfer->rx_len) 1083 xfer->result = 0; 1084 1085 clear_fifo: 1086 length = DSI_RX_FIFO_SIZE / 4; 1087 do { 1088 reg = DSI_READ(dsi, DSIM_RXFIFO_REG); 1089 if (reg == DSI_RX_FIFO_EMPTY) 1090 break; 1091 } while (--length); 1092 } 1093 1094 static void exynos_dsi_transfer_start(struct exynos_dsi *dsi) 1095 { 1096 unsigned long flags; 1097 struct exynos_dsi_transfer *xfer; 1098 bool start = false; 1099 1100 again: 1101 spin_lock_irqsave(&dsi->transfer_lock, flags); 1102 1103 if (list_empty(&dsi->transfer_list)) { 1104 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1105 return; 1106 } 1107 1108 xfer = list_first_entry(&dsi->transfer_list, 1109 struct exynos_dsi_transfer, list); 1110 1111 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1112 1113 if (xfer->tx_len && xfer->tx_done == xfer->tx_len) 1114 /* waiting for RX */ 1115 return; 1116 1117 exynos_dsi_send_to_fifo(dsi, xfer); 1118 1119 if (xfer->tx_len || xfer->rx_len) 1120 return; 1121 1122 xfer->result = 0; 1123 complete(&xfer->completed); 1124 1125 spin_lock_irqsave(&dsi->transfer_lock, flags); 1126 1127 list_del_init(&xfer->list); 1128 start = !list_empty(&dsi->transfer_list); 1129 1130 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1131 1132 if (start) 1133 goto again; 1134 } 1135 1136 static bool exynos_dsi_transfer_finish(struct exynos_dsi *dsi) 1137 { 1138 struct exynos_dsi_transfer *xfer; 1139 unsigned long flags; 1140 bool start = true; 1141 1142 spin_lock_irqsave(&dsi->transfer_lock, flags); 1143 1144 if (list_empty(&dsi->transfer_list)) { 1145 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1146 return false; 1147 } 1148 1149 xfer = list_first_entry(&dsi->transfer_list, 1150 struct exynos_dsi_transfer, list); 1151 1152 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1153 1154 dev_dbg(dsi->dev, 1155 "> xfer %p, tx_len %u, tx_done %u, rx_len %u, rx_done %u\n", 1156 xfer, xfer->tx_len, xfer->tx_done, xfer->rx_len, xfer->rx_done); 1157 1158 if (xfer->tx_done != xfer->tx_len) 1159 return true; 1160 1161 if (xfer->rx_done != xfer->rx_len) 1162 exynos_dsi_read_from_fifo(dsi, xfer); 1163 1164 if (xfer->rx_done != xfer->rx_len) 1165 return true; 1166 1167 spin_lock_irqsave(&dsi->transfer_lock, flags); 1168 1169 list_del_init(&xfer->list); 1170 start = !list_empty(&dsi->transfer_list); 1171 1172 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1173 1174 if (!xfer->rx_len) 1175 xfer->result = 0; 1176 complete(&xfer->completed); 1177 1178 return start; 1179 } 1180 1181 static void exynos_dsi_remove_transfer(struct exynos_dsi *dsi, 1182 struct exynos_dsi_transfer *xfer) 1183 { 1184 unsigned long flags; 1185 bool start; 1186 1187 spin_lock_irqsave(&dsi->transfer_lock, flags); 1188 1189 if (!list_empty(&dsi->transfer_list) && 1190 xfer == list_first_entry(&dsi->transfer_list, 1191 struct exynos_dsi_transfer, list)) { 1192 list_del_init(&xfer->list); 1193 start = !list_empty(&dsi->transfer_list); 1194 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1195 if (start) 1196 exynos_dsi_transfer_start(dsi); 1197 return; 1198 } 1199 1200 list_del_init(&xfer->list); 1201 1202 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1203 } 1204 1205 static int exynos_dsi_transfer(struct exynos_dsi *dsi, 1206 struct exynos_dsi_transfer *xfer) 1207 { 1208 unsigned long flags; 1209 bool stopped; 1210 1211 xfer->tx_done = 0; 1212 xfer->rx_done = 0; 1213 xfer->result = -ETIMEDOUT; 1214 init_completion(&xfer->completed); 1215 1216 spin_lock_irqsave(&dsi->transfer_lock, flags); 1217 1218 stopped = list_empty(&dsi->transfer_list); 1219 list_add_tail(&xfer->list, &dsi->transfer_list); 1220 1221 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1222 1223 if (stopped) 1224 exynos_dsi_transfer_start(dsi); 1225 1226 wait_for_completion_timeout(&xfer->completed, 1227 msecs_to_jiffies(DSI_XFER_TIMEOUT_MS)); 1228 if (xfer->result == -ETIMEDOUT) { 1229 exynos_dsi_remove_transfer(dsi, xfer); 1230 dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 2, xfer->data, 1231 xfer->tx_len, xfer->tx_payload); 1232 return -ETIMEDOUT; 1233 } 1234 1235 /* Also covers hardware timeout condition */ 1236 return xfer->result; 1237 } 1238 1239 static irqreturn_t exynos_dsi_irq(int irq, void *dev_id) 1240 { 1241 struct exynos_dsi *dsi = dev_id; 1242 u32 status; 1243 1244 status = DSI_READ(dsi, DSIM_INTSRC_REG); 1245 if (!status) { 1246 static unsigned long int j; 1247 if (printk_timed_ratelimit(&j, 500)) 1248 dev_warn(dsi->dev, "spurious interrupt\n"); 1249 return IRQ_HANDLED; 1250 } 1251 DSI_WRITE(dsi, DSIM_INTSRC_REG, status); 1252 1253 if (status & DSIM_INT_SW_RST_RELEASE) { 1254 u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY | 1255 DSIM_INT_SFR_HDR_FIFO_EMPTY | DSIM_INT_FRAME_DONE | 1256 DSIM_INT_RX_ECC_ERR | DSIM_INT_SW_RST_RELEASE); 1257 DSI_WRITE(dsi, DSIM_INTMSK_REG, mask); 1258 complete(&dsi->completed); 1259 return IRQ_HANDLED; 1260 } 1261 1262 if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY | 1263 DSIM_INT_FRAME_DONE | DSIM_INT_PLL_STABLE))) 1264 return IRQ_HANDLED; 1265 1266 if (exynos_dsi_transfer_finish(dsi)) 1267 exynos_dsi_transfer_start(dsi); 1268 1269 return IRQ_HANDLED; 1270 } 1271 1272 static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id) 1273 { 1274 struct exynos_dsi *dsi = (struct exynos_dsi *)dev_id; 1275 struct drm_encoder *encoder = &dsi->encoder; 1276 1277 if (dsi->state & DSIM_STATE_VIDOUT_AVAILABLE) 1278 exynos_drm_crtc_te_handler(encoder->crtc); 1279 1280 return IRQ_HANDLED; 1281 } 1282 1283 static void exynos_dsi_enable_irq(struct exynos_dsi *dsi) 1284 { 1285 enable_irq(dsi->irq); 1286 1287 if (gpio_is_valid(dsi->te_gpio)) 1288 enable_irq(gpio_to_irq(dsi->te_gpio)); 1289 } 1290 1291 static void exynos_dsi_disable_irq(struct exynos_dsi *dsi) 1292 { 1293 if (gpio_is_valid(dsi->te_gpio)) 1294 disable_irq(gpio_to_irq(dsi->te_gpio)); 1295 1296 disable_irq(dsi->irq); 1297 } 1298 1299 static int exynos_dsi_init(struct exynos_dsi *dsi) 1300 { 1301 struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 1302 1303 exynos_dsi_reset(dsi); 1304 exynos_dsi_enable_irq(dsi); 1305 1306 if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST) 1307 exynos_dsi_enable_lane(dsi, BIT(dsi->lanes) - 1); 1308 1309 exynos_dsi_enable_clock(dsi); 1310 if (driver_data->wait_for_reset) 1311 exynos_dsi_wait_for_reset(dsi); 1312 exynos_dsi_set_phy_ctrl(dsi); 1313 exynos_dsi_init_link(dsi); 1314 1315 return 0; 1316 } 1317 1318 static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi) 1319 { 1320 int ret; 1321 int te_gpio_irq; 1322 1323 dsi->te_gpio = of_get_named_gpio(dsi->panel_node, "te-gpios", 0); 1324 if (!gpio_is_valid(dsi->te_gpio)) { 1325 dev_err(dsi->dev, "no te-gpios specified\n"); 1326 ret = dsi->te_gpio; 1327 goto out; 1328 } 1329 1330 ret = gpio_request(dsi->te_gpio, "te_gpio"); 1331 if (ret) { 1332 dev_err(dsi->dev, "gpio request failed with %d\n", ret); 1333 goto out; 1334 } 1335 1336 te_gpio_irq = gpio_to_irq(dsi->te_gpio); 1337 irq_set_status_flags(te_gpio_irq, IRQ_NOAUTOEN); 1338 1339 ret = request_threaded_irq(te_gpio_irq, exynos_dsi_te_irq_handler, NULL, 1340 IRQF_TRIGGER_RISING, "TE", dsi); 1341 if (ret) { 1342 dev_err(dsi->dev, "request interrupt failed with %d\n", ret); 1343 gpio_free(dsi->te_gpio); 1344 goto out; 1345 } 1346 1347 out: 1348 return ret; 1349 } 1350 1351 static void exynos_dsi_unregister_te_irq(struct exynos_dsi *dsi) 1352 { 1353 if (gpio_is_valid(dsi->te_gpio)) { 1354 free_irq(gpio_to_irq(dsi->te_gpio), dsi); 1355 gpio_free(dsi->te_gpio); 1356 dsi->te_gpio = -ENOENT; 1357 } 1358 } 1359 1360 static int exynos_dsi_host_attach(struct mipi_dsi_host *host, 1361 struct mipi_dsi_device *device) 1362 { 1363 struct exynos_dsi *dsi = host_to_dsi(host); 1364 1365 dsi->lanes = device->lanes; 1366 dsi->format = device->format; 1367 dsi->mode_flags = device->mode_flags; 1368 dsi->panel_node = device->dev.of_node; 1369 1370 /* 1371 * This is a temporary solution and should be made by more generic way. 1372 * 1373 * If attached panel device is for command mode one, dsi should register 1374 * TE interrupt handler. 1375 */ 1376 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) { 1377 int ret = exynos_dsi_register_te_irq(dsi); 1378 1379 if (ret) 1380 return ret; 1381 } 1382 1383 if (dsi->connector.dev) 1384 drm_helper_hpd_irq_event(dsi->connector.dev); 1385 1386 return 0; 1387 } 1388 1389 static int exynos_dsi_host_detach(struct mipi_dsi_host *host, 1390 struct mipi_dsi_device *device) 1391 { 1392 struct exynos_dsi *dsi = host_to_dsi(host); 1393 1394 exynos_dsi_unregister_te_irq(dsi); 1395 1396 dsi->panel_node = NULL; 1397 1398 if (dsi->connector.dev) 1399 drm_helper_hpd_irq_event(dsi->connector.dev); 1400 1401 return 0; 1402 } 1403 1404 /* distinguish between short and long DSI packet types */ 1405 static bool exynos_dsi_is_short_dsi_type(u8 type) 1406 { 1407 return (type & 0x0f) <= 8; 1408 } 1409 1410 static ssize_t exynos_dsi_host_transfer(struct mipi_dsi_host *host, 1411 const struct mipi_dsi_msg *msg) 1412 { 1413 struct exynos_dsi *dsi = host_to_dsi(host); 1414 struct exynos_dsi_transfer xfer; 1415 int ret; 1416 1417 if (!(dsi->state & DSIM_STATE_ENABLED)) 1418 return -EINVAL; 1419 1420 if (!(dsi->state & DSIM_STATE_INITIALIZED)) { 1421 ret = exynos_dsi_init(dsi); 1422 if (ret) 1423 return ret; 1424 dsi->state |= DSIM_STATE_INITIALIZED; 1425 } 1426 1427 if (msg->tx_len == 0) 1428 return -EINVAL; 1429 1430 xfer.data_id = msg->type | (msg->channel << 6); 1431 1432 if (exynos_dsi_is_short_dsi_type(msg->type)) { 1433 const char *tx_buf = msg->tx_buf; 1434 1435 if (msg->tx_len > 2) 1436 return -EINVAL; 1437 xfer.tx_len = 0; 1438 xfer.data[0] = tx_buf[0]; 1439 xfer.data[1] = (msg->tx_len == 2) ? tx_buf[1] : 0; 1440 } else { 1441 xfer.tx_len = msg->tx_len; 1442 xfer.data[0] = msg->tx_len & 0xff; 1443 xfer.data[1] = msg->tx_len >> 8; 1444 xfer.tx_payload = msg->tx_buf; 1445 } 1446 1447 xfer.rx_len = msg->rx_len; 1448 xfer.rx_payload = msg->rx_buf; 1449 xfer.flags = msg->flags; 1450 1451 ret = exynos_dsi_transfer(dsi, &xfer); 1452 return (ret < 0) ? ret : xfer.rx_done; 1453 } 1454 1455 static const struct mipi_dsi_host_ops exynos_dsi_ops = { 1456 .attach = exynos_dsi_host_attach, 1457 .detach = exynos_dsi_host_detach, 1458 .transfer = exynos_dsi_host_transfer, 1459 }; 1460 1461 static int exynos_dsi_poweron(struct exynos_dsi *dsi) 1462 { 1463 struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 1464 int ret, i; 1465 1466 ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 1467 if (ret < 0) { 1468 dev_err(dsi->dev, "cannot enable regulators %d\n", ret); 1469 return ret; 1470 } 1471 1472 for (i = 0; i < driver_data->num_clks; i++) { 1473 ret = clk_prepare_enable(dsi->clks[i]); 1474 if (ret < 0) 1475 goto err_clk; 1476 } 1477 1478 ret = phy_power_on(dsi->phy); 1479 if (ret < 0) { 1480 dev_err(dsi->dev, "cannot enable phy %d\n", ret); 1481 goto err_clk; 1482 } 1483 1484 return 0; 1485 1486 err_clk: 1487 while (--i > -1) 1488 clk_disable_unprepare(dsi->clks[i]); 1489 regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 1490 1491 return ret; 1492 } 1493 1494 static void exynos_dsi_poweroff(struct exynos_dsi *dsi) 1495 { 1496 struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 1497 int ret, i; 1498 1499 usleep_range(10000, 20000); 1500 1501 if (dsi->state & DSIM_STATE_INITIALIZED) { 1502 dsi->state &= ~DSIM_STATE_INITIALIZED; 1503 1504 exynos_dsi_disable_clock(dsi); 1505 1506 exynos_dsi_disable_irq(dsi); 1507 } 1508 1509 dsi->state &= ~DSIM_STATE_CMD_LPM; 1510 1511 phy_power_off(dsi->phy); 1512 1513 for (i = driver_data->num_clks - 1; i > -1; i--) 1514 clk_disable_unprepare(dsi->clks[i]); 1515 1516 ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 1517 if (ret < 0) 1518 dev_err(dsi->dev, "cannot disable regulators %d\n", ret); 1519 } 1520 1521 static void exynos_dsi_enable(struct drm_encoder *encoder) 1522 { 1523 struct exynos_dsi *dsi = encoder_to_dsi(encoder); 1524 int ret; 1525 1526 if (dsi->state & DSIM_STATE_ENABLED) 1527 return; 1528 1529 ret = exynos_dsi_poweron(dsi); 1530 if (ret < 0) 1531 return; 1532 1533 dsi->state |= DSIM_STATE_ENABLED; 1534 1535 ret = drm_panel_prepare(dsi->panel); 1536 if (ret < 0) { 1537 dsi->state &= ~DSIM_STATE_ENABLED; 1538 exynos_dsi_poweroff(dsi); 1539 return; 1540 } 1541 1542 exynos_dsi_set_display_mode(dsi); 1543 exynos_dsi_set_display_enable(dsi, true); 1544 1545 ret = drm_panel_enable(dsi->panel); 1546 if (ret < 0) { 1547 dsi->state &= ~DSIM_STATE_ENABLED; 1548 exynos_dsi_set_display_enable(dsi, false); 1549 drm_panel_unprepare(dsi->panel); 1550 exynos_dsi_poweroff(dsi); 1551 return; 1552 } 1553 1554 dsi->state |= DSIM_STATE_VIDOUT_AVAILABLE; 1555 } 1556 1557 static void exynos_dsi_disable(struct drm_encoder *encoder) 1558 { 1559 struct exynos_dsi *dsi = encoder_to_dsi(encoder); 1560 1561 if (!(dsi->state & DSIM_STATE_ENABLED)) 1562 return; 1563 1564 dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE; 1565 1566 drm_panel_disable(dsi->panel); 1567 exynos_dsi_set_display_enable(dsi, false); 1568 drm_panel_unprepare(dsi->panel); 1569 1570 dsi->state &= ~DSIM_STATE_ENABLED; 1571 1572 exynos_dsi_poweroff(dsi); 1573 } 1574 1575 static enum drm_connector_status 1576 exynos_dsi_detect(struct drm_connector *connector, bool force) 1577 { 1578 struct exynos_dsi *dsi = connector_to_dsi(connector); 1579 1580 if (!dsi->panel) { 1581 dsi->panel = of_drm_find_panel(dsi->panel_node); 1582 if (dsi->panel) 1583 drm_panel_attach(dsi->panel, &dsi->connector); 1584 } else if (!dsi->panel_node) { 1585 struct drm_encoder *encoder; 1586 1587 encoder = platform_get_drvdata(to_platform_device(dsi->dev)); 1588 exynos_dsi_disable(encoder); 1589 drm_panel_detach(dsi->panel); 1590 dsi->panel = NULL; 1591 } 1592 1593 if (dsi->panel) 1594 return connector_status_connected; 1595 1596 return connector_status_disconnected; 1597 } 1598 1599 static void exynos_dsi_connector_destroy(struct drm_connector *connector) 1600 { 1601 drm_connector_unregister(connector); 1602 drm_connector_cleanup(connector); 1603 connector->dev = NULL; 1604 } 1605 1606 static struct drm_connector_funcs exynos_dsi_connector_funcs = { 1607 .dpms = drm_atomic_helper_connector_dpms, 1608 .detect = exynos_dsi_detect, 1609 .fill_modes = drm_helper_probe_single_connector_modes, 1610 .destroy = exynos_dsi_connector_destroy, 1611 .reset = drm_atomic_helper_connector_reset, 1612 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1613 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1614 }; 1615 1616 static int exynos_dsi_get_modes(struct drm_connector *connector) 1617 { 1618 struct exynos_dsi *dsi = connector_to_dsi(connector); 1619 1620 if (dsi->panel) 1621 return dsi->panel->funcs->get_modes(dsi->panel); 1622 1623 return 0; 1624 } 1625 1626 static struct drm_encoder * 1627 exynos_dsi_best_encoder(struct drm_connector *connector) 1628 { 1629 struct exynos_dsi *dsi = connector_to_dsi(connector); 1630 1631 return &dsi->encoder; 1632 } 1633 1634 static struct drm_connector_helper_funcs exynos_dsi_connector_helper_funcs = { 1635 .get_modes = exynos_dsi_get_modes, 1636 .best_encoder = exynos_dsi_best_encoder, 1637 }; 1638 1639 static int exynos_dsi_create_connector(struct drm_encoder *encoder) 1640 { 1641 struct exynos_dsi *dsi = encoder_to_dsi(encoder); 1642 struct drm_connector *connector = &dsi->connector; 1643 int ret; 1644 1645 connector->polled = DRM_CONNECTOR_POLL_HPD; 1646 1647 ret = drm_connector_init(encoder->dev, connector, 1648 &exynos_dsi_connector_funcs, 1649 DRM_MODE_CONNECTOR_DSI); 1650 if (ret) { 1651 DRM_ERROR("Failed to initialize connector with drm\n"); 1652 return ret; 1653 } 1654 1655 drm_connector_helper_add(connector, &exynos_dsi_connector_helper_funcs); 1656 drm_connector_register(connector); 1657 drm_mode_connector_attach_encoder(connector, encoder); 1658 1659 return 0; 1660 } 1661 1662 static bool exynos_dsi_mode_fixup(struct drm_encoder *encoder, 1663 const struct drm_display_mode *mode, 1664 struct drm_display_mode *adjusted_mode) 1665 { 1666 return true; 1667 } 1668 1669 static void exynos_dsi_mode_set(struct drm_encoder *encoder, 1670 struct drm_display_mode *mode, 1671 struct drm_display_mode *adjusted_mode) 1672 { 1673 struct exynos_dsi *dsi = encoder_to_dsi(encoder); 1674 struct videomode *vm = &dsi->vm; 1675 struct drm_display_mode *m = adjusted_mode; 1676 1677 vm->hactive = m->hdisplay; 1678 vm->vactive = m->vdisplay; 1679 vm->vfront_porch = m->vsync_start - m->vdisplay; 1680 vm->vback_porch = m->vtotal - m->vsync_end; 1681 vm->vsync_len = m->vsync_end - m->vsync_start; 1682 vm->hfront_porch = m->hsync_start - m->hdisplay; 1683 vm->hback_porch = m->htotal - m->hsync_end; 1684 vm->hsync_len = m->hsync_end - m->hsync_start; 1685 } 1686 1687 static struct drm_encoder_helper_funcs exynos_dsi_encoder_helper_funcs = { 1688 .mode_fixup = exynos_dsi_mode_fixup, 1689 .mode_set = exynos_dsi_mode_set, 1690 .enable = exynos_dsi_enable, 1691 .disable = exynos_dsi_disable, 1692 }; 1693 1694 static struct drm_encoder_funcs exynos_dsi_encoder_funcs = { 1695 .destroy = drm_encoder_cleanup, 1696 }; 1697 1698 MODULE_DEVICE_TABLE(of, exynos_dsi_of_match); 1699 1700 /* of_* functions will be removed after merge of of_graph patches */ 1701 static struct device_node * 1702 of_get_child_by_name_reg(struct device_node *parent, const char *name, u32 reg) 1703 { 1704 struct device_node *np; 1705 1706 for_each_child_of_node(parent, np) { 1707 u32 r; 1708 1709 if (!np->name || of_node_cmp(np->name, name)) 1710 continue; 1711 1712 if (of_property_read_u32(np, "reg", &r) < 0) 1713 r = 0; 1714 1715 if (reg == r) 1716 break; 1717 } 1718 1719 return np; 1720 } 1721 1722 static struct device_node *of_graph_get_port_by_reg(struct device_node *parent, 1723 u32 reg) 1724 { 1725 struct device_node *ports, *port; 1726 1727 ports = of_get_child_by_name(parent, "ports"); 1728 if (ports) 1729 parent = ports; 1730 1731 port = of_get_child_by_name_reg(parent, "port", reg); 1732 1733 of_node_put(ports); 1734 1735 return port; 1736 } 1737 1738 static struct device_node * 1739 of_graph_get_endpoint_by_reg(struct device_node *port, u32 reg) 1740 { 1741 return of_get_child_by_name_reg(port, "endpoint", reg); 1742 } 1743 1744 static int exynos_dsi_of_read_u32(const struct device_node *np, 1745 const char *propname, u32 *out_value) 1746 { 1747 int ret = of_property_read_u32(np, propname, out_value); 1748 1749 if (ret < 0) 1750 pr_err("%s: failed to get '%s' property\n", np->full_name, 1751 propname); 1752 1753 return ret; 1754 } 1755 1756 enum { 1757 DSI_PORT_IN, 1758 DSI_PORT_OUT 1759 }; 1760 1761 static int exynos_dsi_parse_dt(struct exynos_dsi *dsi) 1762 { 1763 struct device *dev = dsi->dev; 1764 struct device_node *node = dev->of_node; 1765 struct device_node *port, *ep; 1766 int ret; 1767 1768 ret = exynos_dsi_of_read_u32(node, "samsung,pll-clock-frequency", 1769 &dsi->pll_clk_rate); 1770 if (ret < 0) 1771 return ret; 1772 1773 port = of_graph_get_port_by_reg(node, DSI_PORT_OUT); 1774 if (!port) { 1775 dev_err(dev, "no output port specified\n"); 1776 return -EINVAL; 1777 } 1778 1779 ep = of_graph_get_endpoint_by_reg(port, 0); 1780 of_node_put(port); 1781 if (!ep) { 1782 dev_err(dev, "no endpoint specified in output port\n"); 1783 return -EINVAL; 1784 } 1785 1786 ret = exynos_dsi_of_read_u32(ep, "samsung,burst-clock-frequency", 1787 &dsi->burst_clk_rate); 1788 if (ret < 0) 1789 goto end; 1790 1791 ret = exynos_dsi_of_read_u32(ep, "samsung,esc-clock-frequency", 1792 &dsi->esc_clk_rate); 1793 if (ret < 0) 1794 goto end; 1795 1796 of_node_put(ep); 1797 1798 ep = of_graph_get_next_endpoint(node, NULL); 1799 if (!ep) { 1800 ret = -ENXIO; 1801 goto end; 1802 } 1803 1804 dsi->bridge_node = of_graph_get_remote_port_parent(ep); 1805 if (!dsi->bridge_node) { 1806 ret = -ENXIO; 1807 goto end; 1808 } 1809 end: 1810 of_node_put(ep); 1811 1812 return ret; 1813 } 1814 1815 static int exynos_dsi_bind(struct device *dev, struct device *master, 1816 void *data) 1817 { 1818 struct drm_encoder *encoder = dev_get_drvdata(dev); 1819 struct exynos_dsi *dsi = encoder_to_dsi(encoder); 1820 struct drm_device *drm_dev = data; 1821 struct drm_bridge *bridge; 1822 int ret; 1823 1824 ret = exynos_drm_crtc_get_pipe_from_type(drm_dev, 1825 EXYNOS_DISPLAY_TYPE_LCD); 1826 if (ret < 0) 1827 return ret; 1828 1829 encoder->possible_crtcs = 1 << ret; 1830 1831 DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs); 1832 1833 drm_encoder_init(drm_dev, encoder, &exynos_dsi_encoder_funcs, 1834 DRM_MODE_ENCODER_TMDS); 1835 1836 drm_encoder_helper_add(encoder, &exynos_dsi_encoder_helper_funcs); 1837 1838 ret = exynos_dsi_create_connector(encoder); 1839 if (ret) { 1840 DRM_ERROR("failed to create connector ret = %d\n", ret); 1841 drm_encoder_cleanup(encoder); 1842 return ret; 1843 } 1844 1845 bridge = of_drm_find_bridge(dsi->bridge_node); 1846 if (bridge) { 1847 drm_bridge_attach(drm_dev, bridge); 1848 } 1849 1850 return mipi_dsi_host_register(&dsi->dsi_host); 1851 } 1852 1853 static void exynos_dsi_unbind(struct device *dev, struct device *master, 1854 void *data) 1855 { 1856 struct drm_encoder *encoder = dev_get_drvdata(dev); 1857 struct exynos_dsi *dsi = encoder_to_dsi(encoder); 1858 1859 exynos_dsi_disable(encoder); 1860 1861 mipi_dsi_host_unregister(&dsi->dsi_host); 1862 } 1863 1864 static const struct component_ops exynos_dsi_component_ops = { 1865 .bind = exynos_dsi_bind, 1866 .unbind = exynos_dsi_unbind, 1867 }; 1868 1869 static int exynos_dsi_probe(struct platform_device *pdev) 1870 { 1871 struct device *dev = &pdev->dev; 1872 struct resource *res; 1873 struct exynos_dsi *dsi; 1874 int ret, i; 1875 1876 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 1877 if (!dsi) 1878 return -ENOMEM; 1879 1880 /* To be checked as invalid one */ 1881 dsi->te_gpio = -ENOENT; 1882 1883 init_completion(&dsi->completed); 1884 spin_lock_init(&dsi->transfer_lock); 1885 INIT_LIST_HEAD(&dsi->transfer_list); 1886 1887 dsi->dsi_host.ops = &exynos_dsi_ops; 1888 dsi->dsi_host.dev = dev; 1889 1890 dsi->dev = dev; 1891 dsi->driver_data = exynos_dsi_get_driver_data(pdev); 1892 1893 ret = exynos_dsi_parse_dt(dsi); 1894 if (ret) 1895 return ret; 1896 1897 dsi->supplies[0].supply = "vddcore"; 1898 dsi->supplies[1].supply = "vddio"; 1899 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies), 1900 dsi->supplies); 1901 if (ret) { 1902 dev_info(dev, "failed to get regulators: %d\n", ret); 1903 return -EPROBE_DEFER; 1904 } 1905 1906 dsi->clks = devm_kzalloc(dev, 1907 sizeof(*dsi->clks) * dsi->driver_data->num_clks, 1908 GFP_KERNEL); 1909 if (!dsi->clks) 1910 return -ENOMEM; 1911 1912 for (i = 0; i < dsi->driver_data->num_clks; i++) { 1913 dsi->clks[i] = devm_clk_get(dev, clk_names[i]); 1914 if (IS_ERR(dsi->clks[i])) { 1915 if (strcmp(clk_names[i], "sclk_mipi") == 0) { 1916 strcpy(clk_names[i], OLD_SCLK_MIPI_CLK_NAME); 1917 i--; 1918 continue; 1919 } 1920 1921 dev_info(dev, "failed to get the clock: %s\n", 1922 clk_names[i]); 1923 return PTR_ERR(dsi->clks[i]); 1924 } 1925 } 1926 1927 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1928 dsi->reg_base = devm_ioremap_resource(dev, res); 1929 if (IS_ERR(dsi->reg_base)) { 1930 dev_err(dev, "failed to remap io region\n"); 1931 return PTR_ERR(dsi->reg_base); 1932 } 1933 1934 dsi->phy = devm_phy_get(dev, "dsim"); 1935 if (IS_ERR(dsi->phy)) { 1936 dev_info(dev, "failed to get dsim phy\n"); 1937 return PTR_ERR(dsi->phy); 1938 } 1939 1940 dsi->irq = platform_get_irq(pdev, 0); 1941 if (dsi->irq < 0) { 1942 dev_err(dev, "failed to request dsi irq resource\n"); 1943 return dsi->irq; 1944 } 1945 1946 irq_set_status_flags(dsi->irq, IRQ_NOAUTOEN); 1947 ret = devm_request_threaded_irq(dev, dsi->irq, NULL, 1948 exynos_dsi_irq, IRQF_ONESHOT, 1949 dev_name(dev), dsi); 1950 if (ret) { 1951 dev_err(dev, "failed to request dsi irq\n"); 1952 return ret; 1953 } 1954 1955 platform_set_drvdata(pdev, &dsi->encoder); 1956 1957 return component_add(dev, &exynos_dsi_component_ops); 1958 } 1959 1960 static int exynos_dsi_remove(struct platform_device *pdev) 1961 { 1962 component_del(&pdev->dev, &exynos_dsi_component_ops); 1963 1964 return 0; 1965 } 1966 1967 struct platform_driver dsi_driver = { 1968 .probe = exynos_dsi_probe, 1969 .remove = exynos_dsi_remove, 1970 .driver = { 1971 .name = "exynos-dsi", 1972 .owner = THIS_MODULE, 1973 .of_match_table = exynos_dsi_of_match, 1974 }, 1975 }; 1976 1977 MODULE_AUTHOR("Tomasz Figa <t.figa@samsung.com>"); 1978 MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>"); 1979 MODULE_DESCRIPTION("Samsung SoC MIPI DSI Master"); 1980 MODULE_LICENSE("GPL v2"); 1981