1 /* 2 * Samsung SoC MIPI DSI Master driver. 3 * 4 * Copyright (c) 2014 Samsung Electronics Co., Ltd 5 * 6 * Contacts: Tomasz Figa <t.figa@samsung.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <drm/drmP.h> 14 #include <drm/drm_crtc_helper.h> 15 #include <drm/drm_mipi_dsi.h> 16 #include <drm/drm_panel.h> 17 18 #include <linux/clk.h> 19 #include <linux/gpio/consumer.h> 20 #include <linux/irq.h> 21 #include <linux/of_device.h> 22 #include <linux/of_gpio.h> 23 #include <linux/phy/phy.h> 24 #include <linux/regulator/consumer.h> 25 #include <linux/component.h> 26 27 #include <video/mipi_display.h> 28 #include <video/videomode.h> 29 30 #include "exynos_drm_crtc.h" 31 #include "exynos_drm_drv.h" 32 33 /* returns true iff both arguments logically differs */ 34 #define NEQV(a, b) (!(a) ^ !(b)) 35 36 #define DSIM_STATUS_REG 0x0 /* Status register */ 37 #define DSIM_SWRST_REG 0x4 /* Software reset register */ 38 #define DSIM_CLKCTRL_REG 0x8 /* Clock control register */ 39 #define DSIM_TIMEOUT_REG 0xc /* Time out register */ 40 #define DSIM_CONFIG_REG 0x10 /* Configuration register */ 41 #define DSIM_ESCMODE_REG 0x14 /* Escape mode register */ 42 43 /* Main display image resolution register */ 44 #define DSIM_MDRESOL_REG 0x18 45 #define DSIM_MVPORCH_REG 0x1c /* Main display Vporch register */ 46 #define DSIM_MHPORCH_REG 0x20 /* Main display Hporch register */ 47 #define DSIM_MSYNC_REG 0x24 /* Main display sync area register */ 48 49 /* Sub display image resolution register */ 50 #define DSIM_SDRESOL_REG 0x28 51 #define DSIM_INTSRC_REG 0x2c /* Interrupt source register */ 52 #define DSIM_INTMSK_REG 0x30 /* Interrupt mask register */ 53 #define DSIM_PKTHDR_REG 0x34 /* Packet Header FIFO register */ 54 #define DSIM_PAYLOAD_REG 0x38 /* Payload FIFO register */ 55 #define DSIM_RXFIFO_REG 0x3c /* Read FIFO register */ 56 #define DSIM_FIFOTHLD_REG 0x40 /* FIFO threshold level register */ 57 #define DSIM_FIFOCTRL_REG 0x44 /* FIFO status and control register */ 58 59 /* FIFO memory AC characteristic register */ 60 #define DSIM_PLLCTRL_REG 0x4c /* PLL control register */ 61 #define DSIM_PHYACCHR_REG 0x54 /* D-PHY AC characteristic register */ 62 #define DSIM_PHYACCHR1_REG 0x58 /* D-PHY AC characteristic register1 */ 63 #define DSIM_PHYCTRL_REG 0x5c 64 #define DSIM_PHYTIMING_REG 0x64 65 #define DSIM_PHYTIMING1_REG 0x68 66 #define DSIM_PHYTIMING2_REG 0x6c 67 68 /* DSIM_STATUS */ 69 #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0) 70 #define DSIM_STOP_STATE_CLK (1 << 8) 71 #define DSIM_TX_READY_HS_CLK (1 << 10) 72 #define DSIM_PLL_STABLE (1 << 31) 73 74 /* DSIM_SWRST */ 75 #define DSIM_FUNCRST (1 << 16) 76 #define DSIM_SWRST (1 << 0) 77 78 /* DSIM_TIMEOUT */ 79 #define DSIM_LPDR_TIMEOUT(x) ((x) << 0) 80 #define DSIM_BTA_TIMEOUT(x) ((x) << 16) 81 82 /* DSIM_CLKCTRL */ 83 #define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << 0) 84 #define DSIM_ESC_PRESCALER_MASK (0xffff << 0) 85 #define DSIM_LANE_ESC_CLK_EN_CLK (1 << 19) 86 #define DSIM_LANE_ESC_CLK_EN_DATA(x) (((x) & 0xf) << 20) 87 #define DSIM_LANE_ESC_CLK_EN_DATA_MASK (0xf << 20) 88 #define DSIM_BYTE_CLKEN (1 << 24) 89 #define DSIM_BYTE_CLK_SRC(x) (((x) & 0x3) << 25) 90 #define DSIM_BYTE_CLK_SRC_MASK (0x3 << 25) 91 #define DSIM_PLL_BYPASS (1 << 27) 92 #define DSIM_ESC_CLKEN (1 << 28) 93 #define DSIM_TX_REQUEST_HSCLK (1 << 31) 94 95 /* DSIM_CONFIG */ 96 #define DSIM_LANE_EN_CLK (1 << 0) 97 #define DSIM_LANE_EN(x) (((x) & 0xf) << 1) 98 #define DSIM_NUM_OF_DATA_LANE(x) (((x) & 0x3) << 5) 99 #define DSIM_SUB_PIX_FORMAT(x) (((x) & 0x7) << 8) 100 #define DSIM_MAIN_PIX_FORMAT_MASK (0x7 << 12) 101 #define DSIM_MAIN_PIX_FORMAT_RGB888 (0x7 << 12) 102 #define DSIM_MAIN_PIX_FORMAT_RGB666 (0x6 << 12) 103 #define DSIM_MAIN_PIX_FORMAT_RGB666_P (0x5 << 12) 104 #define DSIM_MAIN_PIX_FORMAT_RGB565 (0x4 << 12) 105 #define DSIM_SUB_VC (((x) & 0x3) << 16) 106 #define DSIM_MAIN_VC (((x) & 0x3) << 18) 107 #define DSIM_HSA_MODE (1 << 20) 108 #define DSIM_HBP_MODE (1 << 21) 109 #define DSIM_HFP_MODE (1 << 22) 110 #define DSIM_HSE_MODE (1 << 23) 111 #define DSIM_AUTO_MODE (1 << 24) 112 #define DSIM_VIDEO_MODE (1 << 25) 113 #define DSIM_BURST_MODE (1 << 26) 114 #define DSIM_SYNC_INFORM (1 << 27) 115 #define DSIM_EOT_DISABLE (1 << 28) 116 #define DSIM_MFLUSH_VS (1 << 29) 117 118 /* DSIM_ESCMODE */ 119 #define DSIM_TX_TRIGGER_RST (1 << 4) 120 #define DSIM_TX_LPDT_LP (1 << 6) 121 #define DSIM_CMD_LPDT_LP (1 << 7) 122 #define DSIM_FORCE_BTA (1 << 16) 123 #define DSIM_FORCE_STOP_STATE (1 << 20) 124 #define DSIM_STOP_STATE_CNT(x) (((x) & 0x7ff) << 21) 125 #define DSIM_STOP_STATE_CNT_MASK (0x7ff << 21) 126 127 /* DSIM_MDRESOL */ 128 #define DSIM_MAIN_STAND_BY (1 << 31) 129 #define DSIM_MAIN_VRESOL(x) (((x) & 0x7ff) << 16) 130 #define DSIM_MAIN_HRESOL(x) (((x) & 0X7ff) << 0) 131 132 /* DSIM_MVPORCH */ 133 #define DSIM_CMD_ALLOW(x) ((x) << 28) 134 #define DSIM_STABLE_VFP(x) ((x) << 16) 135 #define DSIM_MAIN_VBP(x) ((x) << 0) 136 #define DSIM_CMD_ALLOW_MASK (0xf << 28) 137 #define DSIM_STABLE_VFP_MASK (0x7ff << 16) 138 #define DSIM_MAIN_VBP_MASK (0x7ff << 0) 139 140 /* DSIM_MHPORCH */ 141 #define DSIM_MAIN_HFP(x) ((x) << 16) 142 #define DSIM_MAIN_HBP(x) ((x) << 0) 143 #define DSIM_MAIN_HFP_MASK ((0xffff) << 16) 144 #define DSIM_MAIN_HBP_MASK ((0xffff) << 0) 145 146 /* DSIM_MSYNC */ 147 #define DSIM_MAIN_VSA(x) ((x) << 22) 148 #define DSIM_MAIN_HSA(x) ((x) << 0) 149 #define DSIM_MAIN_VSA_MASK ((0x3ff) << 22) 150 #define DSIM_MAIN_HSA_MASK ((0xffff) << 0) 151 152 /* DSIM_SDRESOL */ 153 #define DSIM_SUB_STANDY(x) ((x) << 31) 154 #define DSIM_SUB_VRESOL(x) ((x) << 16) 155 #define DSIM_SUB_HRESOL(x) ((x) << 0) 156 #define DSIM_SUB_STANDY_MASK ((0x1) << 31) 157 #define DSIM_SUB_VRESOL_MASK ((0x7ff) << 16) 158 #define DSIM_SUB_HRESOL_MASK ((0x7ff) << 0) 159 160 /* DSIM_INTSRC */ 161 #define DSIM_INT_PLL_STABLE (1 << 31) 162 #define DSIM_INT_SW_RST_RELEASE (1 << 30) 163 #define DSIM_INT_SFR_FIFO_EMPTY (1 << 29) 164 #define DSIM_INT_BTA (1 << 25) 165 #define DSIM_INT_FRAME_DONE (1 << 24) 166 #define DSIM_INT_RX_TIMEOUT (1 << 21) 167 #define DSIM_INT_BTA_TIMEOUT (1 << 20) 168 #define DSIM_INT_RX_DONE (1 << 18) 169 #define DSIM_INT_RX_TE (1 << 17) 170 #define DSIM_INT_RX_ACK (1 << 16) 171 #define DSIM_INT_RX_ECC_ERR (1 << 15) 172 #define DSIM_INT_RX_CRC_ERR (1 << 14) 173 174 /* DSIM_FIFOCTRL */ 175 #define DSIM_RX_DATA_FULL (1 << 25) 176 #define DSIM_RX_DATA_EMPTY (1 << 24) 177 #define DSIM_SFR_HEADER_FULL (1 << 23) 178 #define DSIM_SFR_HEADER_EMPTY (1 << 22) 179 #define DSIM_SFR_PAYLOAD_FULL (1 << 21) 180 #define DSIM_SFR_PAYLOAD_EMPTY (1 << 20) 181 #define DSIM_I80_HEADER_FULL (1 << 19) 182 #define DSIM_I80_HEADER_EMPTY (1 << 18) 183 #define DSIM_I80_PAYLOAD_FULL (1 << 17) 184 #define DSIM_I80_PAYLOAD_EMPTY (1 << 16) 185 #define DSIM_SD_HEADER_FULL (1 << 15) 186 #define DSIM_SD_HEADER_EMPTY (1 << 14) 187 #define DSIM_SD_PAYLOAD_FULL (1 << 13) 188 #define DSIM_SD_PAYLOAD_EMPTY (1 << 12) 189 #define DSIM_MD_HEADER_FULL (1 << 11) 190 #define DSIM_MD_HEADER_EMPTY (1 << 10) 191 #define DSIM_MD_PAYLOAD_FULL (1 << 9) 192 #define DSIM_MD_PAYLOAD_EMPTY (1 << 8) 193 #define DSIM_RX_FIFO (1 << 4) 194 #define DSIM_SFR_FIFO (1 << 3) 195 #define DSIM_I80_FIFO (1 << 2) 196 #define DSIM_SD_FIFO (1 << 1) 197 #define DSIM_MD_FIFO (1 << 0) 198 199 /* DSIM_PHYACCHR */ 200 #define DSIM_AFC_EN (1 << 14) 201 #define DSIM_AFC_CTL(x) (((x) & 0x7) << 5) 202 203 /* DSIM_PLLCTRL */ 204 #define DSIM_FREQ_BAND(x) ((x) << 24) 205 #define DSIM_PLL_EN (1 << 23) 206 #define DSIM_PLL_P(x) ((x) << 13) 207 #define DSIM_PLL_M(x) ((x) << 4) 208 #define DSIM_PLL_S(x) ((x) << 1) 209 210 /* DSIM_PHYCTRL */ 211 #define DSIM_PHYCTRL_ULPS_EXIT(x) (((x) & 0x1ff) << 0) 212 213 /* DSIM_PHYTIMING */ 214 #define DSIM_PHYTIMING_LPX(x) ((x) << 8) 215 #define DSIM_PHYTIMING_HS_EXIT(x) ((x) << 0) 216 217 /* DSIM_PHYTIMING1 */ 218 #define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24) 219 #define DSIM_PHYTIMING1_CLK_ZERO(x) ((x) << 16) 220 #define DSIM_PHYTIMING1_CLK_POST(x) ((x) << 8) 221 #define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) << 0) 222 223 /* DSIM_PHYTIMING2 */ 224 #define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) << 16) 225 #define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8) 226 #define DSIM_PHYTIMING2_HS_TRAIL(x) ((x) << 0) 227 228 #define DSI_MAX_BUS_WIDTH 4 229 #define DSI_NUM_VIRTUAL_CHANNELS 4 230 #define DSI_TX_FIFO_SIZE 2048 231 #define DSI_RX_FIFO_SIZE 256 232 #define DSI_XFER_TIMEOUT_MS 100 233 #define DSI_RX_FIFO_EMPTY 0x30800002 234 235 enum exynos_dsi_transfer_type { 236 EXYNOS_DSI_TX, 237 EXYNOS_DSI_RX, 238 }; 239 240 struct exynos_dsi_transfer { 241 struct list_head list; 242 struct completion completed; 243 int result; 244 u8 data_id; 245 u8 data[2]; 246 u16 flags; 247 248 const u8 *tx_payload; 249 u16 tx_len; 250 u16 tx_done; 251 252 u8 *rx_payload; 253 u16 rx_len; 254 u16 rx_done; 255 }; 256 257 #define DSIM_STATE_ENABLED BIT(0) 258 #define DSIM_STATE_INITIALIZED BIT(1) 259 #define DSIM_STATE_CMD_LPM BIT(2) 260 261 struct exynos_dsi_driver_data { 262 unsigned int plltmr_reg; 263 264 unsigned int has_freqband:1; 265 }; 266 267 struct exynos_dsi { 268 struct mipi_dsi_host dsi_host; 269 struct drm_connector connector; 270 struct drm_encoder *encoder; 271 struct device_node *panel_node; 272 struct drm_panel *panel; 273 struct device *dev; 274 275 void __iomem *reg_base; 276 struct phy *phy; 277 struct clk *pll_clk; 278 struct clk *bus_clk; 279 struct regulator_bulk_data supplies[2]; 280 int irq; 281 int te_gpio; 282 283 u32 pll_clk_rate; 284 u32 burst_clk_rate; 285 u32 esc_clk_rate; 286 u32 lanes; 287 u32 mode_flags; 288 u32 format; 289 struct videomode vm; 290 291 int state; 292 struct drm_property *brightness; 293 struct completion completed; 294 295 spinlock_t transfer_lock; /* protects transfer_list */ 296 struct list_head transfer_list; 297 298 struct exynos_dsi_driver_data *driver_data; 299 }; 300 301 #define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host) 302 #define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector) 303 304 static struct exynos_dsi_driver_data exynos4_dsi_driver_data = { 305 .plltmr_reg = 0x50, 306 .has_freqband = 1, 307 }; 308 309 static struct exynos_dsi_driver_data exynos5_dsi_driver_data = { 310 .plltmr_reg = 0x58, 311 }; 312 313 static struct of_device_id exynos_dsi_of_match[] = { 314 { .compatible = "samsung,exynos4210-mipi-dsi", 315 .data = &exynos4_dsi_driver_data }, 316 { .compatible = "samsung,exynos5410-mipi-dsi", 317 .data = &exynos5_dsi_driver_data }, 318 { } 319 }; 320 321 static inline struct exynos_dsi_driver_data *exynos_dsi_get_driver_data( 322 struct platform_device *pdev) 323 { 324 const struct of_device_id *of_id = 325 of_match_device(exynos_dsi_of_match, &pdev->dev); 326 327 return (struct exynos_dsi_driver_data *)of_id->data; 328 } 329 330 static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi) 331 { 332 if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300))) 333 return; 334 335 dev_err(dsi->dev, "timeout waiting for reset\n"); 336 } 337 338 static void exynos_dsi_reset(struct exynos_dsi *dsi) 339 { 340 reinit_completion(&dsi->completed); 341 writel(DSIM_SWRST, dsi->reg_base + DSIM_SWRST_REG); 342 } 343 344 #ifndef MHZ 345 #define MHZ (1000*1000) 346 #endif 347 348 static unsigned long exynos_dsi_pll_find_pms(struct exynos_dsi *dsi, 349 unsigned long fin, unsigned long fout, u8 *p, u16 *m, u8 *s) 350 { 351 unsigned long best_freq = 0; 352 u32 min_delta = 0xffffffff; 353 u8 p_min, p_max; 354 u8 _p, uninitialized_var(best_p); 355 u16 _m, uninitialized_var(best_m); 356 u8 _s, uninitialized_var(best_s); 357 358 p_min = DIV_ROUND_UP(fin, (12 * MHZ)); 359 p_max = fin / (6 * MHZ); 360 361 for (_p = p_min; _p <= p_max; ++_p) { 362 for (_s = 0; _s <= 5; ++_s) { 363 u64 tmp; 364 u32 delta; 365 366 tmp = (u64)fout * (_p << _s); 367 do_div(tmp, fin); 368 _m = tmp; 369 if (_m < 41 || _m > 125) 370 continue; 371 372 tmp = (u64)_m * fin; 373 do_div(tmp, _p); 374 if (tmp < 500 * MHZ || tmp > 1000 * MHZ) 375 continue; 376 377 tmp = (u64)_m * fin; 378 do_div(tmp, _p << _s); 379 380 delta = abs(fout - tmp); 381 if (delta < min_delta) { 382 best_p = _p; 383 best_m = _m; 384 best_s = _s; 385 min_delta = delta; 386 best_freq = tmp; 387 } 388 } 389 } 390 391 if (best_freq) { 392 *p = best_p; 393 *m = best_m; 394 *s = best_s; 395 } 396 397 return best_freq; 398 } 399 400 static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi, 401 unsigned long freq) 402 { 403 struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 404 unsigned long fin, fout; 405 int timeout; 406 u8 p, s; 407 u16 m; 408 u32 reg; 409 410 clk_set_rate(dsi->pll_clk, dsi->pll_clk_rate); 411 412 fin = clk_get_rate(dsi->pll_clk); 413 if (!fin) { 414 dev_err(dsi->dev, "failed to get PLL clock frequency\n"); 415 return 0; 416 } 417 418 dev_dbg(dsi->dev, "PLL input frequency: %lu\n", fin); 419 420 fout = exynos_dsi_pll_find_pms(dsi, fin, freq, &p, &m, &s); 421 if (!fout) { 422 dev_err(dsi->dev, 423 "failed to find PLL PMS for requested frequency\n"); 424 return -EFAULT; 425 } 426 dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s); 427 428 writel(500, dsi->reg_base + driver_data->plltmr_reg); 429 430 reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s); 431 432 if (driver_data->has_freqband) { 433 static const unsigned long freq_bands[] = { 434 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ, 435 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ, 436 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ, 437 770 * MHZ, 870 * MHZ, 950 * MHZ, 438 }; 439 int band; 440 441 for (band = 0; band < ARRAY_SIZE(freq_bands); ++band) 442 if (fout < freq_bands[band]) 443 break; 444 445 dev_dbg(dsi->dev, "band %d\n", band); 446 447 reg |= DSIM_FREQ_BAND(band); 448 } 449 450 writel(reg, dsi->reg_base + DSIM_PLLCTRL_REG); 451 452 timeout = 1000; 453 do { 454 if (timeout-- == 0) { 455 dev_err(dsi->dev, "PLL failed to stabilize\n"); 456 return -EFAULT; 457 } 458 reg = readl(dsi->reg_base + DSIM_STATUS_REG); 459 } while ((reg & DSIM_PLL_STABLE) == 0); 460 461 return fout; 462 } 463 464 static int exynos_dsi_enable_clock(struct exynos_dsi *dsi) 465 { 466 unsigned long hs_clk, byte_clk, esc_clk; 467 unsigned long esc_div; 468 u32 reg; 469 470 hs_clk = exynos_dsi_set_pll(dsi, dsi->burst_clk_rate); 471 if (!hs_clk) { 472 dev_err(dsi->dev, "failed to configure DSI PLL\n"); 473 return -EFAULT; 474 } 475 476 byte_clk = hs_clk / 8; 477 esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate); 478 esc_clk = byte_clk / esc_div; 479 480 if (esc_clk > 20 * MHZ) { 481 ++esc_div; 482 esc_clk = byte_clk / esc_div; 483 } 484 485 dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n", 486 hs_clk, byte_clk, esc_clk); 487 488 reg = readl(dsi->reg_base + DSIM_CLKCTRL_REG); 489 reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK 490 | DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS 491 | DSIM_BYTE_CLK_SRC_MASK); 492 reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN 493 | DSIM_ESC_PRESCALER(esc_div) 494 | DSIM_LANE_ESC_CLK_EN_CLK 495 | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1) 496 | DSIM_BYTE_CLK_SRC(0) 497 | DSIM_TX_REQUEST_HSCLK; 498 writel(reg, dsi->reg_base + DSIM_CLKCTRL_REG); 499 500 return 0; 501 } 502 503 static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi) 504 { 505 struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 506 u32 reg; 507 508 if (driver_data->has_freqband) 509 return; 510 511 /* B D-PHY: D-PHY Master & Slave Analog Block control */ 512 reg = DSIM_PHYCTRL_ULPS_EXIT(0x0af); 513 writel(reg, dsi->reg_base + DSIM_PHYCTRL_REG); 514 515 /* 516 * T LPX: Transmitted length of any Low-Power state period 517 * T HS-EXIT: Time that the transmitter drives LP-11 following a HS 518 * burst 519 */ 520 reg = DSIM_PHYTIMING_LPX(0x06) | DSIM_PHYTIMING_HS_EXIT(0x0b); 521 writel(reg, dsi->reg_base + DSIM_PHYTIMING_REG); 522 523 /* 524 * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00 525 * Line state immediately before the HS-0 Line state starting the 526 * HS transmission 527 * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to 528 * transmitting the Clock. 529 * T CLK_POST: Time that the transmitter continues to send HS clock 530 * after the last associated Data Lane has transitioned to LP Mode 531 * Interval is defined as the period from the end of T HS-TRAIL to 532 * the beginning of T CLK-TRAIL 533 * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after 534 * the last payload clock bit of a HS transmission burst 535 */ 536 reg = DSIM_PHYTIMING1_CLK_PREPARE(0x07) | 537 DSIM_PHYTIMING1_CLK_ZERO(0x27) | 538 DSIM_PHYTIMING1_CLK_POST(0x0d) | 539 DSIM_PHYTIMING1_CLK_TRAIL(0x08); 540 writel(reg, dsi->reg_base + DSIM_PHYTIMING1_REG); 541 542 /* 543 * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00 544 * Line state immediately before the HS-0 Line state starting the 545 * HS transmission 546 * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to 547 * transmitting the Sync sequence. 548 * T HS-TRAIL: Time that the transmitter drives the flipped differential 549 * state after last payload data bit of a HS transmission burst 550 */ 551 reg = DSIM_PHYTIMING2_HS_PREPARE(0x09) | DSIM_PHYTIMING2_HS_ZERO(0x0d) | 552 DSIM_PHYTIMING2_HS_TRAIL(0x0b); 553 writel(reg, dsi->reg_base + DSIM_PHYTIMING2_REG); 554 } 555 556 static void exynos_dsi_disable_clock(struct exynos_dsi *dsi) 557 { 558 u32 reg; 559 560 reg = readl(dsi->reg_base + DSIM_CLKCTRL_REG); 561 reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK 562 | DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN); 563 writel(reg, dsi->reg_base + DSIM_CLKCTRL_REG); 564 565 reg = readl(dsi->reg_base + DSIM_PLLCTRL_REG); 566 reg &= ~DSIM_PLL_EN; 567 writel(reg, dsi->reg_base + DSIM_PLLCTRL_REG); 568 } 569 570 static int exynos_dsi_init_link(struct exynos_dsi *dsi) 571 { 572 int timeout; 573 u32 reg; 574 u32 lanes_mask; 575 576 /* Initialize FIFO pointers */ 577 reg = readl(dsi->reg_base + DSIM_FIFOCTRL_REG); 578 reg &= ~0x1f; 579 writel(reg, dsi->reg_base + DSIM_FIFOCTRL_REG); 580 581 usleep_range(9000, 11000); 582 583 reg |= 0x1f; 584 writel(reg, dsi->reg_base + DSIM_FIFOCTRL_REG); 585 586 usleep_range(9000, 11000); 587 588 /* DSI configuration */ 589 reg = 0; 590 591 /* 592 * The first bit of mode_flags specifies display configuration. 593 * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video 594 * mode, otherwise it will support command mode. 595 */ 596 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 597 reg |= DSIM_VIDEO_MODE; 598 599 /* 600 * The user manual describes that following bits are ignored in 601 * command mode. 602 */ 603 if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH)) 604 reg |= DSIM_MFLUSH_VS; 605 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 606 reg |= DSIM_SYNC_INFORM; 607 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 608 reg |= DSIM_BURST_MODE; 609 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT) 610 reg |= DSIM_AUTO_MODE; 611 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE) 612 reg |= DSIM_HSE_MODE; 613 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP)) 614 reg |= DSIM_HFP_MODE; 615 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP)) 616 reg |= DSIM_HBP_MODE; 617 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSA)) 618 reg |= DSIM_HSA_MODE; 619 } 620 621 if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET)) 622 reg |= DSIM_EOT_DISABLE; 623 624 switch (dsi->format) { 625 case MIPI_DSI_FMT_RGB888: 626 reg |= DSIM_MAIN_PIX_FORMAT_RGB888; 627 break; 628 case MIPI_DSI_FMT_RGB666: 629 reg |= DSIM_MAIN_PIX_FORMAT_RGB666; 630 break; 631 case MIPI_DSI_FMT_RGB666_PACKED: 632 reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P; 633 break; 634 case MIPI_DSI_FMT_RGB565: 635 reg |= DSIM_MAIN_PIX_FORMAT_RGB565; 636 break; 637 default: 638 dev_err(dsi->dev, "invalid pixel format\n"); 639 return -EINVAL; 640 } 641 642 reg |= DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1); 643 644 writel(reg, dsi->reg_base + DSIM_CONFIG_REG); 645 646 reg |= DSIM_LANE_EN_CLK; 647 writel(reg, dsi->reg_base + DSIM_CONFIG_REG); 648 649 lanes_mask = BIT(dsi->lanes) - 1; 650 reg |= DSIM_LANE_EN(lanes_mask); 651 writel(reg, dsi->reg_base + DSIM_CONFIG_REG); 652 653 /* Check clock and data lane state are stop state */ 654 timeout = 100; 655 do { 656 if (timeout-- == 0) { 657 dev_err(dsi->dev, "waiting for bus lanes timed out\n"); 658 return -EFAULT; 659 } 660 661 reg = readl(dsi->reg_base + DSIM_STATUS_REG); 662 if ((reg & DSIM_STOP_STATE_DAT(lanes_mask)) 663 != DSIM_STOP_STATE_DAT(lanes_mask)) 664 continue; 665 } while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK))); 666 667 reg = readl(dsi->reg_base + DSIM_ESCMODE_REG); 668 reg &= ~DSIM_STOP_STATE_CNT_MASK; 669 reg |= DSIM_STOP_STATE_CNT(0xf); 670 writel(reg, dsi->reg_base + DSIM_ESCMODE_REG); 671 672 reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff); 673 writel(reg, dsi->reg_base + DSIM_TIMEOUT_REG); 674 675 return 0; 676 } 677 678 static void exynos_dsi_set_display_mode(struct exynos_dsi *dsi) 679 { 680 struct videomode *vm = &dsi->vm; 681 u32 reg; 682 683 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 684 reg = DSIM_CMD_ALLOW(0xf) 685 | DSIM_STABLE_VFP(vm->vfront_porch) 686 | DSIM_MAIN_VBP(vm->vback_porch); 687 writel(reg, dsi->reg_base + DSIM_MVPORCH_REG); 688 689 reg = DSIM_MAIN_HFP(vm->hfront_porch) 690 | DSIM_MAIN_HBP(vm->hback_porch); 691 writel(reg, dsi->reg_base + DSIM_MHPORCH_REG); 692 693 reg = DSIM_MAIN_VSA(vm->vsync_len) 694 | DSIM_MAIN_HSA(vm->hsync_len); 695 writel(reg, dsi->reg_base + DSIM_MSYNC_REG); 696 } 697 698 reg = DSIM_MAIN_HRESOL(vm->hactive) | DSIM_MAIN_VRESOL(vm->vactive); 699 writel(reg, dsi->reg_base + DSIM_MDRESOL_REG); 700 701 dev_dbg(dsi->dev, "LCD size = %dx%d\n", vm->hactive, vm->vactive); 702 } 703 704 static void exynos_dsi_set_display_enable(struct exynos_dsi *dsi, bool enable) 705 { 706 u32 reg; 707 708 reg = readl(dsi->reg_base + DSIM_MDRESOL_REG); 709 if (enable) 710 reg |= DSIM_MAIN_STAND_BY; 711 else 712 reg &= ~DSIM_MAIN_STAND_BY; 713 writel(reg, dsi->reg_base + DSIM_MDRESOL_REG); 714 } 715 716 static int exynos_dsi_wait_for_hdr_fifo(struct exynos_dsi *dsi) 717 { 718 int timeout = 2000; 719 720 do { 721 u32 reg = readl(dsi->reg_base + DSIM_FIFOCTRL_REG); 722 723 if (!(reg & DSIM_SFR_HEADER_FULL)) 724 return 0; 725 726 if (!cond_resched()) 727 usleep_range(950, 1050); 728 } while (--timeout); 729 730 return -ETIMEDOUT; 731 } 732 733 static void exynos_dsi_set_cmd_lpm(struct exynos_dsi *dsi, bool lpm) 734 { 735 u32 v = readl(dsi->reg_base + DSIM_ESCMODE_REG); 736 737 if (lpm) 738 v |= DSIM_CMD_LPDT_LP; 739 else 740 v &= ~DSIM_CMD_LPDT_LP; 741 742 writel(v, dsi->reg_base + DSIM_ESCMODE_REG); 743 } 744 745 static void exynos_dsi_force_bta(struct exynos_dsi *dsi) 746 { 747 u32 v = readl(dsi->reg_base + DSIM_ESCMODE_REG); 748 749 v |= DSIM_FORCE_BTA; 750 writel(v, dsi->reg_base + DSIM_ESCMODE_REG); 751 } 752 753 static void exynos_dsi_send_to_fifo(struct exynos_dsi *dsi, 754 struct exynos_dsi_transfer *xfer) 755 { 756 struct device *dev = dsi->dev; 757 const u8 *payload = xfer->tx_payload + xfer->tx_done; 758 u16 length = xfer->tx_len - xfer->tx_done; 759 bool first = !xfer->tx_done; 760 u32 reg; 761 762 dev_dbg(dev, "< xfer %p: tx len %u, done %u, rx len %u, done %u\n", 763 xfer, xfer->tx_len, xfer->tx_done, xfer->rx_len, xfer->rx_done); 764 765 if (length > DSI_TX_FIFO_SIZE) 766 length = DSI_TX_FIFO_SIZE; 767 768 xfer->tx_done += length; 769 770 /* Send payload */ 771 while (length >= 4) { 772 reg = (payload[3] << 24) | (payload[2] << 16) 773 | (payload[1] << 8) | payload[0]; 774 writel(reg, dsi->reg_base + DSIM_PAYLOAD_REG); 775 payload += 4; 776 length -= 4; 777 } 778 779 reg = 0; 780 switch (length) { 781 case 3: 782 reg |= payload[2] << 16; 783 /* Fall through */ 784 case 2: 785 reg |= payload[1] << 8; 786 /* Fall through */ 787 case 1: 788 reg |= payload[0]; 789 writel(reg, dsi->reg_base + DSIM_PAYLOAD_REG); 790 break; 791 case 0: 792 /* Do nothing */ 793 break; 794 } 795 796 /* Send packet header */ 797 if (!first) 798 return; 799 800 reg = (xfer->data[1] << 16) | (xfer->data[0] << 8) | xfer->data_id; 801 if (exynos_dsi_wait_for_hdr_fifo(dsi)) { 802 dev_err(dev, "waiting for header FIFO timed out\n"); 803 return; 804 } 805 806 if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM, 807 dsi->state & DSIM_STATE_CMD_LPM)) { 808 exynos_dsi_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM); 809 dsi->state ^= DSIM_STATE_CMD_LPM; 810 } 811 812 writel(reg, dsi->reg_base + DSIM_PKTHDR_REG); 813 814 if (xfer->flags & MIPI_DSI_MSG_REQ_ACK) 815 exynos_dsi_force_bta(dsi); 816 } 817 818 static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi, 819 struct exynos_dsi_transfer *xfer) 820 { 821 u8 *payload = xfer->rx_payload + xfer->rx_done; 822 bool first = !xfer->rx_done; 823 struct device *dev = dsi->dev; 824 u16 length; 825 u32 reg; 826 827 if (first) { 828 reg = readl(dsi->reg_base + DSIM_RXFIFO_REG); 829 830 switch (reg & 0x3f) { 831 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 832 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 833 if (xfer->rx_len >= 2) { 834 payload[1] = reg >> 16; 835 ++xfer->rx_done; 836 } 837 /* Fall through */ 838 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 839 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 840 payload[0] = reg >> 8; 841 ++xfer->rx_done; 842 xfer->rx_len = xfer->rx_done; 843 xfer->result = 0; 844 goto clear_fifo; 845 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 846 dev_err(dev, "DSI Error Report: 0x%04x\n", 847 (reg >> 8) & 0xffff); 848 xfer->result = 0; 849 goto clear_fifo; 850 } 851 852 length = (reg >> 8) & 0xffff; 853 if (length > xfer->rx_len) { 854 dev_err(dev, 855 "response too long (%u > %u bytes), stripping\n", 856 xfer->rx_len, length); 857 length = xfer->rx_len; 858 } else if (length < xfer->rx_len) 859 xfer->rx_len = length; 860 } 861 862 length = xfer->rx_len - xfer->rx_done; 863 xfer->rx_done += length; 864 865 /* Receive payload */ 866 while (length >= 4) { 867 reg = readl(dsi->reg_base + DSIM_RXFIFO_REG); 868 payload[0] = (reg >> 0) & 0xff; 869 payload[1] = (reg >> 8) & 0xff; 870 payload[2] = (reg >> 16) & 0xff; 871 payload[3] = (reg >> 24) & 0xff; 872 payload += 4; 873 length -= 4; 874 } 875 876 if (length) { 877 reg = readl(dsi->reg_base + DSIM_RXFIFO_REG); 878 switch (length) { 879 case 3: 880 payload[2] = (reg >> 16) & 0xff; 881 /* Fall through */ 882 case 2: 883 payload[1] = (reg >> 8) & 0xff; 884 /* Fall through */ 885 case 1: 886 payload[0] = reg & 0xff; 887 } 888 } 889 890 if (xfer->rx_done == xfer->rx_len) 891 xfer->result = 0; 892 893 clear_fifo: 894 length = DSI_RX_FIFO_SIZE / 4; 895 do { 896 reg = readl(dsi->reg_base + DSIM_RXFIFO_REG); 897 if (reg == DSI_RX_FIFO_EMPTY) 898 break; 899 } while (--length); 900 } 901 902 static void exynos_dsi_transfer_start(struct exynos_dsi *dsi) 903 { 904 unsigned long flags; 905 struct exynos_dsi_transfer *xfer; 906 bool start = false; 907 908 again: 909 spin_lock_irqsave(&dsi->transfer_lock, flags); 910 911 if (list_empty(&dsi->transfer_list)) { 912 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 913 return; 914 } 915 916 xfer = list_first_entry(&dsi->transfer_list, 917 struct exynos_dsi_transfer, list); 918 919 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 920 921 if (xfer->tx_len && xfer->tx_done == xfer->tx_len) 922 /* waiting for RX */ 923 return; 924 925 exynos_dsi_send_to_fifo(dsi, xfer); 926 927 if (xfer->tx_len || xfer->rx_len) 928 return; 929 930 xfer->result = 0; 931 complete(&xfer->completed); 932 933 spin_lock_irqsave(&dsi->transfer_lock, flags); 934 935 list_del_init(&xfer->list); 936 start = !list_empty(&dsi->transfer_list); 937 938 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 939 940 if (start) 941 goto again; 942 } 943 944 static bool exynos_dsi_transfer_finish(struct exynos_dsi *dsi) 945 { 946 struct exynos_dsi_transfer *xfer; 947 unsigned long flags; 948 bool start = true; 949 950 spin_lock_irqsave(&dsi->transfer_lock, flags); 951 952 if (list_empty(&dsi->transfer_list)) { 953 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 954 return false; 955 } 956 957 xfer = list_first_entry(&dsi->transfer_list, 958 struct exynos_dsi_transfer, list); 959 960 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 961 962 dev_dbg(dsi->dev, 963 "> xfer %p, tx_len %u, tx_done %u, rx_len %u, rx_done %u\n", 964 xfer, xfer->tx_len, xfer->tx_done, xfer->rx_len, xfer->rx_done); 965 966 if (xfer->tx_done != xfer->tx_len) 967 return true; 968 969 if (xfer->rx_done != xfer->rx_len) 970 exynos_dsi_read_from_fifo(dsi, xfer); 971 972 if (xfer->rx_done != xfer->rx_len) 973 return true; 974 975 spin_lock_irqsave(&dsi->transfer_lock, flags); 976 977 list_del_init(&xfer->list); 978 start = !list_empty(&dsi->transfer_list); 979 980 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 981 982 if (!xfer->rx_len) 983 xfer->result = 0; 984 complete(&xfer->completed); 985 986 return start; 987 } 988 989 static void exynos_dsi_remove_transfer(struct exynos_dsi *dsi, 990 struct exynos_dsi_transfer *xfer) 991 { 992 unsigned long flags; 993 bool start; 994 995 spin_lock_irqsave(&dsi->transfer_lock, flags); 996 997 if (!list_empty(&dsi->transfer_list) && 998 xfer == list_first_entry(&dsi->transfer_list, 999 struct exynos_dsi_transfer, list)) { 1000 list_del_init(&xfer->list); 1001 start = !list_empty(&dsi->transfer_list); 1002 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1003 if (start) 1004 exynos_dsi_transfer_start(dsi); 1005 return; 1006 } 1007 1008 list_del_init(&xfer->list); 1009 1010 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1011 } 1012 1013 static int exynos_dsi_transfer(struct exynos_dsi *dsi, 1014 struct exynos_dsi_transfer *xfer) 1015 { 1016 unsigned long flags; 1017 bool stopped; 1018 1019 xfer->tx_done = 0; 1020 xfer->rx_done = 0; 1021 xfer->result = -ETIMEDOUT; 1022 init_completion(&xfer->completed); 1023 1024 spin_lock_irqsave(&dsi->transfer_lock, flags); 1025 1026 stopped = list_empty(&dsi->transfer_list); 1027 list_add_tail(&xfer->list, &dsi->transfer_list); 1028 1029 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1030 1031 if (stopped) 1032 exynos_dsi_transfer_start(dsi); 1033 1034 wait_for_completion_timeout(&xfer->completed, 1035 msecs_to_jiffies(DSI_XFER_TIMEOUT_MS)); 1036 if (xfer->result == -ETIMEDOUT) { 1037 exynos_dsi_remove_transfer(dsi, xfer); 1038 dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 2, xfer->data, 1039 xfer->tx_len, xfer->tx_payload); 1040 return -ETIMEDOUT; 1041 } 1042 1043 /* Also covers hardware timeout condition */ 1044 return xfer->result; 1045 } 1046 1047 static irqreturn_t exynos_dsi_irq(int irq, void *dev_id) 1048 { 1049 struct exynos_dsi *dsi = dev_id; 1050 u32 status; 1051 1052 status = readl(dsi->reg_base + DSIM_INTSRC_REG); 1053 if (!status) { 1054 static unsigned long int j; 1055 if (printk_timed_ratelimit(&j, 500)) 1056 dev_warn(dsi->dev, "spurious interrupt\n"); 1057 return IRQ_HANDLED; 1058 } 1059 writel(status, dsi->reg_base + DSIM_INTSRC_REG); 1060 1061 if (status & DSIM_INT_SW_RST_RELEASE) { 1062 u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY); 1063 writel(mask, dsi->reg_base + DSIM_INTMSK_REG); 1064 complete(&dsi->completed); 1065 return IRQ_HANDLED; 1066 } 1067 1068 if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY))) 1069 return IRQ_HANDLED; 1070 1071 if (exynos_dsi_transfer_finish(dsi)) 1072 exynos_dsi_transfer_start(dsi); 1073 1074 return IRQ_HANDLED; 1075 } 1076 1077 static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id) 1078 { 1079 struct exynos_dsi *dsi = (struct exynos_dsi *)dev_id; 1080 struct drm_encoder *encoder = dsi->encoder; 1081 1082 if (dsi->state & DSIM_STATE_ENABLED) 1083 exynos_drm_crtc_te_handler(encoder->crtc); 1084 1085 return IRQ_HANDLED; 1086 } 1087 1088 static void exynos_dsi_enable_irq(struct exynos_dsi *dsi) 1089 { 1090 enable_irq(dsi->irq); 1091 1092 if (gpio_is_valid(dsi->te_gpio)) 1093 enable_irq(gpio_to_irq(dsi->te_gpio)); 1094 } 1095 1096 static void exynos_dsi_disable_irq(struct exynos_dsi *dsi) 1097 { 1098 if (gpio_is_valid(dsi->te_gpio)) 1099 disable_irq(gpio_to_irq(dsi->te_gpio)); 1100 1101 disable_irq(dsi->irq); 1102 } 1103 1104 static int exynos_dsi_init(struct exynos_dsi *dsi) 1105 { 1106 exynos_dsi_reset(dsi); 1107 exynos_dsi_enable_irq(dsi); 1108 exynos_dsi_enable_clock(dsi); 1109 exynos_dsi_wait_for_reset(dsi); 1110 exynos_dsi_set_phy_ctrl(dsi); 1111 exynos_dsi_init_link(dsi); 1112 1113 return 0; 1114 } 1115 1116 static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi) 1117 { 1118 int ret; 1119 1120 dsi->te_gpio = of_get_named_gpio(dsi->panel_node, "te-gpios", 0); 1121 if (!gpio_is_valid(dsi->te_gpio)) { 1122 dev_err(dsi->dev, "no te-gpios specified\n"); 1123 ret = dsi->te_gpio; 1124 goto out; 1125 } 1126 1127 ret = gpio_request_one(dsi->te_gpio, GPIOF_IN, "te_gpio"); 1128 if (ret) { 1129 dev_err(dsi->dev, "gpio request failed with %d\n", ret); 1130 goto out; 1131 } 1132 1133 /* 1134 * This TE GPIO IRQ should not be set to IRQ_NOAUTOEN, because panel 1135 * calls drm_panel_init() first then calls mipi_dsi_attach() in probe(). 1136 * It means that te_gpio is invalid when exynos_dsi_enable_irq() is 1137 * called by drm_panel_init() before panel is attached. 1138 */ 1139 ret = request_threaded_irq(gpio_to_irq(dsi->te_gpio), 1140 exynos_dsi_te_irq_handler, NULL, 1141 IRQF_TRIGGER_RISING, "TE", dsi); 1142 if (ret) { 1143 dev_err(dsi->dev, "request interrupt failed with %d\n", ret); 1144 gpio_free(dsi->te_gpio); 1145 goto out; 1146 } 1147 1148 out: 1149 return ret; 1150 } 1151 1152 static void exynos_dsi_unregister_te_irq(struct exynos_dsi *dsi) 1153 { 1154 if (gpio_is_valid(dsi->te_gpio)) { 1155 free_irq(gpio_to_irq(dsi->te_gpio), dsi); 1156 gpio_free(dsi->te_gpio); 1157 dsi->te_gpio = -ENOENT; 1158 } 1159 } 1160 1161 static int exynos_dsi_host_attach(struct mipi_dsi_host *host, 1162 struct mipi_dsi_device *device) 1163 { 1164 struct exynos_dsi *dsi = host_to_dsi(host); 1165 1166 dsi->lanes = device->lanes; 1167 dsi->format = device->format; 1168 dsi->mode_flags = device->mode_flags; 1169 dsi->panel_node = device->dev.of_node; 1170 1171 if (dsi->connector.dev) 1172 drm_helper_hpd_irq_event(dsi->connector.dev); 1173 1174 /* 1175 * This is a temporary solution and should be made by more generic way. 1176 * 1177 * If attached panel device is for command mode one, dsi should register 1178 * TE interrupt handler. 1179 */ 1180 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) { 1181 int ret = exynos_dsi_register_te_irq(dsi); 1182 1183 if (ret) 1184 return ret; 1185 } 1186 1187 return 0; 1188 } 1189 1190 static int exynos_dsi_host_detach(struct mipi_dsi_host *host, 1191 struct mipi_dsi_device *device) 1192 { 1193 struct exynos_dsi *dsi = host_to_dsi(host); 1194 1195 exynos_dsi_unregister_te_irq(dsi); 1196 1197 dsi->panel_node = NULL; 1198 1199 if (dsi->connector.dev) 1200 drm_helper_hpd_irq_event(dsi->connector.dev); 1201 1202 return 0; 1203 } 1204 1205 /* distinguish between short and long DSI packet types */ 1206 static bool exynos_dsi_is_short_dsi_type(u8 type) 1207 { 1208 return (type & 0x0f) <= 8; 1209 } 1210 1211 static ssize_t exynos_dsi_host_transfer(struct mipi_dsi_host *host, 1212 struct mipi_dsi_msg *msg) 1213 { 1214 struct exynos_dsi *dsi = host_to_dsi(host); 1215 struct exynos_dsi_transfer xfer; 1216 int ret; 1217 1218 if (!(dsi->state & DSIM_STATE_INITIALIZED)) { 1219 ret = exynos_dsi_init(dsi); 1220 if (ret) 1221 return ret; 1222 dsi->state |= DSIM_STATE_INITIALIZED; 1223 } 1224 1225 if (msg->tx_len == 0) 1226 return -EINVAL; 1227 1228 xfer.data_id = msg->type | (msg->channel << 6); 1229 1230 if (exynos_dsi_is_short_dsi_type(msg->type)) { 1231 const char *tx_buf = msg->tx_buf; 1232 1233 if (msg->tx_len > 2) 1234 return -EINVAL; 1235 xfer.tx_len = 0; 1236 xfer.data[0] = tx_buf[0]; 1237 xfer.data[1] = (msg->tx_len == 2) ? tx_buf[1] : 0; 1238 } else { 1239 xfer.tx_len = msg->tx_len; 1240 xfer.data[0] = msg->tx_len & 0xff; 1241 xfer.data[1] = msg->tx_len >> 8; 1242 xfer.tx_payload = msg->tx_buf; 1243 } 1244 1245 xfer.rx_len = msg->rx_len; 1246 xfer.rx_payload = msg->rx_buf; 1247 xfer.flags = msg->flags; 1248 1249 ret = exynos_dsi_transfer(dsi, &xfer); 1250 return (ret < 0) ? ret : xfer.rx_done; 1251 } 1252 1253 static const struct mipi_dsi_host_ops exynos_dsi_ops = { 1254 .attach = exynos_dsi_host_attach, 1255 .detach = exynos_dsi_host_detach, 1256 .transfer = exynos_dsi_host_transfer, 1257 }; 1258 1259 static int exynos_dsi_poweron(struct exynos_dsi *dsi) 1260 { 1261 int ret; 1262 1263 ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 1264 if (ret < 0) { 1265 dev_err(dsi->dev, "cannot enable regulators %d\n", ret); 1266 return ret; 1267 } 1268 1269 ret = clk_prepare_enable(dsi->bus_clk); 1270 if (ret < 0) { 1271 dev_err(dsi->dev, "cannot enable bus clock %d\n", ret); 1272 goto err_bus_clk; 1273 } 1274 1275 ret = clk_prepare_enable(dsi->pll_clk); 1276 if (ret < 0) { 1277 dev_err(dsi->dev, "cannot enable pll clock %d\n", ret); 1278 goto err_pll_clk; 1279 } 1280 1281 ret = phy_power_on(dsi->phy); 1282 if (ret < 0) { 1283 dev_err(dsi->dev, "cannot enable phy %d\n", ret); 1284 goto err_phy; 1285 } 1286 1287 return 0; 1288 1289 err_phy: 1290 clk_disable_unprepare(dsi->pll_clk); 1291 err_pll_clk: 1292 clk_disable_unprepare(dsi->bus_clk); 1293 err_bus_clk: 1294 regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 1295 1296 return ret; 1297 } 1298 1299 static void exynos_dsi_poweroff(struct exynos_dsi *dsi) 1300 { 1301 int ret; 1302 1303 usleep_range(10000, 20000); 1304 1305 if (dsi->state & DSIM_STATE_INITIALIZED) { 1306 dsi->state &= ~DSIM_STATE_INITIALIZED; 1307 1308 exynos_dsi_disable_clock(dsi); 1309 1310 exynos_dsi_disable_irq(dsi); 1311 } 1312 1313 dsi->state &= ~DSIM_STATE_CMD_LPM; 1314 1315 phy_power_off(dsi->phy); 1316 1317 clk_disable_unprepare(dsi->pll_clk); 1318 clk_disable_unprepare(dsi->bus_clk); 1319 1320 ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 1321 if (ret < 0) 1322 dev_err(dsi->dev, "cannot disable regulators %d\n", ret); 1323 } 1324 1325 static int exynos_dsi_enable(struct exynos_dsi *dsi) 1326 { 1327 int ret; 1328 1329 if (dsi->state & DSIM_STATE_ENABLED) 1330 return 0; 1331 1332 ret = exynos_dsi_poweron(dsi); 1333 if (ret < 0) 1334 return ret; 1335 1336 ret = drm_panel_prepare(dsi->panel); 1337 if (ret < 0) { 1338 exynos_dsi_poweroff(dsi); 1339 return ret; 1340 } 1341 1342 exynos_dsi_set_display_mode(dsi); 1343 exynos_dsi_set_display_enable(dsi, true); 1344 1345 ret = drm_panel_enable(dsi->panel); 1346 if (ret < 0) { 1347 exynos_dsi_set_display_enable(dsi, false); 1348 drm_panel_unprepare(dsi->panel); 1349 exynos_dsi_poweroff(dsi); 1350 return ret; 1351 } 1352 1353 dsi->state |= DSIM_STATE_ENABLED; 1354 1355 return 0; 1356 } 1357 1358 static void exynos_dsi_disable(struct exynos_dsi *dsi) 1359 { 1360 if (!(dsi->state & DSIM_STATE_ENABLED)) 1361 return; 1362 1363 drm_panel_disable(dsi->panel); 1364 exynos_dsi_set_display_enable(dsi, false); 1365 drm_panel_unprepare(dsi->panel); 1366 exynos_dsi_poweroff(dsi); 1367 1368 dsi->state &= ~DSIM_STATE_ENABLED; 1369 } 1370 1371 static void exynos_dsi_dpms(struct exynos_drm_display *display, int mode) 1372 { 1373 struct exynos_dsi *dsi = display->ctx; 1374 1375 if (dsi->panel) { 1376 switch (mode) { 1377 case DRM_MODE_DPMS_ON: 1378 exynos_dsi_enable(dsi); 1379 break; 1380 case DRM_MODE_DPMS_STANDBY: 1381 case DRM_MODE_DPMS_SUSPEND: 1382 case DRM_MODE_DPMS_OFF: 1383 exynos_dsi_disable(dsi); 1384 break; 1385 default: 1386 break; 1387 } 1388 } 1389 } 1390 1391 static enum drm_connector_status 1392 exynos_dsi_detect(struct drm_connector *connector, bool force) 1393 { 1394 struct exynos_dsi *dsi = connector_to_dsi(connector); 1395 1396 if (!dsi->panel) { 1397 dsi->panel = of_drm_find_panel(dsi->panel_node); 1398 if (dsi->panel) 1399 drm_panel_attach(dsi->panel, &dsi->connector); 1400 } else if (!dsi->panel_node) { 1401 struct exynos_drm_display *display; 1402 1403 display = platform_get_drvdata(to_platform_device(dsi->dev)); 1404 exynos_dsi_dpms(display, DRM_MODE_DPMS_OFF); 1405 drm_panel_detach(dsi->panel); 1406 dsi->panel = NULL; 1407 } 1408 1409 if (dsi->panel) 1410 return connector_status_connected; 1411 1412 return connector_status_disconnected; 1413 } 1414 1415 static void exynos_dsi_connector_destroy(struct drm_connector *connector) 1416 { 1417 } 1418 1419 static struct drm_connector_funcs exynos_dsi_connector_funcs = { 1420 .dpms = drm_helper_connector_dpms, 1421 .detect = exynos_dsi_detect, 1422 .fill_modes = drm_helper_probe_single_connector_modes, 1423 .destroy = exynos_dsi_connector_destroy, 1424 }; 1425 1426 static int exynos_dsi_get_modes(struct drm_connector *connector) 1427 { 1428 struct exynos_dsi *dsi = connector_to_dsi(connector); 1429 1430 if (dsi->panel) 1431 return dsi->panel->funcs->get_modes(dsi->panel); 1432 1433 return 0; 1434 } 1435 1436 static int exynos_dsi_mode_valid(struct drm_connector *connector, 1437 struct drm_display_mode *mode) 1438 { 1439 return MODE_OK; 1440 } 1441 1442 static struct drm_encoder * 1443 exynos_dsi_best_encoder(struct drm_connector *connector) 1444 { 1445 struct exynos_dsi *dsi = connector_to_dsi(connector); 1446 1447 return dsi->encoder; 1448 } 1449 1450 static struct drm_connector_helper_funcs exynos_dsi_connector_helper_funcs = { 1451 .get_modes = exynos_dsi_get_modes, 1452 .mode_valid = exynos_dsi_mode_valid, 1453 .best_encoder = exynos_dsi_best_encoder, 1454 }; 1455 1456 static int exynos_dsi_create_connector(struct exynos_drm_display *display, 1457 struct drm_encoder *encoder) 1458 { 1459 struct exynos_dsi *dsi = display->ctx; 1460 struct drm_connector *connector = &dsi->connector; 1461 int ret; 1462 1463 dsi->encoder = encoder; 1464 1465 connector->polled = DRM_CONNECTOR_POLL_HPD; 1466 1467 ret = drm_connector_init(encoder->dev, connector, 1468 &exynos_dsi_connector_funcs, 1469 DRM_MODE_CONNECTOR_DSI); 1470 if (ret) { 1471 DRM_ERROR("Failed to initialize connector with drm\n"); 1472 return ret; 1473 } 1474 1475 drm_connector_helper_add(connector, &exynos_dsi_connector_helper_funcs); 1476 drm_connector_register(connector); 1477 drm_mode_connector_attach_encoder(connector, encoder); 1478 1479 return 0; 1480 } 1481 1482 static void exynos_dsi_mode_set(struct exynos_drm_display *display, 1483 struct drm_display_mode *mode) 1484 { 1485 struct exynos_dsi *dsi = display->ctx; 1486 struct videomode *vm = &dsi->vm; 1487 1488 vm->hactive = mode->hdisplay; 1489 vm->vactive = mode->vdisplay; 1490 vm->vfront_porch = mode->vsync_start - mode->vdisplay; 1491 vm->vback_porch = mode->vtotal - mode->vsync_end; 1492 vm->vsync_len = mode->vsync_end - mode->vsync_start; 1493 vm->hfront_porch = mode->hsync_start - mode->hdisplay; 1494 vm->hback_porch = mode->htotal - mode->hsync_end; 1495 vm->hsync_len = mode->hsync_end - mode->hsync_start; 1496 } 1497 1498 static struct exynos_drm_display_ops exynos_dsi_display_ops = { 1499 .create_connector = exynos_dsi_create_connector, 1500 .mode_set = exynos_dsi_mode_set, 1501 .dpms = exynos_dsi_dpms 1502 }; 1503 1504 static struct exynos_drm_display exynos_dsi_display = { 1505 .type = EXYNOS_DISPLAY_TYPE_LCD, 1506 .ops = &exynos_dsi_display_ops, 1507 }; 1508 MODULE_DEVICE_TABLE(of, exynos_dsi_of_match); 1509 1510 /* of_* functions will be removed after merge of of_graph patches */ 1511 static struct device_node * 1512 of_get_child_by_name_reg(struct device_node *parent, const char *name, u32 reg) 1513 { 1514 struct device_node *np; 1515 1516 for_each_child_of_node(parent, np) { 1517 u32 r; 1518 1519 if (!np->name || of_node_cmp(np->name, name)) 1520 continue; 1521 1522 if (of_property_read_u32(np, "reg", &r) < 0) 1523 r = 0; 1524 1525 if (reg == r) 1526 break; 1527 } 1528 1529 return np; 1530 } 1531 1532 static struct device_node *of_graph_get_port_by_reg(struct device_node *parent, 1533 u32 reg) 1534 { 1535 struct device_node *ports, *port; 1536 1537 ports = of_get_child_by_name(parent, "ports"); 1538 if (ports) 1539 parent = ports; 1540 1541 port = of_get_child_by_name_reg(parent, "port", reg); 1542 1543 of_node_put(ports); 1544 1545 return port; 1546 } 1547 1548 static struct device_node * 1549 of_graph_get_endpoint_by_reg(struct device_node *port, u32 reg) 1550 { 1551 return of_get_child_by_name_reg(port, "endpoint", reg); 1552 } 1553 1554 static int exynos_dsi_of_read_u32(const struct device_node *np, 1555 const char *propname, u32 *out_value) 1556 { 1557 int ret = of_property_read_u32(np, propname, out_value); 1558 1559 if (ret < 0) 1560 pr_err("%s: failed to get '%s' property\n", np->full_name, 1561 propname); 1562 1563 return ret; 1564 } 1565 1566 enum { 1567 DSI_PORT_IN, 1568 DSI_PORT_OUT 1569 }; 1570 1571 static int exynos_dsi_parse_dt(struct exynos_dsi *dsi) 1572 { 1573 struct device *dev = dsi->dev; 1574 struct device_node *node = dev->of_node; 1575 struct device_node *port, *ep; 1576 int ret; 1577 1578 ret = exynos_dsi_of_read_u32(node, "samsung,pll-clock-frequency", 1579 &dsi->pll_clk_rate); 1580 if (ret < 0) 1581 return ret; 1582 1583 port = of_graph_get_port_by_reg(node, DSI_PORT_OUT); 1584 if (!port) { 1585 dev_err(dev, "no output port specified\n"); 1586 return -EINVAL; 1587 } 1588 1589 ep = of_graph_get_endpoint_by_reg(port, 0); 1590 of_node_put(port); 1591 if (!ep) { 1592 dev_err(dev, "no endpoint specified in output port\n"); 1593 return -EINVAL; 1594 } 1595 1596 ret = exynos_dsi_of_read_u32(ep, "samsung,burst-clock-frequency", 1597 &dsi->burst_clk_rate); 1598 if (ret < 0) 1599 goto end; 1600 1601 ret = exynos_dsi_of_read_u32(ep, "samsung,esc-clock-frequency", 1602 &dsi->esc_clk_rate); 1603 1604 end: 1605 of_node_put(ep); 1606 1607 return ret; 1608 } 1609 1610 static int exynos_dsi_bind(struct device *dev, struct device *master, 1611 void *data) 1612 { 1613 struct drm_device *drm_dev = data; 1614 struct exynos_dsi *dsi; 1615 int ret; 1616 1617 ret = exynos_drm_create_enc_conn(drm_dev, &exynos_dsi_display); 1618 if (ret) { 1619 DRM_ERROR("Encoder create [%d] failed with %d\n", 1620 exynos_dsi_display.type, ret); 1621 return ret; 1622 } 1623 1624 dsi = exynos_dsi_display.ctx; 1625 1626 return mipi_dsi_host_register(&dsi->dsi_host); 1627 } 1628 1629 static void exynos_dsi_unbind(struct device *dev, struct device *master, 1630 void *data) 1631 { 1632 struct exynos_dsi *dsi = exynos_dsi_display.ctx; 1633 struct drm_encoder *encoder = dsi->encoder; 1634 1635 exynos_dsi_dpms(&exynos_dsi_display, DRM_MODE_DPMS_OFF); 1636 1637 mipi_dsi_host_unregister(&dsi->dsi_host); 1638 1639 encoder->funcs->destroy(encoder); 1640 drm_connector_cleanup(&dsi->connector); 1641 } 1642 1643 static const struct component_ops exynos_dsi_component_ops = { 1644 .bind = exynos_dsi_bind, 1645 .unbind = exynos_dsi_unbind, 1646 }; 1647 1648 static int exynos_dsi_probe(struct platform_device *pdev) 1649 { 1650 struct resource *res; 1651 struct exynos_dsi *dsi; 1652 int ret; 1653 1654 ret = exynos_drm_component_add(&pdev->dev, EXYNOS_DEVICE_TYPE_CONNECTOR, 1655 exynos_dsi_display.type); 1656 if (ret) 1657 return ret; 1658 1659 dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL); 1660 if (!dsi) { 1661 dev_err(&pdev->dev, "failed to allocate dsi object.\n"); 1662 ret = -ENOMEM; 1663 goto err_del_component; 1664 } 1665 1666 /* To be checked as invalid one */ 1667 dsi->te_gpio = -ENOENT; 1668 1669 init_completion(&dsi->completed); 1670 spin_lock_init(&dsi->transfer_lock); 1671 INIT_LIST_HEAD(&dsi->transfer_list); 1672 1673 dsi->dsi_host.ops = &exynos_dsi_ops; 1674 dsi->dsi_host.dev = &pdev->dev; 1675 1676 dsi->dev = &pdev->dev; 1677 dsi->driver_data = exynos_dsi_get_driver_data(pdev); 1678 1679 ret = exynos_dsi_parse_dt(dsi); 1680 if (ret) 1681 goto err_del_component; 1682 1683 dsi->supplies[0].supply = "vddcore"; 1684 dsi->supplies[1].supply = "vddio"; 1685 ret = devm_regulator_bulk_get(&pdev->dev, ARRAY_SIZE(dsi->supplies), 1686 dsi->supplies); 1687 if (ret) { 1688 dev_info(&pdev->dev, "failed to get regulators: %d\n", ret); 1689 return -EPROBE_DEFER; 1690 } 1691 1692 dsi->pll_clk = devm_clk_get(&pdev->dev, "pll_clk"); 1693 if (IS_ERR(dsi->pll_clk)) { 1694 dev_info(&pdev->dev, "failed to get dsi pll input clock\n"); 1695 ret = PTR_ERR(dsi->pll_clk); 1696 goto err_del_component; 1697 } 1698 1699 dsi->bus_clk = devm_clk_get(&pdev->dev, "bus_clk"); 1700 if (IS_ERR(dsi->bus_clk)) { 1701 dev_info(&pdev->dev, "failed to get dsi bus clock\n"); 1702 ret = PTR_ERR(dsi->bus_clk); 1703 goto err_del_component; 1704 } 1705 1706 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1707 dsi->reg_base = devm_ioremap_resource(&pdev->dev, res); 1708 if (IS_ERR(dsi->reg_base)) { 1709 dev_err(&pdev->dev, "failed to remap io region\n"); 1710 ret = PTR_ERR(dsi->reg_base); 1711 goto err_del_component; 1712 } 1713 1714 dsi->phy = devm_phy_get(&pdev->dev, "dsim"); 1715 if (IS_ERR(dsi->phy)) { 1716 dev_info(&pdev->dev, "failed to get dsim phy\n"); 1717 ret = PTR_ERR(dsi->phy); 1718 goto err_del_component; 1719 } 1720 1721 dsi->irq = platform_get_irq(pdev, 0); 1722 if (dsi->irq < 0) { 1723 dev_err(&pdev->dev, "failed to request dsi irq resource\n"); 1724 ret = dsi->irq; 1725 goto err_del_component; 1726 } 1727 1728 irq_set_status_flags(dsi->irq, IRQ_NOAUTOEN); 1729 ret = devm_request_threaded_irq(&pdev->dev, dsi->irq, NULL, 1730 exynos_dsi_irq, IRQF_ONESHOT, 1731 dev_name(&pdev->dev), dsi); 1732 if (ret) { 1733 dev_err(&pdev->dev, "failed to request dsi irq\n"); 1734 goto err_del_component; 1735 } 1736 1737 exynos_dsi_display.ctx = dsi; 1738 1739 platform_set_drvdata(pdev, &exynos_dsi_display); 1740 1741 ret = component_add(&pdev->dev, &exynos_dsi_component_ops); 1742 if (ret) 1743 goto err_del_component; 1744 1745 return ret; 1746 1747 err_del_component: 1748 exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CONNECTOR); 1749 return ret; 1750 } 1751 1752 static int exynos_dsi_remove(struct platform_device *pdev) 1753 { 1754 component_del(&pdev->dev, &exynos_dsi_component_ops); 1755 exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CONNECTOR); 1756 1757 return 0; 1758 } 1759 1760 struct platform_driver dsi_driver = { 1761 .probe = exynos_dsi_probe, 1762 .remove = exynos_dsi_remove, 1763 .driver = { 1764 .name = "exynos-dsi", 1765 .owner = THIS_MODULE, 1766 .of_match_table = exynos_dsi_of_match, 1767 }, 1768 }; 1769 1770 MODULE_AUTHOR("Tomasz Figa <t.figa@samsung.com>"); 1771 MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>"); 1772 MODULE_DESCRIPTION("Samsung SoC MIPI DSI Master"); 1773 MODULE_LICENSE("GPL v2"); 1774