1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* drivers/gpu/drm/exynos/exynos7_drm_decon.c 3 * 4 * Copyright (C) 2014 Samsung Electronics Co.Ltd 5 * Authors: 6 * Akshu Agarwal <akshua@gmail.com> 7 * Ajay Kumar <ajaykumar.rs@samsung.com> 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/component.h> 12 #include <linux/kernel.h> 13 #include <linux/of.h> 14 #include <linux/of_address.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 18 #include <video/of_display_timing.h> 19 #include <video/of_videomode.h> 20 21 #include <drm/drm_fourcc.h> 22 #include <drm/drm_framebuffer.h> 23 #include <drm/drm_vblank.h> 24 #include <drm/exynos_drm.h> 25 26 #include "exynos_drm_crtc.h" 27 #include "exynos_drm_drv.h" 28 #include "exynos_drm_fb.h" 29 #include "exynos_drm_plane.h" 30 #include "regs-decon7.h" 31 32 /* 33 * DECON stands for Display and Enhancement controller. 34 */ 35 36 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 37 38 #define WINDOWS_NR 2 39 40 struct decon_data { 41 unsigned int vidw_buf_start_base; 42 unsigned int shadowcon_win_protect_shift; 43 unsigned int wincon_burstlen_shift; 44 }; 45 46 static const struct decon_data exynos7_decon_data = { 47 .vidw_buf_start_base = 0x80, 48 .shadowcon_win_protect_shift = 10, 49 .wincon_burstlen_shift = 11, 50 }; 51 52 static const struct decon_data exynos7870_decon_data = { 53 .vidw_buf_start_base = 0x880, 54 .shadowcon_win_protect_shift = 8, 55 .wincon_burstlen_shift = 10, 56 }; 57 58 struct decon_context { 59 struct device *dev; 60 struct drm_device *drm_dev; 61 void *dma_priv; 62 struct exynos_drm_crtc *crtc; 63 struct exynos_drm_plane planes[WINDOWS_NR]; 64 struct exynos_drm_plane_config configs[WINDOWS_NR]; 65 struct clk *pclk; 66 struct clk *aclk; 67 struct clk *eclk; 68 struct clk *vclk; 69 void __iomem *regs; 70 unsigned long irq_flags; 71 bool i80_if; 72 wait_queue_head_t wait_vsync_queue; 73 atomic_t wait_vsync_event; 74 75 const struct decon_data *data; 76 struct drm_encoder *encoder; 77 }; 78 79 static const struct of_device_id decon_driver_dt_match[] = { 80 { 81 .compatible = "samsung,exynos7-decon", 82 .data = &exynos7_decon_data, 83 }, 84 { 85 .compatible = "samsung,exynos7870-decon", 86 .data = &exynos7870_decon_data, 87 }, 88 {}, 89 }; 90 MODULE_DEVICE_TABLE(of, decon_driver_dt_match); 91 92 static const uint32_t decon_formats[] = { 93 DRM_FORMAT_RGB565, 94 DRM_FORMAT_XRGB8888, 95 DRM_FORMAT_XBGR8888, 96 DRM_FORMAT_RGBX8888, 97 DRM_FORMAT_BGRX8888, 98 DRM_FORMAT_ARGB8888, 99 DRM_FORMAT_ABGR8888, 100 DRM_FORMAT_RGBA8888, 101 DRM_FORMAT_BGRA8888, 102 }; 103 104 static const enum drm_plane_type decon_win_types[WINDOWS_NR] = { 105 DRM_PLANE_TYPE_PRIMARY, 106 DRM_PLANE_TYPE_CURSOR, 107 }; 108 109 /** 110 * decon_shadow_protect_win() - disable updating values from shadow registers at vsync 111 * 112 * @ctx: display and enhancement controller context 113 * @win: window to protect registers for 114 * @protect: 1 to protect (disable updates) 115 */ 116 static void decon_shadow_protect_win(struct decon_context *ctx, 117 unsigned int win, bool protect) 118 { 119 u32 bits, val; 120 unsigned int shift = ctx->data->shadowcon_win_protect_shift; 121 122 bits = SHADOWCON_WINx_PROTECT(shift, win); 123 124 val = readl(ctx->regs + SHADOWCON); 125 if (protect) 126 val |= bits; 127 else 128 val &= ~bits; 129 writel(val, ctx->regs + SHADOWCON); 130 } 131 132 static void decon_wait_for_vblank(struct decon_context *ctx) 133 { 134 atomic_set(&ctx->wait_vsync_event, 1); 135 136 /* 137 * wait for DECON to signal VSYNC interrupt or return after 138 * timeout which is set to 50ms (refresh rate of 20). 139 */ 140 if (!wait_event_timeout(ctx->wait_vsync_queue, 141 !atomic_read(&ctx->wait_vsync_event), 142 HZ/20)) 143 DRM_DEV_DEBUG_KMS(ctx->dev, "vblank wait timed out.\n"); 144 } 145 146 static void decon_clear_channels(struct decon_context *ctx) 147 { 148 unsigned int win, ch_enabled = 0; 149 u32 val; 150 151 /* Check if any channel is enabled. */ 152 for (win = 0; win < WINDOWS_NR; win++) { 153 val = readl(ctx->regs + WINCON(win)); 154 155 if (val & WINCONx_ENWIN) { 156 decon_shadow_protect_win(ctx, win, true); 157 158 val &= ~WINCONx_ENWIN; 159 writel(val, ctx->regs + WINCON(win)); 160 ch_enabled = 1; 161 162 decon_shadow_protect_win(ctx, win, false); 163 } 164 } 165 166 val = readl(ctx->regs + DECON_UPDATE); 167 val |= DECON_UPDATE_STANDALONE_F; 168 writel(val, ctx->regs + DECON_UPDATE); 169 170 /* Wait for vsync, as disable channel takes effect at next vsync */ 171 if (ch_enabled) 172 decon_wait_for_vblank(ctx); 173 } 174 175 static int decon_ctx_initialize(struct decon_context *ctx, 176 struct drm_device *drm_dev) 177 { 178 ctx->drm_dev = drm_dev; 179 180 decon_clear_channels(ctx); 181 182 return exynos_drm_register_dma(drm_dev, ctx->dev, &ctx->dma_priv); 183 } 184 185 static void decon_ctx_remove(struct decon_context *ctx) 186 { 187 /* detach this sub driver from iommu mapping if supported. */ 188 exynos_drm_unregister_dma(ctx->drm_dev, ctx->dev, &ctx->dma_priv); 189 } 190 191 static u32 decon_calc_clkdiv(struct decon_context *ctx, 192 const struct drm_display_mode *mode) 193 { 194 unsigned long ideal_clk = mode->clock * 1000; 195 u32 clkdiv; 196 197 /* Find the clock divider value that gets us closest to ideal_clk */ 198 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->vclk), ideal_clk); 199 200 return (clkdiv < 0x100) ? clkdiv : 0xff; 201 } 202 203 static void decon_commit(struct exynos_drm_crtc *crtc) 204 { 205 struct decon_context *ctx = crtc->ctx; 206 struct drm_display_mode *mode = &crtc->base.state->adjusted_mode; 207 u32 val, clkdiv; 208 209 /* nothing to do if we haven't set the mode yet */ 210 if (mode->htotal == 0 || mode->vtotal == 0) 211 return; 212 213 if (!ctx->i80_if) { 214 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd; 215 /* setup vertical timing values. */ 216 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 217 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end; 218 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay; 219 220 val = VIDTCON0_VBPD(vbpd - 1) | VIDTCON0_VFPD(vfpd - 1); 221 writel(val, ctx->regs + VIDTCON0); 222 223 val = VIDTCON1_VSPW(vsync_len - 1); 224 writel(val, ctx->regs + VIDTCON1); 225 226 /* setup horizontal timing values. */ 227 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 228 hbpd = mode->crtc_htotal - mode->crtc_hsync_end; 229 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay; 230 231 /* setup horizontal timing values. */ 232 val = VIDTCON2_HBPD(hbpd - 1) | VIDTCON2_HFPD(hfpd - 1); 233 writel(val, ctx->regs + VIDTCON2); 234 235 val = VIDTCON3_HSPW(hsync_len - 1); 236 writel(val, ctx->regs + VIDTCON3); 237 } 238 239 /* setup horizontal and vertical display size. */ 240 val = VIDTCON4_LINEVAL(mode->vdisplay - 1) | 241 VIDTCON4_HOZVAL(mode->hdisplay - 1); 242 writel(val, ctx->regs + VIDTCON4); 243 244 writel(mode->vdisplay - 1, ctx->regs + LINECNT_OP_THRESHOLD); 245 246 /* 247 * fields of register with prefix '_F' would be updated 248 * at vsync(same as dma start) 249 */ 250 val = VIDCON0_ENVID | VIDCON0_ENVID_F; 251 writel(val, ctx->regs + VIDCON0); 252 253 clkdiv = decon_calc_clkdiv(ctx, mode); 254 if (clkdiv > 1) { 255 val = VCLKCON1_CLKVAL_NUM_VCLK(clkdiv - 1); 256 writel(val, ctx->regs + VCLKCON1); 257 writel(val, ctx->regs + VCLKCON2); 258 } 259 260 val = readl(ctx->regs + DECON_UPDATE); 261 val |= DECON_UPDATE_STANDALONE_F; 262 writel(val, ctx->regs + DECON_UPDATE); 263 } 264 265 static int decon_enable_vblank(struct exynos_drm_crtc *crtc) 266 { 267 struct decon_context *ctx = crtc->ctx; 268 u32 val; 269 270 if (!test_and_set_bit(0, &ctx->irq_flags)) { 271 val = readl(ctx->regs + VIDINTCON0); 272 273 val |= VIDINTCON0_INT_ENABLE; 274 275 if (!ctx->i80_if) { 276 val |= VIDINTCON0_INT_FRAME; 277 val &= ~VIDINTCON0_FRAMESEL0_MASK; 278 val |= VIDINTCON0_FRAMESEL0_VSYNC; 279 } 280 281 writel(val, ctx->regs + VIDINTCON0); 282 } 283 284 return 0; 285 } 286 287 static void decon_disable_vblank(struct exynos_drm_crtc *crtc) 288 { 289 struct decon_context *ctx = crtc->ctx; 290 u32 val; 291 292 if (test_and_clear_bit(0, &ctx->irq_flags)) { 293 val = readl(ctx->regs + VIDINTCON0); 294 295 val &= ~VIDINTCON0_INT_ENABLE; 296 if (!ctx->i80_if) 297 val &= ~VIDINTCON0_INT_FRAME; 298 299 writel(val, ctx->regs + VIDINTCON0); 300 } 301 } 302 303 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win, 304 struct drm_framebuffer *fb) 305 { 306 unsigned long val; 307 int padding; 308 unsigned int shift = ctx->data->wincon_burstlen_shift; 309 310 val = readl(ctx->regs + WINCON(win)); 311 val &= ~WINCONx_BPPMODE_MASK; 312 313 switch (fb->format->format) { 314 case DRM_FORMAT_RGB565: 315 val |= WINCONx_BPPMODE_16BPP_565; 316 val |= WINCONx_BURSTLEN_16WORD(shift); 317 break; 318 case DRM_FORMAT_XRGB8888: 319 val |= WINCONx_BPPMODE_24BPP_xRGB; 320 val |= WINCONx_BURSTLEN_16WORD(shift); 321 break; 322 case DRM_FORMAT_XBGR8888: 323 val |= WINCONx_BPPMODE_24BPP_xBGR; 324 val |= WINCONx_BURSTLEN_16WORD(shift); 325 break; 326 case DRM_FORMAT_RGBX8888: 327 val |= WINCONx_BPPMODE_24BPP_RGBx; 328 val |= WINCONx_BURSTLEN_16WORD(shift); 329 break; 330 case DRM_FORMAT_BGRX8888: 331 val |= WINCONx_BPPMODE_24BPP_BGRx; 332 val |= WINCONx_BURSTLEN_16WORD(shift); 333 break; 334 case DRM_FORMAT_ARGB8888: 335 val |= WINCONx_BPPMODE_32BPP_ARGB | WINCONx_BLD_PIX | 336 WINCONx_ALPHA_SEL; 337 val |= WINCONx_BURSTLEN_16WORD(shift); 338 break; 339 case DRM_FORMAT_ABGR8888: 340 val |= WINCONx_BPPMODE_32BPP_ABGR | WINCONx_BLD_PIX | 341 WINCONx_ALPHA_SEL; 342 val |= WINCONx_BURSTLEN_16WORD(shift); 343 break; 344 case DRM_FORMAT_RGBA8888: 345 val |= WINCONx_BPPMODE_32BPP_RGBA | WINCONx_BLD_PIX | 346 WINCONx_ALPHA_SEL; 347 val |= WINCONx_BURSTLEN_16WORD(shift); 348 break; 349 case DRM_FORMAT_BGRA8888: 350 default: 351 val |= WINCONx_BPPMODE_32BPP_BGRA | WINCONx_BLD_PIX | 352 WINCONx_ALPHA_SEL; 353 val |= WINCONx_BURSTLEN_16WORD(shift); 354 break; 355 } 356 357 DRM_DEV_DEBUG_KMS(ctx->dev, "cpp = %d\n", fb->format->cpp[0]); 358 359 /* 360 * In case of exynos, setting dma-burst to 16Word causes permanent 361 * tearing for very small buffers, e.g. cursor buffer. Burst Mode 362 * switching which is based on plane size is not recommended as 363 * plane size varies a lot towards the end of the screen and rapid 364 * movement causes unstable DMA which results into iommu crash/tear. 365 */ 366 367 padding = (fb->pitches[0] / fb->format->cpp[0]) - fb->width; 368 if (fb->width + padding < MIN_FB_WIDTH_FOR_16WORD_BURST) { 369 val &= ~WINCONx_BURSTLEN_MASK(shift); 370 val |= WINCONx_BURSTLEN_8WORD(shift); 371 } 372 373 writel(val, ctx->regs + WINCON(win)); 374 } 375 376 static void decon_win_set_colkey(struct decon_context *ctx, unsigned int win) 377 { 378 unsigned int keycon0 = 0, keycon1 = 0; 379 380 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F | 381 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0); 382 383 keycon1 = WxKEYCON1_COLVAL(0xffffffff); 384 385 writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); 386 writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); 387 } 388 389 static void decon_atomic_begin(struct exynos_drm_crtc *crtc) 390 { 391 struct decon_context *ctx = crtc->ctx; 392 int i; 393 394 for (i = 0; i < WINDOWS_NR; i++) 395 decon_shadow_protect_win(ctx, i, true); 396 } 397 398 static void decon_update_plane(struct exynos_drm_crtc *crtc, 399 struct exynos_drm_plane *plane) 400 { 401 struct exynos_drm_plane_state *state = 402 to_exynos_plane_state(plane->base.state); 403 struct decon_context *ctx = crtc->ctx; 404 struct drm_framebuffer *fb = state->base.fb; 405 int padding; 406 unsigned long val, alpha; 407 unsigned int last_x; 408 unsigned int last_y; 409 unsigned int win = plane->index; 410 unsigned int cpp = fb->format->cpp[0]; 411 unsigned int pitch = fb->pitches[0]; 412 unsigned int vidw_addr0_base = ctx->data->vidw_buf_start_base; 413 414 /* 415 * SHADOWCON/PRTCON register is used for enabling timing. 416 * 417 * for example, once only width value of a register is set, 418 * if the dma is started then decon hardware could malfunction so 419 * with protect window setting, the register fields with prefix '_F' 420 * wouldn't be updated at vsync also but updated once unprotect window 421 * is set. 422 */ 423 424 /* buffer start address */ 425 val = (unsigned long)exynos_drm_fb_dma_addr(fb, 0); 426 writel(val, ctx->regs + VIDW_BUF_START(vidw_addr0_base, win)); 427 428 padding = (pitch / cpp) - fb->width; 429 430 /* buffer size */ 431 writel(fb->width + padding, ctx->regs + VIDW_WHOLE_X(win)); 432 writel(fb->height, ctx->regs + VIDW_WHOLE_Y(win)); 433 434 /* offset from the start of the buffer to read */ 435 writel(state->src.x, ctx->regs + VIDW_OFFSET_X(win)); 436 writel(state->src.y, ctx->regs + VIDW_OFFSET_Y(win)); 437 438 DRM_DEV_DEBUG_KMS(ctx->dev, "start addr = 0x%lx\n", 439 (unsigned long)val); 440 DRM_DEV_DEBUG_KMS(ctx->dev, "ovl_width = %d, ovl_height = %d\n", 441 state->crtc.w, state->crtc.h); 442 443 val = VIDOSDxA_TOPLEFT_X(state->crtc.x) | 444 VIDOSDxA_TOPLEFT_Y(state->crtc.y); 445 writel(val, ctx->regs + VIDOSD_A(win)); 446 447 last_x = state->crtc.x + state->crtc.w; 448 if (last_x) 449 last_x--; 450 last_y = state->crtc.y + state->crtc.h; 451 if (last_y) 452 last_y--; 453 454 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y); 455 456 writel(val, ctx->regs + VIDOSD_B(win)); 457 458 DRM_DEV_DEBUG_KMS(ctx->dev, "osd pos: tx = %d, ty = %d, bx = %d, by = %d\n", 459 state->crtc.x, state->crtc.y, last_x, last_y); 460 461 /* OSD alpha */ 462 alpha = VIDOSDxC_ALPHA0_R_F(0x0) | 463 VIDOSDxC_ALPHA0_G_F(0x0) | 464 VIDOSDxC_ALPHA0_B_F(0x0); 465 466 writel(alpha, ctx->regs + VIDOSD_C(win)); 467 468 alpha = VIDOSDxD_ALPHA1_R_F(0xff) | 469 VIDOSDxD_ALPHA1_G_F(0xff) | 470 VIDOSDxD_ALPHA1_B_F(0xff); 471 472 writel(alpha, ctx->regs + VIDOSD_D(win)); 473 474 decon_win_set_pixfmt(ctx, win, fb); 475 476 /* hardware window 0 doesn't support color key. */ 477 if (win != 0) 478 decon_win_set_colkey(ctx, win); 479 480 /* wincon */ 481 val = readl(ctx->regs + WINCON(win)); 482 val |= WINCONx_TRIPLE_BUF_MODE; 483 val |= WINCONx_ENWIN; 484 writel(val, ctx->regs + WINCON(win)); 485 486 /* Enable DMA channel and unprotect windows */ 487 decon_shadow_protect_win(ctx, win, false); 488 489 val = readl(ctx->regs + DECON_UPDATE); 490 val |= DECON_UPDATE_STANDALONE_F; 491 writel(val, ctx->regs + DECON_UPDATE); 492 } 493 494 static void decon_disable_plane(struct exynos_drm_crtc *crtc, 495 struct exynos_drm_plane *plane) 496 { 497 struct decon_context *ctx = crtc->ctx; 498 unsigned int win = plane->index; 499 u32 val; 500 501 /* protect windows */ 502 decon_shadow_protect_win(ctx, win, true); 503 504 /* wincon */ 505 val = readl(ctx->regs + WINCON(win)); 506 val &= ~WINCONx_ENWIN; 507 writel(val, ctx->regs + WINCON(win)); 508 509 val = readl(ctx->regs + DECON_UPDATE); 510 val |= DECON_UPDATE_STANDALONE_F; 511 writel(val, ctx->regs + DECON_UPDATE); 512 } 513 514 static void decon_atomic_flush(struct exynos_drm_crtc *crtc) 515 { 516 struct decon_context *ctx = crtc->ctx; 517 int i; 518 519 for (i = 0; i < WINDOWS_NR; i++) 520 decon_shadow_protect_win(ctx, i, false); 521 exynos_crtc_handle_event(crtc); 522 } 523 524 static void decon_init(struct decon_context *ctx) 525 { 526 u32 val; 527 528 writel(VIDCON0_SWRESET, ctx->regs + VIDCON0); 529 530 val = VIDOUTCON0_DISP_IF_0_ON; 531 if (!ctx->i80_if) 532 val |= VIDOUTCON0_RGBIF; 533 writel(val, ctx->regs + VIDOUTCON0); 534 535 writel(VCLKCON0_CLKVALUP | VCLKCON0_VCLKFREE, ctx->regs + VCLKCON0); 536 537 if (!ctx->i80_if) 538 writel(VIDCON1_VCLK_HOLD, ctx->regs + VIDCON1(0)); 539 } 540 541 static void decon_atomic_enable(struct exynos_drm_crtc *crtc) 542 { 543 struct decon_context *ctx = crtc->ctx; 544 int ret; 545 546 ret = pm_runtime_resume_and_get(ctx->dev); 547 if (ret < 0) { 548 DRM_DEV_ERROR(ctx->dev, "failed to enable DECON device.\n"); 549 return; 550 } 551 552 decon_init(ctx); 553 554 /* if vblank was enabled status, enable it again. */ 555 if (test_and_clear_bit(0, &ctx->irq_flags)) 556 decon_enable_vblank(ctx->crtc); 557 558 decon_commit(ctx->crtc); 559 } 560 561 static void decon_atomic_disable(struct exynos_drm_crtc *crtc) 562 { 563 struct decon_context *ctx = crtc->ctx; 564 int i; 565 566 /* 567 * We need to make sure that all windows are disabled before we 568 * suspend that connector. Otherwise we might try to scan from 569 * a destroyed buffer later. 570 */ 571 for (i = 0; i < WINDOWS_NR; i++) 572 decon_disable_plane(crtc, &ctx->planes[i]); 573 574 pm_runtime_put_sync(ctx->dev); 575 } 576 577 static const struct exynos_drm_crtc_ops decon_crtc_ops = { 578 .atomic_enable = decon_atomic_enable, 579 .atomic_disable = decon_atomic_disable, 580 .enable_vblank = decon_enable_vblank, 581 .disable_vblank = decon_disable_vblank, 582 .atomic_begin = decon_atomic_begin, 583 .update_plane = decon_update_plane, 584 .disable_plane = decon_disable_plane, 585 .atomic_flush = decon_atomic_flush, 586 }; 587 588 589 static irqreturn_t decon_irq_handler(int irq, void *dev_id) 590 { 591 struct decon_context *ctx = (struct decon_context *)dev_id; 592 u32 val, clear_bit; 593 594 val = readl(ctx->regs + VIDINTCON1); 595 596 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME; 597 if (val & clear_bit) 598 writel(clear_bit, ctx->regs + VIDINTCON1); 599 600 /* check the crtc is detached already from encoder */ 601 if (!ctx->drm_dev) 602 goto out; 603 604 /* check if crtc and vblank have been initialized properly */ 605 if (!drm_dev_has_vblank(ctx->drm_dev)) 606 goto out; 607 608 if (!ctx->i80_if) { 609 drm_crtc_handle_vblank(&ctx->crtc->base); 610 611 /* set wait vsync event to zero and wake up queue. */ 612 if (atomic_read(&ctx->wait_vsync_event)) { 613 atomic_set(&ctx->wait_vsync_event, 0); 614 wake_up(&ctx->wait_vsync_queue); 615 } 616 } 617 out: 618 return IRQ_HANDLED; 619 } 620 621 static int decon_bind(struct device *dev, struct device *master, void *data) 622 { 623 struct decon_context *ctx = dev_get_drvdata(dev); 624 struct drm_device *drm_dev = data; 625 struct exynos_drm_plane *exynos_plane; 626 unsigned int i; 627 int ret; 628 629 ret = decon_ctx_initialize(ctx, drm_dev); 630 if (ret) { 631 DRM_DEV_ERROR(dev, "decon_ctx_initialize failed.\n"); 632 return ret; 633 } 634 635 for (i = 0; i < WINDOWS_NR; i++) { 636 ctx->configs[i].pixel_formats = decon_formats; 637 ctx->configs[i].num_pixel_formats = ARRAY_SIZE(decon_formats); 638 ctx->configs[i].zpos = i; 639 ctx->configs[i].type = decon_win_types[i]; 640 641 ret = exynos_plane_init(drm_dev, &ctx->planes[i], i, 642 &ctx->configs[i]); 643 if (ret) 644 return ret; 645 } 646 647 exynos_plane = &ctx->planes[DEFAULT_WIN]; 648 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, 649 EXYNOS_DISPLAY_TYPE_LCD, &decon_crtc_ops, ctx); 650 if (IS_ERR(ctx->crtc)) { 651 decon_ctx_remove(ctx); 652 return PTR_ERR(ctx->crtc); 653 } 654 655 if (ctx->encoder) 656 exynos_dpi_bind(drm_dev, ctx->encoder); 657 658 return 0; 659 660 } 661 662 static void decon_unbind(struct device *dev, struct device *master, 663 void *data) 664 { 665 struct decon_context *ctx = dev_get_drvdata(dev); 666 667 decon_atomic_disable(ctx->crtc); 668 669 if (ctx->encoder) 670 exynos_dpi_remove(ctx->encoder); 671 672 decon_ctx_remove(ctx); 673 } 674 675 static const struct component_ops decon_component_ops = { 676 .bind = decon_bind, 677 .unbind = decon_unbind, 678 }; 679 680 static int decon_probe(struct platform_device *pdev) 681 { 682 struct device *dev = &pdev->dev; 683 struct decon_context *ctx; 684 struct device_node *i80_if_timings; 685 int ret; 686 687 if (!dev->of_node) 688 return -ENODEV; 689 690 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 691 if (!ctx) 692 return -ENOMEM; 693 694 ctx->dev = dev; 695 ctx->data = of_device_get_match_data(dev); 696 697 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings"); 698 if (i80_if_timings) 699 ctx->i80_if = true; 700 of_node_put(i80_if_timings); 701 702 ctx->regs = of_iomap(dev->of_node, 0); 703 if (!ctx->regs) 704 return -ENOMEM; 705 706 ctx->pclk = devm_clk_get(dev, "pclk_decon0"); 707 if (IS_ERR(ctx->pclk)) { 708 dev_err(dev, "failed to get bus clock pclk\n"); 709 ret = PTR_ERR(ctx->pclk); 710 goto err_iounmap; 711 } 712 713 ctx->aclk = devm_clk_get(dev, "aclk_decon0"); 714 if (IS_ERR(ctx->aclk)) { 715 dev_err(dev, "failed to get bus clock aclk\n"); 716 ret = PTR_ERR(ctx->aclk); 717 goto err_iounmap; 718 } 719 720 ctx->eclk = devm_clk_get(dev, "decon0_eclk"); 721 if (IS_ERR(ctx->eclk)) { 722 dev_err(dev, "failed to get eclock\n"); 723 ret = PTR_ERR(ctx->eclk); 724 goto err_iounmap; 725 } 726 727 ctx->vclk = devm_clk_get(dev, "decon0_vclk"); 728 if (IS_ERR(ctx->vclk)) { 729 dev_err(dev, "failed to get vclock\n"); 730 ret = PTR_ERR(ctx->vclk); 731 goto err_iounmap; 732 } 733 734 ret = platform_get_irq_byname(pdev, ctx->i80_if ? "lcd_sys" : "vsync"); 735 if (ret < 0) 736 goto err_iounmap; 737 738 ret = devm_request_irq(dev, ret, decon_irq_handler, 0, "drm_decon", ctx); 739 if (ret) { 740 dev_err(dev, "irq request failed.\n"); 741 goto err_iounmap; 742 } 743 744 init_waitqueue_head(&ctx->wait_vsync_queue); 745 atomic_set(&ctx->wait_vsync_event, 0); 746 747 platform_set_drvdata(pdev, ctx); 748 749 ctx->encoder = exynos_dpi_probe(dev); 750 if (IS_ERR(ctx->encoder)) { 751 ret = PTR_ERR(ctx->encoder); 752 goto err_iounmap; 753 } 754 755 pm_runtime_enable(dev); 756 757 ret = component_add(dev, &decon_component_ops); 758 if (ret) 759 goto err_disable_pm_runtime; 760 761 return ret; 762 763 err_disable_pm_runtime: 764 pm_runtime_disable(dev); 765 766 err_iounmap: 767 iounmap(ctx->regs); 768 769 return ret; 770 } 771 772 static void decon_remove(struct platform_device *pdev) 773 { 774 struct decon_context *ctx = dev_get_drvdata(&pdev->dev); 775 776 pm_runtime_disable(&pdev->dev); 777 778 iounmap(ctx->regs); 779 780 component_del(&pdev->dev, &decon_component_ops); 781 } 782 783 static int exynos7_decon_suspend(struct device *dev) 784 { 785 struct decon_context *ctx = dev_get_drvdata(dev); 786 787 clk_disable_unprepare(ctx->vclk); 788 clk_disable_unprepare(ctx->eclk); 789 clk_disable_unprepare(ctx->aclk); 790 clk_disable_unprepare(ctx->pclk); 791 792 return 0; 793 } 794 795 static int exynos7_decon_resume(struct device *dev) 796 { 797 struct decon_context *ctx = dev_get_drvdata(dev); 798 int ret; 799 800 ret = clk_prepare_enable(ctx->pclk); 801 if (ret < 0) { 802 DRM_DEV_ERROR(dev, "Failed to prepare_enable the pclk [%d]\n", 803 ret); 804 goto err_pclk_enable; 805 } 806 807 ret = clk_prepare_enable(ctx->aclk); 808 if (ret < 0) { 809 DRM_DEV_ERROR(dev, "Failed to prepare_enable the aclk [%d]\n", 810 ret); 811 goto err_aclk_enable; 812 } 813 814 ret = clk_prepare_enable(ctx->eclk); 815 if (ret < 0) { 816 DRM_DEV_ERROR(dev, "Failed to prepare_enable the eclk [%d]\n", 817 ret); 818 goto err_eclk_enable; 819 } 820 821 ret = clk_prepare_enable(ctx->vclk); 822 if (ret < 0) { 823 DRM_DEV_ERROR(dev, "Failed to prepare_enable the vclk [%d]\n", 824 ret); 825 goto err_vclk_enable; 826 } 827 828 return 0; 829 830 err_vclk_enable: 831 clk_disable_unprepare(ctx->eclk); 832 err_eclk_enable: 833 clk_disable_unprepare(ctx->aclk); 834 err_aclk_enable: 835 clk_disable_unprepare(ctx->pclk); 836 err_pclk_enable: 837 return ret; 838 } 839 840 static DEFINE_RUNTIME_DEV_PM_OPS(exynos7_decon_pm_ops, exynos7_decon_suspend, 841 exynos7_decon_resume, NULL); 842 843 struct platform_driver decon_driver = { 844 .probe = decon_probe, 845 .remove = decon_remove, 846 .driver = { 847 .name = "exynos-decon", 848 .pm = pm_ptr(&exynos7_decon_pm_ops), 849 .of_match_table = decon_driver_dt_match, 850 }, 851 }; 852