1 #ifndef STATE_HI_XML 2 #define STATE_HI_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://0x04.net/cgit/index.cgi/rules-ng-ng 8 git clone git://0x04.net/rules-ng-ng 9 10 The rules-ng-ng source files this header was generated from are: 11 - state_hi.xml ( 24309 bytes, from 2015-12-12 09:02:53) 12 - common.xml ( 18437 bytes, from 2015-12-12 09:02:53) 13 14 Copyright (C) 2015 15 */ 16 17 18 #define MMU_EXCEPTION_SLAVE_NOT_PRESENT 0x00000001 19 #define MMU_EXCEPTION_PAGE_NOT_PRESENT 0x00000002 20 #define MMU_EXCEPTION_WRITE_VIOLATION 0x00000003 21 #define VIVS_HI 0x00000000 22 23 #define VIVS_HI_CLOCK_CONTROL 0x00000000 24 #define VIVS_HI_CLOCK_CONTROL_CLK3D_DIS 0x00000001 25 #define VIVS_HI_CLOCK_CONTROL_CLK2D_DIS 0x00000002 26 #define VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK 0x000001fc 27 #define VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__SHIFT 2 28 #define VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(x) (((x) << VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__SHIFT) & VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK) 29 #define VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD 0x00000200 30 #define VIVS_HI_CLOCK_CONTROL_DISABLE_RAM_CLK_GATING 0x00000400 31 #define VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS 0x00000800 32 #define VIVS_HI_CLOCK_CONTROL_SOFT_RESET 0x00001000 33 #define VIVS_HI_CLOCK_CONTROL_IDLE_3D 0x00010000 34 #define VIVS_HI_CLOCK_CONTROL_IDLE_2D 0x00020000 35 #define VIVS_HI_CLOCK_CONTROL_IDLE_VG 0x00040000 36 #define VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU 0x00080000 37 #define VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK 0x00f00000 38 #define VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__SHIFT 20 39 #define VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE(x) (((x) << VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__SHIFT) & VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK) 40 41 #define VIVS_HI_IDLE_STATE 0x00000004 42 #define VIVS_HI_IDLE_STATE_FE 0x00000001 43 #define VIVS_HI_IDLE_STATE_DE 0x00000002 44 #define VIVS_HI_IDLE_STATE_PE 0x00000004 45 #define VIVS_HI_IDLE_STATE_SH 0x00000008 46 #define VIVS_HI_IDLE_STATE_PA 0x00000010 47 #define VIVS_HI_IDLE_STATE_SE 0x00000020 48 #define VIVS_HI_IDLE_STATE_RA 0x00000040 49 #define VIVS_HI_IDLE_STATE_TX 0x00000080 50 #define VIVS_HI_IDLE_STATE_VG 0x00000100 51 #define VIVS_HI_IDLE_STATE_IM 0x00000200 52 #define VIVS_HI_IDLE_STATE_FP 0x00000400 53 #define VIVS_HI_IDLE_STATE_TS 0x00000800 54 #define VIVS_HI_IDLE_STATE_AXI_LP 0x80000000 55 56 #define VIVS_HI_AXI_CONFIG 0x00000008 57 #define VIVS_HI_AXI_CONFIG_AWID__MASK 0x0000000f 58 #define VIVS_HI_AXI_CONFIG_AWID__SHIFT 0 59 #define VIVS_HI_AXI_CONFIG_AWID(x) (((x) << VIVS_HI_AXI_CONFIG_AWID__SHIFT) & VIVS_HI_AXI_CONFIG_AWID__MASK) 60 #define VIVS_HI_AXI_CONFIG_ARID__MASK 0x000000f0 61 #define VIVS_HI_AXI_CONFIG_ARID__SHIFT 4 62 #define VIVS_HI_AXI_CONFIG_ARID(x) (((x) << VIVS_HI_AXI_CONFIG_ARID__SHIFT) & VIVS_HI_AXI_CONFIG_ARID__MASK) 63 #define VIVS_HI_AXI_CONFIG_AWCACHE__MASK 0x00000f00 64 #define VIVS_HI_AXI_CONFIG_AWCACHE__SHIFT 8 65 #define VIVS_HI_AXI_CONFIG_AWCACHE(x) (((x) << VIVS_HI_AXI_CONFIG_AWCACHE__SHIFT) & VIVS_HI_AXI_CONFIG_AWCACHE__MASK) 66 #define VIVS_HI_AXI_CONFIG_ARCACHE__MASK 0x0000f000 67 #define VIVS_HI_AXI_CONFIG_ARCACHE__SHIFT 12 68 #define VIVS_HI_AXI_CONFIG_ARCACHE(x) (((x) << VIVS_HI_AXI_CONFIG_ARCACHE__SHIFT) & VIVS_HI_AXI_CONFIG_ARCACHE__MASK) 69 70 #define VIVS_HI_AXI_STATUS 0x0000000c 71 #define VIVS_HI_AXI_STATUS_WR_ERR_ID__MASK 0x0000000f 72 #define VIVS_HI_AXI_STATUS_WR_ERR_ID__SHIFT 0 73 #define VIVS_HI_AXI_STATUS_WR_ERR_ID(x) (((x) << VIVS_HI_AXI_STATUS_WR_ERR_ID__SHIFT) & VIVS_HI_AXI_STATUS_WR_ERR_ID__MASK) 74 #define VIVS_HI_AXI_STATUS_RD_ERR_ID__MASK 0x000000f0 75 #define VIVS_HI_AXI_STATUS_RD_ERR_ID__SHIFT 4 76 #define VIVS_HI_AXI_STATUS_RD_ERR_ID(x) (((x) << VIVS_HI_AXI_STATUS_RD_ERR_ID__SHIFT) & VIVS_HI_AXI_STATUS_RD_ERR_ID__MASK) 77 #define VIVS_HI_AXI_STATUS_DET_WR_ERR 0x00000100 78 #define VIVS_HI_AXI_STATUS_DET_RD_ERR 0x00000200 79 80 #define VIVS_HI_INTR_ACKNOWLEDGE 0x00000010 81 #define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__MASK 0x7fffffff 82 #define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__SHIFT 0 83 #define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC(x) (((x) << VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__SHIFT) & VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__MASK) 84 #define VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR 0x80000000 85 86 #define VIVS_HI_INTR_ENBL 0x00000014 87 #define VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__MASK 0xffffffff 88 #define VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__SHIFT 0 89 #define VIVS_HI_INTR_ENBL_INTR_ENBL_VEC(x) (((x) << VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__SHIFT) & VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__MASK) 90 91 #define VIVS_HI_CHIP_IDENTITY 0x00000018 92 #define VIVS_HI_CHIP_IDENTITY_FAMILY__MASK 0xff000000 93 #define VIVS_HI_CHIP_IDENTITY_FAMILY__SHIFT 24 94 #define VIVS_HI_CHIP_IDENTITY_FAMILY(x) (((x) << VIVS_HI_CHIP_IDENTITY_FAMILY__SHIFT) & VIVS_HI_CHIP_IDENTITY_FAMILY__MASK) 95 #define VIVS_HI_CHIP_IDENTITY_PRODUCT__MASK 0x00ff0000 96 #define VIVS_HI_CHIP_IDENTITY_PRODUCT__SHIFT 16 97 #define VIVS_HI_CHIP_IDENTITY_PRODUCT(x) (((x) << VIVS_HI_CHIP_IDENTITY_PRODUCT__SHIFT) & VIVS_HI_CHIP_IDENTITY_PRODUCT__MASK) 98 #define VIVS_HI_CHIP_IDENTITY_REVISION__MASK 0x0000f000 99 #define VIVS_HI_CHIP_IDENTITY_REVISION__SHIFT 12 100 #define VIVS_HI_CHIP_IDENTITY_REVISION(x) (((x) << VIVS_HI_CHIP_IDENTITY_REVISION__SHIFT) & VIVS_HI_CHIP_IDENTITY_REVISION__MASK) 101 102 #define VIVS_HI_CHIP_FEATURE 0x0000001c 103 104 #define VIVS_HI_CHIP_MODEL 0x00000020 105 106 #define VIVS_HI_CHIP_REV 0x00000024 107 108 #define VIVS_HI_CHIP_DATE 0x00000028 109 110 #define VIVS_HI_CHIP_TIME 0x0000002c 111 112 #define VIVS_HI_CHIP_MINOR_FEATURE_0 0x00000034 113 114 #define VIVS_HI_CACHE_CONTROL 0x00000038 115 116 #define VIVS_HI_MEMORY_COUNTER_RESET 0x0000003c 117 118 #define VIVS_HI_PROFILE_READ_BYTES8 0x00000040 119 120 #define VIVS_HI_PROFILE_WRITE_BYTES8 0x00000044 121 122 #define VIVS_HI_CHIP_SPECS 0x00000048 123 #define VIVS_HI_CHIP_SPECS_STREAM_COUNT__MASK 0x0000000f 124 #define VIVS_HI_CHIP_SPECS_STREAM_COUNT__SHIFT 0 125 #define VIVS_HI_CHIP_SPECS_STREAM_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_STREAM_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_STREAM_COUNT__MASK) 126 #define VIVS_HI_CHIP_SPECS_REGISTER_MAX__MASK 0x000000f0 127 #define VIVS_HI_CHIP_SPECS_REGISTER_MAX__SHIFT 4 128 #define VIVS_HI_CHIP_SPECS_REGISTER_MAX(x) (((x) << VIVS_HI_CHIP_SPECS_REGISTER_MAX__SHIFT) & VIVS_HI_CHIP_SPECS_REGISTER_MAX__MASK) 129 #define VIVS_HI_CHIP_SPECS_THREAD_COUNT__MASK 0x00000f00 130 #define VIVS_HI_CHIP_SPECS_THREAD_COUNT__SHIFT 8 131 #define VIVS_HI_CHIP_SPECS_THREAD_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_THREAD_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_THREAD_COUNT__MASK) 132 #define VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE__MASK 0x0001f000 133 #define VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE__SHIFT 12 134 #define VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE(x) (((x) << VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE__SHIFT) & VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE__MASK) 135 #define VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT__MASK 0x01f00000 136 #define VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT__SHIFT 20 137 #define VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT__MASK) 138 #define VIVS_HI_CHIP_SPECS_PIXEL_PIPES__MASK 0x0e000000 139 #define VIVS_HI_CHIP_SPECS_PIXEL_PIPES__SHIFT 25 140 #define VIVS_HI_CHIP_SPECS_PIXEL_PIPES(x) (((x) << VIVS_HI_CHIP_SPECS_PIXEL_PIPES__SHIFT) & VIVS_HI_CHIP_SPECS_PIXEL_PIPES__MASK) 141 #define VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE__MASK 0xf0000000 142 #define VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE__SHIFT 28 143 #define VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE(x) (((x) << VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE__SHIFT) & VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE__MASK) 144 145 #define VIVS_HI_PROFILE_WRITE_BURSTS 0x0000004c 146 147 #define VIVS_HI_PROFILE_WRITE_REQUESTS 0x00000050 148 149 #define VIVS_HI_PROFILE_READ_BURSTS 0x00000058 150 151 #define VIVS_HI_PROFILE_READ_REQUESTS 0x0000005c 152 153 #define VIVS_HI_PROFILE_READ_LASTS 0x00000060 154 155 #define VIVS_HI_GP_OUT0 0x00000064 156 157 #define VIVS_HI_GP_OUT1 0x00000068 158 159 #define VIVS_HI_GP_OUT2 0x0000006c 160 161 #define VIVS_HI_AXI_CONTROL 0x00000070 162 #define VIVS_HI_AXI_CONTROL_WR_FULL_BURST_MODE 0x00000001 163 164 #define VIVS_HI_CHIP_MINOR_FEATURE_1 0x00000074 165 166 #define VIVS_HI_PROFILE_TOTAL_CYCLES 0x00000078 167 168 #define VIVS_HI_PROFILE_IDLE_CYCLES 0x0000007c 169 170 #define VIVS_HI_CHIP_SPECS_2 0x00000080 171 #define VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__MASK 0x000000ff 172 #define VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__SHIFT 0 173 #define VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE(x) (((x) << VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__SHIFT) & VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__MASK) 174 #define VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT__MASK 0x0000ff00 175 #define VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT__SHIFT 8 176 #define VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT__MASK) 177 #define VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS__MASK 0xffff0000 178 #define VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS__SHIFT 16 179 #define VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS(x) (((x) << VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS__SHIFT) & VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS__MASK) 180 181 #define VIVS_HI_CHIP_MINOR_FEATURE_2 0x00000084 182 183 #define VIVS_HI_CHIP_MINOR_FEATURE_3 0x00000088 184 185 #define VIVS_HI_CHIP_SPECS_3 0x0000008c 186 #define VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT__MASK 0x000001f0 187 #define VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT__SHIFT 4 188 #define VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT__MASK) 189 #define VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__MASK 0x00000007 190 #define VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__SHIFT 0 191 #define VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__MASK) 192 193 #define VIVS_HI_CHIP_MINOR_FEATURE_4 0x00000094 194 195 #define VIVS_HI_CHIP_SPECS_4 0x0000009c 196 #define VIVS_HI_CHIP_SPECS_4_STREAM_COUNT__MASK 0x0001f000 197 #define VIVS_HI_CHIP_SPECS_4_STREAM_COUNT__SHIFT 12 198 #define VIVS_HI_CHIP_SPECS_4_STREAM_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_4_STREAM_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_4_STREAM_COUNT__MASK) 199 200 #define VIVS_HI_CHIP_MINOR_FEATURE_5 0x000000a0 201 202 #define VIVS_HI_CHIP_PRODUCT_ID 0x000000a8 203 204 #define VIVS_PM 0x00000000 205 206 #define VIVS_PM_POWER_CONTROLS 0x00000100 207 #define VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING 0x00000001 208 #define VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING 0x00000002 209 #define VIVS_PM_POWER_CONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING 0x00000004 210 #define VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER__MASK 0x000000f0 211 #define VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER__SHIFT 4 212 #define VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER(x) (((x) << VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER__SHIFT) & VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER__MASK) 213 #define VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER__MASK 0xffff0000 214 #define VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER__SHIFT 16 215 #define VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER(x) (((x) << VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER__SHIFT) & VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER__MASK) 216 217 #define VIVS_PM_MODULE_CONTROLS 0x00000104 218 #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_FE 0x00000001 219 #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_DE 0x00000002 220 #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE 0x00000004 221 222 #define VIVS_PM_MODULE_STATUS 0x00000108 223 #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_FE 0x00000001 224 #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_DE 0x00000002 225 #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_PE 0x00000004 226 #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_SH 0x00000008 227 #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_PA 0x00000010 228 #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_SE 0x00000020 229 #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_RA 0x00000040 230 #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_TX 0x00000080 231 232 #define VIVS_PM_PULSE_EATER 0x0000010c 233 234 #define VIVS_MMUv2 0x00000000 235 236 #define VIVS_MMUv2_SAFE_ADDRESS 0x00000180 237 238 #define VIVS_MMUv2_CONFIGURATION 0x00000184 239 #define VIVS_MMUv2_CONFIGURATION_MODE__MASK 0x00000001 240 #define VIVS_MMUv2_CONFIGURATION_MODE__SHIFT 0 241 #define VIVS_MMUv2_CONFIGURATION_MODE_MODE4_K 0x00000000 242 #define VIVS_MMUv2_CONFIGURATION_MODE_MODE1_K 0x00000001 243 #define VIVS_MMUv2_CONFIGURATION_MODE_MASK 0x00000008 244 #define VIVS_MMUv2_CONFIGURATION_FLUSH__MASK 0x00000010 245 #define VIVS_MMUv2_CONFIGURATION_FLUSH__SHIFT 4 246 #define VIVS_MMUv2_CONFIGURATION_FLUSH_FLUSH 0x00000010 247 #define VIVS_MMUv2_CONFIGURATION_FLUSH_MASK 0x00000080 248 #define VIVS_MMUv2_CONFIGURATION_ADDRESS_MASK 0x00000100 249 #define VIVS_MMUv2_CONFIGURATION_ADDRESS__MASK 0xfffffc00 250 #define VIVS_MMUv2_CONFIGURATION_ADDRESS__SHIFT 10 251 #define VIVS_MMUv2_CONFIGURATION_ADDRESS(x) (((x) << VIVS_MMUv2_CONFIGURATION_ADDRESS__SHIFT) & VIVS_MMUv2_CONFIGURATION_ADDRESS__MASK) 252 253 #define VIVS_MMUv2_STATUS 0x00000188 254 #define VIVS_MMUv2_STATUS_EXCEPTION0__MASK 0x00000003 255 #define VIVS_MMUv2_STATUS_EXCEPTION0__SHIFT 0 256 #define VIVS_MMUv2_STATUS_EXCEPTION0(x) (((x) << VIVS_MMUv2_STATUS_EXCEPTION0__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION0__MASK) 257 #define VIVS_MMUv2_STATUS_EXCEPTION1__MASK 0x00000030 258 #define VIVS_MMUv2_STATUS_EXCEPTION1__SHIFT 4 259 #define VIVS_MMUv2_STATUS_EXCEPTION1(x) (((x) << VIVS_MMUv2_STATUS_EXCEPTION1__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION1__MASK) 260 #define VIVS_MMUv2_STATUS_EXCEPTION2__MASK 0x00000300 261 #define VIVS_MMUv2_STATUS_EXCEPTION2__SHIFT 8 262 #define VIVS_MMUv2_STATUS_EXCEPTION2(x) (((x) << VIVS_MMUv2_STATUS_EXCEPTION2__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION2__MASK) 263 #define VIVS_MMUv2_STATUS_EXCEPTION3__MASK 0x00003000 264 #define VIVS_MMUv2_STATUS_EXCEPTION3__SHIFT 12 265 #define VIVS_MMUv2_STATUS_EXCEPTION3(x) (((x) << VIVS_MMUv2_STATUS_EXCEPTION3__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION3__MASK) 266 267 #define VIVS_MMUv2_CONTROL 0x0000018c 268 #define VIVS_MMUv2_CONTROL_ENABLE 0x00000001 269 270 #define VIVS_MMUv2_EXCEPTION_ADDR(i0) (0x00000190 + 0x4*(i0)) 271 #define VIVS_MMUv2_EXCEPTION_ADDR__ESIZE 0x00000004 272 #define VIVS_MMUv2_EXCEPTION_ADDR__LEN 0x00000004 273 274 #define VIVS_MC 0x00000000 275 276 #define VIVS_MC_MMU_FE_PAGE_TABLE 0x00000400 277 278 #define VIVS_MC_MMU_TX_PAGE_TABLE 0x00000404 279 280 #define VIVS_MC_MMU_PE_PAGE_TABLE 0x00000408 281 282 #define VIVS_MC_MMU_PEZ_PAGE_TABLE 0x0000040c 283 284 #define VIVS_MC_MMU_RA_PAGE_TABLE 0x00000410 285 286 #define VIVS_MC_DEBUG_MEMORY 0x00000414 287 #define VIVS_MC_DEBUG_MEMORY_SPECIAL_PATCH_GC320 0x00000008 288 #define VIVS_MC_DEBUG_MEMORY_FAST_CLEAR_BYPASS 0x00100000 289 #define VIVS_MC_DEBUG_MEMORY_COMPRESSION_BYPASS 0x00200000 290 291 #define VIVS_MC_MEMORY_BASE_ADDR_RA 0x00000418 292 293 #define VIVS_MC_MEMORY_BASE_ADDR_FE 0x0000041c 294 295 #define VIVS_MC_MEMORY_BASE_ADDR_TX 0x00000420 296 297 #define VIVS_MC_MEMORY_BASE_ADDR_PEZ 0x00000424 298 299 #define VIVS_MC_MEMORY_BASE_ADDR_PE 0x00000428 300 301 #define VIVS_MC_MEMORY_TIMING_CONTROL 0x0000042c 302 303 #define VIVS_MC_MEMORY_FLUSH 0x00000430 304 305 #define VIVS_MC_PROFILE_CYCLE_COUNTER 0x00000438 306 307 #define VIVS_MC_DEBUG_READ0 0x0000043c 308 309 #define VIVS_MC_DEBUG_READ1 0x00000440 310 311 #define VIVS_MC_DEBUG_WRITE 0x00000444 312 313 #define VIVS_MC_PROFILE_RA_READ 0x00000448 314 315 #define VIVS_MC_PROFILE_TX_READ 0x0000044c 316 317 #define VIVS_MC_PROFILE_FE_READ 0x00000450 318 319 #define VIVS_MC_PROFILE_PE_READ 0x00000454 320 321 #define VIVS_MC_PROFILE_DE_READ 0x00000458 322 323 #define VIVS_MC_PROFILE_SH_READ 0x0000045c 324 325 #define VIVS_MC_PROFILE_PA_READ 0x00000460 326 327 #define VIVS_MC_PROFILE_SE_READ 0x00000464 328 329 #define VIVS_MC_PROFILE_MC_READ 0x00000468 330 331 #define VIVS_MC_PROFILE_HI_READ 0x0000046c 332 333 #define VIVS_MC_PROFILE_CONFIG0 0x00000470 334 #define VIVS_MC_PROFILE_CONFIG0_FE__MASK 0x0000000f 335 #define VIVS_MC_PROFILE_CONFIG0_FE__SHIFT 0 336 #define VIVS_MC_PROFILE_CONFIG0_FE_RESET 0x0000000f 337 #define VIVS_MC_PROFILE_CONFIG0_DE__MASK 0x00000f00 338 #define VIVS_MC_PROFILE_CONFIG0_DE__SHIFT 8 339 #define VIVS_MC_PROFILE_CONFIG0_DE_RESET 0x00000f00 340 #define VIVS_MC_PROFILE_CONFIG0_PE__MASK 0x000f0000 341 #define VIVS_MC_PROFILE_CONFIG0_PE__SHIFT 16 342 #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_COLOR_PIPE 0x00000000 343 #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_DEPTH_PIPE 0x00010000 344 #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_COLOR_PIPE 0x00020000 345 #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_DEPTH_PIPE 0x00030000 346 #define VIVS_MC_PROFILE_CONFIG0_PE_PIXELS_RENDERED_2D 0x000b0000 347 #define VIVS_MC_PROFILE_CONFIG0_PE_RESET 0x000f0000 348 #define VIVS_MC_PROFILE_CONFIG0_SH__MASK 0x0f000000 349 #define VIVS_MC_PROFILE_CONFIG0_SH__SHIFT 24 350 #define VIVS_MC_PROFILE_CONFIG0_SH_SHADER_CYCLES 0x04000000 351 #define VIVS_MC_PROFILE_CONFIG0_SH_PS_INST_COUNTER 0x07000000 352 #define VIVS_MC_PROFILE_CONFIG0_SH_RENDERED_PIXEL_COUNTER 0x08000000 353 #define VIVS_MC_PROFILE_CONFIG0_SH_VS_INST_COUNTER 0x09000000 354 #define VIVS_MC_PROFILE_CONFIG0_SH_RENDERED_VERTICE_COUNTER 0x0a000000 355 #define VIVS_MC_PROFILE_CONFIG0_SH_VTX_BRANCH_INST_COUNTER 0x0b000000 356 #define VIVS_MC_PROFILE_CONFIG0_SH_VTX_TEXLD_INST_COUNTER 0x0c000000 357 #define VIVS_MC_PROFILE_CONFIG0_SH_PXL_BRANCH_INST_COUNTER 0x0d000000 358 #define VIVS_MC_PROFILE_CONFIG0_SH_PXL_TEXLD_INST_COUNTER 0x0e000000 359 #define VIVS_MC_PROFILE_CONFIG0_SH_RESET 0x0f000000 360 361 #define VIVS_MC_PROFILE_CONFIG1 0x00000474 362 #define VIVS_MC_PROFILE_CONFIG1_PA__MASK 0x0000000f 363 #define VIVS_MC_PROFILE_CONFIG1_PA__SHIFT 0 364 #define VIVS_MC_PROFILE_CONFIG1_PA_INPUT_VTX_COUNTER 0x00000003 365 #define VIVS_MC_PROFILE_CONFIG1_PA_INPUT_PRIM_COUNTER 0x00000004 366 #define VIVS_MC_PROFILE_CONFIG1_PA_OUTPUT_PRIM_COUNTER 0x00000005 367 #define VIVS_MC_PROFILE_CONFIG1_PA_DEPTH_CLIPPED_COUNTER 0x00000006 368 #define VIVS_MC_PROFILE_CONFIG1_PA_TRIVIAL_REJECTED_COUNTER 0x00000007 369 #define VIVS_MC_PROFILE_CONFIG1_PA_CULLED_COUNTER 0x00000008 370 #define VIVS_MC_PROFILE_CONFIG1_PA_RESET 0x0000000f 371 #define VIVS_MC_PROFILE_CONFIG1_SE__MASK 0x00000f00 372 #define VIVS_MC_PROFILE_CONFIG1_SE__SHIFT 8 373 #define VIVS_MC_PROFILE_CONFIG1_SE_CULLED_TRIANGLE_COUNT 0x00000000 374 #define VIVS_MC_PROFILE_CONFIG1_SE_CULLED_LINES_COUNT 0x00000100 375 #define VIVS_MC_PROFILE_CONFIG1_SE_RESET 0x00000f00 376 #define VIVS_MC_PROFILE_CONFIG1_RA__MASK 0x000f0000 377 #define VIVS_MC_PROFILE_CONFIG1_RA__SHIFT 16 378 #define VIVS_MC_PROFILE_CONFIG1_RA_VALID_PIXEL_COUNT 0x00000000 379 #define VIVS_MC_PROFILE_CONFIG1_RA_TOTAL_QUAD_COUNT 0x00010000 380 #define VIVS_MC_PROFILE_CONFIG1_RA_VALID_QUAD_COUNT_AFTER_EARLY_Z 0x00020000 381 #define VIVS_MC_PROFILE_CONFIG1_RA_TOTAL_PRIMITIVE_COUNT 0x00030000 382 #define VIVS_MC_PROFILE_CONFIG1_RA_PIPE_CACHE_MISS_COUNTER 0x00090000 383 #define VIVS_MC_PROFILE_CONFIG1_RA_PREFETCH_CACHE_MISS_COUNTER 0x000a0000 384 #define VIVS_MC_PROFILE_CONFIG1_RA_CULLED_QUAD_COUNT 0x000b0000 385 #define VIVS_MC_PROFILE_CONFIG1_RA_RESET 0x000f0000 386 #define VIVS_MC_PROFILE_CONFIG1_TX__MASK 0x0f000000 387 #define VIVS_MC_PROFILE_CONFIG1_TX__SHIFT 24 388 #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_BILINEAR_REQUESTS 0x00000000 389 #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_TRILINEAR_REQUESTS 0x01000000 390 #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_DISCARDED_TEXTURE_REQUESTS 0x02000000 391 #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_TEXTURE_REQUESTS 0x03000000 392 #define VIVS_MC_PROFILE_CONFIG1_TX_UNKNOWN 0x04000000 393 #define VIVS_MC_PROFILE_CONFIG1_TX_MEM_READ_COUNT 0x05000000 394 #define VIVS_MC_PROFILE_CONFIG1_TX_MEM_READ_IN_8B_COUNT 0x06000000 395 #define VIVS_MC_PROFILE_CONFIG1_TX_CACHE_MISS_COUNT 0x07000000 396 #define VIVS_MC_PROFILE_CONFIG1_TX_CACHE_HIT_TEXEL_COUNT 0x08000000 397 #define VIVS_MC_PROFILE_CONFIG1_TX_CACHE_MISS_TEXEL_COUNT 0x09000000 398 #define VIVS_MC_PROFILE_CONFIG1_TX_RESET 0x0f000000 399 400 #define VIVS_MC_PROFILE_CONFIG2 0x00000478 401 #define VIVS_MC_PROFILE_CONFIG2_MC__MASK 0x0000000f 402 #define VIVS_MC_PROFILE_CONFIG2_MC__SHIFT 0 403 #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_PIPELINE 0x00000001 404 #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_IP 0x00000002 405 #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_8B_FROM_PIPELINE 0x00000003 406 #define VIVS_MC_PROFILE_CONFIG2_MC_RESET 0x0000000f 407 #define VIVS_MC_PROFILE_CONFIG2_HI__MASK 0x00000f00 408 #define VIVS_MC_PROFILE_CONFIG2_HI__SHIFT 8 409 #define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_READ_REQUEST_STALLED 0x00000000 410 #define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_REQUEST_STALLED 0x00000100 411 #define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_DATA_STALLED 0x00000200 412 #define VIVS_MC_PROFILE_CONFIG2_HI_RESET 0x00000f00 413 414 #define VIVS_MC_PROFILE_CONFIG3 0x0000047c 415 416 #define VIVS_MC_BUS_CONFIG 0x00000480 417 #define VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK 0x0000000f 418 #define VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__SHIFT 0 419 #define VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(x) (((x) << VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__SHIFT) & VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK) 420 #define VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK 0x000000f0 421 #define VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__SHIFT 4 422 #define VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(x) (((x) << VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__SHIFT) & VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK) 423 424 #define VIVS_MC_START_COMPOSITION 0x00000554 425 426 #define VIVS_MC_128B_MERGE 0x00000558 427 428 429 #endif /* STATE_HI_XML */ 430