1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2015-2018 Etnaviv Project 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/component.h> 8 #include <linux/delay.h> 9 #include <linux/dma-fence.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/mod_devicetable.h> 12 #include <linux/module.h> 13 #include <linux/platform_device.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/reset.h> 17 #include <linux/thermal.h> 18 19 #include "etnaviv_cmdbuf.h" 20 #include "etnaviv_dump.h" 21 #include "etnaviv_gpu.h" 22 #include "etnaviv_gem.h" 23 #include "etnaviv_mmu.h" 24 #include "etnaviv_perfmon.h" 25 #include "etnaviv_sched.h" 26 #include "common.xml.h" 27 #include "state.xml.h" 28 #include "state_hi.xml.h" 29 #include "cmdstream.xml.h" 30 31 static const struct platform_device_id gpu_ids[] = { 32 { .name = "etnaviv-gpu,2d" }, 33 { }, 34 }; 35 36 /* 37 * Driver functions: 38 */ 39 40 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value) 41 { 42 struct etnaviv_drm_private *priv = gpu->drm->dev_private; 43 44 switch (param) { 45 case ETNAVIV_PARAM_GPU_MODEL: 46 *value = gpu->identity.model; 47 break; 48 49 case ETNAVIV_PARAM_GPU_REVISION: 50 *value = gpu->identity.revision; 51 break; 52 53 case ETNAVIV_PARAM_GPU_FEATURES_0: 54 *value = gpu->identity.features; 55 break; 56 57 case ETNAVIV_PARAM_GPU_FEATURES_1: 58 *value = gpu->identity.minor_features0; 59 break; 60 61 case ETNAVIV_PARAM_GPU_FEATURES_2: 62 *value = gpu->identity.minor_features1; 63 break; 64 65 case ETNAVIV_PARAM_GPU_FEATURES_3: 66 *value = gpu->identity.minor_features2; 67 break; 68 69 case ETNAVIV_PARAM_GPU_FEATURES_4: 70 *value = gpu->identity.minor_features3; 71 break; 72 73 case ETNAVIV_PARAM_GPU_FEATURES_5: 74 *value = gpu->identity.minor_features4; 75 break; 76 77 case ETNAVIV_PARAM_GPU_FEATURES_6: 78 *value = gpu->identity.minor_features5; 79 break; 80 81 case ETNAVIV_PARAM_GPU_FEATURES_7: 82 *value = gpu->identity.minor_features6; 83 break; 84 85 case ETNAVIV_PARAM_GPU_FEATURES_8: 86 *value = gpu->identity.minor_features7; 87 break; 88 89 case ETNAVIV_PARAM_GPU_FEATURES_9: 90 *value = gpu->identity.minor_features8; 91 break; 92 93 case ETNAVIV_PARAM_GPU_FEATURES_10: 94 *value = gpu->identity.minor_features9; 95 break; 96 97 case ETNAVIV_PARAM_GPU_FEATURES_11: 98 *value = gpu->identity.minor_features10; 99 break; 100 101 case ETNAVIV_PARAM_GPU_FEATURES_12: 102 *value = gpu->identity.minor_features11; 103 break; 104 105 case ETNAVIV_PARAM_GPU_STREAM_COUNT: 106 *value = gpu->identity.stream_count; 107 break; 108 109 case ETNAVIV_PARAM_GPU_REGISTER_MAX: 110 *value = gpu->identity.register_max; 111 break; 112 113 case ETNAVIV_PARAM_GPU_THREAD_COUNT: 114 *value = gpu->identity.thread_count; 115 break; 116 117 case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE: 118 *value = gpu->identity.vertex_cache_size; 119 break; 120 121 case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT: 122 *value = gpu->identity.shader_core_count; 123 break; 124 125 case ETNAVIV_PARAM_GPU_PIXEL_PIPES: 126 *value = gpu->identity.pixel_pipes; 127 break; 128 129 case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE: 130 *value = gpu->identity.vertex_output_buffer_size; 131 break; 132 133 case ETNAVIV_PARAM_GPU_BUFFER_SIZE: 134 *value = gpu->identity.buffer_size; 135 break; 136 137 case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT: 138 *value = gpu->identity.instruction_count; 139 break; 140 141 case ETNAVIV_PARAM_GPU_NUM_CONSTANTS: 142 *value = gpu->identity.num_constants; 143 break; 144 145 case ETNAVIV_PARAM_GPU_NUM_VARYINGS: 146 *value = gpu->identity.varyings_count; 147 break; 148 149 case ETNAVIV_PARAM_SOFTPIN_START_ADDR: 150 if (priv->mmu_global->version == ETNAVIV_IOMMU_V2) 151 *value = ETNAVIV_SOFTPIN_START_ADDRESS; 152 else 153 *value = ~0ULL; 154 break; 155 156 case ETNAVIV_PARAM_GPU_PRODUCT_ID: 157 *value = gpu->identity.product_id; 158 break; 159 160 case ETNAVIV_PARAM_GPU_CUSTOMER_ID: 161 *value = gpu->identity.customer_id; 162 break; 163 164 case ETNAVIV_PARAM_GPU_ECO_ID: 165 *value = gpu->identity.eco_id; 166 break; 167 168 default: 169 DBG("%s: invalid param: %u", dev_name(gpu->dev), param); 170 return -EINVAL; 171 } 172 173 return 0; 174 } 175 176 static int etnaviv_gpu_reset_deassert(struct etnaviv_gpu *gpu) 177 { 178 int ret; 179 180 /* 181 * 32 core clock cycles (slowest clock) required before deassertion 182 * 1 microsecond might match all implementations without computation 183 */ 184 usleep_range(1, 2); 185 186 ret = reset_control_deassert(gpu->rst); 187 if (ret) 188 return ret; 189 190 /* 191 * 128 core clock cycles (slowest clock) required before any activity on AHB 192 * 1 microsecond might match all implementations without computation 193 */ 194 usleep_range(1, 2); 195 196 return 0; 197 } 198 199 static inline bool etnaviv_is_model_rev(struct etnaviv_gpu *gpu, u32 model, u32 revision) 200 { 201 return gpu->identity.model == model && 202 gpu->identity.revision == revision; 203 } 204 205 #define etnaviv_field(val, field) \ 206 (((val) & field##__MASK) >> field##__SHIFT) 207 208 static void etnaviv_hw_specs(struct etnaviv_gpu *gpu) 209 { 210 if (gpu->identity.minor_features0 & 211 chipMinorFeatures0_MORE_MINOR_FEATURES) { 212 u32 specs[4]; 213 unsigned int streams; 214 215 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS); 216 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2); 217 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3); 218 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4); 219 220 gpu->identity.stream_count = etnaviv_field(specs[0], 221 VIVS_HI_CHIP_SPECS_STREAM_COUNT); 222 gpu->identity.register_max = etnaviv_field(specs[0], 223 VIVS_HI_CHIP_SPECS_REGISTER_MAX); 224 gpu->identity.thread_count = etnaviv_field(specs[0], 225 VIVS_HI_CHIP_SPECS_THREAD_COUNT); 226 gpu->identity.vertex_cache_size = etnaviv_field(specs[0], 227 VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE); 228 gpu->identity.shader_core_count = etnaviv_field(specs[0], 229 VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT); 230 gpu->identity.pixel_pipes = etnaviv_field(specs[0], 231 VIVS_HI_CHIP_SPECS_PIXEL_PIPES); 232 gpu->identity.vertex_output_buffer_size = 233 etnaviv_field(specs[0], 234 VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE); 235 236 gpu->identity.buffer_size = etnaviv_field(specs[1], 237 VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE); 238 gpu->identity.instruction_count = etnaviv_field(specs[1], 239 VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT); 240 gpu->identity.num_constants = etnaviv_field(specs[1], 241 VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS); 242 243 gpu->identity.varyings_count = etnaviv_field(specs[2], 244 VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT); 245 246 /* This overrides the value from older register if non-zero */ 247 streams = etnaviv_field(specs[3], 248 VIVS_HI_CHIP_SPECS_4_STREAM_COUNT); 249 if (streams) 250 gpu->identity.stream_count = streams; 251 } 252 253 /* Fill in the stream count if not specified */ 254 if (gpu->identity.stream_count == 0) { 255 if (gpu->identity.model >= 0x1000) 256 gpu->identity.stream_count = 4; 257 else 258 gpu->identity.stream_count = 1; 259 } 260 261 /* Convert the register max value */ 262 if (gpu->identity.register_max) 263 gpu->identity.register_max = 1 << gpu->identity.register_max; 264 else if (gpu->identity.model == chipModel_GC400) 265 gpu->identity.register_max = 32; 266 else 267 gpu->identity.register_max = 64; 268 269 /* Convert thread count */ 270 if (gpu->identity.thread_count) 271 gpu->identity.thread_count = 1 << gpu->identity.thread_count; 272 else if (gpu->identity.model == chipModel_GC400) 273 gpu->identity.thread_count = 64; 274 else if (gpu->identity.model == chipModel_GC500 || 275 gpu->identity.model == chipModel_GC530) 276 gpu->identity.thread_count = 128; 277 else 278 gpu->identity.thread_count = 256; 279 280 if (gpu->identity.vertex_cache_size == 0) 281 gpu->identity.vertex_cache_size = 8; 282 283 if (gpu->identity.shader_core_count == 0) { 284 if (gpu->identity.model >= 0x1000) 285 gpu->identity.shader_core_count = 2; 286 else 287 gpu->identity.shader_core_count = 1; 288 } 289 290 if (gpu->identity.pixel_pipes == 0) 291 gpu->identity.pixel_pipes = 1; 292 293 /* Convert virtex buffer size */ 294 if (gpu->identity.vertex_output_buffer_size) { 295 gpu->identity.vertex_output_buffer_size = 296 1 << gpu->identity.vertex_output_buffer_size; 297 } else if (gpu->identity.model == chipModel_GC400) { 298 if (gpu->identity.revision < 0x4000) 299 gpu->identity.vertex_output_buffer_size = 512; 300 else if (gpu->identity.revision < 0x4200) 301 gpu->identity.vertex_output_buffer_size = 256; 302 else 303 gpu->identity.vertex_output_buffer_size = 128; 304 } else { 305 gpu->identity.vertex_output_buffer_size = 512; 306 } 307 308 switch (gpu->identity.instruction_count) { 309 case 0: 310 if (etnaviv_is_model_rev(gpu, 0x2000, 0x5108) || 311 gpu->identity.model == chipModel_GC880) 312 gpu->identity.instruction_count = 512; 313 else 314 gpu->identity.instruction_count = 256; 315 break; 316 317 case 1: 318 gpu->identity.instruction_count = 1024; 319 break; 320 321 case 2: 322 gpu->identity.instruction_count = 2048; 323 break; 324 325 default: 326 gpu->identity.instruction_count = 256; 327 break; 328 } 329 330 if (gpu->identity.num_constants == 0) 331 gpu->identity.num_constants = 168; 332 333 if (gpu->identity.varyings_count == 0) { 334 if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0) 335 gpu->identity.varyings_count = 12; 336 else 337 gpu->identity.varyings_count = 8; 338 } 339 340 /* 341 * For some cores, two varyings are consumed for position, so the 342 * maximum varying count needs to be reduced by one. 343 */ 344 if (etnaviv_is_model_rev(gpu, 0x5000, 0x5434) || 345 etnaviv_is_model_rev(gpu, 0x4000, 0x5222) || 346 etnaviv_is_model_rev(gpu, 0x4000, 0x5245) || 347 etnaviv_is_model_rev(gpu, 0x4000, 0x5208) || 348 etnaviv_is_model_rev(gpu, 0x3000, 0x5435) || 349 etnaviv_is_model_rev(gpu, 0x2200, 0x5244) || 350 etnaviv_is_model_rev(gpu, 0x2100, 0x5108) || 351 etnaviv_is_model_rev(gpu, 0x2000, 0x5108) || 352 etnaviv_is_model_rev(gpu, 0x1500, 0x5246) || 353 etnaviv_is_model_rev(gpu, 0x880, 0x5107) || 354 etnaviv_is_model_rev(gpu, 0x880, 0x5106)) 355 gpu->identity.varyings_count -= 1; 356 } 357 358 static void etnaviv_hw_identify(struct etnaviv_gpu *gpu) 359 { 360 u32 chipIdentity; 361 362 chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY); 363 364 /* Special case for older graphic cores. */ 365 if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) { 366 gpu->identity.model = chipModel_GC500; 367 gpu->identity.revision = etnaviv_field(chipIdentity, 368 VIVS_HI_CHIP_IDENTITY_REVISION); 369 } else { 370 u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE); 371 372 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL); 373 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV); 374 gpu->identity.customer_id = gpu_read(gpu, VIVS_HI_CHIP_CUSTOMER_ID); 375 376 /* 377 * Reading these two registers on GC600 rev 0x19 result in a 378 * unhandled fault: external abort on non-linefetch 379 */ 380 if (!etnaviv_is_model_rev(gpu, 0x600, 0x19)) { 381 gpu->identity.product_id = gpu_read(gpu, VIVS_HI_CHIP_PRODUCT_ID); 382 gpu->identity.eco_id = gpu_read(gpu, VIVS_HI_CHIP_ECO_ID); 383 } 384 385 /* 386 * !!!! HACK ALERT !!!! 387 * Because people change device IDs without letting software 388 * know about it - here is the hack to make it all look the 389 * same. Only for GC400 family. 390 */ 391 if ((gpu->identity.model & 0xff00) == 0x0400 && 392 gpu->identity.model != chipModel_GC420) { 393 gpu->identity.model = gpu->identity.model & 0x0400; 394 } 395 396 /* Another special case */ 397 if (etnaviv_is_model_rev(gpu, 0x300, 0x2201)) { 398 u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME); 399 400 if (chipDate == 0x20080814 && chipTime == 0x12051100) { 401 /* 402 * This IP has an ECO; put the correct 403 * revision in it. 404 */ 405 gpu->identity.revision = 0x1051; 406 } 407 } 408 409 /* 410 * NXP likes to call the GPU on the i.MX6QP GC2000+, but in 411 * reality it's just a re-branded GC3000. We can identify this 412 * core by the upper half of the revision register being all 1. 413 * Fix model/rev here, so all other places can refer to this 414 * core by its real identity. 415 */ 416 if (etnaviv_is_model_rev(gpu, 0x2000, 0xffff5450)) { 417 gpu->identity.model = chipModel_GC3000; 418 gpu->identity.revision &= 0xffff; 419 } 420 421 if (etnaviv_is_model_rev(gpu, 0x1000, 0x5037) && (chipDate == 0x20120617)) 422 gpu->identity.eco_id = 1; 423 424 if (etnaviv_is_model_rev(gpu, 0x320, 0x5303) && (chipDate == 0x20140511)) 425 gpu->identity.eco_id = 1; 426 } 427 428 dev_info(gpu->dev, "model: GC%x, revision: %x\n", 429 gpu->identity.model, gpu->identity.revision); 430 431 gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP; 432 /* 433 * If there is a match in the HWDB, we aren't interested in the 434 * remaining register values, as they might be wrong. 435 */ 436 if (etnaviv_fill_identity_from_hwdb(gpu)) 437 return; 438 439 gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE); 440 441 /* Disable fast clear on GC700. */ 442 if (gpu->identity.model == chipModel_GC700) 443 gpu->identity.features &= ~chipFeatures_FAST_CLEAR; 444 445 /* These models/revisions don't have the 2D pipe bit */ 446 if ((gpu->identity.model == chipModel_GC500 && 447 gpu->identity.revision <= 2) || 448 gpu->identity.model == chipModel_GC300) 449 gpu->identity.features |= chipFeatures_PIPE_2D; 450 451 if ((gpu->identity.model == chipModel_GC500 && 452 gpu->identity.revision < 2) || 453 (gpu->identity.model == chipModel_GC300 && 454 gpu->identity.revision < 0x2000)) { 455 456 /* 457 * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these 458 * registers. 459 */ 460 gpu->identity.minor_features0 = 0; 461 gpu->identity.minor_features1 = 0; 462 gpu->identity.minor_features2 = 0; 463 gpu->identity.minor_features3 = 0; 464 gpu->identity.minor_features4 = 0; 465 gpu->identity.minor_features5 = 0; 466 } else 467 gpu->identity.minor_features0 = 468 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0); 469 470 if (gpu->identity.minor_features0 & 471 chipMinorFeatures0_MORE_MINOR_FEATURES) { 472 gpu->identity.minor_features1 = 473 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1); 474 gpu->identity.minor_features2 = 475 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2); 476 gpu->identity.minor_features3 = 477 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3); 478 gpu->identity.minor_features4 = 479 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4); 480 gpu->identity.minor_features5 = 481 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5); 482 } 483 484 /* GC600/300 idle register reports zero bits where modules aren't present */ 485 if (gpu->identity.model == chipModel_GC600 || 486 gpu->identity.model == chipModel_GC300) 487 gpu->idle_mask = VIVS_HI_IDLE_STATE_TX | 488 VIVS_HI_IDLE_STATE_RA | 489 VIVS_HI_IDLE_STATE_SE | 490 VIVS_HI_IDLE_STATE_PA | 491 VIVS_HI_IDLE_STATE_SH | 492 VIVS_HI_IDLE_STATE_PE | 493 VIVS_HI_IDLE_STATE_DE | 494 VIVS_HI_IDLE_STATE_FE; 495 496 etnaviv_hw_specs(gpu); 497 } 498 499 static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock) 500 { 501 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock | 502 VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD); 503 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); 504 } 505 506 static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu) 507 { 508 if (gpu->identity.minor_features2 & 509 chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING) { 510 clk_set_rate(gpu->clk_core, 511 gpu->base_rate_core >> gpu->freq_scale); 512 clk_set_rate(gpu->clk_shader, 513 gpu->base_rate_shader >> gpu->freq_scale); 514 } else { 515 unsigned int fscale = 1 << (6 - gpu->freq_scale); 516 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 517 518 clock &= ~VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK; 519 clock |= VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale); 520 etnaviv_gpu_load_clock(gpu, clock); 521 } 522 523 /* 524 * Choose number of wait cycles to target a ~30us (1/32768) max latency 525 * until new work is picked up by the FE when it polls in the idle loop. 526 * If the GPU base frequency is unknown use 200 wait cycles. 527 */ 528 gpu->fe_waitcycles = clamp(gpu->base_rate_core >> (15 - gpu->freq_scale), 529 200UL, 0xffffUL); 530 } 531 532 static int etnaviv_hw_reset(struct etnaviv_gpu *gpu) 533 { 534 u32 control, idle; 535 unsigned long timeout; 536 bool failed = true; 537 538 /* We hope that the GPU resets in under one second */ 539 timeout = jiffies + msecs_to_jiffies(1000); 540 541 while (time_is_after_jiffies(timeout)) { 542 unsigned int fscale = 1 << (6 - gpu->freq_scale); 543 u32 pulse_eater = 0x01590880; 544 545 /* disable clock gating */ 546 gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, 0x0); 547 548 /* disable pulse eater */ 549 pulse_eater |= BIT(17); 550 gpu_write_power(gpu, VIVS_PM_PULSE_EATER, pulse_eater); 551 pulse_eater |= BIT(0); 552 gpu_write_power(gpu, VIVS_PM_PULSE_EATER, pulse_eater); 553 554 /* enable clock */ 555 control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale); 556 etnaviv_gpu_load_clock(gpu, control); 557 558 /* isolate the GPU. */ 559 control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU; 560 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 561 562 if (gpu->sec_mode == ETNA_SEC_KERNEL) { 563 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, 564 VIVS_MMUv2_AHB_CONTROL_RESET); 565 } else { 566 /* set soft reset. */ 567 control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET; 568 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 569 } 570 571 /* wait for reset. */ 572 usleep_range(10, 20); 573 574 /* reset soft reset bit. */ 575 control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET; 576 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 577 578 /* reset GPU isolation. */ 579 control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU; 580 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 581 582 /* read idle register. */ 583 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 584 585 /* try resetting again if FE is not idle */ 586 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) { 587 dev_dbg(gpu->dev, "FE is not idle\n"); 588 continue; 589 } 590 591 /* read reset register. */ 592 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 593 594 /* is the GPU idle? */ 595 if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) || 596 ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) { 597 dev_dbg(gpu->dev, "GPU is not idle\n"); 598 continue; 599 } 600 601 /* enable debug register access */ 602 control &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS; 603 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 604 605 failed = false; 606 break; 607 } 608 609 if (failed) { 610 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 611 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 612 613 dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n", 614 idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ", 615 control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ", 616 control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not "); 617 618 return -EBUSY; 619 } 620 621 /* We rely on the GPU running, so program the clock */ 622 etnaviv_gpu_update_clock(gpu); 623 624 gpu->state = ETNA_GPU_STATE_RESET; 625 gpu->exec_state = -1; 626 if (gpu->mmu_context) 627 etnaviv_iommu_context_put(gpu->mmu_context); 628 gpu->mmu_context = NULL; 629 630 return 0; 631 } 632 633 static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu) 634 { 635 u32 pmc, ppc; 636 637 /* enable clock gating */ 638 ppc = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS); 639 ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; 640 641 /* Disable stall module clock gating for 4.3.0.1 and 4.3.0.2 revs */ 642 if (gpu->identity.revision == 0x4301 || 643 gpu->identity.revision == 0x4302) 644 ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING; 645 646 gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, ppc); 647 648 pmc = gpu_read_power(gpu, VIVS_PM_MODULE_CONTROLS); 649 650 /* Disable PA clock gating for GC400+ without bugfix except for GC420 */ 651 if (gpu->identity.model >= chipModel_GC400 && 652 gpu->identity.model != chipModel_GC420 && 653 !(gpu->identity.minor_features3 & chipMinorFeatures3_BUG_FIXES12)) 654 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA; 655 656 /* 657 * Disable PE clock gating on revs < 5.0.0.0 when HZ is 658 * present without a bug fix. 659 */ 660 if (gpu->identity.revision < 0x5000 && 661 gpu->identity.minor_features0 & chipMinorFeatures0_HZ && 662 !(gpu->identity.minor_features1 & 663 chipMinorFeatures1_DISABLE_PE_GATING)) 664 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE; 665 666 if (gpu->identity.revision < 0x5422) 667 pmc |= BIT(15); /* Unknown bit */ 668 669 /* Disable TX clock gating on affected core revisions. */ 670 if (etnaviv_is_model_rev(gpu, 0x4000, 0x5222) || 671 etnaviv_is_model_rev(gpu, 0x2000, 0x5108) || 672 etnaviv_is_model_rev(gpu, 0x7000, 0x6202) || 673 etnaviv_is_model_rev(gpu, 0x7000, 0x6203)) 674 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX; 675 676 /* Disable SE and RA clock gating on affected core revisions. */ 677 if (etnaviv_is_model_rev(gpu, 0x7000, 0x6202)) 678 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE | 679 VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA; 680 681 /* Disable SH_EU clock gating on affected core revisions. */ 682 if (etnaviv_is_model_rev(gpu, 0x8000, 0x7200) || 683 etnaviv_is_model_rev(gpu, 0x8000, 0x8002) || 684 etnaviv_is_model_rev(gpu, 0x9200, 0x6304)) 685 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SH_EU; 686 687 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ; 688 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ; 689 690 gpu_write_power(gpu, VIVS_PM_MODULE_CONTROLS, pmc); 691 } 692 693 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch) 694 { 695 gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address); 696 gpu_write(gpu, VIVS_FE_COMMAND_CONTROL, 697 VIVS_FE_COMMAND_CONTROL_ENABLE | 698 VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch)); 699 700 if (gpu->sec_mode == ETNA_SEC_KERNEL) { 701 gpu_write(gpu, VIVS_MMUv2_SEC_COMMAND_CONTROL, 702 VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE | 703 VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH(prefetch)); 704 } 705 } 706 707 static void etnaviv_gpu_start_fe_idleloop(struct etnaviv_gpu *gpu, 708 struct etnaviv_iommu_context *context) 709 { 710 u16 prefetch; 711 u32 address; 712 713 WARN_ON(gpu->state != ETNA_GPU_STATE_INITIALIZED); 714 715 /* setup the MMU */ 716 etnaviv_iommu_restore(gpu, context); 717 718 /* Start command processor */ 719 prefetch = etnaviv_buffer_init(gpu); 720 address = etnaviv_cmdbuf_get_va(&gpu->buffer, 721 &gpu->mmu_context->cmdbuf_mapping); 722 723 etnaviv_gpu_start_fe(gpu, address, prefetch); 724 725 gpu->state = ETNA_GPU_STATE_RUNNING; 726 } 727 728 static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu) 729 { 730 /* 731 * Base value for VIVS_PM_PULSE_EATER register on models where it 732 * cannot be read, extracted from vivante kernel driver. 733 */ 734 u32 pulse_eater = 0x01590880; 735 736 if (etnaviv_is_model_rev(gpu, 0x4000, 0x5208) || 737 etnaviv_is_model_rev(gpu, 0x4000, 0x5222)) { 738 pulse_eater |= BIT(23); 739 740 } 741 742 if (etnaviv_is_model_rev(gpu, 0x1000, 0x5039) || 743 etnaviv_is_model_rev(gpu, 0x1000, 0x5040)) { 744 pulse_eater &= ~BIT(16); 745 pulse_eater |= BIT(17); 746 } 747 748 if ((gpu->identity.revision > 0x5420) && 749 (gpu->identity.features & chipFeatures_PIPE_3D)) 750 { 751 /* Performance fix: disable internal DFS */ 752 pulse_eater = gpu_read_power(gpu, VIVS_PM_PULSE_EATER); 753 pulse_eater |= BIT(18); 754 } 755 756 gpu_write_power(gpu, VIVS_PM_PULSE_EATER, pulse_eater); 757 } 758 759 static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu) 760 { 761 WARN_ON(!(gpu->state == ETNA_GPU_STATE_IDENTIFIED || 762 gpu->state == ETNA_GPU_STATE_RESET)); 763 764 if ((etnaviv_is_model_rev(gpu, 0x320, 0x5007) || 765 etnaviv_is_model_rev(gpu, 0x320, 0x5220)) && 766 gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) { 767 u32 mc_memory_debug; 768 769 mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff; 770 771 if (gpu->identity.revision == 0x5007) 772 mc_memory_debug |= 0x0c; 773 else 774 mc_memory_debug |= 0x08; 775 776 gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug); 777 } 778 779 /* enable module-level clock gating */ 780 etnaviv_gpu_enable_mlcg(gpu); 781 782 /* 783 * Update GPU AXI cache atttribute to "cacheable, no allocate". 784 * This is necessary to prevent the iMX6 SoC locking up. 785 */ 786 gpu_write(gpu, VIVS_HI_AXI_CONFIG, 787 VIVS_HI_AXI_CONFIG_AWCACHE(2) | 788 VIVS_HI_AXI_CONFIG_ARCACHE(2)); 789 790 /* GC2000 rev 5108 needs a special bus config */ 791 if (etnaviv_is_model_rev(gpu, 0x2000, 0x5108)) { 792 u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG); 793 bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK | 794 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK); 795 bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) | 796 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0); 797 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config); 798 } 799 800 if (gpu->sec_mode == ETNA_SEC_KERNEL) { 801 u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL); 802 val |= VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS; 803 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val); 804 } 805 806 /* setup the pulse eater */ 807 etnaviv_gpu_setup_pulse_eater(gpu); 808 809 gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U); 810 811 gpu->state = ETNA_GPU_STATE_INITIALIZED; 812 } 813 814 int etnaviv_gpu_init(struct etnaviv_gpu *gpu) 815 { 816 struct etnaviv_drm_private *priv = gpu->drm->dev_private; 817 dma_addr_t cmdbuf_paddr; 818 int ret, i; 819 820 ret = pm_runtime_get_sync(gpu->dev); 821 if (ret < 0) { 822 dev_err(gpu->dev, "Failed to enable GPU power domain\n"); 823 goto pm_put; 824 } 825 826 ret = etnaviv_gpu_reset_deassert(gpu); 827 if (ret) { 828 dev_err(gpu->dev, "GPU reset deassert failed\n"); 829 goto fail; 830 } 831 832 etnaviv_hw_identify(gpu); 833 834 if (gpu->identity.model == 0) { 835 dev_err(gpu->dev, "Unknown GPU model\n"); 836 ret = -ENXIO; 837 goto fail; 838 } 839 840 if (gpu->identity.nn_core_count > 0) 841 dev_warn(gpu->dev, "etnaviv has been instantiated on a NPU, " 842 "for which the UAPI is still experimental\n"); 843 844 /* Exclude VG cores with FE2.0 */ 845 if (gpu->identity.features & chipFeatures_PIPE_VG && 846 gpu->identity.features & chipFeatures_FE20) { 847 dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n"); 848 ret = -ENXIO; 849 goto fail; 850 } 851 852 /* 853 * On cores with security features supported, we claim control over the 854 * security states. 855 */ 856 if ((gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) && 857 (gpu->identity.minor_features10 & chipMinorFeatures10_SECURITY_AHB)) 858 gpu->sec_mode = ETNA_SEC_KERNEL; 859 860 gpu->state = ETNA_GPU_STATE_IDENTIFIED; 861 862 ret = etnaviv_hw_reset(gpu); 863 if (ret) { 864 dev_err(gpu->dev, "GPU reset failed\n"); 865 goto fail; 866 } 867 868 ret = etnaviv_iommu_global_init(gpu); 869 if (ret) 870 goto fail; 871 872 /* Create buffer: */ 873 ret = etnaviv_cmdbuf_init(priv->cmdbuf_suballoc, &gpu->buffer, SZ_4K); 874 if (ret) { 875 dev_err(gpu->dev, "could not create command buffer\n"); 876 goto fail; 877 } 878 879 /* 880 * Set the GPU linear window to cover the cmdbuf region, as the GPU 881 * won't be able to start execution otherwise. The alignment to 128M is 882 * chosen arbitrarily but helps in debugging, as the MMU offset 883 * calculations are much more straight forward this way. 884 * 885 * On MC1.0 cores the linear window offset is ignored by the TS engine, 886 * leading to inconsistent memory views. Avoid using the offset on those 887 * cores if possible, otherwise disable the TS feature. MMUv2 doesn't 888 * expose this issue, as all TS accesses are MMU translated, so the 889 * linear window offset won't be used. 890 */ 891 cmdbuf_paddr = ALIGN_DOWN(etnaviv_cmdbuf_get_pa(&gpu->buffer), SZ_128M); 892 893 if (!(gpu->identity.features & chipFeatures_PIPE_3D) || 894 (gpu->identity.minor_features0 & chipMinorFeatures0_MC20) || 895 (gpu->identity.minor_features1 & chipMinorFeatures1_MMU_VERSION)) { 896 if (cmdbuf_paddr >= SZ_2G) 897 priv->mmu_global->memory_base = SZ_2G; 898 else 899 priv->mmu_global->memory_base = cmdbuf_paddr; 900 } else if (cmdbuf_paddr + SZ_128M >= SZ_2G) { 901 dev_info(gpu->dev, 902 "Need to move linear window on MC1.0, disabling TS\n"); 903 gpu->identity.features &= ~chipFeatures_FAST_CLEAR; 904 priv->mmu_global->memory_base = SZ_2G; 905 } 906 907 /* Setup event management */ 908 spin_lock_init(&gpu->event_spinlock); 909 init_completion(&gpu->event_free); 910 bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS); 911 for (i = 0; i < ARRAY_SIZE(gpu->event); i++) 912 complete(&gpu->event_free); 913 914 /* Now program the hardware */ 915 mutex_lock(&gpu->lock); 916 etnaviv_gpu_hw_init(gpu); 917 mutex_unlock(&gpu->lock); 918 919 pm_runtime_mark_last_busy(gpu->dev); 920 pm_runtime_put_autosuspend(gpu->dev); 921 922 return 0; 923 924 fail: 925 pm_runtime_mark_last_busy(gpu->dev); 926 pm_put: 927 pm_runtime_put_autosuspend(gpu->dev); 928 929 return ret; 930 } 931 932 #ifdef CONFIG_DEBUG_FS 933 struct dma_debug { 934 u32 address[2]; 935 u32 state[2]; 936 }; 937 938 static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug) 939 { 940 u32 i; 941 942 debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 943 debug->state[0] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE); 944 945 for (i = 0; i < 500; i++) { 946 debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 947 debug->state[1] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE); 948 949 if (debug->address[0] != debug->address[1]) 950 break; 951 952 if (debug->state[0] != debug->state[1]) 953 break; 954 } 955 } 956 957 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m) 958 { 959 struct dma_debug debug; 960 u32 dma_lo, dma_hi, axi, idle; 961 int ret; 962 963 seq_printf(m, "%s Status:\n", dev_name(gpu->dev)); 964 965 ret = pm_runtime_get_sync(gpu->dev); 966 if (ret < 0) 967 goto pm_put; 968 969 dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW); 970 dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH); 971 axi = gpu_read(gpu, VIVS_HI_AXI_STATUS); 972 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 973 974 verify_dma(gpu, &debug); 975 976 seq_puts(m, "\tidentity\n"); 977 seq_printf(m, "\t model: 0x%x\n", gpu->identity.model); 978 seq_printf(m, "\t revision: 0x%x\n", gpu->identity.revision); 979 seq_printf(m, "\t product_id: 0x%x\n", gpu->identity.product_id); 980 seq_printf(m, "\t customer_id: 0x%x\n", gpu->identity.customer_id); 981 seq_printf(m, "\t eco_id: 0x%x\n", gpu->identity.eco_id); 982 983 seq_puts(m, "\tfeatures\n"); 984 seq_printf(m, "\t major_features: 0x%08x\n", 985 gpu->identity.features); 986 seq_printf(m, "\t minor_features0: 0x%08x\n", 987 gpu->identity.minor_features0); 988 seq_printf(m, "\t minor_features1: 0x%08x\n", 989 gpu->identity.minor_features1); 990 seq_printf(m, "\t minor_features2: 0x%08x\n", 991 gpu->identity.minor_features2); 992 seq_printf(m, "\t minor_features3: 0x%08x\n", 993 gpu->identity.minor_features3); 994 seq_printf(m, "\t minor_features4: 0x%08x\n", 995 gpu->identity.minor_features4); 996 seq_printf(m, "\t minor_features5: 0x%08x\n", 997 gpu->identity.minor_features5); 998 seq_printf(m, "\t minor_features6: 0x%08x\n", 999 gpu->identity.minor_features6); 1000 seq_printf(m, "\t minor_features7: 0x%08x\n", 1001 gpu->identity.minor_features7); 1002 seq_printf(m, "\t minor_features8: 0x%08x\n", 1003 gpu->identity.minor_features8); 1004 seq_printf(m, "\t minor_features9: 0x%08x\n", 1005 gpu->identity.minor_features9); 1006 seq_printf(m, "\t minor_features10: 0x%08x\n", 1007 gpu->identity.minor_features10); 1008 seq_printf(m, "\t minor_features11: 0x%08x\n", 1009 gpu->identity.minor_features11); 1010 1011 seq_puts(m, "\tspecs\n"); 1012 seq_printf(m, "\t stream_count: %d\n", 1013 gpu->identity.stream_count); 1014 seq_printf(m, "\t register_max: %d\n", 1015 gpu->identity.register_max); 1016 seq_printf(m, "\t thread_count: %d\n", 1017 gpu->identity.thread_count); 1018 seq_printf(m, "\t vertex_cache_size: %d\n", 1019 gpu->identity.vertex_cache_size); 1020 seq_printf(m, "\t shader_core_count: %d\n", 1021 gpu->identity.shader_core_count); 1022 seq_printf(m, "\t nn_core_count: %d\n", 1023 gpu->identity.nn_core_count); 1024 seq_printf(m, "\t pixel_pipes: %d\n", 1025 gpu->identity.pixel_pipes); 1026 seq_printf(m, "\t vertex_output_buffer_size: %d\n", 1027 gpu->identity.vertex_output_buffer_size); 1028 seq_printf(m, "\t buffer_size: %d\n", 1029 gpu->identity.buffer_size); 1030 seq_printf(m, "\t instruction_count: %d\n", 1031 gpu->identity.instruction_count); 1032 seq_printf(m, "\t num_constants: %d\n", 1033 gpu->identity.num_constants); 1034 seq_printf(m, "\t varyings_count: %d\n", 1035 gpu->identity.varyings_count); 1036 1037 seq_printf(m, "\taxi: 0x%08x\n", axi); 1038 seq_printf(m, "\tidle: 0x%08x\n", idle); 1039 idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP; 1040 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) 1041 seq_puts(m, "\t FE is not idle\n"); 1042 if ((idle & VIVS_HI_IDLE_STATE_DE) == 0) 1043 seq_puts(m, "\t DE is not idle\n"); 1044 if ((idle & VIVS_HI_IDLE_STATE_PE) == 0) 1045 seq_puts(m, "\t PE is not idle\n"); 1046 if ((idle & VIVS_HI_IDLE_STATE_SH) == 0) 1047 seq_puts(m, "\t SH is not idle\n"); 1048 if ((idle & VIVS_HI_IDLE_STATE_PA) == 0) 1049 seq_puts(m, "\t PA is not idle\n"); 1050 if ((idle & VIVS_HI_IDLE_STATE_SE) == 0) 1051 seq_puts(m, "\t SE is not idle\n"); 1052 if ((idle & VIVS_HI_IDLE_STATE_RA) == 0) 1053 seq_puts(m, "\t RA is not idle\n"); 1054 if ((idle & VIVS_HI_IDLE_STATE_TX) == 0) 1055 seq_puts(m, "\t TX is not idle\n"); 1056 if ((idle & VIVS_HI_IDLE_STATE_VG) == 0) 1057 seq_puts(m, "\t VG is not idle\n"); 1058 if ((idle & VIVS_HI_IDLE_STATE_IM) == 0) 1059 seq_puts(m, "\t IM is not idle\n"); 1060 if ((idle & VIVS_HI_IDLE_STATE_FP) == 0) 1061 seq_puts(m, "\t FP is not idle\n"); 1062 if ((idle & VIVS_HI_IDLE_STATE_TS) == 0) 1063 seq_puts(m, "\t TS is not idle\n"); 1064 if ((idle & VIVS_HI_IDLE_STATE_BL) == 0) 1065 seq_puts(m, "\t BL is not idle\n"); 1066 if ((idle & VIVS_HI_IDLE_STATE_ASYNCFE) == 0) 1067 seq_puts(m, "\t ASYNCFE is not idle\n"); 1068 if ((idle & VIVS_HI_IDLE_STATE_MC) == 0) 1069 seq_puts(m, "\t MC is not idle\n"); 1070 if ((idle & VIVS_HI_IDLE_STATE_PPA) == 0) 1071 seq_puts(m, "\t PPA is not idle\n"); 1072 if ((idle & VIVS_HI_IDLE_STATE_WD) == 0) 1073 seq_puts(m, "\t WD is not idle\n"); 1074 if ((idle & VIVS_HI_IDLE_STATE_NN) == 0) 1075 seq_puts(m, "\t NN is not idle\n"); 1076 if ((idle & VIVS_HI_IDLE_STATE_TP) == 0) 1077 seq_puts(m, "\t TP is not idle\n"); 1078 if (idle & VIVS_HI_IDLE_STATE_AXI_LP) 1079 seq_puts(m, "\t AXI low power mode\n"); 1080 1081 if (gpu->identity.features & chipFeatures_DEBUG_MODE) { 1082 u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0); 1083 u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1); 1084 u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE); 1085 1086 seq_puts(m, "\tMC\n"); 1087 seq_printf(m, "\t read0: 0x%08x\n", read0); 1088 seq_printf(m, "\t read1: 0x%08x\n", read1); 1089 seq_printf(m, "\t write: 0x%08x\n", write); 1090 } 1091 1092 seq_puts(m, "\tDMA "); 1093 1094 if (debug.address[0] == debug.address[1] && 1095 debug.state[0] == debug.state[1]) { 1096 seq_puts(m, "seems to be stuck\n"); 1097 } else if (debug.address[0] == debug.address[1]) { 1098 seq_puts(m, "address is constant\n"); 1099 } else { 1100 seq_puts(m, "is running\n"); 1101 } 1102 1103 seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]); 1104 seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]); 1105 seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]); 1106 seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]); 1107 seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n", 1108 dma_lo, dma_hi); 1109 1110 ret = 0; 1111 1112 pm_runtime_mark_last_busy(gpu->dev); 1113 pm_put: 1114 pm_runtime_put_autosuspend(gpu->dev); 1115 1116 return ret; 1117 } 1118 #endif 1119 1120 /* fence object management */ 1121 struct etnaviv_fence { 1122 struct etnaviv_gpu *gpu; 1123 struct dma_fence base; 1124 }; 1125 1126 static inline struct etnaviv_fence *to_etnaviv_fence(struct dma_fence *fence) 1127 { 1128 return container_of(fence, struct etnaviv_fence, base); 1129 } 1130 1131 static const char *etnaviv_fence_get_driver_name(struct dma_fence *fence) 1132 { 1133 return "etnaviv"; 1134 } 1135 1136 static const char *etnaviv_fence_get_timeline_name(struct dma_fence *fence) 1137 { 1138 struct etnaviv_fence *f = to_etnaviv_fence(fence); 1139 1140 return dev_name(f->gpu->dev); 1141 } 1142 1143 static bool etnaviv_fence_signaled(struct dma_fence *fence) 1144 { 1145 struct etnaviv_fence *f = to_etnaviv_fence(fence); 1146 1147 return (s32)(f->gpu->completed_fence - f->base.seqno) >= 0; 1148 } 1149 1150 static void etnaviv_fence_release(struct dma_fence *fence) 1151 { 1152 struct etnaviv_fence *f = to_etnaviv_fence(fence); 1153 1154 kfree_rcu(f, base.rcu); 1155 } 1156 1157 static const struct dma_fence_ops etnaviv_fence_ops = { 1158 .get_driver_name = etnaviv_fence_get_driver_name, 1159 .get_timeline_name = etnaviv_fence_get_timeline_name, 1160 .signaled = etnaviv_fence_signaled, 1161 .release = etnaviv_fence_release, 1162 }; 1163 1164 static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu) 1165 { 1166 struct etnaviv_fence *f; 1167 1168 /* 1169 * GPU lock must already be held, otherwise fence completion order might 1170 * not match the seqno order assigned here. 1171 */ 1172 lockdep_assert_held(&gpu->lock); 1173 1174 f = kzalloc(sizeof(*f), GFP_KERNEL); 1175 if (!f) 1176 return NULL; 1177 1178 f->gpu = gpu; 1179 1180 dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock, 1181 gpu->fence_context, ++gpu->next_fence); 1182 1183 return &f->base; 1184 } 1185 1186 /* returns true if fence a comes after fence b */ 1187 static inline bool fence_after(u32 a, u32 b) 1188 { 1189 return (s32)(a - b) > 0; 1190 } 1191 1192 /* 1193 * event management: 1194 */ 1195 1196 static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events, 1197 unsigned int *events) 1198 { 1199 unsigned long timeout = msecs_to_jiffies(10 * 10000); 1200 unsigned i, acquired = 0, rpm_count = 0; 1201 int ret; 1202 1203 for (i = 0; i < nr_events; i++) { 1204 unsigned long remaining; 1205 1206 remaining = wait_for_completion_timeout(&gpu->event_free, timeout); 1207 1208 if (!remaining) { 1209 dev_err(gpu->dev, "wait_for_completion_timeout failed"); 1210 ret = -EBUSY; 1211 goto out; 1212 } 1213 1214 acquired++; 1215 timeout = remaining; 1216 } 1217 1218 spin_lock(&gpu->event_spinlock); 1219 1220 for (i = 0; i < nr_events; i++) { 1221 int event = find_first_zero_bit(gpu->event_bitmap, ETNA_NR_EVENTS); 1222 1223 events[i] = event; 1224 memset(&gpu->event[event], 0, sizeof(struct etnaviv_event)); 1225 set_bit(event, gpu->event_bitmap); 1226 } 1227 1228 spin_unlock(&gpu->event_spinlock); 1229 1230 for (i = 0; i < nr_events; i++) { 1231 ret = pm_runtime_resume_and_get(gpu->dev); 1232 if (ret) 1233 goto out_rpm; 1234 rpm_count++; 1235 } 1236 1237 return 0; 1238 1239 out_rpm: 1240 for (i = 0; i < rpm_count; i++) 1241 pm_runtime_put_autosuspend(gpu->dev); 1242 out: 1243 for (i = 0; i < acquired; i++) 1244 complete(&gpu->event_free); 1245 1246 return ret; 1247 } 1248 1249 static void event_free(struct etnaviv_gpu *gpu, unsigned int event) 1250 { 1251 if (!test_bit(event, gpu->event_bitmap)) { 1252 dev_warn(gpu->dev, "event %u is already marked as free", 1253 event); 1254 } else { 1255 clear_bit(event, gpu->event_bitmap); 1256 complete(&gpu->event_free); 1257 } 1258 1259 pm_runtime_put_autosuspend(gpu->dev); 1260 } 1261 1262 /* 1263 * Cmdstream submission/retirement: 1264 */ 1265 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu, 1266 u32 id, struct drm_etnaviv_timespec *timeout) 1267 { 1268 struct dma_fence *fence; 1269 int ret; 1270 1271 /* 1272 * Look up the fence and take a reference. We might still find a fence 1273 * whose refcount has already dropped to zero. dma_fence_get_rcu 1274 * pretends we didn't find a fence in that case. 1275 */ 1276 rcu_read_lock(); 1277 fence = xa_load(&gpu->user_fences, id); 1278 if (fence) 1279 fence = dma_fence_get_rcu(fence); 1280 rcu_read_unlock(); 1281 1282 if (!fence) 1283 return 0; 1284 1285 if (!timeout) { 1286 /* No timeout was requested: just test for completion */ 1287 ret = dma_fence_is_signaled(fence) ? 0 : -EBUSY; 1288 } else { 1289 unsigned long remaining = etnaviv_timeout_to_jiffies(timeout); 1290 1291 ret = dma_fence_wait_timeout(fence, true, remaining); 1292 if (ret == 0) 1293 ret = -ETIMEDOUT; 1294 else if (ret != -ERESTARTSYS) 1295 ret = 0; 1296 1297 } 1298 1299 dma_fence_put(fence); 1300 return ret; 1301 } 1302 1303 /* 1304 * Wait for an object to become inactive. This, on it's own, is not race 1305 * free: the object is moved by the scheduler off the active list, and 1306 * then the iova is put. Moreover, the object could be re-submitted just 1307 * after we notice that it's become inactive. 1308 * 1309 * Although the retirement happens under the gpu lock, we don't want to hold 1310 * that lock in this function while waiting. 1311 */ 1312 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu, 1313 struct etnaviv_gem_object *etnaviv_obj, 1314 struct drm_etnaviv_timespec *timeout) 1315 { 1316 unsigned long remaining; 1317 long ret; 1318 1319 if (!timeout) 1320 return !is_active(etnaviv_obj) ? 0 : -EBUSY; 1321 1322 remaining = etnaviv_timeout_to_jiffies(timeout); 1323 1324 ret = wait_event_interruptible_timeout(gpu->fence_event, 1325 !is_active(etnaviv_obj), 1326 remaining); 1327 if (ret > 0) 1328 return 0; 1329 else if (ret == -ERESTARTSYS) 1330 return -ERESTARTSYS; 1331 else 1332 return -ETIMEDOUT; 1333 } 1334 1335 static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu, 1336 struct etnaviv_event *event, unsigned int flags) 1337 { 1338 const struct etnaviv_gem_submit *submit = event->submit; 1339 unsigned int i; 1340 1341 for (i = 0; i < submit->nr_pmrs; i++) { 1342 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i; 1343 1344 if (pmr->flags == flags) 1345 etnaviv_perfmon_process(gpu, pmr, submit->exec_state); 1346 } 1347 } 1348 1349 static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu, 1350 struct etnaviv_event *event) 1351 { 1352 u32 val; 1353 1354 mutex_lock(&gpu->lock); 1355 1356 /* disable clock gating */ 1357 val = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS); 1358 val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; 1359 gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, val); 1360 1361 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE); 1362 1363 mutex_unlock(&gpu->lock); 1364 } 1365 1366 static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu, 1367 struct etnaviv_event *event) 1368 { 1369 const struct etnaviv_gem_submit *submit = event->submit; 1370 unsigned int i; 1371 u32 val; 1372 1373 mutex_lock(&gpu->lock); 1374 1375 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST); 1376 1377 /* enable clock gating */ 1378 val = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS); 1379 val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; 1380 gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, val); 1381 1382 mutex_unlock(&gpu->lock); 1383 1384 for (i = 0; i < submit->nr_pmrs; i++) { 1385 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i; 1386 1387 *pmr->bo_vma = pmr->sequence; 1388 } 1389 } 1390 1391 1392 /* add bo's to gpu's ring, and kick gpu: */ 1393 struct dma_fence *etnaviv_gpu_submit(struct etnaviv_gem_submit *submit) 1394 { 1395 struct etnaviv_gpu *gpu = submit->gpu; 1396 struct dma_fence *gpu_fence; 1397 unsigned int i, nr_events = 1, event[3]; 1398 int ret; 1399 1400 /* 1401 * if there are performance monitor requests we need to have 1402 * - a sync point to re-configure gpu and process ETNA_PM_PROCESS_PRE 1403 * requests. 1404 * - a sync point to re-configure gpu, process ETNA_PM_PROCESS_POST requests 1405 * and update the sequence number for userspace. 1406 */ 1407 if (submit->nr_pmrs) 1408 nr_events = 3; 1409 1410 ret = event_alloc(gpu, nr_events, event); 1411 if (ret) { 1412 DRM_ERROR("no free events\n"); 1413 pm_runtime_put_noidle(gpu->dev); 1414 return NULL; 1415 } 1416 1417 mutex_lock(&gpu->lock); 1418 1419 gpu_fence = etnaviv_gpu_fence_alloc(gpu); 1420 if (!gpu_fence) { 1421 for (i = 0; i < nr_events; i++) 1422 event_free(gpu, event[i]); 1423 1424 goto out_unlock; 1425 } 1426 1427 if (gpu->state == ETNA_GPU_STATE_INITIALIZED) 1428 etnaviv_gpu_start_fe_idleloop(gpu, submit->mmu_context); 1429 1430 if (submit->prev_mmu_context) 1431 etnaviv_iommu_context_put(submit->prev_mmu_context); 1432 submit->prev_mmu_context = etnaviv_iommu_context_get(gpu->mmu_context); 1433 1434 if (submit->nr_pmrs) { 1435 gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre; 1436 kref_get(&submit->refcount); 1437 gpu->event[event[1]].submit = submit; 1438 etnaviv_sync_point_queue(gpu, event[1]); 1439 } 1440 1441 gpu->event[event[0]].fence = gpu_fence; 1442 submit->cmdbuf.user_size = submit->cmdbuf.size - 8; 1443 etnaviv_buffer_queue(gpu, submit->exec_state, submit->mmu_context, 1444 event[0], &submit->cmdbuf); 1445 1446 if (submit->nr_pmrs) { 1447 gpu->event[event[2]].sync_point = &sync_point_perfmon_sample_post; 1448 kref_get(&submit->refcount); 1449 gpu->event[event[2]].submit = submit; 1450 etnaviv_sync_point_queue(gpu, event[2]); 1451 } 1452 1453 out_unlock: 1454 mutex_unlock(&gpu->lock); 1455 1456 return gpu_fence; 1457 } 1458 1459 static void sync_point_worker(struct work_struct *work) 1460 { 1461 struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu, 1462 sync_point_work); 1463 struct etnaviv_event *event = &gpu->event[gpu->sync_point_event]; 1464 u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 1465 1466 event->sync_point(gpu, event); 1467 etnaviv_submit_put(event->submit); 1468 event_free(gpu, gpu->sync_point_event); 1469 1470 /* restart FE last to avoid GPU and IRQ racing against this worker */ 1471 etnaviv_gpu_start_fe(gpu, addr + 2, 2); 1472 } 1473 1474 void etnaviv_gpu_recover_hang(struct etnaviv_gem_submit *submit) 1475 { 1476 struct etnaviv_gpu *gpu = submit->gpu; 1477 char *comm = NULL, *cmd = NULL; 1478 struct task_struct *task; 1479 unsigned int i; 1480 1481 dev_err(gpu->dev, "recover hung GPU!\n"); 1482 1483 task = get_pid_task(submit->pid, PIDTYPE_PID); 1484 if (task) { 1485 comm = kstrdup(task->comm, GFP_KERNEL); 1486 cmd = kstrdup_quotable_cmdline(task, GFP_KERNEL); 1487 put_task_struct(task); 1488 } 1489 1490 if (comm && cmd) 1491 dev_err(gpu->dev, "offending task: %s (%s)\n", comm, cmd); 1492 1493 kfree(cmd); 1494 kfree(comm); 1495 1496 if (pm_runtime_get_sync(gpu->dev) < 0) 1497 goto pm_put; 1498 1499 mutex_lock(&gpu->lock); 1500 1501 etnaviv_hw_reset(gpu); 1502 1503 /* complete all events, the GPU won't do it after the reset */ 1504 spin_lock(&gpu->event_spinlock); 1505 for_each_set_bit(i, gpu->event_bitmap, ETNA_NR_EVENTS) 1506 event_free(gpu, i); 1507 spin_unlock(&gpu->event_spinlock); 1508 1509 etnaviv_gpu_hw_init(gpu); 1510 1511 mutex_unlock(&gpu->lock); 1512 pm_runtime_mark_last_busy(gpu->dev); 1513 pm_put: 1514 pm_runtime_put_autosuspend(gpu->dev); 1515 } 1516 1517 static void dump_mmu_fault(struct etnaviv_gpu *gpu) 1518 { 1519 static const char *fault_reasons[] = { 1520 "slave not present", 1521 "page not present", 1522 "write violation", 1523 "out of bounds", 1524 "read security violation", 1525 "write security violation", 1526 }; 1527 1528 u32 status_reg, status; 1529 int i; 1530 1531 if (gpu->sec_mode == ETNA_SEC_NONE) 1532 status_reg = VIVS_MMUv2_STATUS; 1533 else 1534 status_reg = VIVS_MMUv2_SEC_STATUS; 1535 1536 status = gpu_read(gpu, status_reg); 1537 dev_err_ratelimited(gpu->dev, "MMU fault status 0x%08x\n", status); 1538 1539 for (i = 0; i < 4; i++) { 1540 const char *reason = "unknown"; 1541 u32 address_reg; 1542 u32 mmu_status; 1543 1544 mmu_status = (status >> (i * 4)) & VIVS_MMUv2_STATUS_EXCEPTION0__MASK; 1545 if (!mmu_status) 1546 continue; 1547 1548 if ((mmu_status - 1) < ARRAY_SIZE(fault_reasons)) 1549 reason = fault_reasons[mmu_status - 1]; 1550 1551 if (gpu->sec_mode == ETNA_SEC_NONE) 1552 address_reg = VIVS_MMUv2_EXCEPTION_ADDR(i); 1553 else 1554 address_reg = VIVS_MMUv2_SEC_EXCEPTION_ADDR; 1555 1556 dev_err_ratelimited(gpu->dev, 1557 "MMU %d fault (%s) addr 0x%08x\n", 1558 i, reason, gpu_read(gpu, address_reg)); 1559 } 1560 } 1561 1562 static irqreturn_t irq_handler(int irq, void *data) 1563 { 1564 struct etnaviv_gpu *gpu = data; 1565 irqreturn_t ret = IRQ_NONE; 1566 1567 u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE); 1568 1569 if (intr != 0) { 1570 ktime_t now = ktime_get(); 1571 int event; 1572 1573 pm_runtime_mark_last_busy(gpu->dev); 1574 1575 dev_dbg(gpu->dev, "intr 0x%08x\n", intr); 1576 1577 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) { 1578 dev_err(gpu->dev, "AXI bus error\n"); 1579 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR; 1580 } 1581 1582 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) { 1583 dump_mmu_fault(gpu); 1584 gpu->state = ETNA_GPU_STATE_FAULT; 1585 drm_sched_fault(&gpu->sched); 1586 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION; 1587 } 1588 1589 while ((event = ffs(intr)) != 0) { 1590 struct dma_fence *fence; 1591 1592 event -= 1; 1593 1594 intr &= ~(1 << event); 1595 1596 dev_dbg(gpu->dev, "event %u\n", event); 1597 1598 if (gpu->event[event].sync_point) { 1599 gpu->sync_point_event = event; 1600 queue_work(gpu->wq, &gpu->sync_point_work); 1601 } 1602 1603 fence = gpu->event[event].fence; 1604 if (!fence) 1605 continue; 1606 1607 gpu->event[event].fence = NULL; 1608 1609 /* 1610 * Events can be processed out of order. Eg, 1611 * - allocate and queue event 0 1612 * - allocate event 1 1613 * - event 0 completes, we process it 1614 * - allocate and queue event 0 1615 * - event 1 and event 0 complete 1616 * we can end up processing event 0 first, then 1. 1617 */ 1618 if (fence_after(fence->seqno, gpu->completed_fence)) 1619 gpu->completed_fence = fence->seqno; 1620 dma_fence_signal_timestamp(fence, now); 1621 1622 event_free(gpu, event); 1623 } 1624 1625 ret = IRQ_HANDLED; 1626 } 1627 1628 return ret; 1629 } 1630 1631 static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu) 1632 { 1633 int ret; 1634 1635 ret = clk_prepare_enable(gpu->clk_reg); 1636 if (ret) 1637 return ret; 1638 1639 ret = clk_prepare_enable(gpu->clk_bus); 1640 if (ret) 1641 goto disable_clk_reg; 1642 1643 ret = clk_prepare_enable(gpu->clk_core); 1644 if (ret) 1645 goto disable_clk_bus; 1646 1647 ret = clk_prepare_enable(gpu->clk_shader); 1648 if (ret) 1649 goto disable_clk_core; 1650 1651 return 0; 1652 1653 disable_clk_core: 1654 clk_disable_unprepare(gpu->clk_core); 1655 disable_clk_bus: 1656 clk_disable_unprepare(gpu->clk_bus); 1657 disable_clk_reg: 1658 clk_disable_unprepare(gpu->clk_reg); 1659 1660 return ret; 1661 } 1662 1663 static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu) 1664 { 1665 clk_disable_unprepare(gpu->clk_shader); 1666 clk_disable_unprepare(gpu->clk_core); 1667 clk_disable_unprepare(gpu->clk_bus); 1668 clk_disable_unprepare(gpu->clk_reg); 1669 1670 return 0; 1671 } 1672 1673 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms) 1674 { 1675 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms); 1676 1677 do { 1678 u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 1679 1680 if ((idle & gpu->idle_mask) == gpu->idle_mask) 1681 return 0; 1682 1683 if (time_is_before_jiffies(timeout)) { 1684 dev_warn(gpu->dev, 1685 "timed out waiting for idle: idle=0x%x\n", 1686 idle); 1687 return -ETIMEDOUT; 1688 } 1689 1690 udelay(5); 1691 } while (1); 1692 } 1693 1694 static void etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu) 1695 { 1696 if (gpu->state == ETNA_GPU_STATE_RUNNING) { 1697 /* Replace the last WAIT with END */ 1698 mutex_lock(&gpu->lock); 1699 etnaviv_buffer_end(gpu); 1700 mutex_unlock(&gpu->lock); 1701 1702 /* 1703 * We know that only the FE is busy here, this should 1704 * happen quickly (as the WAIT is only 200 cycles). If 1705 * we fail, just warn and continue. 1706 */ 1707 etnaviv_gpu_wait_idle(gpu, 100); 1708 1709 gpu->state = ETNA_GPU_STATE_INITIALIZED; 1710 } 1711 1712 gpu->exec_state = -1; 1713 } 1714 1715 static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu) 1716 { 1717 int ret; 1718 1719 ret = mutex_lock_killable(&gpu->lock); 1720 if (ret) 1721 return ret; 1722 1723 etnaviv_gpu_update_clock(gpu); 1724 etnaviv_gpu_hw_init(gpu); 1725 1726 mutex_unlock(&gpu->lock); 1727 1728 return 0; 1729 } 1730 1731 static int 1732 etnaviv_gpu_cooling_get_max_state(struct thermal_cooling_device *cdev, 1733 unsigned long *state) 1734 { 1735 *state = 6; 1736 1737 return 0; 1738 } 1739 1740 static int 1741 etnaviv_gpu_cooling_get_cur_state(struct thermal_cooling_device *cdev, 1742 unsigned long *state) 1743 { 1744 struct etnaviv_gpu *gpu = cdev->devdata; 1745 1746 *state = gpu->freq_scale; 1747 1748 return 0; 1749 } 1750 1751 static int 1752 etnaviv_gpu_cooling_set_cur_state(struct thermal_cooling_device *cdev, 1753 unsigned long state) 1754 { 1755 struct etnaviv_gpu *gpu = cdev->devdata; 1756 1757 mutex_lock(&gpu->lock); 1758 gpu->freq_scale = state; 1759 if (!pm_runtime_suspended(gpu->dev)) 1760 etnaviv_gpu_update_clock(gpu); 1761 mutex_unlock(&gpu->lock); 1762 1763 return 0; 1764 } 1765 1766 static const struct thermal_cooling_device_ops cooling_ops = { 1767 .get_max_state = etnaviv_gpu_cooling_get_max_state, 1768 .get_cur_state = etnaviv_gpu_cooling_get_cur_state, 1769 .set_cur_state = etnaviv_gpu_cooling_set_cur_state, 1770 }; 1771 1772 static int etnaviv_gpu_bind(struct device *dev, struct device *master, 1773 void *data) 1774 { 1775 struct drm_device *drm = data; 1776 struct etnaviv_drm_private *priv = drm->dev_private; 1777 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1778 int ret; 1779 1780 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) { 1781 gpu->cooling = thermal_of_cooling_device_register(dev->of_node, 1782 (char *)dev_name(dev), gpu, &cooling_ops); 1783 if (IS_ERR(gpu->cooling)) 1784 return PTR_ERR(gpu->cooling); 1785 } 1786 1787 gpu->wq = alloc_ordered_workqueue(dev_name(dev), 0); 1788 if (!gpu->wq) { 1789 ret = -ENOMEM; 1790 goto out_thermal; 1791 } 1792 1793 ret = etnaviv_sched_init(gpu); 1794 if (ret) 1795 goto out_workqueue; 1796 1797 if (!IS_ENABLED(CONFIG_PM)) { 1798 ret = etnaviv_gpu_clk_enable(gpu); 1799 if (ret < 0) 1800 goto out_sched; 1801 } 1802 1803 gpu->drm = drm; 1804 gpu->fence_context = dma_fence_context_alloc(1); 1805 xa_init_flags(&gpu->user_fences, XA_FLAGS_ALLOC); 1806 spin_lock_init(&gpu->fence_spinlock); 1807 1808 INIT_WORK(&gpu->sync_point_work, sync_point_worker); 1809 init_waitqueue_head(&gpu->fence_event); 1810 1811 priv->gpu[priv->num_gpus++] = gpu; 1812 1813 return 0; 1814 1815 out_sched: 1816 etnaviv_sched_fini(gpu); 1817 1818 out_workqueue: 1819 destroy_workqueue(gpu->wq); 1820 1821 out_thermal: 1822 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) 1823 thermal_cooling_device_unregister(gpu->cooling); 1824 1825 return ret; 1826 } 1827 1828 static void etnaviv_gpu_unbind(struct device *dev, struct device *master, 1829 void *data) 1830 { 1831 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1832 1833 DBG("%s", dev_name(gpu->dev)); 1834 1835 destroy_workqueue(gpu->wq); 1836 1837 etnaviv_sched_fini(gpu); 1838 1839 if (IS_ENABLED(CONFIG_PM)) { 1840 pm_runtime_get_sync(gpu->dev); 1841 pm_runtime_put_sync_suspend(gpu->dev); 1842 } else { 1843 etnaviv_gpu_hw_suspend(gpu); 1844 etnaviv_gpu_clk_disable(gpu); 1845 } 1846 1847 if (gpu->mmu_context) 1848 etnaviv_iommu_context_put(gpu->mmu_context); 1849 1850 etnaviv_cmdbuf_free(&gpu->buffer); 1851 etnaviv_iommu_global_fini(gpu); 1852 1853 gpu->drm = NULL; 1854 xa_destroy(&gpu->user_fences); 1855 1856 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) 1857 thermal_cooling_device_unregister(gpu->cooling); 1858 gpu->cooling = NULL; 1859 } 1860 1861 static const struct component_ops gpu_ops = { 1862 .bind = etnaviv_gpu_bind, 1863 .unbind = etnaviv_gpu_unbind, 1864 }; 1865 1866 static const struct of_device_id etnaviv_gpu_match[] = { 1867 { 1868 .compatible = "vivante,gc" 1869 }, 1870 { /* sentinel */ } 1871 }; 1872 MODULE_DEVICE_TABLE(of, etnaviv_gpu_match); 1873 1874 static int etnaviv_gpu_platform_probe(struct platform_device *pdev) 1875 { 1876 struct device *dev = &pdev->dev; 1877 struct etnaviv_gpu *gpu; 1878 int err; 1879 1880 gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL); 1881 if (!gpu) 1882 return -ENOMEM; 1883 1884 gpu->dev = dev; 1885 mutex_init(&gpu->lock); 1886 mutex_init(&gpu->sched_lock); 1887 1888 /* Map registers: */ 1889 gpu->mmio = devm_platform_ioremap_resource(pdev, 0); 1890 if (IS_ERR(gpu->mmio)) 1891 return PTR_ERR(gpu->mmio); 1892 1893 1894 /* Get Reset: */ 1895 gpu->rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); 1896 if (IS_ERR(gpu->rst)) 1897 return dev_err_probe(dev, PTR_ERR(gpu->rst), 1898 "failed to get reset\n"); 1899 1900 err = reset_control_assert(gpu->rst); 1901 if (err) 1902 return dev_err_probe(dev, err, "failed to assert reset\n"); 1903 1904 /* Get Interrupt: */ 1905 gpu->irq = platform_get_irq(pdev, 0); 1906 if (gpu->irq < 0) 1907 return gpu->irq; 1908 1909 err = devm_request_irq(dev, gpu->irq, irq_handler, 0, 1910 dev_name(dev), gpu); 1911 if (err) { 1912 dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err); 1913 return err; 1914 } 1915 1916 /* Get Clocks: */ 1917 gpu->clk_reg = devm_clk_get_optional(&pdev->dev, "reg"); 1918 DBG("clk_reg: %p", gpu->clk_reg); 1919 if (IS_ERR(gpu->clk_reg)) 1920 return PTR_ERR(gpu->clk_reg); 1921 1922 gpu->clk_bus = devm_clk_get_optional(&pdev->dev, "bus"); 1923 DBG("clk_bus: %p", gpu->clk_bus); 1924 if (IS_ERR(gpu->clk_bus)) 1925 return PTR_ERR(gpu->clk_bus); 1926 1927 gpu->clk_core = devm_clk_get(&pdev->dev, "core"); 1928 DBG("clk_core: %p", gpu->clk_core); 1929 if (IS_ERR(gpu->clk_core)) 1930 return PTR_ERR(gpu->clk_core); 1931 gpu->base_rate_core = clk_get_rate(gpu->clk_core); 1932 1933 gpu->clk_shader = devm_clk_get_optional(&pdev->dev, "shader"); 1934 DBG("clk_shader: %p", gpu->clk_shader); 1935 if (IS_ERR(gpu->clk_shader)) 1936 return PTR_ERR(gpu->clk_shader); 1937 gpu->base_rate_shader = clk_get_rate(gpu->clk_shader); 1938 1939 /* TODO: figure out max mapped size */ 1940 dev_set_drvdata(dev, gpu); 1941 1942 /* 1943 * We treat the device as initially suspended. The runtime PM 1944 * autosuspend delay is rather arbitary: no measurements have 1945 * yet been performed to determine an appropriate value. 1946 */ 1947 pm_runtime_use_autosuspend(dev); 1948 pm_runtime_set_autosuspend_delay(dev, 200); 1949 pm_runtime_enable(dev); 1950 1951 err = component_add(dev, &gpu_ops); 1952 if (err < 0) { 1953 dev_err(dev, "failed to register component: %d\n", err); 1954 return err; 1955 } 1956 1957 return 0; 1958 } 1959 1960 static void etnaviv_gpu_platform_remove(struct platform_device *pdev) 1961 { 1962 struct etnaviv_gpu *gpu = dev_get_drvdata(&pdev->dev); 1963 1964 component_del(&pdev->dev, &gpu_ops); 1965 pm_runtime_disable(&pdev->dev); 1966 1967 mutex_destroy(&gpu->lock); 1968 mutex_destroy(&gpu->sched_lock); 1969 } 1970 1971 static int etnaviv_gpu_rpm_suspend(struct device *dev) 1972 { 1973 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1974 u32 idle, mask; 1975 1976 /* If there are any jobs in the HW queue, we're not idle */ 1977 if (atomic_read(&gpu->sched.credit_count)) 1978 return -EBUSY; 1979 1980 /* Check whether the hardware (except FE and MC) is idle */ 1981 mask = gpu->idle_mask & ~(VIVS_HI_IDLE_STATE_FE | 1982 VIVS_HI_IDLE_STATE_MC); 1983 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask; 1984 if (idle != mask) { 1985 dev_warn_ratelimited(dev, "GPU not yet idle, mask: 0x%08x\n", 1986 idle); 1987 return -EBUSY; 1988 } 1989 1990 etnaviv_gpu_hw_suspend(gpu); 1991 1992 gpu->state = ETNA_GPU_STATE_IDENTIFIED; 1993 1994 return etnaviv_gpu_clk_disable(gpu); 1995 } 1996 1997 static int etnaviv_gpu_rpm_resume(struct device *dev) 1998 { 1999 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 2000 int ret; 2001 2002 ret = etnaviv_gpu_clk_enable(gpu); 2003 if (ret) 2004 return ret; 2005 2006 /* Re-initialise the basic hardware state */ 2007 if (gpu->state == ETNA_GPU_STATE_IDENTIFIED) { 2008 ret = etnaviv_gpu_hw_resume(gpu); 2009 if (ret) { 2010 etnaviv_gpu_clk_disable(gpu); 2011 return ret; 2012 } 2013 } 2014 2015 return 0; 2016 } 2017 2018 static const struct dev_pm_ops etnaviv_gpu_pm_ops = { 2019 RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume, NULL) 2020 }; 2021 2022 struct platform_driver etnaviv_gpu_driver = { 2023 .driver = { 2024 .name = "etnaviv-gpu", 2025 .pm = pm_ptr(&etnaviv_gpu_pm_ops), 2026 .of_match_table = etnaviv_gpu_match, 2027 }, 2028 .probe = etnaviv_gpu_platform_probe, 2029 .remove = etnaviv_gpu_platform_remove, 2030 .id_table = gpu_ids, 2031 }; 2032