1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2015-2018 Etnaviv Project 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/component.h> 8 #include <linux/delay.h> 9 #include <linux/dma-fence.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/regulator/consumer.h> 15 #include <linux/reset.h> 16 #include <linux/thermal.h> 17 18 #include <drm/drm_print.h> 19 20 #include "etnaviv_cmdbuf.h" 21 #include "etnaviv_dump.h" 22 #include "etnaviv_flop_reset.h" 23 #include "etnaviv_gpu.h" 24 #include "etnaviv_gem.h" 25 #include "etnaviv_mmu.h" 26 #include "etnaviv_perfmon.h" 27 #include "etnaviv_sched.h" 28 #include "common.xml.h" 29 #include "state.xml.h" 30 #include "state_hi.xml.h" 31 #include "cmdstream.xml.h" 32 33 static const struct platform_device_id gpu_ids[] = { 34 { .name = "etnaviv-gpu,2d" }, 35 { }, 36 }; 37 38 /* 39 * Driver functions: 40 */ 41 42 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value) 43 { 44 struct etnaviv_drm_private *priv = gpu->drm->dev_private; 45 46 switch (param) { 47 case ETNAVIV_PARAM_GPU_MODEL: 48 *value = gpu->identity.model; 49 break; 50 51 case ETNAVIV_PARAM_GPU_REVISION: 52 *value = gpu->identity.revision; 53 break; 54 55 case ETNAVIV_PARAM_GPU_FEATURES_0: 56 *value = gpu->identity.features; 57 break; 58 59 case ETNAVIV_PARAM_GPU_FEATURES_1: 60 *value = gpu->identity.minor_features0; 61 break; 62 63 case ETNAVIV_PARAM_GPU_FEATURES_2: 64 *value = gpu->identity.minor_features1; 65 break; 66 67 case ETNAVIV_PARAM_GPU_FEATURES_3: 68 *value = gpu->identity.minor_features2; 69 break; 70 71 case ETNAVIV_PARAM_GPU_FEATURES_4: 72 *value = gpu->identity.minor_features3; 73 break; 74 75 case ETNAVIV_PARAM_GPU_FEATURES_5: 76 *value = gpu->identity.minor_features4; 77 break; 78 79 case ETNAVIV_PARAM_GPU_FEATURES_6: 80 *value = gpu->identity.minor_features5; 81 break; 82 83 case ETNAVIV_PARAM_GPU_FEATURES_7: 84 *value = gpu->identity.minor_features6; 85 break; 86 87 case ETNAVIV_PARAM_GPU_FEATURES_8: 88 *value = gpu->identity.minor_features7; 89 break; 90 91 case ETNAVIV_PARAM_GPU_FEATURES_9: 92 *value = gpu->identity.minor_features8; 93 break; 94 95 case ETNAVIV_PARAM_GPU_FEATURES_10: 96 *value = gpu->identity.minor_features9; 97 break; 98 99 case ETNAVIV_PARAM_GPU_FEATURES_11: 100 *value = gpu->identity.minor_features10; 101 break; 102 103 case ETNAVIV_PARAM_GPU_FEATURES_12: 104 *value = gpu->identity.minor_features11; 105 break; 106 107 case ETNAVIV_PARAM_GPU_STREAM_COUNT: 108 *value = gpu->identity.stream_count; 109 break; 110 111 case ETNAVIV_PARAM_GPU_REGISTER_MAX: 112 *value = gpu->identity.register_max; 113 break; 114 115 case ETNAVIV_PARAM_GPU_THREAD_COUNT: 116 *value = gpu->identity.thread_count; 117 break; 118 119 case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE: 120 *value = gpu->identity.vertex_cache_size; 121 break; 122 123 case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT: 124 *value = gpu->identity.shader_core_count; 125 break; 126 127 case ETNAVIV_PARAM_GPU_PIXEL_PIPES: 128 *value = gpu->identity.pixel_pipes; 129 break; 130 131 case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE: 132 *value = gpu->identity.vertex_output_buffer_size; 133 break; 134 135 case ETNAVIV_PARAM_GPU_BUFFER_SIZE: 136 *value = gpu->identity.buffer_size; 137 break; 138 139 case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT: 140 *value = gpu->identity.instruction_count; 141 break; 142 143 case ETNAVIV_PARAM_GPU_NUM_CONSTANTS: 144 *value = gpu->identity.num_constants; 145 break; 146 147 case ETNAVIV_PARAM_GPU_NUM_VARYINGS: 148 *value = gpu->identity.varyings_count; 149 break; 150 151 case ETNAVIV_PARAM_SOFTPIN_START_ADDR: 152 if (priv->mmu_global->version == ETNAVIV_IOMMU_V2) 153 *value = ETNAVIV_SOFTPIN_START_ADDRESS; 154 else 155 *value = ~0ULL; 156 break; 157 158 case ETNAVIV_PARAM_GPU_PRODUCT_ID: 159 *value = gpu->identity.product_id; 160 break; 161 162 case ETNAVIV_PARAM_GPU_CUSTOMER_ID: 163 *value = gpu->identity.customer_id; 164 break; 165 166 case ETNAVIV_PARAM_GPU_ECO_ID: 167 *value = gpu->identity.eco_id; 168 break; 169 170 default: 171 DBG("%s: invalid param: %u", dev_name(gpu->dev), param); 172 return -EINVAL; 173 } 174 175 return 0; 176 } 177 178 static int etnaviv_gpu_reset_deassert(struct etnaviv_gpu *gpu) 179 { 180 int ret; 181 182 /* 183 * 32 core clock cycles (slowest clock) required before deassertion 184 * 1 microsecond might match all implementations without computation 185 */ 186 usleep_range(1, 2); 187 188 ret = reset_control_deassert(gpu->rst); 189 if (ret) 190 return ret; 191 192 /* 193 * 128 core clock cycles (slowest clock) required before any activity on AHB 194 * 1 microsecond might match all implementations without computation 195 */ 196 usleep_range(1, 2); 197 198 return 0; 199 } 200 201 static inline bool etnaviv_is_model_rev(struct etnaviv_gpu *gpu, u32 model, u32 revision) 202 { 203 return gpu->identity.model == model && 204 gpu->identity.revision == revision; 205 } 206 207 #define etnaviv_field(val, field) \ 208 (((val) & field##__MASK) >> field##__SHIFT) 209 210 static void etnaviv_hw_specs(struct etnaviv_gpu *gpu) 211 { 212 if (gpu->identity.minor_features0 & 213 chipMinorFeatures0_MORE_MINOR_FEATURES) { 214 u32 specs[4]; 215 unsigned int streams; 216 217 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS); 218 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2); 219 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3); 220 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4); 221 222 gpu->identity.stream_count = etnaviv_field(specs[0], 223 VIVS_HI_CHIP_SPECS_STREAM_COUNT); 224 gpu->identity.register_max = etnaviv_field(specs[0], 225 VIVS_HI_CHIP_SPECS_REGISTER_MAX); 226 gpu->identity.thread_count = etnaviv_field(specs[0], 227 VIVS_HI_CHIP_SPECS_THREAD_COUNT); 228 gpu->identity.vertex_cache_size = etnaviv_field(specs[0], 229 VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE); 230 gpu->identity.shader_core_count = etnaviv_field(specs[0], 231 VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT); 232 gpu->identity.pixel_pipes = etnaviv_field(specs[0], 233 VIVS_HI_CHIP_SPECS_PIXEL_PIPES); 234 gpu->identity.vertex_output_buffer_size = 235 etnaviv_field(specs[0], 236 VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE); 237 238 gpu->identity.buffer_size = etnaviv_field(specs[1], 239 VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE); 240 gpu->identity.instruction_count = etnaviv_field(specs[1], 241 VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT); 242 gpu->identity.num_constants = etnaviv_field(specs[1], 243 VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS); 244 245 gpu->identity.varyings_count = etnaviv_field(specs[2], 246 VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT); 247 248 /* This overrides the value from older register if non-zero */ 249 streams = etnaviv_field(specs[3], 250 VIVS_HI_CHIP_SPECS_4_STREAM_COUNT); 251 if (streams) 252 gpu->identity.stream_count = streams; 253 } 254 255 /* Fill in the stream count if not specified */ 256 if (gpu->identity.stream_count == 0) { 257 if (gpu->identity.model >= 0x1000) 258 gpu->identity.stream_count = 4; 259 else 260 gpu->identity.stream_count = 1; 261 } 262 263 /* Convert the register max value */ 264 if (gpu->identity.register_max) 265 gpu->identity.register_max = 1 << gpu->identity.register_max; 266 else if (gpu->identity.model == chipModel_GC400) 267 gpu->identity.register_max = 32; 268 else 269 gpu->identity.register_max = 64; 270 271 /* Convert thread count */ 272 if (gpu->identity.thread_count) 273 gpu->identity.thread_count = 1 << gpu->identity.thread_count; 274 else if (gpu->identity.model == chipModel_GC400) 275 gpu->identity.thread_count = 64; 276 else if (gpu->identity.model == chipModel_GC500 || 277 gpu->identity.model == chipModel_GC530) 278 gpu->identity.thread_count = 128; 279 else 280 gpu->identity.thread_count = 256; 281 282 if (gpu->identity.vertex_cache_size == 0) 283 gpu->identity.vertex_cache_size = 8; 284 285 if (gpu->identity.shader_core_count == 0) { 286 if (gpu->identity.model >= 0x1000) 287 gpu->identity.shader_core_count = 2; 288 else 289 gpu->identity.shader_core_count = 1; 290 } 291 292 if (gpu->identity.pixel_pipes == 0) 293 gpu->identity.pixel_pipes = 1; 294 295 /* Convert virtex buffer size */ 296 if (gpu->identity.vertex_output_buffer_size) { 297 gpu->identity.vertex_output_buffer_size = 298 1 << gpu->identity.vertex_output_buffer_size; 299 } else if (gpu->identity.model == chipModel_GC400) { 300 if (gpu->identity.revision < 0x4000) 301 gpu->identity.vertex_output_buffer_size = 512; 302 else if (gpu->identity.revision < 0x4200) 303 gpu->identity.vertex_output_buffer_size = 256; 304 else 305 gpu->identity.vertex_output_buffer_size = 128; 306 } else { 307 gpu->identity.vertex_output_buffer_size = 512; 308 } 309 310 switch (gpu->identity.instruction_count) { 311 case 0: 312 if (etnaviv_is_model_rev(gpu, 0x2000, 0x5108) || 313 gpu->identity.model == chipModel_GC880) 314 gpu->identity.instruction_count = 512; 315 else 316 gpu->identity.instruction_count = 256; 317 break; 318 319 case 1: 320 gpu->identity.instruction_count = 1024; 321 break; 322 323 case 2: 324 gpu->identity.instruction_count = 2048; 325 break; 326 327 default: 328 gpu->identity.instruction_count = 256; 329 break; 330 } 331 332 if (gpu->identity.num_constants == 0) 333 gpu->identity.num_constants = 168; 334 335 if (gpu->identity.varyings_count == 0) { 336 if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0) 337 gpu->identity.varyings_count = 12; 338 else 339 gpu->identity.varyings_count = 8; 340 } 341 342 /* 343 * For some cores, two varyings are consumed for position, so the 344 * maximum varying count needs to be reduced by one. 345 */ 346 if (etnaviv_is_model_rev(gpu, 0x5000, 0x5434) || 347 etnaviv_is_model_rev(gpu, 0x4000, 0x5222) || 348 etnaviv_is_model_rev(gpu, 0x4000, 0x5245) || 349 etnaviv_is_model_rev(gpu, 0x4000, 0x5208) || 350 etnaviv_is_model_rev(gpu, 0x3000, 0x5435) || 351 etnaviv_is_model_rev(gpu, 0x2200, 0x5244) || 352 etnaviv_is_model_rev(gpu, 0x2100, 0x5108) || 353 etnaviv_is_model_rev(gpu, 0x2000, 0x5108) || 354 etnaviv_is_model_rev(gpu, 0x1500, 0x5246) || 355 etnaviv_is_model_rev(gpu, 0x880, 0x5107) || 356 etnaviv_is_model_rev(gpu, 0x880, 0x5106)) 357 gpu->identity.varyings_count -= 1; 358 } 359 360 static void etnaviv_hw_identify(struct etnaviv_gpu *gpu) 361 { 362 u32 chipIdentity; 363 364 chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY); 365 366 /* Special case for older graphic cores. */ 367 if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) { 368 gpu->identity.model = chipModel_GC500; 369 gpu->identity.revision = etnaviv_field(chipIdentity, 370 VIVS_HI_CHIP_IDENTITY_REVISION); 371 } else { 372 u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE); 373 374 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL); 375 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV); 376 gpu->identity.customer_id = gpu_read(gpu, VIVS_HI_CHIP_CUSTOMER_ID); 377 378 /* 379 * Reading these two registers on GC600 rev 0x19 result in a 380 * unhandled fault: external abort on non-linefetch 381 */ 382 if (!etnaviv_is_model_rev(gpu, 0x600, 0x19)) { 383 gpu->identity.product_id = gpu_read(gpu, VIVS_HI_CHIP_PRODUCT_ID); 384 gpu->identity.eco_id = gpu_read(gpu, VIVS_HI_CHIP_ECO_ID); 385 } 386 387 /* 388 * !!!! HACK ALERT !!!! 389 * Because people change device IDs without letting software 390 * know about it - here is the hack to make it all look the 391 * same. Only for GC400 family. 392 */ 393 if ((gpu->identity.model & 0xff00) == 0x0400 && 394 gpu->identity.model != chipModel_GC420) { 395 gpu->identity.model = gpu->identity.model & 0x0400; 396 } 397 398 /* Another special case */ 399 if (etnaviv_is_model_rev(gpu, 0x300, 0x2201)) { 400 u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME); 401 402 if (chipDate == 0x20080814 && chipTime == 0x12051100) { 403 /* 404 * This IP has an ECO; put the correct 405 * revision in it. 406 */ 407 gpu->identity.revision = 0x1051; 408 } 409 } 410 411 /* 412 * NXP likes to call the GPU on the i.MX6QP GC2000+, but in 413 * reality it's just a re-branded GC3000. We can identify this 414 * core by the upper half of the revision register being all 1. 415 * Fix model/rev here, so all other places can refer to this 416 * core by its real identity. 417 */ 418 if (etnaviv_is_model_rev(gpu, 0x2000, 0xffff5450)) { 419 gpu->identity.model = chipModel_GC3000; 420 gpu->identity.revision &= 0xffff; 421 } 422 423 if (etnaviv_is_model_rev(gpu, 0x1000, 0x5037) && (chipDate == 0x20120617)) 424 gpu->identity.eco_id = 1; 425 426 if (etnaviv_is_model_rev(gpu, 0x320, 0x5303) && (chipDate == 0x20140511)) 427 gpu->identity.eco_id = 1; 428 } 429 430 dev_info(gpu->dev, "model: GC%x, revision: %x\n", 431 gpu->identity.model, gpu->identity.revision); 432 433 gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP; 434 /* 435 * If there is a match in the HWDB, we aren't interested in the 436 * remaining register values, as they might be wrong. 437 */ 438 if (etnaviv_fill_identity_from_hwdb(gpu)) 439 return; 440 441 gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE); 442 443 /* Disable fast clear on GC700. */ 444 if (gpu->identity.model == chipModel_GC700) 445 gpu->identity.features &= ~chipFeatures_FAST_CLEAR; 446 447 /* These models/revisions don't have the 2D pipe bit */ 448 if ((gpu->identity.model == chipModel_GC500 && 449 gpu->identity.revision <= 2) || 450 gpu->identity.model == chipModel_GC300) 451 gpu->identity.features |= chipFeatures_PIPE_2D; 452 453 if ((gpu->identity.model == chipModel_GC500 && 454 gpu->identity.revision < 2) || 455 (gpu->identity.model == chipModel_GC300 && 456 gpu->identity.revision < 0x2000)) { 457 458 /* 459 * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these 460 * registers. 461 */ 462 gpu->identity.minor_features0 = 0; 463 gpu->identity.minor_features1 = 0; 464 gpu->identity.minor_features2 = 0; 465 gpu->identity.minor_features3 = 0; 466 gpu->identity.minor_features4 = 0; 467 gpu->identity.minor_features5 = 0; 468 } else 469 gpu->identity.minor_features0 = 470 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0); 471 472 if (gpu->identity.minor_features0 & 473 chipMinorFeatures0_MORE_MINOR_FEATURES) { 474 gpu->identity.minor_features1 = 475 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1); 476 gpu->identity.minor_features2 = 477 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2); 478 gpu->identity.minor_features3 = 479 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3); 480 gpu->identity.minor_features4 = 481 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4); 482 gpu->identity.minor_features5 = 483 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5); 484 } 485 486 /* GC600/300 idle register reports zero bits where modules aren't present */ 487 if (gpu->identity.model == chipModel_GC600 || 488 gpu->identity.model == chipModel_GC300) 489 gpu->idle_mask = VIVS_HI_IDLE_STATE_TX | 490 VIVS_HI_IDLE_STATE_RA | 491 VIVS_HI_IDLE_STATE_SE | 492 VIVS_HI_IDLE_STATE_PA | 493 VIVS_HI_IDLE_STATE_SH | 494 VIVS_HI_IDLE_STATE_PE | 495 VIVS_HI_IDLE_STATE_DE | 496 VIVS_HI_IDLE_STATE_FE; 497 498 etnaviv_hw_specs(gpu); 499 } 500 501 static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock) 502 { 503 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock | 504 VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD); 505 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); 506 } 507 508 static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu) 509 { 510 if (gpu->identity.minor_features2 & 511 chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING) { 512 clk_set_rate(gpu->clk_core, 513 gpu->base_rate_core >> gpu->freq_scale); 514 clk_set_rate(gpu->clk_shader, 515 gpu->base_rate_shader >> gpu->freq_scale); 516 } else { 517 unsigned int fscale = 1 << (6 - gpu->freq_scale); 518 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 519 520 clock &= ~VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK; 521 clock |= VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale); 522 etnaviv_gpu_load_clock(gpu, clock); 523 } 524 525 /* 526 * Choose number of wait cycles to target a ~30us (1/32768) max latency 527 * until new work is picked up by the FE when it polls in the idle loop. 528 * If the GPU base frequency is unknown use 200 wait cycles. 529 */ 530 gpu->fe_waitcycles = clamp(gpu->base_rate_core >> (15 - gpu->freq_scale), 531 200UL, 0xffffUL); 532 } 533 534 static int etnaviv_hw_reset(struct etnaviv_gpu *gpu) 535 { 536 u32 control, idle; 537 unsigned long timeout; 538 bool failed = true; 539 540 /* We hope that the GPU resets in under one second */ 541 timeout = jiffies + msecs_to_jiffies(1000); 542 543 while (time_is_after_jiffies(timeout)) { 544 unsigned int fscale = 1 << (6 - gpu->freq_scale); 545 u32 pulse_eater = 0x01590880; 546 547 /* disable clock gating */ 548 gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, 0x0); 549 550 /* disable pulse eater */ 551 pulse_eater |= BIT(17); 552 gpu_write_power(gpu, VIVS_PM_PULSE_EATER, pulse_eater); 553 pulse_eater |= BIT(0); 554 gpu_write_power(gpu, VIVS_PM_PULSE_EATER, pulse_eater); 555 556 /* enable clock */ 557 control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale); 558 etnaviv_gpu_load_clock(gpu, control); 559 560 /* isolate the GPU. */ 561 control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU; 562 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 563 564 if (gpu->sec_mode == ETNA_SEC_KERNEL) { 565 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, 566 VIVS_MMUv2_AHB_CONTROL_RESET); 567 } else { 568 /* set soft reset. */ 569 control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET; 570 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 571 } 572 573 /* wait for reset. */ 574 usleep_range(10, 20); 575 576 /* reset soft reset bit. */ 577 control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET; 578 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 579 580 /* reset GPU isolation. */ 581 control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU; 582 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 583 584 /* read idle register. */ 585 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 586 587 /* try resetting again if FE is not idle */ 588 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) { 589 dev_dbg(gpu->dev, "FE is not idle\n"); 590 continue; 591 } 592 593 /* read reset register. */ 594 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 595 596 /* is the GPU idle? */ 597 if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) || 598 ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) { 599 dev_dbg(gpu->dev, "GPU is not idle\n"); 600 continue; 601 } 602 603 /* enable debug register access */ 604 control &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS; 605 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 606 607 failed = false; 608 break; 609 } 610 611 if (failed) { 612 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 613 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 614 615 dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n", 616 idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ", 617 control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ", 618 control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not "); 619 620 return -EBUSY; 621 } 622 623 /* We rely on the GPU running, so program the clock */ 624 etnaviv_gpu_update_clock(gpu); 625 626 gpu->state = ETNA_GPU_STATE_RESET; 627 gpu->exec_state = -1; 628 if (gpu->mmu_context) 629 etnaviv_iommu_context_put(gpu->mmu_context); 630 gpu->mmu_context = NULL; 631 632 return 0; 633 } 634 635 static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu) 636 { 637 u32 pmc, ppc; 638 639 /* enable clock gating */ 640 ppc = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS); 641 ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; 642 643 /* Disable stall module clock gating for 4.3.0.1 and 4.3.0.2 revs */ 644 if (gpu->identity.revision == 0x4301 || 645 gpu->identity.revision == 0x4302) 646 ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING; 647 648 gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, ppc); 649 650 pmc = gpu_read_power(gpu, VIVS_PM_MODULE_CONTROLS); 651 652 /* Disable PA clock gating for GC400+ without bugfix except for GC420 */ 653 if (gpu->identity.model >= chipModel_GC400 && 654 gpu->identity.model != chipModel_GC420 && 655 !(gpu->identity.minor_features3 & chipMinorFeatures3_BUG_FIXES12)) 656 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA; 657 658 /* 659 * Disable PE clock gating on revs < 5.0.0.0 when HZ is 660 * present without a bug fix. 661 */ 662 if (gpu->identity.revision < 0x5000 && 663 gpu->identity.minor_features0 & chipMinorFeatures0_HZ && 664 !(gpu->identity.minor_features1 & 665 chipMinorFeatures1_DISABLE_PE_GATING)) 666 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE; 667 668 if (gpu->identity.revision < 0x5422) 669 pmc |= BIT(15); /* Unknown bit */ 670 671 /* Disable TX clock gating on affected core revisions. */ 672 if (etnaviv_is_model_rev(gpu, 0x4000, 0x5222) || 673 etnaviv_is_model_rev(gpu, 0x2000, 0x5108) || 674 etnaviv_is_model_rev(gpu, 0x7000, 0x6202) || 675 etnaviv_is_model_rev(gpu, 0x7000, 0x6203)) 676 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX; 677 678 /* Disable SE and RA clock gating on affected core revisions. */ 679 if (etnaviv_is_model_rev(gpu, 0x7000, 0x6202)) 680 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE | 681 VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA; 682 683 /* Disable SH_EU clock gating on affected core revisions. */ 684 if (etnaviv_is_model_rev(gpu, 0x8000, 0x7200) || 685 etnaviv_is_model_rev(gpu, 0x8000, 0x8002) || 686 etnaviv_is_model_rev(gpu, 0x9200, 0x6304)) 687 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SH_EU; 688 689 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ; 690 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ; 691 692 gpu_write_power(gpu, VIVS_PM_MODULE_CONTROLS, pmc); 693 } 694 695 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch) 696 { 697 gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address); 698 gpu_write(gpu, VIVS_FE_COMMAND_CONTROL, 699 VIVS_FE_COMMAND_CONTROL_ENABLE | 700 VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch)); 701 702 if (gpu->sec_mode == ETNA_SEC_KERNEL) { 703 gpu_write(gpu, VIVS_MMUv2_SEC_COMMAND_CONTROL, 704 VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE | 705 VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH(prefetch)); 706 } 707 } 708 709 static void etnaviv_gpu_start_fe_idleloop(struct etnaviv_gpu *gpu, 710 struct etnaviv_iommu_context *context) 711 { 712 u16 prefetch; 713 u32 address; 714 715 WARN_ON(gpu->state != ETNA_GPU_STATE_INITIALIZED); 716 717 /* setup the MMU */ 718 etnaviv_iommu_restore(gpu, context); 719 720 /* Start command processor */ 721 prefetch = etnaviv_buffer_init(gpu); 722 address = etnaviv_cmdbuf_get_va(&gpu->buffer, 723 &gpu->mmu_context->cmdbuf_mapping); 724 725 etnaviv_gpu_start_fe(gpu, address, prefetch); 726 727 gpu->state = ETNA_GPU_STATE_RUNNING; 728 } 729 730 static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu) 731 { 732 /* 733 * Base value for VIVS_PM_PULSE_EATER register on models where it 734 * cannot be read, extracted from vivante kernel driver. 735 */ 736 u32 pulse_eater = 0x01590880; 737 738 if (etnaviv_is_model_rev(gpu, 0x4000, 0x5208) || 739 etnaviv_is_model_rev(gpu, 0x4000, 0x5222)) { 740 pulse_eater |= BIT(23); 741 742 } 743 744 if (etnaviv_is_model_rev(gpu, 0x1000, 0x5039) || 745 etnaviv_is_model_rev(gpu, 0x1000, 0x5040)) { 746 pulse_eater &= ~BIT(16); 747 pulse_eater |= BIT(17); 748 } 749 750 if ((gpu->identity.revision > 0x5420) && 751 (gpu->identity.features & chipFeatures_PIPE_3D)) 752 { 753 /* Performance fix: disable internal DFS */ 754 pulse_eater = gpu_read_power(gpu, VIVS_PM_PULSE_EATER); 755 pulse_eater |= BIT(18); 756 } 757 758 gpu_write_power(gpu, VIVS_PM_PULSE_EATER, pulse_eater); 759 } 760 761 static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu) 762 { 763 WARN_ON(!(gpu->state == ETNA_GPU_STATE_IDENTIFIED || 764 gpu->state == ETNA_GPU_STATE_RESET)); 765 766 if ((etnaviv_is_model_rev(gpu, 0x320, 0x5007) || 767 etnaviv_is_model_rev(gpu, 0x320, 0x5220)) && 768 gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) { 769 u32 mc_memory_debug; 770 771 mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff; 772 773 if (gpu->identity.revision == 0x5007) 774 mc_memory_debug |= 0x0c; 775 else 776 mc_memory_debug |= 0x08; 777 778 gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug); 779 } 780 781 /* enable module-level clock gating */ 782 etnaviv_gpu_enable_mlcg(gpu); 783 784 /* 785 * Update GPU AXI cache atttribute to "cacheable, no allocate". 786 * This is necessary to prevent the iMX6 SoC locking up. 787 */ 788 gpu_write(gpu, VIVS_HI_AXI_CONFIG, 789 VIVS_HI_AXI_CONFIG_AWCACHE(2) | 790 VIVS_HI_AXI_CONFIG_ARCACHE(2)); 791 792 /* GC2000 rev 5108 needs a special bus config */ 793 if (etnaviv_is_model_rev(gpu, 0x2000, 0x5108)) { 794 u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG); 795 bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK | 796 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK); 797 bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) | 798 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0); 799 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config); 800 } 801 802 if (gpu->sec_mode == ETNA_SEC_KERNEL) { 803 u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL); 804 val |= VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS; 805 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val); 806 } 807 808 /* setup the pulse eater */ 809 etnaviv_gpu_setup_pulse_eater(gpu); 810 811 gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U); 812 813 gpu->state = ETNA_GPU_STATE_INITIALIZED; 814 } 815 816 int etnaviv_gpu_init(struct etnaviv_gpu *gpu) 817 { 818 struct etnaviv_drm_private *priv = gpu->drm->dev_private; 819 dma_addr_t cmdbuf_paddr; 820 int ret, i; 821 822 ret = pm_runtime_get_sync(gpu->dev); 823 if (ret < 0) { 824 dev_err(gpu->dev, "Failed to enable GPU power domain\n"); 825 goto pm_put; 826 } 827 828 ret = etnaviv_gpu_reset_deassert(gpu); 829 if (ret) { 830 dev_err(gpu->dev, "GPU reset deassert failed\n"); 831 goto fail; 832 } 833 834 etnaviv_hw_identify(gpu); 835 836 if (gpu->identity.model == 0) { 837 dev_err(gpu->dev, "Unknown GPU model\n"); 838 ret = -ENXIO; 839 goto fail; 840 } 841 842 if (etnaviv_flop_reset_ppu_require(&gpu->identity) && 843 !priv->flop_reset_data_ppu) { 844 ret = etnaviv_flop_reset_ppu_init(priv); 845 if (ret) { 846 dev_err(gpu->dev, 847 "Unable to initialize PPU flop reset data\n"); 848 goto fail; 849 } 850 } 851 852 if (gpu->identity.nn_core_count > 0) 853 dev_warn(gpu->dev, "etnaviv has been instantiated on a NPU, " 854 "for which the UAPI is still experimental\n"); 855 856 /* Exclude VG cores with FE2.0 */ 857 if (gpu->identity.features & chipFeatures_PIPE_VG && 858 gpu->identity.features & chipFeatures_FE20) { 859 dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n"); 860 ret = -ENXIO; 861 goto fail; 862 } 863 864 /* 865 * On cores with security features supported, we claim control over the 866 * security states. 867 */ 868 if ((gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) && 869 (gpu->identity.minor_features10 & chipMinorFeatures10_SECURITY_AHB)) 870 gpu->sec_mode = ETNA_SEC_KERNEL; 871 872 gpu->state = ETNA_GPU_STATE_IDENTIFIED; 873 874 ret = etnaviv_hw_reset(gpu); 875 if (ret) { 876 dev_err(gpu->dev, "GPU reset failed\n"); 877 goto fail; 878 } 879 880 ret = etnaviv_iommu_global_init(gpu); 881 if (ret) 882 goto fail; 883 884 /* Create buffer: */ 885 ret = etnaviv_cmdbuf_init(priv->cmdbuf_suballoc, &gpu->buffer, SZ_4K); 886 if (ret) { 887 dev_err(gpu->dev, "could not create command buffer\n"); 888 goto fail; 889 } 890 891 /* 892 * Set the GPU linear window to cover the cmdbuf region, as the GPU 893 * won't be able to start execution otherwise. The alignment to 128M is 894 * chosen arbitrarily but helps in debugging, as the MMU offset 895 * calculations are much more straight forward this way. 896 * 897 * On MC1.0 cores the linear window offset is ignored by the TS engine, 898 * leading to inconsistent memory views. Avoid using the offset on those 899 * cores if possible, otherwise disable the TS feature. MMUv2 doesn't 900 * expose this issue, as all TS accesses are MMU translated, so the 901 * linear window offset won't be used. 902 */ 903 cmdbuf_paddr = ALIGN_DOWN(etnaviv_cmdbuf_get_pa(&gpu->buffer), SZ_128M); 904 905 if (!(gpu->identity.features & chipFeatures_PIPE_3D) || 906 (gpu->identity.minor_features0 & chipMinorFeatures0_MC20) || 907 (gpu->identity.minor_features1 & chipMinorFeatures1_MMU_VERSION)) { 908 if (cmdbuf_paddr >= SZ_2G) 909 priv->mmu_global->memory_base = SZ_2G; 910 else 911 priv->mmu_global->memory_base = cmdbuf_paddr; 912 } else if (cmdbuf_paddr + SZ_128M >= SZ_2G) { 913 dev_info(gpu->dev, 914 "Need to move linear window on MC1.0, disabling TS\n"); 915 gpu->identity.features &= ~chipFeatures_FAST_CLEAR; 916 priv->mmu_global->memory_base = SZ_2G; 917 } 918 919 /* Setup event management */ 920 spin_lock_init(&gpu->event_spinlock); 921 init_completion(&gpu->event_free); 922 bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS); 923 for (i = 0; i < ARRAY_SIZE(gpu->event); i++) 924 complete(&gpu->event_free); 925 926 /* Now program the hardware */ 927 mutex_lock(&gpu->lock); 928 etnaviv_gpu_hw_init(gpu); 929 mutex_unlock(&gpu->lock); 930 931 pm_runtime_mark_last_busy(gpu->dev); 932 pm_runtime_put_autosuspend(gpu->dev); 933 934 return 0; 935 936 fail: 937 pm_runtime_mark_last_busy(gpu->dev); 938 pm_put: 939 pm_runtime_put_autosuspend(gpu->dev); 940 941 return ret; 942 } 943 944 #ifdef CONFIG_DEBUG_FS 945 struct dma_debug { 946 u32 address[2]; 947 u32 state[2]; 948 }; 949 950 static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug) 951 { 952 u32 i; 953 954 debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 955 debug->state[0] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE); 956 957 for (i = 0; i < 500; i++) { 958 debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 959 debug->state[1] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE); 960 961 if (debug->address[0] != debug->address[1]) 962 break; 963 964 if (debug->state[0] != debug->state[1]) 965 break; 966 } 967 } 968 969 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m) 970 { 971 struct dma_debug debug; 972 u32 dma_lo, dma_hi, axi, idle; 973 int ret; 974 975 seq_printf(m, "%s Status:\n", dev_name(gpu->dev)); 976 977 ret = pm_runtime_get_sync(gpu->dev); 978 if (ret < 0) 979 goto pm_put; 980 981 dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW); 982 dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH); 983 axi = gpu_read(gpu, VIVS_HI_AXI_STATUS); 984 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 985 986 verify_dma(gpu, &debug); 987 988 seq_puts(m, "\tidentity\n"); 989 seq_printf(m, "\t model: 0x%x\n", gpu->identity.model); 990 seq_printf(m, "\t revision: 0x%x\n", gpu->identity.revision); 991 seq_printf(m, "\t product_id: 0x%x\n", gpu->identity.product_id); 992 seq_printf(m, "\t customer_id: 0x%x\n", gpu->identity.customer_id); 993 seq_printf(m, "\t eco_id: 0x%x\n", gpu->identity.eco_id); 994 995 seq_puts(m, "\tfeatures\n"); 996 seq_printf(m, "\t major_features: 0x%08x\n", 997 gpu->identity.features); 998 seq_printf(m, "\t minor_features0: 0x%08x\n", 999 gpu->identity.minor_features0); 1000 seq_printf(m, "\t minor_features1: 0x%08x\n", 1001 gpu->identity.minor_features1); 1002 seq_printf(m, "\t minor_features2: 0x%08x\n", 1003 gpu->identity.minor_features2); 1004 seq_printf(m, "\t minor_features3: 0x%08x\n", 1005 gpu->identity.minor_features3); 1006 seq_printf(m, "\t minor_features4: 0x%08x\n", 1007 gpu->identity.minor_features4); 1008 seq_printf(m, "\t minor_features5: 0x%08x\n", 1009 gpu->identity.minor_features5); 1010 seq_printf(m, "\t minor_features6: 0x%08x\n", 1011 gpu->identity.minor_features6); 1012 seq_printf(m, "\t minor_features7: 0x%08x\n", 1013 gpu->identity.minor_features7); 1014 seq_printf(m, "\t minor_features8: 0x%08x\n", 1015 gpu->identity.minor_features8); 1016 seq_printf(m, "\t minor_features9: 0x%08x\n", 1017 gpu->identity.minor_features9); 1018 seq_printf(m, "\t minor_features10: 0x%08x\n", 1019 gpu->identity.minor_features10); 1020 seq_printf(m, "\t minor_features11: 0x%08x\n", 1021 gpu->identity.minor_features11); 1022 1023 seq_puts(m, "\tspecs\n"); 1024 seq_printf(m, "\t stream_count: %d\n", 1025 gpu->identity.stream_count); 1026 seq_printf(m, "\t register_max: %d\n", 1027 gpu->identity.register_max); 1028 seq_printf(m, "\t thread_count: %d\n", 1029 gpu->identity.thread_count); 1030 seq_printf(m, "\t vertex_cache_size: %d\n", 1031 gpu->identity.vertex_cache_size); 1032 seq_printf(m, "\t shader_core_count: %d\n", 1033 gpu->identity.shader_core_count); 1034 seq_printf(m, "\t nn_core_count: %d\n", 1035 gpu->identity.nn_core_count); 1036 seq_printf(m, "\t pixel_pipes: %d\n", 1037 gpu->identity.pixel_pipes); 1038 seq_printf(m, "\t vertex_output_buffer_size: %d\n", 1039 gpu->identity.vertex_output_buffer_size); 1040 seq_printf(m, "\t buffer_size: %d\n", 1041 gpu->identity.buffer_size); 1042 seq_printf(m, "\t instruction_count: %d\n", 1043 gpu->identity.instruction_count); 1044 seq_printf(m, "\t num_constants: %d\n", 1045 gpu->identity.num_constants); 1046 seq_printf(m, "\t varyings_count: %d\n", 1047 gpu->identity.varyings_count); 1048 1049 seq_printf(m, "\taxi: 0x%08x\n", axi); 1050 seq_printf(m, "\tidle: 0x%08x\n", idle); 1051 idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP; 1052 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) 1053 seq_puts(m, "\t FE is not idle\n"); 1054 if ((idle & VIVS_HI_IDLE_STATE_DE) == 0) 1055 seq_puts(m, "\t DE is not idle\n"); 1056 if ((idle & VIVS_HI_IDLE_STATE_PE) == 0) 1057 seq_puts(m, "\t PE is not idle\n"); 1058 if ((idle & VIVS_HI_IDLE_STATE_SH) == 0) 1059 seq_puts(m, "\t SH is not idle\n"); 1060 if ((idle & VIVS_HI_IDLE_STATE_PA) == 0) 1061 seq_puts(m, "\t PA is not idle\n"); 1062 if ((idle & VIVS_HI_IDLE_STATE_SE) == 0) 1063 seq_puts(m, "\t SE is not idle\n"); 1064 if ((idle & VIVS_HI_IDLE_STATE_RA) == 0) 1065 seq_puts(m, "\t RA is not idle\n"); 1066 if ((idle & VIVS_HI_IDLE_STATE_TX) == 0) 1067 seq_puts(m, "\t TX is not idle\n"); 1068 if ((idle & VIVS_HI_IDLE_STATE_VG) == 0) 1069 seq_puts(m, "\t VG is not idle\n"); 1070 if ((idle & VIVS_HI_IDLE_STATE_IM) == 0) 1071 seq_puts(m, "\t IM is not idle\n"); 1072 if ((idle & VIVS_HI_IDLE_STATE_FP) == 0) 1073 seq_puts(m, "\t FP is not idle\n"); 1074 if ((idle & VIVS_HI_IDLE_STATE_TS) == 0) 1075 seq_puts(m, "\t TS is not idle\n"); 1076 if ((idle & VIVS_HI_IDLE_STATE_BL) == 0) 1077 seq_puts(m, "\t BL is not idle\n"); 1078 if ((idle & VIVS_HI_IDLE_STATE_ASYNCFE) == 0) 1079 seq_puts(m, "\t ASYNCFE is not idle\n"); 1080 if ((idle & VIVS_HI_IDLE_STATE_MC) == 0) 1081 seq_puts(m, "\t MC is not idle\n"); 1082 if ((idle & VIVS_HI_IDLE_STATE_PPA) == 0) 1083 seq_puts(m, "\t PPA is not idle\n"); 1084 if ((idle & VIVS_HI_IDLE_STATE_WD) == 0) 1085 seq_puts(m, "\t WD is not idle\n"); 1086 if ((idle & VIVS_HI_IDLE_STATE_NN) == 0) 1087 seq_puts(m, "\t NN is not idle\n"); 1088 if ((idle & VIVS_HI_IDLE_STATE_TP) == 0) 1089 seq_puts(m, "\t TP is not idle\n"); 1090 if (idle & VIVS_HI_IDLE_STATE_AXI_LP) 1091 seq_puts(m, "\t AXI low power mode\n"); 1092 1093 if (gpu->identity.features & chipFeatures_DEBUG_MODE) { 1094 u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0); 1095 u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1); 1096 u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE); 1097 1098 seq_puts(m, "\tMC\n"); 1099 seq_printf(m, "\t read0: 0x%08x\n", read0); 1100 seq_printf(m, "\t read1: 0x%08x\n", read1); 1101 seq_printf(m, "\t write: 0x%08x\n", write); 1102 } 1103 1104 seq_puts(m, "\tDMA "); 1105 1106 if (debug.address[0] == debug.address[1] && 1107 debug.state[0] == debug.state[1]) { 1108 seq_puts(m, "seems to be stuck\n"); 1109 } else if (debug.address[0] == debug.address[1]) { 1110 seq_puts(m, "address is constant\n"); 1111 } else { 1112 seq_puts(m, "is running\n"); 1113 } 1114 1115 seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]); 1116 seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]); 1117 seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]); 1118 seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]); 1119 seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n", 1120 dma_lo, dma_hi); 1121 1122 ret = 0; 1123 1124 pm_runtime_mark_last_busy(gpu->dev); 1125 pm_put: 1126 pm_runtime_put_autosuspend(gpu->dev); 1127 1128 return ret; 1129 } 1130 #endif 1131 1132 /* fence object management */ 1133 struct etnaviv_fence { 1134 struct etnaviv_gpu *gpu; 1135 struct dma_fence base; 1136 }; 1137 1138 static inline struct etnaviv_fence *to_etnaviv_fence(struct dma_fence *fence) 1139 { 1140 return container_of(fence, struct etnaviv_fence, base); 1141 } 1142 1143 static const char *etnaviv_fence_get_driver_name(struct dma_fence *fence) 1144 { 1145 return "etnaviv"; 1146 } 1147 1148 static const char *etnaviv_fence_get_timeline_name(struct dma_fence *fence) 1149 { 1150 struct etnaviv_fence *f = to_etnaviv_fence(fence); 1151 1152 return dev_name(f->gpu->dev); 1153 } 1154 1155 static bool etnaviv_fence_signaled(struct dma_fence *fence) 1156 { 1157 struct etnaviv_fence *f = to_etnaviv_fence(fence); 1158 1159 return (s32)(f->gpu->completed_fence - f->base.seqno) >= 0; 1160 } 1161 1162 static void etnaviv_fence_release(struct dma_fence *fence) 1163 { 1164 struct etnaviv_fence *f = to_etnaviv_fence(fence); 1165 1166 kfree_rcu(f, base.rcu); 1167 } 1168 1169 static const struct dma_fence_ops etnaviv_fence_ops = { 1170 .get_driver_name = etnaviv_fence_get_driver_name, 1171 .get_timeline_name = etnaviv_fence_get_timeline_name, 1172 .signaled = etnaviv_fence_signaled, 1173 .release = etnaviv_fence_release, 1174 }; 1175 1176 static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu) 1177 { 1178 struct etnaviv_fence *f; 1179 1180 /* 1181 * GPU lock must already be held, otherwise fence completion order might 1182 * not match the seqno order assigned here. 1183 */ 1184 lockdep_assert_held(&gpu->lock); 1185 1186 f = kzalloc_obj(*f); 1187 if (!f) 1188 return NULL; 1189 1190 f->gpu = gpu; 1191 1192 dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock, 1193 gpu->fence_context, ++gpu->next_fence); 1194 1195 return &f->base; 1196 } 1197 1198 /* returns true if fence a comes after fence b */ 1199 static inline bool fence_after(u32 a, u32 b) 1200 { 1201 return (s32)(a - b) > 0; 1202 } 1203 1204 /* 1205 * event management: 1206 */ 1207 1208 static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events, 1209 unsigned int *events) 1210 { 1211 unsigned long timeout = msecs_to_jiffies(10 * 10000); 1212 unsigned i, acquired = 0, rpm_count = 0; 1213 int ret; 1214 1215 for (i = 0; i < nr_events; i++) { 1216 unsigned long remaining; 1217 1218 remaining = wait_for_completion_timeout(&gpu->event_free, timeout); 1219 1220 if (!remaining) { 1221 dev_err(gpu->dev, "wait_for_completion_timeout failed"); 1222 ret = -EBUSY; 1223 goto out; 1224 } 1225 1226 acquired++; 1227 timeout = remaining; 1228 } 1229 1230 spin_lock(&gpu->event_spinlock); 1231 1232 for (i = 0; i < nr_events; i++) { 1233 int event = find_first_zero_bit(gpu->event_bitmap, ETNA_NR_EVENTS); 1234 1235 events[i] = event; 1236 memset(&gpu->event[event], 0, sizeof(struct etnaviv_event)); 1237 set_bit(event, gpu->event_bitmap); 1238 } 1239 1240 spin_unlock(&gpu->event_spinlock); 1241 1242 for (i = 0; i < nr_events; i++) { 1243 ret = pm_runtime_resume_and_get(gpu->dev); 1244 if (ret) 1245 goto out_rpm; 1246 rpm_count++; 1247 } 1248 1249 return 0; 1250 1251 out_rpm: 1252 for (i = 0; i < rpm_count; i++) 1253 pm_runtime_put_autosuspend(gpu->dev); 1254 out: 1255 for (i = 0; i < acquired; i++) 1256 complete(&gpu->event_free); 1257 1258 return ret; 1259 } 1260 1261 static void event_free(struct etnaviv_gpu *gpu, unsigned int event) 1262 { 1263 if (!test_bit(event, gpu->event_bitmap)) { 1264 dev_warn(gpu->dev, "event %u is already marked as free", 1265 event); 1266 } else { 1267 clear_bit(event, gpu->event_bitmap); 1268 complete(&gpu->event_free); 1269 } 1270 1271 pm_runtime_put_autosuspend(gpu->dev); 1272 } 1273 1274 /* 1275 * Cmdstream submission/retirement: 1276 */ 1277 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu, 1278 u32 id, struct drm_etnaviv_timespec *timeout) 1279 { 1280 struct dma_fence *fence; 1281 int ret; 1282 1283 /* 1284 * Look up the fence and take a reference. We might still find a fence 1285 * whose refcount has already dropped to zero. dma_fence_get_rcu 1286 * pretends we didn't find a fence in that case. 1287 */ 1288 rcu_read_lock(); 1289 fence = xa_load(&gpu->user_fences, id); 1290 if (fence) 1291 fence = dma_fence_get_rcu(fence); 1292 rcu_read_unlock(); 1293 1294 if (!fence) 1295 return 0; 1296 1297 if (!timeout) { 1298 /* No timeout was requested: just test for completion */ 1299 ret = dma_fence_is_signaled(fence) ? 0 : -EBUSY; 1300 } else { 1301 unsigned long remaining = etnaviv_timeout_to_jiffies(timeout); 1302 1303 ret = dma_fence_wait_timeout(fence, true, remaining); 1304 if (ret == 0) 1305 ret = -ETIMEDOUT; 1306 else if (ret != -ERESTARTSYS) 1307 ret = 0; 1308 1309 } 1310 1311 dma_fence_put(fence); 1312 return ret; 1313 } 1314 1315 /* 1316 * Wait for an object to become inactive. This, on it's own, is not race 1317 * free: the object is moved by the scheduler off the active list, and 1318 * then the iova is put. Moreover, the object could be re-submitted just 1319 * after we notice that it's become inactive. 1320 * 1321 * Although the retirement happens under the gpu lock, we don't want to hold 1322 * that lock in this function while waiting. 1323 */ 1324 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu, 1325 struct etnaviv_gem_object *etnaviv_obj, 1326 struct drm_etnaviv_timespec *timeout) 1327 { 1328 unsigned long remaining; 1329 long ret; 1330 1331 if (!timeout) 1332 return !is_active(etnaviv_obj) ? 0 : -EBUSY; 1333 1334 remaining = etnaviv_timeout_to_jiffies(timeout); 1335 1336 ret = wait_event_interruptible_timeout(gpu->fence_event, 1337 !is_active(etnaviv_obj), 1338 remaining); 1339 if (ret > 0) 1340 return 0; 1341 else if (ret == -ERESTARTSYS) 1342 return -ERESTARTSYS; 1343 else 1344 return -ETIMEDOUT; 1345 } 1346 1347 static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu, 1348 struct etnaviv_event *event, unsigned int flags) 1349 { 1350 const struct etnaviv_gem_submit *submit = event->submit; 1351 unsigned int i; 1352 1353 for (i = 0; i < submit->nr_pmrs; i++) { 1354 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i; 1355 1356 if (pmr->flags == flags) 1357 etnaviv_perfmon_process(gpu, pmr, submit->exec_state); 1358 } 1359 } 1360 1361 static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu, 1362 struct etnaviv_event *event) 1363 { 1364 u32 val; 1365 1366 mutex_lock(&gpu->lock); 1367 1368 /* disable clock gating */ 1369 val = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS); 1370 val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; 1371 gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, val); 1372 1373 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE); 1374 1375 mutex_unlock(&gpu->lock); 1376 } 1377 1378 static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu, 1379 struct etnaviv_event *event) 1380 { 1381 const struct etnaviv_gem_submit *submit = event->submit; 1382 unsigned int i; 1383 u32 val; 1384 1385 mutex_lock(&gpu->lock); 1386 1387 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST); 1388 1389 /* enable clock gating */ 1390 val = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS); 1391 val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; 1392 gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, val); 1393 1394 mutex_unlock(&gpu->lock); 1395 1396 for (i = 0; i < submit->nr_pmrs; i++) { 1397 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i; 1398 1399 *pmr->bo_vma = pmr->sequence; 1400 } 1401 } 1402 1403 1404 /* add bo's to gpu's ring, and kick gpu: */ 1405 struct dma_fence *etnaviv_gpu_submit(struct etnaviv_gem_submit *submit) 1406 { 1407 struct etnaviv_gpu *gpu = submit->gpu; 1408 struct dma_fence *gpu_fence; 1409 unsigned int i, nr_events = 1, event[3]; 1410 int ret; 1411 1412 /* 1413 * if there are performance monitor requests we need to have 1414 * - a sync point to re-configure gpu and process ETNA_PM_PROCESS_PRE 1415 * requests. 1416 * - a sync point to re-configure gpu, process ETNA_PM_PROCESS_POST requests 1417 * and update the sequence number for userspace. 1418 */ 1419 if (submit->nr_pmrs) 1420 nr_events = 3; 1421 1422 ret = event_alloc(gpu, nr_events, event); 1423 if (ret) { 1424 DRM_ERROR("no free events\n"); 1425 pm_runtime_put_noidle(gpu->dev); 1426 return NULL; 1427 } 1428 1429 mutex_lock(&gpu->lock); 1430 1431 gpu_fence = etnaviv_gpu_fence_alloc(gpu); 1432 if (!gpu_fence) { 1433 for (i = 0; i < nr_events; i++) 1434 event_free(gpu, event[i]); 1435 1436 goto out_unlock; 1437 } 1438 1439 if (gpu->state == ETNA_GPU_STATE_INITIALIZED) 1440 etnaviv_gpu_start_fe_idleloop(gpu, submit->mmu_context); 1441 1442 if (submit->prev_mmu_context) 1443 etnaviv_iommu_context_put(submit->prev_mmu_context); 1444 submit->prev_mmu_context = etnaviv_iommu_context_get(gpu->mmu_context); 1445 1446 if (submit->nr_pmrs) { 1447 gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre; 1448 kref_get(&submit->refcount); 1449 gpu->event[event[1]].submit = submit; 1450 etnaviv_sync_point_queue(gpu, event[1]); 1451 } 1452 1453 gpu->event[event[0]].fence = gpu_fence; 1454 submit->cmdbuf.user_size = submit->cmdbuf.size - 8; 1455 etnaviv_buffer_queue(gpu, submit->exec_state, submit->mmu_context, 1456 event[0], &submit->cmdbuf); 1457 1458 if (submit->nr_pmrs) { 1459 gpu->event[event[2]].sync_point = &sync_point_perfmon_sample_post; 1460 kref_get(&submit->refcount); 1461 gpu->event[event[2]].submit = submit; 1462 etnaviv_sync_point_queue(gpu, event[2]); 1463 } 1464 1465 out_unlock: 1466 mutex_unlock(&gpu->lock); 1467 1468 return gpu_fence; 1469 } 1470 1471 static void sync_point_worker(struct work_struct *work) 1472 { 1473 struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu, 1474 sync_point_work); 1475 struct etnaviv_event *event = &gpu->event[gpu->sync_point_event]; 1476 u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 1477 1478 event->sync_point(gpu, event); 1479 etnaviv_submit_put(event->submit); 1480 event_free(gpu, gpu->sync_point_event); 1481 1482 /* restart FE last to avoid GPU and IRQ racing against this worker */ 1483 etnaviv_gpu_start_fe(gpu, addr + 2, 2); 1484 } 1485 1486 void etnaviv_gpu_recover_hang(struct etnaviv_gem_submit *submit) 1487 { 1488 struct etnaviv_gpu *gpu = submit->gpu; 1489 char *comm = NULL, *cmd = NULL; 1490 struct task_struct *task; 1491 unsigned int i; 1492 1493 dev_err(gpu->dev, "recover hung GPU!\n"); 1494 1495 task = get_pid_task(submit->pid, PIDTYPE_PID); 1496 if (task) { 1497 comm = kstrdup(task->comm, GFP_KERNEL); 1498 cmd = kstrdup_quotable_cmdline(task, GFP_KERNEL); 1499 put_task_struct(task); 1500 } 1501 1502 if (comm && cmd) 1503 dev_err(gpu->dev, "offending task: %s (%s)\n", comm, cmd); 1504 1505 kfree(cmd); 1506 kfree(comm); 1507 1508 if (pm_runtime_get_sync(gpu->dev) < 0) 1509 goto pm_put; 1510 1511 mutex_lock(&gpu->lock); 1512 1513 etnaviv_hw_reset(gpu); 1514 1515 /* complete all events, the GPU won't do it after the reset */ 1516 spin_lock(&gpu->event_spinlock); 1517 for_each_set_bit(i, gpu->event_bitmap, ETNA_NR_EVENTS) 1518 event_free(gpu, i); 1519 spin_unlock(&gpu->event_spinlock); 1520 1521 etnaviv_gpu_hw_init(gpu); 1522 1523 mutex_unlock(&gpu->lock); 1524 pm_runtime_mark_last_busy(gpu->dev); 1525 pm_put: 1526 pm_runtime_put_autosuspend(gpu->dev); 1527 } 1528 1529 static void dump_mmu_fault(struct etnaviv_gpu *gpu) 1530 { 1531 static const char *fault_reasons[] = { 1532 "slave not present", 1533 "page not present", 1534 "write violation", 1535 "out of bounds", 1536 "read security violation", 1537 "write security violation", 1538 }; 1539 1540 u32 status_reg, status; 1541 int i; 1542 1543 if (gpu->sec_mode == ETNA_SEC_NONE) 1544 status_reg = VIVS_MMUv2_STATUS; 1545 else 1546 status_reg = VIVS_MMUv2_SEC_STATUS; 1547 1548 status = gpu_read(gpu, status_reg); 1549 dev_err_ratelimited(gpu->dev, "MMU fault status 0x%08x\n", status); 1550 1551 for (i = 0; i < 4; i++) { 1552 const char *reason = "unknown"; 1553 u32 address_reg; 1554 u32 mmu_status; 1555 1556 mmu_status = (status >> (i * 4)) & VIVS_MMUv2_STATUS_EXCEPTION0__MASK; 1557 if (!mmu_status) 1558 continue; 1559 1560 if ((mmu_status - 1) < ARRAY_SIZE(fault_reasons)) 1561 reason = fault_reasons[mmu_status - 1]; 1562 1563 if (gpu->sec_mode == ETNA_SEC_NONE) 1564 address_reg = VIVS_MMUv2_EXCEPTION_ADDR(i); 1565 else 1566 address_reg = VIVS_MMUv2_SEC_EXCEPTION_ADDR; 1567 1568 dev_err_ratelimited(gpu->dev, 1569 "MMU %d fault (%s) addr 0x%08x\n", 1570 i, reason, gpu_read(gpu, address_reg)); 1571 } 1572 } 1573 1574 static irqreturn_t irq_handler(int irq, void *data) 1575 { 1576 struct etnaviv_gpu *gpu = data; 1577 irqreturn_t ret = IRQ_NONE; 1578 1579 u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE); 1580 1581 if (intr != 0) { 1582 ktime_t now = ktime_get(); 1583 int event; 1584 1585 pm_runtime_mark_last_busy(gpu->dev); 1586 1587 dev_dbg(gpu->dev, "intr 0x%08x\n", intr); 1588 1589 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) { 1590 dev_err(gpu->dev, "AXI bus error\n"); 1591 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR; 1592 } 1593 1594 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) { 1595 dump_mmu_fault(gpu); 1596 gpu->state = ETNA_GPU_STATE_FAULT; 1597 drm_sched_fault(&gpu->sched); 1598 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION; 1599 } 1600 1601 while ((event = ffs(intr)) != 0) { 1602 struct dma_fence *fence; 1603 1604 event -= 1; 1605 1606 intr &= ~(1 << event); 1607 1608 dev_dbg(gpu->dev, "event %u\n", event); 1609 1610 if (gpu->event[event].sync_point) { 1611 gpu->sync_point_event = event; 1612 queue_work(gpu->wq, &gpu->sync_point_work); 1613 } 1614 1615 fence = gpu->event[event].fence; 1616 if (!fence) 1617 continue; 1618 1619 gpu->event[event].fence = NULL; 1620 1621 /* 1622 * Events can be processed out of order. Eg, 1623 * - allocate and queue event 0 1624 * - allocate event 1 1625 * - event 0 completes, we process it 1626 * - allocate and queue event 0 1627 * - event 1 and event 0 complete 1628 * we can end up processing event 0 first, then 1. 1629 */ 1630 if (fence_after(fence->seqno, gpu->completed_fence)) 1631 gpu->completed_fence = fence->seqno; 1632 dma_fence_signal_timestamp(fence, now); 1633 1634 event_free(gpu, event); 1635 } 1636 1637 ret = IRQ_HANDLED; 1638 } 1639 1640 return ret; 1641 } 1642 1643 static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu) 1644 { 1645 int ret; 1646 1647 ret = clk_prepare_enable(gpu->clk_reg); 1648 if (ret) 1649 return ret; 1650 1651 ret = clk_prepare_enable(gpu->clk_bus); 1652 if (ret) 1653 goto disable_clk_reg; 1654 1655 ret = clk_prepare_enable(gpu->clk_core); 1656 if (ret) 1657 goto disable_clk_bus; 1658 1659 ret = clk_prepare_enable(gpu->clk_shader); 1660 if (ret) 1661 goto disable_clk_core; 1662 1663 return 0; 1664 1665 disable_clk_core: 1666 clk_disable_unprepare(gpu->clk_core); 1667 disable_clk_bus: 1668 clk_disable_unprepare(gpu->clk_bus); 1669 disable_clk_reg: 1670 clk_disable_unprepare(gpu->clk_reg); 1671 1672 return ret; 1673 } 1674 1675 static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu) 1676 { 1677 clk_disable_unprepare(gpu->clk_shader); 1678 clk_disable_unprepare(gpu->clk_core); 1679 clk_disable_unprepare(gpu->clk_bus); 1680 clk_disable_unprepare(gpu->clk_reg); 1681 1682 return 0; 1683 } 1684 1685 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms) 1686 { 1687 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms); 1688 1689 do { 1690 u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 1691 1692 if ((idle & gpu->idle_mask) == gpu->idle_mask) 1693 return 0; 1694 1695 if (time_is_before_jiffies(timeout)) { 1696 dev_warn(gpu->dev, 1697 "timed out waiting for idle: idle=0x%x\n", 1698 idle); 1699 return -ETIMEDOUT; 1700 } 1701 1702 udelay(5); 1703 } while (1); 1704 } 1705 1706 static void etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu) 1707 { 1708 if (gpu->state == ETNA_GPU_STATE_RUNNING) { 1709 /* Replace the last WAIT with END */ 1710 mutex_lock(&gpu->lock); 1711 etnaviv_buffer_end(gpu); 1712 mutex_unlock(&gpu->lock); 1713 1714 /* 1715 * We know that only the FE is busy here, this should 1716 * happen quickly (as the WAIT is only 200 cycles). If 1717 * we fail, just warn and continue. 1718 */ 1719 etnaviv_gpu_wait_idle(gpu, 100); 1720 1721 gpu->state = ETNA_GPU_STATE_INITIALIZED; 1722 } 1723 1724 gpu->exec_state = -1; 1725 } 1726 1727 static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu) 1728 { 1729 int ret; 1730 1731 ret = mutex_lock_killable(&gpu->lock); 1732 if (ret) 1733 return ret; 1734 1735 etnaviv_gpu_update_clock(gpu); 1736 etnaviv_gpu_hw_init(gpu); 1737 1738 mutex_unlock(&gpu->lock); 1739 1740 return 0; 1741 } 1742 1743 static int 1744 etnaviv_gpu_cooling_get_max_state(struct thermal_cooling_device *cdev, 1745 unsigned long *state) 1746 { 1747 *state = 6; 1748 1749 return 0; 1750 } 1751 1752 static int 1753 etnaviv_gpu_cooling_get_cur_state(struct thermal_cooling_device *cdev, 1754 unsigned long *state) 1755 { 1756 struct etnaviv_gpu *gpu = cdev->devdata; 1757 1758 *state = gpu->freq_scale; 1759 1760 return 0; 1761 } 1762 1763 static int 1764 etnaviv_gpu_cooling_set_cur_state(struct thermal_cooling_device *cdev, 1765 unsigned long state) 1766 { 1767 struct etnaviv_gpu *gpu = cdev->devdata; 1768 1769 mutex_lock(&gpu->lock); 1770 gpu->freq_scale = state; 1771 if (!pm_runtime_suspended(gpu->dev)) 1772 etnaviv_gpu_update_clock(gpu); 1773 mutex_unlock(&gpu->lock); 1774 1775 return 0; 1776 } 1777 1778 static const struct thermal_cooling_device_ops cooling_ops = { 1779 .get_max_state = etnaviv_gpu_cooling_get_max_state, 1780 .get_cur_state = etnaviv_gpu_cooling_get_cur_state, 1781 .set_cur_state = etnaviv_gpu_cooling_set_cur_state, 1782 }; 1783 1784 static int etnaviv_gpu_bind(struct device *dev, struct device *master, 1785 void *data) 1786 { 1787 struct drm_device *drm = data; 1788 struct etnaviv_drm_private *priv = drm->dev_private; 1789 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1790 int ret; 1791 1792 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) { 1793 gpu->cooling = thermal_of_cooling_device_register(dev->of_node, 0, 1794 dev_name(dev), 1795 gpu, &cooling_ops); 1796 if (IS_ERR(gpu->cooling)) 1797 return PTR_ERR(gpu->cooling); 1798 } 1799 1800 gpu->wq = alloc_ordered_workqueue(dev_name(dev), 0); 1801 if (!gpu->wq) { 1802 ret = -ENOMEM; 1803 goto out_thermal; 1804 } 1805 1806 ret = etnaviv_sched_init(gpu); 1807 if (ret) 1808 goto out_workqueue; 1809 1810 if (!IS_ENABLED(CONFIG_PM)) { 1811 ret = etnaviv_gpu_clk_enable(gpu); 1812 if (ret < 0) 1813 goto out_sched; 1814 } 1815 1816 gpu->drm = drm; 1817 gpu->fence_context = dma_fence_context_alloc(1); 1818 xa_init_flags(&gpu->user_fences, XA_FLAGS_ALLOC); 1819 spin_lock_init(&gpu->fence_spinlock); 1820 1821 INIT_WORK(&gpu->sync_point_work, sync_point_worker); 1822 init_waitqueue_head(&gpu->fence_event); 1823 1824 priv->gpu[priv->num_gpus++] = gpu; 1825 1826 return 0; 1827 1828 out_sched: 1829 etnaviv_sched_fini(gpu); 1830 1831 out_workqueue: 1832 destroy_workqueue(gpu->wq); 1833 1834 out_thermal: 1835 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) 1836 thermal_cooling_device_unregister(gpu->cooling); 1837 1838 return ret; 1839 } 1840 1841 static void etnaviv_gpu_unbind(struct device *dev, struct device *master, 1842 void *data) 1843 { 1844 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1845 1846 DBG("%s", dev_name(gpu->dev)); 1847 1848 destroy_workqueue(gpu->wq); 1849 1850 etnaviv_sched_fini(gpu); 1851 1852 if (IS_ENABLED(CONFIG_PM)) { 1853 pm_runtime_get_sync(gpu->dev); 1854 pm_runtime_put_sync_suspend(gpu->dev); 1855 } else { 1856 etnaviv_gpu_hw_suspend(gpu); 1857 etnaviv_gpu_clk_disable(gpu); 1858 } 1859 1860 if (gpu->mmu_context) 1861 etnaviv_iommu_context_put(gpu->mmu_context); 1862 1863 etnaviv_cmdbuf_free(&gpu->buffer); 1864 etnaviv_iommu_global_fini(gpu); 1865 1866 gpu->drm = NULL; 1867 xa_destroy(&gpu->user_fences); 1868 1869 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) 1870 thermal_cooling_device_unregister(gpu->cooling); 1871 gpu->cooling = NULL; 1872 } 1873 1874 static const struct component_ops gpu_ops = { 1875 .bind = etnaviv_gpu_bind, 1876 .unbind = etnaviv_gpu_unbind, 1877 }; 1878 1879 static const struct of_device_id etnaviv_gpu_match[] = { 1880 { 1881 .compatible = "vivante,gc" 1882 }, 1883 { /* sentinel */ } 1884 }; 1885 MODULE_DEVICE_TABLE(of, etnaviv_gpu_match); 1886 1887 static int etnaviv_gpu_platform_probe(struct platform_device *pdev) 1888 { 1889 struct device *dev = &pdev->dev; 1890 struct etnaviv_gpu *gpu; 1891 int err; 1892 1893 gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL); 1894 if (!gpu) 1895 return -ENOMEM; 1896 1897 gpu->dev = dev; 1898 mutex_init(&gpu->lock); 1899 mutex_init(&gpu->sched_lock); 1900 1901 /* Map registers: */ 1902 gpu->mmio = devm_platform_ioremap_resource(pdev, 0); 1903 if (IS_ERR(gpu->mmio)) 1904 return PTR_ERR(gpu->mmio); 1905 1906 1907 /* Get Reset: */ 1908 gpu->rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); 1909 if (IS_ERR(gpu->rst)) 1910 return dev_err_probe(dev, PTR_ERR(gpu->rst), 1911 "failed to get reset\n"); 1912 1913 err = reset_control_assert(gpu->rst); 1914 if (err) 1915 return dev_err_probe(dev, err, "failed to assert reset\n"); 1916 1917 /* Get Interrupt: */ 1918 gpu->irq = platform_get_irq(pdev, 0); 1919 if (gpu->irq < 0) 1920 return gpu->irq; 1921 1922 err = devm_request_irq(dev, gpu->irq, irq_handler, 0, 1923 dev_name(dev), gpu); 1924 if (err) { 1925 dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err); 1926 return err; 1927 } 1928 1929 /* Get Clocks: */ 1930 gpu->clk_reg = devm_clk_get_optional(&pdev->dev, "reg"); 1931 DBG("clk_reg: %p", gpu->clk_reg); 1932 if (IS_ERR(gpu->clk_reg)) 1933 return PTR_ERR(gpu->clk_reg); 1934 1935 gpu->clk_bus = devm_clk_get_optional(&pdev->dev, "bus"); 1936 DBG("clk_bus: %p", gpu->clk_bus); 1937 if (IS_ERR(gpu->clk_bus)) 1938 return PTR_ERR(gpu->clk_bus); 1939 1940 gpu->clk_core = devm_clk_get(&pdev->dev, "core"); 1941 DBG("clk_core: %p", gpu->clk_core); 1942 if (IS_ERR(gpu->clk_core)) 1943 return PTR_ERR(gpu->clk_core); 1944 gpu->base_rate_core = clk_get_rate(gpu->clk_core); 1945 1946 gpu->clk_shader = devm_clk_get_optional(&pdev->dev, "shader"); 1947 DBG("clk_shader: %p", gpu->clk_shader); 1948 if (IS_ERR(gpu->clk_shader)) 1949 return PTR_ERR(gpu->clk_shader); 1950 gpu->base_rate_shader = clk_get_rate(gpu->clk_shader); 1951 1952 /* TODO: figure out max mapped size */ 1953 dev_set_drvdata(dev, gpu); 1954 1955 /* 1956 * We treat the device as initially suspended. The runtime PM 1957 * autosuspend delay is rather arbitary: no measurements have 1958 * yet been performed to determine an appropriate value. 1959 */ 1960 pm_runtime_use_autosuspend(dev); 1961 pm_runtime_set_autosuspend_delay(dev, 200); 1962 pm_runtime_enable(dev); 1963 1964 err = component_add(dev, &gpu_ops); 1965 if (err < 0) { 1966 dev_err(dev, "failed to register component: %d\n", err); 1967 return err; 1968 } 1969 1970 return 0; 1971 } 1972 1973 static void etnaviv_gpu_platform_remove(struct platform_device *pdev) 1974 { 1975 struct etnaviv_gpu *gpu = dev_get_drvdata(&pdev->dev); 1976 1977 component_del(&pdev->dev, &gpu_ops); 1978 pm_runtime_disable(&pdev->dev); 1979 1980 mutex_destroy(&gpu->lock); 1981 mutex_destroy(&gpu->sched_lock); 1982 } 1983 1984 static int etnaviv_gpu_rpm_suspend(struct device *dev) 1985 { 1986 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1987 u32 idle, mask; 1988 1989 /* If there are any jobs in the HW queue, we're not idle */ 1990 if (atomic_read(&gpu->sched.credit_count)) 1991 return -EBUSY; 1992 1993 /* Check whether the hardware (except FE and MC) is idle */ 1994 mask = gpu->idle_mask & ~(VIVS_HI_IDLE_STATE_FE | 1995 VIVS_HI_IDLE_STATE_MC); 1996 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask; 1997 if (idle != mask) { 1998 dev_warn_ratelimited(dev, "GPU not yet idle, mask: 0x%08x\n", 1999 idle); 2000 return -EBUSY; 2001 } 2002 2003 etnaviv_gpu_hw_suspend(gpu); 2004 2005 gpu->state = ETNA_GPU_STATE_IDENTIFIED; 2006 2007 return etnaviv_gpu_clk_disable(gpu); 2008 } 2009 2010 static int etnaviv_gpu_rpm_resume(struct device *dev) 2011 { 2012 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 2013 int ret; 2014 2015 ret = etnaviv_gpu_clk_enable(gpu); 2016 if (ret) 2017 return ret; 2018 2019 /* Re-initialise the basic hardware state */ 2020 if (gpu->state == ETNA_GPU_STATE_IDENTIFIED) { 2021 ret = etnaviv_gpu_hw_resume(gpu); 2022 if (ret) { 2023 etnaviv_gpu_clk_disable(gpu); 2024 return ret; 2025 } 2026 } 2027 2028 return 0; 2029 } 2030 2031 static const struct dev_pm_ops etnaviv_gpu_pm_ops = { 2032 RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume, NULL) 2033 }; 2034 2035 struct platform_driver etnaviv_gpu_driver = { 2036 .driver = { 2037 .name = "etnaviv-gpu", 2038 .pm = pm_ptr(&etnaviv_gpu_pm_ops), 2039 .of_match_table = etnaviv_gpu_match, 2040 }, 2041 .probe = etnaviv_gpu_platform_probe, 2042 .remove = etnaviv_gpu_platform_remove, 2043 .id_table = gpu_ids, 2044 }; 2045