1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2015-2018 Etnaviv Project 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/component.h> 8 #include <linux/delay.h> 9 #include <linux/dma-fence.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/regulator/consumer.h> 15 #include <linux/reset.h> 16 #include <linux/thermal.h> 17 18 #include <drm/drm_print.h> 19 20 #include "etnaviv_cmdbuf.h" 21 #include "etnaviv_dump.h" 22 #include "etnaviv_flop_reset.h" 23 #include "etnaviv_gpu.h" 24 #include "etnaviv_gem.h" 25 #include "etnaviv_mmu.h" 26 #include "etnaviv_perfmon.h" 27 #include "etnaviv_sched.h" 28 #include "common.xml.h" 29 #include "state.xml.h" 30 #include "state_hi.xml.h" 31 #include "cmdstream.xml.h" 32 33 static const struct platform_device_id gpu_ids[] = { 34 { .name = "etnaviv-gpu,2d" }, 35 { }, 36 }; 37 38 /* 39 * Driver functions: 40 */ 41 42 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value) 43 { 44 struct etnaviv_drm_private *priv = gpu->drm->dev_private; 45 46 switch (param) { 47 case ETNAVIV_PARAM_GPU_MODEL: 48 *value = gpu->identity.model; 49 break; 50 51 case ETNAVIV_PARAM_GPU_REVISION: 52 *value = gpu->identity.revision; 53 break; 54 55 case ETNAVIV_PARAM_GPU_FEATURES_0: 56 *value = gpu->identity.features; 57 break; 58 59 case ETNAVIV_PARAM_GPU_FEATURES_1: 60 *value = gpu->identity.minor_features0; 61 break; 62 63 case ETNAVIV_PARAM_GPU_FEATURES_2: 64 *value = gpu->identity.minor_features1; 65 break; 66 67 case ETNAVIV_PARAM_GPU_FEATURES_3: 68 *value = gpu->identity.minor_features2; 69 break; 70 71 case ETNAVIV_PARAM_GPU_FEATURES_4: 72 *value = gpu->identity.minor_features3; 73 break; 74 75 case ETNAVIV_PARAM_GPU_FEATURES_5: 76 *value = gpu->identity.minor_features4; 77 break; 78 79 case ETNAVIV_PARAM_GPU_FEATURES_6: 80 *value = gpu->identity.minor_features5; 81 break; 82 83 case ETNAVIV_PARAM_GPU_FEATURES_7: 84 *value = gpu->identity.minor_features6; 85 break; 86 87 case ETNAVIV_PARAM_GPU_FEATURES_8: 88 *value = gpu->identity.minor_features7; 89 break; 90 91 case ETNAVIV_PARAM_GPU_FEATURES_9: 92 *value = gpu->identity.minor_features8; 93 break; 94 95 case ETNAVIV_PARAM_GPU_FEATURES_10: 96 *value = gpu->identity.minor_features9; 97 break; 98 99 case ETNAVIV_PARAM_GPU_FEATURES_11: 100 *value = gpu->identity.minor_features10; 101 break; 102 103 case ETNAVIV_PARAM_GPU_FEATURES_12: 104 *value = gpu->identity.minor_features11; 105 break; 106 107 case ETNAVIV_PARAM_GPU_STREAM_COUNT: 108 *value = gpu->identity.stream_count; 109 break; 110 111 case ETNAVIV_PARAM_GPU_REGISTER_MAX: 112 *value = gpu->identity.register_max; 113 break; 114 115 case ETNAVIV_PARAM_GPU_THREAD_COUNT: 116 *value = gpu->identity.thread_count; 117 break; 118 119 case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE: 120 *value = gpu->identity.vertex_cache_size; 121 break; 122 123 case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT: 124 *value = gpu->identity.shader_core_count; 125 break; 126 127 case ETNAVIV_PARAM_GPU_PIXEL_PIPES: 128 *value = gpu->identity.pixel_pipes; 129 break; 130 131 case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE: 132 *value = gpu->identity.vertex_output_buffer_size; 133 break; 134 135 case ETNAVIV_PARAM_GPU_BUFFER_SIZE: 136 *value = gpu->identity.buffer_size; 137 break; 138 139 case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT: 140 *value = gpu->identity.instruction_count; 141 break; 142 143 case ETNAVIV_PARAM_GPU_NUM_CONSTANTS: 144 *value = gpu->identity.num_constants; 145 break; 146 147 case ETNAVIV_PARAM_GPU_NUM_VARYINGS: 148 *value = gpu->identity.varyings_count; 149 break; 150 151 case ETNAVIV_PARAM_SOFTPIN_START_ADDR: 152 if (priv->mmu_global->version == ETNAVIV_IOMMU_V2) 153 *value = ETNAVIV_SOFTPIN_START_ADDRESS; 154 else 155 *value = ~0ULL; 156 break; 157 158 case ETNAVIV_PARAM_GPU_PRODUCT_ID: 159 *value = gpu->identity.product_id; 160 break; 161 162 case ETNAVIV_PARAM_GPU_CUSTOMER_ID: 163 *value = gpu->identity.customer_id; 164 break; 165 166 case ETNAVIV_PARAM_GPU_ECO_ID: 167 *value = gpu->identity.eco_id; 168 break; 169 170 default: 171 DBG("%s: invalid param: %u", dev_name(gpu->dev), param); 172 return -EINVAL; 173 } 174 175 return 0; 176 } 177 178 static int etnaviv_gpu_reset_deassert(struct etnaviv_gpu *gpu) 179 { 180 int ret; 181 182 /* 183 * 32 core clock cycles (slowest clock) required before deassertion 184 * 1 microsecond might match all implementations without computation 185 */ 186 usleep_range(1, 2); 187 188 ret = reset_control_deassert(gpu->rst); 189 if (ret) 190 return ret; 191 192 /* 193 * 128 core clock cycles (slowest clock) required before any activity on AHB 194 * 1 microsecond might match all implementations without computation 195 */ 196 usleep_range(1, 2); 197 198 return 0; 199 } 200 201 static inline bool etnaviv_is_model_rev(struct etnaviv_gpu *gpu, u32 model, u32 revision) 202 { 203 return gpu->identity.model == model && 204 gpu->identity.revision == revision; 205 } 206 207 #define etnaviv_field(val, field) \ 208 (((val) & field##__MASK) >> field##__SHIFT) 209 210 static void etnaviv_hw_specs(struct etnaviv_gpu *gpu) 211 { 212 if (gpu->identity.minor_features0 & 213 chipMinorFeatures0_MORE_MINOR_FEATURES) { 214 u32 specs[4]; 215 unsigned int streams; 216 217 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS); 218 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2); 219 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3); 220 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4); 221 222 gpu->identity.stream_count = etnaviv_field(specs[0], 223 VIVS_HI_CHIP_SPECS_STREAM_COUNT); 224 gpu->identity.register_max = etnaviv_field(specs[0], 225 VIVS_HI_CHIP_SPECS_REGISTER_MAX); 226 gpu->identity.thread_count = etnaviv_field(specs[0], 227 VIVS_HI_CHIP_SPECS_THREAD_COUNT); 228 gpu->identity.vertex_cache_size = etnaviv_field(specs[0], 229 VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE); 230 gpu->identity.shader_core_count = etnaviv_field(specs[0], 231 VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT); 232 gpu->identity.pixel_pipes = etnaviv_field(specs[0], 233 VIVS_HI_CHIP_SPECS_PIXEL_PIPES); 234 gpu->identity.vertex_output_buffer_size = 235 etnaviv_field(specs[0], 236 VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE); 237 238 gpu->identity.buffer_size = etnaviv_field(specs[1], 239 VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE); 240 gpu->identity.instruction_count = etnaviv_field(specs[1], 241 VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT); 242 gpu->identity.num_constants = etnaviv_field(specs[1], 243 VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS); 244 245 gpu->identity.varyings_count = etnaviv_field(specs[2], 246 VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT); 247 248 /* This overrides the value from older register if non-zero */ 249 streams = etnaviv_field(specs[3], 250 VIVS_HI_CHIP_SPECS_4_STREAM_COUNT); 251 if (streams) 252 gpu->identity.stream_count = streams; 253 } 254 255 /* Fill in the stream count if not specified */ 256 if (gpu->identity.stream_count == 0) { 257 if (gpu->identity.model >= 0x1000) 258 gpu->identity.stream_count = 4; 259 else 260 gpu->identity.stream_count = 1; 261 } 262 263 /* Convert the register max value */ 264 if (gpu->identity.register_max) 265 gpu->identity.register_max = 1 << gpu->identity.register_max; 266 else if (gpu->identity.model == chipModel_GC400) 267 gpu->identity.register_max = 32; 268 else 269 gpu->identity.register_max = 64; 270 271 /* Convert thread count */ 272 if (gpu->identity.thread_count) 273 gpu->identity.thread_count = 1 << gpu->identity.thread_count; 274 else if (gpu->identity.model == chipModel_GC400) 275 gpu->identity.thread_count = 64; 276 else if (gpu->identity.model == chipModel_GC500 || 277 gpu->identity.model == chipModel_GC530) 278 gpu->identity.thread_count = 128; 279 else 280 gpu->identity.thread_count = 256; 281 282 if (gpu->identity.vertex_cache_size == 0) 283 gpu->identity.vertex_cache_size = 8; 284 285 if (gpu->identity.shader_core_count == 0) { 286 if (gpu->identity.model >= 0x1000) 287 gpu->identity.shader_core_count = 2; 288 else 289 gpu->identity.shader_core_count = 1; 290 } 291 292 if (gpu->identity.pixel_pipes == 0) 293 gpu->identity.pixel_pipes = 1; 294 295 /* Convert virtex buffer size */ 296 if (gpu->identity.vertex_output_buffer_size) { 297 gpu->identity.vertex_output_buffer_size = 298 1 << gpu->identity.vertex_output_buffer_size; 299 } else if (gpu->identity.model == chipModel_GC400) { 300 if (gpu->identity.revision < 0x4000) 301 gpu->identity.vertex_output_buffer_size = 512; 302 else if (gpu->identity.revision < 0x4200) 303 gpu->identity.vertex_output_buffer_size = 256; 304 else 305 gpu->identity.vertex_output_buffer_size = 128; 306 } else { 307 gpu->identity.vertex_output_buffer_size = 512; 308 } 309 310 switch (gpu->identity.instruction_count) { 311 case 0: 312 if (etnaviv_is_model_rev(gpu, 0x2000, 0x5108) || 313 gpu->identity.model == chipModel_GC880) 314 gpu->identity.instruction_count = 512; 315 else 316 gpu->identity.instruction_count = 256; 317 break; 318 319 case 1: 320 gpu->identity.instruction_count = 1024; 321 break; 322 323 case 2: 324 gpu->identity.instruction_count = 2048; 325 break; 326 327 default: 328 gpu->identity.instruction_count = 256; 329 break; 330 } 331 332 if (gpu->identity.num_constants == 0) 333 gpu->identity.num_constants = 168; 334 335 if (gpu->identity.varyings_count == 0) { 336 if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0) 337 gpu->identity.varyings_count = 12; 338 else 339 gpu->identity.varyings_count = 8; 340 } 341 342 /* 343 * For some cores, two varyings are consumed for position, so the 344 * maximum varying count needs to be reduced by one. 345 */ 346 if (etnaviv_is_model_rev(gpu, 0x5000, 0x5434) || 347 etnaviv_is_model_rev(gpu, 0x4000, 0x5222) || 348 etnaviv_is_model_rev(gpu, 0x4000, 0x5245) || 349 etnaviv_is_model_rev(gpu, 0x4000, 0x5208) || 350 etnaviv_is_model_rev(gpu, 0x3000, 0x5435) || 351 etnaviv_is_model_rev(gpu, 0x2200, 0x5244) || 352 etnaviv_is_model_rev(gpu, 0x2100, 0x5108) || 353 etnaviv_is_model_rev(gpu, 0x2000, 0x5108) || 354 etnaviv_is_model_rev(gpu, 0x1500, 0x5246) || 355 etnaviv_is_model_rev(gpu, 0x880, 0x5107) || 356 etnaviv_is_model_rev(gpu, 0x880, 0x5106)) 357 gpu->identity.varyings_count -= 1; 358 } 359 360 static void etnaviv_hw_identify(struct etnaviv_gpu *gpu) 361 { 362 u32 chipIdentity; 363 364 chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY); 365 366 /* Special case for older graphic cores. */ 367 if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) { 368 gpu->identity.model = chipModel_GC500; 369 gpu->identity.revision = etnaviv_field(chipIdentity, 370 VIVS_HI_CHIP_IDENTITY_REVISION); 371 } else { 372 u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE); 373 374 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL); 375 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV); 376 gpu->identity.customer_id = gpu_read(gpu, VIVS_HI_CHIP_CUSTOMER_ID); 377 378 /* 379 * Reading these two registers on GC600 rev 0x19 result in a 380 * unhandled fault: external abort on non-linefetch 381 */ 382 if (!etnaviv_is_model_rev(gpu, 0x600, 0x19)) { 383 gpu->identity.product_id = gpu_read(gpu, VIVS_HI_CHIP_PRODUCT_ID); 384 gpu->identity.eco_id = gpu_read(gpu, VIVS_HI_CHIP_ECO_ID); 385 } 386 387 /* 388 * !!!! HACK ALERT !!!! 389 * Because people change device IDs without letting software 390 * know about it - here is the hack to make it all look the 391 * same. Only for GC400 family. 392 */ 393 if ((gpu->identity.model & 0xff00) == 0x0400 && 394 gpu->identity.model != chipModel_GC420) { 395 gpu->identity.model = gpu->identity.model & 0x0400; 396 } 397 398 /* Another special case */ 399 if (etnaviv_is_model_rev(gpu, 0x300, 0x2201)) { 400 u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME); 401 402 if (chipDate == 0x20080814 && chipTime == 0x12051100) { 403 /* 404 * This IP has an ECO; put the correct 405 * revision in it. 406 */ 407 gpu->identity.revision = 0x1051; 408 } 409 } 410 411 /* 412 * NXP likes to call the GPU on the i.MX6QP GC2000+, but in 413 * reality it's just a re-branded GC3000. We can identify this 414 * core by the upper half of the revision register being all 1. 415 * Fix model/rev here, so all other places can refer to this 416 * core by its real identity. 417 */ 418 if (etnaviv_is_model_rev(gpu, 0x2000, 0xffff5450)) { 419 gpu->identity.model = chipModel_GC3000; 420 gpu->identity.revision &= 0xffff; 421 } 422 423 if (etnaviv_is_model_rev(gpu, 0x1000, 0x5037) && (chipDate == 0x20120617)) 424 gpu->identity.eco_id = 1; 425 426 if (etnaviv_is_model_rev(gpu, 0x320, 0x5303) && (chipDate == 0x20140511)) 427 gpu->identity.eco_id = 1; 428 } 429 430 dev_info(gpu->dev, "model: GC%x, revision: %x\n", 431 gpu->identity.model, gpu->identity.revision); 432 433 gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP; 434 /* 435 * If there is a match in the HWDB, we aren't interested in the 436 * remaining register values, as they might be wrong. 437 */ 438 if (etnaviv_fill_identity_from_hwdb(gpu)) 439 return; 440 441 gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE); 442 443 /* Disable fast clear on GC700. */ 444 if (gpu->identity.model == chipModel_GC700) 445 gpu->identity.features &= ~chipFeatures_FAST_CLEAR; 446 447 /* These models/revisions don't have the 2D pipe bit */ 448 if ((gpu->identity.model == chipModel_GC500 && 449 gpu->identity.revision <= 2) || 450 gpu->identity.model == chipModel_GC300) 451 gpu->identity.features |= chipFeatures_PIPE_2D; 452 453 if ((gpu->identity.model == chipModel_GC500 && 454 gpu->identity.revision < 2) || 455 (gpu->identity.model == chipModel_GC300 && 456 gpu->identity.revision < 0x2000)) { 457 458 /* 459 * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these 460 * registers. 461 */ 462 gpu->identity.minor_features0 = 0; 463 gpu->identity.minor_features1 = 0; 464 gpu->identity.minor_features2 = 0; 465 gpu->identity.minor_features3 = 0; 466 gpu->identity.minor_features4 = 0; 467 gpu->identity.minor_features5 = 0; 468 } else 469 gpu->identity.minor_features0 = 470 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0); 471 472 if (gpu->identity.minor_features0 & 473 chipMinorFeatures0_MORE_MINOR_FEATURES) { 474 gpu->identity.minor_features1 = 475 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1); 476 gpu->identity.minor_features2 = 477 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2); 478 gpu->identity.minor_features3 = 479 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3); 480 gpu->identity.minor_features4 = 481 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4); 482 gpu->identity.minor_features5 = 483 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5); 484 } 485 486 /* GC600/300 idle register reports zero bits where modules aren't present */ 487 if (gpu->identity.model == chipModel_GC600 || 488 gpu->identity.model == chipModel_GC300) 489 gpu->idle_mask = VIVS_HI_IDLE_STATE_TX | 490 VIVS_HI_IDLE_STATE_RA | 491 VIVS_HI_IDLE_STATE_SE | 492 VIVS_HI_IDLE_STATE_PA | 493 VIVS_HI_IDLE_STATE_SH | 494 VIVS_HI_IDLE_STATE_PE | 495 VIVS_HI_IDLE_STATE_DE | 496 VIVS_HI_IDLE_STATE_FE; 497 498 etnaviv_hw_specs(gpu); 499 } 500 501 static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock) 502 { 503 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock | 504 VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD); 505 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); 506 } 507 508 static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu) 509 { 510 if (gpu->identity.minor_features2 & 511 chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING) { 512 clk_set_rate(gpu->clk_core, 513 gpu->base_rate_core >> gpu->freq_scale); 514 clk_set_rate(gpu->clk_shader, 515 gpu->base_rate_shader >> gpu->freq_scale); 516 } else { 517 unsigned int fscale = 1 << (6 - gpu->freq_scale); 518 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 519 520 clock &= ~VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK; 521 clock |= VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale); 522 etnaviv_gpu_load_clock(gpu, clock); 523 } 524 525 /* 526 * Choose number of wait cycles to target a ~30us (1/32768) max latency 527 * until new work is picked up by the FE when it polls in the idle loop. 528 * If the GPU base frequency is unknown use 200 wait cycles. 529 */ 530 gpu->fe_waitcycles = clamp(gpu->base_rate_core >> (15 - gpu->freq_scale), 531 200UL, 0xffffUL); 532 } 533 534 static int etnaviv_hw_reset(struct etnaviv_gpu *gpu) 535 { 536 u32 control, idle; 537 unsigned long timeout; 538 bool failed = true; 539 540 /* We hope that the GPU resets in under one second */ 541 timeout = jiffies + msecs_to_jiffies(1000); 542 543 while (time_is_after_jiffies(timeout)) { 544 unsigned int fscale = 1 << (6 - gpu->freq_scale); 545 u32 pulse_eater = 0x01590880; 546 547 /* disable clock gating */ 548 gpu_write_power_sync(gpu, VIVS_PM_POWER_CONTROLS, 0x0); 549 550 /* disable pulse eater */ 551 pulse_eater |= BIT(17); 552 gpu_write_power(gpu, VIVS_PM_PULSE_EATER, pulse_eater); 553 pulse_eater |= BIT(0); 554 gpu_write_power_sync(gpu, VIVS_PM_PULSE_EATER, pulse_eater); 555 556 /* enable clock */ 557 control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale); 558 etnaviv_gpu_load_clock(gpu, control); 559 560 /* isolate the GPU. */ 561 control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU; 562 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 563 564 if (gpu->sec_mode == ETNA_SEC_KERNEL) { 565 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, 566 VIVS_MMUv2_AHB_CONTROL_RESET); 567 } else { 568 /* set soft reset. */ 569 control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET; 570 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 571 } 572 573 /* wait for reset. */ 574 usleep_range(10, 20); 575 576 /* reset soft reset bit. */ 577 control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET; 578 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 579 580 /* reset GPU isolation. */ 581 control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU; 582 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 583 584 /* read idle register. */ 585 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 586 587 /* try resetting again if any module is not idle */ 588 if ((idle & gpu->idle_mask) != gpu->idle_mask) { 589 dev_dbg(gpu->dev, "GPU modules not idle\n"); 590 continue; 591 } 592 593 /* read reset register. */ 594 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 595 596 /* is the GPU idle? */ 597 if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) || 598 ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) { 599 dev_dbg(gpu->dev, "GPU is not idle\n"); 600 continue; 601 } 602 603 /* try resetting again if MMUv2 is not disabled */ 604 if (gpu->identity.minor_features1 & chipMinorFeatures1_MMU_VERSION) { 605 if (gpu->sec_mode == ETNA_SEC_KERNEL) { 606 if (gpu_read(gpu, VIVS_MMUv2_SEC_CONTROL) & 607 VIVS_MMUv2_SEC_CONTROL_ENABLE) { 608 dev_dbg(gpu->dev, "MMU is not disabled\n"); 609 continue; 610 } 611 } else { 612 if (gpu_read(gpu, VIVS_MMUv2_CONTROL) & 613 VIVS_MMUv2_CONTROL_ENABLE) { 614 dev_dbg(gpu->dev, "MMU is not disabled\n"); 615 continue; 616 } 617 } 618 } 619 620 /* enable debug register access */ 621 control &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS; 622 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 623 624 failed = false; 625 break; 626 } 627 628 if (failed) { 629 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 630 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 631 632 dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n", 633 idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ", 634 control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ", 635 control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not "); 636 637 return -EBUSY; 638 } 639 640 /* We rely on the GPU running, so program the clock */ 641 etnaviv_gpu_update_clock(gpu); 642 643 gpu->state = ETNA_GPU_STATE_RESET; 644 gpu->exec_state = -1; 645 if (gpu->mmu_context) 646 etnaviv_iommu_context_put(gpu->mmu_context); 647 gpu->mmu_context = NULL; 648 649 return 0; 650 } 651 652 static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu) 653 { 654 u32 pmc, ppc; 655 656 /* enable clock gating */ 657 ppc = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS); 658 ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; 659 660 /* Disable stall module clock gating for 4.3.0.1 and 4.3.0.2 revs */ 661 if (gpu->identity.revision == 0x4301 || 662 gpu->identity.revision == 0x4302) 663 ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING; 664 665 gpu_write_power_sync(gpu, VIVS_PM_POWER_CONTROLS, ppc); 666 667 pmc = gpu_read_power(gpu, VIVS_PM_MODULE_CONTROLS); 668 669 /* Disable PA clock gating for GC400+ without bugfix except for GC420 */ 670 if (gpu->identity.model >= chipModel_GC400 && 671 gpu->identity.model != chipModel_GC420 && 672 !(gpu->identity.minor_features3 & chipMinorFeatures3_BUG_FIXES12)) 673 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA; 674 675 /* 676 * Disable PE clock gating on revs < 5.0.0.0 when HZ is 677 * present without a bug fix. 678 */ 679 if (gpu->identity.revision < 0x5000 && 680 gpu->identity.minor_features0 & chipMinorFeatures0_HZ && 681 !(gpu->identity.minor_features1 & 682 chipMinorFeatures1_DISABLE_PE_GATING)) 683 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE; 684 685 if (gpu->identity.revision < 0x5422) 686 pmc |= BIT(15); /* Unknown bit */ 687 688 /* Disable TX clock gating on affected core revisions. */ 689 if (etnaviv_is_model_rev(gpu, 0x4000, 0x5222) || 690 etnaviv_is_model_rev(gpu, 0x2000, 0x5108) || 691 etnaviv_is_model_rev(gpu, 0x7000, 0x6202) || 692 etnaviv_is_model_rev(gpu, 0x7000, 0x6203)) 693 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX; 694 695 /* Disable SE and RA clock gating on affected core revisions. */ 696 if (etnaviv_is_model_rev(gpu, 0x7000, 0x6202)) 697 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE | 698 VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA; 699 700 /* Disable SH_EU clock gating on affected core revisions. */ 701 if (etnaviv_is_model_rev(gpu, 0x8000, 0x7200) || 702 etnaviv_is_model_rev(gpu, 0x8000, 0x8002) || 703 etnaviv_is_model_rev(gpu, 0x9200, 0x6304)) 704 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SH_EU; 705 706 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ; 707 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ; 708 709 gpu_write_power_sync(gpu, VIVS_PM_MODULE_CONTROLS, pmc); 710 } 711 712 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch) 713 { 714 gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address); 715 gpu_write(gpu, VIVS_FE_COMMAND_CONTROL, 716 VIVS_FE_COMMAND_CONTROL_ENABLE | 717 VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch)); 718 719 if (gpu->sec_mode == ETNA_SEC_KERNEL) { 720 gpu_write(gpu, VIVS_MMUv2_SEC_COMMAND_CONTROL, 721 VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE | 722 VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH(prefetch)); 723 } 724 } 725 726 static void etnaviv_gpu_start_fe_idleloop(struct etnaviv_gpu *gpu, 727 struct etnaviv_iommu_context *context) 728 { 729 u16 prefetch; 730 u32 address; 731 732 WARN_ON(gpu->state != ETNA_GPU_STATE_INITIALIZED); 733 734 /* setup the MMU */ 735 etnaviv_iommu_restore(gpu, context); 736 737 /* Start command processor */ 738 prefetch = etnaviv_buffer_init(gpu); 739 address = etnaviv_cmdbuf_get_va(&gpu->buffer, 740 &gpu->mmu_context->cmdbuf_mapping); 741 742 etnaviv_gpu_start_fe(gpu, address, prefetch); 743 744 gpu->state = ETNA_GPU_STATE_RUNNING; 745 } 746 747 static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu) 748 { 749 /* 750 * Base value for VIVS_PM_PULSE_EATER register on models where it 751 * cannot be read, extracted from vivante kernel driver. 752 */ 753 u32 pulse_eater = 0x01590880; 754 755 if (etnaviv_is_model_rev(gpu, 0x4000, 0x5208) || 756 etnaviv_is_model_rev(gpu, 0x4000, 0x5222)) { 757 pulse_eater |= BIT(23); 758 759 } 760 761 if (etnaviv_is_model_rev(gpu, 0x1000, 0x5039) || 762 etnaviv_is_model_rev(gpu, 0x1000, 0x5040)) { 763 pulse_eater &= ~BIT(16); 764 pulse_eater |= BIT(17); 765 } 766 767 if ((gpu->identity.revision > 0x5420) && 768 (gpu->identity.features & chipFeatures_PIPE_3D)) 769 { 770 /* Performance fix: disable internal DFS */ 771 pulse_eater = gpu_read_power(gpu, VIVS_PM_PULSE_EATER); 772 pulse_eater |= BIT(18); 773 } 774 775 gpu_write_power_sync(gpu, VIVS_PM_PULSE_EATER, pulse_eater); 776 } 777 778 static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu) 779 { 780 WARN_ON(!(gpu->state == ETNA_GPU_STATE_IDENTIFIED || 781 gpu->state == ETNA_GPU_STATE_RESET)); 782 783 if ((etnaviv_is_model_rev(gpu, 0x320, 0x5007) || 784 etnaviv_is_model_rev(gpu, 0x320, 0x5220)) && 785 gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) { 786 u32 mc_memory_debug; 787 788 mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff; 789 790 if (gpu->identity.revision == 0x5007) 791 mc_memory_debug |= 0x0c; 792 else 793 mc_memory_debug |= 0x08; 794 795 gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug); 796 } 797 798 /* enable module-level clock gating */ 799 etnaviv_gpu_enable_mlcg(gpu); 800 801 /* 802 * Update GPU AXI cache atttribute to "cacheable, no allocate". 803 * This is necessary to prevent the iMX6 SoC locking up. 804 */ 805 gpu_write(gpu, VIVS_HI_AXI_CONFIG, 806 VIVS_HI_AXI_CONFIG_AWCACHE(2) | 807 VIVS_HI_AXI_CONFIG_ARCACHE(2)); 808 809 /* GC2000 rev 5108 needs a special bus config */ 810 if (etnaviv_is_model_rev(gpu, 0x2000, 0x5108)) { 811 u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG); 812 bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK | 813 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK); 814 bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) | 815 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0); 816 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config); 817 } 818 819 if (gpu->sec_mode == ETNA_SEC_KERNEL) { 820 u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL); 821 val |= VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS; 822 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val); 823 } 824 825 /* setup the pulse eater */ 826 etnaviv_gpu_setup_pulse_eater(gpu); 827 828 gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U); 829 830 gpu->state = ETNA_GPU_STATE_INITIALIZED; 831 } 832 833 int etnaviv_gpu_init(struct etnaviv_gpu *gpu) 834 { 835 struct etnaviv_drm_private *priv = gpu->drm->dev_private; 836 dma_addr_t cmdbuf_paddr; 837 int ret, i; 838 839 ret = pm_runtime_get_sync(gpu->dev); 840 if (ret < 0) { 841 dev_err(gpu->dev, "Failed to enable GPU power domain\n"); 842 goto pm_put; 843 } 844 845 ret = etnaviv_gpu_reset_deassert(gpu); 846 if (ret) { 847 dev_err(gpu->dev, "GPU reset deassert failed\n"); 848 goto fail; 849 } 850 851 etnaviv_hw_identify(gpu); 852 853 if (gpu->identity.model == 0) { 854 dev_err(gpu->dev, "Unknown GPU model\n"); 855 ret = -ENXIO; 856 goto fail; 857 } 858 859 if (etnaviv_flop_reset_ppu_require(&gpu->identity) && 860 !priv->flop_reset_data_ppu) { 861 ret = etnaviv_flop_reset_ppu_init(priv); 862 if (ret) { 863 dev_err(gpu->dev, 864 "Unable to initialize PPU flop reset data\n"); 865 goto fail; 866 } 867 } 868 869 if (gpu->identity.nn_core_count > 0) 870 dev_warn(gpu->dev, "etnaviv has been instantiated on a NPU, " 871 "for which the UAPI is still experimental\n"); 872 873 /* Exclude VG cores with FE2.0 */ 874 if (gpu->identity.features & chipFeatures_PIPE_VG && 875 gpu->identity.features & chipFeatures_FE20) { 876 dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n"); 877 ret = -ENXIO; 878 goto fail; 879 } 880 881 /* 882 * On cores with security features supported, we claim control over the 883 * security states. 884 */ 885 if ((gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) && 886 (gpu->identity.minor_features10 & chipMinorFeatures10_SECURITY_AHB)) 887 gpu->sec_mode = ETNA_SEC_KERNEL; 888 889 gpu->state = ETNA_GPU_STATE_IDENTIFIED; 890 891 ret = etnaviv_hw_reset(gpu); 892 if (ret) { 893 dev_err(gpu->dev, "GPU reset failed\n"); 894 goto fail; 895 } 896 897 ret = etnaviv_iommu_global_init(gpu); 898 if (ret) 899 goto fail; 900 901 /* Create buffer: */ 902 ret = etnaviv_cmdbuf_init(priv->cmdbuf_suballoc, &gpu->buffer, SZ_4K); 903 if (ret) { 904 dev_err(gpu->dev, "could not create command buffer\n"); 905 goto fail; 906 } 907 908 /* 909 * Set the GPU linear window to cover the cmdbuf region, as the GPU 910 * won't be able to start execution otherwise. The alignment to 128M is 911 * chosen arbitrarily but helps in debugging, as the MMU offset 912 * calculations are much more straight forward this way. 913 * 914 * On MC1.0 cores the linear window offset is ignored by the TS engine, 915 * leading to inconsistent memory views. Avoid using the offset on those 916 * cores if possible, otherwise disable the TS feature. MMUv2 doesn't 917 * expose this issue, as all TS accesses are MMU translated, so the 918 * linear window offset won't be used. 919 */ 920 cmdbuf_paddr = ALIGN_DOWN(etnaviv_cmdbuf_get_pa(&gpu->buffer), SZ_128M); 921 922 if (!(gpu->identity.features & chipFeatures_PIPE_3D) || 923 (gpu->identity.minor_features0 & chipMinorFeatures0_MC20) || 924 (gpu->identity.minor_features1 & chipMinorFeatures1_MMU_VERSION)) { 925 if (cmdbuf_paddr >= SZ_2G) 926 priv->mmu_global->memory_base = SZ_2G; 927 else 928 priv->mmu_global->memory_base = cmdbuf_paddr; 929 } else if (cmdbuf_paddr + SZ_128M >= SZ_2G) { 930 dev_info(gpu->dev, 931 "Need to move linear window on MC1.0, disabling TS\n"); 932 gpu->identity.features &= ~chipFeatures_FAST_CLEAR; 933 priv->mmu_global->memory_base = SZ_2G; 934 } 935 936 /* Setup event management */ 937 spin_lock_init(&gpu->event_spinlock); 938 init_completion(&gpu->event_free); 939 bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS); 940 for (i = 0; i < ARRAY_SIZE(gpu->event); i++) 941 complete(&gpu->event_free); 942 943 /* Now program the hardware */ 944 mutex_lock(&gpu->lock); 945 etnaviv_gpu_hw_init(gpu); 946 mutex_unlock(&gpu->lock); 947 948 pm_runtime_mark_last_busy(gpu->dev); 949 pm_runtime_put_autosuspend(gpu->dev); 950 951 return 0; 952 953 fail: 954 pm_runtime_mark_last_busy(gpu->dev); 955 pm_put: 956 pm_runtime_put_autosuspend(gpu->dev); 957 958 return ret; 959 } 960 961 #ifdef CONFIG_DEBUG_FS 962 struct dma_debug { 963 u32 address[2]; 964 u32 state[2]; 965 }; 966 967 static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug) 968 { 969 u32 i; 970 971 debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 972 debug->state[0] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE); 973 974 for (i = 0; i < 500; i++) { 975 debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 976 debug->state[1] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE); 977 978 if (debug->address[0] != debug->address[1]) 979 break; 980 981 if (debug->state[0] != debug->state[1]) 982 break; 983 } 984 } 985 986 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m) 987 { 988 struct dma_debug debug; 989 u32 dma_lo, dma_hi, axi, idle; 990 int ret; 991 992 seq_printf(m, "%s Status:\n", dev_name(gpu->dev)); 993 994 ret = pm_runtime_get_sync(gpu->dev); 995 if (ret < 0) 996 goto pm_put; 997 998 dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW); 999 dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH); 1000 axi = gpu_read(gpu, VIVS_HI_AXI_STATUS); 1001 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 1002 1003 verify_dma(gpu, &debug); 1004 1005 seq_puts(m, "\tidentity\n"); 1006 seq_printf(m, "\t model: 0x%x\n", gpu->identity.model); 1007 seq_printf(m, "\t revision: 0x%x\n", gpu->identity.revision); 1008 seq_printf(m, "\t product_id: 0x%x\n", gpu->identity.product_id); 1009 seq_printf(m, "\t customer_id: 0x%x\n", gpu->identity.customer_id); 1010 seq_printf(m, "\t eco_id: 0x%x\n", gpu->identity.eco_id); 1011 1012 seq_puts(m, "\tfeatures\n"); 1013 seq_printf(m, "\t major_features: 0x%08x\n", 1014 gpu->identity.features); 1015 seq_printf(m, "\t minor_features0: 0x%08x\n", 1016 gpu->identity.minor_features0); 1017 seq_printf(m, "\t minor_features1: 0x%08x\n", 1018 gpu->identity.minor_features1); 1019 seq_printf(m, "\t minor_features2: 0x%08x\n", 1020 gpu->identity.minor_features2); 1021 seq_printf(m, "\t minor_features3: 0x%08x\n", 1022 gpu->identity.minor_features3); 1023 seq_printf(m, "\t minor_features4: 0x%08x\n", 1024 gpu->identity.minor_features4); 1025 seq_printf(m, "\t minor_features5: 0x%08x\n", 1026 gpu->identity.minor_features5); 1027 seq_printf(m, "\t minor_features6: 0x%08x\n", 1028 gpu->identity.minor_features6); 1029 seq_printf(m, "\t minor_features7: 0x%08x\n", 1030 gpu->identity.minor_features7); 1031 seq_printf(m, "\t minor_features8: 0x%08x\n", 1032 gpu->identity.minor_features8); 1033 seq_printf(m, "\t minor_features9: 0x%08x\n", 1034 gpu->identity.minor_features9); 1035 seq_printf(m, "\t minor_features10: 0x%08x\n", 1036 gpu->identity.minor_features10); 1037 seq_printf(m, "\t minor_features11: 0x%08x\n", 1038 gpu->identity.minor_features11); 1039 1040 seq_puts(m, "\tspecs\n"); 1041 seq_printf(m, "\t stream_count: %d\n", 1042 gpu->identity.stream_count); 1043 seq_printf(m, "\t register_max: %d\n", 1044 gpu->identity.register_max); 1045 seq_printf(m, "\t thread_count: %d\n", 1046 gpu->identity.thread_count); 1047 seq_printf(m, "\t vertex_cache_size: %d\n", 1048 gpu->identity.vertex_cache_size); 1049 seq_printf(m, "\t shader_core_count: %d\n", 1050 gpu->identity.shader_core_count); 1051 seq_printf(m, "\t nn_core_count: %d\n", 1052 gpu->identity.nn_core_count); 1053 seq_printf(m, "\t pixel_pipes: %d\n", 1054 gpu->identity.pixel_pipes); 1055 seq_printf(m, "\t vertex_output_buffer_size: %d\n", 1056 gpu->identity.vertex_output_buffer_size); 1057 seq_printf(m, "\t buffer_size: %d\n", 1058 gpu->identity.buffer_size); 1059 seq_printf(m, "\t instruction_count: %d\n", 1060 gpu->identity.instruction_count); 1061 seq_printf(m, "\t num_constants: %d\n", 1062 gpu->identity.num_constants); 1063 seq_printf(m, "\t varyings_count: %d\n", 1064 gpu->identity.varyings_count); 1065 1066 seq_printf(m, "\taxi: 0x%08x\n", axi); 1067 seq_printf(m, "\tidle: 0x%08x\n", idle); 1068 idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP; 1069 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) 1070 seq_puts(m, "\t FE is not idle\n"); 1071 if ((idle & VIVS_HI_IDLE_STATE_DE) == 0) 1072 seq_puts(m, "\t DE is not idle\n"); 1073 if ((idle & VIVS_HI_IDLE_STATE_PE) == 0) 1074 seq_puts(m, "\t PE is not idle\n"); 1075 if ((idle & VIVS_HI_IDLE_STATE_SH) == 0) 1076 seq_puts(m, "\t SH is not idle\n"); 1077 if ((idle & VIVS_HI_IDLE_STATE_PA) == 0) 1078 seq_puts(m, "\t PA is not idle\n"); 1079 if ((idle & VIVS_HI_IDLE_STATE_SE) == 0) 1080 seq_puts(m, "\t SE is not idle\n"); 1081 if ((idle & VIVS_HI_IDLE_STATE_RA) == 0) 1082 seq_puts(m, "\t RA is not idle\n"); 1083 if ((idle & VIVS_HI_IDLE_STATE_TX) == 0) 1084 seq_puts(m, "\t TX is not idle\n"); 1085 if ((idle & VIVS_HI_IDLE_STATE_VG) == 0) 1086 seq_puts(m, "\t VG is not idle\n"); 1087 if ((idle & VIVS_HI_IDLE_STATE_IM) == 0) 1088 seq_puts(m, "\t IM is not idle\n"); 1089 if ((idle & VIVS_HI_IDLE_STATE_FP) == 0) 1090 seq_puts(m, "\t FP is not idle\n"); 1091 if ((idle & VIVS_HI_IDLE_STATE_TS) == 0) 1092 seq_puts(m, "\t TS is not idle\n"); 1093 if ((idle & VIVS_HI_IDLE_STATE_BL) == 0) 1094 seq_puts(m, "\t BL is not idle\n"); 1095 if ((idle & VIVS_HI_IDLE_STATE_ASYNCFE) == 0) 1096 seq_puts(m, "\t ASYNCFE is not idle\n"); 1097 if ((idle & VIVS_HI_IDLE_STATE_MC) == 0) 1098 seq_puts(m, "\t MC is not idle\n"); 1099 if ((idle & VIVS_HI_IDLE_STATE_PPA) == 0) 1100 seq_puts(m, "\t PPA is not idle\n"); 1101 if ((idle & VIVS_HI_IDLE_STATE_WD) == 0) 1102 seq_puts(m, "\t WD is not idle\n"); 1103 if ((idle & VIVS_HI_IDLE_STATE_NN) == 0) 1104 seq_puts(m, "\t NN is not idle\n"); 1105 if ((idle & VIVS_HI_IDLE_STATE_TP) == 0) 1106 seq_puts(m, "\t TP is not idle\n"); 1107 if (idle & VIVS_HI_IDLE_STATE_AXI_LP) 1108 seq_puts(m, "\t AXI low power mode\n"); 1109 1110 if (gpu->identity.features & chipFeatures_DEBUG_MODE) { 1111 u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0); 1112 u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1); 1113 u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE); 1114 1115 seq_puts(m, "\tMC\n"); 1116 seq_printf(m, "\t read0: 0x%08x\n", read0); 1117 seq_printf(m, "\t read1: 0x%08x\n", read1); 1118 seq_printf(m, "\t write: 0x%08x\n", write); 1119 } 1120 1121 seq_puts(m, "\tDMA "); 1122 1123 if (debug.address[0] == debug.address[1] && 1124 debug.state[0] == debug.state[1]) { 1125 seq_puts(m, "seems to be stuck\n"); 1126 } else if (debug.address[0] == debug.address[1]) { 1127 seq_puts(m, "address is constant\n"); 1128 } else { 1129 seq_puts(m, "is running\n"); 1130 } 1131 1132 seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]); 1133 seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]); 1134 seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]); 1135 seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]); 1136 seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n", 1137 dma_lo, dma_hi); 1138 1139 ret = 0; 1140 1141 pm_runtime_mark_last_busy(gpu->dev); 1142 pm_put: 1143 pm_runtime_put_autosuspend(gpu->dev); 1144 1145 return ret; 1146 } 1147 #endif 1148 1149 /* fence object management */ 1150 struct etnaviv_fence { 1151 struct etnaviv_gpu *gpu; 1152 struct dma_fence base; 1153 }; 1154 1155 static inline struct etnaviv_fence *to_etnaviv_fence(struct dma_fence *fence) 1156 { 1157 return container_of(fence, struct etnaviv_fence, base); 1158 } 1159 1160 static const char *etnaviv_fence_get_driver_name(struct dma_fence *fence) 1161 { 1162 return "etnaviv"; 1163 } 1164 1165 static const char *etnaviv_fence_get_timeline_name(struct dma_fence *fence) 1166 { 1167 struct etnaviv_fence *f = to_etnaviv_fence(fence); 1168 1169 return dev_name(f->gpu->dev); 1170 } 1171 1172 static bool etnaviv_fence_signaled(struct dma_fence *fence) 1173 { 1174 struct etnaviv_fence *f = to_etnaviv_fence(fence); 1175 1176 return (s32)(f->gpu->completed_fence - f->base.seqno) >= 0; 1177 } 1178 1179 static void etnaviv_fence_release(struct dma_fence *fence) 1180 { 1181 struct etnaviv_fence *f = to_etnaviv_fence(fence); 1182 1183 kfree_rcu(f, base.rcu); 1184 } 1185 1186 static const struct dma_fence_ops etnaviv_fence_ops = { 1187 .get_driver_name = etnaviv_fence_get_driver_name, 1188 .get_timeline_name = etnaviv_fence_get_timeline_name, 1189 .signaled = etnaviv_fence_signaled, 1190 .release = etnaviv_fence_release, 1191 }; 1192 1193 static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu) 1194 { 1195 struct etnaviv_fence *f; 1196 1197 /* 1198 * GPU lock must already be held, otherwise fence completion order might 1199 * not match the seqno order assigned here. 1200 */ 1201 lockdep_assert_held(&gpu->lock); 1202 1203 f = kzalloc_obj(*f); 1204 if (!f) 1205 return NULL; 1206 1207 f->gpu = gpu; 1208 1209 dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock, 1210 gpu->fence_context, ++gpu->next_fence); 1211 1212 return &f->base; 1213 } 1214 1215 /* returns true if fence a comes after fence b */ 1216 static inline bool fence_after(u32 a, u32 b) 1217 { 1218 return (s32)(a - b) > 0; 1219 } 1220 1221 /* 1222 * event management: 1223 */ 1224 1225 static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events, 1226 unsigned int *events) 1227 { 1228 unsigned long timeout = msecs_to_jiffies(10 * 10000); 1229 unsigned i, acquired = 0, rpm_count = 0; 1230 int ret; 1231 1232 for (i = 0; i < nr_events; i++) { 1233 unsigned long remaining; 1234 1235 remaining = wait_for_completion_timeout(&gpu->event_free, timeout); 1236 1237 if (!remaining) { 1238 dev_err(gpu->dev, "wait_for_completion_timeout failed"); 1239 ret = -EBUSY; 1240 goto out; 1241 } 1242 1243 acquired++; 1244 timeout = remaining; 1245 } 1246 1247 spin_lock(&gpu->event_spinlock); 1248 1249 for (i = 0; i < nr_events; i++) { 1250 int event = find_first_zero_bit(gpu->event_bitmap, ETNA_NR_EVENTS); 1251 1252 events[i] = event; 1253 memset(&gpu->event[event], 0, sizeof(struct etnaviv_event)); 1254 set_bit(event, gpu->event_bitmap); 1255 } 1256 1257 spin_unlock(&gpu->event_spinlock); 1258 1259 for (i = 0; i < nr_events; i++) { 1260 ret = pm_runtime_resume_and_get(gpu->dev); 1261 if (ret) 1262 goto out_rpm; 1263 rpm_count++; 1264 } 1265 1266 return 0; 1267 1268 out_rpm: 1269 for (i = 0; i < rpm_count; i++) 1270 pm_runtime_put_autosuspend(gpu->dev); 1271 out: 1272 for (i = 0; i < acquired; i++) 1273 complete(&gpu->event_free); 1274 1275 return ret; 1276 } 1277 1278 static void event_free(struct etnaviv_gpu *gpu, unsigned int event) 1279 { 1280 if (!test_bit(event, gpu->event_bitmap)) { 1281 dev_warn(gpu->dev, "event %u is already marked as free", 1282 event); 1283 } else { 1284 clear_bit(event, gpu->event_bitmap); 1285 complete(&gpu->event_free); 1286 } 1287 1288 pm_runtime_put_autosuspend(gpu->dev); 1289 } 1290 1291 /* 1292 * Cmdstream submission/retirement: 1293 */ 1294 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu, 1295 u32 id, struct drm_etnaviv_timespec *timeout) 1296 { 1297 struct dma_fence *fence; 1298 int ret; 1299 1300 /* 1301 * Look up the fence and take a reference. We might still find a fence 1302 * whose refcount has already dropped to zero. dma_fence_get_rcu 1303 * pretends we didn't find a fence in that case. 1304 */ 1305 rcu_read_lock(); 1306 fence = xa_load(&gpu->user_fences, id); 1307 if (fence) 1308 fence = dma_fence_get_rcu(fence); 1309 rcu_read_unlock(); 1310 1311 if (!fence) 1312 return 0; 1313 1314 if (!timeout) { 1315 /* No timeout was requested: just test for completion */ 1316 ret = dma_fence_is_signaled(fence) ? 0 : -EBUSY; 1317 } else { 1318 unsigned long remaining = etnaviv_timeout_to_jiffies(timeout); 1319 1320 ret = dma_fence_wait_timeout(fence, true, remaining); 1321 if (ret == 0) 1322 ret = -ETIMEDOUT; 1323 else if (ret != -ERESTARTSYS) 1324 ret = 0; 1325 1326 } 1327 1328 dma_fence_put(fence); 1329 return ret; 1330 } 1331 1332 /* 1333 * Wait for an object to become inactive. This, on it's own, is not race 1334 * free: the object is moved by the scheduler off the active list, and 1335 * then the iova is put. Moreover, the object could be re-submitted just 1336 * after we notice that it's become inactive. 1337 * 1338 * Although the retirement happens under the gpu lock, we don't want to hold 1339 * that lock in this function while waiting. 1340 */ 1341 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu, 1342 struct etnaviv_gem_object *etnaviv_obj, 1343 struct drm_etnaviv_timespec *timeout) 1344 { 1345 unsigned long remaining; 1346 long ret; 1347 1348 if (!timeout) 1349 return !is_active(etnaviv_obj) ? 0 : -EBUSY; 1350 1351 remaining = etnaviv_timeout_to_jiffies(timeout); 1352 1353 ret = wait_event_interruptible_timeout(gpu->fence_event, 1354 !is_active(etnaviv_obj), 1355 remaining); 1356 if (ret > 0) 1357 return 0; 1358 else if (ret == -ERESTARTSYS) 1359 return -ERESTARTSYS; 1360 else 1361 return -ETIMEDOUT; 1362 } 1363 1364 static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu, 1365 struct etnaviv_event *event, unsigned int flags) 1366 { 1367 const struct etnaviv_gem_submit *submit = event->submit; 1368 unsigned int i; 1369 1370 for (i = 0; i < submit->nr_pmrs; i++) { 1371 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i; 1372 1373 if (pmr->flags == flags) 1374 etnaviv_perfmon_process(gpu, pmr, submit->exec_state); 1375 } 1376 } 1377 1378 static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu, 1379 struct etnaviv_event *event) 1380 { 1381 u32 val; 1382 1383 mutex_lock(&gpu->lock); 1384 1385 /* disable clock gating */ 1386 val = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS); 1387 val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; 1388 gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, val); 1389 1390 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE); 1391 1392 mutex_unlock(&gpu->lock); 1393 } 1394 1395 static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu, 1396 struct etnaviv_event *event) 1397 { 1398 const struct etnaviv_gem_submit *submit = event->submit; 1399 unsigned int i; 1400 u32 val; 1401 1402 mutex_lock(&gpu->lock); 1403 1404 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST); 1405 1406 /* enable clock gating */ 1407 val = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS); 1408 val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; 1409 gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, val); 1410 1411 mutex_unlock(&gpu->lock); 1412 1413 for (i = 0; i < submit->nr_pmrs; i++) { 1414 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i; 1415 1416 *pmr->bo_vma = pmr->sequence; 1417 } 1418 } 1419 1420 1421 /* add bo's to gpu's ring, and kick gpu: */ 1422 struct dma_fence *etnaviv_gpu_submit(struct etnaviv_gem_submit *submit) 1423 { 1424 struct etnaviv_gpu *gpu = submit->gpu; 1425 struct dma_fence *gpu_fence; 1426 unsigned int i, nr_events = 1, event[3]; 1427 int ret; 1428 1429 /* 1430 * if there are performance monitor requests we need to have 1431 * - a sync point to re-configure gpu and process ETNA_PM_PROCESS_PRE 1432 * requests. 1433 * - a sync point to re-configure gpu, process ETNA_PM_PROCESS_POST requests 1434 * and update the sequence number for userspace. 1435 */ 1436 if (submit->nr_pmrs) 1437 nr_events = 3; 1438 1439 ret = event_alloc(gpu, nr_events, event); 1440 if (ret) { 1441 DRM_ERROR("no free events\n"); 1442 pm_runtime_put_noidle(gpu->dev); 1443 return NULL; 1444 } 1445 1446 mutex_lock(&gpu->lock); 1447 1448 gpu_fence = etnaviv_gpu_fence_alloc(gpu); 1449 if (!gpu_fence) { 1450 for (i = 0; i < nr_events; i++) 1451 event_free(gpu, event[i]); 1452 1453 goto out_unlock; 1454 } 1455 1456 if (gpu->state == ETNA_GPU_STATE_INITIALIZED) 1457 etnaviv_gpu_start_fe_idleloop(gpu, submit->mmu_context); 1458 1459 if (submit->prev_mmu_context) 1460 etnaviv_iommu_context_put(submit->prev_mmu_context); 1461 submit->prev_mmu_context = etnaviv_iommu_context_get(gpu->mmu_context); 1462 1463 if (submit->nr_pmrs) { 1464 gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre; 1465 kref_get(&submit->refcount); 1466 gpu->event[event[1]].submit = submit; 1467 etnaviv_sync_point_queue(gpu, event[1]); 1468 } 1469 1470 gpu->event[event[0]].fence = gpu_fence; 1471 submit->cmdbuf.user_size = submit->cmdbuf.size - 8; 1472 etnaviv_buffer_queue(gpu, submit->exec_state, submit->mmu_context, 1473 event[0], &submit->cmdbuf); 1474 1475 if (submit->nr_pmrs) { 1476 gpu->event[event[2]].sync_point = &sync_point_perfmon_sample_post; 1477 kref_get(&submit->refcount); 1478 gpu->event[event[2]].submit = submit; 1479 etnaviv_sync_point_queue(gpu, event[2]); 1480 } 1481 1482 out_unlock: 1483 mutex_unlock(&gpu->lock); 1484 1485 return gpu_fence; 1486 } 1487 1488 static void sync_point_worker(struct work_struct *work) 1489 { 1490 struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu, 1491 sync_point_work); 1492 struct etnaviv_event *event = &gpu->event[gpu->sync_point_event]; 1493 u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 1494 1495 event->sync_point(gpu, event); 1496 etnaviv_submit_put(event->submit); 1497 event_free(gpu, gpu->sync_point_event); 1498 1499 /* restart FE last to avoid GPU and IRQ racing against this worker */ 1500 etnaviv_gpu_start_fe(gpu, addr + 2, 2); 1501 } 1502 1503 void etnaviv_gpu_recover_hang(struct etnaviv_gem_submit *submit) 1504 { 1505 struct etnaviv_gpu *gpu = submit->gpu; 1506 char *comm = NULL, *cmd = NULL; 1507 struct task_struct *task; 1508 unsigned int i; 1509 1510 dev_err(gpu->dev, "recover hung GPU!\n"); 1511 1512 task = get_pid_task(submit->pid, PIDTYPE_PID); 1513 if (task) { 1514 comm = kstrdup(task->comm, GFP_KERNEL); 1515 cmd = kstrdup_quotable_cmdline(task, GFP_KERNEL); 1516 put_task_struct(task); 1517 } 1518 1519 if (comm && cmd) 1520 dev_err(gpu->dev, "offending task: %s (%s)\n", comm, cmd); 1521 1522 kfree(cmd); 1523 kfree(comm); 1524 1525 if (pm_runtime_get_sync(gpu->dev) < 0) 1526 goto pm_put; 1527 1528 mutex_lock(&gpu->lock); 1529 1530 etnaviv_hw_reset(gpu); 1531 1532 /* complete all events, the GPU won't do it after the reset */ 1533 spin_lock(&gpu->event_spinlock); 1534 for_each_set_bit(i, gpu->event_bitmap, ETNA_NR_EVENTS) 1535 event_free(gpu, i); 1536 spin_unlock(&gpu->event_spinlock); 1537 1538 etnaviv_gpu_hw_init(gpu); 1539 1540 mutex_unlock(&gpu->lock); 1541 pm_runtime_mark_last_busy(gpu->dev); 1542 pm_put: 1543 pm_runtime_put_autosuspend(gpu->dev); 1544 } 1545 1546 static void dump_mmu_fault(struct etnaviv_gpu *gpu) 1547 { 1548 static const char *fault_reasons[] = { 1549 "slave not present", 1550 "page not present", 1551 "write violation", 1552 "out of bounds", 1553 "read security violation", 1554 "write security violation", 1555 }; 1556 1557 u32 status_reg, status; 1558 int i; 1559 1560 if (gpu->sec_mode == ETNA_SEC_NONE) 1561 status_reg = VIVS_MMUv2_STATUS; 1562 else 1563 status_reg = VIVS_MMUv2_SEC_STATUS; 1564 1565 status = gpu_read(gpu, status_reg); 1566 dev_err_ratelimited(gpu->dev, "MMU fault status 0x%08x\n", status); 1567 1568 for (i = 0; i < 4; i++) { 1569 const char *reason = "unknown"; 1570 u32 address_reg; 1571 u32 mmu_status; 1572 1573 mmu_status = (status >> (i * 4)) & VIVS_MMUv2_STATUS_EXCEPTION0__MASK; 1574 if (!mmu_status) 1575 continue; 1576 1577 if ((mmu_status - 1) < ARRAY_SIZE(fault_reasons)) 1578 reason = fault_reasons[mmu_status - 1]; 1579 1580 if (gpu->sec_mode == ETNA_SEC_NONE) 1581 address_reg = VIVS_MMUv2_EXCEPTION_ADDR(i); 1582 else 1583 address_reg = VIVS_MMUv2_SEC_EXCEPTION_ADDR; 1584 1585 dev_err_ratelimited(gpu->dev, 1586 "MMU %d fault (%s) addr 0x%08x\n", 1587 i, reason, gpu_read(gpu, address_reg)); 1588 } 1589 } 1590 1591 static irqreturn_t irq_handler(int irq, void *data) 1592 { 1593 struct etnaviv_gpu *gpu = data; 1594 irqreturn_t ret = IRQ_NONE; 1595 1596 u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE); 1597 1598 if (intr != 0) { 1599 ktime_t now = ktime_get(); 1600 int event; 1601 1602 pm_runtime_mark_last_busy(gpu->dev); 1603 1604 dev_dbg(gpu->dev, "intr 0x%08x\n", intr); 1605 1606 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) { 1607 dev_err(gpu->dev, "AXI bus error\n"); 1608 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR; 1609 } 1610 1611 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) { 1612 dump_mmu_fault(gpu); 1613 gpu->state = ETNA_GPU_STATE_FAULT; 1614 drm_sched_fault(&gpu->sched); 1615 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION; 1616 } 1617 1618 while ((event = ffs(intr)) != 0) { 1619 struct dma_fence *fence; 1620 1621 event -= 1; 1622 1623 intr &= ~(1 << event); 1624 1625 dev_dbg(gpu->dev, "event %u\n", event); 1626 1627 if (gpu->event[event].sync_point) { 1628 gpu->sync_point_event = event; 1629 queue_work(gpu->wq, &gpu->sync_point_work); 1630 } 1631 1632 fence = gpu->event[event].fence; 1633 if (!fence) 1634 continue; 1635 1636 gpu->event[event].fence = NULL; 1637 1638 /* 1639 * Events can be processed out of order. Eg, 1640 * - allocate and queue event 0 1641 * - allocate event 1 1642 * - event 0 completes, we process it 1643 * - allocate and queue event 0 1644 * - event 1 and event 0 complete 1645 * we can end up processing event 0 first, then 1. 1646 */ 1647 if (fence_after(fence->seqno, gpu->completed_fence)) 1648 gpu->completed_fence = fence->seqno; 1649 dma_fence_signal_timestamp(fence, now); 1650 1651 event_free(gpu, event); 1652 } 1653 1654 ret = IRQ_HANDLED; 1655 } 1656 1657 return ret; 1658 } 1659 1660 static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu) 1661 { 1662 int ret; 1663 1664 ret = clk_prepare_enable(gpu->clk_reg); 1665 if (ret) 1666 return ret; 1667 1668 ret = clk_prepare_enable(gpu->clk_bus); 1669 if (ret) 1670 goto disable_clk_reg; 1671 1672 ret = clk_prepare_enable(gpu->clk_core); 1673 if (ret) 1674 goto disable_clk_bus; 1675 1676 ret = clk_prepare_enable(gpu->clk_shader); 1677 if (ret) 1678 goto disable_clk_core; 1679 1680 return 0; 1681 1682 disable_clk_core: 1683 clk_disable_unprepare(gpu->clk_core); 1684 disable_clk_bus: 1685 clk_disable_unprepare(gpu->clk_bus); 1686 disable_clk_reg: 1687 clk_disable_unprepare(gpu->clk_reg); 1688 1689 return ret; 1690 } 1691 1692 static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu) 1693 { 1694 clk_disable_unprepare(gpu->clk_shader); 1695 clk_disable_unprepare(gpu->clk_core); 1696 clk_disable_unprepare(gpu->clk_bus); 1697 clk_disable_unprepare(gpu->clk_reg); 1698 1699 return 0; 1700 } 1701 1702 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms) 1703 { 1704 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms); 1705 1706 do { 1707 u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 1708 1709 if ((idle & gpu->idle_mask) == gpu->idle_mask) 1710 return 0; 1711 1712 if (time_is_before_jiffies(timeout)) { 1713 dev_warn(gpu->dev, 1714 "timed out waiting for idle: idle=0x%x\n", 1715 idle); 1716 return -ETIMEDOUT; 1717 } 1718 1719 udelay(5); 1720 } while (1); 1721 } 1722 1723 static void etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu) 1724 { 1725 if (gpu->state == ETNA_GPU_STATE_RUNNING) { 1726 /* Replace the last WAIT with END */ 1727 mutex_lock(&gpu->lock); 1728 etnaviv_buffer_end(gpu); 1729 mutex_unlock(&gpu->lock); 1730 1731 /* 1732 * We know that only the FE is busy here, this should 1733 * happen quickly (as the WAIT is only 200 cycles). If 1734 * we fail, just warn and continue. 1735 */ 1736 etnaviv_gpu_wait_idle(gpu, 100); 1737 1738 gpu->state = ETNA_GPU_STATE_INITIALIZED; 1739 } 1740 1741 gpu->exec_state = -1; 1742 } 1743 1744 static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu) 1745 { 1746 int ret; 1747 1748 ret = mutex_lock_killable(&gpu->lock); 1749 if (ret) 1750 return ret; 1751 1752 etnaviv_gpu_update_clock(gpu); 1753 etnaviv_gpu_hw_init(gpu); 1754 1755 mutex_unlock(&gpu->lock); 1756 1757 return 0; 1758 } 1759 1760 static int 1761 etnaviv_gpu_cooling_get_max_state(struct thermal_cooling_device *cdev, 1762 unsigned long *state) 1763 { 1764 *state = 6; 1765 1766 return 0; 1767 } 1768 1769 static int 1770 etnaviv_gpu_cooling_get_cur_state(struct thermal_cooling_device *cdev, 1771 unsigned long *state) 1772 { 1773 struct etnaviv_gpu *gpu = cdev->devdata; 1774 1775 *state = gpu->freq_scale; 1776 1777 return 0; 1778 } 1779 1780 static int 1781 etnaviv_gpu_cooling_set_cur_state(struct thermal_cooling_device *cdev, 1782 unsigned long state) 1783 { 1784 struct etnaviv_gpu *gpu = cdev->devdata; 1785 1786 mutex_lock(&gpu->lock); 1787 gpu->freq_scale = state; 1788 if (!pm_runtime_suspended(gpu->dev)) 1789 etnaviv_gpu_update_clock(gpu); 1790 mutex_unlock(&gpu->lock); 1791 1792 return 0; 1793 } 1794 1795 static const struct thermal_cooling_device_ops cooling_ops = { 1796 .get_max_state = etnaviv_gpu_cooling_get_max_state, 1797 .get_cur_state = etnaviv_gpu_cooling_get_cur_state, 1798 .set_cur_state = etnaviv_gpu_cooling_set_cur_state, 1799 }; 1800 1801 static int etnaviv_gpu_bind(struct device *dev, struct device *master, 1802 void *data) 1803 { 1804 struct drm_device *drm = data; 1805 struct etnaviv_drm_private *priv = drm->dev_private; 1806 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1807 int ret; 1808 1809 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) { 1810 gpu->cooling = thermal_of_cooling_device_register(dev->of_node, 0, 1811 dev_name(dev), 1812 gpu, &cooling_ops); 1813 if (IS_ERR(gpu->cooling)) 1814 return PTR_ERR(gpu->cooling); 1815 } 1816 1817 gpu->wq = alloc_ordered_workqueue(dev_name(dev), 0); 1818 if (!gpu->wq) { 1819 ret = -ENOMEM; 1820 goto out_thermal; 1821 } 1822 1823 ret = etnaviv_sched_init(gpu); 1824 if (ret) 1825 goto out_workqueue; 1826 1827 if (!IS_ENABLED(CONFIG_PM)) { 1828 ret = etnaviv_gpu_clk_enable(gpu); 1829 if (ret < 0) 1830 goto out_sched; 1831 } 1832 1833 gpu->drm = drm; 1834 gpu->fence_context = dma_fence_context_alloc(1); 1835 xa_init_flags(&gpu->user_fences, XA_FLAGS_ALLOC); 1836 spin_lock_init(&gpu->fence_spinlock); 1837 1838 INIT_WORK(&gpu->sync_point_work, sync_point_worker); 1839 init_waitqueue_head(&gpu->fence_event); 1840 1841 priv->gpu[priv->num_gpus++] = gpu; 1842 1843 return 0; 1844 1845 out_sched: 1846 etnaviv_sched_fini(gpu); 1847 1848 out_workqueue: 1849 destroy_workqueue(gpu->wq); 1850 1851 out_thermal: 1852 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) 1853 thermal_cooling_device_unregister(gpu->cooling); 1854 1855 return ret; 1856 } 1857 1858 static void etnaviv_gpu_unbind(struct device *dev, struct device *master, 1859 void *data) 1860 { 1861 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1862 1863 DBG("%s", dev_name(gpu->dev)); 1864 1865 destroy_workqueue(gpu->wq); 1866 1867 etnaviv_sched_fini(gpu); 1868 1869 if (IS_ENABLED(CONFIG_PM)) { 1870 pm_runtime_get_sync(gpu->dev); 1871 pm_runtime_put_sync_suspend(gpu->dev); 1872 } else { 1873 etnaviv_gpu_hw_suspend(gpu); 1874 etnaviv_gpu_clk_disable(gpu); 1875 } 1876 1877 if (gpu->mmu_context) 1878 etnaviv_iommu_context_put(gpu->mmu_context); 1879 1880 etnaviv_cmdbuf_free(&gpu->buffer); 1881 etnaviv_iommu_global_fini(gpu); 1882 1883 gpu->drm = NULL; 1884 xa_destroy(&gpu->user_fences); 1885 1886 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) 1887 thermal_cooling_device_unregister(gpu->cooling); 1888 gpu->cooling = NULL; 1889 } 1890 1891 static const struct component_ops gpu_ops = { 1892 .bind = etnaviv_gpu_bind, 1893 .unbind = etnaviv_gpu_unbind, 1894 }; 1895 1896 static const struct of_device_id etnaviv_gpu_match[] = { 1897 { 1898 .compatible = "vivante,gc" 1899 }, 1900 { /* sentinel */ } 1901 }; 1902 MODULE_DEVICE_TABLE(of, etnaviv_gpu_match); 1903 1904 static int etnaviv_gpu_platform_probe(struct platform_device *pdev) 1905 { 1906 struct device *dev = &pdev->dev; 1907 struct etnaviv_gpu *gpu; 1908 int err; 1909 1910 gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL); 1911 if (!gpu) 1912 return -ENOMEM; 1913 1914 gpu->dev = dev; 1915 mutex_init(&gpu->lock); 1916 mutex_init(&gpu->sched_lock); 1917 1918 /* Map registers: */ 1919 gpu->mmio = devm_platform_ioremap_resource(pdev, 0); 1920 if (IS_ERR(gpu->mmio)) 1921 return PTR_ERR(gpu->mmio); 1922 1923 1924 /* Get Reset: */ 1925 gpu->rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); 1926 if (IS_ERR(gpu->rst)) 1927 return dev_err_probe(dev, PTR_ERR(gpu->rst), 1928 "failed to get reset\n"); 1929 1930 err = reset_control_assert(gpu->rst); 1931 if (err) 1932 return dev_err_probe(dev, err, "failed to assert reset\n"); 1933 1934 /* Get Interrupt: */ 1935 gpu->irq = platform_get_irq(pdev, 0); 1936 if (gpu->irq < 0) 1937 return gpu->irq; 1938 1939 err = devm_request_irq(dev, gpu->irq, irq_handler, 0, 1940 dev_name(dev), gpu); 1941 if (err) { 1942 dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err); 1943 return err; 1944 } 1945 1946 /* Get Clocks: */ 1947 gpu->clk_reg = devm_clk_get_optional(&pdev->dev, "reg"); 1948 DBG("clk_reg: %p", gpu->clk_reg); 1949 if (IS_ERR(gpu->clk_reg)) 1950 return PTR_ERR(gpu->clk_reg); 1951 1952 gpu->clk_bus = devm_clk_get_optional(&pdev->dev, "bus"); 1953 DBG("clk_bus: %p", gpu->clk_bus); 1954 if (IS_ERR(gpu->clk_bus)) 1955 return PTR_ERR(gpu->clk_bus); 1956 1957 gpu->clk_core = devm_clk_get(&pdev->dev, "core"); 1958 DBG("clk_core: %p", gpu->clk_core); 1959 if (IS_ERR(gpu->clk_core)) 1960 return PTR_ERR(gpu->clk_core); 1961 gpu->base_rate_core = clk_get_rate(gpu->clk_core); 1962 1963 gpu->clk_shader = devm_clk_get_optional(&pdev->dev, "shader"); 1964 DBG("clk_shader: %p", gpu->clk_shader); 1965 if (IS_ERR(gpu->clk_shader)) 1966 return PTR_ERR(gpu->clk_shader); 1967 gpu->base_rate_shader = clk_get_rate(gpu->clk_shader); 1968 1969 /* TODO: figure out max mapped size */ 1970 dev_set_drvdata(dev, gpu); 1971 1972 /* 1973 * We treat the device as initially suspended. The runtime PM 1974 * autosuspend delay is rather arbitary: no measurements have 1975 * yet been performed to determine an appropriate value. 1976 */ 1977 pm_runtime_use_autosuspend(dev); 1978 pm_runtime_set_autosuspend_delay(dev, 200); 1979 pm_runtime_enable(dev); 1980 1981 err = component_add(dev, &gpu_ops); 1982 if (err < 0) { 1983 dev_err(dev, "failed to register component: %d\n", err); 1984 return err; 1985 } 1986 1987 return 0; 1988 } 1989 1990 static void etnaviv_gpu_platform_remove(struct platform_device *pdev) 1991 { 1992 struct etnaviv_gpu *gpu = dev_get_drvdata(&pdev->dev); 1993 1994 component_del(&pdev->dev, &gpu_ops); 1995 pm_runtime_disable(&pdev->dev); 1996 1997 mutex_destroy(&gpu->lock); 1998 mutex_destroy(&gpu->sched_lock); 1999 } 2000 2001 static int etnaviv_gpu_rpm_suspend(struct device *dev) 2002 { 2003 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 2004 u32 idle, mask; 2005 2006 /* If there are any jobs in the HW queue, we're not idle */ 2007 if (atomic_read(&gpu->sched.credit_count)) 2008 return -EBUSY; 2009 2010 /* Check whether the hardware (except FE and MC) is idle */ 2011 mask = gpu->idle_mask & ~(VIVS_HI_IDLE_STATE_FE | 2012 VIVS_HI_IDLE_STATE_MC); 2013 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask; 2014 if (idle != mask) { 2015 dev_warn_ratelimited(dev, "GPU not yet idle, mask: 0x%08x\n", 2016 idle); 2017 return -EBUSY; 2018 } 2019 2020 etnaviv_gpu_hw_suspend(gpu); 2021 2022 gpu->state = ETNA_GPU_STATE_IDENTIFIED; 2023 2024 return etnaviv_gpu_clk_disable(gpu); 2025 } 2026 2027 static int etnaviv_gpu_rpm_resume(struct device *dev) 2028 { 2029 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 2030 int ret; 2031 2032 ret = etnaviv_gpu_clk_enable(gpu); 2033 if (ret) 2034 return ret; 2035 2036 /* Re-initialise the basic hardware state */ 2037 if (gpu->state == ETNA_GPU_STATE_IDENTIFIED) { 2038 ret = etnaviv_gpu_hw_resume(gpu); 2039 if (ret) { 2040 etnaviv_gpu_clk_disable(gpu); 2041 return ret; 2042 } 2043 } 2044 2045 return 0; 2046 } 2047 2048 static const struct dev_pm_ops etnaviv_gpu_pm_ops = { 2049 RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume, NULL) 2050 }; 2051 2052 struct platform_driver etnaviv_gpu_driver = { 2053 .driver = { 2054 .name = "etnaviv-gpu", 2055 .pm = pm_ptr(&etnaviv_gpu_pm_ops), 2056 .of_match_table = etnaviv_gpu_match, 2057 }, 2058 .probe = etnaviv_gpu_platform_probe, 2059 .remove = etnaviv_gpu_platform_remove, 2060 .id_table = gpu_ids, 2061 }; 2062