1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2015-2018 Etnaviv Project 4 */ 5 6 #include <linux/component.h> 7 #include <linux/dma-mapping.h> 8 #include <linux/module.h> 9 #include <linux/of_platform.h> 10 #include <linux/uaccess.h> 11 12 #include <drm/drm_debugfs.h> 13 #include <drm/drm_drv.h> 14 #include <drm/drm_file.h> 15 #include <drm/drm_ioctl.h> 16 #include <drm/drm_of.h> 17 #include <drm/drm_prime.h> 18 19 #include "etnaviv_cmdbuf.h" 20 #include "etnaviv_drv.h" 21 #include "etnaviv_gpu.h" 22 #include "etnaviv_gem.h" 23 #include "etnaviv_mmu.h" 24 #include "etnaviv_perfmon.h" 25 26 /* 27 * DRM operations: 28 */ 29 30 31 static void load_gpu(struct drm_device *dev) 32 { 33 struct etnaviv_drm_private *priv = dev->dev_private; 34 unsigned int i; 35 36 for (i = 0; i < ETNA_MAX_PIPES; i++) { 37 struct etnaviv_gpu *g = priv->gpu[i]; 38 39 if (g) { 40 int ret; 41 42 ret = etnaviv_gpu_init(g); 43 if (ret) 44 priv->gpu[i] = NULL; 45 } 46 } 47 } 48 49 static int etnaviv_open(struct drm_device *dev, struct drm_file *file) 50 { 51 struct etnaviv_drm_private *priv = dev->dev_private; 52 struct etnaviv_file_private *ctx; 53 int ret, i; 54 55 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 56 if (!ctx) 57 return -ENOMEM; 58 59 ret = xa_alloc_cyclic(&priv->active_contexts, &ctx->id, ctx, 60 xa_limit_32b, &priv->next_context_id, GFP_KERNEL); 61 if (ret < 0) 62 goto out_free; 63 64 ctx->mmu = etnaviv_iommu_context_init(priv->mmu_global, 65 priv->cmdbuf_suballoc); 66 if (!ctx->mmu) { 67 ret = -ENOMEM; 68 goto out_free; 69 } 70 71 for (i = 0; i < ETNA_MAX_PIPES; i++) { 72 struct etnaviv_gpu *gpu = priv->gpu[i]; 73 struct drm_gpu_scheduler *sched; 74 75 if (gpu) { 76 sched = &gpu->sched; 77 drm_sched_entity_init(&ctx->sched_entity[i], 78 DRM_SCHED_PRIORITY_NORMAL, &sched, 79 1, NULL); 80 } 81 } 82 83 file->driver_priv = ctx; 84 85 return 0; 86 87 out_free: 88 kfree(ctx); 89 return ret; 90 } 91 92 static void etnaviv_postclose(struct drm_device *dev, struct drm_file *file) 93 { 94 struct etnaviv_drm_private *priv = dev->dev_private; 95 struct etnaviv_file_private *ctx = file->driver_priv; 96 unsigned int i; 97 98 for (i = 0; i < ETNA_MAX_PIPES; i++) { 99 struct etnaviv_gpu *gpu = priv->gpu[i]; 100 101 if (gpu) 102 drm_sched_entity_destroy(&ctx->sched_entity[i]); 103 } 104 105 etnaviv_iommu_context_put(ctx->mmu); 106 107 xa_erase(&priv->active_contexts, ctx->id); 108 109 kfree(ctx); 110 } 111 112 /* 113 * DRM debugfs: 114 */ 115 116 #ifdef CONFIG_DEBUG_FS 117 static int etnaviv_gem_show(struct drm_device *dev, struct seq_file *m) 118 { 119 struct etnaviv_drm_private *priv = dev->dev_private; 120 121 etnaviv_gem_describe_objects(priv, m); 122 123 return 0; 124 } 125 126 static int etnaviv_mm_show(struct drm_device *dev, struct seq_file *m) 127 { 128 struct drm_printer p = drm_seq_file_printer(m); 129 130 read_lock(&dev->vma_offset_manager->vm_lock); 131 drm_mm_print(&dev->vma_offset_manager->vm_addr_space_mm, &p); 132 read_unlock(&dev->vma_offset_manager->vm_lock); 133 134 return 0; 135 } 136 137 static int etnaviv_mmu_show(struct etnaviv_gpu *gpu, struct seq_file *m) 138 { 139 struct drm_printer p = drm_seq_file_printer(m); 140 struct etnaviv_iommu_context *mmu_context; 141 142 seq_printf(m, "Active Objects (%s):\n", dev_name(gpu->dev)); 143 144 /* 145 * Lock the GPU to avoid a MMU context switch just now and elevate 146 * the refcount of the current context to avoid it disappearing from 147 * under our feet. 148 */ 149 mutex_lock(&gpu->lock); 150 mmu_context = gpu->mmu_context; 151 if (mmu_context) 152 etnaviv_iommu_context_get(mmu_context); 153 mutex_unlock(&gpu->lock); 154 155 if (!mmu_context) 156 return 0; 157 158 mutex_lock(&mmu_context->lock); 159 drm_mm_print(&mmu_context->mm, &p); 160 mutex_unlock(&mmu_context->lock); 161 162 etnaviv_iommu_context_put(mmu_context); 163 164 return 0; 165 } 166 167 static void etnaviv_buffer_dump(struct etnaviv_gpu *gpu, struct seq_file *m) 168 { 169 struct etnaviv_cmdbuf *buf = &gpu->buffer; 170 u32 size = buf->size; 171 u32 *ptr = buf->vaddr; 172 u32 i; 173 174 seq_printf(m, "virt %p - phys 0x%llx - free 0x%08x\n", 175 buf->vaddr, (u64)etnaviv_cmdbuf_get_pa(buf), 176 size - buf->user_size); 177 178 for (i = 0; i < size / 4; i++) { 179 if (i && !(i % 4)) 180 seq_puts(m, "\n"); 181 if (i % 4 == 0) 182 seq_printf(m, "\t0x%p: ", ptr + i); 183 seq_printf(m, "%08x ", *(ptr + i)); 184 } 185 seq_puts(m, "\n"); 186 } 187 188 static int etnaviv_ring_show(struct etnaviv_gpu *gpu, struct seq_file *m) 189 { 190 seq_printf(m, "Ring Buffer (%s): ", dev_name(gpu->dev)); 191 192 mutex_lock(&gpu->lock); 193 etnaviv_buffer_dump(gpu, m); 194 mutex_unlock(&gpu->lock); 195 196 return 0; 197 } 198 199 static int show_unlocked(struct seq_file *m, void *arg) 200 { 201 struct drm_info_node *node = (struct drm_info_node *) m->private; 202 struct drm_device *dev = node->minor->dev; 203 int (*show)(struct drm_device *dev, struct seq_file *m) = 204 node->info_ent->data; 205 206 return show(dev, m); 207 } 208 209 static int show_each_gpu(struct seq_file *m, void *arg) 210 { 211 struct drm_info_node *node = (struct drm_info_node *) m->private; 212 struct drm_device *dev = node->minor->dev; 213 struct etnaviv_drm_private *priv = dev->dev_private; 214 struct etnaviv_gpu *gpu; 215 int (*show)(struct etnaviv_gpu *gpu, struct seq_file *m) = 216 node->info_ent->data; 217 unsigned int i; 218 int ret = 0; 219 220 for (i = 0; i < ETNA_MAX_PIPES; i++) { 221 gpu = priv->gpu[i]; 222 if (!gpu) 223 continue; 224 225 ret = show(gpu, m); 226 if (ret < 0) 227 break; 228 } 229 230 return ret; 231 } 232 233 static struct drm_info_list etnaviv_debugfs_list[] = { 234 {"gpu", show_each_gpu, 0, etnaviv_gpu_debugfs}, 235 {"gem", show_unlocked, 0, etnaviv_gem_show}, 236 { "mm", show_unlocked, 0, etnaviv_mm_show }, 237 {"mmu", show_each_gpu, 0, etnaviv_mmu_show}, 238 {"ring", show_each_gpu, 0, etnaviv_ring_show}, 239 }; 240 241 static void etnaviv_debugfs_init(struct drm_minor *minor) 242 { 243 drm_debugfs_create_files(etnaviv_debugfs_list, 244 ARRAY_SIZE(etnaviv_debugfs_list), 245 minor->debugfs_root, minor); 246 } 247 #endif 248 249 /* 250 * DRM ioctls: 251 */ 252 253 static int etnaviv_ioctl_get_param(struct drm_device *dev, void *data, 254 struct drm_file *file) 255 { 256 struct etnaviv_drm_private *priv = dev->dev_private; 257 struct drm_etnaviv_param *args = data; 258 struct etnaviv_gpu *gpu; 259 260 if (args->pipe >= ETNA_MAX_PIPES) 261 return -EINVAL; 262 263 gpu = priv->gpu[args->pipe]; 264 if (!gpu) 265 return -ENXIO; 266 267 return etnaviv_gpu_get_param(gpu, args->param, &args->value); 268 } 269 270 static int etnaviv_ioctl_gem_new(struct drm_device *dev, void *data, 271 struct drm_file *file) 272 { 273 struct drm_etnaviv_gem_new *args = data; 274 275 if (args->flags & ~(ETNA_BO_CACHED | ETNA_BO_WC | ETNA_BO_UNCACHED | 276 ETNA_BO_FORCE_MMU)) 277 return -EINVAL; 278 279 return etnaviv_gem_new_handle(dev, file, args->size, 280 args->flags, &args->handle); 281 } 282 283 static int etnaviv_ioctl_gem_cpu_prep(struct drm_device *dev, void *data, 284 struct drm_file *file) 285 { 286 struct drm_etnaviv_gem_cpu_prep *args = data; 287 struct drm_gem_object *obj; 288 int ret; 289 290 if (args->op & ~(ETNA_PREP_READ | ETNA_PREP_WRITE | ETNA_PREP_NOSYNC)) 291 return -EINVAL; 292 293 obj = drm_gem_object_lookup(file, args->handle); 294 if (!obj) 295 return -ENOENT; 296 297 ret = etnaviv_gem_cpu_prep(obj, args->op, &args->timeout); 298 299 drm_gem_object_put(obj); 300 301 return ret; 302 } 303 304 static int etnaviv_ioctl_gem_cpu_fini(struct drm_device *dev, void *data, 305 struct drm_file *file) 306 { 307 struct drm_etnaviv_gem_cpu_fini *args = data; 308 struct drm_gem_object *obj; 309 int ret; 310 311 if (args->flags) 312 return -EINVAL; 313 314 obj = drm_gem_object_lookup(file, args->handle); 315 if (!obj) 316 return -ENOENT; 317 318 ret = etnaviv_gem_cpu_fini(obj); 319 320 drm_gem_object_put(obj); 321 322 return ret; 323 } 324 325 static int etnaviv_ioctl_gem_info(struct drm_device *dev, void *data, 326 struct drm_file *file) 327 { 328 struct drm_etnaviv_gem_info *args = data; 329 struct drm_gem_object *obj; 330 int ret; 331 332 if (args->pad) 333 return -EINVAL; 334 335 obj = drm_gem_object_lookup(file, args->handle); 336 if (!obj) 337 return -ENOENT; 338 339 ret = etnaviv_gem_mmap_offset(obj, &args->offset); 340 drm_gem_object_put(obj); 341 342 return ret; 343 } 344 345 static int etnaviv_ioctl_wait_fence(struct drm_device *dev, void *data, 346 struct drm_file *file) 347 { 348 struct drm_etnaviv_wait_fence *args = data; 349 struct etnaviv_drm_private *priv = dev->dev_private; 350 struct drm_etnaviv_timespec *timeout = &args->timeout; 351 struct etnaviv_gpu *gpu; 352 353 if (args->flags & ~(ETNA_WAIT_NONBLOCK)) 354 return -EINVAL; 355 356 if (args->pipe >= ETNA_MAX_PIPES) 357 return -EINVAL; 358 359 gpu = priv->gpu[args->pipe]; 360 if (!gpu) 361 return -ENXIO; 362 363 if (args->flags & ETNA_WAIT_NONBLOCK) 364 timeout = NULL; 365 366 return etnaviv_gpu_wait_fence_interruptible(gpu, args->fence, 367 timeout); 368 } 369 370 static int etnaviv_ioctl_gem_userptr(struct drm_device *dev, void *data, 371 struct drm_file *file) 372 { 373 struct drm_etnaviv_gem_userptr *args = data; 374 375 if (args->flags & ~(ETNA_USERPTR_READ|ETNA_USERPTR_WRITE) || 376 args->flags == 0) 377 return -EINVAL; 378 379 if (offset_in_page(args->user_ptr | args->user_size) || 380 (uintptr_t)args->user_ptr != args->user_ptr || 381 (u32)args->user_size != args->user_size || 382 args->user_ptr & ~PAGE_MASK) 383 return -EINVAL; 384 385 if (!access_ok((void __user *)(unsigned long)args->user_ptr, 386 args->user_size)) 387 return -EFAULT; 388 389 return etnaviv_gem_new_userptr(dev, file, args->user_ptr, 390 args->user_size, args->flags, 391 &args->handle); 392 } 393 394 static int etnaviv_ioctl_gem_wait(struct drm_device *dev, void *data, 395 struct drm_file *file) 396 { 397 struct etnaviv_drm_private *priv = dev->dev_private; 398 struct drm_etnaviv_gem_wait *args = data; 399 struct drm_etnaviv_timespec *timeout = &args->timeout; 400 struct drm_gem_object *obj; 401 struct etnaviv_gpu *gpu; 402 int ret; 403 404 if (args->flags & ~(ETNA_WAIT_NONBLOCK)) 405 return -EINVAL; 406 407 if (args->pipe >= ETNA_MAX_PIPES) 408 return -EINVAL; 409 410 gpu = priv->gpu[args->pipe]; 411 if (!gpu) 412 return -ENXIO; 413 414 obj = drm_gem_object_lookup(file, args->handle); 415 if (!obj) 416 return -ENOENT; 417 418 if (args->flags & ETNA_WAIT_NONBLOCK) 419 timeout = NULL; 420 421 ret = etnaviv_gem_wait_bo(gpu, obj, timeout); 422 423 drm_gem_object_put(obj); 424 425 return ret; 426 } 427 428 static int etnaviv_ioctl_pm_query_dom(struct drm_device *dev, void *data, 429 struct drm_file *file) 430 { 431 struct etnaviv_drm_private *priv = dev->dev_private; 432 struct drm_etnaviv_pm_domain *args = data; 433 struct etnaviv_gpu *gpu; 434 435 if (args->pipe >= ETNA_MAX_PIPES) 436 return -EINVAL; 437 438 gpu = priv->gpu[args->pipe]; 439 if (!gpu) 440 return -ENXIO; 441 442 return etnaviv_pm_query_dom(gpu, args); 443 } 444 445 static int etnaviv_ioctl_pm_query_sig(struct drm_device *dev, void *data, 446 struct drm_file *file) 447 { 448 struct etnaviv_drm_private *priv = dev->dev_private; 449 struct drm_etnaviv_pm_signal *args = data; 450 struct etnaviv_gpu *gpu; 451 452 if (args->pipe >= ETNA_MAX_PIPES) 453 return -EINVAL; 454 455 gpu = priv->gpu[args->pipe]; 456 if (!gpu) 457 return -ENXIO; 458 459 return etnaviv_pm_query_sig(gpu, args); 460 } 461 462 static const struct drm_ioctl_desc etnaviv_ioctls[] = { 463 #define ETNA_IOCTL(n, func, flags) \ 464 DRM_IOCTL_DEF_DRV(ETNAVIV_##n, etnaviv_ioctl_##func, flags) 465 ETNA_IOCTL(GET_PARAM, get_param, DRM_RENDER_ALLOW), 466 ETNA_IOCTL(GEM_NEW, gem_new, DRM_RENDER_ALLOW), 467 ETNA_IOCTL(GEM_INFO, gem_info, DRM_RENDER_ALLOW), 468 ETNA_IOCTL(GEM_CPU_PREP, gem_cpu_prep, DRM_RENDER_ALLOW), 469 ETNA_IOCTL(GEM_CPU_FINI, gem_cpu_fini, DRM_RENDER_ALLOW), 470 ETNA_IOCTL(GEM_SUBMIT, gem_submit, DRM_RENDER_ALLOW), 471 ETNA_IOCTL(WAIT_FENCE, wait_fence, DRM_RENDER_ALLOW), 472 ETNA_IOCTL(GEM_USERPTR, gem_userptr, DRM_RENDER_ALLOW), 473 ETNA_IOCTL(GEM_WAIT, gem_wait, DRM_RENDER_ALLOW), 474 ETNA_IOCTL(PM_QUERY_DOM, pm_query_dom, DRM_RENDER_ALLOW), 475 ETNA_IOCTL(PM_QUERY_SIG, pm_query_sig, DRM_RENDER_ALLOW), 476 }; 477 478 DEFINE_DRM_GEM_FOPS(fops); 479 480 static const struct drm_driver etnaviv_drm_driver = { 481 .driver_features = DRIVER_GEM | DRIVER_RENDER, 482 .open = etnaviv_open, 483 .postclose = etnaviv_postclose, 484 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 485 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 486 .gem_prime_import_sg_table = etnaviv_gem_prime_import_sg_table, 487 .gem_prime_mmap = drm_gem_prime_mmap, 488 #ifdef CONFIG_DEBUG_FS 489 .debugfs_init = etnaviv_debugfs_init, 490 #endif 491 .ioctls = etnaviv_ioctls, 492 .num_ioctls = DRM_ETNAVIV_NUM_IOCTLS, 493 .fops = &fops, 494 .name = "etnaviv", 495 .desc = "etnaviv DRM", 496 .date = "20151214", 497 .major = 1, 498 .minor = 3, 499 }; 500 501 /* 502 * Platform driver: 503 */ 504 static int etnaviv_bind(struct device *dev) 505 { 506 struct etnaviv_drm_private *priv; 507 struct drm_device *drm; 508 int ret; 509 510 drm = drm_dev_alloc(&etnaviv_drm_driver, dev); 511 if (IS_ERR(drm)) 512 return PTR_ERR(drm); 513 514 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 515 if (!priv) { 516 dev_err(dev, "failed to allocate private data\n"); 517 ret = -ENOMEM; 518 goto out_put; 519 } 520 drm->dev_private = priv; 521 522 dma_set_max_seg_size(dev, SZ_2G); 523 524 xa_init_flags(&priv->active_contexts, XA_FLAGS_ALLOC); 525 526 mutex_init(&priv->gem_lock); 527 INIT_LIST_HEAD(&priv->gem_list); 528 priv->num_gpus = 0; 529 priv->shm_gfp_mask = GFP_HIGHUSER | __GFP_RETRY_MAYFAIL | __GFP_NOWARN; 530 531 priv->cmdbuf_suballoc = etnaviv_cmdbuf_suballoc_new(drm->dev); 532 if (IS_ERR(priv->cmdbuf_suballoc)) { 533 dev_err(drm->dev, "Failed to create cmdbuf suballocator\n"); 534 ret = PTR_ERR(priv->cmdbuf_suballoc); 535 goto out_free_priv; 536 } 537 538 dev_set_drvdata(dev, drm); 539 540 ret = component_bind_all(dev, drm); 541 if (ret < 0) 542 goto out_destroy_suballoc; 543 544 load_gpu(drm); 545 546 ret = drm_dev_register(drm, 0); 547 if (ret) 548 goto out_unbind; 549 550 return 0; 551 552 out_unbind: 553 component_unbind_all(dev, drm); 554 out_destroy_suballoc: 555 etnaviv_cmdbuf_suballoc_destroy(priv->cmdbuf_suballoc); 556 out_free_priv: 557 kfree(priv); 558 out_put: 559 drm_dev_put(drm); 560 561 return ret; 562 } 563 564 static void etnaviv_unbind(struct device *dev) 565 { 566 struct drm_device *drm = dev_get_drvdata(dev); 567 struct etnaviv_drm_private *priv = drm->dev_private; 568 569 drm_dev_unregister(drm); 570 571 component_unbind_all(dev, drm); 572 573 etnaviv_cmdbuf_suballoc_destroy(priv->cmdbuf_suballoc); 574 575 xa_destroy(&priv->active_contexts); 576 577 drm->dev_private = NULL; 578 kfree(priv); 579 580 drm_dev_put(drm); 581 } 582 583 static const struct component_master_ops etnaviv_master_ops = { 584 .bind = etnaviv_bind, 585 .unbind = etnaviv_unbind, 586 }; 587 588 static int etnaviv_pdev_probe(struct platform_device *pdev) 589 { 590 struct device *dev = &pdev->dev; 591 struct device_node *first_node = NULL; 592 struct component_match *match = NULL; 593 594 if (!dev->platform_data) { 595 struct device_node *core_node; 596 597 for_each_compatible_node(core_node, NULL, "vivante,gc") { 598 if (!of_device_is_available(core_node)) 599 continue; 600 601 if (!first_node) 602 first_node = core_node; 603 604 drm_of_component_match_add(&pdev->dev, &match, 605 component_compare_of, core_node); 606 } 607 } else { 608 char **names = dev->platform_data; 609 unsigned i; 610 611 for (i = 0; names[i]; i++) 612 component_match_add(dev, &match, component_compare_dev_name, names[i]); 613 } 614 615 /* 616 * PTA and MTLB can have 40 bit base addresses, but 617 * unfortunately, an entry in the MTLB can only point to a 618 * 32 bit base address of a STLB. Moreover, to initialize the 619 * MMU we need a command buffer with a 32 bit address because 620 * without an MMU there is only an indentity mapping between 621 * the internal 32 bit addresses and the bus addresses. 622 * 623 * To make things easy, we set the dma_coherent_mask to 32 624 * bit to make sure we are allocating the command buffers and 625 * TLBs in the lower 4 GiB address space. 626 */ 627 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(40)) || 628 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32))) { 629 dev_dbg(&pdev->dev, "No suitable DMA available\n"); 630 return -ENODEV; 631 } 632 633 /* 634 * Apply the same DMA configuration to the virtual etnaviv 635 * device as the GPU we found. This assumes that all Vivante 636 * GPUs in the system share the same DMA constraints. 637 */ 638 if (first_node) 639 of_dma_configure(&pdev->dev, first_node, true); 640 641 return component_master_add_with_match(dev, &etnaviv_master_ops, match); 642 } 643 644 static int etnaviv_pdev_remove(struct platform_device *pdev) 645 { 646 component_master_del(&pdev->dev, &etnaviv_master_ops); 647 648 return 0; 649 } 650 651 static struct platform_driver etnaviv_platform_driver = { 652 .probe = etnaviv_pdev_probe, 653 .remove = etnaviv_pdev_remove, 654 .driver = { 655 .name = "etnaviv", 656 }, 657 }; 658 659 static struct platform_device *etnaviv_drm; 660 661 static int __init etnaviv_init(void) 662 { 663 struct platform_device *pdev; 664 int ret; 665 struct device_node *np; 666 667 etnaviv_validate_init(); 668 669 ret = platform_driver_register(&etnaviv_gpu_driver); 670 if (ret != 0) 671 return ret; 672 673 ret = platform_driver_register(&etnaviv_platform_driver); 674 if (ret != 0) 675 goto unregister_gpu_driver; 676 677 /* 678 * If the DT contains at least one available GPU device, instantiate 679 * the DRM platform device. 680 */ 681 for_each_compatible_node(np, NULL, "vivante,gc") { 682 if (!of_device_is_available(np)) 683 continue; 684 685 pdev = platform_device_alloc("etnaviv", PLATFORM_DEVID_NONE); 686 if (!pdev) { 687 ret = -ENOMEM; 688 of_node_put(np); 689 goto unregister_platform_driver; 690 } 691 692 ret = platform_device_add(pdev); 693 if (ret) { 694 platform_device_put(pdev); 695 of_node_put(np); 696 goto unregister_platform_driver; 697 } 698 699 etnaviv_drm = pdev; 700 of_node_put(np); 701 break; 702 } 703 704 return 0; 705 706 unregister_platform_driver: 707 platform_driver_unregister(&etnaviv_platform_driver); 708 unregister_gpu_driver: 709 platform_driver_unregister(&etnaviv_gpu_driver); 710 return ret; 711 } 712 module_init(etnaviv_init); 713 714 static void __exit etnaviv_exit(void) 715 { 716 platform_device_unregister(etnaviv_drm); 717 platform_driver_unregister(&etnaviv_platform_driver); 718 platform_driver_unregister(&etnaviv_gpu_driver); 719 } 720 module_exit(etnaviv_exit); 721 722 MODULE_AUTHOR("Christian Gmeiner <christian.gmeiner@gmail.com>"); 723 MODULE_AUTHOR("Russell King <rmk+kernel@armlinux.org.uk>"); 724 MODULE_AUTHOR("Lucas Stach <l.stach@pengutronix.de>"); 725 MODULE_DESCRIPTION("etnaviv DRM Driver"); 726 MODULE_LICENSE("GPL v2"); 727 MODULE_ALIAS("platform:etnaviv"); 728