xref: /linux/drivers/gpu/drm/etnaviv/etnaviv_cmdbuf.c (revision db82a0435b8be32d544bbed91c43c2f21b5f4ea7)
1f6ffbd4fSLucas Stach // SPDX-License-Identifier: GPL-2.0
2ea1f5729SLucas Stach /*
3f6ffbd4fSLucas Stach  * Copyright (C) 2017-2018 Etnaviv Project
4ea1f5729SLucas Stach  */
5ea1f5729SLucas Stach 
66eae41feSSam Ravnborg #include <linux/dma-mapping.h>
76eae41feSSam Ravnborg 
8e66774ddSLucas Stach #include <drm/drm_mm.h>
9e66774ddSLucas Stach 
10ea1f5729SLucas Stach #include "etnaviv_cmdbuf.h"
11*db82a043SLucas Stach #include "etnaviv_gem.h"
12ea1f5729SLucas Stach #include "etnaviv_gpu.h"
13ea1f5729SLucas Stach #include "etnaviv_mmu.h"
144fc3e66aSChristian Gmeiner #include "etnaviv_perfmon.h"
15ea1f5729SLucas Stach 
16e66774ddSLucas Stach #define SUBALLOC_SIZE		SZ_256K
17e66774ddSLucas Stach #define SUBALLOC_GRANULE	SZ_4K
18e66774ddSLucas Stach #define SUBALLOC_GRANULES	(SUBALLOC_SIZE / SUBALLOC_GRANULE)
19e66774ddSLucas Stach 
20e66774ddSLucas Stach struct etnaviv_cmdbuf_suballoc {
21e66774ddSLucas Stach 	/* suballocated dma buffer properties */
22e66774ddSLucas Stach 	struct etnaviv_gpu *gpu;
23e66774ddSLucas Stach 	void *vaddr;
24e66774ddSLucas Stach 	dma_addr_t paddr;
25e66774ddSLucas Stach 
26e66774ddSLucas Stach 	/* allocation management */
27e66774ddSLucas Stach 	struct mutex lock;
28e66774ddSLucas Stach 	DECLARE_BITMAP(granule_map, SUBALLOC_GRANULES);
29e66774ddSLucas Stach 	int free_space;
30e66774ddSLucas Stach 	wait_queue_head_t free_event;
31e66774ddSLucas Stach };
32e66774ddSLucas Stach 
33e66774ddSLucas Stach struct etnaviv_cmdbuf_suballoc *
34e66774ddSLucas Stach etnaviv_cmdbuf_suballoc_new(struct etnaviv_gpu * gpu)
35e66774ddSLucas Stach {
36e66774ddSLucas Stach 	struct etnaviv_cmdbuf_suballoc *suballoc;
37e66774ddSLucas Stach 	int ret;
38e66774ddSLucas Stach 
39e66774ddSLucas Stach 	suballoc = kzalloc(sizeof(*suballoc), GFP_KERNEL);
40e66774ddSLucas Stach 	if (!suballoc)
41e66774ddSLucas Stach 		return ERR_PTR(-ENOMEM);
42e66774ddSLucas Stach 
43e66774ddSLucas Stach 	suballoc->gpu = gpu;
44e66774ddSLucas Stach 	mutex_init(&suballoc->lock);
45e66774ddSLucas Stach 	init_waitqueue_head(&suballoc->free_event);
46e66774ddSLucas Stach 
47e66774ddSLucas Stach 	suballoc->vaddr = dma_alloc_wc(gpu->dev, SUBALLOC_SIZE,
48e66774ddSLucas Stach 				       &suballoc->paddr, GFP_KERNEL);
49c53ab613SLucas Stach 	if (!suballoc->vaddr) {
50c53ab613SLucas Stach 		ret = -ENOMEM;
51e66774ddSLucas Stach 		goto free_suballoc;
52c53ab613SLucas Stach 	}
53e66774ddSLucas Stach 
54e66774ddSLucas Stach 	return suballoc;
55e66774ddSLucas Stach 
56e66774ddSLucas Stach free_suballoc:
57e66774ddSLucas Stach 	kfree(suballoc);
58e66774ddSLucas Stach 
59c53ab613SLucas Stach 	return ERR_PTR(ret);
60e66774ddSLucas Stach }
61e66774ddSLucas Stach 
62*db82a043SLucas Stach int etnaviv_cmdbuf_suballoc_map(struct etnaviv_cmdbuf_suballoc *suballoc,
63*db82a043SLucas Stach 				struct etnaviv_iommu *mmu,
64*db82a043SLucas Stach 				struct etnaviv_vram_mapping *mapping,
65*db82a043SLucas Stach 				u32 memory_base)
66*db82a043SLucas Stach {
67*db82a043SLucas Stach 	return etnaviv_iommu_get_suballoc_va(mmu, mapping, memory_base,
68*db82a043SLucas Stach 					     suballoc->paddr, SUBALLOC_SIZE);
69*db82a043SLucas Stach }
70*db82a043SLucas Stach 
71*db82a043SLucas Stach void etnaviv_cmdbuf_suballoc_unmap(struct etnaviv_iommu *mmu,
72*db82a043SLucas Stach 				   struct etnaviv_vram_mapping *mapping)
73*db82a043SLucas Stach {
74*db82a043SLucas Stach 	etnaviv_iommu_put_suballoc_va(mmu, mapping);
75*db82a043SLucas Stach }
76*db82a043SLucas Stach 
77e66774ddSLucas Stach void etnaviv_cmdbuf_suballoc_destroy(struct etnaviv_cmdbuf_suballoc *suballoc)
78e66774ddSLucas Stach {
79e66774ddSLucas Stach 	dma_free_wc(suballoc->gpu->dev, SUBALLOC_SIZE, suballoc->vaddr,
80e66774ddSLucas Stach 		    suballoc->paddr);
81e66774ddSLucas Stach 	kfree(suballoc);
82e66774ddSLucas Stach }
83e66774ddSLucas Stach 
842f9225dbSLucas Stach int etnaviv_cmdbuf_init(struct etnaviv_cmdbuf_suballoc *suballoc,
852f9225dbSLucas Stach 			struct etnaviv_cmdbuf *cmdbuf, u32 size)
86ea1f5729SLucas Stach {
87e66774ddSLucas Stach 	int granule_offs, order, ret;
88ea1f5729SLucas Stach 
89e66774ddSLucas Stach 	cmdbuf->suballoc = suballoc;
90e66774ddSLucas Stach 	cmdbuf->size = size;
91ea1f5729SLucas Stach 
92e66774ddSLucas Stach 	order = order_base_2(ALIGN(size, SUBALLOC_GRANULE) / SUBALLOC_GRANULE);
93e66774ddSLucas Stach retry:
94e66774ddSLucas Stach 	mutex_lock(&suballoc->lock);
95e66774ddSLucas Stach 	granule_offs = bitmap_find_free_region(suballoc->granule_map,
96e66774ddSLucas Stach 					SUBALLOC_GRANULES, order);
97e66774ddSLucas Stach 	if (granule_offs < 0) {
98e66774ddSLucas Stach 		suballoc->free_space = 0;
99e66774ddSLucas Stach 		mutex_unlock(&suballoc->lock);
100e66774ddSLucas Stach 		ret = wait_event_interruptible_timeout(suballoc->free_event,
101e66774ddSLucas Stach 						       suballoc->free_space,
102e66774ddSLucas Stach 						       msecs_to_jiffies(10 * 1000));
103e66774ddSLucas Stach 		if (!ret) {
104e66774ddSLucas Stach 			dev_err(suballoc->gpu->dev,
105e66774ddSLucas Stach 				"Timeout waiting for cmdbuf space\n");
1062f9225dbSLucas Stach 			return -ETIMEDOUT;
107ea1f5729SLucas Stach 		}
108e66774ddSLucas Stach 		goto retry;
109e66774ddSLucas Stach 	}
110e66774ddSLucas Stach 	mutex_unlock(&suballoc->lock);
111e66774ddSLucas Stach 	cmdbuf->suballoc_offset = granule_offs * SUBALLOC_GRANULE;
112e66774ddSLucas Stach 	cmdbuf->vaddr = suballoc->vaddr + cmdbuf->suballoc_offset;
113ea1f5729SLucas Stach 
1142f9225dbSLucas Stach 	return 0;
115ea1f5729SLucas Stach }
116ea1f5729SLucas Stach 
117ea1f5729SLucas Stach void etnaviv_cmdbuf_free(struct etnaviv_cmdbuf *cmdbuf)
118ea1f5729SLucas Stach {
119e66774ddSLucas Stach 	struct etnaviv_cmdbuf_suballoc *suballoc = cmdbuf->suballoc;
120e66774ddSLucas Stach 	int order = order_base_2(ALIGN(cmdbuf->size, SUBALLOC_GRANULE) /
121e66774ddSLucas Stach 				 SUBALLOC_GRANULE);
122e66774ddSLucas Stach 
123e66774ddSLucas Stach 	mutex_lock(&suballoc->lock);
124e66774ddSLucas Stach 	bitmap_release_region(suballoc->granule_map,
125e66774ddSLucas Stach 			      cmdbuf->suballoc_offset / SUBALLOC_GRANULE,
126e66774ddSLucas Stach 			      order);
127e66774ddSLucas Stach 	suballoc->free_space = 1;
128e66774ddSLucas Stach 	mutex_unlock(&suballoc->lock);
129e66774ddSLucas Stach 	wake_up_all(&suballoc->free_event);
130ea1f5729SLucas Stach }
131c3ef4b8cSLucas Stach 
132*db82a043SLucas Stach u32 etnaviv_cmdbuf_get_va(struct etnaviv_cmdbuf *buf,
133*db82a043SLucas Stach 			  struct etnaviv_vram_mapping *mapping)
134c3ef4b8cSLucas Stach {
135*db82a043SLucas Stach 	return mapping->iova + buf->suballoc_offset;
136c3ef4b8cSLucas Stach }
1379912b4dbSLucas Stach 
1389912b4dbSLucas Stach dma_addr_t etnaviv_cmdbuf_get_pa(struct etnaviv_cmdbuf *buf)
1399912b4dbSLucas Stach {
140e66774ddSLucas Stach 	return buf->suballoc->paddr + buf->suballoc_offset;
1419912b4dbSLucas Stach }
142