xref: /linux/drivers/gpu/drm/etnaviv/common.xml.h (revision 53a2ebaaabc1eb8458796fec3bc1e0e80746b642)
1 #ifndef COMMON_XML
2 #define COMMON_XML
3 
4 /* Autogenerated file, DO NOT EDIT manually!
5 
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
9 
10 The rules-ng-ng source files this header was generated from are:
11 - state.xml     (  19930 bytes, from 2017-03-09 15:43:43)
12 - common.xml    (  23473 bytes, from 2017-03-09 15:43:43)
13 - state_hi.xml  (  26403 bytes, from 2017-03-09 15:43:43)
14 - copyright.xml (   1597 bytes, from 2016-12-08 16:37:56)
15 - state_2d.xml  (  51552 bytes, from 2016-12-08 16:37:56)
16 - state_3d.xml  (  66957 bytes, from 2017-03-09 15:43:43)
17 - state_vg.xml  (   5975 bytes, from 2016-12-08 16:37:56)
18 
19 Copyright (C) 2012-2017 by the following authors:
20 - Wladimir J. van der Laan <laanwj@gmail.com>
21 - Christian Gmeiner <christian.gmeiner@gmail.com>
22 - Lucas Stach <l.stach@pengutronix.de>
23 - Russell King <rmk@arm.linux.org.uk>
24 
25 Permission is hereby granted, free of charge, to any person obtaining a
26 copy of this software and associated documentation files (the "Software"),
27 to deal in the Software without restriction, including without limitation
28 the rights to use, copy, modify, merge, publish, distribute, sub license,
29 and/or sell copies of the Software, and to permit persons to whom the
30 Software is furnished to do so, subject to the following conditions:
31 
32 The above copyright notice and this permission notice (including the
33 next paragraph) shall be included in all copies or substantial portions
34 of the Software.
35 
36 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
37 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
38 FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
39 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
40 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
42 DEALINGS IN THE SOFTWARE.
43 */
44 
45 
46 #define PIPE_ID_PIPE_3D						0x00000000
47 #define PIPE_ID_PIPE_2D						0x00000001
48 #define SYNC_RECIPIENT_FE					0x00000001
49 #define SYNC_RECIPIENT_RA					0x00000005
50 #define SYNC_RECIPIENT_PE					0x00000007
51 #define SYNC_RECIPIENT_DE					0x0000000b
52 #define SYNC_RECIPIENT_VG					0x0000000f
53 #define SYNC_RECIPIENT_TESSELATOR				0x00000010
54 #define SYNC_RECIPIENT_VG2					0x00000011
55 #define SYNC_RECIPIENT_TESSELATOR2				0x00000012
56 #define SYNC_RECIPIENT_VG3					0x00000013
57 #define SYNC_RECIPIENT_TESSELATOR3				0x00000014
58 #define ENDIAN_MODE_NO_SWAP					0x00000000
59 #define ENDIAN_MODE_SWAP_16					0x00000001
60 #define ENDIAN_MODE_SWAP_32					0x00000002
61 #define chipModel_GC200						0x00000200
62 #define chipModel_GC300						0x00000300
63 #define chipModel_GC320						0x00000320
64 #define chipModel_GC328						0x00000328
65 #define chipModel_GC350						0x00000350
66 #define chipModel_GC355						0x00000355
67 #define chipModel_GC400						0x00000400
68 #define chipModel_GC410						0x00000410
69 #define chipModel_GC420						0x00000420
70 #define chipModel_GC428						0x00000428
71 #define chipModel_GC450						0x00000450
72 #define chipModel_GC500						0x00000500
73 #define chipModel_GC520						0x00000520
74 #define chipModel_GC530						0x00000530
75 #define chipModel_GC600						0x00000600
76 #define chipModel_GC700						0x00000700
77 #define chipModel_GC800						0x00000800
78 #define chipModel_GC860						0x00000860
79 #define chipModel_GC880						0x00000880
80 #define chipModel_GC1000					0x00001000
81 #define chipModel_GC1500					0x00001500
82 #define chipModel_GC2000					0x00002000
83 #define chipModel_GC2100					0x00002100
84 #define chipModel_GC2200					0x00002200
85 #define chipModel_GC2500					0x00002500
86 #define chipModel_GC3000					0x00003000
87 #define chipModel_GC4000					0x00004000
88 #define chipModel_GC5000					0x00005000
89 #define chipModel_GC5200					0x00005200
90 #define chipModel_GC6400					0x00006400
91 #define RGBA_BITS_R						0x00000001
92 #define RGBA_BITS_G						0x00000002
93 #define RGBA_BITS_B						0x00000004
94 #define RGBA_BITS_A						0x00000008
95 #define chipFeatures_FAST_CLEAR					0x00000001
96 #define chipFeatures_SPECIAL_ANTI_ALIASING			0x00000002
97 #define chipFeatures_PIPE_3D					0x00000004
98 #define chipFeatures_DXT_TEXTURE_COMPRESSION			0x00000008
99 #define chipFeatures_DEBUG_MODE					0x00000010
100 #define chipFeatures_Z_COMPRESSION				0x00000020
101 #define chipFeatures_YUV420_SCALER				0x00000040
102 #define chipFeatures_MSAA					0x00000080
103 #define chipFeatures_DC						0x00000100
104 #define chipFeatures_PIPE_2D					0x00000200
105 #define chipFeatures_ETC1_TEXTURE_COMPRESSION			0x00000400
106 #define chipFeatures_FAST_SCALER				0x00000800
107 #define chipFeatures_HIGH_DYNAMIC_RANGE				0x00001000
108 #define chipFeatures_YUV420_TILER				0x00002000
109 #define chipFeatures_MODULE_CG					0x00004000
110 #define chipFeatures_MIN_AREA					0x00008000
111 #define chipFeatures_NO_EARLY_Z					0x00010000
112 #define chipFeatures_NO_422_TEXTURE				0x00020000
113 #define chipFeatures_BUFFER_INTERLEAVING			0x00040000
114 #define chipFeatures_BYTE_WRITE_2D				0x00080000
115 #define chipFeatures_NO_SCALER					0x00100000
116 #define chipFeatures_YUY2_AVERAGING				0x00200000
117 #define chipFeatures_HALF_PE_CACHE				0x00400000
118 #define chipFeatures_HALF_TX_CACHE				0x00800000
119 #define chipFeatures_YUY2_RENDER_TARGET				0x01000000
120 #define chipFeatures_MEM32					0x02000000
121 #define chipFeatures_PIPE_VG					0x04000000
122 #define chipFeatures_VGTS					0x08000000
123 #define chipFeatures_FE20					0x10000000
124 #define chipFeatures_BYTE_WRITE_3D				0x20000000
125 #define chipFeatures_RS_YUV_TARGET				0x40000000
126 #define chipFeatures_32_BIT_INDICES				0x80000000
127 #define chipMinorFeatures0_FLIP_Y				0x00000001
128 #define chipMinorFeatures0_DUAL_RETURN_BUS			0x00000002
129 #define chipMinorFeatures0_ENDIANNESS_CONFIG			0x00000004
130 #define chipMinorFeatures0_TEXTURE_8K				0x00000008
131 #define chipMinorFeatures0_CORRECT_TEXTURE_CONVERTER		0x00000010
132 #define chipMinorFeatures0_SPECIAL_MSAA_LOD			0x00000020
133 #define chipMinorFeatures0_FAST_CLEAR_FLUSH			0x00000040
134 #define chipMinorFeatures0_2DPE20				0x00000080
135 #define chipMinorFeatures0_CORRECT_AUTO_DISABLE			0x00000100
136 #define chipMinorFeatures0_RENDERTARGET_8K			0x00000200
137 #define chipMinorFeatures0_2BITPERTILE				0x00000400
138 #define chipMinorFeatures0_SEPARATE_TILE_STATUS_WHEN_INTERLEAVED	0x00000800
139 #define chipMinorFeatures0_SUPER_TILED				0x00001000
140 #define chipMinorFeatures0_VG_20				0x00002000
141 #define chipMinorFeatures0_TS_EXTENDED_COMMANDS			0x00004000
142 #define chipMinorFeatures0_COMPRESSION_FIFO_FIXED		0x00008000
143 #define chipMinorFeatures0_HAS_SIGN_FLOOR_CEIL			0x00010000
144 #define chipMinorFeatures0_VG_FILTER				0x00020000
145 #define chipMinorFeatures0_VG_21				0x00040000
146 #define chipMinorFeatures0_SHADER_HAS_W				0x00080000
147 #define chipMinorFeatures0_HAS_SQRT_TRIG			0x00100000
148 #define chipMinorFeatures0_MORE_MINOR_FEATURES			0x00200000
149 #define chipMinorFeatures0_MC20					0x00400000
150 #define chipMinorFeatures0_MSAA_SIDEBAND			0x00800000
151 #define chipMinorFeatures0_BUG_FIXES0				0x01000000
152 #define chipMinorFeatures0_VAA					0x02000000
153 #define chipMinorFeatures0_BYPASS_IN_MSAA			0x04000000
154 #define chipMinorFeatures0_HZ					0x08000000
155 #define chipMinorFeatures0_NEW_TEXTURE				0x10000000
156 #define chipMinorFeatures0_2D_A8_TARGET				0x20000000
157 #define chipMinorFeatures0_CORRECT_STENCIL			0x40000000
158 #define chipMinorFeatures0_ENHANCE_VR				0x80000000
159 #define chipMinorFeatures1_RSUV_SWIZZLE				0x00000001
160 #define chipMinorFeatures1_V2_COMPRESSION			0x00000002
161 #define chipMinorFeatures1_VG_DOUBLE_BUFFER			0x00000004
162 #define chipMinorFeatures1_EXTRA_EVENT_STATES			0x00000008
163 #define chipMinorFeatures1_NO_STRIPING_NEEDED			0x00000010
164 #define chipMinorFeatures1_TEXTURE_STRIDE			0x00000020
165 #define chipMinorFeatures1_BUG_FIXES3				0x00000040
166 #define chipMinorFeatures1_AUTO_DISABLE				0x00000080
167 #define chipMinorFeatures1_AUTO_RESTART_TS			0x00000100
168 #define chipMinorFeatures1_DISABLE_PE_GATING			0x00000200
169 #define chipMinorFeatures1_L2_WINDOWING				0x00000400
170 #define chipMinorFeatures1_HALF_FLOAT				0x00000800
171 #define chipMinorFeatures1_PIXEL_DITHER				0x00001000
172 #define chipMinorFeatures1_TWO_STENCIL_REFERENCE		0x00002000
173 #define chipMinorFeatures1_EXTENDED_PIXEL_FORMAT		0x00004000
174 #define chipMinorFeatures1_CORRECT_MIN_MAX_DEPTH		0x00008000
175 #define chipMinorFeatures1_2D_DITHER				0x00010000
176 #define chipMinorFeatures1_BUG_FIXES5				0x00020000
177 #define chipMinorFeatures1_NEW_2D				0x00040000
178 #define chipMinorFeatures1_NEW_FP				0x00080000
179 #define chipMinorFeatures1_TEXTURE_HALIGN			0x00100000
180 #define chipMinorFeatures1_NON_POWER_OF_TWO			0x00200000
181 #define chipMinorFeatures1_LINEAR_TEXTURE_SUPPORT		0x00400000
182 #define chipMinorFeatures1_HALTI0				0x00800000
183 #define chipMinorFeatures1_CORRECT_OVERFLOW_VG			0x01000000
184 #define chipMinorFeatures1_NEGATIVE_LOG_FIX			0x02000000
185 #define chipMinorFeatures1_RESOLVE_OFFSET			0x04000000
186 #define chipMinorFeatures1_OK_TO_GATE_AXI_CLOCK			0x08000000
187 #define chipMinorFeatures1_MMU_VERSION				0x10000000
188 #define chipMinorFeatures1_WIDE_LINE				0x20000000
189 #define chipMinorFeatures1_BUG_FIXES6				0x40000000
190 #define chipMinorFeatures1_FC_FLUSH_STALL			0x80000000
191 #define chipMinorFeatures2_LINE_LOOP				0x00000001
192 #define chipMinorFeatures2_LOGIC_OP				0x00000002
193 #define chipMinorFeatures2_SEAMLESS_CUBE_MAP			0x00000004
194 #define chipMinorFeatures2_SUPERTILED_TEXTURE			0x00000008
195 #define chipMinorFeatures2_LINEAR_PE				0x00000010
196 #define chipMinorFeatures2_RECT_PRIMITIVE			0x00000020
197 #define chipMinorFeatures2_COMPOSITION				0x00000040
198 #define chipMinorFeatures2_CORRECT_AUTO_DISABLE_COUNT		0x00000080
199 #define chipMinorFeatures2_PE_SWIZZLE				0x00000100
200 #define chipMinorFeatures2_END_EVENT				0x00000200
201 #define chipMinorFeatures2_S1S8					0x00000400
202 #define chipMinorFeatures2_HALTI1				0x00000800
203 #define chipMinorFeatures2_RGB888				0x00001000
204 #define chipMinorFeatures2_TX__YUV_ASSEMBLER			0x00002000
205 #define chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING		0x00004000
206 #define chipMinorFeatures2_EXTRA_TEXTURE_STATE			0x00008000
207 #define chipMinorFeatures2_FULL_DIRECTFB			0x00010000
208 #define chipMinorFeatures2_2D_TILING				0x00020000
209 #define chipMinorFeatures2_THREAD_WALKER_IN_PS			0x00040000
210 #define chipMinorFeatures2_TILE_FILLER				0x00080000
211 #define chipMinorFeatures2_YUV_STANDARD				0x00100000
212 #define chipMinorFeatures2_2D_MULTI_SOURCE_BLIT			0x00200000
213 #define chipMinorFeatures2_YUV_CONVERSION			0x00400000
214 #define chipMinorFeatures2_FLUSH_FIXED_2D			0x00800000
215 #define chipMinorFeatures2_INTERLEAVER				0x01000000
216 #define chipMinorFeatures2_MIXED_STREAMS			0x02000000
217 #define chipMinorFeatures2_2D_420_L2CACHE			0x04000000
218 #define chipMinorFeatures2_BUG_FIXES7				0x08000000
219 #define chipMinorFeatures2_2D_NO_INDEX8_BRUSH			0x10000000
220 #define chipMinorFeatures2_TEXTURE_TILED_READ			0x20000000
221 #define chipMinorFeatures2_DECOMPRESS_Z16			0x40000000
222 #define chipMinorFeatures2_BUG_FIXES8				0x80000000
223 #define chipMinorFeatures3_ROTATION_STALL_FIX			0x00000001
224 #define chipMinorFeatures3_OCL_ONLY				0x00000002
225 #define chipMinorFeatures3_2D_MULTI_SOURCE_BLT_EX		0x00000004
226 #define chipMinorFeatures3_INSTRUCTION_CACHE			0x00000008
227 #define chipMinorFeatures3_GEOMETRY_SHADER			0x00000010
228 #define chipMinorFeatures3_TEX_COMPRESSION_SUPERTILED		0x00000020
229 #define chipMinorFeatures3_GENERICS				0x00000040
230 #define chipMinorFeatures3_BUG_FIXES9				0x00000080
231 #define chipMinorFeatures3_FAST_MSAA				0x00000100
232 #define chipMinorFeatures3_WCLIP				0x00000200
233 #define chipMinorFeatures3_BUG_FIXES10				0x00000400
234 #define chipMinorFeatures3_UNIFIED_SAMPLERS			0x00000800
235 #define chipMinorFeatures3_BUG_FIXES11				0x00001000
236 #define chipMinorFeatures3_PERFORMANCE_COUNTERS			0x00002000
237 #define chipMinorFeatures3_HAS_FAST_TRANSCENDENTALS		0x00004000
238 #define chipMinorFeatures3_BUG_FIXES12				0x00008000
239 #define chipMinorFeatures3_BUG_FIXES13				0x00010000
240 #define chipMinorFeatures3_DE_ENHANCEMENTS1			0x00020000
241 #define chipMinorFeatures3_ACE					0x00040000
242 #define chipMinorFeatures3_TX_ENHANCEMENTS1			0x00080000
243 #define chipMinorFeatures3_SH_ENHANCEMENTS1			0x00100000
244 #define chipMinorFeatures3_SH_ENHANCEMENTS2			0x00200000
245 #define chipMinorFeatures3_UNK22				0x00400000
246 #define chipMinorFeatures3_2D_FC_SOURCE				0x00800000
247 #define chipMinorFeatures3_UNK24				0x01000000
248 #define chipMinorFeatures3_UNK25				0x02000000
249 #define chipMinorFeatures3_NEW_HZ				0x04000000
250 #define chipMinorFeatures3_UNK27				0x08000000
251 #define chipMinorFeatures3_UNK28				0x10000000
252 #define chipMinorFeatures3_SH_ENHANCEMENTS3			0x20000000
253 #define chipMinorFeatures3_UNK30				0x40000000
254 #define chipMinorFeatures3_UNK31				0x80000000
255 #define chipMinorFeatures4_UNK0					0x00000001
256 #define chipMinorFeatures4_PE_ENHANCEMENTS2			0x00000002
257 #define chipMinorFeatures4_FRUSTUM_CLIP_FIX			0x00000004
258 #define chipMinorFeatures4_UNK3					0x00000008
259 #define chipMinorFeatures4_UNK4					0x00000010
260 #define chipMinorFeatures4_2D_GAMMA				0x00000020
261 #define chipMinorFeatures4_SINGLE_BUFFER			0x00000040
262 #define chipMinorFeatures4_UNK7					0x00000080
263 #define chipMinorFeatures4_UNK8					0x00000100
264 #define chipMinorFeatures4_UNK9					0x00000200
265 #define chipMinorFeatures4_UNK10				0x00000400
266 #define chipMinorFeatures4_TX_LERP_PRECISION_FIX		0x00000800
267 #define chipMinorFeatures4_2D_COLOR_SPACE_CONVERSION		0x00001000
268 #define chipMinorFeatures4_TEXTURE_ASTC				0x00002000
269 #define chipMinorFeatures4_UNK14				0x00004000
270 #define chipMinorFeatures4_UNK15				0x00008000
271 #define chipMinorFeatures4_HALTI2				0x00010000
272 #define chipMinorFeatures4_UNK17				0x00020000
273 #define chipMinorFeatures4_SMALL_MSAA				0x00040000
274 #define chipMinorFeatures4_UNK19				0x00080000
275 #define chipMinorFeatures4_NEW_RA				0x00100000
276 #define chipMinorFeatures4_2D_OPF_YUV_OUTPUT			0x00200000
277 #define chipMinorFeatures4_2D_MULTI_SOURCE_BLT_EX2		0x00400000
278 #define chipMinorFeatures4_NO_USER_CSC				0x00800000
279 #define chipMinorFeatures4_ZFIXES				0x01000000
280 #define chipMinorFeatures4_BUG_FIXES18				0x02000000
281 #define chipMinorFeatures4_2D_COMPRESSION			0x04000000
282 #define chipMinorFeatures4_PROBE				0x08000000
283 #define chipMinorFeatures4_UNK28				0x10000000
284 #define chipMinorFeatures4_2D_SUPER_TILE_VERSION		0x20000000
285 #define chipMinorFeatures4_UNK30				0x40000000
286 #define chipMinorFeatures4_UNK31				0x80000000
287 #define chipMinorFeatures5_UNK0					0x00000001
288 #define chipMinorFeatures5_UNK1					0x00000002
289 #define chipMinorFeatures5_UNK2					0x00000004
290 #define chipMinorFeatures5_UNK3					0x00000008
291 #define chipMinorFeatures5_EEZ					0x00000010
292 #define chipMinorFeatures5_UNK5					0x00000020
293 #define chipMinorFeatures5_UNK6					0x00000040
294 #define chipMinorFeatures5_UNK7					0x00000080
295 #define chipMinorFeatures5_UNK8					0x00000100
296 #define chipMinorFeatures5_HALTI3				0x00000200
297 #define chipMinorFeatures5_UNK10				0x00000400
298 #define chipMinorFeatures5_2D_ONE_PASS_FILTER_TAP		0x00000800
299 #define chipMinorFeatures5_UNK12				0x00001000
300 #define chipMinorFeatures5_SEPARATE_SRC_DST			0x00002000
301 #define chipMinorFeatures5_HALTI4				0x00004000
302 #define chipMinorFeatures5_UNK15				0x00008000
303 #define chipMinorFeatures5_ANDROID_ONLY				0x00010000
304 #define chipMinorFeatures5_HAS_PRODUCTID			0x00020000
305 #define chipMinorFeatures5_UNK18				0x00040000
306 #define chipMinorFeatures5_UNK19				0x00080000
307 #define chipMinorFeatures5_PE_DITHER_FIX2			0x00100000
308 #define chipMinorFeatures5_UNK21				0x00200000
309 #define chipMinorFeatures5_UNK22				0x00400000
310 #define chipMinorFeatures5_UNK23				0x00800000
311 #define chipMinorFeatures5_UNK24				0x01000000
312 #define chipMinorFeatures5_UNK25				0x02000000
313 #define chipMinorFeatures5_UNK26				0x04000000
314 #define chipMinorFeatures5_RS_DEPTHSTENCIL_NATIVE_SUPPORT	0x08000000
315 #define chipMinorFeatures5_V2_MSAA_COMP_FIX			0x10000000
316 #define chipMinorFeatures5_UNK29				0x20000000
317 #define chipMinorFeatures5_UNK30				0x40000000
318 #define chipMinorFeatures5_UNK31				0x80000000
319 
320 #endif /* COMMON_XML */
321