1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * MIPI Display Bus Interface (DBI) LCD controller support 4 * 5 * Copyright 2016 Noralf Trønnes 6 */ 7 8 #include <linux/backlight.h> 9 #include <linux/debugfs.h> 10 #include <linux/delay.h> 11 #include <linux/export.h> 12 #include <linux/gpio/consumer.h> 13 #include <linux/module.h> 14 #include <linux/regulator/consumer.h> 15 #include <linux/spi/spi.h> 16 17 #include <drm/drm_connector.h> 18 #include <drm/drm_damage_helper.h> 19 #include <drm/drm_drv.h> 20 #include <drm/drm_file.h> 21 #include <drm/drm_format_helper.h> 22 #include <drm/drm_fourcc.h> 23 #include <drm/drm_framebuffer.h> 24 #include <drm/drm_gem.h> 25 #include <drm/drm_gem_atomic_helper.h> 26 #include <drm/drm_gem_framebuffer_helper.h> 27 #include <drm/drm_mipi_dbi.h> 28 #include <drm/drm_modes.h> 29 #include <drm/drm_probe_helper.h> 30 #include <drm/drm_rect.h> 31 #include <video/mipi_display.h> 32 33 #define MIPI_DBI_MAX_SPI_READ_SPEED 2000000 /* 2MHz */ 34 35 #define DCS_POWER_MODE_DISPLAY BIT(2) 36 #define DCS_POWER_MODE_DISPLAY_NORMAL_MODE BIT(3) 37 #define DCS_POWER_MODE_SLEEP_MODE BIT(4) 38 #define DCS_POWER_MODE_PARTIAL_MODE BIT(5) 39 #define DCS_POWER_MODE_IDLE_MODE BIT(6) 40 #define DCS_POWER_MODE_RESERVED_MASK (BIT(0) | BIT(1) | BIT(7)) 41 42 /** 43 * DOC: overview 44 * 45 * This library provides helpers for MIPI Display Bus Interface (DBI) 46 * compatible display controllers. 47 * 48 * Many controllers for tiny lcd displays are MIPI compliant and can use this 49 * library. If a controller uses registers 0x2A and 0x2B to set the area to 50 * update and uses register 0x2C to write to frame memory, it is most likely 51 * MIPI compliant. 52 * 53 * Only MIPI Type 1 displays are supported since a full frame memory is needed. 54 * 55 * There are 3 MIPI DBI implementation types: 56 * 57 * A. Motorola 6800 type parallel bus 58 * 59 * B. Intel 8080 type parallel bus 60 * 61 * C. SPI type with 3 options: 62 * 63 * 1. 9-bit with the Data/Command signal as the ninth bit 64 * 2. Same as above except it's sent as 16 bits 65 * 3. 8-bit with the Data/Command signal as a separate D/CX pin 66 * 67 * Currently mipi_dbi only supports Type C options 1 and 3 with 68 * mipi_dbi_spi_init(). 69 */ 70 71 #define MIPI_DBI_DEBUG_COMMAND(cmd, data, len) \ 72 ({ \ 73 if (!len) \ 74 DRM_DEBUG_DRIVER("cmd=%02x\n", cmd); \ 75 else if (len <= 32) \ 76 DRM_DEBUG_DRIVER("cmd=%02x, par=%*ph\n", cmd, (int)len, data);\ 77 else \ 78 DRM_DEBUG_DRIVER("cmd=%02x, len=%zu\n", cmd, len); \ 79 }) 80 81 static const u8 mipi_dbi_dcs_read_commands[] = { 82 MIPI_DCS_GET_DISPLAY_ID, 83 MIPI_DCS_GET_RED_CHANNEL, 84 MIPI_DCS_GET_GREEN_CHANNEL, 85 MIPI_DCS_GET_BLUE_CHANNEL, 86 MIPI_DCS_GET_DISPLAY_STATUS, 87 MIPI_DCS_GET_POWER_MODE, 88 MIPI_DCS_GET_ADDRESS_MODE, 89 MIPI_DCS_GET_PIXEL_FORMAT, 90 MIPI_DCS_GET_DISPLAY_MODE, 91 MIPI_DCS_GET_SIGNAL_MODE, 92 MIPI_DCS_GET_DIAGNOSTIC_RESULT, 93 MIPI_DCS_READ_MEMORY_START, 94 MIPI_DCS_READ_MEMORY_CONTINUE, 95 MIPI_DCS_GET_SCANLINE, 96 MIPI_DCS_GET_DISPLAY_BRIGHTNESS, 97 MIPI_DCS_GET_CONTROL_DISPLAY, 98 MIPI_DCS_GET_POWER_SAVE, 99 MIPI_DCS_GET_CABC_MIN_BRIGHTNESS, 100 MIPI_DCS_READ_DDB_START, 101 MIPI_DCS_READ_DDB_CONTINUE, 102 0, /* sentinel */ 103 }; 104 105 static bool mipi_dbi_command_is_read(struct mipi_dbi *dbi, u8 cmd) 106 { 107 unsigned int i; 108 109 if (!dbi->read_commands) 110 return false; 111 112 for (i = 0; i < 0xff; i++) { 113 if (!dbi->read_commands[i]) 114 return false; 115 if (cmd == dbi->read_commands[i]) 116 return true; 117 } 118 119 return false; 120 } 121 122 /** 123 * mipi_dbi_command_read - MIPI DCS read command 124 * @dbi: MIPI DBI structure 125 * @cmd: Command 126 * @val: Value read 127 * 128 * Send MIPI DCS read command to the controller. 129 * 130 * Returns: 131 * Zero on success, negative error code on failure. 132 */ 133 int mipi_dbi_command_read(struct mipi_dbi *dbi, u8 cmd, u8 *val) 134 { 135 if (!dbi->read_commands) 136 return -EACCES; 137 138 if (!mipi_dbi_command_is_read(dbi, cmd)) 139 return -EINVAL; 140 141 return mipi_dbi_command_buf(dbi, cmd, val, 1); 142 } 143 EXPORT_SYMBOL(mipi_dbi_command_read); 144 145 /** 146 * mipi_dbi_command_buf - MIPI DCS command with parameter(s) in an array 147 * @dbi: MIPI DBI structure 148 * @cmd: Command 149 * @data: Parameter buffer 150 * @len: Buffer length 151 * 152 * Returns: 153 * Zero on success, negative error code on failure. 154 */ 155 int mipi_dbi_command_buf(struct mipi_dbi *dbi, u8 cmd, u8 *data, size_t len) 156 { 157 u8 *cmdbuf; 158 int ret; 159 160 /* SPI requires dma-safe buffers */ 161 cmdbuf = kmemdup(&cmd, 1, GFP_KERNEL); 162 if (!cmdbuf) 163 return -ENOMEM; 164 165 mutex_lock(&dbi->cmdlock); 166 ret = dbi->command(dbi, cmdbuf, data, len); 167 mutex_unlock(&dbi->cmdlock); 168 169 kfree(cmdbuf); 170 171 return ret; 172 } 173 EXPORT_SYMBOL(mipi_dbi_command_buf); 174 175 /* This should only be used by mipi_dbi_command() */ 176 int mipi_dbi_command_stackbuf(struct mipi_dbi *dbi, u8 cmd, const u8 *data, 177 size_t len) 178 { 179 u8 *buf; 180 int ret; 181 182 buf = kmemdup(data, len, GFP_KERNEL); 183 if (!buf) 184 return -ENOMEM; 185 186 ret = mipi_dbi_command_buf(dbi, cmd, buf, len); 187 188 kfree(buf); 189 190 return ret; 191 } 192 EXPORT_SYMBOL(mipi_dbi_command_stackbuf); 193 194 /** 195 * mipi_dbi_buf_copy - Copy a framebuffer, transforming it if necessary 196 * @dst: The destination buffer 197 * @src: The source buffer 198 * @fb: The source framebuffer 199 * @clip: Clipping rectangle of the area to be copied 200 * @swap: When true, swap MSB/LSB of 16-bit values 201 * @fmtcnv_state: Format-conversion state 202 * 203 * Returns: 204 * Zero on success, negative error code on failure. 205 */ 206 int mipi_dbi_buf_copy(void *dst, struct iosys_map *src, struct drm_framebuffer *fb, 207 struct drm_rect *clip, bool swap, 208 struct drm_format_conv_state *fmtcnv_state) 209 { 210 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(fb->dev); 211 struct drm_gem_object *gem = drm_gem_fb_get_obj(fb, 0); 212 struct iosys_map dst_map = IOSYS_MAP_INIT_VADDR(dst); 213 int ret; 214 215 ret = drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE); 216 if (ret) 217 return ret; 218 219 switch (fb->format->format) { 220 case DRM_FORMAT_RGB565: 221 if (swap) 222 drm_fb_swab(&dst_map, NULL, src, fb, clip, !drm_gem_is_imported(gem), 223 fmtcnv_state); 224 else 225 drm_fb_memcpy(&dst_map, NULL, src, fb, clip); 226 break; 227 case DRM_FORMAT_RGB888: 228 drm_fb_memcpy(&dst_map, NULL, src, fb, clip); 229 break; 230 case DRM_FORMAT_XRGB8888: 231 switch (dbidev->pixel_format) { 232 case DRM_FORMAT_RGB565: 233 if (swap) { 234 drm_fb_xrgb8888_to_rgb565be(&dst_map, NULL, src, fb, clip, 235 fmtcnv_state); 236 } else { 237 drm_fb_xrgb8888_to_rgb565(&dst_map, NULL, src, fb, clip, 238 fmtcnv_state); 239 } 240 break; 241 case DRM_FORMAT_RGB888: 242 drm_fb_xrgb8888_to_rgb888(&dst_map, NULL, src, fb, clip, fmtcnv_state); 243 break; 244 } 245 break; 246 default: 247 drm_err_once(fb->dev, "Format is not supported: %p4cc\n", 248 &fb->format->format); 249 ret = -EINVAL; 250 } 251 252 drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE); 253 254 return ret; 255 } 256 EXPORT_SYMBOL(mipi_dbi_buf_copy); 257 258 static void mipi_dbi_set_window_address(struct mipi_dbi_dev *dbidev, 259 unsigned int xs, unsigned int xe, 260 unsigned int ys, unsigned int ye) 261 { 262 struct mipi_dbi *dbi = &dbidev->dbi; 263 264 xs += dbidev->left_offset; 265 xe += dbidev->left_offset; 266 ys += dbidev->top_offset; 267 ye += dbidev->top_offset; 268 269 mipi_dbi_command(dbi, MIPI_DCS_SET_COLUMN_ADDRESS, (xs >> 8) & 0xff, 270 xs & 0xff, (xe >> 8) & 0xff, xe & 0xff); 271 mipi_dbi_command(dbi, MIPI_DCS_SET_PAGE_ADDRESS, (ys >> 8) & 0xff, 272 ys & 0xff, (ye >> 8) & 0xff, ye & 0xff); 273 } 274 275 static void mipi_dbi_fb_dirty(struct iosys_map *src, struct drm_framebuffer *fb, 276 struct drm_rect *rect, struct drm_format_conv_state *fmtcnv_state) 277 { 278 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(fb->dev); 279 unsigned int height = rect->y2 - rect->y1; 280 unsigned int width = rect->x2 - rect->x1; 281 const struct drm_format_info *dst_format; 282 struct mipi_dbi *dbi = &dbidev->dbi; 283 bool swap = dbi->swap_bytes; 284 int ret = 0; 285 size_t len; 286 bool full; 287 void *tr; 288 289 full = width == fb->width && height == fb->height; 290 291 DRM_DEBUG_KMS("Flushing [FB:%d] " DRM_RECT_FMT "\n", fb->base.id, DRM_RECT_ARG(rect)); 292 293 if (!dbi->dc || !full || swap || 294 fb->format->format == DRM_FORMAT_XRGB8888) { 295 tr = dbidev->tx_buf; 296 ret = mipi_dbi_buf_copy(tr, src, fb, rect, swap, fmtcnv_state); 297 if (ret) 298 goto err_msg; 299 } else { 300 tr = src->vaddr; /* TODO: Use mapping abstraction properly */ 301 } 302 303 mipi_dbi_set_window_address(dbidev, rect->x1, rect->x2 - 1, rect->y1, 304 rect->y2 - 1); 305 306 if (fb->format->format == DRM_FORMAT_XRGB8888) 307 dst_format = drm_format_info(dbidev->pixel_format); 308 else 309 dst_format = fb->format; 310 len = drm_format_info_min_pitch(dst_format, 0, width) * height; 311 312 ret = mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START, tr, len); 313 err_msg: 314 if (ret) 315 drm_err_once(fb->dev, "Failed to update display %d\n", ret); 316 } 317 318 /** 319 * mipi_dbi_pipe_mode_valid - MIPI DBI mode-valid helper 320 * @pipe: Simple display pipe 321 * @mode: The mode to test 322 * 323 * This function validates a given display mode against the MIPI DBI's hardware 324 * display. Drivers can use this as their &drm_simple_display_pipe_funcs->mode_valid 325 * callback. 326 */ 327 enum drm_mode_status mipi_dbi_pipe_mode_valid(struct drm_simple_display_pipe *pipe, 328 const struct drm_display_mode *mode) 329 { 330 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev); 331 332 return drm_crtc_helper_mode_valid_fixed(&pipe->crtc, mode, &dbidev->mode); 333 } 334 EXPORT_SYMBOL(mipi_dbi_pipe_mode_valid); 335 336 /** 337 * mipi_dbi_pipe_update - Display pipe update helper 338 * @pipe: Simple display pipe 339 * @old_state: Old plane state 340 * 341 * This function handles framebuffer flushing and vblank events. Drivers can use 342 * this as their &drm_simple_display_pipe_funcs->update callback. 343 */ 344 void mipi_dbi_pipe_update(struct drm_simple_display_pipe *pipe, 345 struct drm_plane_state *old_state) 346 { 347 struct drm_plane_state *state = pipe->plane.state; 348 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(state); 349 struct drm_framebuffer *fb = state->fb; 350 struct drm_rect rect; 351 int idx; 352 353 if (!pipe->crtc.state->active) 354 return; 355 356 if (WARN_ON(!fb)) 357 return; 358 359 if (!drm_dev_enter(fb->dev, &idx)) 360 return; 361 362 if (drm_atomic_helper_damage_merged(old_state, state, &rect)) 363 mipi_dbi_fb_dirty(&shadow_plane_state->data[0], fb, &rect, 364 &shadow_plane_state->fmtcnv_state); 365 366 drm_dev_exit(idx); 367 } 368 EXPORT_SYMBOL(mipi_dbi_pipe_update); 369 370 /** 371 * mipi_dbi_enable_flush - MIPI DBI enable helper 372 * @dbidev: MIPI DBI device structure 373 * @crtc_state: CRTC state 374 * @plane_state: Plane state 375 * 376 * Flushes the whole framebuffer and enables the backlight. Drivers can use this 377 * in their &drm_simple_display_pipe_funcs->enable callback. 378 * 379 * Note: Drivers which don't use mipi_dbi_pipe_update() because they have custom 380 * framebuffer flushing, can't use this function since they both use the same 381 * flushing code. 382 */ 383 void mipi_dbi_enable_flush(struct mipi_dbi_dev *dbidev, 384 struct drm_crtc_state *crtc_state, 385 struct drm_plane_state *plane_state) 386 { 387 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state); 388 struct drm_framebuffer *fb = plane_state->fb; 389 struct drm_rect rect = { 390 .x1 = 0, 391 .x2 = fb->width, 392 .y1 = 0, 393 .y2 = fb->height, 394 }; 395 int idx; 396 397 if (!drm_dev_enter(&dbidev->drm, &idx)) 398 return; 399 400 mipi_dbi_fb_dirty(&shadow_plane_state->data[0], fb, &rect, 401 &shadow_plane_state->fmtcnv_state); 402 backlight_enable(dbidev->backlight); 403 404 drm_dev_exit(idx); 405 } 406 EXPORT_SYMBOL(mipi_dbi_enable_flush); 407 408 static void mipi_dbi_blank(struct mipi_dbi_dev *dbidev) 409 { 410 struct drm_device *drm = &dbidev->drm; 411 u16 height = drm->mode_config.min_height; 412 u16 width = drm->mode_config.min_width; 413 struct mipi_dbi *dbi = &dbidev->dbi; 414 const struct drm_format_info *dst_format; 415 size_t len; 416 int idx; 417 418 if (!drm_dev_enter(drm, &idx)) 419 return; 420 421 dst_format = drm_format_info(dbidev->pixel_format); 422 len = drm_format_info_min_pitch(dst_format, 0, width) * height; 423 424 memset(dbidev->tx_buf, 0, len); 425 426 mipi_dbi_set_window_address(dbidev, 0, width - 1, 0, height - 1); 427 mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START, 428 (u8 *)dbidev->tx_buf, len); 429 430 drm_dev_exit(idx); 431 } 432 433 /** 434 * mipi_dbi_pipe_disable - MIPI DBI pipe disable helper 435 * @pipe: Display pipe 436 * 437 * This function disables backlight if present, if not the display memory is 438 * blanked. The regulator is disabled if in use. Drivers can use this as their 439 * &drm_simple_display_pipe_funcs->disable callback. 440 */ 441 void mipi_dbi_pipe_disable(struct drm_simple_display_pipe *pipe) 442 { 443 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev); 444 445 DRM_DEBUG_KMS("\n"); 446 447 if (dbidev->backlight) 448 backlight_disable(dbidev->backlight); 449 else 450 mipi_dbi_blank(dbidev); 451 452 if (dbidev->regulator) 453 regulator_disable(dbidev->regulator); 454 if (dbidev->io_regulator) 455 regulator_disable(dbidev->io_regulator); 456 } 457 EXPORT_SYMBOL(mipi_dbi_pipe_disable); 458 459 /** 460 * mipi_dbi_pipe_begin_fb_access - MIPI DBI pipe begin-access helper 461 * @pipe: Display pipe 462 * @plane_state: Plane state 463 * 464 * This function implements struct &drm_simple_display_funcs.begin_fb_access. 465 * 466 * See drm_gem_begin_shadow_fb_access() for details and mipi_dbi_pipe_cleanup_fb() 467 * for cleanup. 468 * 469 * Returns: 470 * 0 on success, or a negative errno code otherwise. 471 */ 472 int mipi_dbi_pipe_begin_fb_access(struct drm_simple_display_pipe *pipe, 473 struct drm_plane_state *plane_state) 474 { 475 return drm_gem_begin_shadow_fb_access(&pipe->plane, plane_state); 476 } 477 EXPORT_SYMBOL(mipi_dbi_pipe_begin_fb_access); 478 479 /** 480 * mipi_dbi_pipe_end_fb_access - MIPI DBI pipe end-access helper 481 * @pipe: Display pipe 482 * @plane_state: Plane state 483 * 484 * This function implements struct &drm_simple_display_funcs.end_fb_access. 485 * 486 * See mipi_dbi_pipe_begin_fb_access(). 487 */ 488 void mipi_dbi_pipe_end_fb_access(struct drm_simple_display_pipe *pipe, 489 struct drm_plane_state *plane_state) 490 { 491 drm_gem_end_shadow_fb_access(&pipe->plane, plane_state); 492 } 493 EXPORT_SYMBOL(mipi_dbi_pipe_end_fb_access); 494 495 /** 496 * mipi_dbi_pipe_reset_plane - MIPI DBI plane-reset helper 497 * @pipe: Display pipe 498 * 499 * This function implements struct &drm_simple_display_funcs.reset_plane 500 * for MIPI DBI planes. 501 */ 502 void mipi_dbi_pipe_reset_plane(struct drm_simple_display_pipe *pipe) 503 { 504 drm_gem_reset_shadow_plane(&pipe->plane); 505 } 506 EXPORT_SYMBOL(mipi_dbi_pipe_reset_plane); 507 508 /** 509 * mipi_dbi_pipe_duplicate_plane_state - duplicates MIPI DBI plane state 510 * @pipe: Display pipe 511 * 512 * This function implements struct &drm_simple_display_funcs.duplicate_plane_state 513 * for MIPI DBI planes. 514 * 515 * See drm_gem_duplicate_shadow_plane_state() for additional details. 516 * 517 * Returns: 518 * A pointer to a new plane state on success, or NULL otherwise. 519 */ 520 struct drm_plane_state *mipi_dbi_pipe_duplicate_plane_state(struct drm_simple_display_pipe *pipe) 521 { 522 return drm_gem_duplicate_shadow_plane_state(&pipe->plane); 523 } 524 EXPORT_SYMBOL(mipi_dbi_pipe_duplicate_plane_state); 525 526 /** 527 * mipi_dbi_pipe_destroy_plane_state - cleans up MIPI DBI plane state 528 * @pipe: Display pipe 529 * @plane_state: Plane state 530 * 531 * This function implements struct drm_simple_display_funcs.destroy_plane_state 532 * for MIPI DBI planes. 533 * 534 * See drm_gem_destroy_shadow_plane_state() for additional details. 535 */ 536 void mipi_dbi_pipe_destroy_plane_state(struct drm_simple_display_pipe *pipe, 537 struct drm_plane_state *plane_state) 538 { 539 drm_gem_destroy_shadow_plane_state(&pipe->plane, plane_state); 540 } 541 EXPORT_SYMBOL(mipi_dbi_pipe_destroy_plane_state); 542 543 static int mipi_dbi_connector_get_modes(struct drm_connector *connector) 544 { 545 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(connector->dev); 546 547 return drm_connector_helper_get_modes_fixed(connector, &dbidev->mode); 548 } 549 550 static const struct drm_connector_helper_funcs mipi_dbi_connector_hfuncs = { 551 .get_modes = mipi_dbi_connector_get_modes, 552 }; 553 554 static const struct drm_connector_funcs mipi_dbi_connector_funcs = { 555 .reset = drm_atomic_helper_connector_reset, 556 .fill_modes = drm_helper_probe_single_connector_modes, 557 .destroy = drm_connector_cleanup, 558 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 559 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 560 }; 561 562 static int mipi_dbi_rotate_mode(struct drm_display_mode *mode, 563 unsigned int rotation) 564 { 565 if (rotation == 0 || rotation == 180) { 566 return 0; 567 } else if (rotation == 90 || rotation == 270) { 568 swap(mode->hdisplay, mode->vdisplay); 569 swap(mode->hsync_start, mode->vsync_start); 570 swap(mode->hsync_end, mode->vsync_end); 571 swap(mode->htotal, mode->vtotal); 572 swap(mode->width_mm, mode->height_mm); 573 return 0; 574 } else { 575 return -EINVAL; 576 } 577 } 578 579 static const struct drm_mode_config_funcs mipi_dbi_mode_config_funcs = { 580 .fb_create = drm_gem_fb_create_with_dirty, 581 .atomic_check = drm_atomic_helper_check, 582 .atomic_commit = drm_atomic_helper_commit, 583 }; 584 585 static const uint32_t mipi_dbi_formats[] = { 586 DRM_FORMAT_RGB565, 587 DRM_FORMAT_XRGB8888, 588 }; 589 590 /** 591 * mipi_dbi_dev_init_with_formats - MIPI DBI device initialization with custom formats 592 * @dbidev: MIPI DBI device structure to initialize 593 * @funcs: Display pipe functions 594 * @formats: Array of supported formats (DRM_FORMAT\_\*). 595 * @format_count: Number of elements in @formats 596 * @mode: Display mode 597 * @rotation: Initial rotation in degrees Counter Clock Wise 598 * @tx_buf_size: Allocate a transmit buffer of this size. 599 * 600 * This function sets up a &drm_simple_display_pipe with a &drm_connector that 601 * has one fixed &drm_display_mode which is rotated according to @rotation. 602 * This mode is used to set the mode config min/max width/height properties. 603 * 604 * Use mipi_dbi_dev_init() if you want native RGB565 and emulated XRGB8888 format. 605 * 606 * Note: 607 * Some of the helper functions expects RGB565 to be the default format and the 608 * transmit buffer sized to fit that. 609 * 610 * Returns: 611 * Zero on success, negative error code on failure. 612 */ 613 int mipi_dbi_dev_init_with_formats(struct mipi_dbi_dev *dbidev, 614 const struct drm_simple_display_pipe_funcs *funcs, 615 const uint32_t *formats, unsigned int format_count, 616 const struct drm_display_mode *mode, 617 unsigned int rotation, size_t tx_buf_size) 618 { 619 static const uint64_t modifiers[] = { 620 DRM_FORMAT_MOD_LINEAR, 621 DRM_FORMAT_MOD_INVALID 622 }; 623 struct drm_device *drm = &dbidev->drm; 624 int ret; 625 626 if (!dbidev->dbi.command) 627 return -EINVAL; 628 629 ret = drmm_mode_config_init(drm); 630 if (ret) 631 return ret; 632 633 dbidev->tx_buf = devm_kmalloc(drm->dev, tx_buf_size, GFP_KERNEL); 634 if (!dbidev->tx_buf) 635 return -ENOMEM; 636 637 drm_mode_copy(&dbidev->mode, mode); 638 ret = mipi_dbi_rotate_mode(&dbidev->mode, rotation); 639 if (ret) { 640 DRM_ERROR("Illegal rotation value %u\n", rotation); 641 return -EINVAL; 642 } 643 644 drm_connector_helper_add(&dbidev->connector, &mipi_dbi_connector_hfuncs); 645 ret = drm_connector_init(drm, &dbidev->connector, &mipi_dbi_connector_funcs, 646 DRM_MODE_CONNECTOR_SPI); 647 if (ret) 648 return ret; 649 650 ret = drm_simple_display_pipe_init(drm, &dbidev->pipe, funcs, formats, format_count, 651 modifiers, &dbidev->connector); 652 if (ret) 653 return ret; 654 655 drm_plane_enable_fb_damage_clips(&dbidev->pipe.plane); 656 657 drm->mode_config.funcs = &mipi_dbi_mode_config_funcs; 658 drm->mode_config.min_width = dbidev->mode.hdisplay; 659 drm->mode_config.max_width = dbidev->mode.hdisplay; 660 drm->mode_config.min_height = dbidev->mode.vdisplay; 661 drm->mode_config.max_height = dbidev->mode.vdisplay; 662 dbidev->rotation = rotation; 663 dbidev->pixel_format = formats[0]; 664 if (formats[0] == DRM_FORMAT_RGB888) 665 dbidev->dbi.write_memory_bpw = 8; 666 667 DRM_DEBUG_KMS("rotation = %u\n", rotation); 668 669 return 0; 670 } 671 EXPORT_SYMBOL(mipi_dbi_dev_init_with_formats); 672 673 /** 674 * mipi_dbi_dev_init - MIPI DBI device initialization 675 * @dbidev: MIPI DBI device structure to initialize 676 * @funcs: Display pipe functions 677 * @mode: Display mode 678 * @rotation: Initial rotation in degrees Counter Clock Wise 679 * 680 * This function sets up a &drm_simple_display_pipe with a &drm_connector that 681 * has one fixed &drm_display_mode which is rotated according to @rotation. 682 * This mode is used to set the mode config min/max width/height properties. 683 * Additionally &mipi_dbi.tx_buf is allocated. 684 * 685 * Supported formats: Native RGB565 and emulated XRGB8888. 686 * 687 * Returns: 688 * Zero on success, negative error code on failure. 689 */ 690 int mipi_dbi_dev_init(struct mipi_dbi_dev *dbidev, 691 const struct drm_simple_display_pipe_funcs *funcs, 692 const struct drm_display_mode *mode, unsigned int rotation) 693 { 694 size_t bufsize = mode->vdisplay * mode->hdisplay * sizeof(u16); 695 696 dbidev->drm.mode_config.preferred_depth = 16; 697 698 return mipi_dbi_dev_init_with_formats(dbidev, funcs, mipi_dbi_formats, 699 ARRAY_SIZE(mipi_dbi_formats), mode, 700 rotation, bufsize); 701 } 702 EXPORT_SYMBOL(mipi_dbi_dev_init); 703 704 /** 705 * mipi_dbi_hw_reset - Hardware reset of controller 706 * @dbi: MIPI DBI structure 707 * 708 * Reset controller if the &mipi_dbi->reset gpio is set. 709 */ 710 void mipi_dbi_hw_reset(struct mipi_dbi *dbi) 711 { 712 if (!dbi->reset) 713 return; 714 715 gpiod_set_value_cansleep(dbi->reset, 0); 716 usleep_range(20, 1000); 717 gpiod_set_value_cansleep(dbi->reset, 1); 718 msleep(120); 719 } 720 EXPORT_SYMBOL(mipi_dbi_hw_reset); 721 722 /** 723 * mipi_dbi_display_is_on - Check if display is on 724 * @dbi: MIPI DBI structure 725 * 726 * This function checks the Power Mode register (if readable) to see if 727 * display output is turned on. This can be used to see if the bootloader 728 * has already turned on the display avoiding flicker when the pipeline is 729 * enabled. 730 * 731 * Returns: 732 * true if the display can be verified to be on, false otherwise. 733 */ 734 bool mipi_dbi_display_is_on(struct mipi_dbi *dbi) 735 { 736 u8 val; 737 738 if (mipi_dbi_command_read(dbi, MIPI_DCS_GET_POWER_MODE, &val)) 739 return false; 740 741 val &= ~DCS_POWER_MODE_RESERVED_MASK; 742 743 /* The poweron/reset value is 08h DCS_POWER_MODE_DISPLAY_NORMAL_MODE */ 744 if (val != (DCS_POWER_MODE_DISPLAY | 745 DCS_POWER_MODE_DISPLAY_NORMAL_MODE | DCS_POWER_MODE_SLEEP_MODE)) 746 return false; 747 748 DRM_DEBUG_DRIVER("Display is ON\n"); 749 750 return true; 751 } 752 EXPORT_SYMBOL(mipi_dbi_display_is_on); 753 754 static int mipi_dbi_poweron_reset_conditional(struct mipi_dbi_dev *dbidev, bool cond) 755 { 756 struct device *dev = dbidev->drm.dev; 757 struct mipi_dbi *dbi = &dbidev->dbi; 758 int ret; 759 760 if (dbidev->regulator) { 761 ret = regulator_enable(dbidev->regulator); 762 if (ret) { 763 DRM_DEV_ERROR(dev, "Failed to enable regulator (%d)\n", ret); 764 return ret; 765 } 766 } 767 768 if (dbidev->io_regulator) { 769 ret = regulator_enable(dbidev->io_regulator); 770 if (ret) { 771 DRM_DEV_ERROR(dev, "Failed to enable I/O regulator (%d)\n", ret); 772 if (dbidev->regulator) 773 regulator_disable(dbidev->regulator); 774 return ret; 775 } 776 } 777 778 if (cond && mipi_dbi_display_is_on(dbi)) 779 return 1; 780 781 mipi_dbi_hw_reset(dbi); 782 ret = mipi_dbi_command(dbi, MIPI_DCS_SOFT_RESET); 783 if (ret) { 784 DRM_DEV_ERROR(dev, "Failed to send reset command (%d)\n", ret); 785 if (dbidev->regulator) 786 regulator_disable(dbidev->regulator); 787 if (dbidev->io_regulator) 788 regulator_disable(dbidev->io_regulator); 789 return ret; 790 } 791 792 /* 793 * If we did a hw reset, we know the controller is in Sleep mode and 794 * per MIPI DSC spec should wait 5ms after soft reset. If we didn't, 795 * we assume worst case and wait 120ms. 796 */ 797 if (dbi->reset) 798 usleep_range(5000, 20000); 799 else 800 msleep(120); 801 802 return 0; 803 } 804 805 /** 806 * mipi_dbi_poweron_reset - MIPI DBI poweron and reset 807 * @dbidev: MIPI DBI device structure 808 * 809 * This function enables the regulator if used and does a hardware and software 810 * reset. 811 * 812 * Returns: 813 * Zero on success, or a negative error code. 814 */ 815 int mipi_dbi_poweron_reset(struct mipi_dbi_dev *dbidev) 816 { 817 return mipi_dbi_poweron_reset_conditional(dbidev, false); 818 } 819 EXPORT_SYMBOL(mipi_dbi_poweron_reset); 820 821 /** 822 * mipi_dbi_poweron_conditional_reset - MIPI DBI poweron and conditional reset 823 * @dbidev: MIPI DBI device structure 824 * 825 * This function enables the regulator if used and if the display is off, it 826 * does a hardware and software reset. If mipi_dbi_display_is_on() determines 827 * that the display is on, no reset is performed. 828 * 829 * Returns: 830 * Zero if the controller was reset, 1 if the display was already on, or a 831 * negative error code. 832 */ 833 int mipi_dbi_poweron_conditional_reset(struct mipi_dbi_dev *dbidev) 834 { 835 return mipi_dbi_poweron_reset_conditional(dbidev, true); 836 } 837 EXPORT_SYMBOL(mipi_dbi_poweron_conditional_reset); 838 839 #if IS_ENABLED(CONFIG_SPI) 840 841 /** 842 * mipi_dbi_spi_cmd_max_speed - get the maximum SPI bus speed 843 * @spi: SPI device 844 * @len: The transfer buffer length. 845 * 846 * Many controllers have a max speed of 10MHz, but can be pushed way beyond 847 * that. Increase reliability by running pixel data at max speed and the rest 848 * at 10MHz, preventing transfer glitches from messing up the init settings. 849 */ 850 u32 mipi_dbi_spi_cmd_max_speed(struct spi_device *spi, size_t len) 851 { 852 if (len > 64) 853 return 0; /* use default */ 854 855 return min_t(u32, 10000000, spi->max_speed_hz); 856 } 857 EXPORT_SYMBOL(mipi_dbi_spi_cmd_max_speed); 858 859 /* 860 * MIPI DBI Type C Option 1 861 * 862 * If the SPI controller doesn't have 9 bits per word support, 863 * use blocks of 9 bytes to send 8x 9-bit words using a 8-bit SPI transfer. 864 * Pad partial blocks with MIPI_DCS_NOP (zero). 865 * This is how the D/C bit (x) is added: 866 * x7654321 867 * 0x765432 868 * 10x76543 869 * 210x7654 870 * 3210x765 871 * 43210x76 872 * 543210x7 873 * 6543210x 874 * 76543210 875 */ 876 877 static int mipi_dbi_spi1e_transfer(struct mipi_dbi *dbi, int dc, 878 const void *buf, size_t len, 879 unsigned int bpw) 880 { 881 bool swap_bytes = (bpw == 16); 882 size_t chunk, max_chunk = dbi->tx_buf9_len; 883 struct spi_device *spi = dbi->spi; 884 struct spi_transfer tr = { 885 .tx_buf = dbi->tx_buf9, 886 .bits_per_word = 8, 887 }; 888 struct spi_message m; 889 const u8 *src = buf; 890 int i, ret; 891 u8 *dst; 892 893 if (drm_debug_enabled(DRM_UT_DRIVER)) 894 pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n", 895 __func__, dc, max_chunk); 896 897 tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len); 898 spi_message_init_with_transfers(&m, &tr, 1); 899 900 if (!dc) { 901 if (WARN_ON_ONCE(len != 1)) 902 return -EINVAL; 903 904 /* Command: pad no-op's (zeroes) at beginning of block */ 905 dst = dbi->tx_buf9; 906 memset(dst, 0, 9); 907 dst[8] = *src; 908 tr.len = 9; 909 910 return spi_sync(spi, &m); 911 } 912 913 /* max with room for adding one bit per byte */ 914 max_chunk = max_chunk / 9 * 8; 915 /* but no bigger than len */ 916 max_chunk = min(max_chunk, len); 917 /* 8 byte blocks */ 918 max_chunk = max_t(size_t, 8, max_chunk & ~0x7); 919 920 while (len) { 921 size_t added = 0; 922 923 chunk = min(len, max_chunk); 924 len -= chunk; 925 dst = dbi->tx_buf9; 926 927 if (chunk < 8) { 928 u8 val, carry = 0; 929 930 /* Data: pad no-op's (zeroes) at end of block */ 931 memset(dst, 0, 9); 932 933 if (swap_bytes) { 934 for (i = 1; i < (chunk + 1); i++) { 935 val = src[1]; 936 *dst++ = carry | BIT(8 - i) | (val >> i); 937 carry = val << (8 - i); 938 i++; 939 val = src[0]; 940 *dst++ = carry | BIT(8 - i) | (val >> i); 941 carry = val << (8 - i); 942 src += 2; 943 } 944 *dst++ = carry; 945 } else { 946 for (i = 1; i < (chunk + 1); i++) { 947 val = *src++; 948 *dst++ = carry | BIT(8 - i) | (val >> i); 949 carry = val << (8 - i); 950 } 951 *dst++ = carry; 952 } 953 954 chunk = 8; 955 added = 1; 956 } else { 957 for (i = 0; i < chunk; i += 8) { 958 if (swap_bytes) { 959 *dst++ = BIT(7) | (src[1] >> 1); 960 *dst++ = (src[1] << 7) | BIT(6) | (src[0] >> 2); 961 *dst++ = (src[0] << 6) | BIT(5) | (src[3] >> 3); 962 *dst++ = (src[3] << 5) | BIT(4) | (src[2] >> 4); 963 *dst++ = (src[2] << 4) | BIT(3) | (src[5] >> 5); 964 *dst++ = (src[5] << 3) | BIT(2) | (src[4] >> 6); 965 *dst++ = (src[4] << 2) | BIT(1) | (src[7] >> 7); 966 *dst++ = (src[7] << 1) | BIT(0); 967 *dst++ = src[6]; 968 } else { 969 *dst++ = BIT(7) | (src[0] >> 1); 970 *dst++ = (src[0] << 7) | BIT(6) | (src[1] >> 2); 971 *dst++ = (src[1] << 6) | BIT(5) | (src[2] >> 3); 972 *dst++ = (src[2] << 5) | BIT(4) | (src[3] >> 4); 973 *dst++ = (src[3] << 4) | BIT(3) | (src[4] >> 5); 974 *dst++ = (src[4] << 3) | BIT(2) | (src[5] >> 6); 975 *dst++ = (src[5] << 2) | BIT(1) | (src[6] >> 7); 976 *dst++ = (src[6] << 1) | BIT(0); 977 *dst++ = src[7]; 978 } 979 980 src += 8; 981 added++; 982 } 983 } 984 985 tr.len = chunk + added; 986 987 ret = spi_sync(spi, &m); 988 if (ret) 989 return ret; 990 } 991 992 return 0; 993 } 994 995 static int mipi_dbi_spi1_transfer(struct mipi_dbi *dbi, int dc, 996 const void *buf, size_t len, 997 unsigned int bpw) 998 { 999 struct spi_device *spi = dbi->spi; 1000 struct spi_transfer tr = { 1001 .bits_per_word = 9, 1002 }; 1003 const u16 *src16 = buf; 1004 const u8 *src8 = buf; 1005 struct spi_message m; 1006 size_t max_chunk; 1007 u16 *dst16; 1008 int ret; 1009 1010 if (!spi_is_bpw_supported(spi, 9)) 1011 return mipi_dbi_spi1e_transfer(dbi, dc, buf, len, bpw); 1012 1013 tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len); 1014 max_chunk = dbi->tx_buf9_len; 1015 dst16 = dbi->tx_buf9; 1016 1017 if (drm_debug_enabled(DRM_UT_DRIVER)) 1018 pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n", 1019 __func__, dc, max_chunk); 1020 1021 max_chunk = min(max_chunk / 2, len); 1022 1023 spi_message_init_with_transfers(&m, &tr, 1); 1024 tr.tx_buf = dst16; 1025 1026 while (len) { 1027 size_t chunk = min(len, max_chunk); 1028 unsigned int i; 1029 1030 if (bpw == 16) { 1031 for (i = 0; i < (chunk * 2); i += 2) { 1032 dst16[i] = *src16 >> 8; 1033 dst16[i + 1] = *src16++ & 0xFF; 1034 if (dc) { 1035 dst16[i] |= 0x0100; 1036 dst16[i + 1] |= 0x0100; 1037 } 1038 } 1039 } else { 1040 for (i = 0; i < chunk; i++) { 1041 dst16[i] = *src8++; 1042 if (dc) 1043 dst16[i] |= 0x0100; 1044 } 1045 } 1046 1047 tr.len = chunk * 2; 1048 len -= chunk; 1049 1050 ret = spi_sync(spi, &m); 1051 if (ret) 1052 return ret; 1053 } 1054 1055 return 0; 1056 } 1057 1058 static int mipi_dbi_typec1_command_read(struct mipi_dbi *dbi, u8 *cmd, 1059 u8 *data, size_t len) 1060 { 1061 struct spi_device *spi = dbi->spi; 1062 u32 speed_hz = min_t(u32, MIPI_DBI_MAX_SPI_READ_SPEED, 1063 spi->max_speed_hz / 2); 1064 struct spi_transfer tr[2] = { 1065 { 1066 .speed_hz = speed_hz, 1067 .bits_per_word = 9, 1068 .tx_buf = dbi->tx_buf9, 1069 .len = 2, 1070 }, { 1071 .speed_hz = speed_hz, 1072 .bits_per_word = 8, 1073 .len = len, 1074 .rx_buf = data, 1075 }, 1076 }; 1077 struct spi_message m; 1078 u16 *dst16; 1079 int ret; 1080 1081 if (!len) 1082 return -EINVAL; 1083 1084 if (!spi_is_bpw_supported(spi, 9)) { 1085 /* 1086 * FIXME: implement something like mipi_dbi_spi1e_transfer() but 1087 * for reads using emulation. 1088 */ 1089 dev_err(&spi->dev, 1090 "reading on host not supporting 9 bpw not yet implemented\n"); 1091 return -EOPNOTSUPP; 1092 } 1093 1094 /* 1095 * Turn the 8bit command into a 16bit version of the command in the 1096 * buffer. Only 9 bits of this will be used when executing the actual 1097 * transfer. 1098 */ 1099 dst16 = dbi->tx_buf9; 1100 dst16[0] = *cmd; 1101 1102 spi_message_init_with_transfers(&m, tr, ARRAY_SIZE(tr)); 1103 ret = spi_sync(spi, &m); 1104 1105 if (!ret) 1106 MIPI_DBI_DEBUG_COMMAND(*cmd, data, len); 1107 1108 return ret; 1109 } 1110 1111 static int mipi_dbi_typec1_command(struct mipi_dbi *dbi, u8 *cmd, 1112 u8 *parameters, size_t num) 1113 { 1114 unsigned int bpw = 8; 1115 int ret; 1116 1117 if (mipi_dbi_command_is_read(dbi, *cmd)) 1118 return mipi_dbi_typec1_command_read(dbi, cmd, parameters, num); 1119 1120 MIPI_DBI_DEBUG_COMMAND(*cmd, parameters, num); 1121 1122 ret = mipi_dbi_spi1_transfer(dbi, 0, cmd, 1, 8); 1123 if (ret || !num) 1124 return ret; 1125 1126 if (*cmd == MIPI_DCS_WRITE_MEMORY_START) 1127 bpw = dbi->write_memory_bpw; 1128 1129 return mipi_dbi_spi1_transfer(dbi, 1, parameters, num, bpw); 1130 } 1131 1132 /* MIPI DBI Type C Option 3 */ 1133 1134 static int mipi_dbi_typec3_command_read(struct mipi_dbi *dbi, u8 *cmd, 1135 u8 *data, size_t len) 1136 { 1137 struct spi_device *spi = dbi->spi; 1138 u32 speed_hz = min_t(u32, MIPI_DBI_MAX_SPI_READ_SPEED, 1139 spi->max_speed_hz / 2); 1140 struct spi_transfer tr[2] = { 1141 { 1142 .speed_hz = speed_hz, 1143 .tx_buf = cmd, 1144 .len = 1, 1145 }, { 1146 .speed_hz = speed_hz, 1147 .len = len, 1148 }, 1149 }; 1150 struct spi_message m; 1151 u8 *buf; 1152 int ret; 1153 1154 if (!len) 1155 return -EINVAL; 1156 1157 /* 1158 * Support non-standard 24-bit and 32-bit Nokia read commands which 1159 * start with a dummy clock, so we need to read an extra byte. 1160 */ 1161 if (*cmd == MIPI_DCS_GET_DISPLAY_ID || 1162 *cmd == MIPI_DCS_GET_DISPLAY_STATUS) { 1163 if (!(len == 3 || len == 4)) 1164 return -EINVAL; 1165 1166 tr[1].len = len + 1; 1167 } 1168 1169 buf = kmalloc(tr[1].len, GFP_KERNEL); 1170 if (!buf) 1171 return -ENOMEM; 1172 1173 tr[1].rx_buf = buf; 1174 1175 spi_bus_lock(spi->controller); 1176 gpiod_set_value_cansleep(dbi->dc, 0); 1177 1178 spi_message_init_with_transfers(&m, tr, ARRAY_SIZE(tr)); 1179 ret = spi_sync_locked(spi, &m); 1180 spi_bus_unlock(spi->controller); 1181 if (ret) 1182 goto err_free; 1183 1184 if (tr[1].len == len) { 1185 memcpy(data, buf, len); 1186 } else { 1187 unsigned int i; 1188 1189 for (i = 0; i < len; i++) 1190 data[i] = (buf[i] << 1) | (buf[i + 1] >> 7); 1191 } 1192 1193 MIPI_DBI_DEBUG_COMMAND(*cmd, data, len); 1194 1195 err_free: 1196 kfree(buf); 1197 1198 return ret; 1199 } 1200 1201 static int mipi_dbi_typec3_command(struct mipi_dbi *dbi, u8 *cmd, 1202 u8 *par, size_t num) 1203 { 1204 struct spi_device *spi = dbi->spi; 1205 unsigned int bpw = 8; 1206 u32 speed_hz; 1207 int ret; 1208 1209 if (mipi_dbi_command_is_read(dbi, *cmd)) 1210 return mipi_dbi_typec3_command_read(dbi, cmd, par, num); 1211 1212 MIPI_DBI_DEBUG_COMMAND(*cmd, par, num); 1213 1214 spi_bus_lock(spi->controller); 1215 gpiod_set_value_cansleep(dbi->dc, 0); 1216 speed_hz = mipi_dbi_spi_cmd_max_speed(spi, 1); 1217 ret = mipi_dbi_spi_transfer(spi, speed_hz, 8, cmd, 1); 1218 spi_bus_unlock(spi->controller); 1219 if (ret || !num) 1220 return ret; 1221 1222 if (*cmd == MIPI_DCS_WRITE_MEMORY_START) 1223 bpw = dbi->write_memory_bpw; 1224 1225 spi_bus_lock(spi->controller); 1226 gpiod_set_value_cansleep(dbi->dc, 1); 1227 speed_hz = mipi_dbi_spi_cmd_max_speed(spi, num); 1228 ret = mipi_dbi_spi_transfer(spi, speed_hz, bpw, par, num); 1229 spi_bus_unlock(spi->controller); 1230 1231 return ret; 1232 } 1233 1234 /** 1235 * mipi_dbi_spi_init - Initialize MIPI DBI SPI interface 1236 * @spi: SPI device 1237 * @dbi: MIPI DBI structure to initialize 1238 * @dc: D/C gpio (optional) 1239 * 1240 * This function sets &mipi_dbi->command, enables &mipi_dbi->read_commands for the 1241 * usual read commands. It should be followed by a call to mipi_dbi_dev_init() or 1242 * a driver-specific init. 1243 * 1244 * If @dc is set, a Type C Option 3 interface is assumed, if not 1245 * Type C Option 1. 1246 * 1247 * If the command is %MIPI_DCS_WRITE_MEMORY_START and the pixel format is RGB565, endianness has 1248 * to be taken into account. The MIPI DBI serial interface is big endian and framebuffers are 1249 * assumed stored in memory as little endian (%DRM_FORMAT_BIG_ENDIAN is not supported). 1250 * 1251 * This is how endianness is handled: 1252 * 1253 * Option 1 (D/C as a bit): The buffer is sent on the wire byte by byte so the 16-bit buffer is 1254 * byteswapped before transfer. 1255 * 1256 * Option 3 (D/C as a gpio): If the SPI controller supports 16 bits per word the buffer can be 1257 * sent as-is. If not the caller is responsible for swapping the bytes 1258 * before calling mipi_dbi_command_buf() and the buffer is sent 8 bpw. 1259 * 1260 * This handling is optimised for %DRM_FORMAT_RGB565 framebuffers. 1261 * 1262 * If the interface is Option 1 and the SPI controller doesn't support 9 bits per word, 1263 * the buffer is sent as 9x 8-bit words, padded with MIPI DCS no-op commands if necessary. 1264 * 1265 * Returns: 1266 * Zero on success, negative error code on failure. 1267 */ 1268 int mipi_dbi_spi_init(struct spi_device *spi, struct mipi_dbi *dbi, 1269 struct gpio_desc *dc) 1270 { 1271 struct device *dev = &spi->dev; 1272 int ret; 1273 1274 /* 1275 * Even though it's not the SPI device that does DMA (the master does), 1276 * the dma mask is necessary for the dma_alloc_wc() in the GEM code 1277 * (e.g., drm_gem_dma_create()). The dma_addr returned will be a physical 1278 * address which might be different from the bus address, but this is 1279 * not a problem since the address will not be used. 1280 * The virtual address is used in the transfer and the SPI core 1281 * re-maps it on the SPI master device using the DMA streaming API 1282 * (spi_map_buf()). 1283 */ 1284 if (!dev->coherent_dma_mask) { 1285 ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32)); 1286 if (ret) { 1287 dev_warn(dev, "Failed to set dma mask %d\n", ret); 1288 return ret; 1289 } 1290 } 1291 1292 dbi->spi = spi; 1293 dbi->read_commands = mipi_dbi_dcs_read_commands; 1294 dbi->write_memory_bpw = 16; 1295 1296 if (dc) { 1297 dbi->command = mipi_dbi_typec3_command; 1298 dbi->dc = dc; 1299 if (!spi_is_bpw_supported(spi, 16)) { 1300 dbi->write_memory_bpw = 8; 1301 dbi->swap_bytes = true; 1302 } 1303 } else { 1304 dbi->command = mipi_dbi_typec1_command; 1305 dbi->tx_buf9_len = SZ_16K; 1306 dbi->tx_buf9 = devm_kmalloc(dev, dbi->tx_buf9_len, GFP_KERNEL); 1307 if (!dbi->tx_buf9) 1308 return -ENOMEM; 1309 } 1310 1311 mutex_init(&dbi->cmdlock); 1312 1313 DRM_DEBUG_DRIVER("SPI speed: %uMHz\n", spi->max_speed_hz / 1000000); 1314 1315 return 0; 1316 } 1317 EXPORT_SYMBOL(mipi_dbi_spi_init); 1318 1319 /** 1320 * mipi_dbi_spi_transfer - SPI transfer helper 1321 * @spi: SPI device 1322 * @speed_hz: Override speed (optional) 1323 * @bpw: Bits per word 1324 * @buf: Buffer to transfer 1325 * @len: Buffer length 1326 * 1327 * This SPI transfer helper breaks up the transfer of @buf into chunks which 1328 * the SPI controller driver can handle. The SPI bus must be locked when 1329 * calling this. 1330 * 1331 * Returns: 1332 * Zero on success, negative error code on failure. 1333 */ 1334 int mipi_dbi_spi_transfer(struct spi_device *spi, u32 speed_hz, 1335 u8 bpw, const void *buf, size_t len) 1336 { 1337 size_t max_chunk = spi_max_transfer_size(spi); 1338 struct spi_transfer tr = { 1339 .bits_per_word = bpw, 1340 .speed_hz = speed_hz, 1341 }; 1342 struct spi_message m; 1343 size_t chunk; 1344 int ret; 1345 1346 /* In __spi_validate, there's a validation that no partial transfers 1347 * are accepted (xfer->len % w_size must be zero). 1348 * Here we align max_chunk to multiple of 2 (16bits), 1349 * to prevent transfers from being rejected. 1350 */ 1351 max_chunk = ALIGN_DOWN(max_chunk, 2); 1352 1353 spi_message_init_with_transfers(&m, &tr, 1); 1354 1355 while (len) { 1356 chunk = min(len, max_chunk); 1357 1358 tr.tx_buf = buf; 1359 tr.len = chunk; 1360 buf += chunk; 1361 len -= chunk; 1362 1363 ret = spi_sync_locked(spi, &m); 1364 if (ret) 1365 return ret; 1366 } 1367 1368 return 0; 1369 } 1370 EXPORT_SYMBOL(mipi_dbi_spi_transfer); 1371 1372 #endif /* CONFIG_SPI */ 1373 1374 #ifdef CONFIG_DEBUG_FS 1375 1376 static ssize_t mipi_dbi_debugfs_command_write(struct file *file, 1377 const char __user *ubuf, 1378 size_t count, loff_t *ppos) 1379 { 1380 struct seq_file *m = file->private_data; 1381 struct mipi_dbi_dev *dbidev = m->private; 1382 u8 val, cmd = 0, parameters[64]; 1383 char *buf, *pos, *token; 1384 int i, ret, idx; 1385 1386 if (!drm_dev_enter(&dbidev->drm, &idx)) 1387 return -ENODEV; 1388 1389 buf = memdup_user_nul(ubuf, count); 1390 if (IS_ERR(buf)) { 1391 ret = PTR_ERR(buf); 1392 goto err_exit; 1393 } 1394 1395 /* strip trailing whitespace */ 1396 for (i = count - 1; i > 0; i--) 1397 if (isspace(buf[i])) 1398 buf[i] = '\0'; 1399 else 1400 break; 1401 i = 0; 1402 pos = buf; 1403 while (pos) { 1404 token = strsep(&pos, " "); 1405 if (!token) { 1406 ret = -EINVAL; 1407 goto err_free; 1408 } 1409 1410 ret = kstrtou8(token, 16, &val); 1411 if (ret < 0) 1412 goto err_free; 1413 1414 if (token == buf) 1415 cmd = val; 1416 else 1417 parameters[i++] = val; 1418 1419 if (i == 64) { 1420 ret = -E2BIG; 1421 goto err_free; 1422 } 1423 } 1424 1425 ret = mipi_dbi_command_buf(&dbidev->dbi, cmd, parameters, i); 1426 1427 err_free: 1428 kfree(buf); 1429 err_exit: 1430 drm_dev_exit(idx); 1431 1432 return ret < 0 ? ret : count; 1433 } 1434 1435 static int mipi_dbi_debugfs_command_show(struct seq_file *m, void *unused) 1436 { 1437 struct mipi_dbi_dev *dbidev = m->private; 1438 struct mipi_dbi *dbi = &dbidev->dbi; 1439 u8 cmd, val[4]; 1440 int ret, idx; 1441 size_t len; 1442 1443 if (!drm_dev_enter(&dbidev->drm, &idx)) 1444 return -ENODEV; 1445 1446 for (cmd = 0; cmd < 255; cmd++) { 1447 if (!mipi_dbi_command_is_read(dbi, cmd)) 1448 continue; 1449 1450 switch (cmd) { 1451 case MIPI_DCS_READ_MEMORY_START: 1452 case MIPI_DCS_READ_MEMORY_CONTINUE: 1453 len = 2; 1454 break; 1455 case MIPI_DCS_GET_DISPLAY_ID: 1456 len = 3; 1457 break; 1458 case MIPI_DCS_GET_DISPLAY_STATUS: 1459 len = 4; 1460 break; 1461 default: 1462 len = 1; 1463 break; 1464 } 1465 1466 seq_printf(m, "%02x: ", cmd); 1467 ret = mipi_dbi_command_buf(dbi, cmd, val, len); 1468 if (ret) { 1469 seq_puts(m, "XX\n"); 1470 continue; 1471 } 1472 seq_printf(m, "%*phN\n", (int)len, val); 1473 } 1474 1475 drm_dev_exit(idx); 1476 1477 return 0; 1478 } 1479 1480 static int mipi_dbi_debugfs_command_open(struct inode *inode, 1481 struct file *file) 1482 { 1483 return single_open(file, mipi_dbi_debugfs_command_show, 1484 inode->i_private); 1485 } 1486 1487 static const struct file_operations mipi_dbi_debugfs_command_fops = { 1488 .owner = THIS_MODULE, 1489 .open = mipi_dbi_debugfs_command_open, 1490 .read = seq_read, 1491 .llseek = seq_lseek, 1492 .release = single_release, 1493 .write = mipi_dbi_debugfs_command_write, 1494 }; 1495 1496 /** 1497 * mipi_dbi_debugfs_init - Create debugfs entries 1498 * @minor: DRM minor 1499 * 1500 * This function creates a 'command' debugfs file for sending commands to the 1501 * controller or getting the read command values. 1502 * Drivers can use this as their &drm_driver->debugfs_init callback. 1503 * 1504 */ 1505 void mipi_dbi_debugfs_init(struct drm_minor *minor) 1506 { 1507 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(minor->dev); 1508 umode_t mode = S_IFREG | S_IWUSR; 1509 1510 if (dbidev->dbi.read_commands) 1511 mode |= S_IRUGO; 1512 debugfs_create_file("command", mode, minor->debugfs_root, dbidev, 1513 &mipi_dbi_debugfs_command_fops); 1514 } 1515 EXPORT_SYMBOL(mipi_dbi_debugfs_init); 1516 1517 #endif 1518 1519 MODULE_DESCRIPTION("MIPI Display Bus Interface (DBI) LCD controller support"); 1520 MODULE_LICENSE("GPL"); 1521