1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * MIPI Display Bus Interface (DBI) LCD controller support 4 * 5 * Copyright 2016 Noralf Trønnes 6 */ 7 8 #include <linux/backlight.h> 9 #include <linux/debugfs.h> 10 #include <linux/delay.h> 11 #include <linux/export.h> 12 #include <linux/gpio/consumer.h> 13 #include <linux/module.h> 14 #include <linux/regulator/consumer.h> 15 #include <linux/spi/spi.h> 16 17 #include <drm/drm_atomic.h> 18 #include <drm/drm_damage_helper.h> 19 #include <drm/drm_drv.h> 20 #include <drm/drm_file.h> 21 #include <drm/drm_format_helper.h> 22 #include <drm/drm_fourcc.h> 23 #include <drm/drm_framebuffer.h> 24 #include <drm/drm_gem.h> 25 #include <drm/drm_mipi_dbi.h> 26 #include <drm/drm_modes.h> 27 #include <drm/drm_print.h> 28 #include <drm/drm_rect.h> 29 #include <video/mipi_display.h> 30 31 #define MIPI_DBI_MAX_SPI_READ_SPEED 2000000 /* 2MHz */ 32 33 #define DCS_POWER_MODE_DISPLAY BIT(2) 34 #define DCS_POWER_MODE_DISPLAY_NORMAL_MODE BIT(3) 35 #define DCS_POWER_MODE_SLEEP_MODE BIT(4) 36 #define DCS_POWER_MODE_PARTIAL_MODE BIT(5) 37 #define DCS_POWER_MODE_IDLE_MODE BIT(6) 38 #define DCS_POWER_MODE_RESERVED_MASK (BIT(0) | BIT(1) | BIT(7)) 39 40 /** 41 * DOC: overview 42 * 43 * This library provides helpers for MIPI Display Bus Interface (DBI) 44 * compatible display controllers. 45 * 46 * Many controllers for tiny lcd displays are MIPI compliant and can use this 47 * library. If a controller uses registers 0x2A and 0x2B to set the area to 48 * update and uses register 0x2C to write to frame memory, it is most likely 49 * MIPI compliant. 50 * 51 * Only MIPI Type 1 displays are supported since a full frame memory is needed. 52 * 53 * There are 3 MIPI DBI implementation types: 54 * 55 * A. Motorola 6800 type parallel bus 56 * 57 * B. Intel 8080 type parallel bus 58 * 59 * C. SPI type with 3 options: 60 * 61 * 1. 9-bit with the Data/Command signal as the ninth bit 62 * 2. Same as above except it's sent as 16 bits 63 * 3. 8-bit with the Data/Command signal as a separate D/CX pin 64 * 65 * Currently mipi_dbi only supports Type C options 1 and 3 with 66 * mipi_dbi_spi_init(). 67 */ 68 69 #define MIPI_DBI_DEBUG_COMMAND(cmd, data, len) \ 70 ({ \ 71 if (!len) \ 72 DRM_DEBUG_DRIVER("cmd=%02x\n", cmd); \ 73 else if (len <= 32) \ 74 DRM_DEBUG_DRIVER("cmd=%02x, par=%*ph\n", cmd, (int)len, data);\ 75 else \ 76 DRM_DEBUG_DRIVER("cmd=%02x, len=%zu\n", cmd, len); \ 77 }) 78 79 static const u8 mipi_dbi_dcs_read_commands[] = { 80 MIPI_DCS_GET_DISPLAY_ID, 81 MIPI_DCS_GET_RED_CHANNEL, 82 MIPI_DCS_GET_GREEN_CHANNEL, 83 MIPI_DCS_GET_BLUE_CHANNEL, 84 MIPI_DCS_GET_DISPLAY_STATUS, 85 MIPI_DCS_GET_POWER_MODE, 86 MIPI_DCS_GET_ADDRESS_MODE, 87 MIPI_DCS_GET_PIXEL_FORMAT, 88 MIPI_DCS_GET_DISPLAY_MODE, 89 MIPI_DCS_GET_SIGNAL_MODE, 90 MIPI_DCS_GET_DIAGNOSTIC_RESULT, 91 MIPI_DCS_READ_MEMORY_START, 92 MIPI_DCS_READ_MEMORY_CONTINUE, 93 MIPI_DCS_GET_SCANLINE, 94 MIPI_DCS_GET_DISPLAY_BRIGHTNESS, 95 MIPI_DCS_GET_CONTROL_DISPLAY, 96 MIPI_DCS_GET_POWER_SAVE, 97 MIPI_DCS_GET_CABC_MIN_BRIGHTNESS, 98 MIPI_DCS_READ_DDB_START, 99 MIPI_DCS_READ_DDB_CONTINUE, 100 0, /* sentinel */ 101 }; 102 103 static bool mipi_dbi_command_is_read(struct mipi_dbi *dbi, u8 cmd) 104 { 105 unsigned int i; 106 107 if (!dbi->read_commands) 108 return false; 109 110 for (i = 0; i < 0xff; i++) { 111 if (!dbi->read_commands[i]) 112 return false; 113 if (cmd == dbi->read_commands[i]) 114 return true; 115 } 116 117 return false; 118 } 119 120 /** 121 * mipi_dbi_command_read - MIPI DCS read command 122 * @dbi: MIPI DBI structure 123 * @cmd: Command 124 * @val: Value read 125 * 126 * Send MIPI DCS read command to the controller. 127 * 128 * Returns: 129 * Zero on success, negative error code on failure. 130 */ 131 int mipi_dbi_command_read(struct mipi_dbi *dbi, u8 cmd, u8 *val) 132 { 133 if (!dbi->read_commands) 134 return -EACCES; 135 136 if (!mipi_dbi_command_is_read(dbi, cmd)) 137 return -EINVAL; 138 139 return mipi_dbi_command_buf(dbi, cmd, val, 1); 140 } 141 EXPORT_SYMBOL(mipi_dbi_command_read); 142 143 /** 144 * mipi_dbi_command_buf - MIPI DCS command with parameter(s) in an array 145 * @dbi: MIPI DBI structure 146 * @cmd: Command 147 * @data: Parameter buffer 148 * @len: Buffer length 149 * 150 * Returns: 151 * Zero on success, negative error code on failure. 152 */ 153 int mipi_dbi_command_buf(struct mipi_dbi *dbi, u8 cmd, u8 *data, size_t len) 154 { 155 u8 *cmdbuf; 156 int ret; 157 158 /* SPI requires dma-safe buffers */ 159 cmdbuf = kmemdup(&cmd, 1, GFP_KERNEL); 160 if (!cmdbuf) 161 return -ENOMEM; 162 163 mutex_lock(&dbi->cmdlock); 164 ret = dbi->command(dbi, cmdbuf, data, len); 165 mutex_unlock(&dbi->cmdlock); 166 167 kfree(cmdbuf); 168 169 return ret; 170 } 171 EXPORT_SYMBOL(mipi_dbi_command_buf); 172 173 /* This should only be used by mipi_dbi_command() */ 174 int mipi_dbi_command_stackbuf(struct mipi_dbi *dbi, u8 cmd, const u8 *data, 175 size_t len) 176 { 177 u8 *buf; 178 int ret; 179 180 buf = kmemdup(data, len, GFP_KERNEL); 181 if (!buf) 182 return -ENOMEM; 183 184 ret = mipi_dbi_command_buf(dbi, cmd, buf, len); 185 186 kfree(buf); 187 188 return ret; 189 } 190 EXPORT_SYMBOL(mipi_dbi_command_stackbuf); 191 192 /** 193 * mipi_dbi_buf_copy - Copy a framebuffer, transforming it if necessary 194 * @dst: The destination buffer 195 * @src: The source buffer 196 * @fb: The source framebuffer 197 * @clip: Clipping rectangle of the area to be copied 198 * @swap: When true, swap MSB/LSB of 16-bit values 199 * @fmtcnv_state: Format-conversion state 200 * 201 * Returns: 202 * Zero on success, negative error code on failure. 203 */ 204 int mipi_dbi_buf_copy(void *dst, struct iosys_map *src, struct drm_framebuffer *fb, 205 struct drm_rect *clip, bool swap, 206 struct drm_format_conv_state *fmtcnv_state) 207 { 208 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(fb->dev); 209 struct drm_gem_object *gem = drm_gem_fb_get_obj(fb, 0); 210 struct iosys_map dst_map = IOSYS_MAP_INIT_VADDR(dst); 211 int ret; 212 213 ret = drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE); 214 if (ret) 215 return ret; 216 217 switch (fb->format->format) { 218 case DRM_FORMAT_RGB565: 219 if (swap) 220 drm_fb_swab(&dst_map, NULL, src, fb, clip, !drm_gem_is_imported(gem), 221 fmtcnv_state); 222 else 223 drm_fb_memcpy(&dst_map, NULL, src, fb, clip); 224 break; 225 case DRM_FORMAT_RGB888: 226 drm_fb_memcpy(&dst_map, NULL, src, fb, clip); 227 break; 228 case DRM_FORMAT_XRGB8888: 229 switch (dbidev->pixel_format) { 230 case DRM_FORMAT_RGB565: 231 if (swap) { 232 drm_fb_xrgb8888_to_rgb565be(&dst_map, NULL, src, fb, clip, 233 fmtcnv_state); 234 } else { 235 drm_fb_xrgb8888_to_rgb565(&dst_map, NULL, src, fb, clip, 236 fmtcnv_state); 237 } 238 break; 239 case DRM_FORMAT_RGB888: 240 drm_fb_xrgb8888_to_rgb888(&dst_map, NULL, src, fb, clip, fmtcnv_state); 241 break; 242 } 243 break; 244 default: 245 drm_err_once(fb->dev, "Format is not supported: %p4cc\n", 246 &fb->format->format); 247 ret = -EINVAL; 248 } 249 250 drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE); 251 252 return ret; 253 } 254 EXPORT_SYMBOL(mipi_dbi_buf_copy); 255 256 static void mipi_dbi_set_window_address(struct mipi_dbi_dev *dbidev, 257 unsigned int xs, unsigned int xe, 258 unsigned int ys, unsigned int ye) 259 { 260 struct mipi_dbi *dbi = &dbidev->dbi; 261 262 xs += dbidev->left_offset; 263 xe += dbidev->left_offset; 264 ys += dbidev->top_offset; 265 ye += dbidev->top_offset; 266 267 mipi_dbi_command(dbi, MIPI_DCS_SET_COLUMN_ADDRESS, (xs >> 8) & 0xff, 268 xs & 0xff, (xe >> 8) & 0xff, xe & 0xff); 269 mipi_dbi_command(dbi, MIPI_DCS_SET_PAGE_ADDRESS, (ys >> 8) & 0xff, 270 ys & 0xff, (ye >> 8) & 0xff, ye & 0xff); 271 } 272 273 static void mipi_dbi_fb_dirty(struct iosys_map *src, struct drm_framebuffer *fb, 274 struct drm_rect *rect, struct drm_format_conv_state *fmtcnv_state) 275 { 276 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(fb->dev); 277 unsigned int height = rect->y2 - rect->y1; 278 unsigned int width = rect->x2 - rect->x1; 279 const struct drm_format_info *dst_format; 280 struct mipi_dbi *dbi = &dbidev->dbi; 281 bool swap = dbi->swap_bytes; 282 int ret = 0; 283 size_t len; 284 bool full; 285 void *tr; 286 287 full = width == fb->width && height == fb->height; 288 289 DRM_DEBUG_KMS("Flushing [FB:%d] " DRM_RECT_FMT "\n", fb->base.id, DRM_RECT_ARG(rect)); 290 291 if (!dbi->dc || !full || swap || 292 fb->format->format == DRM_FORMAT_XRGB8888) { 293 tr = dbidev->tx_buf; 294 ret = mipi_dbi_buf_copy(tr, src, fb, rect, swap, fmtcnv_state); 295 if (ret) 296 goto err_msg; 297 } else { 298 tr = src->vaddr; /* TODO: Use mapping abstraction properly */ 299 } 300 301 mipi_dbi_set_window_address(dbidev, rect->x1, rect->x2 - 1, rect->y1, 302 rect->y2 - 1); 303 304 if (fb->format->format == DRM_FORMAT_XRGB8888) 305 dst_format = drm_format_info(dbidev->pixel_format); 306 else 307 dst_format = fb->format; 308 len = drm_format_info_min_pitch(dst_format, 0, width) * height; 309 310 ret = mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START, tr, len); 311 err_msg: 312 if (ret) 313 drm_err_once(fb->dev, "Failed to update display %d\n", ret); 314 } 315 316 /** 317 * drm_mipi_dbi_crtc_helper_mode_valid - MIPI DBI mode-valid helper 318 * @crtc: The CRTC 319 * @mode: The mode to test 320 * 321 * This function validates a given display mode against the MIPI DBI's hardware 322 * display. Drivers can use this as their struct &drm_crtc_helper_funcs.mode_valid 323 * callback. 324 */ 325 enum drm_mode_status drm_mipi_dbi_crtc_helper_mode_valid(struct drm_crtc *crtc, 326 const struct drm_display_mode *mode) 327 { 328 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(crtc->dev); 329 330 return drm_crtc_helper_mode_valid_fixed(crtc, mode, &dbidev->mode); 331 } 332 EXPORT_SYMBOL(drm_mipi_dbi_crtc_helper_mode_valid); 333 334 /** 335 * drm_mipi_dbi_plane_helper_atomic_check - MIPI DBI plane check helper 336 * @plane: Plane to check 337 * @state: Atomic state 338 * 339 * This function performs the default checks on the primary plane 340 * of a MIPI DBI device. Drivers can use this as their 341 * struct &drm_crtc_helper_funcs.atomic_check callback. 342 * 343 * Returns: 344 * 0 on success, or a negative errno code otherwise. 345 */ 346 int drm_mipi_dbi_plane_helper_atomic_check(struct drm_plane *plane, 347 struct drm_atomic_state *state) 348 { 349 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); 350 struct drm_crtc_state *new_crtc_state = NULL; 351 int ret; 352 353 if (new_plane_state->crtc) 354 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); 355 356 ret = drm_atomic_helper_check_plane_state(new_plane_state, new_crtc_state, 357 DRM_PLANE_NO_SCALING, 358 DRM_PLANE_NO_SCALING, 359 false, false); 360 if (ret) 361 return ret; 362 else if (!new_plane_state->visible) 363 return 0; 364 365 return 0; 366 } 367 EXPORT_SYMBOL(drm_mipi_dbi_plane_helper_atomic_check); 368 369 /** 370 * drm_mipi_dbi_plane_helper_atomic_update - Display update helper 371 * @plane: Plane 372 * @state: Atomic state 373 * 374 * This function handles framebuffer flushing and vblank events. Drivers can use 375 * this as their struct &drm_plane_helper_funcs.atomic_update callback. 376 */ 377 void drm_mipi_dbi_plane_helper_atomic_update(struct drm_plane *plane, 378 struct drm_atomic_state *state) 379 { 380 struct drm_plane_state *plane_state = plane->state; 381 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state); 382 struct drm_framebuffer *fb = plane_state->fb; 383 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane); 384 struct drm_rect rect; 385 int idx; 386 387 if (!fb) 388 return; 389 390 if (drm_dev_enter(plane->dev, &idx)) { 391 if (drm_atomic_helper_damage_merged(old_plane_state, plane_state, &rect)) 392 mipi_dbi_fb_dirty(&shadow_plane_state->data[0], fb, &rect, 393 &shadow_plane_state->fmtcnv_state); 394 drm_dev_exit(idx); 395 } 396 } 397 EXPORT_SYMBOL(drm_mipi_dbi_plane_helper_atomic_update); 398 399 static void mipi_dbi_blank(struct mipi_dbi_dev *dbidev) 400 { 401 struct drm_device *drm = &dbidev->drm; 402 u16 height = drm->mode_config.min_height; 403 u16 width = drm->mode_config.min_width; 404 struct mipi_dbi *dbi = &dbidev->dbi; 405 const struct drm_format_info *dst_format; 406 size_t len; 407 int idx; 408 409 if (!drm_dev_enter(drm, &idx)) 410 return; 411 412 dst_format = drm_format_info(dbidev->pixel_format); 413 len = drm_format_info_min_pitch(dst_format, 0, width) * height; 414 415 memset(dbidev->tx_buf, 0, len); 416 417 mipi_dbi_set_window_address(dbidev, 0, width - 1, 0, height - 1); 418 mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START, 419 (u8 *)dbidev->tx_buf, len); 420 421 drm_dev_exit(idx); 422 } 423 424 /** 425 * drm_mipi_dbi_crtc_helper_atomic_check - MIPI DBI CRTC check helper 426 * @crtc: CRTC to check 427 * @state: Atomic state 428 * 429 * This function performs the default checks on the CRTC of a MIPI DBI 430 * device and ensures that the primary plane as been set up correctly. 431 * Drivers can use this as their struct &drm_crtc_helper_funcs.atomic_check 432 * callback. 433 * 434 * Returns: 435 * 0 on success, or a negative errno code otherwise. 436 */ 437 int drm_mipi_dbi_crtc_helper_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state) 438 { 439 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 440 int ret; 441 442 if (!crtc_state->enable) 443 goto out; 444 445 ret = drm_atomic_helper_check_crtc_primary_plane(crtc_state); 446 if (ret) 447 return ret; 448 449 out: 450 return drm_atomic_add_affected_planes(state, crtc); 451 } 452 EXPORT_SYMBOL(drm_mipi_dbi_crtc_helper_atomic_check); 453 454 /** 455 * drm_mipi_dbi_crtc_helper_atomic_disable - MIPI DBI CRTC disable helper 456 * @crtc: CRTC to disable 457 * @state: Atomic state 458 * 459 * This function disables backlight if present, if not the display memory is 460 * blanked. The regulator is disabled if in use. Drivers can use this as their 461 * struct &drm_crtc_helper_funcs.atomic_disable callback. 462 */ 463 void drm_mipi_dbi_crtc_helper_atomic_disable(struct drm_crtc *crtc, 464 struct drm_atomic_state *state) 465 { 466 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(crtc->dev); 467 468 if (dbidev->backlight) 469 backlight_disable(dbidev->backlight); 470 else 471 mipi_dbi_blank(dbidev); 472 473 if (dbidev->regulator) 474 regulator_disable(dbidev->regulator); 475 if (dbidev->io_regulator) 476 regulator_disable(dbidev->io_regulator); 477 } 478 EXPORT_SYMBOL(drm_mipi_dbi_crtc_helper_atomic_disable); 479 480 /** 481 * drm_mipi_dbi_connector_helper_get_modes - Duplicates the MIPI DBI mode for the connector 482 * @connector: The connector 483 * 484 * Sets the connecto rmodes from the MIPI DBI mode. Drivers can use this as their 485 * &drm_connector_helper_funcs->get_mods callback. See drm_gem_destroy_shadow_plane_state() 486 * for additional details. 487 * 488 * Returns: 489 * The number of created modes. 490 */ 491 int drm_mipi_dbi_connector_helper_get_modes(struct drm_connector *connector) 492 { 493 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(connector->dev); 494 495 return drm_connector_helper_get_modes_fixed(connector, &dbidev->mode); 496 } 497 EXPORT_SYMBOL(drm_mipi_dbi_connector_helper_get_modes); 498 499 static int mipi_dbi_rotate_mode(struct drm_display_mode *mode, 500 unsigned int rotation) 501 { 502 if (rotation == 0 || rotation == 180) { 503 return 0; 504 } else if (rotation == 90 || rotation == 270) { 505 swap(mode->hdisplay, mode->vdisplay); 506 swap(mode->hsync_start, mode->vsync_start); 507 swap(mode->hsync_end, mode->vsync_end); 508 swap(mode->htotal, mode->vtotal); 509 swap(mode->width_mm, mode->height_mm); 510 return 0; 511 } else { 512 return -EINVAL; 513 } 514 } 515 516 /** 517 * drm_mipi_dbi_dev_init - MIPI DBI device initialization 518 * @dbidev: MIPI DBI device structure to initialize 519 * @mode: Hardware display mode 520 * @format: Hardware color format (DRM_FORMAT\_\*). 521 * @rotation: Initial rotation in degrees Counter Clock Wise 522 * @tx_buf_size: Allocate a transmit buffer of at least this size. 523 * 524 * Initializes a MIPI-DBI device. The minimum size of the transmit buffer 525 * in @tx_buf_size is optional. Pass 0 to allocate enough memory to transmit 526 * a single scanline of the display. 527 * 528 * Returns: 529 * Zero on success, negative error code on failure. 530 */ 531 int drm_mipi_dbi_dev_init(struct mipi_dbi_dev *dbidev, const struct drm_display_mode *mode, 532 u32 format, unsigned int rotation, size_t tx_buf_size) 533 { 534 struct drm_device *drm = &dbidev->drm; 535 int ret; 536 537 if (!dbidev->dbi.command) 538 return -EINVAL; 539 540 if (!tx_buf_size) { 541 const struct drm_format_info *info = drm_format_info(format); 542 543 tx_buf_size = drm_format_info_min_pitch(info, 0, mode->hdisplay) * 544 mode->vdisplay; 545 } 546 547 dbidev->tx_buf = devm_kmalloc(drm->dev, tx_buf_size, GFP_KERNEL); 548 if (!dbidev->tx_buf) 549 return -ENOMEM; 550 551 drm_mode_copy(&dbidev->mode, mode); 552 ret = mipi_dbi_rotate_mode(&dbidev->mode, rotation); 553 if (ret) { 554 drm_err(drm, "Illegal rotation value %u\n", rotation); 555 return -EINVAL; 556 } 557 558 dbidev->rotation = rotation; 559 drm_dbg(drm, "rotation = %u\n", rotation); 560 561 dbidev->pixel_format = format; 562 if (dbidev->pixel_format == DRM_FORMAT_RGB888) 563 dbidev->dbi.write_memory_bpw = 8; 564 565 return 0; 566 } 567 EXPORT_SYMBOL(drm_mipi_dbi_dev_init); 568 569 /** 570 * mipi_dbi_hw_reset - Hardware reset of controller 571 * @dbi: MIPI DBI structure 572 * 573 * Reset controller if the &mipi_dbi->reset gpio is set. 574 */ 575 void mipi_dbi_hw_reset(struct mipi_dbi *dbi) 576 { 577 if (!dbi->reset) 578 return; 579 580 gpiod_set_value_cansleep(dbi->reset, 0); 581 usleep_range(20, 1000); 582 gpiod_set_value_cansleep(dbi->reset, 1); 583 msleep(120); 584 } 585 EXPORT_SYMBOL(mipi_dbi_hw_reset); 586 587 /** 588 * mipi_dbi_display_is_on - Check if display is on 589 * @dbi: MIPI DBI structure 590 * 591 * This function checks the Power Mode register (if readable) to see if 592 * display output is turned on. This can be used to see if the bootloader 593 * has already turned on the display avoiding flicker when the pipeline is 594 * enabled. 595 * 596 * Returns: 597 * true if the display can be verified to be on, false otherwise. 598 */ 599 bool mipi_dbi_display_is_on(struct mipi_dbi *dbi) 600 { 601 u8 val; 602 603 if (mipi_dbi_command_read(dbi, MIPI_DCS_GET_POWER_MODE, &val)) 604 return false; 605 606 val &= ~DCS_POWER_MODE_RESERVED_MASK; 607 608 /* The poweron/reset value is 08h DCS_POWER_MODE_DISPLAY_NORMAL_MODE */ 609 if (val != (DCS_POWER_MODE_DISPLAY | 610 DCS_POWER_MODE_DISPLAY_NORMAL_MODE | DCS_POWER_MODE_SLEEP_MODE)) 611 return false; 612 613 DRM_DEBUG_DRIVER("Display is ON\n"); 614 615 return true; 616 } 617 EXPORT_SYMBOL(mipi_dbi_display_is_on); 618 619 static int mipi_dbi_poweron_reset_conditional(struct mipi_dbi_dev *dbidev, bool cond) 620 { 621 struct device *dev = dbidev->drm.dev; 622 struct mipi_dbi *dbi = &dbidev->dbi; 623 int ret; 624 625 if (dbidev->regulator) { 626 ret = regulator_enable(dbidev->regulator); 627 if (ret) { 628 DRM_DEV_ERROR(dev, "Failed to enable regulator (%d)\n", ret); 629 return ret; 630 } 631 } 632 633 if (dbidev->io_regulator) { 634 ret = regulator_enable(dbidev->io_regulator); 635 if (ret) { 636 DRM_DEV_ERROR(dev, "Failed to enable I/O regulator (%d)\n", ret); 637 if (dbidev->regulator) 638 regulator_disable(dbidev->regulator); 639 return ret; 640 } 641 } 642 643 if (cond && mipi_dbi_display_is_on(dbi)) 644 return 1; 645 646 mipi_dbi_hw_reset(dbi); 647 ret = mipi_dbi_command(dbi, MIPI_DCS_SOFT_RESET); 648 if (ret) { 649 DRM_DEV_ERROR(dev, "Failed to send reset command (%d)\n", ret); 650 if (dbidev->regulator) 651 regulator_disable(dbidev->regulator); 652 if (dbidev->io_regulator) 653 regulator_disable(dbidev->io_regulator); 654 return ret; 655 } 656 657 /* 658 * If we did a hw reset, we know the controller is in Sleep mode and 659 * per MIPI DSC spec should wait 5ms after soft reset. If we didn't, 660 * we assume worst case and wait 120ms. 661 */ 662 if (dbi->reset) 663 usleep_range(5000, 20000); 664 else 665 msleep(120); 666 667 return 0; 668 } 669 670 /** 671 * mipi_dbi_poweron_reset - MIPI DBI poweron and reset 672 * @dbidev: MIPI DBI device structure 673 * 674 * This function enables the regulator if used and does a hardware and software 675 * reset. 676 * 677 * Returns: 678 * Zero on success, or a negative error code. 679 */ 680 int mipi_dbi_poweron_reset(struct mipi_dbi_dev *dbidev) 681 { 682 return mipi_dbi_poweron_reset_conditional(dbidev, false); 683 } 684 EXPORT_SYMBOL(mipi_dbi_poweron_reset); 685 686 /** 687 * mipi_dbi_poweron_conditional_reset - MIPI DBI poweron and conditional reset 688 * @dbidev: MIPI DBI device structure 689 * 690 * This function enables the regulator if used and if the display is off, it 691 * does a hardware and software reset. If mipi_dbi_display_is_on() determines 692 * that the display is on, no reset is performed. 693 * 694 * Returns: 695 * Zero if the controller was reset, 1 if the display was already on, or a 696 * negative error code. 697 */ 698 int mipi_dbi_poweron_conditional_reset(struct mipi_dbi_dev *dbidev) 699 { 700 return mipi_dbi_poweron_reset_conditional(dbidev, true); 701 } 702 EXPORT_SYMBOL(mipi_dbi_poweron_conditional_reset); 703 704 #if IS_ENABLED(CONFIG_SPI) 705 706 /** 707 * mipi_dbi_spi_cmd_max_speed - get the maximum SPI bus speed 708 * @spi: SPI device 709 * @len: The transfer buffer length. 710 * 711 * Many controllers have a max speed of 10MHz, but can be pushed way beyond 712 * that. Increase reliability by running pixel data at max speed and the rest 713 * at 10MHz, preventing transfer glitches from messing up the init settings. 714 */ 715 u32 mipi_dbi_spi_cmd_max_speed(struct spi_device *spi, size_t len) 716 { 717 if (len > 64) 718 return 0; /* use default */ 719 720 return min_t(u32, 10000000, spi->max_speed_hz); 721 } 722 EXPORT_SYMBOL(mipi_dbi_spi_cmd_max_speed); 723 724 /* 725 * MIPI DBI Type C Option 1 726 * 727 * If the SPI controller doesn't have 9 bits per word support, 728 * use blocks of 9 bytes to send 8x 9-bit words using a 8-bit SPI transfer. 729 * Pad partial blocks with MIPI_DCS_NOP (zero). 730 * This is how the D/C bit (x) is added: 731 * x7654321 732 * 0x765432 733 * 10x76543 734 * 210x7654 735 * 3210x765 736 * 43210x76 737 * 543210x7 738 * 6543210x 739 * 76543210 740 */ 741 742 static int mipi_dbi_spi1e_transfer(struct mipi_dbi *dbi, int dc, 743 const void *buf, size_t len, 744 unsigned int bpw) 745 { 746 bool swap_bytes = (bpw == 16); 747 size_t chunk, max_chunk = dbi->tx_buf9_len; 748 struct spi_device *spi = dbi->spi; 749 struct spi_transfer tr = { 750 .tx_buf = dbi->tx_buf9, 751 .bits_per_word = 8, 752 }; 753 struct spi_message m; 754 const u8 *src = buf; 755 int i, ret; 756 u8 *dst; 757 758 if (drm_debug_enabled(DRM_UT_DRIVER)) 759 pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n", 760 __func__, dc, max_chunk); 761 762 tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len); 763 spi_message_init_with_transfers(&m, &tr, 1); 764 765 if (!dc) { 766 if (WARN_ON_ONCE(len != 1)) 767 return -EINVAL; 768 769 /* Command: pad no-op's (zeroes) at beginning of block */ 770 dst = dbi->tx_buf9; 771 memset(dst, 0, 9); 772 dst[8] = *src; 773 tr.len = 9; 774 775 return spi_sync(spi, &m); 776 } 777 778 /* max with room for adding one bit per byte */ 779 max_chunk = max_chunk / 9 * 8; 780 /* but no bigger than len */ 781 max_chunk = min(max_chunk, len); 782 /* 8 byte blocks */ 783 max_chunk = max_t(size_t, 8, max_chunk & ~0x7); 784 785 while (len) { 786 size_t added = 0; 787 788 chunk = min(len, max_chunk); 789 len -= chunk; 790 dst = dbi->tx_buf9; 791 792 if (chunk < 8) { 793 u8 val, carry = 0; 794 795 /* Data: pad no-op's (zeroes) at end of block */ 796 memset(dst, 0, 9); 797 798 if (swap_bytes) { 799 for (i = 1; i < (chunk + 1); i++) { 800 val = src[1]; 801 *dst++ = carry | BIT(8 - i) | (val >> i); 802 carry = val << (8 - i); 803 i++; 804 val = src[0]; 805 *dst++ = carry | BIT(8 - i) | (val >> i); 806 carry = val << (8 - i); 807 src += 2; 808 } 809 *dst++ = carry; 810 } else { 811 for (i = 1; i < (chunk + 1); i++) { 812 val = *src++; 813 *dst++ = carry | BIT(8 - i) | (val >> i); 814 carry = val << (8 - i); 815 } 816 *dst++ = carry; 817 } 818 819 chunk = 8; 820 added = 1; 821 } else { 822 for (i = 0; i < chunk; i += 8) { 823 if (swap_bytes) { 824 *dst++ = BIT(7) | (src[1] >> 1); 825 *dst++ = (src[1] << 7) | BIT(6) | (src[0] >> 2); 826 *dst++ = (src[0] << 6) | BIT(5) | (src[3] >> 3); 827 *dst++ = (src[3] << 5) | BIT(4) | (src[2] >> 4); 828 *dst++ = (src[2] << 4) | BIT(3) | (src[5] >> 5); 829 *dst++ = (src[5] << 3) | BIT(2) | (src[4] >> 6); 830 *dst++ = (src[4] << 2) | BIT(1) | (src[7] >> 7); 831 *dst++ = (src[7] << 1) | BIT(0); 832 *dst++ = src[6]; 833 } else { 834 *dst++ = BIT(7) | (src[0] >> 1); 835 *dst++ = (src[0] << 7) | BIT(6) | (src[1] >> 2); 836 *dst++ = (src[1] << 6) | BIT(5) | (src[2] >> 3); 837 *dst++ = (src[2] << 5) | BIT(4) | (src[3] >> 4); 838 *dst++ = (src[3] << 4) | BIT(3) | (src[4] >> 5); 839 *dst++ = (src[4] << 3) | BIT(2) | (src[5] >> 6); 840 *dst++ = (src[5] << 2) | BIT(1) | (src[6] >> 7); 841 *dst++ = (src[6] << 1) | BIT(0); 842 *dst++ = src[7]; 843 } 844 845 src += 8; 846 added++; 847 } 848 } 849 850 tr.len = chunk + added; 851 852 ret = spi_sync(spi, &m); 853 if (ret) 854 return ret; 855 } 856 857 return 0; 858 } 859 860 static int mipi_dbi_spi1_transfer(struct mipi_dbi *dbi, int dc, 861 const void *buf, size_t len, 862 unsigned int bpw) 863 { 864 struct spi_device *spi = dbi->spi; 865 struct spi_transfer tr = { 866 .bits_per_word = 9, 867 }; 868 const u16 *src16 = buf; 869 const u8 *src8 = buf; 870 struct spi_message m; 871 size_t max_chunk; 872 u16 *dst16; 873 int ret; 874 875 if (!spi_is_bpw_supported(spi, 9)) 876 return mipi_dbi_spi1e_transfer(dbi, dc, buf, len, bpw); 877 878 tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len); 879 max_chunk = dbi->tx_buf9_len; 880 dst16 = dbi->tx_buf9; 881 882 if (drm_debug_enabled(DRM_UT_DRIVER)) 883 pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n", 884 __func__, dc, max_chunk); 885 886 max_chunk = min(max_chunk / 2, len); 887 888 spi_message_init_with_transfers(&m, &tr, 1); 889 tr.tx_buf = dst16; 890 891 while (len) { 892 size_t chunk = min(len, max_chunk); 893 unsigned int i; 894 895 if (bpw == 16) { 896 for (i = 0; i < (chunk * 2); i += 2) { 897 dst16[i] = *src16 >> 8; 898 dst16[i + 1] = *src16++ & 0xFF; 899 if (dc) { 900 dst16[i] |= 0x0100; 901 dst16[i + 1] |= 0x0100; 902 } 903 } 904 } else { 905 for (i = 0; i < chunk; i++) { 906 dst16[i] = *src8++; 907 if (dc) 908 dst16[i] |= 0x0100; 909 } 910 } 911 912 tr.len = chunk * 2; 913 len -= chunk; 914 915 ret = spi_sync(spi, &m); 916 if (ret) 917 return ret; 918 } 919 920 return 0; 921 } 922 923 static int mipi_dbi_typec1_command_read(struct mipi_dbi *dbi, u8 *cmd, 924 u8 *data, size_t len) 925 { 926 struct spi_device *spi = dbi->spi; 927 u32 speed_hz = min_t(u32, MIPI_DBI_MAX_SPI_READ_SPEED, 928 spi->max_speed_hz / 2); 929 struct spi_transfer tr[2] = { 930 { 931 .speed_hz = speed_hz, 932 .bits_per_word = 9, 933 .tx_buf = dbi->tx_buf9, 934 .len = 2, 935 }, { 936 .speed_hz = speed_hz, 937 .bits_per_word = 8, 938 .len = len, 939 .rx_buf = data, 940 }, 941 }; 942 struct spi_message m; 943 u16 *dst16; 944 int ret; 945 946 if (!len) 947 return -EINVAL; 948 949 if (!spi_is_bpw_supported(spi, 9)) { 950 /* 951 * FIXME: implement something like mipi_dbi_spi1e_transfer() but 952 * for reads using emulation. 953 */ 954 dev_err(&spi->dev, 955 "reading on host not supporting 9 bpw not yet implemented\n"); 956 return -EOPNOTSUPP; 957 } 958 959 /* 960 * Turn the 8bit command into a 16bit version of the command in the 961 * buffer. Only 9 bits of this will be used when executing the actual 962 * transfer. 963 */ 964 dst16 = dbi->tx_buf9; 965 dst16[0] = *cmd; 966 967 spi_message_init_with_transfers(&m, tr, ARRAY_SIZE(tr)); 968 ret = spi_sync(spi, &m); 969 970 if (!ret) 971 MIPI_DBI_DEBUG_COMMAND(*cmd, data, len); 972 973 return ret; 974 } 975 976 static int mipi_dbi_typec1_command(struct mipi_dbi *dbi, u8 *cmd, 977 u8 *parameters, size_t num) 978 { 979 unsigned int bpw = 8; 980 int ret; 981 982 if (mipi_dbi_command_is_read(dbi, *cmd)) 983 return mipi_dbi_typec1_command_read(dbi, cmd, parameters, num); 984 985 MIPI_DBI_DEBUG_COMMAND(*cmd, parameters, num); 986 987 ret = mipi_dbi_spi1_transfer(dbi, 0, cmd, 1, 8); 988 if (ret || !num) 989 return ret; 990 991 if (*cmd == MIPI_DCS_WRITE_MEMORY_START) 992 bpw = dbi->write_memory_bpw; 993 994 return mipi_dbi_spi1_transfer(dbi, 1, parameters, num, bpw); 995 } 996 997 /* MIPI DBI Type C Option 3 */ 998 999 static int mipi_dbi_typec3_command_read(struct mipi_dbi *dbi, u8 *cmd, 1000 u8 *data, size_t len) 1001 { 1002 struct spi_device *spi = dbi->spi; 1003 u32 speed_hz = min_t(u32, MIPI_DBI_MAX_SPI_READ_SPEED, 1004 spi->max_speed_hz / 2); 1005 struct spi_transfer tr[2] = { 1006 { 1007 .speed_hz = speed_hz, 1008 .tx_buf = cmd, 1009 .len = 1, 1010 }, { 1011 .speed_hz = speed_hz, 1012 .len = len, 1013 }, 1014 }; 1015 struct spi_message m; 1016 u8 *buf; 1017 int ret; 1018 1019 if (!len) 1020 return -EINVAL; 1021 1022 /* 1023 * Support non-standard 24-bit and 32-bit Nokia read commands which 1024 * start with a dummy clock, so we need to read an extra byte. 1025 */ 1026 if (*cmd == MIPI_DCS_GET_DISPLAY_ID || 1027 *cmd == MIPI_DCS_GET_DISPLAY_STATUS) { 1028 if (!(len == 3 || len == 4)) 1029 return -EINVAL; 1030 1031 tr[1].len = len + 1; 1032 } 1033 1034 buf = kmalloc(tr[1].len, GFP_KERNEL); 1035 if (!buf) 1036 return -ENOMEM; 1037 1038 tr[1].rx_buf = buf; 1039 1040 spi_bus_lock(spi->controller); 1041 gpiod_set_value_cansleep(dbi->dc, 0); 1042 1043 spi_message_init_with_transfers(&m, tr, ARRAY_SIZE(tr)); 1044 ret = spi_sync_locked(spi, &m); 1045 spi_bus_unlock(spi->controller); 1046 if (ret) 1047 goto err_free; 1048 1049 if (tr[1].len == len) { 1050 memcpy(data, buf, len); 1051 } else { 1052 unsigned int i; 1053 1054 for (i = 0; i < len; i++) 1055 data[i] = (buf[i] << 1) | (buf[i + 1] >> 7); 1056 } 1057 1058 MIPI_DBI_DEBUG_COMMAND(*cmd, data, len); 1059 1060 err_free: 1061 kfree(buf); 1062 1063 return ret; 1064 } 1065 1066 static int mipi_dbi_typec3_command(struct mipi_dbi *dbi, u8 *cmd, 1067 u8 *par, size_t num) 1068 { 1069 struct spi_device *spi = dbi->spi; 1070 unsigned int bpw = 8; 1071 u32 speed_hz; 1072 int ret; 1073 1074 if (mipi_dbi_command_is_read(dbi, *cmd)) 1075 return mipi_dbi_typec3_command_read(dbi, cmd, par, num); 1076 1077 MIPI_DBI_DEBUG_COMMAND(*cmd, par, num); 1078 1079 spi_bus_lock(spi->controller); 1080 gpiod_set_value_cansleep(dbi->dc, 0); 1081 speed_hz = mipi_dbi_spi_cmd_max_speed(spi, 1); 1082 ret = mipi_dbi_spi_transfer(spi, speed_hz, 8, cmd, 1); 1083 spi_bus_unlock(spi->controller); 1084 if (ret || !num) 1085 return ret; 1086 1087 if (*cmd == MIPI_DCS_WRITE_MEMORY_START) 1088 bpw = dbi->write_memory_bpw; 1089 1090 spi_bus_lock(spi->controller); 1091 gpiod_set_value_cansleep(dbi->dc, 1); 1092 speed_hz = mipi_dbi_spi_cmd_max_speed(spi, num); 1093 ret = mipi_dbi_spi_transfer(spi, speed_hz, bpw, par, num); 1094 spi_bus_unlock(spi->controller); 1095 1096 return ret; 1097 } 1098 1099 /** 1100 * mipi_dbi_spi_init - Initialize MIPI DBI SPI interface 1101 * @spi: SPI device 1102 * @dbi: MIPI DBI structure to initialize 1103 * @dc: D/C gpio (optional) 1104 * 1105 * This function sets &mipi_dbi->command, enables &mipi_dbi->read_commands for the 1106 * usual read commands. It should be followed by a call to mipi_dbi_dev_init() or 1107 * a driver-specific init. 1108 * 1109 * If @dc is set, a Type C Option 3 interface is assumed, if not 1110 * Type C Option 1. 1111 * 1112 * If the command is %MIPI_DCS_WRITE_MEMORY_START and the pixel format is RGB565, endianness has 1113 * to be taken into account. The MIPI DBI serial interface is big endian and framebuffers are 1114 * assumed stored in memory as little endian (%DRM_FORMAT_BIG_ENDIAN is not supported). 1115 * 1116 * This is how endianness is handled: 1117 * 1118 * Option 1 (D/C as a bit): The buffer is sent on the wire byte by byte so the 16-bit buffer is 1119 * byteswapped before transfer. 1120 * 1121 * Option 3 (D/C as a gpio): If the SPI controller supports 16 bits per word the buffer can be 1122 * sent as-is. If not the caller is responsible for swapping the bytes 1123 * before calling mipi_dbi_command_buf() and the buffer is sent 8 bpw. 1124 * 1125 * This handling is optimised for %DRM_FORMAT_RGB565 framebuffers. 1126 * 1127 * If the interface is Option 1 and the SPI controller doesn't support 9 bits per word, 1128 * the buffer is sent as 9x 8-bit words, padded with MIPI DCS no-op commands if necessary. 1129 * 1130 * Returns: 1131 * Zero on success, negative error code on failure. 1132 */ 1133 int mipi_dbi_spi_init(struct spi_device *spi, struct mipi_dbi *dbi, 1134 struct gpio_desc *dc) 1135 { 1136 struct device *dev = &spi->dev; 1137 int ret; 1138 1139 /* 1140 * Even though it's not the SPI device that does DMA (the master does), 1141 * the dma mask is necessary for the dma_alloc_wc() in the GEM code 1142 * (e.g., drm_gem_dma_create()). The dma_addr returned will be a physical 1143 * address which might be different from the bus address, but this is 1144 * not a problem since the address will not be used. 1145 * The virtual address is used in the transfer and the SPI core 1146 * re-maps it on the SPI master device using the DMA streaming API 1147 * (spi_map_buf()). 1148 */ 1149 if (!dev->coherent_dma_mask) { 1150 ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32)); 1151 if (ret) { 1152 dev_warn(dev, "Failed to set dma mask %d\n", ret); 1153 return ret; 1154 } 1155 } 1156 1157 dbi->spi = spi; 1158 dbi->read_commands = mipi_dbi_dcs_read_commands; 1159 dbi->write_memory_bpw = 16; 1160 1161 if (dc) { 1162 dbi->command = mipi_dbi_typec3_command; 1163 dbi->dc = dc; 1164 if (!spi_is_bpw_supported(spi, 16)) { 1165 dbi->write_memory_bpw = 8; 1166 dbi->swap_bytes = true; 1167 } 1168 } else { 1169 dbi->command = mipi_dbi_typec1_command; 1170 dbi->tx_buf9_len = SZ_16K; 1171 dbi->tx_buf9 = devm_kmalloc(dev, dbi->tx_buf9_len, GFP_KERNEL); 1172 if (!dbi->tx_buf9) 1173 return -ENOMEM; 1174 } 1175 1176 mutex_init(&dbi->cmdlock); 1177 1178 DRM_DEBUG_DRIVER("SPI speed: %uMHz\n", spi->max_speed_hz / 1000000); 1179 1180 return 0; 1181 } 1182 EXPORT_SYMBOL(mipi_dbi_spi_init); 1183 1184 /** 1185 * mipi_dbi_spi_transfer - SPI transfer helper 1186 * @spi: SPI device 1187 * @speed_hz: Override speed (optional) 1188 * @bpw: Bits per word 1189 * @buf: Buffer to transfer 1190 * @len: Buffer length 1191 * 1192 * This SPI transfer helper breaks up the transfer of @buf into chunks which 1193 * the SPI controller driver can handle. The SPI bus must be locked when 1194 * calling this. 1195 * 1196 * Returns: 1197 * Zero on success, negative error code on failure. 1198 */ 1199 int mipi_dbi_spi_transfer(struct spi_device *spi, u32 speed_hz, 1200 u8 bpw, const void *buf, size_t len) 1201 { 1202 size_t max_chunk = spi_max_transfer_size(spi); 1203 struct spi_transfer tr = { 1204 .bits_per_word = bpw, 1205 .speed_hz = speed_hz, 1206 }; 1207 struct spi_message m; 1208 size_t chunk; 1209 int ret; 1210 1211 /* In __spi_validate, there's a validation that no partial transfers 1212 * are accepted (xfer->len % w_size must be zero). 1213 * Here we align max_chunk to multiple of 2 (16bits), 1214 * to prevent transfers from being rejected. 1215 */ 1216 max_chunk = ALIGN_DOWN(max_chunk, 2); 1217 1218 spi_message_init_with_transfers(&m, &tr, 1); 1219 1220 while (len) { 1221 chunk = min(len, max_chunk); 1222 1223 tr.tx_buf = buf; 1224 tr.len = chunk; 1225 buf += chunk; 1226 len -= chunk; 1227 1228 ret = spi_sync_locked(spi, &m); 1229 if (ret) 1230 return ret; 1231 } 1232 1233 return 0; 1234 } 1235 EXPORT_SYMBOL(mipi_dbi_spi_transfer); 1236 1237 #endif /* CONFIG_SPI */ 1238 1239 #ifdef CONFIG_DEBUG_FS 1240 1241 static ssize_t mipi_dbi_debugfs_command_write(struct file *file, 1242 const char __user *ubuf, 1243 size_t count, loff_t *ppos) 1244 { 1245 struct seq_file *m = file->private_data; 1246 struct mipi_dbi_dev *dbidev = m->private; 1247 u8 val, cmd = 0, parameters[64]; 1248 char *buf, *pos, *token; 1249 int i, ret, idx; 1250 1251 if (!drm_dev_enter(&dbidev->drm, &idx)) 1252 return -ENODEV; 1253 1254 buf = memdup_user_nul(ubuf, count); 1255 if (IS_ERR(buf)) { 1256 ret = PTR_ERR(buf); 1257 goto err_exit; 1258 } 1259 1260 /* strip trailing whitespace */ 1261 for (i = count - 1; i > 0; i--) 1262 if (isspace(buf[i])) 1263 buf[i] = '\0'; 1264 else 1265 break; 1266 i = 0; 1267 pos = buf; 1268 while (pos) { 1269 token = strsep(&pos, " "); 1270 if (!token) { 1271 ret = -EINVAL; 1272 goto err_free; 1273 } 1274 1275 ret = kstrtou8(token, 16, &val); 1276 if (ret < 0) 1277 goto err_free; 1278 1279 if (token == buf) 1280 cmd = val; 1281 else 1282 parameters[i++] = val; 1283 1284 if (i == 64) { 1285 ret = -E2BIG; 1286 goto err_free; 1287 } 1288 } 1289 1290 ret = mipi_dbi_command_buf(&dbidev->dbi, cmd, parameters, i); 1291 1292 err_free: 1293 kfree(buf); 1294 err_exit: 1295 drm_dev_exit(idx); 1296 1297 return ret < 0 ? ret : count; 1298 } 1299 1300 static int mipi_dbi_debugfs_command_show(struct seq_file *m, void *unused) 1301 { 1302 struct mipi_dbi_dev *dbidev = m->private; 1303 struct mipi_dbi *dbi = &dbidev->dbi; 1304 u8 cmd, val[4]; 1305 int ret, idx; 1306 size_t len; 1307 1308 if (!drm_dev_enter(&dbidev->drm, &idx)) 1309 return -ENODEV; 1310 1311 for (cmd = 0; cmd < 255; cmd++) { 1312 if (!mipi_dbi_command_is_read(dbi, cmd)) 1313 continue; 1314 1315 switch (cmd) { 1316 case MIPI_DCS_READ_MEMORY_START: 1317 case MIPI_DCS_READ_MEMORY_CONTINUE: 1318 len = 2; 1319 break; 1320 case MIPI_DCS_GET_DISPLAY_ID: 1321 len = 3; 1322 break; 1323 case MIPI_DCS_GET_DISPLAY_STATUS: 1324 len = 4; 1325 break; 1326 default: 1327 len = 1; 1328 break; 1329 } 1330 1331 seq_printf(m, "%02x: ", cmd); 1332 ret = mipi_dbi_command_buf(dbi, cmd, val, len); 1333 if (ret) { 1334 seq_puts(m, "XX\n"); 1335 continue; 1336 } 1337 seq_printf(m, "%*phN\n", (int)len, val); 1338 } 1339 1340 drm_dev_exit(idx); 1341 1342 return 0; 1343 } 1344 1345 static int mipi_dbi_debugfs_command_open(struct inode *inode, 1346 struct file *file) 1347 { 1348 return single_open(file, mipi_dbi_debugfs_command_show, 1349 inode->i_private); 1350 } 1351 1352 static const struct file_operations mipi_dbi_debugfs_command_fops = { 1353 .owner = THIS_MODULE, 1354 .open = mipi_dbi_debugfs_command_open, 1355 .read = seq_read, 1356 .llseek = seq_lseek, 1357 .release = single_release, 1358 .write = mipi_dbi_debugfs_command_write, 1359 }; 1360 1361 /** 1362 * mipi_dbi_debugfs_init - Create debugfs entries 1363 * @minor: DRM minor 1364 * 1365 * This function creates a 'command' debugfs file for sending commands to the 1366 * controller or getting the read command values. 1367 * Drivers can use this as their &drm_driver->debugfs_init callback. 1368 * 1369 */ 1370 void mipi_dbi_debugfs_init(struct drm_minor *minor) 1371 { 1372 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(minor->dev); 1373 umode_t mode = S_IFREG | S_IWUSR; 1374 1375 if (dbidev->dbi.read_commands) 1376 mode |= S_IRUGO; 1377 debugfs_create_file("command", mode, minor->debugfs_root, dbidev, 1378 &mipi_dbi_debugfs_command_fops); 1379 } 1380 EXPORT_SYMBOL(mipi_dbi_debugfs_init); 1381 1382 #endif 1383 1384 MODULE_DESCRIPTION("MIPI Display Bus Interface (DBI) LCD controller support"); 1385 MODULE_LICENSE("GPL"); 1386