1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * MIPI Display Bus Interface (DBI) LCD controller support 4 * 5 * Copyright 2016 Noralf Trønnes 6 */ 7 8 #include <linux/backlight.h> 9 #include <linux/debugfs.h> 10 #include <linux/delay.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/module.h> 13 #include <linux/regulator/consumer.h> 14 #include <linux/spi/spi.h> 15 16 #include <drm/drm_connector.h> 17 #include <drm/drm_damage_helper.h> 18 #include <drm/drm_drv.h> 19 #include <drm/drm_file.h> 20 #include <drm/drm_format_helper.h> 21 #include <drm/drm_fourcc.h> 22 #include <drm/drm_framebuffer.h> 23 #include <drm/drm_gem.h> 24 #include <drm/drm_gem_framebuffer_helper.h> 25 #include <drm/drm_mipi_dbi.h> 26 #include <drm/drm_modes.h> 27 #include <drm/drm_probe_helper.h> 28 #include <drm/drm_rect.h> 29 #include <video/mipi_display.h> 30 31 #define MIPI_DBI_MAX_SPI_READ_SPEED 2000000 /* 2MHz */ 32 33 #define DCS_POWER_MODE_DISPLAY BIT(2) 34 #define DCS_POWER_MODE_DISPLAY_NORMAL_MODE BIT(3) 35 #define DCS_POWER_MODE_SLEEP_MODE BIT(4) 36 #define DCS_POWER_MODE_PARTIAL_MODE BIT(5) 37 #define DCS_POWER_MODE_IDLE_MODE BIT(6) 38 #define DCS_POWER_MODE_RESERVED_MASK (BIT(0) | BIT(1) | BIT(7)) 39 40 /** 41 * DOC: overview 42 * 43 * This library provides helpers for MIPI Display Bus Interface (DBI) 44 * compatible display controllers. 45 * 46 * Many controllers for tiny lcd displays are MIPI compliant and can use this 47 * library. If a controller uses registers 0x2A and 0x2B to set the area to 48 * update and uses register 0x2C to write to frame memory, it is most likely 49 * MIPI compliant. 50 * 51 * Only MIPI Type 1 displays are supported since a full frame memory is needed. 52 * 53 * There are 3 MIPI DBI implementation types: 54 * 55 * A. Motorola 6800 type parallel bus 56 * 57 * B. Intel 8080 type parallel bus 58 * 59 * C. SPI type with 3 options: 60 * 61 * 1. 9-bit with the Data/Command signal as the ninth bit 62 * 2. Same as above except it's sent as 16 bits 63 * 3. 8-bit with the Data/Command signal as a separate D/CX pin 64 * 65 * Currently mipi_dbi only supports Type C options 1 and 3 with 66 * mipi_dbi_spi_init(). 67 */ 68 69 #define MIPI_DBI_DEBUG_COMMAND(cmd, data, len) \ 70 ({ \ 71 if (!len) \ 72 DRM_DEBUG_DRIVER("cmd=%02x\n", cmd); \ 73 else if (len <= 32) \ 74 DRM_DEBUG_DRIVER("cmd=%02x, par=%*ph\n", cmd, (int)len, data);\ 75 else \ 76 DRM_DEBUG_DRIVER("cmd=%02x, len=%zu\n", cmd, len); \ 77 }) 78 79 static const u8 mipi_dbi_dcs_read_commands[] = { 80 MIPI_DCS_GET_DISPLAY_ID, 81 MIPI_DCS_GET_RED_CHANNEL, 82 MIPI_DCS_GET_GREEN_CHANNEL, 83 MIPI_DCS_GET_BLUE_CHANNEL, 84 MIPI_DCS_GET_DISPLAY_STATUS, 85 MIPI_DCS_GET_POWER_MODE, 86 MIPI_DCS_GET_ADDRESS_MODE, 87 MIPI_DCS_GET_PIXEL_FORMAT, 88 MIPI_DCS_GET_DISPLAY_MODE, 89 MIPI_DCS_GET_SIGNAL_MODE, 90 MIPI_DCS_GET_DIAGNOSTIC_RESULT, 91 MIPI_DCS_READ_MEMORY_START, 92 MIPI_DCS_READ_MEMORY_CONTINUE, 93 MIPI_DCS_GET_SCANLINE, 94 MIPI_DCS_GET_DISPLAY_BRIGHTNESS, 95 MIPI_DCS_GET_CONTROL_DISPLAY, 96 MIPI_DCS_GET_POWER_SAVE, 97 MIPI_DCS_GET_CABC_MIN_BRIGHTNESS, 98 MIPI_DCS_READ_DDB_START, 99 MIPI_DCS_READ_DDB_CONTINUE, 100 0, /* sentinel */ 101 }; 102 103 static bool mipi_dbi_command_is_read(struct mipi_dbi *dbi, u8 cmd) 104 { 105 unsigned int i; 106 107 if (!dbi->read_commands) 108 return false; 109 110 for (i = 0; i < 0xff; i++) { 111 if (!dbi->read_commands[i]) 112 return false; 113 if (cmd == dbi->read_commands[i]) 114 return true; 115 } 116 117 return false; 118 } 119 120 /** 121 * mipi_dbi_command_read - MIPI DCS read command 122 * @dbi: MIPI DBI structure 123 * @cmd: Command 124 * @val: Value read 125 * 126 * Send MIPI DCS read command to the controller. 127 * 128 * Returns: 129 * Zero on success, negative error code on failure. 130 */ 131 int mipi_dbi_command_read(struct mipi_dbi *dbi, u8 cmd, u8 *val) 132 { 133 if (!dbi->read_commands) 134 return -EACCES; 135 136 if (!mipi_dbi_command_is_read(dbi, cmd)) 137 return -EINVAL; 138 139 return mipi_dbi_command_buf(dbi, cmd, val, 1); 140 } 141 EXPORT_SYMBOL(mipi_dbi_command_read); 142 143 /** 144 * mipi_dbi_command_buf - MIPI DCS command with parameter(s) in an array 145 * @dbi: MIPI DBI structure 146 * @cmd: Command 147 * @data: Parameter buffer 148 * @len: Buffer length 149 * 150 * Returns: 151 * Zero on success, negative error code on failure. 152 */ 153 int mipi_dbi_command_buf(struct mipi_dbi *dbi, u8 cmd, u8 *data, size_t len) 154 { 155 u8 *cmdbuf; 156 int ret; 157 158 /* SPI requires dma-safe buffers */ 159 cmdbuf = kmemdup(&cmd, 1, GFP_KERNEL); 160 if (!cmdbuf) 161 return -ENOMEM; 162 163 mutex_lock(&dbi->cmdlock); 164 ret = dbi->command(dbi, cmdbuf, data, len); 165 mutex_unlock(&dbi->cmdlock); 166 167 kfree(cmdbuf); 168 169 return ret; 170 } 171 EXPORT_SYMBOL(mipi_dbi_command_buf); 172 173 /* This should only be used by mipi_dbi_command() */ 174 int mipi_dbi_command_stackbuf(struct mipi_dbi *dbi, u8 cmd, const u8 *data, 175 size_t len) 176 { 177 u8 *buf; 178 int ret; 179 180 buf = kmemdup(data, len, GFP_KERNEL); 181 if (!buf) 182 return -ENOMEM; 183 184 ret = mipi_dbi_command_buf(dbi, cmd, buf, len); 185 186 kfree(buf); 187 188 return ret; 189 } 190 EXPORT_SYMBOL(mipi_dbi_command_stackbuf); 191 192 /** 193 * mipi_dbi_buf_copy - Copy a framebuffer, transforming it if necessary 194 * @dst: The destination buffer 195 * @fb: The source framebuffer 196 * @clip: Clipping rectangle of the area to be copied 197 * @swap: When true, swap MSB/LSB of 16-bit values 198 * 199 * Returns: 200 * Zero on success, negative error code on failure. 201 */ 202 int mipi_dbi_buf_copy(void *dst, struct drm_framebuffer *fb, 203 struct drm_rect *clip, bool swap) 204 { 205 struct drm_gem_object *gem = drm_gem_fb_get_obj(fb, 0); 206 struct iosys_map map[DRM_FORMAT_MAX_PLANES]; 207 struct iosys_map data[DRM_FORMAT_MAX_PLANES]; 208 void *src; 209 int ret; 210 211 ret = drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE); 212 if (ret) 213 return ret; 214 215 ret = drm_gem_fb_vmap(fb, map, data); 216 if (ret) 217 goto out_drm_gem_fb_end_cpu_access; 218 src = data[0].vaddr; /* TODO: Use mapping abstraction properly */ 219 220 switch (fb->format->format) { 221 case DRM_FORMAT_RGB565: 222 if (swap) 223 drm_fb_swab(dst, 0, src, fb, clip, !gem->import_attach); 224 else 225 drm_fb_memcpy(dst, 0, src, fb, clip); 226 break; 227 case DRM_FORMAT_XRGB8888: 228 drm_fb_xrgb8888_to_rgb565(dst, 0, src, fb, clip, swap); 229 break; 230 default: 231 drm_err_once(fb->dev, "Format is not supported: %p4cc\n", 232 &fb->format->format); 233 ret = -EINVAL; 234 } 235 236 drm_gem_fb_vunmap(fb, map); 237 out_drm_gem_fb_end_cpu_access: 238 drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE); 239 240 return ret; 241 } 242 EXPORT_SYMBOL(mipi_dbi_buf_copy); 243 244 static void mipi_dbi_set_window_address(struct mipi_dbi_dev *dbidev, 245 unsigned int xs, unsigned int xe, 246 unsigned int ys, unsigned int ye) 247 { 248 struct mipi_dbi *dbi = &dbidev->dbi; 249 250 xs += dbidev->left_offset; 251 xe += dbidev->left_offset; 252 ys += dbidev->top_offset; 253 ye += dbidev->top_offset; 254 255 mipi_dbi_command(dbi, MIPI_DCS_SET_COLUMN_ADDRESS, (xs >> 8) & 0xff, 256 xs & 0xff, (xe >> 8) & 0xff, xe & 0xff); 257 mipi_dbi_command(dbi, MIPI_DCS_SET_PAGE_ADDRESS, (ys >> 8) & 0xff, 258 ys & 0xff, (ye >> 8) & 0xff, ye & 0xff); 259 } 260 261 static void mipi_dbi_fb_dirty(struct drm_framebuffer *fb, struct drm_rect *rect) 262 { 263 struct iosys_map map[DRM_FORMAT_MAX_PLANES]; 264 struct iosys_map data[DRM_FORMAT_MAX_PLANES]; 265 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(fb->dev); 266 unsigned int height = rect->y2 - rect->y1; 267 unsigned int width = rect->x2 - rect->x1; 268 struct mipi_dbi *dbi = &dbidev->dbi; 269 bool swap = dbi->swap_bytes; 270 int idx, ret = 0; 271 bool full; 272 void *tr; 273 274 if (WARN_ON(!fb)) 275 return; 276 277 if (!drm_dev_enter(fb->dev, &idx)) 278 return; 279 280 ret = drm_gem_fb_vmap(fb, map, data); 281 if (ret) 282 goto err_drm_dev_exit; 283 284 full = width == fb->width && height == fb->height; 285 286 DRM_DEBUG_KMS("Flushing [FB:%d] " DRM_RECT_FMT "\n", fb->base.id, DRM_RECT_ARG(rect)); 287 288 if (!dbi->dc || !full || swap || 289 fb->format->format == DRM_FORMAT_XRGB8888) { 290 tr = dbidev->tx_buf; 291 ret = mipi_dbi_buf_copy(dbidev->tx_buf, fb, rect, swap); 292 if (ret) 293 goto err_msg; 294 } else { 295 tr = data[0].vaddr; /* TODO: Use mapping abstraction properly */ 296 } 297 298 mipi_dbi_set_window_address(dbidev, rect->x1, rect->x2 - 1, rect->y1, 299 rect->y2 - 1); 300 301 ret = mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START, tr, 302 width * height * 2); 303 err_msg: 304 if (ret) 305 drm_err_once(fb->dev, "Failed to update display %d\n", ret); 306 307 drm_gem_fb_vunmap(fb, map); 308 309 err_drm_dev_exit: 310 drm_dev_exit(idx); 311 } 312 313 /** 314 * mipi_dbi_pipe_update - Display pipe update helper 315 * @pipe: Simple display pipe 316 * @old_state: Old plane state 317 * 318 * This function handles framebuffer flushing and vblank events. Drivers can use 319 * this as their &drm_simple_display_pipe_funcs->update callback. 320 */ 321 void mipi_dbi_pipe_update(struct drm_simple_display_pipe *pipe, 322 struct drm_plane_state *old_state) 323 { 324 struct drm_plane_state *state = pipe->plane.state; 325 struct drm_rect rect; 326 327 if (!pipe->crtc.state->active) 328 return; 329 330 if (drm_atomic_helper_damage_merged(old_state, state, &rect)) 331 mipi_dbi_fb_dirty(state->fb, &rect); 332 } 333 EXPORT_SYMBOL(mipi_dbi_pipe_update); 334 335 /** 336 * mipi_dbi_enable_flush - MIPI DBI enable helper 337 * @dbidev: MIPI DBI device structure 338 * @crtc_state: CRTC state 339 * @plane_state: Plane state 340 * 341 * Flushes the whole framebuffer and enables the backlight. Drivers can use this 342 * in their &drm_simple_display_pipe_funcs->enable callback. 343 * 344 * Note: Drivers which don't use mipi_dbi_pipe_update() because they have custom 345 * framebuffer flushing, can't use this function since they both use the same 346 * flushing code. 347 */ 348 void mipi_dbi_enable_flush(struct mipi_dbi_dev *dbidev, 349 struct drm_crtc_state *crtc_state, 350 struct drm_plane_state *plane_state) 351 { 352 struct drm_framebuffer *fb = plane_state->fb; 353 struct drm_rect rect = { 354 .x1 = 0, 355 .x2 = fb->width, 356 .y1 = 0, 357 .y2 = fb->height, 358 }; 359 int idx; 360 361 if (!drm_dev_enter(&dbidev->drm, &idx)) 362 return; 363 364 mipi_dbi_fb_dirty(fb, &rect); 365 backlight_enable(dbidev->backlight); 366 367 drm_dev_exit(idx); 368 } 369 EXPORT_SYMBOL(mipi_dbi_enable_flush); 370 371 static void mipi_dbi_blank(struct mipi_dbi_dev *dbidev) 372 { 373 struct drm_device *drm = &dbidev->drm; 374 u16 height = drm->mode_config.min_height; 375 u16 width = drm->mode_config.min_width; 376 struct mipi_dbi *dbi = &dbidev->dbi; 377 size_t len = width * height * 2; 378 int idx; 379 380 if (!drm_dev_enter(drm, &idx)) 381 return; 382 383 memset(dbidev->tx_buf, 0, len); 384 385 mipi_dbi_set_window_address(dbidev, 0, width - 1, 0, height - 1); 386 mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START, 387 (u8 *)dbidev->tx_buf, len); 388 389 drm_dev_exit(idx); 390 } 391 392 /** 393 * mipi_dbi_pipe_disable - MIPI DBI pipe disable helper 394 * @pipe: Display pipe 395 * 396 * This function disables backlight if present, if not the display memory is 397 * blanked. The regulator is disabled if in use. Drivers can use this as their 398 * &drm_simple_display_pipe_funcs->disable callback. 399 */ 400 void mipi_dbi_pipe_disable(struct drm_simple_display_pipe *pipe) 401 { 402 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev); 403 404 DRM_DEBUG_KMS("\n"); 405 406 if (dbidev->backlight) 407 backlight_disable(dbidev->backlight); 408 else 409 mipi_dbi_blank(dbidev); 410 411 if (dbidev->regulator) 412 regulator_disable(dbidev->regulator); 413 } 414 EXPORT_SYMBOL(mipi_dbi_pipe_disable); 415 416 static int mipi_dbi_connector_get_modes(struct drm_connector *connector) 417 { 418 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(connector->dev); 419 struct drm_display_mode *mode; 420 421 mode = drm_mode_duplicate(connector->dev, &dbidev->mode); 422 if (!mode) { 423 DRM_ERROR("Failed to duplicate mode\n"); 424 return 0; 425 } 426 427 if (mode->name[0] == '\0') 428 drm_mode_set_name(mode); 429 430 mode->type |= DRM_MODE_TYPE_PREFERRED; 431 drm_mode_probed_add(connector, mode); 432 433 if (mode->width_mm) { 434 connector->display_info.width_mm = mode->width_mm; 435 connector->display_info.height_mm = mode->height_mm; 436 } 437 438 return 1; 439 } 440 441 static const struct drm_connector_helper_funcs mipi_dbi_connector_hfuncs = { 442 .get_modes = mipi_dbi_connector_get_modes, 443 }; 444 445 static const struct drm_connector_funcs mipi_dbi_connector_funcs = { 446 .reset = drm_atomic_helper_connector_reset, 447 .fill_modes = drm_helper_probe_single_connector_modes, 448 .destroy = drm_connector_cleanup, 449 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 450 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 451 }; 452 453 static int mipi_dbi_rotate_mode(struct drm_display_mode *mode, 454 unsigned int rotation) 455 { 456 if (rotation == 0 || rotation == 180) { 457 return 0; 458 } else if (rotation == 90 || rotation == 270) { 459 swap(mode->hdisplay, mode->vdisplay); 460 swap(mode->hsync_start, mode->vsync_start); 461 swap(mode->hsync_end, mode->vsync_end); 462 swap(mode->htotal, mode->vtotal); 463 swap(mode->width_mm, mode->height_mm); 464 return 0; 465 } else { 466 return -EINVAL; 467 } 468 } 469 470 static const struct drm_mode_config_funcs mipi_dbi_mode_config_funcs = { 471 .fb_create = drm_gem_fb_create_with_dirty, 472 .atomic_check = drm_atomic_helper_check, 473 .atomic_commit = drm_atomic_helper_commit, 474 }; 475 476 static const uint32_t mipi_dbi_formats[] = { 477 DRM_FORMAT_RGB565, 478 DRM_FORMAT_XRGB8888, 479 }; 480 481 /** 482 * mipi_dbi_dev_init_with_formats - MIPI DBI device initialization with custom formats 483 * @dbidev: MIPI DBI device structure to initialize 484 * @funcs: Display pipe functions 485 * @formats: Array of supported formats (DRM_FORMAT\_\*). 486 * @format_count: Number of elements in @formats 487 * @mode: Display mode 488 * @rotation: Initial rotation in degrees Counter Clock Wise 489 * @tx_buf_size: Allocate a transmit buffer of this size. 490 * 491 * This function sets up a &drm_simple_display_pipe with a &drm_connector that 492 * has one fixed &drm_display_mode which is rotated according to @rotation. 493 * This mode is used to set the mode config min/max width/height properties. 494 * 495 * Use mipi_dbi_dev_init() if you don't need custom formats. 496 * 497 * Note: 498 * Some of the helper functions expects RGB565 to be the default format and the 499 * transmit buffer sized to fit that. 500 * 501 * Returns: 502 * Zero on success, negative error code on failure. 503 */ 504 int mipi_dbi_dev_init_with_formats(struct mipi_dbi_dev *dbidev, 505 const struct drm_simple_display_pipe_funcs *funcs, 506 const uint32_t *formats, unsigned int format_count, 507 const struct drm_display_mode *mode, 508 unsigned int rotation, size_t tx_buf_size) 509 { 510 static const uint64_t modifiers[] = { 511 DRM_FORMAT_MOD_LINEAR, 512 DRM_FORMAT_MOD_INVALID 513 }; 514 struct drm_device *drm = &dbidev->drm; 515 int ret; 516 517 if (!dbidev->dbi.command) 518 return -EINVAL; 519 520 ret = drmm_mode_config_init(drm); 521 if (ret) 522 return ret; 523 524 dbidev->tx_buf = devm_kmalloc(drm->dev, tx_buf_size, GFP_KERNEL); 525 if (!dbidev->tx_buf) 526 return -ENOMEM; 527 528 drm_mode_copy(&dbidev->mode, mode); 529 ret = mipi_dbi_rotate_mode(&dbidev->mode, rotation); 530 if (ret) { 531 DRM_ERROR("Illegal rotation value %u\n", rotation); 532 return -EINVAL; 533 } 534 535 drm_connector_helper_add(&dbidev->connector, &mipi_dbi_connector_hfuncs); 536 ret = drm_connector_init(drm, &dbidev->connector, &mipi_dbi_connector_funcs, 537 DRM_MODE_CONNECTOR_SPI); 538 if (ret) 539 return ret; 540 541 ret = drm_simple_display_pipe_init(drm, &dbidev->pipe, funcs, formats, format_count, 542 modifiers, &dbidev->connector); 543 if (ret) 544 return ret; 545 546 drm_plane_enable_fb_damage_clips(&dbidev->pipe.plane); 547 548 drm->mode_config.funcs = &mipi_dbi_mode_config_funcs; 549 drm->mode_config.min_width = dbidev->mode.hdisplay; 550 drm->mode_config.max_width = dbidev->mode.hdisplay; 551 drm->mode_config.min_height = dbidev->mode.vdisplay; 552 drm->mode_config.max_height = dbidev->mode.vdisplay; 553 dbidev->rotation = rotation; 554 555 DRM_DEBUG_KMS("rotation = %u\n", rotation); 556 557 return 0; 558 } 559 EXPORT_SYMBOL(mipi_dbi_dev_init_with_formats); 560 561 /** 562 * mipi_dbi_dev_init - MIPI DBI device initialization 563 * @dbidev: MIPI DBI device structure to initialize 564 * @funcs: Display pipe functions 565 * @mode: Display mode 566 * @rotation: Initial rotation in degrees Counter Clock Wise 567 * 568 * This function sets up a &drm_simple_display_pipe with a &drm_connector that 569 * has one fixed &drm_display_mode which is rotated according to @rotation. 570 * This mode is used to set the mode config min/max width/height properties. 571 * Additionally &mipi_dbi.tx_buf is allocated. 572 * 573 * Supported formats: Native RGB565 and emulated XRGB8888. 574 * 575 * Returns: 576 * Zero on success, negative error code on failure. 577 */ 578 int mipi_dbi_dev_init(struct mipi_dbi_dev *dbidev, 579 const struct drm_simple_display_pipe_funcs *funcs, 580 const struct drm_display_mode *mode, unsigned int rotation) 581 { 582 size_t bufsize = mode->vdisplay * mode->hdisplay * sizeof(u16); 583 584 dbidev->drm.mode_config.preferred_depth = 16; 585 586 return mipi_dbi_dev_init_with_formats(dbidev, funcs, mipi_dbi_formats, 587 ARRAY_SIZE(mipi_dbi_formats), mode, 588 rotation, bufsize); 589 } 590 EXPORT_SYMBOL(mipi_dbi_dev_init); 591 592 /** 593 * mipi_dbi_hw_reset - Hardware reset of controller 594 * @dbi: MIPI DBI structure 595 * 596 * Reset controller if the &mipi_dbi->reset gpio is set. 597 */ 598 void mipi_dbi_hw_reset(struct mipi_dbi *dbi) 599 { 600 if (!dbi->reset) 601 return; 602 603 gpiod_set_value_cansleep(dbi->reset, 0); 604 usleep_range(20, 1000); 605 gpiod_set_value_cansleep(dbi->reset, 1); 606 msleep(120); 607 } 608 EXPORT_SYMBOL(mipi_dbi_hw_reset); 609 610 /** 611 * mipi_dbi_display_is_on - Check if display is on 612 * @dbi: MIPI DBI structure 613 * 614 * This function checks the Power Mode register (if readable) to see if 615 * display output is turned on. This can be used to see if the bootloader 616 * has already turned on the display avoiding flicker when the pipeline is 617 * enabled. 618 * 619 * Returns: 620 * true if the display can be verified to be on, false otherwise. 621 */ 622 bool mipi_dbi_display_is_on(struct mipi_dbi *dbi) 623 { 624 u8 val; 625 626 if (mipi_dbi_command_read(dbi, MIPI_DCS_GET_POWER_MODE, &val)) 627 return false; 628 629 val &= ~DCS_POWER_MODE_RESERVED_MASK; 630 631 /* The poweron/reset value is 08h DCS_POWER_MODE_DISPLAY_NORMAL_MODE */ 632 if (val != (DCS_POWER_MODE_DISPLAY | 633 DCS_POWER_MODE_DISPLAY_NORMAL_MODE | DCS_POWER_MODE_SLEEP_MODE)) 634 return false; 635 636 DRM_DEBUG_DRIVER("Display is ON\n"); 637 638 return true; 639 } 640 EXPORT_SYMBOL(mipi_dbi_display_is_on); 641 642 static int mipi_dbi_poweron_reset_conditional(struct mipi_dbi_dev *dbidev, bool cond) 643 { 644 struct device *dev = dbidev->drm.dev; 645 struct mipi_dbi *dbi = &dbidev->dbi; 646 int ret; 647 648 if (dbidev->regulator) { 649 ret = regulator_enable(dbidev->regulator); 650 if (ret) { 651 DRM_DEV_ERROR(dev, "Failed to enable regulator (%d)\n", ret); 652 return ret; 653 } 654 } 655 656 if (cond && mipi_dbi_display_is_on(dbi)) 657 return 1; 658 659 mipi_dbi_hw_reset(dbi); 660 ret = mipi_dbi_command(dbi, MIPI_DCS_SOFT_RESET); 661 if (ret) { 662 DRM_DEV_ERROR(dev, "Failed to send reset command (%d)\n", ret); 663 if (dbidev->regulator) 664 regulator_disable(dbidev->regulator); 665 return ret; 666 } 667 668 /* 669 * If we did a hw reset, we know the controller is in Sleep mode and 670 * per MIPI DSC spec should wait 5ms after soft reset. If we didn't, 671 * we assume worst case and wait 120ms. 672 */ 673 if (dbi->reset) 674 usleep_range(5000, 20000); 675 else 676 msleep(120); 677 678 return 0; 679 } 680 681 /** 682 * mipi_dbi_poweron_reset - MIPI DBI poweron and reset 683 * @dbidev: MIPI DBI device structure 684 * 685 * This function enables the regulator if used and does a hardware and software 686 * reset. 687 * 688 * Returns: 689 * Zero on success, or a negative error code. 690 */ 691 int mipi_dbi_poweron_reset(struct mipi_dbi_dev *dbidev) 692 { 693 return mipi_dbi_poweron_reset_conditional(dbidev, false); 694 } 695 EXPORT_SYMBOL(mipi_dbi_poweron_reset); 696 697 /** 698 * mipi_dbi_poweron_conditional_reset - MIPI DBI poweron and conditional reset 699 * @dbidev: MIPI DBI device structure 700 * 701 * This function enables the regulator if used and if the display is off, it 702 * does a hardware and software reset. If mipi_dbi_display_is_on() determines 703 * that the display is on, no reset is performed. 704 * 705 * Returns: 706 * Zero if the controller was reset, 1 if the display was already on, or a 707 * negative error code. 708 */ 709 int mipi_dbi_poweron_conditional_reset(struct mipi_dbi_dev *dbidev) 710 { 711 return mipi_dbi_poweron_reset_conditional(dbidev, true); 712 } 713 EXPORT_SYMBOL(mipi_dbi_poweron_conditional_reset); 714 715 #if IS_ENABLED(CONFIG_SPI) 716 717 /** 718 * mipi_dbi_spi_cmd_max_speed - get the maximum SPI bus speed 719 * @spi: SPI device 720 * @len: The transfer buffer length. 721 * 722 * Many controllers have a max speed of 10MHz, but can be pushed way beyond 723 * that. Increase reliability by running pixel data at max speed and the rest 724 * at 10MHz, preventing transfer glitches from messing up the init settings. 725 */ 726 u32 mipi_dbi_spi_cmd_max_speed(struct spi_device *spi, size_t len) 727 { 728 if (len > 64) 729 return 0; /* use default */ 730 731 return min_t(u32, 10000000, spi->max_speed_hz); 732 } 733 EXPORT_SYMBOL(mipi_dbi_spi_cmd_max_speed); 734 735 static bool mipi_dbi_machine_little_endian(void) 736 { 737 #if defined(__LITTLE_ENDIAN) 738 return true; 739 #else 740 return false; 741 #endif 742 } 743 744 /* 745 * MIPI DBI Type C Option 1 746 * 747 * If the SPI controller doesn't have 9 bits per word support, 748 * use blocks of 9 bytes to send 8x 9-bit words using a 8-bit SPI transfer. 749 * Pad partial blocks with MIPI_DCS_NOP (zero). 750 * This is how the D/C bit (x) is added: 751 * x7654321 752 * 0x765432 753 * 10x76543 754 * 210x7654 755 * 3210x765 756 * 43210x76 757 * 543210x7 758 * 6543210x 759 * 76543210 760 */ 761 762 static int mipi_dbi_spi1e_transfer(struct mipi_dbi *dbi, int dc, 763 const void *buf, size_t len, 764 unsigned int bpw) 765 { 766 bool swap_bytes = (bpw == 16 && mipi_dbi_machine_little_endian()); 767 size_t chunk, max_chunk = dbi->tx_buf9_len; 768 struct spi_device *spi = dbi->spi; 769 struct spi_transfer tr = { 770 .tx_buf = dbi->tx_buf9, 771 .bits_per_word = 8, 772 }; 773 struct spi_message m; 774 const u8 *src = buf; 775 int i, ret; 776 u8 *dst; 777 778 if (drm_debug_enabled(DRM_UT_DRIVER)) 779 pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n", 780 __func__, dc, max_chunk); 781 782 tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len); 783 spi_message_init_with_transfers(&m, &tr, 1); 784 785 if (!dc) { 786 if (WARN_ON_ONCE(len != 1)) 787 return -EINVAL; 788 789 /* Command: pad no-op's (zeroes) at beginning of block */ 790 dst = dbi->tx_buf9; 791 memset(dst, 0, 9); 792 dst[8] = *src; 793 tr.len = 9; 794 795 return spi_sync(spi, &m); 796 } 797 798 /* max with room for adding one bit per byte */ 799 max_chunk = max_chunk / 9 * 8; 800 /* but no bigger than len */ 801 max_chunk = min(max_chunk, len); 802 /* 8 byte blocks */ 803 max_chunk = max_t(size_t, 8, max_chunk & ~0x7); 804 805 while (len) { 806 size_t added = 0; 807 808 chunk = min(len, max_chunk); 809 len -= chunk; 810 dst = dbi->tx_buf9; 811 812 if (chunk < 8) { 813 u8 val, carry = 0; 814 815 /* Data: pad no-op's (zeroes) at end of block */ 816 memset(dst, 0, 9); 817 818 if (swap_bytes) { 819 for (i = 1; i < (chunk + 1); i++) { 820 val = src[1]; 821 *dst++ = carry | BIT(8 - i) | (val >> i); 822 carry = val << (8 - i); 823 i++; 824 val = src[0]; 825 *dst++ = carry | BIT(8 - i) | (val >> i); 826 carry = val << (8 - i); 827 src += 2; 828 } 829 *dst++ = carry; 830 } else { 831 for (i = 1; i < (chunk + 1); i++) { 832 val = *src++; 833 *dst++ = carry | BIT(8 - i) | (val >> i); 834 carry = val << (8 - i); 835 } 836 *dst++ = carry; 837 } 838 839 chunk = 8; 840 added = 1; 841 } else { 842 for (i = 0; i < chunk; i += 8) { 843 if (swap_bytes) { 844 *dst++ = BIT(7) | (src[1] >> 1); 845 *dst++ = (src[1] << 7) | BIT(6) | (src[0] >> 2); 846 *dst++ = (src[0] << 6) | BIT(5) | (src[3] >> 3); 847 *dst++ = (src[3] << 5) | BIT(4) | (src[2] >> 4); 848 *dst++ = (src[2] << 4) | BIT(3) | (src[5] >> 5); 849 *dst++ = (src[5] << 3) | BIT(2) | (src[4] >> 6); 850 *dst++ = (src[4] << 2) | BIT(1) | (src[7] >> 7); 851 *dst++ = (src[7] << 1) | BIT(0); 852 *dst++ = src[6]; 853 } else { 854 *dst++ = BIT(7) | (src[0] >> 1); 855 *dst++ = (src[0] << 7) | BIT(6) | (src[1] >> 2); 856 *dst++ = (src[1] << 6) | BIT(5) | (src[2] >> 3); 857 *dst++ = (src[2] << 5) | BIT(4) | (src[3] >> 4); 858 *dst++ = (src[3] << 4) | BIT(3) | (src[4] >> 5); 859 *dst++ = (src[4] << 3) | BIT(2) | (src[5] >> 6); 860 *dst++ = (src[5] << 2) | BIT(1) | (src[6] >> 7); 861 *dst++ = (src[6] << 1) | BIT(0); 862 *dst++ = src[7]; 863 } 864 865 src += 8; 866 added++; 867 } 868 } 869 870 tr.len = chunk + added; 871 872 ret = spi_sync(spi, &m); 873 if (ret) 874 return ret; 875 } 876 877 return 0; 878 } 879 880 static int mipi_dbi_spi1_transfer(struct mipi_dbi *dbi, int dc, 881 const void *buf, size_t len, 882 unsigned int bpw) 883 { 884 struct spi_device *spi = dbi->spi; 885 struct spi_transfer tr = { 886 .bits_per_word = 9, 887 }; 888 const u16 *src16 = buf; 889 const u8 *src8 = buf; 890 struct spi_message m; 891 size_t max_chunk; 892 u16 *dst16; 893 int ret; 894 895 if (!spi_is_bpw_supported(spi, 9)) 896 return mipi_dbi_spi1e_transfer(dbi, dc, buf, len, bpw); 897 898 tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len); 899 max_chunk = dbi->tx_buf9_len; 900 dst16 = dbi->tx_buf9; 901 902 if (drm_debug_enabled(DRM_UT_DRIVER)) 903 pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n", 904 __func__, dc, max_chunk); 905 906 max_chunk = min(max_chunk / 2, len); 907 908 spi_message_init_with_transfers(&m, &tr, 1); 909 tr.tx_buf = dst16; 910 911 while (len) { 912 size_t chunk = min(len, max_chunk); 913 unsigned int i; 914 915 if (bpw == 16 && mipi_dbi_machine_little_endian()) { 916 for (i = 0; i < (chunk * 2); i += 2) { 917 dst16[i] = *src16 >> 8; 918 dst16[i + 1] = *src16++ & 0xFF; 919 if (dc) { 920 dst16[i] |= 0x0100; 921 dst16[i + 1] |= 0x0100; 922 } 923 } 924 } else { 925 for (i = 0; i < chunk; i++) { 926 dst16[i] = *src8++; 927 if (dc) 928 dst16[i] |= 0x0100; 929 } 930 } 931 932 tr.len = chunk * 2; 933 len -= chunk; 934 935 ret = spi_sync(spi, &m); 936 if (ret) 937 return ret; 938 } 939 940 return 0; 941 } 942 943 static int mipi_dbi_typec1_command_read(struct mipi_dbi *dbi, u8 *cmd, 944 u8 *data, size_t len) 945 { 946 struct spi_device *spi = dbi->spi; 947 u32 speed_hz = min_t(u32, MIPI_DBI_MAX_SPI_READ_SPEED, 948 spi->max_speed_hz / 2); 949 struct spi_transfer tr[2] = { 950 { 951 .speed_hz = speed_hz, 952 .bits_per_word = 9, 953 .tx_buf = dbi->tx_buf9, 954 .len = 2, 955 }, { 956 .speed_hz = speed_hz, 957 .bits_per_word = 8, 958 .len = len, 959 .rx_buf = data, 960 }, 961 }; 962 struct spi_message m; 963 u16 *dst16; 964 int ret; 965 966 if (!len) 967 return -EINVAL; 968 969 if (!spi_is_bpw_supported(spi, 9)) { 970 /* 971 * FIXME: implement something like mipi_dbi_spi1e_transfer() but 972 * for reads using emulation. 973 */ 974 dev_err(&spi->dev, 975 "reading on host not supporting 9 bpw not yet implemented\n"); 976 return -EOPNOTSUPP; 977 } 978 979 /* 980 * Turn the 8bit command into a 16bit version of the command in the 981 * buffer. Only 9 bits of this will be used when executing the actual 982 * transfer. 983 */ 984 dst16 = dbi->tx_buf9; 985 dst16[0] = *cmd; 986 987 spi_message_init_with_transfers(&m, tr, ARRAY_SIZE(tr)); 988 ret = spi_sync(spi, &m); 989 990 if (!ret) 991 MIPI_DBI_DEBUG_COMMAND(*cmd, data, len); 992 993 return ret; 994 } 995 996 static int mipi_dbi_typec1_command(struct mipi_dbi *dbi, u8 *cmd, 997 u8 *parameters, size_t num) 998 { 999 unsigned int bpw = (*cmd == MIPI_DCS_WRITE_MEMORY_START) ? 16 : 8; 1000 int ret; 1001 1002 if (mipi_dbi_command_is_read(dbi, *cmd)) 1003 return mipi_dbi_typec1_command_read(dbi, cmd, parameters, num); 1004 1005 MIPI_DBI_DEBUG_COMMAND(*cmd, parameters, num); 1006 1007 ret = mipi_dbi_spi1_transfer(dbi, 0, cmd, 1, 8); 1008 if (ret || !num) 1009 return ret; 1010 1011 return mipi_dbi_spi1_transfer(dbi, 1, parameters, num, bpw); 1012 } 1013 1014 /* MIPI DBI Type C Option 3 */ 1015 1016 static int mipi_dbi_typec3_command_read(struct mipi_dbi *dbi, u8 *cmd, 1017 u8 *data, size_t len) 1018 { 1019 struct spi_device *spi = dbi->spi; 1020 u32 speed_hz = min_t(u32, MIPI_DBI_MAX_SPI_READ_SPEED, 1021 spi->max_speed_hz / 2); 1022 struct spi_transfer tr[2] = { 1023 { 1024 .speed_hz = speed_hz, 1025 .tx_buf = cmd, 1026 .len = 1, 1027 }, { 1028 .speed_hz = speed_hz, 1029 .len = len, 1030 }, 1031 }; 1032 struct spi_message m; 1033 u8 *buf; 1034 int ret; 1035 1036 if (!len) 1037 return -EINVAL; 1038 1039 /* 1040 * Support non-standard 24-bit and 32-bit Nokia read commands which 1041 * start with a dummy clock, so we need to read an extra byte. 1042 */ 1043 if (*cmd == MIPI_DCS_GET_DISPLAY_ID || 1044 *cmd == MIPI_DCS_GET_DISPLAY_STATUS) { 1045 if (!(len == 3 || len == 4)) 1046 return -EINVAL; 1047 1048 tr[1].len = len + 1; 1049 } 1050 1051 buf = kmalloc(tr[1].len, GFP_KERNEL); 1052 if (!buf) 1053 return -ENOMEM; 1054 1055 tr[1].rx_buf = buf; 1056 gpiod_set_value_cansleep(dbi->dc, 0); 1057 1058 spi_message_init_with_transfers(&m, tr, ARRAY_SIZE(tr)); 1059 ret = spi_sync(spi, &m); 1060 if (ret) 1061 goto err_free; 1062 1063 if (tr[1].len == len) { 1064 memcpy(data, buf, len); 1065 } else { 1066 unsigned int i; 1067 1068 for (i = 0; i < len; i++) 1069 data[i] = (buf[i] << 1) | (buf[i + 1] >> 7); 1070 } 1071 1072 MIPI_DBI_DEBUG_COMMAND(*cmd, data, len); 1073 1074 err_free: 1075 kfree(buf); 1076 1077 return ret; 1078 } 1079 1080 static int mipi_dbi_typec3_command(struct mipi_dbi *dbi, u8 *cmd, 1081 u8 *par, size_t num) 1082 { 1083 struct spi_device *spi = dbi->spi; 1084 unsigned int bpw = 8; 1085 u32 speed_hz; 1086 int ret; 1087 1088 if (mipi_dbi_command_is_read(dbi, *cmd)) 1089 return mipi_dbi_typec3_command_read(dbi, cmd, par, num); 1090 1091 MIPI_DBI_DEBUG_COMMAND(*cmd, par, num); 1092 1093 gpiod_set_value_cansleep(dbi->dc, 0); 1094 speed_hz = mipi_dbi_spi_cmd_max_speed(spi, 1); 1095 ret = mipi_dbi_spi_transfer(spi, speed_hz, 8, cmd, 1); 1096 if (ret || !num) 1097 return ret; 1098 1099 if (*cmd == MIPI_DCS_WRITE_MEMORY_START && !dbi->swap_bytes) 1100 bpw = 16; 1101 1102 gpiod_set_value_cansleep(dbi->dc, 1); 1103 speed_hz = mipi_dbi_spi_cmd_max_speed(spi, num); 1104 1105 return mipi_dbi_spi_transfer(spi, speed_hz, bpw, par, num); 1106 } 1107 1108 /** 1109 * mipi_dbi_spi_init - Initialize MIPI DBI SPI interface 1110 * @spi: SPI device 1111 * @dbi: MIPI DBI structure to initialize 1112 * @dc: D/C gpio (optional) 1113 * 1114 * This function sets &mipi_dbi->command, enables &mipi_dbi->read_commands for the 1115 * usual read commands. It should be followed by a call to mipi_dbi_dev_init() or 1116 * a driver-specific init. 1117 * 1118 * If @dc is set, a Type C Option 3 interface is assumed, if not 1119 * Type C Option 1. 1120 * 1121 * If the SPI master driver doesn't support the necessary bits per word, 1122 * the following transformation is used: 1123 * 1124 * - 9-bit: reorder buffer as 9x 8-bit words, padded with no-op command. 1125 * - 16-bit: if big endian send as 8-bit, if little endian swap bytes 1126 * 1127 * Returns: 1128 * Zero on success, negative error code on failure. 1129 */ 1130 int mipi_dbi_spi_init(struct spi_device *spi, struct mipi_dbi *dbi, 1131 struct gpio_desc *dc) 1132 { 1133 struct device *dev = &spi->dev; 1134 int ret; 1135 1136 /* 1137 * Even though it's not the SPI device that does DMA (the master does), 1138 * the dma mask is necessary for the dma_alloc_wc() in the GEM code 1139 * (e.g., drm_gem_cma_create()). The dma_addr returned will be a physical 1140 * address which might be different from the bus address, but this is 1141 * not a problem since the address will not be used. 1142 * The virtual address is used in the transfer and the SPI core 1143 * re-maps it on the SPI master device using the DMA streaming API 1144 * (spi_map_buf()). 1145 */ 1146 if (!dev->coherent_dma_mask) { 1147 ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32)); 1148 if (ret) { 1149 dev_warn(dev, "Failed to set dma mask %d\n", ret); 1150 return ret; 1151 } 1152 } 1153 1154 dbi->spi = spi; 1155 dbi->read_commands = mipi_dbi_dcs_read_commands; 1156 1157 if (dc) { 1158 dbi->command = mipi_dbi_typec3_command; 1159 dbi->dc = dc; 1160 if (mipi_dbi_machine_little_endian() && !spi_is_bpw_supported(spi, 16)) 1161 dbi->swap_bytes = true; 1162 } else { 1163 dbi->command = mipi_dbi_typec1_command; 1164 dbi->tx_buf9_len = SZ_16K; 1165 dbi->tx_buf9 = devm_kmalloc(dev, dbi->tx_buf9_len, GFP_KERNEL); 1166 if (!dbi->tx_buf9) 1167 return -ENOMEM; 1168 } 1169 1170 mutex_init(&dbi->cmdlock); 1171 1172 DRM_DEBUG_DRIVER("SPI speed: %uMHz\n", spi->max_speed_hz / 1000000); 1173 1174 return 0; 1175 } 1176 EXPORT_SYMBOL(mipi_dbi_spi_init); 1177 1178 /** 1179 * mipi_dbi_spi_transfer - SPI transfer helper 1180 * @spi: SPI device 1181 * @speed_hz: Override speed (optional) 1182 * @bpw: Bits per word 1183 * @buf: Buffer to transfer 1184 * @len: Buffer length 1185 * 1186 * This SPI transfer helper breaks up the transfer of @buf into chunks which 1187 * the SPI controller driver can handle. 1188 * 1189 * Returns: 1190 * Zero on success, negative error code on failure. 1191 */ 1192 int mipi_dbi_spi_transfer(struct spi_device *spi, u32 speed_hz, 1193 u8 bpw, const void *buf, size_t len) 1194 { 1195 size_t max_chunk = spi_max_transfer_size(spi); 1196 struct spi_transfer tr = { 1197 .bits_per_word = bpw, 1198 .speed_hz = speed_hz, 1199 }; 1200 struct spi_message m; 1201 size_t chunk; 1202 int ret; 1203 1204 /* In __spi_validate, there's a validation that no partial transfers 1205 * are accepted (xfer->len % w_size must be zero). 1206 * Here we align max_chunk to multiple of 2 (16bits), 1207 * to prevent transfers from being rejected. 1208 */ 1209 max_chunk = ALIGN_DOWN(max_chunk, 2); 1210 1211 spi_message_init_with_transfers(&m, &tr, 1); 1212 1213 while (len) { 1214 chunk = min(len, max_chunk); 1215 1216 tr.tx_buf = buf; 1217 tr.len = chunk; 1218 buf += chunk; 1219 len -= chunk; 1220 1221 ret = spi_sync(spi, &m); 1222 if (ret) 1223 return ret; 1224 } 1225 1226 return 0; 1227 } 1228 EXPORT_SYMBOL(mipi_dbi_spi_transfer); 1229 1230 #endif /* CONFIG_SPI */ 1231 1232 #ifdef CONFIG_DEBUG_FS 1233 1234 static ssize_t mipi_dbi_debugfs_command_write(struct file *file, 1235 const char __user *ubuf, 1236 size_t count, loff_t *ppos) 1237 { 1238 struct seq_file *m = file->private_data; 1239 struct mipi_dbi_dev *dbidev = m->private; 1240 u8 val, cmd = 0, parameters[64]; 1241 char *buf, *pos, *token; 1242 int i, ret, idx; 1243 1244 if (!drm_dev_enter(&dbidev->drm, &idx)) 1245 return -ENODEV; 1246 1247 buf = memdup_user_nul(ubuf, count); 1248 if (IS_ERR(buf)) { 1249 ret = PTR_ERR(buf); 1250 goto err_exit; 1251 } 1252 1253 /* strip trailing whitespace */ 1254 for (i = count - 1; i > 0; i--) 1255 if (isspace(buf[i])) 1256 buf[i] = '\0'; 1257 else 1258 break; 1259 i = 0; 1260 pos = buf; 1261 while (pos) { 1262 token = strsep(&pos, " "); 1263 if (!token) { 1264 ret = -EINVAL; 1265 goto err_free; 1266 } 1267 1268 ret = kstrtou8(token, 16, &val); 1269 if (ret < 0) 1270 goto err_free; 1271 1272 if (token == buf) 1273 cmd = val; 1274 else 1275 parameters[i++] = val; 1276 1277 if (i == 64) { 1278 ret = -E2BIG; 1279 goto err_free; 1280 } 1281 } 1282 1283 ret = mipi_dbi_command_buf(&dbidev->dbi, cmd, parameters, i); 1284 1285 err_free: 1286 kfree(buf); 1287 err_exit: 1288 drm_dev_exit(idx); 1289 1290 return ret < 0 ? ret : count; 1291 } 1292 1293 static int mipi_dbi_debugfs_command_show(struct seq_file *m, void *unused) 1294 { 1295 struct mipi_dbi_dev *dbidev = m->private; 1296 struct mipi_dbi *dbi = &dbidev->dbi; 1297 u8 cmd, val[4]; 1298 int ret, idx; 1299 size_t len; 1300 1301 if (!drm_dev_enter(&dbidev->drm, &idx)) 1302 return -ENODEV; 1303 1304 for (cmd = 0; cmd < 255; cmd++) { 1305 if (!mipi_dbi_command_is_read(dbi, cmd)) 1306 continue; 1307 1308 switch (cmd) { 1309 case MIPI_DCS_READ_MEMORY_START: 1310 case MIPI_DCS_READ_MEMORY_CONTINUE: 1311 len = 2; 1312 break; 1313 case MIPI_DCS_GET_DISPLAY_ID: 1314 len = 3; 1315 break; 1316 case MIPI_DCS_GET_DISPLAY_STATUS: 1317 len = 4; 1318 break; 1319 default: 1320 len = 1; 1321 break; 1322 } 1323 1324 seq_printf(m, "%02x: ", cmd); 1325 ret = mipi_dbi_command_buf(dbi, cmd, val, len); 1326 if (ret) { 1327 seq_puts(m, "XX\n"); 1328 continue; 1329 } 1330 seq_printf(m, "%*phN\n", (int)len, val); 1331 } 1332 1333 drm_dev_exit(idx); 1334 1335 return 0; 1336 } 1337 1338 static int mipi_dbi_debugfs_command_open(struct inode *inode, 1339 struct file *file) 1340 { 1341 return single_open(file, mipi_dbi_debugfs_command_show, 1342 inode->i_private); 1343 } 1344 1345 static const struct file_operations mipi_dbi_debugfs_command_fops = { 1346 .owner = THIS_MODULE, 1347 .open = mipi_dbi_debugfs_command_open, 1348 .read = seq_read, 1349 .llseek = seq_lseek, 1350 .release = single_release, 1351 .write = mipi_dbi_debugfs_command_write, 1352 }; 1353 1354 /** 1355 * mipi_dbi_debugfs_init - Create debugfs entries 1356 * @minor: DRM minor 1357 * 1358 * This function creates a 'command' debugfs file for sending commands to the 1359 * controller or getting the read command values. 1360 * Drivers can use this as their &drm_driver->debugfs_init callback. 1361 * 1362 */ 1363 void mipi_dbi_debugfs_init(struct drm_minor *minor) 1364 { 1365 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(minor->dev); 1366 umode_t mode = S_IFREG | S_IWUSR; 1367 1368 if (dbidev->dbi.read_commands) 1369 mode |= S_IRUGO; 1370 debugfs_create_file("command", mode, minor->debugfs_root, dbidev, 1371 &mipi_dbi_debugfs_command_fops); 1372 } 1373 EXPORT_SYMBOL(mipi_dbi_debugfs_init); 1374 1375 #endif 1376 1377 MODULE_LICENSE("GPL"); 1378