1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * MIPI Display Bus Interface (DBI) LCD controller support 4 * 5 * Copyright 2016 Noralf Trønnes 6 */ 7 8 #include <linux/backlight.h> 9 #include <linux/debugfs.h> 10 #include <linux/delay.h> 11 #include <linux/export.h> 12 #include <linux/gpio/consumer.h> 13 #include <linux/module.h> 14 #include <linux/regulator/consumer.h> 15 #include <linux/spi/spi.h> 16 17 #include <drm/drm_connector.h> 18 #include <drm/drm_damage_helper.h> 19 #include <drm/drm_drv.h> 20 #include <drm/drm_file.h> 21 #include <drm/drm_format_helper.h> 22 #include <drm/drm_fourcc.h> 23 #include <drm/drm_framebuffer.h> 24 #include <drm/drm_gem.h> 25 #include <drm/drm_gem_atomic_helper.h> 26 #include <drm/drm_gem_framebuffer_helper.h> 27 #include <drm/drm_mipi_dbi.h> 28 #include <drm/drm_modes.h> 29 #include <drm/drm_probe_helper.h> 30 #include <drm/drm_rect.h> 31 #include <video/mipi_display.h> 32 33 #define MIPI_DBI_MAX_SPI_READ_SPEED 2000000 /* 2MHz */ 34 35 #define DCS_POWER_MODE_DISPLAY BIT(2) 36 #define DCS_POWER_MODE_DISPLAY_NORMAL_MODE BIT(3) 37 #define DCS_POWER_MODE_SLEEP_MODE BIT(4) 38 #define DCS_POWER_MODE_PARTIAL_MODE BIT(5) 39 #define DCS_POWER_MODE_IDLE_MODE BIT(6) 40 #define DCS_POWER_MODE_RESERVED_MASK (BIT(0) | BIT(1) | BIT(7)) 41 42 /** 43 * DOC: overview 44 * 45 * This library provides helpers for MIPI Display Bus Interface (DBI) 46 * compatible display controllers. 47 * 48 * Many controllers for tiny lcd displays are MIPI compliant and can use this 49 * library. If a controller uses registers 0x2A and 0x2B to set the area to 50 * update and uses register 0x2C to write to frame memory, it is most likely 51 * MIPI compliant. 52 * 53 * Only MIPI Type 1 displays are supported since a full frame memory is needed. 54 * 55 * There are 3 MIPI DBI implementation types: 56 * 57 * A. Motorola 6800 type parallel bus 58 * 59 * B. Intel 8080 type parallel bus 60 * 61 * C. SPI type with 3 options: 62 * 63 * 1. 9-bit with the Data/Command signal as the ninth bit 64 * 2. Same as above except it's sent as 16 bits 65 * 3. 8-bit with the Data/Command signal as a separate D/CX pin 66 * 67 * Currently mipi_dbi only supports Type C options 1 and 3 with 68 * mipi_dbi_spi_init(). 69 */ 70 71 #define MIPI_DBI_DEBUG_COMMAND(cmd, data, len) \ 72 ({ \ 73 if (!len) \ 74 DRM_DEBUG_DRIVER("cmd=%02x\n", cmd); \ 75 else if (len <= 32) \ 76 DRM_DEBUG_DRIVER("cmd=%02x, par=%*ph\n", cmd, (int)len, data);\ 77 else \ 78 DRM_DEBUG_DRIVER("cmd=%02x, len=%zu\n", cmd, len); \ 79 }) 80 81 static const u8 mipi_dbi_dcs_read_commands[] = { 82 MIPI_DCS_GET_DISPLAY_ID, 83 MIPI_DCS_GET_RED_CHANNEL, 84 MIPI_DCS_GET_GREEN_CHANNEL, 85 MIPI_DCS_GET_BLUE_CHANNEL, 86 MIPI_DCS_GET_DISPLAY_STATUS, 87 MIPI_DCS_GET_POWER_MODE, 88 MIPI_DCS_GET_ADDRESS_MODE, 89 MIPI_DCS_GET_PIXEL_FORMAT, 90 MIPI_DCS_GET_DISPLAY_MODE, 91 MIPI_DCS_GET_SIGNAL_MODE, 92 MIPI_DCS_GET_DIAGNOSTIC_RESULT, 93 MIPI_DCS_READ_MEMORY_START, 94 MIPI_DCS_READ_MEMORY_CONTINUE, 95 MIPI_DCS_GET_SCANLINE, 96 MIPI_DCS_GET_DISPLAY_BRIGHTNESS, 97 MIPI_DCS_GET_CONTROL_DISPLAY, 98 MIPI_DCS_GET_POWER_SAVE, 99 MIPI_DCS_GET_CABC_MIN_BRIGHTNESS, 100 MIPI_DCS_READ_DDB_START, 101 MIPI_DCS_READ_DDB_CONTINUE, 102 0, /* sentinel */ 103 }; 104 105 static bool mipi_dbi_command_is_read(struct mipi_dbi *dbi, u8 cmd) 106 { 107 unsigned int i; 108 109 if (!dbi->read_commands) 110 return false; 111 112 for (i = 0; i < 0xff; i++) { 113 if (!dbi->read_commands[i]) 114 return false; 115 if (cmd == dbi->read_commands[i]) 116 return true; 117 } 118 119 return false; 120 } 121 122 /** 123 * mipi_dbi_command_read - MIPI DCS read command 124 * @dbi: MIPI DBI structure 125 * @cmd: Command 126 * @val: Value read 127 * 128 * Send MIPI DCS read command to the controller. 129 * 130 * Returns: 131 * Zero on success, negative error code on failure. 132 */ 133 int mipi_dbi_command_read(struct mipi_dbi *dbi, u8 cmd, u8 *val) 134 { 135 if (!dbi->read_commands) 136 return -EACCES; 137 138 if (!mipi_dbi_command_is_read(dbi, cmd)) 139 return -EINVAL; 140 141 return mipi_dbi_command_buf(dbi, cmd, val, 1); 142 } 143 EXPORT_SYMBOL(mipi_dbi_command_read); 144 145 /** 146 * mipi_dbi_command_buf - MIPI DCS command with parameter(s) in an array 147 * @dbi: MIPI DBI structure 148 * @cmd: Command 149 * @data: Parameter buffer 150 * @len: Buffer length 151 * 152 * Returns: 153 * Zero on success, negative error code on failure. 154 */ 155 int mipi_dbi_command_buf(struct mipi_dbi *dbi, u8 cmd, u8 *data, size_t len) 156 { 157 u8 *cmdbuf; 158 int ret; 159 160 /* SPI requires dma-safe buffers */ 161 cmdbuf = kmemdup(&cmd, 1, GFP_KERNEL); 162 if (!cmdbuf) 163 return -ENOMEM; 164 165 mutex_lock(&dbi->cmdlock); 166 ret = dbi->command(dbi, cmdbuf, data, len); 167 mutex_unlock(&dbi->cmdlock); 168 169 kfree(cmdbuf); 170 171 return ret; 172 } 173 EXPORT_SYMBOL(mipi_dbi_command_buf); 174 175 /* This should only be used by mipi_dbi_command() */ 176 int mipi_dbi_command_stackbuf(struct mipi_dbi *dbi, u8 cmd, const u8 *data, 177 size_t len) 178 { 179 u8 *buf; 180 int ret; 181 182 buf = kmemdup(data, len, GFP_KERNEL); 183 if (!buf) 184 return -ENOMEM; 185 186 ret = mipi_dbi_command_buf(dbi, cmd, buf, len); 187 188 kfree(buf); 189 190 return ret; 191 } 192 EXPORT_SYMBOL(mipi_dbi_command_stackbuf); 193 194 /** 195 * mipi_dbi_buf_copy - Copy a framebuffer, transforming it if necessary 196 * @dst: The destination buffer 197 * @src: The source buffer 198 * @fb: The source framebuffer 199 * @clip: Clipping rectangle of the area to be copied 200 * @swap: When true, swap MSB/LSB of 16-bit values 201 * @fmtcnv_state: Format-conversion state 202 * 203 * Returns: 204 * Zero on success, negative error code on failure. 205 */ 206 int mipi_dbi_buf_copy(void *dst, struct iosys_map *src, struct drm_framebuffer *fb, 207 struct drm_rect *clip, bool swap, 208 struct drm_format_conv_state *fmtcnv_state) 209 { 210 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(fb->dev); 211 struct drm_gem_object *gem = drm_gem_fb_get_obj(fb, 0); 212 struct iosys_map dst_map = IOSYS_MAP_INIT_VADDR(dst); 213 int ret; 214 215 ret = drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE); 216 if (ret) 217 return ret; 218 219 switch (fb->format->format) { 220 case DRM_FORMAT_RGB565: 221 if (swap) 222 drm_fb_swab(&dst_map, NULL, src, fb, clip, !drm_gem_is_imported(gem), 223 fmtcnv_state); 224 else 225 drm_fb_memcpy(&dst_map, NULL, src, fb, clip); 226 break; 227 case DRM_FORMAT_RGB888: 228 drm_fb_memcpy(&dst_map, NULL, src, fb, clip); 229 break; 230 case DRM_FORMAT_XRGB8888: 231 switch (dbidev->pixel_format) { 232 case DRM_FORMAT_RGB565: 233 drm_fb_xrgb8888_to_rgb565(&dst_map, NULL, src, fb, clip, fmtcnv_state, swap); 234 break; 235 case DRM_FORMAT_RGB888: 236 drm_fb_xrgb8888_to_rgb888(&dst_map, NULL, src, fb, clip, fmtcnv_state); 237 break; 238 } 239 break; 240 default: 241 drm_err_once(fb->dev, "Format is not supported: %p4cc\n", 242 &fb->format->format); 243 ret = -EINVAL; 244 } 245 246 drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE); 247 248 return ret; 249 } 250 EXPORT_SYMBOL(mipi_dbi_buf_copy); 251 252 static void mipi_dbi_set_window_address(struct mipi_dbi_dev *dbidev, 253 unsigned int xs, unsigned int xe, 254 unsigned int ys, unsigned int ye) 255 { 256 struct mipi_dbi *dbi = &dbidev->dbi; 257 258 xs += dbidev->left_offset; 259 xe += dbidev->left_offset; 260 ys += dbidev->top_offset; 261 ye += dbidev->top_offset; 262 263 mipi_dbi_command(dbi, MIPI_DCS_SET_COLUMN_ADDRESS, (xs >> 8) & 0xff, 264 xs & 0xff, (xe >> 8) & 0xff, xe & 0xff); 265 mipi_dbi_command(dbi, MIPI_DCS_SET_PAGE_ADDRESS, (ys >> 8) & 0xff, 266 ys & 0xff, (ye >> 8) & 0xff, ye & 0xff); 267 } 268 269 static void mipi_dbi_fb_dirty(struct iosys_map *src, struct drm_framebuffer *fb, 270 struct drm_rect *rect, struct drm_format_conv_state *fmtcnv_state) 271 { 272 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(fb->dev); 273 unsigned int height = rect->y2 - rect->y1; 274 unsigned int width = rect->x2 - rect->x1; 275 const struct drm_format_info *dst_format; 276 struct mipi_dbi *dbi = &dbidev->dbi; 277 bool swap = dbi->swap_bytes; 278 int ret = 0; 279 size_t len; 280 bool full; 281 void *tr; 282 283 full = width == fb->width && height == fb->height; 284 285 DRM_DEBUG_KMS("Flushing [FB:%d] " DRM_RECT_FMT "\n", fb->base.id, DRM_RECT_ARG(rect)); 286 287 if (!dbi->dc || !full || swap || 288 fb->format->format == DRM_FORMAT_XRGB8888) { 289 tr = dbidev->tx_buf; 290 ret = mipi_dbi_buf_copy(tr, src, fb, rect, swap, fmtcnv_state); 291 if (ret) 292 goto err_msg; 293 } else { 294 tr = src->vaddr; /* TODO: Use mapping abstraction properly */ 295 } 296 297 mipi_dbi_set_window_address(dbidev, rect->x1, rect->x2 - 1, rect->y1, 298 rect->y2 - 1); 299 300 if (fb->format->format == DRM_FORMAT_XRGB8888) 301 dst_format = drm_format_info(dbidev->pixel_format); 302 else 303 dst_format = fb->format; 304 len = drm_format_info_min_pitch(dst_format, 0, width) * height; 305 306 ret = mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START, tr, len); 307 err_msg: 308 if (ret) 309 drm_err_once(fb->dev, "Failed to update display %d\n", ret); 310 } 311 312 /** 313 * mipi_dbi_pipe_mode_valid - MIPI DBI mode-valid helper 314 * @pipe: Simple display pipe 315 * @mode: The mode to test 316 * 317 * This function validates a given display mode against the MIPI DBI's hardware 318 * display. Drivers can use this as their &drm_simple_display_pipe_funcs->mode_valid 319 * callback. 320 */ 321 enum drm_mode_status mipi_dbi_pipe_mode_valid(struct drm_simple_display_pipe *pipe, 322 const struct drm_display_mode *mode) 323 { 324 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev); 325 326 return drm_crtc_helper_mode_valid_fixed(&pipe->crtc, mode, &dbidev->mode); 327 } 328 EXPORT_SYMBOL(mipi_dbi_pipe_mode_valid); 329 330 /** 331 * mipi_dbi_pipe_update - Display pipe update helper 332 * @pipe: Simple display pipe 333 * @old_state: Old plane state 334 * 335 * This function handles framebuffer flushing and vblank events. Drivers can use 336 * this as their &drm_simple_display_pipe_funcs->update callback. 337 */ 338 void mipi_dbi_pipe_update(struct drm_simple_display_pipe *pipe, 339 struct drm_plane_state *old_state) 340 { 341 struct drm_plane_state *state = pipe->plane.state; 342 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(state); 343 struct drm_framebuffer *fb = state->fb; 344 struct drm_rect rect; 345 int idx; 346 347 if (!pipe->crtc.state->active) 348 return; 349 350 if (WARN_ON(!fb)) 351 return; 352 353 if (!drm_dev_enter(fb->dev, &idx)) 354 return; 355 356 if (drm_atomic_helper_damage_merged(old_state, state, &rect)) 357 mipi_dbi_fb_dirty(&shadow_plane_state->data[0], fb, &rect, 358 &shadow_plane_state->fmtcnv_state); 359 360 drm_dev_exit(idx); 361 } 362 EXPORT_SYMBOL(mipi_dbi_pipe_update); 363 364 /** 365 * mipi_dbi_enable_flush - MIPI DBI enable helper 366 * @dbidev: MIPI DBI device structure 367 * @crtc_state: CRTC state 368 * @plane_state: Plane state 369 * 370 * Flushes the whole framebuffer and enables the backlight. Drivers can use this 371 * in their &drm_simple_display_pipe_funcs->enable callback. 372 * 373 * Note: Drivers which don't use mipi_dbi_pipe_update() because they have custom 374 * framebuffer flushing, can't use this function since they both use the same 375 * flushing code. 376 */ 377 void mipi_dbi_enable_flush(struct mipi_dbi_dev *dbidev, 378 struct drm_crtc_state *crtc_state, 379 struct drm_plane_state *plane_state) 380 { 381 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state); 382 struct drm_framebuffer *fb = plane_state->fb; 383 struct drm_rect rect = { 384 .x1 = 0, 385 .x2 = fb->width, 386 .y1 = 0, 387 .y2 = fb->height, 388 }; 389 int idx; 390 391 if (!drm_dev_enter(&dbidev->drm, &idx)) 392 return; 393 394 mipi_dbi_fb_dirty(&shadow_plane_state->data[0], fb, &rect, 395 &shadow_plane_state->fmtcnv_state); 396 backlight_enable(dbidev->backlight); 397 398 drm_dev_exit(idx); 399 } 400 EXPORT_SYMBOL(mipi_dbi_enable_flush); 401 402 static void mipi_dbi_blank(struct mipi_dbi_dev *dbidev) 403 { 404 struct drm_device *drm = &dbidev->drm; 405 u16 height = drm->mode_config.min_height; 406 u16 width = drm->mode_config.min_width; 407 struct mipi_dbi *dbi = &dbidev->dbi; 408 const struct drm_format_info *dst_format; 409 size_t len; 410 int idx; 411 412 if (!drm_dev_enter(drm, &idx)) 413 return; 414 415 dst_format = drm_format_info(dbidev->pixel_format); 416 len = drm_format_info_min_pitch(dst_format, 0, width) * height; 417 418 memset(dbidev->tx_buf, 0, len); 419 420 mipi_dbi_set_window_address(dbidev, 0, width - 1, 0, height - 1); 421 mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START, 422 (u8 *)dbidev->tx_buf, len); 423 424 drm_dev_exit(idx); 425 } 426 427 /** 428 * mipi_dbi_pipe_disable - MIPI DBI pipe disable helper 429 * @pipe: Display pipe 430 * 431 * This function disables backlight if present, if not the display memory is 432 * blanked. The regulator is disabled if in use. Drivers can use this as their 433 * &drm_simple_display_pipe_funcs->disable callback. 434 */ 435 void mipi_dbi_pipe_disable(struct drm_simple_display_pipe *pipe) 436 { 437 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev); 438 439 DRM_DEBUG_KMS("\n"); 440 441 if (dbidev->backlight) 442 backlight_disable(dbidev->backlight); 443 else 444 mipi_dbi_blank(dbidev); 445 446 if (dbidev->regulator) 447 regulator_disable(dbidev->regulator); 448 if (dbidev->io_regulator) 449 regulator_disable(dbidev->io_regulator); 450 } 451 EXPORT_SYMBOL(mipi_dbi_pipe_disable); 452 453 /** 454 * mipi_dbi_pipe_begin_fb_access - MIPI DBI pipe begin-access helper 455 * @pipe: Display pipe 456 * @plane_state: Plane state 457 * 458 * This function implements struct &drm_simple_display_funcs.begin_fb_access. 459 * 460 * See drm_gem_begin_shadow_fb_access() for details and mipi_dbi_pipe_cleanup_fb() 461 * for cleanup. 462 * 463 * Returns: 464 * 0 on success, or a negative errno code otherwise. 465 */ 466 int mipi_dbi_pipe_begin_fb_access(struct drm_simple_display_pipe *pipe, 467 struct drm_plane_state *plane_state) 468 { 469 return drm_gem_begin_shadow_fb_access(&pipe->plane, plane_state); 470 } 471 EXPORT_SYMBOL(mipi_dbi_pipe_begin_fb_access); 472 473 /** 474 * mipi_dbi_pipe_end_fb_access - MIPI DBI pipe end-access helper 475 * @pipe: Display pipe 476 * @plane_state: Plane state 477 * 478 * This function implements struct &drm_simple_display_funcs.end_fb_access. 479 * 480 * See mipi_dbi_pipe_begin_fb_access(). 481 */ 482 void mipi_dbi_pipe_end_fb_access(struct drm_simple_display_pipe *pipe, 483 struct drm_plane_state *plane_state) 484 { 485 drm_gem_end_shadow_fb_access(&pipe->plane, plane_state); 486 } 487 EXPORT_SYMBOL(mipi_dbi_pipe_end_fb_access); 488 489 /** 490 * mipi_dbi_pipe_reset_plane - MIPI DBI plane-reset helper 491 * @pipe: Display pipe 492 * 493 * This function implements struct &drm_simple_display_funcs.reset_plane 494 * for MIPI DBI planes. 495 */ 496 void mipi_dbi_pipe_reset_plane(struct drm_simple_display_pipe *pipe) 497 { 498 drm_gem_reset_shadow_plane(&pipe->plane); 499 } 500 EXPORT_SYMBOL(mipi_dbi_pipe_reset_plane); 501 502 /** 503 * mipi_dbi_pipe_duplicate_plane_state - duplicates MIPI DBI plane state 504 * @pipe: Display pipe 505 * 506 * This function implements struct &drm_simple_display_funcs.duplicate_plane_state 507 * for MIPI DBI planes. 508 * 509 * See drm_gem_duplicate_shadow_plane_state() for additional details. 510 * 511 * Returns: 512 * A pointer to a new plane state on success, or NULL otherwise. 513 */ 514 struct drm_plane_state *mipi_dbi_pipe_duplicate_plane_state(struct drm_simple_display_pipe *pipe) 515 { 516 return drm_gem_duplicate_shadow_plane_state(&pipe->plane); 517 } 518 EXPORT_SYMBOL(mipi_dbi_pipe_duplicate_plane_state); 519 520 /** 521 * mipi_dbi_pipe_destroy_plane_state - cleans up MIPI DBI plane state 522 * @pipe: Display pipe 523 * @plane_state: Plane state 524 * 525 * This function implements struct drm_simple_display_funcs.destroy_plane_state 526 * for MIPI DBI planes. 527 * 528 * See drm_gem_destroy_shadow_plane_state() for additional details. 529 */ 530 void mipi_dbi_pipe_destroy_plane_state(struct drm_simple_display_pipe *pipe, 531 struct drm_plane_state *plane_state) 532 { 533 drm_gem_destroy_shadow_plane_state(&pipe->plane, plane_state); 534 } 535 EXPORT_SYMBOL(mipi_dbi_pipe_destroy_plane_state); 536 537 static int mipi_dbi_connector_get_modes(struct drm_connector *connector) 538 { 539 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(connector->dev); 540 541 return drm_connector_helper_get_modes_fixed(connector, &dbidev->mode); 542 } 543 544 static const struct drm_connector_helper_funcs mipi_dbi_connector_hfuncs = { 545 .get_modes = mipi_dbi_connector_get_modes, 546 }; 547 548 static const struct drm_connector_funcs mipi_dbi_connector_funcs = { 549 .reset = drm_atomic_helper_connector_reset, 550 .fill_modes = drm_helper_probe_single_connector_modes, 551 .destroy = drm_connector_cleanup, 552 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 553 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 554 }; 555 556 static int mipi_dbi_rotate_mode(struct drm_display_mode *mode, 557 unsigned int rotation) 558 { 559 if (rotation == 0 || rotation == 180) { 560 return 0; 561 } else if (rotation == 90 || rotation == 270) { 562 swap(mode->hdisplay, mode->vdisplay); 563 swap(mode->hsync_start, mode->vsync_start); 564 swap(mode->hsync_end, mode->vsync_end); 565 swap(mode->htotal, mode->vtotal); 566 swap(mode->width_mm, mode->height_mm); 567 return 0; 568 } else { 569 return -EINVAL; 570 } 571 } 572 573 static const struct drm_mode_config_funcs mipi_dbi_mode_config_funcs = { 574 .fb_create = drm_gem_fb_create_with_dirty, 575 .atomic_check = drm_atomic_helper_check, 576 .atomic_commit = drm_atomic_helper_commit, 577 }; 578 579 static const uint32_t mipi_dbi_formats[] = { 580 DRM_FORMAT_RGB565, 581 DRM_FORMAT_XRGB8888, 582 }; 583 584 /** 585 * mipi_dbi_dev_init_with_formats - MIPI DBI device initialization with custom formats 586 * @dbidev: MIPI DBI device structure to initialize 587 * @funcs: Display pipe functions 588 * @formats: Array of supported formats (DRM_FORMAT\_\*). 589 * @format_count: Number of elements in @formats 590 * @mode: Display mode 591 * @rotation: Initial rotation in degrees Counter Clock Wise 592 * @tx_buf_size: Allocate a transmit buffer of this size. 593 * 594 * This function sets up a &drm_simple_display_pipe with a &drm_connector that 595 * has one fixed &drm_display_mode which is rotated according to @rotation. 596 * This mode is used to set the mode config min/max width/height properties. 597 * 598 * Use mipi_dbi_dev_init() if you want native RGB565 and emulated XRGB8888 format. 599 * 600 * Note: 601 * Some of the helper functions expects RGB565 to be the default format and the 602 * transmit buffer sized to fit that. 603 * 604 * Returns: 605 * Zero on success, negative error code on failure. 606 */ 607 int mipi_dbi_dev_init_with_formats(struct mipi_dbi_dev *dbidev, 608 const struct drm_simple_display_pipe_funcs *funcs, 609 const uint32_t *formats, unsigned int format_count, 610 const struct drm_display_mode *mode, 611 unsigned int rotation, size_t tx_buf_size) 612 { 613 static const uint64_t modifiers[] = { 614 DRM_FORMAT_MOD_LINEAR, 615 DRM_FORMAT_MOD_INVALID 616 }; 617 struct drm_device *drm = &dbidev->drm; 618 int ret; 619 620 if (!dbidev->dbi.command) 621 return -EINVAL; 622 623 ret = drmm_mode_config_init(drm); 624 if (ret) 625 return ret; 626 627 dbidev->tx_buf = devm_kmalloc(drm->dev, tx_buf_size, GFP_KERNEL); 628 if (!dbidev->tx_buf) 629 return -ENOMEM; 630 631 drm_mode_copy(&dbidev->mode, mode); 632 ret = mipi_dbi_rotate_mode(&dbidev->mode, rotation); 633 if (ret) { 634 DRM_ERROR("Illegal rotation value %u\n", rotation); 635 return -EINVAL; 636 } 637 638 drm_connector_helper_add(&dbidev->connector, &mipi_dbi_connector_hfuncs); 639 ret = drm_connector_init(drm, &dbidev->connector, &mipi_dbi_connector_funcs, 640 DRM_MODE_CONNECTOR_SPI); 641 if (ret) 642 return ret; 643 644 ret = drm_simple_display_pipe_init(drm, &dbidev->pipe, funcs, formats, format_count, 645 modifiers, &dbidev->connector); 646 if (ret) 647 return ret; 648 649 drm_plane_enable_fb_damage_clips(&dbidev->pipe.plane); 650 651 drm->mode_config.funcs = &mipi_dbi_mode_config_funcs; 652 drm->mode_config.min_width = dbidev->mode.hdisplay; 653 drm->mode_config.max_width = dbidev->mode.hdisplay; 654 drm->mode_config.min_height = dbidev->mode.vdisplay; 655 drm->mode_config.max_height = dbidev->mode.vdisplay; 656 dbidev->rotation = rotation; 657 dbidev->pixel_format = formats[0]; 658 if (formats[0] == DRM_FORMAT_RGB888) 659 dbidev->dbi.write_memory_bpw = 8; 660 661 DRM_DEBUG_KMS("rotation = %u\n", rotation); 662 663 return 0; 664 } 665 EXPORT_SYMBOL(mipi_dbi_dev_init_with_formats); 666 667 /** 668 * mipi_dbi_dev_init - MIPI DBI device initialization 669 * @dbidev: MIPI DBI device structure to initialize 670 * @funcs: Display pipe functions 671 * @mode: Display mode 672 * @rotation: Initial rotation in degrees Counter Clock Wise 673 * 674 * This function sets up a &drm_simple_display_pipe with a &drm_connector that 675 * has one fixed &drm_display_mode which is rotated according to @rotation. 676 * This mode is used to set the mode config min/max width/height properties. 677 * Additionally &mipi_dbi.tx_buf is allocated. 678 * 679 * Supported formats: Native RGB565 and emulated XRGB8888. 680 * 681 * Returns: 682 * Zero on success, negative error code on failure. 683 */ 684 int mipi_dbi_dev_init(struct mipi_dbi_dev *dbidev, 685 const struct drm_simple_display_pipe_funcs *funcs, 686 const struct drm_display_mode *mode, unsigned int rotation) 687 { 688 size_t bufsize = mode->vdisplay * mode->hdisplay * sizeof(u16); 689 690 dbidev->drm.mode_config.preferred_depth = 16; 691 692 return mipi_dbi_dev_init_with_formats(dbidev, funcs, mipi_dbi_formats, 693 ARRAY_SIZE(mipi_dbi_formats), mode, 694 rotation, bufsize); 695 } 696 EXPORT_SYMBOL(mipi_dbi_dev_init); 697 698 /** 699 * mipi_dbi_hw_reset - Hardware reset of controller 700 * @dbi: MIPI DBI structure 701 * 702 * Reset controller if the &mipi_dbi->reset gpio is set. 703 */ 704 void mipi_dbi_hw_reset(struct mipi_dbi *dbi) 705 { 706 if (!dbi->reset) 707 return; 708 709 gpiod_set_value_cansleep(dbi->reset, 0); 710 usleep_range(20, 1000); 711 gpiod_set_value_cansleep(dbi->reset, 1); 712 msleep(120); 713 } 714 EXPORT_SYMBOL(mipi_dbi_hw_reset); 715 716 /** 717 * mipi_dbi_display_is_on - Check if display is on 718 * @dbi: MIPI DBI structure 719 * 720 * This function checks the Power Mode register (if readable) to see if 721 * display output is turned on. This can be used to see if the bootloader 722 * has already turned on the display avoiding flicker when the pipeline is 723 * enabled. 724 * 725 * Returns: 726 * true if the display can be verified to be on, false otherwise. 727 */ 728 bool mipi_dbi_display_is_on(struct mipi_dbi *dbi) 729 { 730 u8 val; 731 732 if (mipi_dbi_command_read(dbi, MIPI_DCS_GET_POWER_MODE, &val)) 733 return false; 734 735 val &= ~DCS_POWER_MODE_RESERVED_MASK; 736 737 /* The poweron/reset value is 08h DCS_POWER_MODE_DISPLAY_NORMAL_MODE */ 738 if (val != (DCS_POWER_MODE_DISPLAY | 739 DCS_POWER_MODE_DISPLAY_NORMAL_MODE | DCS_POWER_MODE_SLEEP_MODE)) 740 return false; 741 742 DRM_DEBUG_DRIVER("Display is ON\n"); 743 744 return true; 745 } 746 EXPORT_SYMBOL(mipi_dbi_display_is_on); 747 748 static int mipi_dbi_poweron_reset_conditional(struct mipi_dbi_dev *dbidev, bool cond) 749 { 750 struct device *dev = dbidev->drm.dev; 751 struct mipi_dbi *dbi = &dbidev->dbi; 752 int ret; 753 754 if (dbidev->regulator) { 755 ret = regulator_enable(dbidev->regulator); 756 if (ret) { 757 DRM_DEV_ERROR(dev, "Failed to enable regulator (%d)\n", ret); 758 return ret; 759 } 760 } 761 762 if (dbidev->io_regulator) { 763 ret = regulator_enable(dbidev->io_regulator); 764 if (ret) { 765 DRM_DEV_ERROR(dev, "Failed to enable I/O regulator (%d)\n", ret); 766 if (dbidev->regulator) 767 regulator_disable(dbidev->regulator); 768 return ret; 769 } 770 } 771 772 if (cond && mipi_dbi_display_is_on(dbi)) 773 return 1; 774 775 mipi_dbi_hw_reset(dbi); 776 ret = mipi_dbi_command(dbi, MIPI_DCS_SOFT_RESET); 777 if (ret) { 778 DRM_DEV_ERROR(dev, "Failed to send reset command (%d)\n", ret); 779 if (dbidev->regulator) 780 regulator_disable(dbidev->regulator); 781 if (dbidev->io_regulator) 782 regulator_disable(dbidev->io_regulator); 783 return ret; 784 } 785 786 /* 787 * If we did a hw reset, we know the controller is in Sleep mode and 788 * per MIPI DSC spec should wait 5ms after soft reset. If we didn't, 789 * we assume worst case and wait 120ms. 790 */ 791 if (dbi->reset) 792 usleep_range(5000, 20000); 793 else 794 msleep(120); 795 796 return 0; 797 } 798 799 /** 800 * mipi_dbi_poweron_reset - MIPI DBI poweron and reset 801 * @dbidev: MIPI DBI device structure 802 * 803 * This function enables the regulator if used and does a hardware and software 804 * reset. 805 * 806 * Returns: 807 * Zero on success, or a negative error code. 808 */ 809 int mipi_dbi_poweron_reset(struct mipi_dbi_dev *dbidev) 810 { 811 return mipi_dbi_poweron_reset_conditional(dbidev, false); 812 } 813 EXPORT_SYMBOL(mipi_dbi_poweron_reset); 814 815 /** 816 * mipi_dbi_poweron_conditional_reset - MIPI DBI poweron and conditional reset 817 * @dbidev: MIPI DBI device structure 818 * 819 * This function enables the regulator if used and if the display is off, it 820 * does a hardware and software reset. If mipi_dbi_display_is_on() determines 821 * that the display is on, no reset is performed. 822 * 823 * Returns: 824 * Zero if the controller was reset, 1 if the display was already on, or a 825 * negative error code. 826 */ 827 int mipi_dbi_poweron_conditional_reset(struct mipi_dbi_dev *dbidev) 828 { 829 return mipi_dbi_poweron_reset_conditional(dbidev, true); 830 } 831 EXPORT_SYMBOL(mipi_dbi_poweron_conditional_reset); 832 833 #if IS_ENABLED(CONFIG_SPI) 834 835 /** 836 * mipi_dbi_spi_cmd_max_speed - get the maximum SPI bus speed 837 * @spi: SPI device 838 * @len: The transfer buffer length. 839 * 840 * Many controllers have a max speed of 10MHz, but can be pushed way beyond 841 * that. Increase reliability by running pixel data at max speed and the rest 842 * at 10MHz, preventing transfer glitches from messing up the init settings. 843 */ 844 u32 mipi_dbi_spi_cmd_max_speed(struct spi_device *spi, size_t len) 845 { 846 if (len > 64) 847 return 0; /* use default */ 848 849 return min_t(u32, 10000000, spi->max_speed_hz); 850 } 851 EXPORT_SYMBOL(mipi_dbi_spi_cmd_max_speed); 852 853 /* 854 * MIPI DBI Type C Option 1 855 * 856 * If the SPI controller doesn't have 9 bits per word support, 857 * use blocks of 9 bytes to send 8x 9-bit words using a 8-bit SPI transfer. 858 * Pad partial blocks with MIPI_DCS_NOP (zero). 859 * This is how the D/C bit (x) is added: 860 * x7654321 861 * 0x765432 862 * 10x76543 863 * 210x7654 864 * 3210x765 865 * 43210x76 866 * 543210x7 867 * 6543210x 868 * 76543210 869 */ 870 871 static int mipi_dbi_spi1e_transfer(struct mipi_dbi *dbi, int dc, 872 const void *buf, size_t len, 873 unsigned int bpw) 874 { 875 bool swap_bytes = (bpw == 16); 876 size_t chunk, max_chunk = dbi->tx_buf9_len; 877 struct spi_device *spi = dbi->spi; 878 struct spi_transfer tr = { 879 .tx_buf = dbi->tx_buf9, 880 .bits_per_word = 8, 881 }; 882 struct spi_message m; 883 const u8 *src = buf; 884 int i, ret; 885 u8 *dst; 886 887 if (drm_debug_enabled(DRM_UT_DRIVER)) 888 pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n", 889 __func__, dc, max_chunk); 890 891 tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len); 892 spi_message_init_with_transfers(&m, &tr, 1); 893 894 if (!dc) { 895 if (WARN_ON_ONCE(len != 1)) 896 return -EINVAL; 897 898 /* Command: pad no-op's (zeroes) at beginning of block */ 899 dst = dbi->tx_buf9; 900 memset(dst, 0, 9); 901 dst[8] = *src; 902 tr.len = 9; 903 904 return spi_sync(spi, &m); 905 } 906 907 /* max with room for adding one bit per byte */ 908 max_chunk = max_chunk / 9 * 8; 909 /* but no bigger than len */ 910 max_chunk = min(max_chunk, len); 911 /* 8 byte blocks */ 912 max_chunk = max_t(size_t, 8, max_chunk & ~0x7); 913 914 while (len) { 915 size_t added = 0; 916 917 chunk = min(len, max_chunk); 918 len -= chunk; 919 dst = dbi->tx_buf9; 920 921 if (chunk < 8) { 922 u8 val, carry = 0; 923 924 /* Data: pad no-op's (zeroes) at end of block */ 925 memset(dst, 0, 9); 926 927 if (swap_bytes) { 928 for (i = 1; i < (chunk + 1); i++) { 929 val = src[1]; 930 *dst++ = carry | BIT(8 - i) | (val >> i); 931 carry = val << (8 - i); 932 i++; 933 val = src[0]; 934 *dst++ = carry | BIT(8 - i) | (val >> i); 935 carry = val << (8 - i); 936 src += 2; 937 } 938 *dst++ = carry; 939 } else { 940 for (i = 1; i < (chunk + 1); i++) { 941 val = *src++; 942 *dst++ = carry | BIT(8 - i) | (val >> i); 943 carry = val << (8 - i); 944 } 945 *dst++ = carry; 946 } 947 948 chunk = 8; 949 added = 1; 950 } else { 951 for (i = 0; i < chunk; i += 8) { 952 if (swap_bytes) { 953 *dst++ = BIT(7) | (src[1] >> 1); 954 *dst++ = (src[1] << 7) | BIT(6) | (src[0] >> 2); 955 *dst++ = (src[0] << 6) | BIT(5) | (src[3] >> 3); 956 *dst++ = (src[3] << 5) | BIT(4) | (src[2] >> 4); 957 *dst++ = (src[2] << 4) | BIT(3) | (src[5] >> 5); 958 *dst++ = (src[5] << 3) | BIT(2) | (src[4] >> 6); 959 *dst++ = (src[4] << 2) | BIT(1) | (src[7] >> 7); 960 *dst++ = (src[7] << 1) | BIT(0); 961 *dst++ = src[6]; 962 } else { 963 *dst++ = BIT(7) | (src[0] >> 1); 964 *dst++ = (src[0] << 7) | BIT(6) | (src[1] >> 2); 965 *dst++ = (src[1] << 6) | BIT(5) | (src[2] >> 3); 966 *dst++ = (src[2] << 5) | BIT(4) | (src[3] >> 4); 967 *dst++ = (src[3] << 4) | BIT(3) | (src[4] >> 5); 968 *dst++ = (src[4] << 3) | BIT(2) | (src[5] >> 6); 969 *dst++ = (src[5] << 2) | BIT(1) | (src[6] >> 7); 970 *dst++ = (src[6] << 1) | BIT(0); 971 *dst++ = src[7]; 972 } 973 974 src += 8; 975 added++; 976 } 977 } 978 979 tr.len = chunk + added; 980 981 ret = spi_sync(spi, &m); 982 if (ret) 983 return ret; 984 } 985 986 return 0; 987 } 988 989 static int mipi_dbi_spi1_transfer(struct mipi_dbi *dbi, int dc, 990 const void *buf, size_t len, 991 unsigned int bpw) 992 { 993 struct spi_device *spi = dbi->spi; 994 struct spi_transfer tr = { 995 .bits_per_word = 9, 996 }; 997 const u16 *src16 = buf; 998 const u8 *src8 = buf; 999 struct spi_message m; 1000 size_t max_chunk; 1001 u16 *dst16; 1002 int ret; 1003 1004 if (!spi_is_bpw_supported(spi, 9)) 1005 return mipi_dbi_spi1e_transfer(dbi, dc, buf, len, bpw); 1006 1007 tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len); 1008 max_chunk = dbi->tx_buf9_len; 1009 dst16 = dbi->tx_buf9; 1010 1011 if (drm_debug_enabled(DRM_UT_DRIVER)) 1012 pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n", 1013 __func__, dc, max_chunk); 1014 1015 max_chunk = min(max_chunk / 2, len); 1016 1017 spi_message_init_with_transfers(&m, &tr, 1); 1018 tr.tx_buf = dst16; 1019 1020 while (len) { 1021 size_t chunk = min(len, max_chunk); 1022 unsigned int i; 1023 1024 if (bpw == 16) { 1025 for (i = 0; i < (chunk * 2); i += 2) { 1026 dst16[i] = *src16 >> 8; 1027 dst16[i + 1] = *src16++ & 0xFF; 1028 if (dc) { 1029 dst16[i] |= 0x0100; 1030 dst16[i + 1] |= 0x0100; 1031 } 1032 } 1033 } else { 1034 for (i = 0; i < chunk; i++) { 1035 dst16[i] = *src8++; 1036 if (dc) 1037 dst16[i] |= 0x0100; 1038 } 1039 } 1040 1041 tr.len = chunk * 2; 1042 len -= chunk; 1043 1044 ret = spi_sync(spi, &m); 1045 if (ret) 1046 return ret; 1047 } 1048 1049 return 0; 1050 } 1051 1052 static int mipi_dbi_typec1_command_read(struct mipi_dbi *dbi, u8 *cmd, 1053 u8 *data, size_t len) 1054 { 1055 struct spi_device *spi = dbi->spi; 1056 u32 speed_hz = min_t(u32, MIPI_DBI_MAX_SPI_READ_SPEED, 1057 spi->max_speed_hz / 2); 1058 struct spi_transfer tr[2] = { 1059 { 1060 .speed_hz = speed_hz, 1061 .bits_per_word = 9, 1062 .tx_buf = dbi->tx_buf9, 1063 .len = 2, 1064 }, { 1065 .speed_hz = speed_hz, 1066 .bits_per_word = 8, 1067 .len = len, 1068 .rx_buf = data, 1069 }, 1070 }; 1071 struct spi_message m; 1072 u16 *dst16; 1073 int ret; 1074 1075 if (!len) 1076 return -EINVAL; 1077 1078 if (!spi_is_bpw_supported(spi, 9)) { 1079 /* 1080 * FIXME: implement something like mipi_dbi_spi1e_transfer() but 1081 * for reads using emulation. 1082 */ 1083 dev_err(&spi->dev, 1084 "reading on host not supporting 9 bpw not yet implemented\n"); 1085 return -EOPNOTSUPP; 1086 } 1087 1088 /* 1089 * Turn the 8bit command into a 16bit version of the command in the 1090 * buffer. Only 9 bits of this will be used when executing the actual 1091 * transfer. 1092 */ 1093 dst16 = dbi->tx_buf9; 1094 dst16[0] = *cmd; 1095 1096 spi_message_init_with_transfers(&m, tr, ARRAY_SIZE(tr)); 1097 ret = spi_sync(spi, &m); 1098 1099 if (!ret) 1100 MIPI_DBI_DEBUG_COMMAND(*cmd, data, len); 1101 1102 return ret; 1103 } 1104 1105 static int mipi_dbi_typec1_command(struct mipi_dbi *dbi, u8 *cmd, 1106 u8 *parameters, size_t num) 1107 { 1108 unsigned int bpw = 8; 1109 int ret; 1110 1111 if (mipi_dbi_command_is_read(dbi, *cmd)) 1112 return mipi_dbi_typec1_command_read(dbi, cmd, parameters, num); 1113 1114 MIPI_DBI_DEBUG_COMMAND(*cmd, parameters, num); 1115 1116 ret = mipi_dbi_spi1_transfer(dbi, 0, cmd, 1, 8); 1117 if (ret || !num) 1118 return ret; 1119 1120 if (*cmd == MIPI_DCS_WRITE_MEMORY_START) 1121 bpw = dbi->write_memory_bpw; 1122 1123 return mipi_dbi_spi1_transfer(dbi, 1, parameters, num, bpw); 1124 } 1125 1126 /* MIPI DBI Type C Option 3 */ 1127 1128 static int mipi_dbi_typec3_command_read(struct mipi_dbi *dbi, u8 *cmd, 1129 u8 *data, size_t len) 1130 { 1131 struct spi_device *spi = dbi->spi; 1132 u32 speed_hz = min_t(u32, MIPI_DBI_MAX_SPI_READ_SPEED, 1133 spi->max_speed_hz / 2); 1134 struct spi_transfer tr[2] = { 1135 { 1136 .speed_hz = speed_hz, 1137 .tx_buf = cmd, 1138 .len = 1, 1139 }, { 1140 .speed_hz = speed_hz, 1141 .len = len, 1142 }, 1143 }; 1144 struct spi_message m; 1145 u8 *buf; 1146 int ret; 1147 1148 if (!len) 1149 return -EINVAL; 1150 1151 /* 1152 * Support non-standard 24-bit and 32-bit Nokia read commands which 1153 * start with a dummy clock, so we need to read an extra byte. 1154 */ 1155 if (*cmd == MIPI_DCS_GET_DISPLAY_ID || 1156 *cmd == MIPI_DCS_GET_DISPLAY_STATUS) { 1157 if (!(len == 3 || len == 4)) 1158 return -EINVAL; 1159 1160 tr[1].len = len + 1; 1161 } 1162 1163 buf = kmalloc(tr[1].len, GFP_KERNEL); 1164 if (!buf) 1165 return -ENOMEM; 1166 1167 tr[1].rx_buf = buf; 1168 1169 spi_bus_lock(spi->controller); 1170 gpiod_set_value_cansleep(dbi->dc, 0); 1171 1172 spi_message_init_with_transfers(&m, tr, ARRAY_SIZE(tr)); 1173 ret = spi_sync_locked(spi, &m); 1174 spi_bus_unlock(spi->controller); 1175 if (ret) 1176 goto err_free; 1177 1178 if (tr[1].len == len) { 1179 memcpy(data, buf, len); 1180 } else { 1181 unsigned int i; 1182 1183 for (i = 0; i < len; i++) 1184 data[i] = (buf[i] << 1) | (buf[i + 1] >> 7); 1185 } 1186 1187 MIPI_DBI_DEBUG_COMMAND(*cmd, data, len); 1188 1189 err_free: 1190 kfree(buf); 1191 1192 return ret; 1193 } 1194 1195 static int mipi_dbi_typec3_command(struct mipi_dbi *dbi, u8 *cmd, 1196 u8 *par, size_t num) 1197 { 1198 struct spi_device *spi = dbi->spi; 1199 unsigned int bpw = 8; 1200 u32 speed_hz; 1201 int ret; 1202 1203 if (mipi_dbi_command_is_read(dbi, *cmd)) 1204 return mipi_dbi_typec3_command_read(dbi, cmd, par, num); 1205 1206 MIPI_DBI_DEBUG_COMMAND(*cmd, par, num); 1207 1208 spi_bus_lock(spi->controller); 1209 gpiod_set_value_cansleep(dbi->dc, 0); 1210 speed_hz = mipi_dbi_spi_cmd_max_speed(spi, 1); 1211 ret = mipi_dbi_spi_transfer(spi, speed_hz, 8, cmd, 1); 1212 spi_bus_unlock(spi->controller); 1213 if (ret || !num) 1214 return ret; 1215 1216 if (*cmd == MIPI_DCS_WRITE_MEMORY_START) 1217 bpw = dbi->write_memory_bpw; 1218 1219 spi_bus_lock(spi->controller); 1220 gpiod_set_value_cansleep(dbi->dc, 1); 1221 speed_hz = mipi_dbi_spi_cmd_max_speed(spi, num); 1222 ret = mipi_dbi_spi_transfer(spi, speed_hz, bpw, par, num); 1223 spi_bus_unlock(spi->controller); 1224 1225 return ret; 1226 } 1227 1228 /** 1229 * mipi_dbi_spi_init - Initialize MIPI DBI SPI interface 1230 * @spi: SPI device 1231 * @dbi: MIPI DBI structure to initialize 1232 * @dc: D/C gpio (optional) 1233 * 1234 * This function sets &mipi_dbi->command, enables &mipi_dbi->read_commands for the 1235 * usual read commands. It should be followed by a call to mipi_dbi_dev_init() or 1236 * a driver-specific init. 1237 * 1238 * If @dc is set, a Type C Option 3 interface is assumed, if not 1239 * Type C Option 1. 1240 * 1241 * If the command is %MIPI_DCS_WRITE_MEMORY_START and the pixel format is RGB565, endianness has 1242 * to be taken into account. The MIPI DBI serial interface is big endian and framebuffers are 1243 * assumed stored in memory as little endian (%DRM_FORMAT_BIG_ENDIAN is not supported). 1244 * 1245 * This is how endianness is handled: 1246 * 1247 * Option 1 (D/C as a bit): The buffer is sent on the wire byte by byte so the 16-bit buffer is 1248 * byteswapped before transfer. 1249 * 1250 * Option 3 (D/C as a gpio): If the SPI controller supports 16 bits per word the buffer can be 1251 * sent as-is. If not the caller is responsible for swapping the bytes 1252 * before calling mipi_dbi_command_buf() and the buffer is sent 8 bpw. 1253 * 1254 * This handling is optimised for %DRM_FORMAT_RGB565 framebuffers. 1255 * 1256 * If the interface is Option 1 and the SPI controller doesn't support 9 bits per word, 1257 * the buffer is sent as 9x 8-bit words, padded with MIPI DCS no-op commands if necessary. 1258 * 1259 * Returns: 1260 * Zero on success, negative error code on failure. 1261 */ 1262 int mipi_dbi_spi_init(struct spi_device *spi, struct mipi_dbi *dbi, 1263 struct gpio_desc *dc) 1264 { 1265 struct device *dev = &spi->dev; 1266 int ret; 1267 1268 /* 1269 * Even though it's not the SPI device that does DMA (the master does), 1270 * the dma mask is necessary for the dma_alloc_wc() in the GEM code 1271 * (e.g., drm_gem_dma_create()). The dma_addr returned will be a physical 1272 * address which might be different from the bus address, but this is 1273 * not a problem since the address will not be used. 1274 * The virtual address is used in the transfer and the SPI core 1275 * re-maps it on the SPI master device using the DMA streaming API 1276 * (spi_map_buf()). 1277 */ 1278 if (!dev->coherent_dma_mask) { 1279 ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32)); 1280 if (ret) { 1281 dev_warn(dev, "Failed to set dma mask %d\n", ret); 1282 return ret; 1283 } 1284 } 1285 1286 dbi->spi = spi; 1287 dbi->read_commands = mipi_dbi_dcs_read_commands; 1288 dbi->write_memory_bpw = 16; 1289 1290 if (dc) { 1291 dbi->command = mipi_dbi_typec3_command; 1292 dbi->dc = dc; 1293 if (!spi_is_bpw_supported(spi, 16)) { 1294 dbi->write_memory_bpw = 8; 1295 dbi->swap_bytes = true; 1296 } 1297 } else { 1298 dbi->command = mipi_dbi_typec1_command; 1299 dbi->tx_buf9_len = SZ_16K; 1300 dbi->tx_buf9 = devm_kmalloc(dev, dbi->tx_buf9_len, GFP_KERNEL); 1301 if (!dbi->tx_buf9) 1302 return -ENOMEM; 1303 } 1304 1305 mutex_init(&dbi->cmdlock); 1306 1307 DRM_DEBUG_DRIVER("SPI speed: %uMHz\n", spi->max_speed_hz / 1000000); 1308 1309 return 0; 1310 } 1311 EXPORT_SYMBOL(mipi_dbi_spi_init); 1312 1313 /** 1314 * mipi_dbi_spi_transfer - SPI transfer helper 1315 * @spi: SPI device 1316 * @speed_hz: Override speed (optional) 1317 * @bpw: Bits per word 1318 * @buf: Buffer to transfer 1319 * @len: Buffer length 1320 * 1321 * This SPI transfer helper breaks up the transfer of @buf into chunks which 1322 * the SPI controller driver can handle. The SPI bus must be locked when 1323 * calling this. 1324 * 1325 * Returns: 1326 * Zero on success, negative error code on failure. 1327 */ 1328 int mipi_dbi_spi_transfer(struct spi_device *spi, u32 speed_hz, 1329 u8 bpw, const void *buf, size_t len) 1330 { 1331 size_t max_chunk = spi_max_transfer_size(spi); 1332 struct spi_transfer tr = { 1333 .bits_per_word = bpw, 1334 .speed_hz = speed_hz, 1335 }; 1336 struct spi_message m; 1337 size_t chunk; 1338 int ret; 1339 1340 /* In __spi_validate, there's a validation that no partial transfers 1341 * are accepted (xfer->len % w_size must be zero). 1342 * Here we align max_chunk to multiple of 2 (16bits), 1343 * to prevent transfers from being rejected. 1344 */ 1345 max_chunk = ALIGN_DOWN(max_chunk, 2); 1346 1347 spi_message_init_with_transfers(&m, &tr, 1); 1348 1349 while (len) { 1350 chunk = min(len, max_chunk); 1351 1352 tr.tx_buf = buf; 1353 tr.len = chunk; 1354 buf += chunk; 1355 len -= chunk; 1356 1357 ret = spi_sync_locked(spi, &m); 1358 if (ret) 1359 return ret; 1360 } 1361 1362 return 0; 1363 } 1364 EXPORT_SYMBOL(mipi_dbi_spi_transfer); 1365 1366 #endif /* CONFIG_SPI */ 1367 1368 #ifdef CONFIG_DEBUG_FS 1369 1370 static ssize_t mipi_dbi_debugfs_command_write(struct file *file, 1371 const char __user *ubuf, 1372 size_t count, loff_t *ppos) 1373 { 1374 struct seq_file *m = file->private_data; 1375 struct mipi_dbi_dev *dbidev = m->private; 1376 u8 val, cmd = 0, parameters[64]; 1377 char *buf, *pos, *token; 1378 int i, ret, idx; 1379 1380 if (!drm_dev_enter(&dbidev->drm, &idx)) 1381 return -ENODEV; 1382 1383 buf = memdup_user_nul(ubuf, count); 1384 if (IS_ERR(buf)) { 1385 ret = PTR_ERR(buf); 1386 goto err_exit; 1387 } 1388 1389 /* strip trailing whitespace */ 1390 for (i = count - 1; i > 0; i--) 1391 if (isspace(buf[i])) 1392 buf[i] = '\0'; 1393 else 1394 break; 1395 i = 0; 1396 pos = buf; 1397 while (pos) { 1398 token = strsep(&pos, " "); 1399 if (!token) { 1400 ret = -EINVAL; 1401 goto err_free; 1402 } 1403 1404 ret = kstrtou8(token, 16, &val); 1405 if (ret < 0) 1406 goto err_free; 1407 1408 if (token == buf) 1409 cmd = val; 1410 else 1411 parameters[i++] = val; 1412 1413 if (i == 64) { 1414 ret = -E2BIG; 1415 goto err_free; 1416 } 1417 } 1418 1419 ret = mipi_dbi_command_buf(&dbidev->dbi, cmd, parameters, i); 1420 1421 err_free: 1422 kfree(buf); 1423 err_exit: 1424 drm_dev_exit(idx); 1425 1426 return ret < 0 ? ret : count; 1427 } 1428 1429 static int mipi_dbi_debugfs_command_show(struct seq_file *m, void *unused) 1430 { 1431 struct mipi_dbi_dev *dbidev = m->private; 1432 struct mipi_dbi *dbi = &dbidev->dbi; 1433 u8 cmd, val[4]; 1434 int ret, idx; 1435 size_t len; 1436 1437 if (!drm_dev_enter(&dbidev->drm, &idx)) 1438 return -ENODEV; 1439 1440 for (cmd = 0; cmd < 255; cmd++) { 1441 if (!mipi_dbi_command_is_read(dbi, cmd)) 1442 continue; 1443 1444 switch (cmd) { 1445 case MIPI_DCS_READ_MEMORY_START: 1446 case MIPI_DCS_READ_MEMORY_CONTINUE: 1447 len = 2; 1448 break; 1449 case MIPI_DCS_GET_DISPLAY_ID: 1450 len = 3; 1451 break; 1452 case MIPI_DCS_GET_DISPLAY_STATUS: 1453 len = 4; 1454 break; 1455 default: 1456 len = 1; 1457 break; 1458 } 1459 1460 seq_printf(m, "%02x: ", cmd); 1461 ret = mipi_dbi_command_buf(dbi, cmd, val, len); 1462 if (ret) { 1463 seq_puts(m, "XX\n"); 1464 continue; 1465 } 1466 seq_printf(m, "%*phN\n", (int)len, val); 1467 } 1468 1469 drm_dev_exit(idx); 1470 1471 return 0; 1472 } 1473 1474 static int mipi_dbi_debugfs_command_open(struct inode *inode, 1475 struct file *file) 1476 { 1477 return single_open(file, mipi_dbi_debugfs_command_show, 1478 inode->i_private); 1479 } 1480 1481 static const struct file_operations mipi_dbi_debugfs_command_fops = { 1482 .owner = THIS_MODULE, 1483 .open = mipi_dbi_debugfs_command_open, 1484 .read = seq_read, 1485 .llseek = seq_lseek, 1486 .release = single_release, 1487 .write = mipi_dbi_debugfs_command_write, 1488 }; 1489 1490 /** 1491 * mipi_dbi_debugfs_init - Create debugfs entries 1492 * @minor: DRM minor 1493 * 1494 * This function creates a 'command' debugfs file for sending commands to the 1495 * controller or getting the read command values. 1496 * Drivers can use this as their &drm_driver->debugfs_init callback. 1497 * 1498 */ 1499 void mipi_dbi_debugfs_init(struct drm_minor *minor) 1500 { 1501 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(minor->dev); 1502 umode_t mode = S_IFREG | S_IWUSR; 1503 1504 if (dbidev->dbi.read_commands) 1505 mode |= S_IRUGO; 1506 debugfs_create_file("command", mode, minor->debugfs_root, dbidev, 1507 &mipi_dbi_debugfs_command_fops); 1508 } 1509 EXPORT_SYMBOL(mipi_dbi_debugfs_init); 1510 1511 #endif 1512 1513 MODULE_DESCRIPTION("MIPI Display Bus Interface (DBI) LCD controller support"); 1514 MODULE_LICENSE("GPL"); 1515