1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 31 #include <linux/hdmi.h> 32 #include <linux/i2c.h> 33 #include <linux/kernel.h> 34 #include <linux/module.h> 35 #include <linux/slab.h> 36 #include <linux/vga_switcheroo.h> 37 38 #include <drm/drm_displayid.h> 39 #include <drm/drm_drv.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_encoder.h> 42 #include <drm/drm_print.h> 43 #include <drm/drm_scdc_helper.h> 44 45 #include "drm_crtc_internal.h" 46 47 #define version_greater(edid, maj, min) \ 48 (((edid)->version > (maj)) || \ 49 ((edid)->version == (maj) && (edid)->revision > (min))) 50 51 #define EDID_EST_TIMINGS 16 52 #define EDID_STD_TIMINGS 8 53 #define EDID_DETAILED_TIMINGS 4 54 55 /* 56 * EDID blocks out in the wild have a variety of bugs, try to collect 57 * them here (note that userspace may work around broken monitors first, 58 * but fixes should make their way here so that the kernel "just works" 59 * on as many displays as possible). 60 */ 61 62 /* First detailed mode wrong, use largest 60Hz mode */ 63 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 64 /* Reported 135MHz pixel clock is too high, needs adjustment */ 65 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 66 /* Prefer the largest mode at 75 Hz */ 67 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 68 /* Detail timing is in cm not mm */ 69 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 70 /* Detailed timing descriptors have bogus size values, so just take the 71 * maximum size and use that. 72 */ 73 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 74 /* use +hsync +vsync for detailed mode */ 75 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 76 /* Force reduced-blanking timings for detailed modes */ 77 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 78 /* Force 8bpc */ 79 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 80 /* Force 12bpc */ 81 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 82 /* Force 6bpc */ 83 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 84 /* Force 10bpc */ 85 #define EDID_QUIRK_FORCE_10BPC (1 << 11) 86 /* Non desktop display (i.e. HMD) */ 87 #define EDID_QUIRK_NON_DESKTOP (1 << 12) 88 89 struct detailed_mode_closure { 90 struct drm_connector *connector; 91 struct edid *edid; 92 bool preferred; 93 u32 quirks; 94 int modes; 95 }; 96 97 #define LEVEL_DMT 0 98 #define LEVEL_GTF 1 99 #define LEVEL_GTF2 2 100 #define LEVEL_CVT 3 101 102 static const struct edid_quirk { 103 char vendor[4]; 104 int product_id; 105 u32 quirks; 106 } edid_quirk_list[] = { 107 /* Acer AL1706 */ 108 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 109 /* Acer F51 */ 110 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 111 112 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 113 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 114 115 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */ 116 { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC }, 117 118 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 119 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC }, 120 121 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ 122 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC }, 123 124 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ 125 { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC }, 126 127 /* Belinea 10 15 55 */ 128 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 129 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 130 131 /* Envision Peripherals, Inc. EN-7100e */ 132 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 133 /* Envision EN2028 */ 134 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 135 136 /* Funai Electronics PM36B */ 137 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 138 EDID_QUIRK_DETAILED_IN_CM }, 139 140 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 141 { "LGD", 764, EDID_QUIRK_FORCE_10BPC }, 142 143 /* LG Philips LCD LP154W01-A5 */ 144 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 145 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 146 147 /* Samsung SyncMaster 205BW. Note: irony */ 148 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 149 /* Samsung SyncMaster 22[5-6]BW */ 150 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 151 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 152 153 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 154 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 155 156 /* ViewSonic VA2026w */ 157 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 158 159 /* Medion MD 30217 PG */ 160 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 161 162 /* Lenovo G50 */ 163 { "SDC", 18514, EDID_QUIRK_FORCE_6BPC }, 164 165 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 166 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 167 168 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 169 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, 170 171 /* Valve Index Headset */ 172 { "VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP }, 173 { "VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP }, 174 { "VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP }, 175 { "VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP }, 176 { "VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP }, 177 { "VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP }, 178 { "VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP }, 179 { "VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP }, 180 { "VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP }, 181 { "VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP }, 182 { "VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP }, 183 { "VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP }, 184 { "VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP }, 185 { "VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP }, 186 { "VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP }, 187 { "VLV", 0x91be, EDID_QUIRK_NON_DESKTOP }, 188 { "VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP }, 189 190 /* HTC Vive and Vive Pro VR Headsets */ 191 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP }, 192 { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP }, 193 194 /* Oculus Rift DK1, DK2, and CV1 VR Headsets */ 195 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP }, 196 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP }, 197 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP }, 198 199 /* Windows Mixed Reality Headsets */ 200 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP }, 201 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP }, 202 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP }, 203 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP }, 204 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP }, 205 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP }, 206 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP }, 207 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP }, 208 209 /* Sony PlayStation VR Headset */ 210 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP }, 211 212 /* Sensics VR Headsets */ 213 { "SEN", 0x1019, EDID_QUIRK_NON_DESKTOP }, 214 215 /* OSVR HDK and HDK2 VR Headsets */ 216 { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP }, 217 }; 218 219 /* 220 * Autogenerated from the DMT spec. 221 * This table is copied from xfree86/modes/xf86EdidModes.c. 222 */ 223 static const struct drm_display_mode drm_dmt_modes[] = { 224 /* 0x01 - 640x350@85Hz */ 225 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 226 736, 832, 0, 350, 382, 385, 445, 0, 227 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 228 /* 0x02 - 640x400@85Hz */ 229 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 230 736, 832, 0, 400, 401, 404, 445, 0, 231 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 232 /* 0x03 - 720x400@85Hz */ 233 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 234 828, 936, 0, 400, 401, 404, 446, 0, 235 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 236 /* 0x04 - 640x480@60Hz */ 237 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 238 752, 800, 0, 480, 490, 492, 525, 0, 239 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 240 /* 0x05 - 640x480@72Hz */ 241 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 242 704, 832, 0, 480, 489, 492, 520, 0, 243 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 244 /* 0x06 - 640x480@75Hz */ 245 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 246 720, 840, 0, 480, 481, 484, 500, 0, 247 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 248 /* 0x07 - 640x480@85Hz */ 249 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 250 752, 832, 0, 480, 481, 484, 509, 0, 251 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 252 /* 0x08 - 800x600@56Hz */ 253 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 254 896, 1024, 0, 600, 601, 603, 625, 0, 255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 256 /* 0x09 - 800x600@60Hz */ 257 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 258 968, 1056, 0, 600, 601, 605, 628, 0, 259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 260 /* 0x0a - 800x600@72Hz */ 261 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 262 976, 1040, 0, 600, 637, 643, 666, 0, 263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 264 /* 0x0b - 800x600@75Hz */ 265 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 266 896, 1056, 0, 600, 601, 604, 625, 0, 267 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 268 /* 0x0c - 800x600@85Hz */ 269 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 270 896, 1048, 0, 600, 601, 604, 631, 0, 271 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 272 /* 0x0d - 800x600@120Hz RB */ 273 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 274 880, 960, 0, 600, 603, 607, 636, 0, 275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 276 /* 0x0e - 848x480@60Hz */ 277 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 278 976, 1088, 0, 480, 486, 494, 517, 0, 279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 280 /* 0x0f - 1024x768@43Hz, interlace */ 281 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 282 1208, 1264, 0, 768, 768, 776, 817, 0, 283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 284 DRM_MODE_FLAG_INTERLACE) }, 285 /* 0x10 - 1024x768@60Hz */ 286 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 287 1184, 1344, 0, 768, 771, 777, 806, 0, 288 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 289 /* 0x11 - 1024x768@70Hz */ 290 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 291 1184, 1328, 0, 768, 771, 777, 806, 0, 292 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 293 /* 0x12 - 1024x768@75Hz */ 294 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 295 1136, 1312, 0, 768, 769, 772, 800, 0, 296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 297 /* 0x13 - 1024x768@85Hz */ 298 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 299 1168, 1376, 0, 768, 769, 772, 808, 0, 300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 301 /* 0x14 - 1024x768@120Hz RB */ 302 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 303 1104, 1184, 0, 768, 771, 775, 813, 0, 304 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 305 /* 0x15 - 1152x864@75Hz */ 306 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 307 1344, 1600, 0, 864, 865, 868, 900, 0, 308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 309 /* 0x55 - 1280x720@60Hz */ 310 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 311 1430, 1650, 0, 720, 725, 730, 750, 0, 312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 313 /* 0x16 - 1280x768@60Hz RB */ 314 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 315 1360, 1440, 0, 768, 771, 778, 790, 0, 316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 317 /* 0x17 - 1280x768@60Hz */ 318 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 319 1472, 1664, 0, 768, 771, 778, 798, 0, 320 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 321 /* 0x18 - 1280x768@75Hz */ 322 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 323 1488, 1696, 0, 768, 771, 778, 805, 0, 324 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 325 /* 0x19 - 1280x768@85Hz */ 326 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 327 1496, 1712, 0, 768, 771, 778, 809, 0, 328 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 329 /* 0x1a - 1280x768@120Hz RB */ 330 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 331 1360, 1440, 0, 768, 771, 778, 813, 0, 332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 333 /* 0x1b - 1280x800@60Hz RB */ 334 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 335 1360, 1440, 0, 800, 803, 809, 823, 0, 336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 337 /* 0x1c - 1280x800@60Hz */ 338 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 339 1480, 1680, 0, 800, 803, 809, 831, 0, 340 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 341 /* 0x1d - 1280x800@75Hz */ 342 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 343 1488, 1696, 0, 800, 803, 809, 838, 0, 344 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 345 /* 0x1e - 1280x800@85Hz */ 346 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 347 1496, 1712, 0, 800, 803, 809, 843, 0, 348 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 349 /* 0x1f - 1280x800@120Hz RB */ 350 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 351 1360, 1440, 0, 800, 803, 809, 847, 0, 352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 353 /* 0x20 - 1280x960@60Hz */ 354 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 355 1488, 1800, 0, 960, 961, 964, 1000, 0, 356 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 357 /* 0x21 - 1280x960@85Hz */ 358 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 359 1504, 1728, 0, 960, 961, 964, 1011, 0, 360 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 361 /* 0x22 - 1280x960@120Hz RB */ 362 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 363 1360, 1440, 0, 960, 963, 967, 1017, 0, 364 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 365 /* 0x23 - 1280x1024@60Hz */ 366 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 367 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 369 /* 0x24 - 1280x1024@75Hz */ 370 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 371 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 373 /* 0x25 - 1280x1024@85Hz */ 374 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 375 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 377 /* 0x26 - 1280x1024@120Hz RB */ 378 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 379 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 381 /* 0x27 - 1360x768@60Hz */ 382 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 383 1536, 1792, 0, 768, 771, 777, 795, 0, 384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 385 /* 0x28 - 1360x768@120Hz RB */ 386 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 387 1440, 1520, 0, 768, 771, 776, 813, 0, 388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 389 /* 0x51 - 1366x768@60Hz */ 390 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 391 1579, 1792, 0, 768, 771, 774, 798, 0, 392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 393 /* 0x56 - 1366x768@60Hz */ 394 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 395 1436, 1500, 0, 768, 769, 772, 800, 0, 396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 397 /* 0x29 - 1400x1050@60Hz RB */ 398 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 399 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 401 /* 0x2a - 1400x1050@60Hz */ 402 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 403 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 404 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 405 /* 0x2b - 1400x1050@75Hz */ 406 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 407 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 408 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 409 /* 0x2c - 1400x1050@85Hz */ 410 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 411 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 412 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 413 /* 0x2d - 1400x1050@120Hz RB */ 414 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 415 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 417 /* 0x2e - 1440x900@60Hz RB */ 418 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 419 1520, 1600, 0, 900, 903, 909, 926, 0, 420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 421 /* 0x2f - 1440x900@60Hz */ 422 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 423 1672, 1904, 0, 900, 903, 909, 934, 0, 424 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 425 /* 0x30 - 1440x900@75Hz */ 426 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 427 1688, 1936, 0, 900, 903, 909, 942, 0, 428 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 429 /* 0x31 - 1440x900@85Hz */ 430 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 431 1696, 1952, 0, 900, 903, 909, 948, 0, 432 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 433 /* 0x32 - 1440x900@120Hz RB */ 434 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 435 1520, 1600, 0, 900, 903, 909, 953, 0, 436 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 437 /* 0x53 - 1600x900@60Hz */ 438 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 439 1704, 1800, 0, 900, 901, 904, 1000, 0, 440 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 441 /* 0x33 - 1600x1200@60Hz */ 442 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 443 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 444 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 445 /* 0x34 - 1600x1200@65Hz */ 446 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 447 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 448 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 449 /* 0x35 - 1600x1200@70Hz */ 450 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 451 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 452 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 453 /* 0x36 - 1600x1200@75Hz */ 454 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 455 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 457 /* 0x37 - 1600x1200@85Hz */ 458 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 459 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 461 /* 0x38 - 1600x1200@120Hz RB */ 462 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 463 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 464 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 465 /* 0x39 - 1680x1050@60Hz RB */ 466 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 467 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 469 /* 0x3a - 1680x1050@60Hz */ 470 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 471 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 472 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 473 /* 0x3b - 1680x1050@75Hz */ 474 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 475 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 476 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 477 /* 0x3c - 1680x1050@85Hz */ 478 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 479 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 480 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 481 /* 0x3d - 1680x1050@120Hz RB */ 482 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 483 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 485 /* 0x3e - 1792x1344@60Hz */ 486 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 487 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 488 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 489 /* 0x3f - 1792x1344@75Hz */ 490 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 491 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 492 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 493 /* 0x40 - 1792x1344@120Hz RB */ 494 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 495 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 497 /* 0x41 - 1856x1392@60Hz */ 498 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 499 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 500 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 501 /* 0x42 - 1856x1392@75Hz */ 502 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 503 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 504 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 505 /* 0x43 - 1856x1392@120Hz RB */ 506 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 507 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 508 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 509 /* 0x52 - 1920x1080@60Hz */ 510 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 511 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 512 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 513 /* 0x44 - 1920x1200@60Hz RB */ 514 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 515 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 517 /* 0x45 - 1920x1200@60Hz */ 518 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 519 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 520 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 521 /* 0x46 - 1920x1200@75Hz */ 522 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 523 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 524 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 525 /* 0x47 - 1920x1200@85Hz */ 526 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 527 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 528 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 529 /* 0x48 - 1920x1200@120Hz RB */ 530 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 531 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 532 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 533 /* 0x49 - 1920x1440@60Hz */ 534 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 535 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 536 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 537 /* 0x4a - 1920x1440@75Hz */ 538 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 539 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 540 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 541 /* 0x4b - 1920x1440@120Hz RB */ 542 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 543 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 544 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 545 /* 0x54 - 2048x1152@60Hz */ 546 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 547 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 548 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 549 /* 0x4c - 2560x1600@60Hz RB */ 550 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 551 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 553 /* 0x4d - 2560x1600@60Hz */ 554 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 555 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 556 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 557 /* 0x4e - 2560x1600@75Hz */ 558 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 559 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 560 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 561 /* 0x4f - 2560x1600@85Hz */ 562 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 563 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 564 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 565 /* 0x50 - 2560x1600@120Hz RB */ 566 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 567 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 568 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 569 /* 0x57 - 4096x2160@60Hz RB */ 570 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 571 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 572 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 573 /* 0x58 - 4096x2160@59.94Hz RB */ 574 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 575 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 576 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 577 }; 578 579 /* 580 * These more or less come from the DMT spec. The 720x400 modes are 581 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 582 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 583 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 584 * mode. 585 * 586 * The DMT modes have been fact-checked; the rest are mild guesses. 587 */ 588 static const struct drm_display_mode edid_est_modes[] = { 589 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 590 968, 1056, 0, 600, 601, 605, 628, 0, 591 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 592 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 593 896, 1024, 0, 600, 601, 603, 625, 0, 594 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 595 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 596 720, 840, 0, 480, 481, 484, 500, 0, 597 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 598 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 599 704, 832, 0, 480, 489, 492, 520, 0, 600 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 601 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 602 768, 864, 0, 480, 483, 486, 525, 0, 603 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 604 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 605 752, 800, 0, 480, 490, 492, 525, 0, 606 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 607 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 608 846, 900, 0, 400, 421, 423, 449, 0, 609 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 610 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 611 846, 900, 0, 400, 412, 414, 449, 0, 612 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 613 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 614 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 615 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 616 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 617 1136, 1312, 0, 768, 769, 772, 800, 0, 618 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 619 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 620 1184, 1328, 0, 768, 771, 777, 806, 0, 621 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 622 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 623 1184, 1344, 0, 768, 771, 777, 806, 0, 624 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 625 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 626 1208, 1264, 0, 768, 768, 776, 817, 0, 627 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 628 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 629 928, 1152, 0, 624, 625, 628, 667, 0, 630 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 631 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 632 896, 1056, 0, 600, 601, 604, 625, 0, 633 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 634 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 635 976, 1040, 0, 600, 637, 643, 666, 0, 636 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 637 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 638 1344, 1600, 0, 864, 865, 868, 900, 0, 639 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 640 }; 641 642 struct minimode { 643 short w; 644 short h; 645 short r; 646 short rb; 647 }; 648 649 static const struct minimode est3_modes[] = { 650 /* byte 6 */ 651 { 640, 350, 85, 0 }, 652 { 640, 400, 85, 0 }, 653 { 720, 400, 85, 0 }, 654 { 640, 480, 85, 0 }, 655 { 848, 480, 60, 0 }, 656 { 800, 600, 85, 0 }, 657 { 1024, 768, 85, 0 }, 658 { 1152, 864, 75, 0 }, 659 /* byte 7 */ 660 { 1280, 768, 60, 1 }, 661 { 1280, 768, 60, 0 }, 662 { 1280, 768, 75, 0 }, 663 { 1280, 768, 85, 0 }, 664 { 1280, 960, 60, 0 }, 665 { 1280, 960, 85, 0 }, 666 { 1280, 1024, 60, 0 }, 667 { 1280, 1024, 85, 0 }, 668 /* byte 8 */ 669 { 1360, 768, 60, 0 }, 670 { 1440, 900, 60, 1 }, 671 { 1440, 900, 60, 0 }, 672 { 1440, 900, 75, 0 }, 673 { 1440, 900, 85, 0 }, 674 { 1400, 1050, 60, 1 }, 675 { 1400, 1050, 60, 0 }, 676 { 1400, 1050, 75, 0 }, 677 /* byte 9 */ 678 { 1400, 1050, 85, 0 }, 679 { 1680, 1050, 60, 1 }, 680 { 1680, 1050, 60, 0 }, 681 { 1680, 1050, 75, 0 }, 682 { 1680, 1050, 85, 0 }, 683 { 1600, 1200, 60, 0 }, 684 { 1600, 1200, 65, 0 }, 685 { 1600, 1200, 70, 0 }, 686 /* byte 10 */ 687 { 1600, 1200, 75, 0 }, 688 { 1600, 1200, 85, 0 }, 689 { 1792, 1344, 60, 0 }, 690 { 1792, 1344, 75, 0 }, 691 { 1856, 1392, 60, 0 }, 692 { 1856, 1392, 75, 0 }, 693 { 1920, 1200, 60, 1 }, 694 { 1920, 1200, 60, 0 }, 695 /* byte 11 */ 696 { 1920, 1200, 75, 0 }, 697 { 1920, 1200, 85, 0 }, 698 { 1920, 1440, 60, 0 }, 699 { 1920, 1440, 75, 0 }, 700 }; 701 702 static const struct minimode extra_modes[] = { 703 { 1024, 576, 60, 0 }, 704 { 1366, 768, 60, 0 }, 705 { 1600, 900, 60, 0 }, 706 { 1680, 945, 60, 0 }, 707 { 1920, 1080, 60, 0 }, 708 { 2048, 1152, 60, 0 }, 709 { 2048, 1536, 60, 0 }, 710 }; 711 712 /* 713 * From CEA/CTA-861 spec. 714 * 715 * Do not access directly, instead always use cea_mode_for_vic(). 716 */ 717 static const struct drm_display_mode edid_cea_modes_1[] = { 718 /* 1 - 640x480@60Hz 4:3 */ 719 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 720 752, 800, 0, 480, 490, 492, 525, 0, 721 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 722 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 723 /* 2 - 720x480@60Hz 4:3 */ 724 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 725 798, 858, 0, 480, 489, 495, 525, 0, 726 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 727 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 728 /* 3 - 720x480@60Hz 16:9 */ 729 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 730 798, 858, 0, 480, 489, 495, 525, 0, 731 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 732 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 733 /* 4 - 1280x720@60Hz 16:9 */ 734 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 735 1430, 1650, 0, 720, 725, 730, 750, 0, 736 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 737 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 738 /* 5 - 1920x1080i@60Hz 16:9 */ 739 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 740 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 741 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 742 DRM_MODE_FLAG_INTERLACE), 743 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 744 /* 6 - 720(1440)x480i@60Hz 4:3 */ 745 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 746 801, 858, 0, 480, 488, 494, 525, 0, 747 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 748 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 749 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 750 /* 7 - 720(1440)x480i@60Hz 16:9 */ 751 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 752 801, 858, 0, 480, 488, 494, 525, 0, 753 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 754 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 755 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 756 /* 8 - 720(1440)x240@60Hz 4:3 */ 757 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 758 801, 858, 0, 240, 244, 247, 262, 0, 759 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 760 DRM_MODE_FLAG_DBLCLK), 761 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 762 /* 9 - 720(1440)x240@60Hz 16:9 */ 763 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 764 801, 858, 0, 240, 244, 247, 262, 0, 765 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 766 DRM_MODE_FLAG_DBLCLK), 767 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 768 /* 10 - 2880x480i@60Hz 4:3 */ 769 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 770 3204, 3432, 0, 480, 488, 494, 525, 0, 771 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 772 DRM_MODE_FLAG_INTERLACE), 773 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 774 /* 11 - 2880x480i@60Hz 16:9 */ 775 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 776 3204, 3432, 0, 480, 488, 494, 525, 0, 777 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 778 DRM_MODE_FLAG_INTERLACE), 779 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 780 /* 12 - 2880x240@60Hz 4:3 */ 781 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 782 3204, 3432, 0, 240, 244, 247, 262, 0, 783 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 784 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 785 /* 13 - 2880x240@60Hz 16:9 */ 786 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 787 3204, 3432, 0, 240, 244, 247, 262, 0, 788 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 789 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 790 /* 14 - 1440x480@60Hz 4:3 */ 791 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 792 1596, 1716, 0, 480, 489, 495, 525, 0, 793 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 794 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 795 /* 15 - 1440x480@60Hz 16:9 */ 796 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 797 1596, 1716, 0, 480, 489, 495, 525, 0, 798 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 799 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 800 /* 16 - 1920x1080@60Hz 16:9 */ 801 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 802 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 803 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 804 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 805 /* 17 - 720x576@50Hz 4:3 */ 806 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 807 796, 864, 0, 576, 581, 586, 625, 0, 808 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 809 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 810 /* 18 - 720x576@50Hz 16:9 */ 811 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 812 796, 864, 0, 576, 581, 586, 625, 0, 813 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 814 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 815 /* 19 - 1280x720@50Hz 16:9 */ 816 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 817 1760, 1980, 0, 720, 725, 730, 750, 0, 818 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 819 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 820 /* 20 - 1920x1080i@50Hz 16:9 */ 821 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 822 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 823 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 824 DRM_MODE_FLAG_INTERLACE), 825 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 826 /* 21 - 720(1440)x576i@50Hz 4:3 */ 827 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 828 795, 864, 0, 576, 580, 586, 625, 0, 829 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 830 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 831 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 832 /* 22 - 720(1440)x576i@50Hz 16:9 */ 833 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 834 795, 864, 0, 576, 580, 586, 625, 0, 835 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 836 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 837 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 838 /* 23 - 720(1440)x288@50Hz 4:3 */ 839 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 840 795, 864, 0, 288, 290, 293, 312, 0, 841 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 842 DRM_MODE_FLAG_DBLCLK), 843 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 844 /* 24 - 720(1440)x288@50Hz 16:9 */ 845 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 846 795, 864, 0, 288, 290, 293, 312, 0, 847 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 848 DRM_MODE_FLAG_DBLCLK), 849 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 850 /* 25 - 2880x576i@50Hz 4:3 */ 851 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 852 3180, 3456, 0, 576, 580, 586, 625, 0, 853 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 854 DRM_MODE_FLAG_INTERLACE), 855 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 856 /* 26 - 2880x576i@50Hz 16:9 */ 857 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 858 3180, 3456, 0, 576, 580, 586, 625, 0, 859 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 860 DRM_MODE_FLAG_INTERLACE), 861 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 862 /* 27 - 2880x288@50Hz 4:3 */ 863 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 864 3180, 3456, 0, 288, 290, 293, 312, 0, 865 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 866 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 867 /* 28 - 2880x288@50Hz 16:9 */ 868 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 869 3180, 3456, 0, 288, 290, 293, 312, 0, 870 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 871 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 872 /* 29 - 1440x576@50Hz 4:3 */ 873 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 874 1592, 1728, 0, 576, 581, 586, 625, 0, 875 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 876 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 877 /* 30 - 1440x576@50Hz 16:9 */ 878 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 879 1592, 1728, 0, 576, 581, 586, 625, 0, 880 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 881 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 882 /* 31 - 1920x1080@50Hz 16:9 */ 883 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 884 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 885 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 886 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 887 /* 32 - 1920x1080@24Hz 16:9 */ 888 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 889 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 890 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 891 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 892 /* 33 - 1920x1080@25Hz 16:9 */ 893 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 894 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 895 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 896 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 897 /* 34 - 1920x1080@30Hz 16:9 */ 898 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 899 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 900 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 901 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 902 /* 35 - 2880x480@60Hz 4:3 */ 903 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 904 3192, 3432, 0, 480, 489, 495, 525, 0, 905 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 906 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 907 /* 36 - 2880x480@60Hz 16:9 */ 908 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 909 3192, 3432, 0, 480, 489, 495, 525, 0, 910 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 911 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 912 /* 37 - 2880x576@50Hz 4:3 */ 913 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 914 3184, 3456, 0, 576, 581, 586, 625, 0, 915 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 916 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 917 /* 38 - 2880x576@50Hz 16:9 */ 918 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 919 3184, 3456, 0, 576, 581, 586, 625, 0, 920 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 921 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 922 /* 39 - 1920x1080i@50Hz 16:9 */ 923 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 924 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 925 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 926 DRM_MODE_FLAG_INTERLACE), 927 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 928 /* 40 - 1920x1080i@100Hz 16:9 */ 929 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 930 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 931 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 932 DRM_MODE_FLAG_INTERLACE), 933 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 934 /* 41 - 1280x720@100Hz 16:9 */ 935 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 936 1760, 1980, 0, 720, 725, 730, 750, 0, 937 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 938 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 939 /* 42 - 720x576@100Hz 4:3 */ 940 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 941 796, 864, 0, 576, 581, 586, 625, 0, 942 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 943 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 944 /* 43 - 720x576@100Hz 16:9 */ 945 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 946 796, 864, 0, 576, 581, 586, 625, 0, 947 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 948 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 949 /* 44 - 720(1440)x576i@100Hz 4:3 */ 950 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 951 795, 864, 0, 576, 580, 586, 625, 0, 952 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 953 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 954 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 955 /* 45 - 720(1440)x576i@100Hz 16:9 */ 956 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 957 795, 864, 0, 576, 580, 586, 625, 0, 958 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 959 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 960 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 961 /* 46 - 1920x1080i@120Hz 16:9 */ 962 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 963 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 964 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 965 DRM_MODE_FLAG_INTERLACE), 966 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 967 /* 47 - 1280x720@120Hz 16:9 */ 968 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 969 1430, 1650, 0, 720, 725, 730, 750, 0, 970 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 971 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 972 /* 48 - 720x480@120Hz 4:3 */ 973 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 974 798, 858, 0, 480, 489, 495, 525, 0, 975 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 976 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 977 /* 49 - 720x480@120Hz 16:9 */ 978 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 979 798, 858, 0, 480, 489, 495, 525, 0, 980 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 981 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 982 /* 50 - 720(1440)x480i@120Hz 4:3 */ 983 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 984 801, 858, 0, 480, 488, 494, 525, 0, 985 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 986 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 987 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 988 /* 51 - 720(1440)x480i@120Hz 16:9 */ 989 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 990 801, 858, 0, 480, 488, 494, 525, 0, 991 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 992 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 993 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 994 /* 52 - 720x576@200Hz 4:3 */ 995 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 996 796, 864, 0, 576, 581, 586, 625, 0, 997 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 998 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 999 /* 53 - 720x576@200Hz 16:9 */ 1000 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1001 796, 864, 0, 576, 581, 586, 625, 0, 1002 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1003 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1004 /* 54 - 720(1440)x576i@200Hz 4:3 */ 1005 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1006 795, 864, 0, 576, 580, 586, 625, 0, 1007 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1008 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1009 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1010 /* 55 - 720(1440)x576i@200Hz 16:9 */ 1011 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1012 795, 864, 0, 576, 580, 586, 625, 0, 1013 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1014 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1015 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1016 /* 56 - 720x480@240Hz 4:3 */ 1017 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1018 798, 858, 0, 480, 489, 495, 525, 0, 1019 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1020 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1021 /* 57 - 720x480@240Hz 16:9 */ 1022 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1023 798, 858, 0, 480, 489, 495, 525, 0, 1024 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1025 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1026 /* 58 - 720(1440)x480i@240Hz 4:3 */ 1027 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1028 801, 858, 0, 480, 488, 494, 525, 0, 1029 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1030 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1031 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1032 /* 59 - 720(1440)x480i@240Hz 16:9 */ 1033 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1034 801, 858, 0, 480, 488, 494, 525, 0, 1035 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1036 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1037 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1038 /* 60 - 1280x720@24Hz 16:9 */ 1039 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1040 3080, 3300, 0, 720, 725, 730, 750, 0, 1041 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1042 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1043 /* 61 - 1280x720@25Hz 16:9 */ 1044 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1045 3740, 3960, 0, 720, 725, 730, 750, 0, 1046 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1047 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1048 /* 62 - 1280x720@30Hz 16:9 */ 1049 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1050 3080, 3300, 0, 720, 725, 730, 750, 0, 1051 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1052 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1053 /* 63 - 1920x1080@120Hz 16:9 */ 1054 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1055 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1056 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1057 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1058 /* 64 - 1920x1080@100Hz 16:9 */ 1059 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1060 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1061 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1062 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1063 /* 65 - 1280x720@24Hz 64:27 */ 1064 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1065 3080, 3300, 0, 720, 725, 730, 750, 0, 1066 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1067 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1068 /* 66 - 1280x720@25Hz 64:27 */ 1069 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1070 3740, 3960, 0, 720, 725, 730, 750, 0, 1071 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1072 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1073 /* 67 - 1280x720@30Hz 64:27 */ 1074 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1075 3080, 3300, 0, 720, 725, 730, 750, 0, 1076 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1077 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1078 /* 68 - 1280x720@50Hz 64:27 */ 1079 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1080 1760, 1980, 0, 720, 725, 730, 750, 0, 1081 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1082 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1083 /* 69 - 1280x720@60Hz 64:27 */ 1084 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1085 1430, 1650, 0, 720, 725, 730, 750, 0, 1086 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1087 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1088 /* 70 - 1280x720@100Hz 64:27 */ 1089 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1090 1760, 1980, 0, 720, 725, 730, 750, 0, 1091 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1092 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1093 /* 71 - 1280x720@120Hz 64:27 */ 1094 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1095 1430, 1650, 0, 720, 725, 730, 750, 0, 1096 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1097 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1098 /* 72 - 1920x1080@24Hz 64:27 */ 1099 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1100 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1101 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1102 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1103 /* 73 - 1920x1080@25Hz 64:27 */ 1104 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1105 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1106 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1107 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1108 /* 74 - 1920x1080@30Hz 64:27 */ 1109 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1110 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1111 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1112 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1113 /* 75 - 1920x1080@50Hz 64:27 */ 1114 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1115 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1116 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1117 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1118 /* 76 - 1920x1080@60Hz 64:27 */ 1119 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1120 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1121 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1122 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1123 /* 77 - 1920x1080@100Hz 64:27 */ 1124 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1125 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1126 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1127 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1128 /* 78 - 1920x1080@120Hz 64:27 */ 1129 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1130 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1131 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1132 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1133 /* 79 - 1680x720@24Hz 64:27 */ 1134 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 1135 3080, 3300, 0, 720, 725, 730, 750, 0, 1136 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1137 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1138 /* 80 - 1680x720@25Hz 64:27 */ 1139 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 1140 2948, 3168, 0, 720, 725, 730, 750, 0, 1141 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1142 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1143 /* 81 - 1680x720@30Hz 64:27 */ 1144 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 1145 2420, 2640, 0, 720, 725, 730, 750, 0, 1146 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1147 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1148 /* 82 - 1680x720@50Hz 64:27 */ 1149 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1150 1980, 2200, 0, 720, 725, 730, 750, 0, 1151 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1152 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1153 /* 83 - 1680x720@60Hz 64:27 */ 1154 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1155 1980, 2200, 0, 720, 725, 730, 750, 0, 1156 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1157 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1158 /* 84 - 1680x720@100Hz 64:27 */ 1159 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1160 1780, 2000, 0, 720, 725, 730, 825, 0, 1161 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1162 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1163 /* 85 - 1680x720@120Hz 64:27 */ 1164 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1165 1780, 2000, 0, 720, 725, 730, 825, 0, 1166 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1167 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1168 /* 86 - 2560x1080@24Hz 64:27 */ 1169 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 1170 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1171 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1172 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1173 /* 87 - 2560x1080@25Hz 64:27 */ 1174 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 1175 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, 1176 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1177 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1178 /* 88 - 2560x1080@30Hz 64:27 */ 1179 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 1180 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, 1181 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1182 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1183 /* 89 - 2560x1080@50Hz 64:27 */ 1184 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 1185 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, 1186 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1187 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1188 /* 90 - 2560x1080@60Hz 64:27 */ 1189 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 1190 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, 1191 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1192 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1193 /* 91 - 2560x1080@100Hz 64:27 */ 1194 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 1195 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, 1196 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1197 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1198 /* 92 - 2560x1080@120Hz 64:27 */ 1199 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 1200 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, 1201 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1202 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1203 /* 93 - 3840x2160@24Hz 16:9 */ 1204 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1205 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1206 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1207 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1208 /* 94 - 3840x2160@25Hz 16:9 */ 1209 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1210 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1211 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1212 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1213 /* 95 - 3840x2160@30Hz 16:9 */ 1214 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1215 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1216 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1217 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1218 /* 96 - 3840x2160@50Hz 16:9 */ 1219 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1220 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1221 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1222 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1223 /* 97 - 3840x2160@60Hz 16:9 */ 1224 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1225 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1226 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1227 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1228 /* 98 - 4096x2160@24Hz 256:135 */ 1229 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1230 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1231 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1232 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1233 /* 99 - 4096x2160@25Hz 256:135 */ 1234 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1235 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1237 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1238 /* 100 - 4096x2160@30Hz 256:135 */ 1239 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1240 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1241 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1242 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1243 /* 101 - 4096x2160@50Hz 256:135 */ 1244 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1245 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1246 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1247 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1248 /* 102 - 4096x2160@60Hz 256:135 */ 1249 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1250 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1251 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1252 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1253 /* 103 - 3840x2160@24Hz 64:27 */ 1254 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1255 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1257 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1258 /* 104 - 3840x2160@25Hz 64:27 */ 1259 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1260 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1261 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1262 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1263 /* 105 - 3840x2160@30Hz 64:27 */ 1264 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1265 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1266 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1267 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1268 /* 106 - 3840x2160@50Hz 64:27 */ 1269 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1270 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1271 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1272 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1273 /* 107 - 3840x2160@60Hz 64:27 */ 1274 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1275 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1277 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1278 /* 108 - 1280x720@48Hz 16:9 */ 1279 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1280 2280, 2500, 0, 720, 725, 730, 750, 0, 1281 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1282 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1283 /* 109 - 1280x720@48Hz 64:27 */ 1284 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1285 2280, 2500, 0, 720, 725, 730, 750, 0, 1286 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1287 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1288 /* 110 - 1680x720@48Hz 64:27 */ 1289 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490, 1290 2530, 2750, 0, 720, 725, 730, 750, 0, 1291 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1292 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1293 /* 111 - 1920x1080@48Hz 16:9 */ 1294 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1295 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1297 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1298 /* 112 - 1920x1080@48Hz 64:27 */ 1299 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1300 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1302 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1303 /* 113 - 2560x1080@48Hz 64:27 */ 1304 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558, 1305 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1306 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1307 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1308 /* 114 - 3840x2160@48Hz 16:9 */ 1309 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1310 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1311 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1312 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1313 /* 115 - 4096x2160@48Hz 256:135 */ 1314 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116, 1315 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1317 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1318 /* 116 - 3840x2160@48Hz 64:27 */ 1319 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1320 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1321 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1322 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1323 /* 117 - 3840x2160@100Hz 16:9 */ 1324 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1325 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1326 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1327 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1328 /* 118 - 3840x2160@120Hz 16:9 */ 1329 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1330 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1331 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1332 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1333 /* 119 - 3840x2160@100Hz 64:27 */ 1334 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1335 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1337 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1338 /* 120 - 3840x2160@120Hz 64:27 */ 1339 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1340 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1341 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1342 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1343 /* 121 - 5120x2160@24Hz 64:27 */ 1344 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116, 1345 7204, 7500, 0, 2160, 2168, 2178, 2200, 0, 1346 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1347 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1348 /* 122 - 5120x2160@25Hz 64:27 */ 1349 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816, 1350 6904, 7200, 0, 2160, 2168, 2178, 2200, 0, 1351 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1352 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1353 /* 123 - 5120x2160@30Hz 64:27 */ 1354 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784, 1355 5872, 6000, 0, 2160, 2168, 2178, 2200, 0, 1356 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1357 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1358 /* 124 - 5120x2160@48Hz 64:27 */ 1359 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866, 1360 5954, 6250, 0, 2160, 2168, 2178, 2475, 0, 1361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1362 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1363 /* 125 - 5120x2160@50Hz 64:27 */ 1364 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216, 1365 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1366 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1367 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1368 /* 126 - 5120x2160@60Hz 64:27 */ 1369 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284, 1370 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1371 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1372 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1373 /* 127 - 5120x2160@100Hz 64:27 */ 1374 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216, 1375 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1377 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1378 }; 1379 1380 /* 1381 * From CEA/CTA-861 spec. 1382 * 1383 * Do not access directly, instead always use cea_mode_for_vic(). 1384 */ 1385 static const struct drm_display_mode edid_cea_modes_193[] = { 1386 /* 193 - 5120x2160@120Hz 64:27 */ 1387 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284, 1388 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1390 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1391 /* 194 - 7680x4320@24Hz 16:9 */ 1392 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1393 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1394 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1395 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1396 /* 195 - 7680x4320@25Hz 16:9 */ 1397 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1398 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1399 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1400 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1401 /* 196 - 7680x4320@30Hz 16:9 */ 1402 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1403 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1404 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1405 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1406 /* 197 - 7680x4320@48Hz 16:9 */ 1407 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1408 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1409 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1410 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1411 /* 198 - 7680x4320@50Hz 16:9 */ 1412 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1413 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1414 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1415 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1416 /* 199 - 7680x4320@60Hz 16:9 */ 1417 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1418 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1419 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1420 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1421 /* 200 - 7680x4320@100Hz 16:9 */ 1422 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1423 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1424 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1425 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1426 /* 201 - 7680x4320@120Hz 16:9 */ 1427 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1428 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1429 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1430 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1431 /* 202 - 7680x4320@24Hz 64:27 */ 1432 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1433 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1434 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1435 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1436 /* 203 - 7680x4320@25Hz 64:27 */ 1437 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1438 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1439 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1440 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1441 /* 204 - 7680x4320@30Hz 64:27 */ 1442 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1443 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1444 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1445 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1446 /* 205 - 7680x4320@48Hz 64:27 */ 1447 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1448 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1450 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1451 /* 206 - 7680x4320@50Hz 64:27 */ 1452 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1453 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1454 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1455 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1456 /* 207 - 7680x4320@60Hz 64:27 */ 1457 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1458 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1459 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1460 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1461 /* 208 - 7680x4320@100Hz 64:27 */ 1462 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1463 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1464 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1465 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1466 /* 209 - 7680x4320@120Hz 64:27 */ 1467 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1468 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1470 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1471 /* 210 - 10240x4320@24Hz 64:27 */ 1472 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732, 1473 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1474 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1475 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1476 /* 211 - 10240x4320@25Hz 64:27 */ 1477 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732, 1478 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1479 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1480 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1481 /* 212 - 10240x4320@30Hz 64:27 */ 1482 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528, 1483 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1485 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1486 /* 213 - 10240x4320@48Hz 64:27 */ 1487 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732, 1488 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1489 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1490 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1491 /* 214 - 10240x4320@50Hz 64:27 */ 1492 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732, 1493 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1494 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1495 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1496 /* 215 - 10240x4320@60Hz 64:27 */ 1497 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528, 1498 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1499 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1500 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1501 /* 216 - 10240x4320@100Hz 64:27 */ 1502 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432, 1503 12608, 13200, 0, 4320, 4336, 4356, 4500, 0, 1504 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1505 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1506 /* 217 - 10240x4320@120Hz 64:27 */ 1507 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528, 1508 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1509 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1510 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1511 /* 218 - 4096x2160@100Hz 256:135 */ 1512 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896, 1513 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1514 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1515 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1516 /* 219 - 4096x2160@120Hz 256:135 */ 1517 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184, 1518 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1519 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1520 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1521 }; 1522 1523 /* 1524 * HDMI 1.4 4k modes. Index using the VIC. 1525 */ 1526 static const struct drm_display_mode edid_4k_modes[] = { 1527 /* 0 - dummy, VICs start at 1 */ 1528 { }, 1529 /* 1 - 3840x2160@30Hz */ 1530 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1531 3840, 4016, 4104, 4400, 0, 1532 2160, 2168, 2178, 2250, 0, 1533 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1534 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1535 /* 2 - 3840x2160@25Hz */ 1536 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1537 3840, 4896, 4984, 5280, 0, 1538 2160, 2168, 2178, 2250, 0, 1539 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1540 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1541 /* 3 - 3840x2160@24Hz */ 1542 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1543 3840, 5116, 5204, 5500, 0, 1544 2160, 2168, 2178, 2250, 0, 1545 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1546 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1547 /* 4 - 4096x2160@24Hz (SMPTE) */ 1548 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1549 4096, 5116, 5204, 5500, 0, 1550 2160, 2168, 2178, 2250, 0, 1551 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1552 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1553 }; 1554 1555 /*** DDC fetch and block validation ***/ 1556 1557 static const u8 edid_header[] = { 1558 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1559 }; 1560 1561 /** 1562 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1563 * @raw_edid: pointer to raw base EDID block 1564 * 1565 * Sanity check the header of the base EDID block. 1566 * 1567 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1568 */ 1569 int drm_edid_header_is_valid(const u8 *raw_edid) 1570 { 1571 int i, score = 0; 1572 1573 for (i = 0; i < sizeof(edid_header); i++) 1574 if (raw_edid[i] == edid_header[i]) 1575 score++; 1576 1577 return score; 1578 } 1579 EXPORT_SYMBOL(drm_edid_header_is_valid); 1580 1581 static int edid_fixup __read_mostly = 6; 1582 module_param_named(edid_fixup, edid_fixup, int, 0400); 1583 MODULE_PARM_DESC(edid_fixup, 1584 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1585 1586 static int validate_displayid(u8 *displayid, int length, int idx); 1587 1588 static int drm_edid_block_checksum(const u8 *raw_edid) 1589 { 1590 int i; 1591 u8 csum = 0, crc = 0; 1592 1593 for (i = 0; i < EDID_LENGTH - 1; i++) 1594 csum += raw_edid[i]; 1595 1596 crc = 0x100 - csum; 1597 1598 return crc; 1599 } 1600 1601 static bool drm_edid_block_checksum_diff(const u8 *raw_edid, u8 real_checksum) 1602 { 1603 if (raw_edid[EDID_LENGTH - 1] != real_checksum) 1604 return true; 1605 else 1606 return false; 1607 } 1608 1609 static bool drm_edid_is_zero(const u8 *in_edid, int length) 1610 { 1611 if (memchr_inv(in_edid, 0, length)) 1612 return false; 1613 1614 return true; 1615 } 1616 1617 /** 1618 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1619 * @raw_edid: pointer to raw EDID block 1620 * @block: type of block to validate (0 for base, extension otherwise) 1621 * @print_bad_edid: if true, dump bad EDID blocks to the console 1622 * @edid_corrupt: if true, the header or checksum is invalid 1623 * 1624 * Validate a base or extension EDID block and optionally dump bad blocks to 1625 * the console. 1626 * 1627 * Return: True if the block is valid, false otherwise. 1628 */ 1629 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 1630 bool *edid_corrupt) 1631 { 1632 u8 csum; 1633 struct edid *edid = (struct edid *)raw_edid; 1634 1635 if (WARN_ON(!raw_edid)) 1636 return false; 1637 1638 if (edid_fixup > 8 || edid_fixup < 0) 1639 edid_fixup = 6; 1640 1641 if (block == 0) { 1642 int score = drm_edid_header_is_valid(raw_edid); 1643 if (score == 8) { 1644 if (edid_corrupt) 1645 *edid_corrupt = false; 1646 } else if (score >= edid_fixup) { 1647 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 1648 * The corrupt flag needs to be set here otherwise, the 1649 * fix-up code here will correct the problem, the 1650 * checksum is correct and the test fails 1651 */ 1652 if (edid_corrupt) 1653 *edid_corrupt = true; 1654 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1655 memcpy(raw_edid, edid_header, sizeof(edid_header)); 1656 } else { 1657 if (edid_corrupt) 1658 *edid_corrupt = true; 1659 goto bad; 1660 } 1661 } 1662 1663 csum = drm_edid_block_checksum(raw_edid); 1664 if (drm_edid_block_checksum_diff(raw_edid, csum)) { 1665 if (edid_corrupt) 1666 *edid_corrupt = true; 1667 1668 /* allow CEA to slide through, switches mangle this */ 1669 if (raw_edid[0] == CEA_EXT) { 1670 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum); 1671 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n"); 1672 } else { 1673 if (print_bad_edid) 1674 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum); 1675 1676 goto bad; 1677 } 1678 } 1679 1680 /* per-block-type checks */ 1681 switch (raw_edid[0]) { 1682 case 0: /* base */ 1683 if (edid->version != 1) { 1684 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version); 1685 goto bad; 1686 } 1687 1688 if (edid->revision > 4) 1689 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1690 break; 1691 1692 default: 1693 break; 1694 } 1695 1696 return true; 1697 1698 bad: 1699 if (print_bad_edid) { 1700 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) { 1701 pr_notice("EDID block is all zeroes\n"); 1702 } else { 1703 pr_notice("Raw EDID:\n"); 1704 print_hex_dump(KERN_NOTICE, 1705 " \t", DUMP_PREFIX_NONE, 16, 1, 1706 raw_edid, EDID_LENGTH, false); 1707 } 1708 } 1709 return false; 1710 } 1711 EXPORT_SYMBOL(drm_edid_block_valid); 1712 1713 /** 1714 * drm_edid_is_valid - sanity check EDID data 1715 * @edid: EDID data 1716 * 1717 * Sanity-check an entire EDID record (including extensions) 1718 * 1719 * Return: True if the EDID data is valid, false otherwise. 1720 */ 1721 bool drm_edid_is_valid(struct edid *edid) 1722 { 1723 int i; 1724 u8 *raw = (u8 *)edid; 1725 1726 if (!edid) 1727 return false; 1728 1729 for (i = 0; i <= edid->extensions; i++) 1730 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL)) 1731 return false; 1732 1733 return true; 1734 } 1735 EXPORT_SYMBOL(drm_edid_is_valid); 1736 1737 #define DDC_SEGMENT_ADDR 0x30 1738 /** 1739 * drm_do_probe_ddc_edid() - get EDID information via I2C 1740 * @data: I2C device adapter 1741 * @buf: EDID data buffer to be filled 1742 * @block: 128 byte EDID block to start fetching from 1743 * @len: EDID data buffer length to fetch 1744 * 1745 * Try to fetch EDID information by calling I2C driver functions. 1746 * 1747 * Return: 0 on success or -1 on failure. 1748 */ 1749 static int 1750 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 1751 { 1752 struct i2c_adapter *adapter = data; 1753 unsigned char start = block * EDID_LENGTH; 1754 unsigned char segment = block >> 1; 1755 unsigned char xfers = segment ? 3 : 2; 1756 int ret, retries = 5; 1757 1758 /* 1759 * The core I2C driver will automatically retry the transfer if the 1760 * adapter reports EAGAIN. However, we find that bit-banging transfers 1761 * are susceptible to errors under a heavily loaded machine and 1762 * generate spurious NAKs and timeouts. Retrying the transfer 1763 * of the individual block a few times seems to overcome this. 1764 */ 1765 do { 1766 struct i2c_msg msgs[] = { 1767 { 1768 .addr = DDC_SEGMENT_ADDR, 1769 .flags = 0, 1770 .len = 1, 1771 .buf = &segment, 1772 }, { 1773 .addr = DDC_ADDR, 1774 .flags = 0, 1775 .len = 1, 1776 .buf = &start, 1777 }, { 1778 .addr = DDC_ADDR, 1779 .flags = I2C_M_RD, 1780 .len = len, 1781 .buf = buf, 1782 } 1783 }; 1784 1785 /* 1786 * Avoid sending the segment addr to not upset non-compliant 1787 * DDC monitors. 1788 */ 1789 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 1790 1791 if (ret == -ENXIO) { 1792 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 1793 adapter->name); 1794 break; 1795 } 1796 } while (ret != xfers && --retries); 1797 1798 return ret == xfers ? 0 : -1; 1799 } 1800 1801 static void connector_bad_edid(struct drm_connector *connector, 1802 u8 *edid, int num_blocks) 1803 { 1804 int i; 1805 u8 num_of_ext = edid[0x7e]; 1806 1807 /* Calculate real checksum for the last edid extension block data */ 1808 connector->real_edid_checksum = 1809 drm_edid_block_checksum(edid + num_of_ext * EDID_LENGTH); 1810 1811 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS)) 1812 return; 1813 1814 dev_warn(connector->dev->dev, 1815 "%s: EDID is invalid:\n", 1816 connector->name); 1817 for (i = 0; i < num_blocks; i++) { 1818 u8 *block = edid + i * EDID_LENGTH; 1819 char prefix[20]; 1820 1821 if (drm_edid_is_zero(block, EDID_LENGTH)) 1822 sprintf(prefix, "\t[%02x] ZERO ", i); 1823 else if (!drm_edid_block_valid(block, i, false, NULL)) 1824 sprintf(prefix, "\t[%02x] BAD ", i); 1825 else 1826 sprintf(prefix, "\t[%02x] GOOD ", i); 1827 1828 print_hex_dump(KERN_WARNING, 1829 prefix, DUMP_PREFIX_NONE, 16, 1, 1830 block, EDID_LENGTH, false); 1831 } 1832 } 1833 1834 /* Get override or firmware EDID */ 1835 static struct edid *drm_get_override_edid(struct drm_connector *connector) 1836 { 1837 struct edid *override = NULL; 1838 1839 if (connector->override_edid) 1840 override = drm_edid_duplicate(connector->edid_blob_ptr->data); 1841 1842 if (!override) 1843 override = drm_load_edid_firmware(connector); 1844 1845 return IS_ERR(override) ? NULL : override; 1846 } 1847 1848 /** 1849 * drm_add_override_edid_modes - add modes from override/firmware EDID 1850 * @connector: connector we're probing 1851 * 1852 * Add modes from the override/firmware EDID, if available. Only to be used from 1853 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe 1854 * failed during drm_get_edid() and caused the override/firmware EDID to be 1855 * skipped. 1856 * 1857 * Return: The number of modes added or 0 if we couldn't find any. 1858 */ 1859 int drm_add_override_edid_modes(struct drm_connector *connector) 1860 { 1861 struct edid *override; 1862 int num_modes = 0; 1863 1864 override = drm_get_override_edid(connector); 1865 if (override) { 1866 drm_connector_update_edid_property(connector, override); 1867 num_modes = drm_add_edid_modes(connector, override); 1868 kfree(override); 1869 1870 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n", 1871 connector->base.id, connector->name, num_modes); 1872 } 1873 1874 return num_modes; 1875 } 1876 EXPORT_SYMBOL(drm_add_override_edid_modes); 1877 1878 /** 1879 * drm_do_get_edid - get EDID data using a custom EDID block read function 1880 * @connector: connector we're probing 1881 * @get_edid_block: EDID block read function 1882 * @data: private data passed to the block read function 1883 * 1884 * When the I2C adapter connected to the DDC bus is hidden behind a device that 1885 * exposes a different interface to read EDID blocks this function can be used 1886 * to get EDID data using a custom block read function. 1887 * 1888 * As in the general case the DDC bus is accessible by the kernel at the I2C 1889 * level, drivers must make all reasonable efforts to expose it as an I2C 1890 * adapter and use drm_get_edid() instead of abusing this function. 1891 * 1892 * The EDID may be overridden using debugfs override_edid or firmare EDID 1893 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority 1894 * order. Having either of them bypasses actual EDID reads. 1895 * 1896 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1897 */ 1898 struct edid *drm_do_get_edid(struct drm_connector *connector, 1899 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 1900 size_t len), 1901 void *data) 1902 { 1903 int i, j = 0, valid_extensions = 0; 1904 u8 *edid, *new; 1905 struct edid *override; 1906 1907 override = drm_get_override_edid(connector); 1908 if (override) 1909 return override; 1910 1911 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) 1912 return NULL; 1913 1914 /* base block fetch */ 1915 for (i = 0; i < 4; i++) { 1916 if (get_edid_block(data, edid, 0, EDID_LENGTH)) 1917 goto out; 1918 if (drm_edid_block_valid(edid, 0, false, 1919 &connector->edid_corrupt)) 1920 break; 1921 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) { 1922 connector->null_edid_counter++; 1923 goto carp; 1924 } 1925 } 1926 if (i == 4) 1927 goto carp; 1928 1929 /* if there's no extensions, we're done */ 1930 valid_extensions = edid[0x7e]; 1931 if (valid_extensions == 0) 1932 return (struct edid *)edid; 1933 1934 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1935 if (!new) 1936 goto out; 1937 edid = new; 1938 1939 for (j = 1; j <= edid[0x7e]; j++) { 1940 u8 *block = edid + j * EDID_LENGTH; 1941 1942 for (i = 0; i < 4; i++) { 1943 if (get_edid_block(data, block, j, EDID_LENGTH)) 1944 goto out; 1945 if (drm_edid_block_valid(block, j, false, NULL)) 1946 break; 1947 } 1948 1949 if (i == 4) 1950 valid_extensions--; 1951 } 1952 1953 if (valid_extensions != edid[0x7e]) { 1954 u8 *base; 1955 1956 connector_bad_edid(connector, edid, edid[0x7e] + 1); 1957 1958 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions; 1959 edid[0x7e] = valid_extensions; 1960 1961 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH, 1962 GFP_KERNEL); 1963 if (!new) 1964 goto out; 1965 1966 base = new; 1967 for (i = 0; i <= edid[0x7e]; i++) { 1968 u8 *block = edid + i * EDID_LENGTH; 1969 1970 if (!drm_edid_block_valid(block, i, false, NULL)) 1971 continue; 1972 1973 memcpy(base, block, EDID_LENGTH); 1974 base += EDID_LENGTH; 1975 } 1976 1977 kfree(edid); 1978 edid = new; 1979 } 1980 1981 return (struct edid *)edid; 1982 1983 carp: 1984 connector_bad_edid(connector, edid, 1); 1985 out: 1986 kfree(edid); 1987 return NULL; 1988 } 1989 EXPORT_SYMBOL_GPL(drm_do_get_edid); 1990 1991 /** 1992 * drm_probe_ddc() - probe DDC presence 1993 * @adapter: I2C adapter to probe 1994 * 1995 * Return: True on success, false on failure. 1996 */ 1997 bool 1998 drm_probe_ddc(struct i2c_adapter *adapter) 1999 { 2000 unsigned char out; 2001 2002 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 2003 } 2004 EXPORT_SYMBOL(drm_probe_ddc); 2005 2006 /** 2007 * drm_get_edid - get EDID data, if available 2008 * @connector: connector we're probing 2009 * @adapter: I2C adapter to use for DDC 2010 * 2011 * Poke the given I2C channel to grab EDID data if possible. If found, 2012 * attach it to the connector. 2013 * 2014 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2015 */ 2016 struct edid *drm_get_edid(struct drm_connector *connector, 2017 struct i2c_adapter *adapter) 2018 { 2019 if (connector->force == DRM_FORCE_OFF) 2020 return NULL; 2021 2022 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2023 return NULL; 2024 2025 return drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); 2026 } 2027 EXPORT_SYMBOL(drm_get_edid); 2028 2029 /** 2030 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 2031 * @connector: connector we're probing 2032 * @adapter: I2C adapter to use for DDC 2033 * 2034 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 2035 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 2036 * switch DDC to the GPU which is retrieving EDID. 2037 * 2038 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2039 */ 2040 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 2041 struct i2c_adapter *adapter) 2042 { 2043 struct pci_dev *pdev = connector->dev->pdev; 2044 struct edid *edid; 2045 2046 vga_switcheroo_lock_ddc(pdev); 2047 edid = drm_get_edid(connector, adapter); 2048 vga_switcheroo_unlock_ddc(pdev); 2049 2050 return edid; 2051 } 2052 EXPORT_SYMBOL(drm_get_edid_switcheroo); 2053 2054 /** 2055 * drm_edid_duplicate - duplicate an EDID and the extensions 2056 * @edid: EDID to duplicate 2057 * 2058 * Return: Pointer to duplicated EDID or NULL on allocation failure. 2059 */ 2060 struct edid *drm_edid_duplicate(const struct edid *edid) 2061 { 2062 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); 2063 } 2064 EXPORT_SYMBOL(drm_edid_duplicate); 2065 2066 /*** EDID parsing ***/ 2067 2068 /** 2069 * edid_vendor - match a string against EDID's obfuscated vendor field 2070 * @edid: EDID to match 2071 * @vendor: vendor string 2072 * 2073 * Returns true if @vendor is in @edid, false otherwise 2074 */ 2075 static bool edid_vendor(const struct edid *edid, const char *vendor) 2076 { 2077 char edid_vendor[3]; 2078 2079 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 2080 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 2081 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 2082 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 2083 2084 return !strncmp(edid_vendor, vendor, 3); 2085 } 2086 2087 /** 2088 * edid_get_quirks - return quirk flags for a given EDID 2089 * @edid: EDID to process 2090 * 2091 * This tells subsequent routines what fixes they need to apply. 2092 */ 2093 static u32 edid_get_quirks(const struct edid *edid) 2094 { 2095 const struct edid_quirk *quirk; 2096 int i; 2097 2098 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 2099 quirk = &edid_quirk_list[i]; 2100 2101 if (edid_vendor(edid, quirk->vendor) && 2102 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 2103 return quirk->quirks; 2104 } 2105 2106 return 0; 2107 } 2108 2109 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 2110 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 2111 2112 /** 2113 * edid_fixup_preferred - set preferred modes based on quirk list 2114 * @connector: has mode list to fix up 2115 * @quirks: quirks list 2116 * 2117 * Walk the mode list for @connector, clearing the preferred status 2118 * on existing modes and setting it anew for the right mode ala @quirks. 2119 */ 2120 static void edid_fixup_preferred(struct drm_connector *connector, 2121 u32 quirks) 2122 { 2123 struct drm_display_mode *t, *cur_mode, *preferred_mode; 2124 int target_refresh = 0; 2125 int cur_vrefresh, preferred_vrefresh; 2126 2127 if (list_empty(&connector->probed_modes)) 2128 return; 2129 2130 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 2131 target_refresh = 60; 2132 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 2133 target_refresh = 75; 2134 2135 preferred_mode = list_first_entry(&connector->probed_modes, 2136 struct drm_display_mode, head); 2137 2138 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 2139 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 2140 2141 if (cur_mode == preferred_mode) 2142 continue; 2143 2144 /* Largest mode is preferred */ 2145 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 2146 preferred_mode = cur_mode; 2147 2148 cur_vrefresh = cur_mode->vrefresh ? 2149 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode); 2150 preferred_vrefresh = preferred_mode->vrefresh ? 2151 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode); 2152 /* At a given size, try to get closest to target refresh */ 2153 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 2154 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 2155 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 2156 preferred_mode = cur_mode; 2157 } 2158 } 2159 2160 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 2161 } 2162 2163 static bool 2164 mode_is_rb(const struct drm_display_mode *mode) 2165 { 2166 return (mode->htotal - mode->hdisplay == 160) && 2167 (mode->hsync_end - mode->hdisplay == 80) && 2168 (mode->hsync_end - mode->hsync_start == 32) && 2169 (mode->vsync_start - mode->vdisplay == 3); 2170 } 2171 2172 /* 2173 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 2174 * @dev: Device to duplicate against 2175 * @hsize: Mode width 2176 * @vsize: Mode height 2177 * @fresh: Mode refresh rate 2178 * @rb: Mode reduced-blanking-ness 2179 * 2180 * Walk the DMT mode list looking for a match for the given parameters. 2181 * 2182 * Return: A newly allocated copy of the mode, or NULL if not found. 2183 */ 2184 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 2185 int hsize, int vsize, int fresh, 2186 bool rb) 2187 { 2188 int i; 2189 2190 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2191 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 2192 if (hsize != ptr->hdisplay) 2193 continue; 2194 if (vsize != ptr->vdisplay) 2195 continue; 2196 if (fresh != drm_mode_vrefresh(ptr)) 2197 continue; 2198 if (rb != mode_is_rb(ptr)) 2199 continue; 2200 2201 return drm_mode_duplicate(dev, ptr); 2202 } 2203 2204 return NULL; 2205 } 2206 EXPORT_SYMBOL(drm_mode_find_dmt); 2207 2208 static bool is_display_descriptor(const u8 d[18], u8 tag) 2209 { 2210 return d[0] == 0x00 && d[1] == 0x00 && 2211 d[2] == 0x00 && d[3] == tag; 2212 } 2213 2214 static bool is_detailed_timing_descriptor(const u8 d[18]) 2215 { 2216 return d[0] != 0x00 || d[1] != 0x00; 2217 } 2218 2219 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 2220 2221 static void 2222 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 2223 { 2224 int i, n; 2225 u8 d = ext[0x02]; 2226 u8 *det_base = ext + d; 2227 2228 if (d < 4 || d > 127) 2229 return; 2230 2231 n = (127 - d) / 18; 2232 for (i = 0; i < n; i++) 2233 cb((struct detailed_timing *)(det_base + 18 * i), closure); 2234 } 2235 2236 static void 2237 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 2238 { 2239 unsigned int i, n = min((int)ext[0x02], 6); 2240 u8 *det_base = ext + 5; 2241 2242 if (ext[0x01] != 1) 2243 return; /* unknown version */ 2244 2245 for (i = 0; i < n; i++) 2246 cb((struct detailed_timing *)(det_base + 18 * i), closure); 2247 } 2248 2249 static void 2250 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 2251 { 2252 int i; 2253 struct edid *edid = (struct edid *)raw_edid; 2254 2255 if (edid == NULL) 2256 return; 2257 2258 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 2259 cb(&(edid->detailed_timings[i]), closure); 2260 2261 for (i = 1; i <= raw_edid[0x7e]; i++) { 2262 u8 *ext = raw_edid + (i * EDID_LENGTH); 2263 switch (*ext) { 2264 case CEA_EXT: 2265 cea_for_each_detailed_block(ext, cb, closure); 2266 break; 2267 case VTB_EXT: 2268 vtb_for_each_detailed_block(ext, cb, closure); 2269 break; 2270 default: 2271 break; 2272 } 2273 } 2274 } 2275 2276 static void 2277 is_rb(struct detailed_timing *t, void *data) 2278 { 2279 u8 *r = (u8 *)t; 2280 2281 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE)) 2282 return; 2283 2284 if (r[15] & 0x10) 2285 *(bool *)data = true; 2286 } 2287 2288 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 2289 static bool 2290 drm_monitor_supports_rb(struct edid *edid) 2291 { 2292 if (edid->revision >= 4) { 2293 bool ret = false; 2294 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 2295 return ret; 2296 } 2297 2298 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 2299 } 2300 2301 static void 2302 find_gtf2(struct detailed_timing *t, void *data) 2303 { 2304 u8 *r = (u8 *)t; 2305 2306 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE)) 2307 return; 2308 2309 if (r[10] == 0x02) 2310 *(u8 **)data = r; 2311 } 2312 2313 /* Secondary GTF curve kicks in above some break frequency */ 2314 static int 2315 drm_gtf2_hbreak(struct edid *edid) 2316 { 2317 u8 *r = NULL; 2318 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2319 return r ? (r[12] * 2) : 0; 2320 } 2321 2322 static int 2323 drm_gtf2_2c(struct edid *edid) 2324 { 2325 u8 *r = NULL; 2326 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2327 return r ? r[13] : 0; 2328 } 2329 2330 static int 2331 drm_gtf2_m(struct edid *edid) 2332 { 2333 u8 *r = NULL; 2334 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2335 return r ? (r[15] << 8) + r[14] : 0; 2336 } 2337 2338 static int 2339 drm_gtf2_k(struct edid *edid) 2340 { 2341 u8 *r = NULL; 2342 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2343 return r ? r[16] : 0; 2344 } 2345 2346 static int 2347 drm_gtf2_2j(struct edid *edid) 2348 { 2349 u8 *r = NULL; 2350 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2351 return r ? r[17] : 0; 2352 } 2353 2354 /** 2355 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 2356 * @edid: EDID block to scan 2357 */ 2358 static int standard_timing_level(struct edid *edid) 2359 { 2360 if (edid->revision >= 2) { 2361 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 2362 return LEVEL_CVT; 2363 if (drm_gtf2_hbreak(edid)) 2364 return LEVEL_GTF2; 2365 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 2366 return LEVEL_GTF; 2367 } 2368 return LEVEL_DMT; 2369 } 2370 2371 /* 2372 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 2373 * monitors fill with ascii space (0x20) instead. 2374 */ 2375 static int 2376 bad_std_timing(u8 a, u8 b) 2377 { 2378 return (a == 0x00 && b == 0x00) || 2379 (a == 0x01 && b == 0x01) || 2380 (a == 0x20 && b == 0x20); 2381 } 2382 2383 static int drm_mode_hsync(const struct drm_display_mode *mode) 2384 { 2385 if (mode->htotal <= 0) 2386 return 0; 2387 2388 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal); 2389 } 2390 2391 /** 2392 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 2393 * @connector: connector of for the EDID block 2394 * @edid: EDID block to scan 2395 * @t: standard timing params 2396 * 2397 * Take the standard timing params (in this case width, aspect, and refresh) 2398 * and convert them into a real mode using CVT/GTF/DMT. 2399 */ 2400 static struct drm_display_mode * 2401 drm_mode_std(struct drm_connector *connector, struct edid *edid, 2402 struct std_timing *t) 2403 { 2404 struct drm_device *dev = connector->dev; 2405 struct drm_display_mode *m, *mode = NULL; 2406 int hsize, vsize; 2407 int vrefresh_rate; 2408 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 2409 >> EDID_TIMING_ASPECT_SHIFT; 2410 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 2411 >> EDID_TIMING_VFREQ_SHIFT; 2412 int timing_level = standard_timing_level(edid); 2413 2414 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 2415 return NULL; 2416 2417 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 2418 hsize = t->hsize * 8 + 248; 2419 /* vrefresh_rate = vfreq + 60 */ 2420 vrefresh_rate = vfreq + 60; 2421 /* the vdisplay is calculated based on the aspect ratio */ 2422 if (aspect_ratio == 0) { 2423 if (edid->revision < 3) 2424 vsize = hsize; 2425 else 2426 vsize = (hsize * 10) / 16; 2427 } else if (aspect_ratio == 1) 2428 vsize = (hsize * 3) / 4; 2429 else if (aspect_ratio == 2) 2430 vsize = (hsize * 4) / 5; 2431 else 2432 vsize = (hsize * 9) / 16; 2433 2434 /* HDTV hack, part 1 */ 2435 if (vrefresh_rate == 60 && 2436 ((hsize == 1360 && vsize == 765) || 2437 (hsize == 1368 && vsize == 769))) { 2438 hsize = 1366; 2439 vsize = 768; 2440 } 2441 2442 /* 2443 * If this connector already has a mode for this size and refresh 2444 * rate (because it came from detailed or CVT info), use that 2445 * instead. This way we don't have to guess at interlace or 2446 * reduced blanking. 2447 */ 2448 list_for_each_entry(m, &connector->probed_modes, head) 2449 if (m->hdisplay == hsize && m->vdisplay == vsize && 2450 drm_mode_vrefresh(m) == vrefresh_rate) 2451 return NULL; 2452 2453 /* HDTV hack, part 2 */ 2454 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 2455 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 2456 false); 2457 if (!mode) 2458 return NULL; 2459 mode->hdisplay = 1366; 2460 mode->hsync_start = mode->hsync_start - 1; 2461 mode->hsync_end = mode->hsync_end - 1; 2462 return mode; 2463 } 2464 2465 /* check whether it can be found in default mode table */ 2466 if (drm_monitor_supports_rb(edid)) { 2467 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 2468 true); 2469 if (mode) 2470 return mode; 2471 } 2472 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 2473 if (mode) 2474 return mode; 2475 2476 /* okay, generate it */ 2477 switch (timing_level) { 2478 case LEVEL_DMT: 2479 break; 2480 case LEVEL_GTF: 2481 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2482 break; 2483 case LEVEL_GTF2: 2484 /* 2485 * This is potentially wrong if there's ever a monitor with 2486 * more than one ranges section, each claiming a different 2487 * secondary GTF curve. Please don't do that. 2488 */ 2489 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2490 if (!mode) 2491 return NULL; 2492 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 2493 drm_mode_destroy(dev, mode); 2494 mode = drm_gtf_mode_complex(dev, hsize, vsize, 2495 vrefresh_rate, 0, 0, 2496 drm_gtf2_m(edid), 2497 drm_gtf2_2c(edid), 2498 drm_gtf2_k(edid), 2499 drm_gtf2_2j(edid)); 2500 } 2501 break; 2502 case LEVEL_CVT: 2503 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 2504 false); 2505 break; 2506 } 2507 return mode; 2508 } 2509 2510 /* 2511 * EDID is delightfully ambiguous about how interlaced modes are to be 2512 * encoded. Our internal representation is of frame height, but some 2513 * HDTV detailed timings are encoded as field height. 2514 * 2515 * The format list here is from CEA, in frame size. Technically we 2516 * should be checking refresh rate too. Whatever. 2517 */ 2518 static void 2519 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 2520 struct detailed_pixel_timing *pt) 2521 { 2522 int i; 2523 static const struct { 2524 int w, h; 2525 } cea_interlaced[] = { 2526 { 1920, 1080 }, 2527 { 720, 480 }, 2528 { 1440, 480 }, 2529 { 2880, 480 }, 2530 { 720, 576 }, 2531 { 1440, 576 }, 2532 { 2880, 576 }, 2533 }; 2534 2535 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 2536 return; 2537 2538 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 2539 if ((mode->hdisplay == cea_interlaced[i].w) && 2540 (mode->vdisplay == cea_interlaced[i].h / 2)) { 2541 mode->vdisplay *= 2; 2542 mode->vsync_start *= 2; 2543 mode->vsync_end *= 2; 2544 mode->vtotal *= 2; 2545 mode->vtotal |= 1; 2546 } 2547 } 2548 2549 mode->flags |= DRM_MODE_FLAG_INTERLACE; 2550 } 2551 2552 /** 2553 * drm_mode_detailed - create a new mode from an EDID detailed timing section 2554 * @dev: DRM device (needed to create new mode) 2555 * @edid: EDID block 2556 * @timing: EDID detailed timing info 2557 * @quirks: quirks to apply 2558 * 2559 * An EDID detailed timing block contains enough info for us to create and 2560 * return a new struct drm_display_mode. 2561 */ 2562 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 2563 struct edid *edid, 2564 struct detailed_timing *timing, 2565 u32 quirks) 2566 { 2567 struct drm_display_mode *mode; 2568 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 2569 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 2570 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 2571 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 2572 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 2573 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 2574 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 2575 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 2576 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 2577 2578 /* ignore tiny modes */ 2579 if (hactive < 64 || vactive < 64) 2580 return NULL; 2581 2582 if (pt->misc & DRM_EDID_PT_STEREO) { 2583 DRM_DEBUG_KMS("stereo mode not supported\n"); 2584 return NULL; 2585 } 2586 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 2587 DRM_DEBUG_KMS("composite sync not supported\n"); 2588 } 2589 2590 /* it is incorrect if hsync/vsync width is zero */ 2591 if (!hsync_pulse_width || !vsync_pulse_width) { 2592 DRM_DEBUG_KMS("Incorrect Detailed timing. " 2593 "Wrong Hsync/Vsync pulse width\n"); 2594 return NULL; 2595 } 2596 2597 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 2598 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 2599 if (!mode) 2600 return NULL; 2601 2602 goto set_size; 2603 } 2604 2605 mode = drm_mode_create(dev); 2606 if (!mode) 2607 return NULL; 2608 2609 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 2610 timing->pixel_clock = cpu_to_le16(1088); 2611 2612 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 2613 2614 mode->hdisplay = hactive; 2615 mode->hsync_start = mode->hdisplay + hsync_offset; 2616 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 2617 mode->htotal = mode->hdisplay + hblank; 2618 2619 mode->vdisplay = vactive; 2620 mode->vsync_start = mode->vdisplay + vsync_offset; 2621 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 2622 mode->vtotal = mode->vdisplay + vblank; 2623 2624 /* Some EDIDs have bogus h/vtotal values */ 2625 if (mode->hsync_end > mode->htotal) 2626 mode->htotal = mode->hsync_end + 1; 2627 if (mode->vsync_end > mode->vtotal) 2628 mode->vtotal = mode->vsync_end + 1; 2629 2630 drm_mode_do_interlace_quirk(mode, pt); 2631 2632 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 2633 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; 2634 } 2635 2636 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 2637 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 2638 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 2639 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 2640 2641 set_size: 2642 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 2643 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 2644 2645 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 2646 mode->width_mm *= 10; 2647 mode->height_mm *= 10; 2648 } 2649 2650 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 2651 mode->width_mm = edid->width_cm * 10; 2652 mode->height_mm = edid->height_cm * 10; 2653 } 2654 2655 mode->type = DRM_MODE_TYPE_DRIVER; 2656 mode->vrefresh = drm_mode_vrefresh(mode); 2657 drm_mode_set_name(mode); 2658 2659 return mode; 2660 } 2661 2662 static bool 2663 mode_in_hsync_range(const struct drm_display_mode *mode, 2664 struct edid *edid, u8 *t) 2665 { 2666 int hsync, hmin, hmax; 2667 2668 hmin = t[7]; 2669 if (edid->revision >= 4) 2670 hmin += ((t[4] & 0x04) ? 255 : 0); 2671 hmax = t[8]; 2672 if (edid->revision >= 4) 2673 hmax += ((t[4] & 0x08) ? 255 : 0); 2674 hsync = drm_mode_hsync(mode); 2675 2676 return (hsync <= hmax && hsync >= hmin); 2677 } 2678 2679 static bool 2680 mode_in_vsync_range(const struct drm_display_mode *mode, 2681 struct edid *edid, u8 *t) 2682 { 2683 int vsync, vmin, vmax; 2684 2685 vmin = t[5]; 2686 if (edid->revision >= 4) 2687 vmin += ((t[4] & 0x01) ? 255 : 0); 2688 vmax = t[6]; 2689 if (edid->revision >= 4) 2690 vmax += ((t[4] & 0x02) ? 255 : 0); 2691 vsync = drm_mode_vrefresh(mode); 2692 2693 return (vsync <= vmax && vsync >= vmin); 2694 } 2695 2696 static u32 2697 range_pixel_clock(struct edid *edid, u8 *t) 2698 { 2699 /* unspecified */ 2700 if (t[9] == 0 || t[9] == 255) 2701 return 0; 2702 2703 /* 1.4 with CVT support gives us real precision, yay */ 2704 if (edid->revision >= 4 && t[10] == 0x04) 2705 return (t[9] * 10000) - ((t[12] >> 2) * 250); 2706 2707 /* 1.3 is pathetic, so fuzz up a bit */ 2708 return t[9] * 10000 + 5001; 2709 } 2710 2711 static bool 2712 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 2713 struct detailed_timing *timing) 2714 { 2715 u32 max_clock; 2716 u8 *t = (u8 *)timing; 2717 2718 if (!mode_in_hsync_range(mode, edid, t)) 2719 return false; 2720 2721 if (!mode_in_vsync_range(mode, edid, t)) 2722 return false; 2723 2724 if ((max_clock = range_pixel_clock(edid, t))) 2725 if (mode->clock > max_clock) 2726 return false; 2727 2728 /* 1.4 max horizontal check */ 2729 if (edid->revision >= 4 && t[10] == 0x04) 2730 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 2731 return false; 2732 2733 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 2734 return false; 2735 2736 return true; 2737 } 2738 2739 static bool valid_inferred_mode(const struct drm_connector *connector, 2740 const struct drm_display_mode *mode) 2741 { 2742 const struct drm_display_mode *m; 2743 bool ok = false; 2744 2745 list_for_each_entry(m, &connector->probed_modes, head) { 2746 if (mode->hdisplay == m->hdisplay && 2747 mode->vdisplay == m->vdisplay && 2748 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 2749 return false; /* duplicated */ 2750 if (mode->hdisplay <= m->hdisplay && 2751 mode->vdisplay <= m->vdisplay) 2752 ok = true; 2753 } 2754 return ok; 2755 } 2756 2757 static int 2758 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2759 struct detailed_timing *timing) 2760 { 2761 int i, modes = 0; 2762 struct drm_display_mode *newmode; 2763 struct drm_device *dev = connector->dev; 2764 2765 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2766 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 2767 valid_inferred_mode(connector, drm_dmt_modes + i)) { 2768 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 2769 if (newmode) { 2770 drm_mode_probed_add(connector, newmode); 2771 modes++; 2772 } 2773 } 2774 } 2775 2776 return modes; 2777 } 2778 2779 /* fix up 1366x768 mode from 1368x768; 2780 * GFT/CVT can't express 1366 width which isn't dividable by 8 2781 */ 2782 void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 2783 { 2784 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 2785 mode->hdisplay = 1366; 2786 mode->hsync_start--; 2787 mode->hsync_end--; 2788 drm_mode_set_name(mode); 2789 } 2790 } 2791 2792 static int 2793 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, 2794 struct detailed_timing *timing) 2795 { 2796 int i, modes = 0; 2797 struct drm_display_mode *newmode; 2798 struct drm_device *dev = connector->dev; 2799 2800 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2801 const struct minimode *m = &extra_modes[i]; 2802 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 2803 if (!newmode) 2804 return modes; 2805 2806 drm_mode_fixup_1366x768(newmode); 2807 if (!mode_in_range(newmode, edid, timing) || 2808 !valid_inferred_mode(connector, newmode)) { 2809 drm_mode_destroy(dev, newmode); 2810 continue; 2811 } 2812 2813 drm_mode_probed_add(connector, newmode); 2814 modes++; 2815 } 2816 2817 return modes; 2818 } 2819 2820 static int 2821 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2822 struct detailed_timing *timing) 2823 { 2824 int i, modes = 0; 2825 struct drm_display_mode *newmode; 2826 struct drm_device *dev = connector->dev; 2827 bool rb = drm_monitor_supports_rb(edid); 2828 2829 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2830 const struct minimode *m = &extra_modes[i]; 2831 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 2832 if (!newmode) 2833 return modes; 2834 2835 drm_mode_fixup_1366x768(newmode); 2836 if (!mode_in_range(newmode, edid, timing) || 2837 !valid_inferred_mode(connector, newmode)) { 2838 drm_mode_destroy(dev, newmode); 2839 continue; 2840 } 2841 2842 drm_mode_probed_add(connector, newmode); 2843 modes++; 2844 } 2845 2846 return modes; 2847 } 2848 2849 static void 2850 do_inferred_modes(struct detailed_timing *timing, void *c) 2851 { 2852 struct detailed_mode_closure *closure = c; 2853 struct detailed_non_pixel *data = &timing->data.other_data; 2854 struct detailed_data_monitor_range *range = &data->data.range; 2855 2856 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE)) 2857 return; 2858 2859 closure->modes += drm_dmt_modes_for_range(closure->connector, 2860 closure->edid, 2861 timing); 2862 2863 if (!version_greater(closure->edid, 1, 1)) 2864 return; /* GTF not defined yet */ 2865 2866 switch (range->flags) { 2867 case 0x02: /* secondary gtf, XXX could do more */ 2868 case 0x00: /* default gtf */ 2869 closure->modes += drm_gtf_modes_for_range(closure->connector, 2870 closure->edid, 2871 timing); 2872 break; 2873 case 0x04: /* cvt, only in 1.4+ */ 2874 if (!version_greater(closure->edid, 1, 3)) 2875 break; 2876 2877 closure->modes += drm_cvt_modes_for_range(closure->connector, 2878 closure->edid, 2879 timing); 2880 break; 2881 case 0x01: /* just the ranges, no formula */ 2882 default: 2883 break; 2884 } 2885 } 2886 2887 static int 2888 add_inferred_modes(struct drm_connector *connector, struct edid *edid) 2889 { 2890 struct detailed_mode_closure closure = { 2891 .connector = connector, 2892 .edid = edid, 2893 }; 2894 2895 if (version_greater(edid, 1, 0)) 2896 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 2897 &closure); 2898 2899 return closure.modes; 2900 } 2901 2902 static int 2903 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 2904 { 2905 int i, j, m, modes = 0; 2906 struct drm_display_mode *mode; 2907 u8 *est = ((u8 *)timing) + 6; 2908 2909 for (i = 0; i < 6; i++) { 2910 for (j = 7; j >= 0; j--) { 2911 m = (i * 8) + (7 - j); 2912 if (m >= ARRAY_SIZE(est3_modes)) 2913 break; 2914 if (est[i] & (1 << j)) { 2915 mode = drm_mode_find_dmt(connector->dev, 2916 est3_modes[m].w, 2917 est3_modes[m].h, 2918 est3_modes[m].r, 2919 est3_modes[m].rb); 2920 if (mode) { 2921 drm_mode_probed_add(connector, mode); 2922 modes++; 2923 } 2924 } 2925 } 2926 } 2927 2928 return modes; 2929 } 2930 2931 static void 2932 do_established_modes(struct detailed_timing *timing, void *c) 2933 { 2934 struct detailed_mode_closure *closure = c; 2935 2936 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_EST_TIMINGS)) 2937 return; 2938 2939 closure->modes += drm_est3_modes(closure->connector, timing); 2940 } 2941 2942 /** 2943 * add_established_modes - get est. modes from EDID and add them 2944 * @connector: connector to add mode(s) to 2945 * @edid: EDID block to scan 2946 * 2947 * Each EDID block contains a bitmap of the supported "established modes" list 2948 * (defined above). Tease them out and add them to the global modes list. 2949 */ 2950 static int 2951 add_established_modes(struct drm_connector *connector, struct edid *edid) 2952 { 2953 struct drm_device *dev = connector->dev; 2954 unsigned long est_bits = edid->established_timings.t1 | 2955 (edid->established_timings.t2 << 8) | 2956 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 2957 int i, modes = 0; 2958 struct detailed_mode_closure closure = { 2959 .connector = connector, 2960 .edid = edid, 2961 }; 2962 2963 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 2964 if (est_bits & (1<<i)) { 2965 struct drm_display_mode *newmode; 2966 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 2967 if (newmode) { 2968 drm_mode_probed_add(connector, newmode); 2969 modes++; 2970 } 2971 } 2972 } 2973 2974 if (version_greater(edid, 1, 0)) 2975 drm_for_each_detailed_block((u8 *)edid, 2976 do_established_modes, &closure); 2977 2978 return modes + closure.modes; 2979 } 2980 2981 static void 2982 do_standard_modes(struct detailed_timing *timing, void *c) 2983 { 2984 struct detailed_mode_closure *closure = c; 2985 struct detailed_non_pixel *data = &timing->data.other_data; 2986 struct drm_connector *connector = closure->connector; 2987 struct edid *edid = closure->edid; 2988 int i; 2989 2990 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_STD_MODES)) 2991 return; 2992 2993 for (i = 0; i < 6; i++) { 2994 struct std_timing *std = &data->data.timings[i]; 2995 struct drm_display_mode *newmode; 2996 2997 newmode = drm_mode_std(connector, edid, std); 2998 if (newmode) { 2999 drm_mode_probed_add(connector, newmode); 3000 closure->modes++; 3001 } 3002 } 3003 } 3004 3005 /** 3006 * add_standard_modes - get std. modes from EDID and add them 3007 * @connector: connector to add mode(s) to 3008 * @edid: EDID block to scan 3009 * 3010 * Standard modes can be calculated using the appropriate standard (DMT, 3011 * GTF or CVT. Grab them from @edid and add them to the list. 3012 */ 3013 static int 3014 add_standard_modes(struct drm_connector *connector, struct edid *edid) 3015 { 3016 int i, modes = 0; 3017 struct detailed_mode_closure closure = { 3018 .connector = connector, 3019 .edid = edid, 3020 }; 3021 3022 for (i = 0; i < EDID_STD_TIMINGS; i++) { 3023 struct drm_display_mode *newmode; 3024 3025 newmode = drm_mode_std(connector, edid, 3026 &edid->standard_timings[i]); 3027 if (newmode) { 3028 drm_mode_probed_add(connector, newmode); 3029 modes++; 3030 } 3031 } 3032 3033 if (version_greater(edid, 1, 0)) 3034 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 3035 &closure); 3036 3037 /* XXX should also look for standard codes in VTB blocks */ 3038 3039 return modes + closure.modes; 3040 } 3041 3042 static int drm_cvt_modes(struct drm_connector *connector, 3043 struct detailed_timing *timing) 3044 { 3045 int i, j, modes = 0; 3046 struct drm_display_mode *newmode; 3047 struct drm_device *dev = connector->dev; 3048 struct cvt_timing *cvt; 3049 const int rates[] = { 60, 85, 75, 60, 50 }; 3050 const u8 empty[3] = { 0, 0, 0 }; 3051 3052 for (i = 0; i < 4; i++) { 3053 int uninitialized_var(width), height; 3054 cvt = &(timing->data.other_data.data.cvt[i]); 3055 3056 if (!memcmp(cvt->code, empty, 3)) 3057 continue; 3058 3059 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 3060 switch (cvt->code[1] & 0x0c) { 3061 case 0x00: 3062 width = height * 4 / 3; 3063 break; 3064 case 0x04: 3065 width = height * 16 / 9; 3066 break; 3067 case 0x08: 3068 width = height * 16 / 10; 3069 break; 3070 case 0x0c: 3071 width = height * 15 / 9; 3072 break; 3073 } 3074 3075 for (j = 1; j < 5; j++) { 3076 if (cvt->code[2] & (1 << j)) { 3077 newmode = drm_cvt_mode(dev, width, height, 3078 rates[j], j == 0, 3079 false, false); 3080 if (newmode) { 3081 drm_mode_probed_add(connector, newmode); 3082 modes++; 3083 } 3084 } 3085 } 3086 } 3087 3088 return modes; 3089 } 3090 3091 static void 3092 do_cvt_mode(struct detailed_timing *timing, void *c) 3093 { 3094 struct detailed_mode_closure *closure = c; 3095 3096 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_CVT_3BYTE)) 3097 return; 3098 3099 closure->modes += drm_cvt_modes(closure->connector, timing); 3100 } 3101 3102 static int 3103 add_cvt_modes(struct drm_connector *connector, struct edid *edid) 3104 { 3105 struct detailed_mode_closure closure = { 3106 .connector = connector, 3107 .edid = edid, 3108 }; 3109 3110 if (version_greater(edid, 1, 2)) 3111 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 3112 3113 /* XXX should also look for CVT codes in VTB blocks */ 3114 3115 return closure.modes; 3116 } 3117 3118 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); 3119 3120 static void 3121 do_detailed_mode(struct detailed_timing *timing, void *c) 3122 { 3123 struct detailed_mode_closure *closure = c; 3124 struct drm_display_mode *newmode; 3125 3126 if (!is_detailed_timing_descriptor((const u8 *)timing)) 3127 return; 3128 3129 newmode = drm_mode_detailed(closure->connector->dev, 3130 closure->edid, timing, 3131 closure->quirks); 3132 if (!newmode) 3133 return; 3134 3135 if (closure->preferred) 3136 newmode->type |= DRM_MODE_TYPE_PREFERRED; 3137 3138 /* 3139 * Detailed modes are limited to 10kHz pixel clock resolution, 3140 * so fix up anything that looks like CEA/HDMI mode, but the clock 3141 * is just slightly off. 3142 */ 3143 fixup_detailed_cea_mode_clock(newmode); 3144 3145 drm_mode_probed_add(closure->connector, newmode); 3146 closure->modes++; 3147 closure->preferred = false; 3148 } 3149 3150 /* 3151 * add_detailed_modes - Add modes from detailed timings 3152 * @connector: attached connector 3153 * @edid: EDID block to scan 3154 * @quirks: quirks to apply 3155 */ 3156 static int 3157 add_detailed_modes(struct drm_connector *connector, struct edid *edid, 3158 u32 quirks) 3159 { 3160 struct detailed_mode_closure closure = { 3161 .connector = connector, 3162 .edid = edid, 3163 .preferred = true, 3164 .quirks = quirks, 3165 }; 3166 3167 if (closure.preferred && !version_greater(edid, 1, 3)) 3168 closure.preferred = 3169 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 3170 3171 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 3172 3173 return closure.modes; 3174 } 3175 3176 #define AUDIO_BLOCK 0x01 3177 #define VIDEO_BLOCK 0x02 3178 #define VENDOR_BLOCK 0x03 3179 #define SPEAKER_BLOCK 0x04 3180 #define HDR_STATIC_METADATA_BLOCK 0x6 3181 #define USE_EXTENDED_TAG 0x07 3182 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00 3183 #define EXT_VIDEO_DATA_BLOCK_420 0x0E 3184 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F 3185 #define EDID_BASIC_AUDIO (1 << 6) 3186 #define EDID_CEA_YCRCB444 (1 << 5) 3187 #define EDID_CEA_YCRCB422 (1 << 4) 3188 #define EDID_CEA_VCDB_QS (1 << 6) 3189 3190 /* 3191 * Search EDID for CEA extension block. 3192 */ 3193 static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id) 3194 { 3195 u8 *edid_ext = NULL; 3196 int i; 3197 3198 /* No EDID or EDID extensions */ 3199 if (edid == NULL || edid->extensions == 0) 3200 return NULL; 3201 3202 /* Find CEA extension */ 3203 for (i = 0; i < edid->extensions; i++) { 3204 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); 3205 if (edid_ext[0] == ext_id) 3206 break; 3207 } 3208 3209 if (i == edid->extensions) 3210 return NULL; 3211 3212 return edid_ext; 3213 } 3214 3215 3216 static u8 *drm_find_displayid_extension(const struct edid *edid, 3217 int *length, int *idx) 3218 { 3219 u8 *displayid = drm_find_edid_extension(edid, DISPLAYID_EXT); 3220 struct displayid_hdr *base; 3221 int ret; 3222 3223 if (!displayid) 3224 return NULL; 3225 3226 /* EDID extensions block checksum isn't for us */ 3227 *length = EDID_LENGTH - 1; 3228 *idx = 1; 3229 3230 ret = validate_displayid(displayid, *length, *idx); 3231 if (ret) 3232 return NULL; 3233 3234 base = (struct displayid_hdr *)&displayid[*idx]; 3235 *length = *idx + sizeof(*base) + base->bytes; 3236 3237 return displayid; 3238 } 3239 3240 static u8 *drm_find_cea_extension(const struct edid *edid) 3241 { 3242 int length, idx; 3243 struct displayid_block *block; 3244 u8 *cea; 3245 u8 *displayid; 3246 3247 /* Look for a top level CEA extension block */ 3248 cea = drm_find_edid_extension(edid, CEA_EXT); 3249 if (cea) 3250 return cea; 3251 3252 /* CEA blocks can also be found embedded in a DisplayID block */ 3253 displayid = drm_find_displayid_extension(edid, &length, &idx); 3254 if (!displayid) 3255 return NULL; 3256 3257 idx += sizeof(struct displayid_hdr); 3258 for_each_displayid_db(displayid, block, idx, length) { 3259 if (block->tag == DATA_BLOCK_CTA) { 3260 cea = (u8 *)block; 3261 break; 3262 } 3263 } 3264 3265 return cea; 3266 } 3267 3268 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic) 3269 { 3270 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127); 3271 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219); 3272 3273 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1)) 3274 return &edid_cea_modes_1[vic - 1]; 3275 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193)) 3276 return &edid_cea_modes_193[vic - 193]; 3277 return NULL; 3278 } 3279 3280 static u8 cea_num_vics(void) 3281 { 3282 return 193 + ARRAY_SIZE(edid_cea_modes_193); 3283 } 3284 3285 static u8 cea_next_vic(u8 vic) 3286 { 3287 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1)) 3288 vic = 193; 3289 return vic; 3290 } 3291 3292 /* 3293 * Calculate the alternate clock for the CEA mode 3294 * (60Hz vs. 59.94Hz etc.) 3295 */ 3296 static unsigned int 3297 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 3298 { 3299 unsigned int clock = cea_mode->clock; 3300 3301 if (cea_mode->vrefresh % 6 != 0) 3302 return clock; 3303 3304 /* 3305 * edid_cea_modes contains the 59.94Hz 3306 * variant for 240 and 480 line modes, 3307 * and the 60Hz variant otherwise. 3308 */ 3309 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 3310 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 3311 else 3312 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 3313 3314 return clock; 3315 } 3316 3317 static bool 3318 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 3319 { 3320 /* 3321 * For certain VICs the spec allows the vertical 3322 * front porch to vary by one or two lines. 3323 * 3324 * cea_modes[] stores the variant with the shortest 3325 * vertical front porch. We can adjust the mode to 3326 * get the other variants by simply increasing the 3327 * vertical front porch length. 3328 */ 3329 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 || 3330 cea_mode_for_vic(9)->vtotal != 262 || 3331 cea_mode_for_vic(12)->vtotal != 262 || 3332 cea_mode_for_vic(13)->vtotal != 262 || 3333 cea_mode_for_vic(23)->vtotal != 312 || 3334 cea_mode_for_vic(24)->vtotal != 312 || 3335 cea_mode_for_vic(27)->vtotal != 312 || 3336 cea_mode_for_vic(28)->vtotal != 312); 3337 3338 if (((vic == 8 || vic == 9 || 3339 vic == 12 || vic == 13) && mode->vtotal < 263) || 3340 ((vic == 23 || vic == 24 || 3341 vic == 27 || vic == 28) && mode->vtotal < 314)) { 3342 mode->vsync_start++; 3343 mode->vsync_end++; 3344 mode->vtotal++; 3345 3346 return true; 3347 } 3348 3349 return false; 3350 } 3351 3352 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 3353 unsigned int clock_tolerance) 3354 { 3355 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3356 u8 vic; 3357 3358 if (!to_match->clock) 3359 return 0; 3360 3361 if (to_match->picture_aspect_ratio) 3362 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3363 3364 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 3365 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic); 3366 unsigned int clock1, clock2; 3367 3368 /* Check both 60Hz and 59.94Hz */ 3369 clock1 = cea_mode.clock; 3370 clock2 = cea_mode_alternate_clock(&cea_mode); 3371 3372 if (abs(to_match->clock - clock1) > clock_tolerance && 3373 abs(to_match->clock - clock2) > clock_tolerance) 3374 continue; 3375 3376 do { 3377 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3378 return vic; 3379 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3380 } 3381 3382 return 0; 3383 } 3384 3385 /** 3386 * drm_match_cea_mode - look for a CEA mode matching given mode 3387 * @to_match: display mode 3388 * 3389 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 3390 * mode. 3391 */ 3392 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 3393 { 3394 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3395 u8 vic; 3396 3397 if (!to_match->clock) 3398 return 0; 3399 3400 if (to_match->picture_aspect_ratio) 3401 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3402 3403 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 3404 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic); 3405 unsigned int clock1, clock2; 3406 3407 /* Check both 60Hz and 59.94Hz */ 3408 clock1 = cea_mode.clock; 3409 clock2 = cea_mode_alternate_clock(&cea_mode); 3410 3411 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 3412 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 3413 continue; 3414 3415 do { 3416 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3417 return vic; 3418 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3419 } 3420 3421 return 0; 3422 } 3423 EXPORT_SYMBOL(drm_match_cea_mode); 3424 3425 static bool drm_valid_cea_vic(u8 vic) 3426 { 3427 return cea_mode_for_vic(vic) != NULL; 3428 } 3429 3430 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 3431 { 3432 const struct drm_display_mode *mode = cea_mode_for_vic(video_code); 3433 3434 if (mode) 3435 return mode->picture_aspect_ratio; 3436 3437 return HDMI_PICTURE_ASPECT_NONE; 3438 } 3439 3440 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code) 3441 { 3442 return edid_4k_modes[video_code].picture_aspect_ratio; 3443 } 3444 3445 /* 3446 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 3447 * specific block). 3448 */ 3449 static unsigned int 3450 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 3451 { 3452 return cea_mode_alternate_clock(hdmi_mode); 3453 } 3454 3455 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 3456 unsigned int clock_tolerance) 3457 { 3458 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3459 u8 vic; 3460 3461 if (!to_match->clock) 3462 return 0; 3463 3464 if (to_match->picture_aspect_ratio) 3465 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3466 3467 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3468 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3469 unsigned int clock1, clock2; 3470 3471 /* Make sure to also match alternate clocks */ 3472 clock1 = hdmi_mode->clock; 3473 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3474 3475 if (abs(to_match->clock - clock1) > clock_tolerance && 3476 abs(to_match->clock - clock2) > clock_tolerance) 3477 continue; 3478 3479 if (drm_mode_match(to_match, hdmi_mode, match_flags)) 3480 return vic; 3481 } 3482 3483 return 0; 3484 } 3485 3486 /* 3487 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 3488 * @to_match: display mode 3489 * 3490 * An HDMI mode is one defined in the HDMI vendor specific block. 3491 * 3492 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 3493 */ 3494 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 3495 { 3496 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3497 u8 vic; 3498 3499 if (!to_match->clock) 3500 return 0; 3501 3502 if (to_match->picture_aspect_ratio) 3503 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3504 3505 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3506 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3507 unsigned int clock1, clock2; 3508 3509 /* Make sure to also match alternate clocks */ 3510 clock1 = hdmi_mode->clock; 3511 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3512 3513 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 3514 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 3515 drm_mode_match(to_match, hdmi_mode, match_flags)) 3516 return vic; 3517 } 3518 return 0; 3519 } 3520 3521 static bool drm_valid_hdmi_vic(u8 vic) 3522 { 3523 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 3524 } 3525 3526 static int 3527 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) 3528 { 3529 struct drm_device *dev = connector->dev; 3530 struct drm_display_mode *mode, *tmp; 3531 LIST_HEAD(list); 3532 int modes = 0; 3533 3534 /* Don't add CEA modes if the CEA extension block is missing */ 3535 if (!drm_find_cea_extension(edid)) 3536 return 0; 3537 3538 /* 3539 * Go through all probed modes and create a new mode 3540 * with the alternate clock for certain CEA modes. 3541 */ 3542 list_for_each_entry(mode, &connector->probed_modes, head) { 3543 const struct drm_display_mode *cea_mode = NULL; 3544 struct drm_display_mode *newmode; 3545 u8 vic = drm_match_cea_mode(mode); 3546 unsigned int clock1, clock2; 3547 3548 if (drm_valid_cea_vic(vic)) { 3549 cea_mode = cea_mode_for_vic(vic); 3550 clock2 = cea_mode_alternate_clock(cea_mode); 3551 } else { 3552 vic = drm_match_hdmi_mode(mode); 3553 if (drm_valid_hdmi_vic(vic)) { 3554 cea_mode = &edid_4k_modes[vic]; 3555 clock2 = hdmi_mode_alternate_clock(cea_mode); 3556 } 3557 } 3558 3559 if (!cea_mode) 3560 continue; 3561 3562 clock1 = cea_mode->clock; 3563 3564 if (clock1 == clock2) 3565 continue; 3566 3567 if (mode->clock != clock1 && mode->clock != clock2) 3568 continue; 3569 3570 newmode = drm_mode_duplicate(dev, cea_mode); 3571 if (!newmode) 3572 continue; 3573 3574 /* Carry over the stereo flags */ 3575 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 3576 3577 /* 3578 * The current mode could be either variant. Make 3579 * sure to pick the "other" clock for the new mode. 3580 */ 3581 if (mode->clock != clock1) 3582 newmode->clock = clock1; 3583 else 3584 newmode->clock = clock2; 3585 3586 list_add_tail(&newmode->head, &list); 3587 } 3588 3589 list_for_each_entry_safe(mode, tmp, &list, head) { 3590 list_del(&mode->head); 3591 drm_mode_probed_add(connector, mode); 3592 modes++; 3593 } 3594 3595 return modes; 3596 } 3597 3598 static u8 svd_to_vic(u8 svd) 3599 { 3600 /* 0-6 bit vic, 7th bit native mode indicator */ 3601 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 3602 return svd & 127; 3603 3604 return svd; 3605 } 3606 3607 static struct drm_display_mode * 3608 drm_display_mode_from_vic_index(struct drm_connector *connector, 3609 const u8 *video_db, u8 video_len, 3610 u8 video_index) 3611 { 3612 struct drm_device *dev = connector->dev; 3613 struct drm_display_mode *newmode; 3614 u8 vic; 3615 3616 if (video_db == NULL || video_index >= video_len) 3617 return NULL; 3618 3619 /* CEA modes are numbered 1..127 */ 3620 vic = svd_to_vic(video_db[video_index]); 3621 if (!drm_valid_cea_vic(vic)) 3622 return NULL; 3623 3624 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 3625 if (!newmode) 3626 return NULL; 3627 3628 newmode->vrefresh = 0; 3629 3630 return newmode; 3631 } 3632 3633 /* 3634 * do_y420vdb_modes - Parse YCBCR 420 only modes 3635 * @connector: connector corresponding to the HDMI sink 3636 * @svds: start of the data block of CEA YCBCR 420 VDB 3637 * @len: length of the CEA YCBCR 420 VDB 3638 * 3639 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 3640 * which contains modes which can be supported in YCBCR 420 3641 * output format only. 3642 */ 3643 static int do_y420vdb_modes(struct drm_connector *connector, 3644 const u8 *svds, u8 svds_len) 3645 { 3646 int modes = 0, i; 3647 struct drm_device *dev = connector->dev; 3648 struct drm_display_info *info = &connector->display_info; 3649 struct drm_hdmi_info *hdmi = &info->hdmi; 3650 3651 for (i = 0; i < svds_len; i++) { 3652 u8 vic = svd_to_vic(svds[i]); 3653 struct drm_display_mode *newmode; 3654 3655 if (!drm_valid_cea_vic(vic)) 3656 continue; 3657 3658 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 3659 if (!newmode) 3660 break; 3661 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 3662 drm_mode_probed_add(connector, newmode); 3663 modes++; 3664 } 3665 3666 if (modes > 0) 3667 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3668 return modes; 3669 } 3670 3671 /* 3672 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap 3673 * @connector: connector corresponding to the HDMI sink 3674 * @vic: CEA vic for the video mode to be added in the map 3675 * 3676 * Makes an entry for a videomode in the YCBCR 420 bitmap 3677 */ 3678 static void 3679 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd) 3680 { 3681 u8 vic = svd_to_vic(svd); 3682 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3683 3684 if (!drm_valid_cea_vic(vic)) 3685 return; 3686 3687 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 3688 } 3689 3690 static int 3691 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 3692 { 3693 int i, modes = 0; 3694 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3695 3696 for (i = 0; i < len; i++) { 3697 struct drm_display_mode *mode; 3698 mode = drm_display_mode_from_vic_index(connector, db, len, i); 3699 if (mode) { 3700 /* 3701 * YCBCR420 capability block contains a bitmap which 3702 * gives the index of CEA modes from CEA VDB, which 3703 * can support YCBCR 420 sampling output also (apart 3704 * from RGB/YCBCR444 etc). 3705 * For example, if the bit 0 in bitmap is set, 3706 * first mode in VDB can support YCBCR420 output too. 3707 * Add YCBCR420 modes only if sink is HDMI 2.0 capable. 3708 */ 3709 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) 3710 drm_add_cmdb_modes(connector, db[i]); 3711 3712 drm_mode_probed_add(connector, mode); 3713 modes++; 3714 } 3715 } 3716 3717 return modes; 3718 } 3719 3720 struct stereo_mandatory_mode { 3721 int width, height, vrefresh; 3722 unsigned int flags; 3723 }; 3724 3725 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 3726 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3727 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3728 { 1920, 1080, 50, 3729 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3730 { 1920, 1080, 60, 3731 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3732 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3733 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3734 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3735 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 3736 }; 3737 3738 static bool 3739 stereo_match_mandatory(const struct drm_display_mode *mode, 3740 const struct stereo_mandatory_mode *stereo_mode) 3741 { 3742 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 3743 3744 return mode->hdisplay == stereo_mode->width && 3745 mode->vdisplay == stereo_mode->height && 3746 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 3747 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 3748 } 3749 3750 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 3751 { 3752 struct drm_device *dev = connector->dev; 3753 const struct drm_display_mode *mode; 3754 struct list_head stereo_modes; 3755 int modes = 0, i; 3756 3757 INIT_LIST_HEAD(&stereo_modes); 3758 3759 list_for_each_entry(mode, &connector->probed_modes, head) { 3760 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 3761 const struct stereo_mandatory_mode *mandatory; 3762 struct drm_display_mode *new_mode; 3763 3764 if (!stereo_match_mandatory(mode, 3765 &stereo_mandatory_modes[i])) 3766 continue; 3767 3768 mandatory = &stereo_mandatory_modes[i]; 3769 new_mode = drm_mode_duplicate(dev, mode); 3770 if (!new_mode) 3771 continue; 3772 3773 new_mode->flags |= mandatory->flags; 3774 list_add_tail(&new_mode->head, &stereo_modes); 3775 modes++; 3776 } 3777 } 3778 3779 list_splice_tail(&stereo_modes, &connector->probed_modes); 3780 3781 return modes; 3782 } 3783 3784 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 3785 { 3786 struct drm_device *dev = connector->dev; 3787 struct drm_display_mode *newmode; 3788 3789 if (!drm_valid_hdmi_vic(vic)) { 3790 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 3791 return 0; 3792 } 3793 3794 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 3795 if (!newmode) 3796 return 0; 3797 3798 drm_mode_probed_add(connector, newmode); 3799 3800 return 1; 3801 } 3802 3803 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 3804 const u8 *video_db, u8 video_len, u8 video_index) 3805 { 3806 struct drm_display_mode *newmode; 3807 int modes = 0; 3808 3809 if (structure & (1 << 0)) { 3810 newmode = drm_display_mode_from_vic_index(connector, video_db, 3811 video_len, 3812 video_index); 3813 if (newmode) { 3814 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 3815 drm_mode_probed_add(connector, newmode); 3816 modes++; 3817 } 3818 } 3819 if (structure & (1 << 6)) { 3820 newmode = drm_display_mode_from_vic_index(connector, video_db, 3821 video_len, 3822 video_index); 3823 if (newmode) { 3824 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3825 drm_mode_probed_add(connector, newmode); 3826 modes++; 3827 } 3828 } 3829 if (structure & (1 << 8)) { 3830 newmode = drm_display_mode_from_vic_index(connector, video_db, 3831 video_len, 3832 video_index); 3833 if (newmode) { 3834 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3835 drm_mode_probed_add(connector, newmode); 3836 modes++; 3837 } 3838 } 3839 3840 return modes; 3841 } 3842 3843 /* 3844 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 3845 * @connector: connector corresponding to the HDMI sink 3846 * @db: start of the CEA vendor specific block 3847 * @len: length of the CEA block payload, ie. one can access up to db[len] 3848 * 3849 * Parses the HDMI VSDB looking for modes to add to @connector. This function 3850 * also adds the stereo 3d modes when applicable. 3851 */ 3852 static int 3853 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 3854 const u8 *video_db, u8 video_len) 3855 { 3856 struct drm_display_info *info = &connector->display_info; 3857 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 3858 u8 vic_len, hdmi_3d_len = 0; 3859 u16 mask; 3860 u16 structure_all; 3861 3862 if (len < 8) 3863 goto out; 3864 3865 /* no HDMI_Video_Present */ 3866 if (!(db[8] & (1 << 5))) 3867 goto out; 3868 3869 /* Latency_Fields_Present */ 3870 if (db[8] & (1 << 7)) 3871 offset += 2; 3872 3873 /* I_Latency_Fields_Present */ 3874 if (db[8] & (1 << 6)) 3875 offset += 2; 3876 3877 /* the declared length is not long enough for the 2 first bytes 3878 * of additional video format capabilities */ 3879 if (len < (8 + offset + 2)) 3880 goto out; 3881 3882 /* 3D_Present */ 3883 offset++; 3884 if (db[8 + offset] & (1 << 7)) { 3885 modes += add_hdmi_mandatory_stereo_modes(connector); 3886 3887 /* 3D_Multi_present */ 3888 multi_present = (db[8 + offset] & 0x60) >> 5; 3889 } 3890 3891 offset++; 3892 vic_len = db[8 + offset] >> 5; 3893 hdmi_3d_len = db[8 + offset] & 0x1f; 3894 3895 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 3896 u8 vic; 3897 3898 vic = db[9 + offset + i]; 3899 modes += add_hdmi_mode(connector, vic); 3900 } 3901 offset += 1 + vic_len; 3902 3903 if (multi_present == 1) 3904 multi_len = 2; 3905 else if (multi_present == 2) 3906 multi_len = 4; 3907 else 3908 multi_len = 0; 3909 3910 if (len < (8 + offset + hdmi_3d_len - 1)) 3911 goto out; 3912 3913 if (hdmi_3d_len < multi_len) 3914 goto out; 3915 3916 if (multi_present == 1 || multi_present == 2) { 3917 /* 3D_Structure_ALL */ 3918 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 3919 3920 /* check if 3D_MASK is present */ 3921 if (multi_present == 2) 3922 mask = (db[10 + offset] << 8) | db[11 + offset]; 3923 else 3924 mask = 0xffff; 3925 3926 for (i = 0; i < 16; i++) { 3927 if (mask & (1 << i)) 3928 modes += add_3d_struct_modes(connector, 3929 structure_all, 3930 video_db, 3931 video_len, i); 3932 } 3933 } 3934 3935 offset += multi_len; 3936 3937 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 3938 int vic_index; 3939 struct drm_display_mode *newmode = NULL; 3940 unsigned int newflag = 0; 3941 bool detail_present; 3942 3943 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 3944 3945 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 3946 break; 3947 3948 /* 2D_VIC_order_X */ 3949 vic_index = db[8 + offset + i] >> 4; 3950 3951 /* 3D_Structure_X */ 3952 switch (db[8 + offset + i] & 0x0f) { 3953 case 0: 3954 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 3955 break; 3956 case 6: 3957 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3958 break; 3959 case 8: 3960 /* 3D_Detail_X */ 3961 if ((db[9 + offset + i] >> 4) == 1) 3962 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3963 break; 3964 } 3965 3966 if (newflag != 0) { 3967 newmode = drm_display_mode_from_vic_index(connector, 3968 video_db, 3969 video_len, 3970 vic_index); 3971 3972 if (newmode) { 3973 newmode->flags |= newflag; 3974 drm_mode_probed_add(connector, newmode); 3975 modes++; 3976 } 3977 } 3978 3979 if (detail_present) 3980 i++; 3981 } 3982 3983 out: 3984 if (modes > 0) 3985 info->has_hdmi_infoframe = true; 3986 return modes; 3987 } 3988 3989 static int 3990 cea_db_payload_len(const u8 *db) 3991 { 3992 return db[0] & 0x1f; 3993 } 3994 3995 static int 3996 cea_db_extended_tag(const u8 *db) 3997 { 3998 return db[1]; 3999 } 4000 4001 static int 4002 cea_db_tag(const u8 *db) 4003 { 4004 return db[0] >> 5; 4005 } 4006 4007 static int 4008 cea_revision(const u8 *cea) 4009 { 4010 /* 4011 * FIXME is this correct for the DispID variant? 4012 * The DispID spec doesn't really specify whether 4013 * this is the revision of the CEA extension or 4014 * the DispID CEA data block. And the only value 4015 * given as an example is 0. 4016 */ 4017 return cea[1]; 4018 } 4019 4020 static int 4021 cea_db_offsets(const u8 *cea, int *start, int *end) 4022 { 4023 /* DisplayID CTA extension blocks and top-level CEA EDID 4024 * block header definitions differ in the following bytes: 4025 * 1) Byte 2 of the header specifies length differently, 4026 * 2) Byte 3 is only present in the CEA top level block. 4027 * 4028 * The different definitions for byte 2 follow. 4029 * 4030 * DisplayID CTA extension block defines byte 2 as: 4031 * Number of payload bytes 4032 * 4033 * CEA EDID block defines byte 2 as: 4034 * Byte number (decimal) within this block where the 18-byte 4035 * DTDs begin. If no non-DTD data is present in this extension 4036 * block, the value should be set to 04h (the byte after next). 4037 * If set to 00h, there are no DTDs present in this block and 4038 * no non-DTD data. 4039 */ 4040 if (cea[0] == DATA_BLOCK_CTA) { 4041 /* 4042 * for_each_displayid_db() has already verified 4043 * that these stay within expected bounds. 4044 */ 4045 *start = 3; 4046 *end = *start + cea[2]; 4047 } else if (cea[0] == CEA_EXT) { 4048 /* Data block offset in CEA extension block */ 4049 *start = 4; 4050 *end = cea[2]; 4051 if (*end == 0) 4052 *end = 127; 4053 if (*end < 4 || *end > 127) 4054 return -ERANGE; 4055 } else { 4056 return -EOPNOTSUPP; 4057 } 4058 4059 return 0; 4060 } 4061 4062 static bool cea_db_is_hdmi_vsdb(const u8 *db) 4063 { 4064 int hdmi_id; 4065 4066 if (cea_db_tag(db) != VENDOR_BLOCK) 4067 return false; 4068 4069 if (cea_db_payload_len(db) < 5) 4070 return false; 4071 4072 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 4073 4074 return hdmi_id == HDMI_IEEE_OUI; 4075 } 4076 4077 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db) 4078 { 4079 unsigned int oui; 4080 4081 if (cea_db_tag(db) != VENDOR_BLOCK) 4082 return false; 4083 4084 if (cea_db_payload_len(db) < 7) 4085 return false; 4086 4087 oui = db[3] << 16 | db[2] << 8 | db[1]; 4088 4089 return oui == HDMI_FORUM_IEEE_OUI; 4090 } 4091 4092 static bool cea_db_is_vcdb(const u8 *db) 4093 { 4094 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4095 return false; 4096 4097 if (cea_db_payload_len(db) != 2) 4098 return false; 4099 4100 if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK) 4101 return false; 4102 4103 return true; 4104 } 4105 4106 static bool cea_db_is_y420cmdb(const u8 *db) 4107 { 4108 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4109 return false; 4110 4111 if (!cea_db_payload_len(db)) 4112 return false; 4113 4114 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB) 4115 return false; 4116 4117 return true; 4118 } 4119 4120 static bool cea_db_is_y420vdb(const u8 *db) 4121 { 4122 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4123 return false; 4124 4125 if (!cea_db_payload_len(db)) 4126 return false; 4127 4128 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420) 4129 return false; 4130 4131 return true; 4132 } 4133 4134 #define for_each_cea_db(cea, i, start, end) \ 4135 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 4136 4137 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector, 4138 const u8 *db) 4139 { 4140 struct drm_display_info *info = &connector->display_info; 4141 struct drm_hdmi_info *hdmi = &info->hdmi; 4142 u8 map_len = cea_db_payload_len(db) - 1; 4143 u8 count; 4144 u64 map = 0; 4145 4146 if (map_len == 0) { 4147 /* All CEA modes support ycbcr420 sampling also.*/ 4148 hdmi->y420_cmdb_map = U64_MAX; 4149 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 4150 return; 4151 } 4152 4153 /* 4154 * This map indicates which of the existing CEA block modes 4155 * from VDB can support YCBCR420 output too. So if bit=0 is 4156 * set, first mode from VDB can support YCBCR420 output too. 4157 * We will parse and keep this map, before parsing VDB itself 4158 * to avoid going through the same block again and again. 4159 * 4160 * Spec is not clear about max possible size of this block. 4161 * Clamping max bitmap block size at 8 bytes. Every byte can 4162 * address 8 CEA modes, in this way this map can address 4163 * 8*8 = first 64 SVDs. 4164 */ 4165 if (WARN_ON_ONCE(map_len > 8)) 4166 map_len = 8; 4167 4168 for (count = 0; count < map_len; count++) 4169 map |= (u64)db[2 + count] << (8 * count); 4170 4171 if (map) 4172 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 4173 4174 hdmi->y420_cmdb_map = map; 4175 } 4176 4177 static int 4178 add_cea_modes(struct drm_connector *connector, struct edid *edid) 4179 { 4180 const u8 *cea = drm_find_cea_extension(edid); 4181 const u8 *db, *hdmi = NULL, *video = NULL; 4182 u8 dbl, hdmi_len, video_len = 0; 4183 int modes = 0; 4184 4185 if (cea && cea_revision(cea) >= 3) { 4186 int i, start, end; 4187 4188 if (cea_db_offsets(cea, &start, &end)) 4189 return 0; 4190 4191 for_each_cea_db(cea, i, start, end) { 4192 db = &cea[i]; 4193 dbl = cea_db_payload_len(db); 4194 4195 if (cea_db_tag(db) == VIDEO_BLOCK) { 4196 video = db + 1; 4197 video_len = dbl; 4198 modes += do_cea_modes(connector, video, dbl); 4199 } else if (cea_db_is_hdmi_vsdb(db)) { 4200 hdmi = db; 4201 hdmi_len = dbl; 4202 } else if (cea_db_is_y420vdb(db)) { 4203 const u8 *vdb420 = &db[2]; 4204 4205 /* Add 4:2:0(only) modes present in EDID */ 4206 modes += do_y420vdb_modes(connector, 4207 vdb420, 4208 dbl - 1); 4209 } 4210 } 4211 } 4212 4213 /* 4214 * We parse the HDMI VSDB after having added the cea modes as we will 4215 * be patching their flags when the sink supports stereo 3D. 4216 */ 4217 if (hdmi) 4218 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, 4219 video_len); 4220 4221 return modes; 4222 } 4223 4224 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 4225 { 4226 const struct drm_display_mode *cea_mode; 4227 int clock1, clock2, clock; 4228 u8 vic; 4229 const char *type; 4230 4231 /* 4232 * allow 5kHz clock difference either way to account for 4233 * the 10kHz clock resolution limit of detailed timings. 4234 */ 4235 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 4236 if (drm_valid_cea_vic(vic)) { 4237 type = "CEA"; 4238 cea_mode = cea_mode_for_vic(vic); 4239 clock1 = cea_mode->clock; 4240 clock2 = cea_mode_alternate_clock(cea_mode); 4241 } else { 4242 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 4243 if (drm_valid_hdmi_vic(vic)) { 4244 type = "HDMI"; 4245 cea_mode = &edid_4k_modes[vic]; 4246 clock1 = cea_mode->clock; 4247 clock2 = hdmi_mode_alternate_clock(cea_mode); 4248 } else { 4249 return; 4250 } 4251 } 4252 4253 /* pick whichever is closest */ 4254 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 4255 clock = clock1; 4256 else 4257 clock = clock2; 4258 4259 if (mode->clock == clock) 4260 return; 4261 4262 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 4263 type, vic, mode->clock, clock); 4264 mode->clock = clock; 4265 } 4266 4267 static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db) 4268 { 4269 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4270 return false; 4271 4272 if (db[1] != HDR_STATIC_METADATA_BLOCK) 4273 return false; 4274 4275 if (cea_db_payload_len(db) < 3) 4276 return false; 4277 4278 return true; 4279 } 4280 4281 static uint8_t eotf_supported(const u8 *edid_ext) 4282 { 4283 return edid_ext[2] & 4284 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) | 4285 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) | 4286 BIT(HDMI_EOTF_SMPTE_ST2084) | 4287 BIT(HDMI_EOTF_BT_2100_HLG)); 4288 } 4289 4290 static uint8_t hdr_metadata_type(const u8 *edid_ext) 4291 { 4292 return edid_ext[3] & 4293 BIT(HDMI_STATIC_METADATA_TYPE1); 4294 } 4295 4296 static void 4297 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db) 4298 { 4299 u16 len; 4300 4301 len = cea_db_payload_len(db); 4302 4303 connector->hdr_sink_metadata.hdmi_type1.eotf = 4304 eotf_supported(db); 4305 connector->hdr_sink_metadata.hdmi_type1.metadata_type = 4306 hdr_metadata_type(db); 4307 4308 if (len >= 4) 4309 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4]; 4310 if (len >= 5) 4311 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5]; 4312 if (len >= 6) 4313 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6]; 4314 } 4315 4316 static void 4317 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 4318 { 4319 u8 len = cea_db_payload_len(db); 4320 4321 if (len >= 6 && (db[6] & (1 << 7))) 4322 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI; 4323 if (len >= 8) { 4324 connector->latency_present[0] = db[8] >> 7; 4325 connector->latency_present[1] = (db[8] >> 6) & 1; 4326 } 4327 if (len >= 9) 4328 connector->video_latency[0] = db[9]; 4329 if (len >= 10) 4330 connector->audio_latency[0] = db[10]; 4331 if (len >= 11) 4332 connector->video_latency[1] = db[11]; 4333 if (len >= 12) 4334 connector->audio_latency[1] = db[12]; 4335 4336 DRM_DEBUG_KMS("HDMI: latency present %d %d, " 4337 "video latency %d %d, " 4338 "audio latency %d %d\n", 4339 connector->latency_present[0], 4340 connector->latency_present[1], 4341 connector->video_latency[0], 4342 connector->video_latency[1], 4343 connector->audio_latency[0], 4344 connector->audio_latency[1]); 4345 } 4346 4347 static void 4348 monitor_name(struct detailed_timing *t, void *data) 4349 { 4350 if (!is_display_descriptor((const u8 *)t, EDID_DETAIL_MONITOR_NAME)) 4351 return; 4352 4353 *(u8 **)data = t->data.other_data.data.str.str; 4354 } 4355 4356 static int get_monitor_name(struct edid *edid, char name[13]) 4357 { 4358 char *edid_name = NULL; 4359 int mnl; 4360 4361 if (!edid || !name) 4362 return 0; 4363 4364 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name); 4365 for (mnl = 0; edid_name && mnl < 13; mnl++) { 4366 if (edid_name[mnl] == 0x0a) 4367 break; 4368 4369 name[mnl] = edid_name[mnl]; 4370 } 4371 4372 return mnl; 4373 } 4374 4375 /** 4376 * drm_edid_get_monitor_name - fetch the monitor name from the edid 4377 * @edid: monitor EDID information 4378 * @name: pointer to a character array to hold the name of the monitor 4379 * @bufsize: The size of the name buffer (should be at least 14 chars.) 4380 * 4381 */ 4382 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize) 4383 { 4384 int name_length; 4385 char buf[13]; 4386 4387 if (bufsize <= 0) 4388 return; 4389 4390 name_length = min(get_monitor_name(edid, buf), bufsize - 1); 4391 memcpy(name, buf, name_length); 4392 name[name_length] = '\0'; 4393 } 4394 EXPORT_SYMBOL(drm_edid_get_monitor_name); 4395 4396 static void clear_eld(struct drm_connector *connector) 4397 { 4398 memset(connector->eld, 0, sizeof(connector->eld)); 4399 4400 connector->latency_present[0] = false; 4401 connector->latency_present[1] = false; 4402 connector->video_latency[0] = 0; 4403 connector->audio_latency[0] = 0; 4404 connector->video_latency[1] = 0; 4405 connector->audio_latency[1] = 0; 4406 } 4407 4408 /* 4409 * drm_edid_to_eld - build ELD from EDID 4410 * @connector: connector corresponding to the HDMI/DP sink 4411 * @edid: EDID to parse 4412 * 4413 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 4414 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 4415 */ 4416 static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 4417 { 4418 uint8_t *eld = connector->eld; 4419 u8 *cea; 4420 u8 *db; 4421 int total_sad_count = 0; 4422 int mnl; 4423 int dbl; 4424 4425 clear_eld(connector); 4426 4427 if (!edid) 4428 return; 4429 4430 cea = drm_find_cea_extension(edid); 4431 if (!cea) { 4432 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 4433 return; 4434 } 4435 4436 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]); 4437 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]); 4438 4439 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT; 4440 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl; 4441 4442 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D; 4443 4444 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0]; 4445 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1]; 4446 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0]; 4447 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1]; 4448 4449 if (cea_revision(cea) >= 3) { 4450 int i, start, end; 4451 int sad_count; 4452 4453 if (cea_db_offsets(cea, &start, &end)) { 4454 start = 0; 4455 end = 0; 4456 } 4457 4458 for_each_cea_db(cea, i, start, end) { 4459 db = &cea[i]; 4460 dbl = cea_db_payload_len(db); 4461 4462 switch (cea_db_tag(db)) { 4463 case AUDIO_BLOCK: 4464 /* Audio Data Block, contains SADs */ 4465 sad_count = min(dbl / 3, 15 - total_sad_count); 4466 if (sad_count >= 1) 4467 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)], 4468 &db[1], sad_count * 3); 4469 total_sad_count += sad_count; 4470 break; 4471 case SPEAKER_BLOCK: 4472 /* Speaker Allocation Data Block */ 4473 if (dbl >= 1) 4474 eld[DRM_ELD_SPEAKER] = db[1]; 4475 break; 4476 case VENDOR_BLOCK: 4477 /* HDMI Vendor-Specific Data Block */ 4478 if (cea_db_is_hdmi_vsdb(db)) 4479 drm_parse_hdmi_vsdb_audio(connector, db); 4480 break; 4481 default: 4482 break; 4483 } 4484 } 4485 } 4486 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT; 4487 4488 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 4489 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 4490 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 4491 else 4492 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 4493 4494 eld[DRM_ELD_BASELINE_ELD_LEN] = 4495 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 4496 4497 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", 4498 drm_eld_size(eld), total_sad_count); 4499 } 4500 4501 /** 4502 * drm_edid_to_sad - extracts SADs from EDID 4503 * @edid: EDID to parse 4504 * @sads: pointer that will be set to the extracted SADs 4505 * 4506 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 4507 * 4508 * Note: The returned pointer needs to be freed using kfree(). 4509 * 4510 * Return: The number of found SADs or negative number on error. 4511 */ 4512 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) 4513 { 4514 int count = 0; 4515 int i, start, end, dbl; 4516 u8 *cea; 4517 4518 cea = drm_find_cea_extension(edid); 4519 if (!cea) { 4520 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4521 return 0; 4522 } 4523 4524 if (cea_revision(cea) < 3) { 4525 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4526 return 0; 4527 } 4528 4529 if (cea_db_offsets(cea, &start, &end)) { 4530 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4531 return -EPROTO; 4532 } 4533 4534 for_each_cea_db(cea, i, start, end) { 4535 u8 *db = &cea[i]; 4536 4537 if (cea_db_tag(db) == AUDIO_BLOCK) { 4538 int j; 4539 dbl = cea_db_payload_len(db); 4540 4541 count = dbl / 3; /* SAD is 3B */ 4542 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 4543 if (!*sads) 4544 return -ENOMEM; 4545 for (j = 0; j < count; j++) { 4546 u8 *sad = &db[1 + j * 3]; 4547 4548 (*sads)[j].format = (sad[0] & 0x78) >> 3; 4549 (*sads)[j].channels = sad[0] & 0x7; 4550 (*sads)[j].freq = sad[1] & 0x7F; 4551 (*sads)[j].byte2 = sad[2]; 4552 } 4553 break; 4554 } 4555 } 4556 4557 return count; 4558 } 4559 EXPORT_SYMBOL(drm_edid_to_sad); 4560 4561 /** 4562 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 4563 * @edid: EDID to parse 4564 * @sadb: pointer to the speaker block 4565 * 4566 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 4567 * 4568 * Note: The returned pointer needs to be freed using kfree(). 4569 * 4570 * Return: The number of found Speaker Allocation Blocks or negative number on 4571 * error. 4572 */ 4573 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) 4574 { 4575 int count = 0; 4576 int i, start, end, dbl; 4577 const u8 *cea; 4578 4579 cea = drm_find_cea_extension(edid); 4580 if (!cea) { 4581 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4582 return 0; 4583 } 4584 4585 if (cea_revision(cea) < 3) { 4586 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4587 return 0; 4588 } 4589 4590 if (cea_db_offsets(cea, &start, &end)) { 4591 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4592 return -EPROTO; 4593 } 4594 4595 for_each_cea_db(cea, i, start, end) { 4596 const u8 *db = &cea[i]; 4597 4598 if (cea_db_tag(db) == SPEAKER_BLOCK) { 4599 dbl = cea_db_payload_len(db); 4600 4601 /* Speaker Allocation Data Block */ 4602 if (dbl == 3) { 4603 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); 4604 if (!*sadb) 4605 return -ENOMEM; 4606 count = dbl; 4607 break; 4608 } 4609 } 4610 } 4611 4612 return count; 4613 } 4614 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 4615 4616 /** 4617 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 4618 * @connector: connector associated with the HDMI/DP sink 4619 * @mode: the display mode 4620 * 4621 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 4622 * the sink doesn't support audio or video. 4623 */ 4624 int drm_av_sync_delay(struct drm_connector *connector, 4625 const struct drm_display_mode *mode) 4626 { 4627 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 4628 int a, v; 4629 4630 if (!connector->latency_present[0]) 4631 return 0; 4632 if (!connector->latency_present[1]) 4633 i = 0; 4634 4635 a = connector->audio_latency[i]; 4636 v = connector->video_latency[i]; 4637 4638 /* 4639 * HDMI/DP sink doesn't support audio or video? 4640 */ 4641 if (a == 255 || v == 255) 4642 return 0; 4643 4644 /* 4645 * Convert raw EDID values to millisecond. 4646 * Treat unknown latency as 0ms. 4647 */ 4648 if (a) 4649 a = min(2 * (a - 1), 500); 4650 if (v) 4651 v = min(2 * (v - 1), 500); 4652 4653 return max(v - a, 0); 4654 } 4655 EXPORT_SYMBOL(drm_av_sync_delay); 4656 4657 /** 4658 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 4659 * @edid: monitor EDID information 4660 * 4661 * Parse the CEA extension according to CEA-861-B. 4662 * 4663 * Drivers that have added the modes parsed from EDID to drm_display_info 4664 * should use &drm_display_info.is_hdmi instead of calling this function. 4665 * 4666 * Return: True if the monitor is HDMI, false if not or unknown. 4667 */ 4668 bool drm_detect_hdmi_monitor(struct edid *edid) 4669 { 4670 u8 *edid_ext; 4671 int i; 4672 int start_offset, end_offset; 4673 4674 edid_ext = drm_find_cea_extension(edid); 4675 if (!edid_ext) 4676 return false; 4677 4678 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4679 return false; 4680 4681 /* 4682 * Because HDMI identifier is in Vendor Specific Block, 4683 * search it from all data blocks of CEA extension. 4684 */ 4685 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4686 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 4687 return true; 4688 } 4689 4690 return false; 4691 } 4692 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 4693 4694 /** 4695 * drm_detect_monitor_audio - check monitor audio capability 4696 * @edid: EDID block to scan 4697 * 4698 * Monitor should have CEA extension block. 4699 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 4700 * audio' only. If there is any audio extension block and supported 4701 * audio format, assume at least 'basic audio' support, even if 'basic 4702 * audio' is not defined in EDID. 4703 * 4704 * Return: True if the monitor supports audio, false otherwise. 4705 */ 4706 bool drm_detect_monitor_audio(struct edid *edid) 4707 { 4708 u8 *edid_ext; 4709 int i, j; 4710 bool has_audio = false; 4711 int start_offset, end_offset; 4712 4713 edid_ext = drm_find_cea_extension(edid); 4714 if (!edid_ext) 4715 goto end; 4716 4717 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 4718 4719 if (has_audio) { 4720 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 4721 goto end; 4722 } 4723 4724 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4725 goto end; 4726 4727 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4728 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 4729 has_audio = true; 4730 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 4731 DRM_DEBUG_KMS("CEA audio format %d\n", 4732 (edid_ext[i + j] >> 3) & 0xf); 4733 goto end; 4734 } 4735 } 4736 end: 4737 return has_audio; 4738 } 4739 EXPORT_SYMBOL(drm_detect_monitor_audio); 4740 4741 4742 /** 4743 * drm_default_rgb_quant_range - default RGB quantization range 4744 * @mode: display mode 4745 * 4746 * Determine the default RGB quantization range for the mode, 4747 * as specified in CEA-861. 4748 * 4749 * Return: The default RGB quantization range for the mode 4750 */ 4751 enum hdmi_quantization_range 4752 drm_default_rgb_quant_range(const struct drm_display_mode *mode) 4753 { 4754 /* All CEA modes other than VIC 1 use limited quantization range. */ 4755 return drm_match_cea_mode(mode) > 1 ? 4756 HDMI_QUANTIZATION_RANGE_LIMITED : 4757 HDMI_QUANTIZATION_RANGE_FULL; 4758 } 4759 EXPORT_SYMBOL(drm_default_rgb_quant_range); 4760 4761 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db) 4762 { 4763 struct drm_display_info *info = &connector->display_info; 4764 4765 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]); 4766 4767 if (db[2] & EDID_CEA_VCDB_QS) 4768 info->rgb_quant_range_selectable = true; 4769 } 4770 4771 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 4772 const u8 *db) 4773 { 4774 u8 dc_mask; 4775 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 4776 4777 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 4778 hdmi->y420_dc_modes = dc_mask; 4779 } 4780 4781 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector, 4782 const u8 *hf_vsdb) 4783 { 4784 struct drm_display_info *display = &connector->display_info; 4785 struct drm_hdmi_info *hdmi = &display->hdmi; 4786 4787 display->has_hdmi_infoframe = true; 4788 4789 if (hf_vsdb[6] & 0x80) { 4790 hdmi->scdc.supported = true; 4791 if (hf_vsdb[6] & 0x40) 4792 hdmi->scdc.read_request = true; 4793 } 4794 4795 /* 4796 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 4797 * And as per the spec, three factors confirm this: 4798 * * Availability of a HF-VSDB block in EDID (check) 4799 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 4800 * * SCDC support available (let's check) 4801 * Lets check it out. 4802 */ 4803 4804 if (hf_vsdb[5]) { 4805 /* max clock is 5000 KHz times block value */ 4806 u32 max_tmds_clock = hf_vsdb[5] * 5000; 4807 struct drm_scdc *scdc = &hdmi->scdc; 4808 4809 if (max_tmds_clock > 340000) { 4810 display->max_tmds_clock = max_tmds_clock; 4811 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n", 4812 display->max_tmds_clock); 4813 } 4814 4815 if (scdc->supported) { 4816 scdc->scrambling.supported = true; 4817 4818 /* Few sinks support scrambling for clocks < 340M */ 4819 if ((hf_vsdb[6] & 0x8)) 4820 scdc->scrambling.low_rates = true; 4821 } 4822 } 4823 4824 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb); 4825 } 4826 4827 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 4828 const u8 *hdmi) 4829 { 4830 struct drm_display_info *info = &connector->display_info; 4831 unsigned int dc_bpc = 0; 4832 4833 /* HDMI supports at least 8 bpc */ 4834 info->bpc = 8; 4835 4836 if (cea_db_payload_len(hdmi) < 6) 4837 return; 4838 4839 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 4840 dc_bpc = 10; 4841 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 4842 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 4843 connector->name); 4844 } 4845 4846 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 4847 dc_bpc = 12; 4848 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 4849 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 4850 connector->name); 4851 } 4852 4853 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 4854 dc_bpc = 16; 4855 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 4856 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 4857 connector->name); 4858 } 4859 4860 if (dc_bpc == 0) { 4861 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 4862 connector->name); 4863 return; 4864 } 4865 4866 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 4867 connector->name, dc_bpc); 4868 info->bpc = dc_bpc; 4869 4870 /* 4871 * Deep color support mandates RGB444 support for all video 4872 * modes and forbids YCRCB422 support for all video modes per 4873 * HDMI 1.3 spec. 4874 */ 4875 info->color_formats = DRM_COLOR_FORMAT_RGB444; 4876 4877 /* YCRCB444 is optional according to spec. */ 4878 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 4879 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4880 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 4881 connector->name); 4882 } 4883 4884 /* 4885 * Spec says that if any deep color mode is supported at all, 4886 * then deep color 36 bit must be supported. 4887 */ 4888 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 4889 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 4890 connector->name); 4891 } 4892 } 4893 4894 static void 4895 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 4896 { 4897 struct drm_display_info *info = &connector->display_info; 4898 u8 len = cea_db_payload_len(db); 4899 4900 info->is_hdmi = true; 4901 4902 if (len >= 6) 4903 info->dvi_dual = db[6] & 1; 4904 if (len >= 7) 4905 info->max_tmds_clock = db[7] * 5000; 4906 4907 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 4908 "max TMDS clock %d kHz\n", 4909 info->dvi_dual, 4910 info->max_tmds_clock); 4911 4912 drm_parse_hdmi_deep_color_info(connector, db); 4913 } 4914 4915 static void drm_parse_cea_ext(struct drm_connector *connector, 4916 const struct edid *edid) 4917 { 4918 struct drm_display_info *info = &connector->display_info; 4919 const u8 *edid_ext; 4920 int i, start, end; 4921 4922 edid_ext = drm_find_cea_extension(edid); 4923 if (!edid_ext) 4924 return; 4925 4926 info->cea_rev = edid_ext[1]; 4927 4928 /* The existence of a CEA block should imply RGB support */ 4929 info->color_formats = DRM_COLOR_FORMAT_RGB444; 4930 if (edid_ext[3] & EDID_CEA_YCRCB444) 4931 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4932 if (edid_ext[3] & EDID_CEA_YCRCB422) 4933 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 4934 4935 if (cea_db_offsets(edid_ext, &start, &end)) 4936 return; 4937 4938 for_each_cea_db(edid_ext, i, start, end) { 4939 const u8 *db = &edid_ext[i]; 4940 4941 if (cea_db_is_hdmi_vsdb(db)) 4942 drm_parse_hdmi_vsdb_video(connector, db); 4943 if (cea_db_is_hdmi_forum_vsdb(db)) 4944 drm_parse_hdmi_forum_vsdb(connector, db); 4945 if (cea_db_is_y420cmdb(db)) 4946 drm_parse_y420cmdb_bitmap(connector, db); 4947 if (cea_db_is_vcdb(db)) 4948 drm_parse_vcdb(connector, db); 4949 if (cea_db_is_hdmi_hdr_metadata_block(db)) 4950 drm_parse_hdr_metadata_block(connector, db); 4951 } 4952 } 4953 4954 static 4955 void get_monitor_range(struct detailed_timing *timing, 4956 void *info_monitor_range) 4957 { 4958 struct drm_monitor_range_info *monitor_range = info_monitor_range; 4959 const struct detailed_non_pixel *data = &timing->data.other_data; 4960 const struct detailed_data_monitor_range *range = &data->data.range; 4961 4962 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE)) 4963 return; 4964 4965 /* 4966 * Check for flag range limits only. If flag == 1 then 4967 * no additional timing information provided. 4968 * Default GTF, GTF Secondary curve and CVT are not 4969 * supported 4970 */ 4971 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG) 4972 return; 4973 4974 monitor_range->min_vfreq = range->min_vfreq; 4975 monitor_range->max_vfreq = range->max_vfreq; 4976 } 4977 4978 static 4979 void drm_get_monitor_range(struct drm_connector *connector, 4980 const struct edid *edid) 4981 { 4982 struct drm_display_info *info = &connector->display_info; 4983 4984 if (!version_greater(edid, 1, 1)) 4985 return; 4986 4987 drm_for_each_detailed_block((u8 *)edid, get_monitor_range, 4988 &info->monitor_range); 4989 4990 DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n", 4991 info->monitor_range.min_vfreq, 4992 info->monitor_range.max_vfreq); 4993 } 4994 4995 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset 4996 * all of the values which would have been set from EDID 4997 */ 4998 void 4999 drm_reset_display_info(struct drm_connector *connector) 5000 { 5001 struct drm_display_info *info = &connector->display_info; 5002 5003 info->width_mm = 0; 5004 info->height_mm = 0; 5005 5006 info->bpc = 0; 5007 info->color_formats = 0; 5008 info->cea_rev = 0; 5009 info->max_tmds_clock = 0; 5010 info->dvi_dual = false; 5011 info->is_hdmi = false; 5012 info->has_hdmi_infoframe = false; 5013 info->rgb_quant_range_selectable = false; 5014 memset(&info->hdmi, 0, sizeof(info->hdmi)); 5015 5016 info->non_desktop = 0; 5017 memset(&info->monitor_range, 0, sizeof(info->monitor_range)); 5018 } 5019 5020 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid) 5021 { 5022 struct drm_display_info *info = &connector->display_info; 5023 5024 u32 quirks = edid_get_quirks(edid); 5025 5026 drm_reset_display_info(connector); 5027 5028 info->width_mm = edid->width_cm * 10; 5029 info->height_mm = edid->height_cm * 10; 5030 5031 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP); 5032 5033 drm_get_monitor_range(connector, edid); 5034 5035 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop); 5036 5037 if (edid->revision < 3) 5038 return quirks; 5039 5040 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 5041 return quirks; 5042 5043 drm_parse_cea_ext(connector, edid); 5044 5045 /* 5046 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 5047 * 5048 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 5049 * tells us to assume 8 bpc color depth if the EDID doesn't have 5050 * extensions which tell otherwise. 5051 */ 5052 if (info->bpc == 0 && edid->revision == 3 && 5053 edid->input & DRM_EDID_DIGITAL_DFP_1_X) { 5054 info->bpc = 8; 5055 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n", 5056 connector->name, info->bpc); 5057 } 5058 5059 /* Only defined for 1.4 with digital displays */ 5060 if (edid->revision < 4) 5061 return quirks; 5062 5063 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 5064 case DRM_EDID_DIGITAL_DEPTH_6: 5065 info->bpc = 6; 5066 break; 5067 case DRM_EDID_DIGITAL_DEPTH_8: 5068 info->bpc = 8; 5069 break; 5070 case DRM_EDID_DIGITAL_DEPTH_10: 5071 info->bpc = 10; 5072 break; 5073 case DRM_EDID_DIGITAL_DEPTH_12: 5074 info->bpc = 12; 5075 break; 5076 case DRM_EDID_DIGITAL_DEPTH_14: 5077 info->bpc = 14; 5078 break; 5079 case DRM_EDID_DIGITAL_DEPTH_16: 5080 info->bpc = 16; 5081 break; 5082 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 5083 default: 5084 info->bpc = 0; 5085 break; 5086 } 5087 5088 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 5089 connector->name, info->bpc); 5090 5091 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 5092 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 5093 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 5094 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 5095 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 5096 return quirks; 5097 } 5098 5099 static int validate_displayid(u8 *displayid, int length, int idx) 5100 { 5101 int i, dispid_length; 5102 u8 csum = 0; 5103 struct displayid_hdr *base; 5104 5105 base = (struct displayid_hdr *)&displayid[idx]; 5106 5107 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n", 5108 base->rev, base->bytes, base->prod_id, base->ext_count); 5109 5110 /* +1 for DispID checksum */ 5111 dispid_length = sizeof(*base) + base->bytes + 1; 5112 if (dispid_length > length - idx) 5113 return -EINVAL; 5114 5115 for (i = 0; i < dispid_length; i++) 5116 csum += displayid[idx + i]; 5117 if (csum) { 5118 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum); 5119 return -EINVAL; 5120 } 5121 5122 return 0; 5123 } 5124 5125 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 5126 struct displayid_detailed_timings_1 *timings) 5127 { 5128 struct drm_display_mode *mode; 5129 unsigned pixel_clock = (timings->pixel_clock[0] | 5130 (timings->pixel_clock[1] << 8) | 5131 (timings->pixel_clock[2] << 16)); 5132 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 5133 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 5134 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 5135 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 5136 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 5137 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 5138 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 5139 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 5140 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 5141 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 5142 mode = drm_mode_create(dev); 5143 if (!mode) 5144 return NULL; 5145 5146 mode->clock = pixel_clock * 10; 5147 mode->hdisplay = hactive; 5148 mode->hsync_start = mode->hdisplay + hsync; 5149 mode->hsync_end = mode->hsync_start + hsync_width; 5150 mode->htotal = mode->hdisplay + hblank; 5151 5152 mode->vdisplay = vactive; 5153 mode->vsync_start = mode->vdisplay + vsync; 5154 mode->vsync_end = mode->vsync_start + vsync_width; 5155 mode->vtotal = mode->vdisplay + vblank; 5156 5157 mode->flags = 0; 5158 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 5159 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 5160 mode->type = DRM_MODE_TYPE_DRIVER; 5161 5162 if (timings->flags & 0x80) 5163 mode->type |= DRM_MODE_TYPE_PREFERRED; 5164 mode->vrefresh = drm_mode_vrefresh(mode); 5165 drm_mode_set_name(mode); 5166 5167 return mode; 5168 } 5169 5170 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 5171 struct displayid_block *block) 5172 { 5173 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 5174 int i; 5175 int num_timings; 5176 struct drm_display_mode *newmode; 5177 int num_modes = 0; 5178 /* blocks must be multiple of 20 bytes length */ 5179 if (block->num_bytes % 20) 5180 return 0; 5181 5182 num_timings = block->num_bytes / 20; 5183 for (i = 0; i < num_timings; i++) { 5184 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 5185 5186 newmode = drm_mode_displayid_detailed(connector->dev, timings); 5187 if (!newmode) 5188 continue; 5189 5190 drm_mode_probed_add(connector, newmode); 5191 num_modes++; 5192 } 5193 return num_modes; 5194 } 5195 5196 static int add_displayid_detailed_modes(struct drm_connector *connector, 5197 struct edid *edid) 5198 { 5199 u8 *displayid; 5200 int length, idx; 5201 struct displayid_block *block; 5202 int num_modes = 0; 5203 5204 displayid = drm_find_displayid_extension(edid, &length, &idx); 5205 if (!displayid) 5206 return 0; 5207 5208 idx += sizeof(struct displayid_hdr); 5209 for_each_displayid_db(displayid, block, idx, length) { 5210 switch (block->tag) { 5211 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 5212 num_modes += add_displayid_detailed_1_modes(connector, block); 5213 break; 5214 } 5215 } 5216 return num_modes; 5217 } 5218 5219 /** 5220 * drm_add_edid_modes - add modes from EDID data, if available 5221 * @connector: connector we're probing 5222 * @edid: EDID data 5223 * 5224 * Add the specified modes to the connector's mode list. Also fills out the 5225 * &drm_display_info structure and ELD in @connector with any information which 5226 * can be derived from the edid. 5227 * 5228 * Return: The number of modes added or 0 if we couldn't find any. 5229 */ 5230 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 5231 { 5232 int num_modes = 0; 5233 u32 quirks; 5234 5235 if (edid == NULL) { 5236 clear_eld(connector); 5237 return 0; 5238 } 5239 if (!drm_edid_is_valid(edid)) { 5240 clear_eld(connector); 5241 dev_warn(connector->dev->dev, "%s: EDID invalid.\n", 5242 connector->name); 5243 return 0; 5244 } 5245 5246 drm_edid_to_eld(connector, edid); 5247 5248 /* 5249 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. 5250 * To avoid multiple parsing of same block, lets parse that map 5251 * from sink info, before parsing CEA modes. 5252 */ 5253 quirks = drm_add_display_info(connector, edid); 5254 5255 /* 5256 * EDID spec says modes should be preferred in this order: 5257 * - preferred detailed mode 5258 * - other detailed modes from base block 5259 * - detailed modes from extension blocks 5260 * - CVT 3-byte code modes 5261 * - standard timing codes 5262 * - established timing codes 5263 * - modes inferred from GTF or CVT range information 5264 * 5265 * We get this pretty much right. 5266 * 5267 * XXX order for additional mode types in extension blocks? 5268 */ 5269 num_modes += add_detailed_modes(connector, edid, quirks); 5270 num_modes += add_cvt_modes(connector, edid); 5271 num_modes += add_standard_modes(connector, edid); 5272 num_modes += add_established_modes(connector, edid); 5273 num_modes += add_cea_modes(connector, edid); 5274 num_modes += add_alternate_cea_modes(connector, edid); 5275 num_modes += add_displayid_detailed_modes(connector, edid); 5276 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 5277 num_modes += add_inferred_modes(connector, edid); 5278 5279 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 5280 edid_fixup_preferred(connector, quirks); 5281 5282 if (quirks & EDID_QUIRK_FORCE_6BPC) 5283 connector->display_info.bpc = 6; 5284 5285 if (quirks & EDID_QUIRK_FORCE_8BPC) 5286 connector->display_info.bpc = 8; 5287 5288 if (quirks & EDID_QUIRK_FORCE_10BPC) 5289 connector->display_info.bpc = 10; 5290 5291 if (quirks & EDID_QUIRK_FORCE_12BPC) 5292 connector->display_info.bpc = 12; 5293 5294 return num_modes; 5295 } 5296 EXPORT_SYMBOL(drm_add_edid_modes); 5297 5298 /** 5299 * drm_add_modes_noedid - add modes for the connectors without EDID 5300 * @connector: connector we're probing 5301 * @hdisplay: the horizontal display limit 5302 * @vdisplay: the vertical display limit 5303 * 5304 * Add the specified modes to the connector's mode list. Only when the 5305 * hdisplay/vdisplay is not beyond the given limit, it will be added. 5306 * 5307 * Return: The number of modes added or 0 if we couldn't find any. 5308 */ 5309 int drm_add_modes_noedid(struct drm_connector *connector, 5310 int hdisplay, int vdisplay) 5311 { 5312 int i, count, num_modes = 0; 5313 struct drm_display_mode *mode; 5314 struct drm_device *dev = connector->dev; 5315 5316 count = ARRAY_SIZE(drm_dmt_modes); 5317 if (hdisplay < 0) 5318 hdisplay = 0; 5319 if (vdisplay < 0) 5320 vdisplay = 0; 5321 5322 for (i = 0; i < count; i++) { 5323 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 5324 if (hdisplay && vdisplay) { 5325 /* 5326 * Only when two are valid, they will be used to check 5327 * whether the mode should be added to the mode list of 5328 * the connector. 5329 */ 5330 if (ptr->hdisplay > hdisplay || 5331 ptr->vdisplay > vdisplay) 5332 continue; 5333 } 5334 if (drm_mode_vrefresh(ptr) > 61) 5335 continue; 5336 mode = drm_mode_duplicate(dev, ptr); 5337 if (mode) { 5338 drm_mode_probed_add(connector, mode); 5339 num_modes++; 5340 } 5341 } 5342 return num_modes; 5343 } 5344 EXPORT_SYMBOL(drm_add_modes_noedid); 5345 5346 /** 5347 * drm_set_preferred_mode - Sets the preferred mode of a connector 5348 * @connector: connector whose mode list should be processed 5349 * @hpref: horizontal resolution of preferred mode 5350 * @vpref: vertical resolution of preferred mode 5351 * 5352 * Marks a mode as preferred if it matches the resolution specified by @hpref 5353 * and @vpref. 5354 */ 5355 void drm_set_preferred_mode(struct drm_connector *connector, 5356 int hpref, int vpref) 5357 { 5358 struct drm_display_mode *mode; 5359 5360 list_for_each_entry(mode, &connector->probed_modes, head) { 5361 if (mode->hdisplay == hpref && 5362 mode->vdisplay == vpref) 5363 mode->type |= DRM_MODE_TYPE_PREFERRED; 5364 } 5365 } 5366 EXPORT_SYMBOL(drm_set_preferred_mode); 5367 5368 static bool is_hdmi2_sink(struct drm_connector *connector) 5369 { 5370 /* 5371 * FIXME: sil-sii8620 doesn't have a connector around when 5372 * we need one, so we have to be prepared for a NULL connector. 5373 */ 5374 if (!connector) 5375 return true; 5376 5377 return connector->display_info.hdmi.scdc.supported || 5378 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420; 5379 } 5380 5381 static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf) 5382 { 5383 return sink_eotf & BIT(output_eotf); 5384 } 5385 5386 /** 5387 * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with 5388 * HDR metadata from userspace 5389 * @frame: HDMI DRM infoframe 5390 * @conn_state: Connector state containing HDR metadata 5391 * 5392 * Return: 0 on success or a negative error code on failure. 5393 */ 5394 int 5395 drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame, 5396 const struct drm_connector_state *conn_state) 5397 { 5398 struct drm_connector *connector; 5399 struct hdr_output_metadata *hdr_metadata; 5400 int err; 5401 5402 if (!frame || !conn_state) 5403 return -EINVAL; 5404 5405 connector = conn_state->connector; 5406 5407 if (!conn_state->hdr_output_metadata) 5408 return -EINVAL; 5409 5410 hdr_metadata = conn_state->hdr_output_metadata->data; 5411 5412 if (!hdr_metadata || !connector) 5413 return -EINVAL; 5414 5415 /* Sink EOTF is Bit map while infoframe is absolute values */ 5416 if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf, 5417 connector->hdr_sink_metadata.hdmi_type1.eotf)) { 5418 DRM_DEBUG_KMS("EOTF Not Supported\n"); 5419 return -EINVAL; 5420 } 5421 5422 err = hdmi_drm_infoframe_init(frame); 5423 if (err < 0) 5424 return err; 5425 5426 frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf; 5427 frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type; 5428 5429 BUILD_BUG_ON(sizeof(frame->display_primaries) != 5430 sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries)); 5431 BUILD_BUG_ON(sizeof(frame->white_point) != 5432 sizeof(hdr_metadata->hdmi_metadata_type1.white_point)); 5433 5434 memcpy(&frame->display_primaries, 5435 &hdr_metadata->hdmi_metadata_type1.display_primaries, 5436 sizeof(frame->display_primaries)); 5437 5438 memcpy(&frame->white_point, 5439 &hdr_metadata->hdmi_metadata_type1.white_point, 5440 sizeof(frame->white_point)); 5441 5442 frame->max_display_mastering_luminance = 5443 hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance; 5444 frame->min_display_mastering_luminance = 5445 hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance; 5446 frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall; 5447 frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll; 5448 5449 return 0; 5450 } 5451 EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata); 5452 5453 static u8 drm_mode_hdmi_vic(struct drm_connector *connector, 5454 const struct drm_display_mode *mode) 5455 { 5456 bool has_hdmi_infoframe = connector ? 5457 connector->display_info.has_hdmi_infoframe : false; 5458 5459 if (!has_hdmi_infoframe) 5460 return 0; 5461 5462 /* No HDMI VIC when signalling 3D video format */ 5463 if (mode->flags & DRM_MODE_FLAG_3D_MASK) 5464 return 0; 5465 5466 return drm_match_hdmi_mode(mode); 5467 } 5468 5469 static u8 drm_mode_cea_vic(struct drm_connector *connector, 5470 const struct drm_display_mode *mode) 5471 { 5472 u8 vic; 5473 5474 /* 5475 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 5476 * we should send its VIC in vendor infoframes, else send the 5477 * VIC in AVI infoframes. Lets check if this mode is present in 5478 * HDMI 1.4b 4K modes 5479 */ 5480 if (drm_mode_hdmi_vic(connector, mode)) 5481 return 0; 5482 5483 vic = drm_match_cea_mode(mode); 5484 5485 /* 5486 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but 5487 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we 5488 * have to make sure we dont break HDMI 1.4 sinks. 5489 */ 5490 if (!is_hdmi2_sink(connector) && vic > 64) 5491 return 0; 5492 5493 return vic; 5494 } 5495 5496 /** 5497 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 5498 * data from a DRM display mode 5499 * @frame: HDMI AVI infoframe 5500 * @connector: the connector 5501 * @mode: DRM display mode 5502 * 5503 * Return: 0 on success or a negative error code on failure. 5504 */ 5505 int 5506 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 5507 struct drm_connector *connector, 5508 const struct drm_display_mode *mode) 5509 { 5510 enum hdmi_picture_aspect picture_aspect; 5511 u8 vic, hdmi_vic; 5512 5513 if (!frame || !mode) 5514 return -EINVAL; 5515 5516 hdmi_avi_infoframe_init(frame); 5517 5518 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 5519 frame->pixel_repeat = 1; 5520 5521 vic = drm_mode_cea_vic(connector, mode); 5522 hdmi_vic = drm_mode_hdmi_vic(connector, mode); 5523 5524 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5525 5526 /* 5527 * As some drivers don't support atomic, we can't use connector state. 5528 * So just initialize the frame with default values, just the same way 5529 * as it's done with other properties here. 5530 */ 5531 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; 5532 frame->itc = 0; 5533 5534 /* 5535 * Populate picture aspect ratio from either 5536 * user input (if specified) or from the CEA/HDMI mode lists. 5537 */ 5538 picture_aspect = mode->picture_aspect_ratio; 5539 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) { 5540 if (vic) 5541 picture_aspect = drm_get_cea_aspect_ratio(vic); 5542 else if (hdmi_vic) 5543 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic); 5544 } 5545 5546 /* 5547 * The infoframe can't convey anything but none, 4:3 5548 * and 16:9, so if the user has asked for anything else 5549 * we can only satisfy it by specifying the right VIC. 5550 */ 5551 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { 5552 if (vic) { 5553 if (picture_aspect != drm_get_cea_aspect_ratio(vic)) 5554 return -EINVAL; 5555 } else if (hdmi_vic) { 5556 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic)) 5557 return -EINVAL; 5558 } else { 5559 return -EINVAL; 5560 } 5561 5562 picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5563 } 5564 5565 frame->video_code = vic; 5566 frame->picture_aspect = picture_aspect; 5567 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 5568 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 5569 5570 return 0; 5571 } 5572 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 5573 5574 /* HDMI Colorspace Spec Definitions */ 5575 #define FULL_COLORIMETRY_MASK 0x1FF 5576 #define NORMAL_COLORIMETRY_MASK 0x3 5577 #define EXTENDED_COLORIMETRY_MASK 0x7 5578 #define EXTENDED_ACE_COLORIMETRY_MASK 0xF 5579 5580 #define C(x) ((x) << 0) 5581 #define EC(x) ((x) << 2) 5582 #define ACE(x) ((x) << 5) 5583 5584 #define HDMI_COLORIMETRY_NO_DATA 0x0 5585 #define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0)) 5586 #define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0)) 5587 #define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0)) 5588 #define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0)) 5589 #define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0)) 5590 #define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0)) 5591 #define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0)) 5592 #define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0)) 5593 #define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0)) 5594 #define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0)) 5595 #define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0)) 5596 #define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1)) 5597 5598 static const u32 hdmi_colorimetry_val[] = { 5599 [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA, 5600 [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC, 5601 [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC, 5602 [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601, 5603 [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709, 5604 [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601, 5605 [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601, 5606 [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB, 5607 [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC, 5608 [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB, 5609 [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC, 5610 }; 5611 5612 #undef C 5613 #undef EC 5614 #undef ACE 5615 5616 /** 5617 * drm_hdmi_avi_infoframe_colorspace() - fill the HDMI AVI infoframe 5618 * colorspace information 5619 * @frame: HDMI AVI infoframe 5620 * @conn_state: connector state 5621 */ 5622 void 5623 drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame, 5624 const struct drm_connector_state *conn_state) 5625 { 5626 u32 colorimetry_val; 5627 u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK; 5628 5629 if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val)) 5630 colorimetry_val = HDMI_COLORIMETRY_NO_DATA; 5631 else 5632 colorimetry_val = hdmi_colorimetry_val[colorimetry_index]; 5633 5634 frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK; 5635 /* 5636 * ToDo: Extend it for ACE formats as well. Modify the infoframe 5637 * structure and extend it in drivers/video/hdmi 5638 */ 5639 frame->extended_colorimetry = (colorimetry_val >> 2) & 5640 EXTENDED_COLORIMETRY_MASK; 5641 } 5642 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace); 5643 5644 /** 5645 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 5646 * quantization range information 5647 * @frame: HDMI AVI infoframe 5648 * @connector: the connector 5649 * @mode: DRM display mode 5650 * @rgb_quant_range: RGB quantization range (Q) 5651 */ 5652 void 5653 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 5654 struct drm_connector *connector, 5655 const struct drm_display_mode *mode, 5656 enum hdmi_quantization_range rgb_quant_range) 5657 { 5658 const struct drm_display_info *info = &connector->display_info; 5659 5660 /* 5661 * CEA-861: 5662 * "A Source shall not send a non-zero Q value that does not correspond 5663 * to the default RGB Quantization Range for the transmitted Picture 5664 * unless the Sink indicates support for the Q bit in a Video 5665 * Capabilities Data Block." 5666 * 5667 * HDMI 2.0 recommends sending non-zero Q when it does match the 5668 * default RGB quantization range for the mode, even when QS=0. 5669 */ 5670 if (info->rgb_quant_range_selectable || 5671 rgb_quant_range == drm_default_rgb_quant_range(mode)) 5672 frame->quantization_range = rgb_quant_range; 5673 else 5674 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 5675 5676 /* 5677 * CEA-861-F: 5678 * "When transmitting any RGB colorimetry, the Source should set the 5679 * YQ-field to match the RGB Quantization Range being transmitted 5680 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 5681 * set YQ=1) and the Sink shall ignore the YQ-field." 5682 * 5683 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused 5684 * by non-zero YQ when receiving RGB. There doesn't seem to be any 5685 * good way to tell which version of CEA-861 the sink supports, so 5686 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based 5687 * on on CEA-861-F. 5688 */ 5689 if (!is_hdmi2_sink(connector) || 5690 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 5691 frame->ycc_quantization_range = 5692 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 5693 else 5694 frame->ycc_quantization_range = 5695 HDMI_YCC_QUANTIZATION_RANGE_FULL; 5696 } 5697 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 5698 5699 /** 5700 * drm_hdmi_avi_infoframe_bars() - fill the HDMI AVI infoframe 5701 * bar information 5702 * @frame: HDMI AVI infoframe 5703 * @conn_state: connector state 5704 */ 5705 void 5706 drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame, 5707 const struct drm_connector_state *conn_state) 5708 { 5709 frame->right_bar = conn_state->tv.margins.right; 5710 frame->left_bar = conn_state->tv.margins.left; 5711 frame->top_bar = conn_state->tv.margins.top; 5712 frame->bottom_bar = conn_state->tv.margins.bottom; 5713 } 5714 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_bars); 5715 5716 static enum hdmi_3d_structure 5717 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 5718 { 5719 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 5720 5721 switch (layout) { 5722 case DRM_MODE_FLAG_3D_FRAME_PACKING: 5723 return HDMI_3D_STRUCTURE_FRAME_PACKING; 5724 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 5725 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 5726 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 5727 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 5728 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 5729 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 5730 case DRM_MODE_FLAG_3D_L_DEPTH: 5731 return HDMI_3D_STRUCTURE_L_DEPTH; 5732 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 5733 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 5734 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 5735 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 5736 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 5737 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 5738 default: 5739 return HDMI_3D_STRUCTURE_INVALID; 5740 } 5741 } 5742 5743 /** 5744 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 5745 * data from a DRM display mode 5746 * @frame: HDMI vendor infoframe 5747 * @connector: the connector 5748 * @mode: DRM display mode 5749 * 5750 * Note that there's is a need to send HDMI vendor infoframes only when using a 5751 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 5752 * function will return -EINVAL, error that can be safely ignored. 5753 * 5754 * Return: 0 on success or a negative error code on failure. 5755 */ 5756 int 5757 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 5758 struct drm_connector *connector, 5759 const struct drm_display_mode *mode) 5760 { 5761 /* 5762 * FIXME: sil-sii8620 doesn't have a connector around when 5763 * we need one, so we have to be prepared for a NULL connector. 5764 */ 5765 bool has_hdmi_infoframe = connector ? 5766 connector->display_info.has_hdmi_infoframe : false; 5767 int err; 5768 5769 if (!frame || !mode) 5770 return -EINVAL; 5771 5772 if (!has_hdmi_infoframe) 5773 return -EINVAL; 5774 5775 err = hdmi_vendor_infoframe_init(frame); 5776 if (err < 0) 5777 return err; 5778 5779 /* 5780 * Even if it's not absolutely necessary to send the infoframe 5781 * (ie.vic==0 and s3d_struct==0) we will still send it if we 5782 * know that the sink can handle it. This is based on a 5783 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks 5784 * have trouble realizing that they shuld switch from 3D to 2D 5785 * mode if the source simply stops sending the infoframe when 5786 * it wants to switch from 3D to 2D. 5787 */ 5788 frame->vic = drm_mode_hdmi_vic(connector, mode); 5789 frame->s3d_struct = s3d_structure_from_display_mode(mode); 5790 5791 return 0; 5792 } 5793 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 5794 5795 static int drm_parse_tiled_block(struct drm_connector *connector, 5796 const struct displayid_block *block) 5797 { 5798 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 5799 u16 w, h; 5800 u8 tile_v_loc, tile_h_loc; 5801 u8 num_v_tile, num_h_tile; 5802 struct drm_tile_group *tg; 5803 5804 w = tile->tile_size[0] | tile->tile_size[1] << 8; 5805 h = tile->tile_size[2] | tile->tile_size[3] << 8; 5806 5807 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 5808 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 5809 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 5810 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 5811 5812 connector->has_tile = true; 5813 if (tile->tile_cap & 0x80) 5814 connector->tile_is_single_monitor = true; 5815 5816 connector->num_h_tile = num_h_tile + 1; 5817 connector->num_v_tile = num_v_tile + 1; 5818 connector->tile_h_loc = tile_h_loc; 5819 connector->tile_v_loc = tile_v_loc; 5820 connector->tile_h_size = w + 1; 5821 connector->tile_v_size = h + 1; 5822 5823 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); 5824 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); 5825 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", 5826 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); 5827 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 5828 5829 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 5830 if (!tg) { 5831 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 5832 } 5833 if (!tg) 5834 return -ENOMEM; 5835 5836 if (connector->tile_group != tg) { 5837 /* if we haven't got a pointer, 5838 take the reference, drop ref to old tile group */ 5839 if (connector->tile_group) { 5840 drm_mode_put_tile_group(connector->dev, connector->tile_group); 5841 } 5842 connector->tile_group = tg; 5843 } else 5844 /* if same tile group, then release the ref we just took. */ 5845 drm_mode_put_tile_group(connector->dev, tg); 5846 return 0; 5847 } 5848 5849 static int drm_displayid_parse_tiled(struct drm_connector *connector, 5850 const u8 *displayid, int length, int idx) 5851 { 5852 const struct displayid_block *block; 5853 int ret; 5854 5855 idx += sizeof(struct displayid_hdr); 5856 for_each_displayid_db(displayid, block, idx, length) { 5857 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n", 5858 block->tag, block->rev, block->num_bytes); 5859 5860 switch (block->tag) { 5861 case DATA_BLOCK_TILED_DISPLAY: 5862 ret = drm_parse_tiled_block(connector, block); 5863 if (ret) 5864 return ret; 5865 break; 5866 default: 5867 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag); 5868 break; 5869 } 5870 } 5871 return 0; 5872 } 5873 5874 void drm_update_tile_info(struct drm_connector *connector, 5875 const struct edid *edid) 5876 { 5877 const void *displayid = NULL; 5878 int length, idx; 5879 int ret; 5880 5881 connector->has_tile = false; 5882 displayid = drm_find_displayid_extension(edid, &length, &idx); 5883 if (!displayid) { 5884 /* drop reference to any tile group we had */ 5885 goto out_drop_ref; 5886 } 5887 5888 ret = drm_displayid_parse_tiled(connector, displayid, length, idx); 5889 if (ret < 0) 5890 goto out_drop_ref; 5891 if (!connector->has_tile) 5892 goto out_drop_ref; 5893 return; 5894 out_drop_ref: 5895 if (connector->tile_group) { 5896 drm_mode_put_tile_group(connector->dev, connector->tile_group); 5897 connector->tile_group = NULL; 5898 } 5899 return; 5900 } 5901