1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 31 #include <linux/bitfield.h> 32 #include <linux/byteorder/generic.h> 33 #include <linux/cec.h> 34 #include <linux/export.h> 35 #include <linux/hdmi.h> 36 #include <linux/i2c.h> 37 #include <linux/kernel.h> 38 #include <linux/module.h> 39 #include <linux/pci.h> 40 #include <linux/seq_buf.h> 41 #include <linux/slab.h> 42 #include <linux/vga_switcheroo.h> 43 44 #include <drm/drm_drv.h> 45 #include <drm/drm_edid.h> 46 #include <drm/drm_eld.h> 47 #include <drm/drm_encoder.h> 48 #include <drm/drm_print.h> 49 50 #include "drm_crtc_internal.h" 51 #include "drm_displayid_internal.h" 52 #include "drm_internal.h" 53 54 static int oui(u8 first, u8 second, u8 third) 55 { 56 return (first << 16) | (second << 8) | third; 57 } 58 59 #define EDID_EST_TIMINGS 16 60 #define EDID_STD_TIMINGS 8 61 #define EDID_DETAILED_TIMINGS 4 62 63 /* 64 * EDID blocks out in the wild have a variety of bugs, try to collect 65 * them here (note that userspace may work around broken monitors first, 66 * but fixes should make their way here so that the kernel "just works" 67 * on as many displays as possible). 68 */ 69 70 enum drm_edid_internal_quirk { 71 /* First detailed mode wrong, use largest 60Hz mode */ 72 EDID_QUIRK_PREFER_LARGE_60 = DRM_EDID_QUIRK_NUM, 73 /* Reported 135MHz pixel clock is too high, needs adjustment */ 74 EDID_QUIRK_135_CLOCK_TOO_HIGH, 75 /* Prefer the largest mode at 75 Hz */ 76 EDID_QUIRK_PREFER_LARGE_75, 77 /* Detail timing is in cm not mm */ 78 EDID_QUIRK_DETAILED_IN_CM, 79 /* Detailed timing descriptors have bogus size values, so just take the 80 * maximum size and use that. 81 */ 82 EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE, 83 /* use +hsync +vsync for detailed mode */ 84 EDID_QUIRK_DETAILED_SYNC_PP, 85 /* Force reduced-blanking timings for detailed modes */ 86 EDID_QUIRK_FORCE_REDUCED_BLANKING, 87 /* Force 8bpc */ 88 EDID_QUIRK_FORCE_8BPC, 89 /* Force 12bpc */ 90 EDID_QUIRK_FORCE_12BPC, 91 /* Force 6bpc */ 92 EDID_QUIRK_FORCE_6BPC, 93 /* Force 10bpc */ 94 EDID_QUIRK_FORCE_10BPC, 95 /* Non desktop display (i.e. HMD) */ 96 EDID_QUIRK_NON_DESKTOP, 97 /* Cap the DSC target bitrate to 15bpp */ 98 EDID_QUIRK_CAP_DSC_15BPP, 99 }; 100 101 #define MICROSOFT_IEEE_OUI 0xca125c 102 103 struct detailed_mode_closure { 104 struct drm_connector *connector; 105 const struct drm_edid *drm_edid; 106 bool preferred; 107 int modes; 108 }; 109 110 struct drm_edid_match_closure { 111 const struct drm_edid_ident *ident; 112 bool matched; 113 }; 114 115 #define LEVEL_DMT 0 116 #define LEVEL_GTF 1 117 #define LEVEL_GTF2 2 118 #define LEVEL_CVT 3 119 120 #define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \ 121 { \ 122 .ident = { \ 123 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, \ 124 vend_chr_2, product_id), \ 125 }, \ 126 .quirks = _quirks \ 127 } 128 129 static const struct edid_quirk { 130 const struct drm_edid_ident ident; 131 u32 quirks; 132 } edid_quirk_list[] = { 133 /* Acer AL1706 */ 134 EDID_QUIRK('A', 'C', 'R', 44358, BIT(EDID_QUIRK_PREFER_LARGE_60)), 135 /* Acer F51 */ 136 EDID_QUIRK('A', 'P', 'I', 0x7602, BIT(EDID_QUIRK_PREFER_LARGE_60)), 137 138 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 139 EDID_QUIRK('A', 'E', 'O', 0, BIT(EDID_QUIRK_FORCE_6BPC)), 140 141 /* BenQ GW2765 */ 142 EDID_QUIRK('B', 'N', 'Q', 0x78d6, BIT(EDID_QUIRK_FORCE_8BPC)), 143 144 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */ 145 EDID_QUIRK('B', 'O', 'E', 0x78b, BIT(EDID_QUIRK_FORCE_6BPC)), 146 147 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 148 EDID_QUIRK('C', 'P', 'T', 0x17df, BIT(EDID_QUIRK_FORCE_6BPC)), 149 150 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ 151 EDID_QUIRK('S', 'D', 'C', 0x3652, BIT(EDID_QUIRK_FORCE_6BPC)), 152 153 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ 154 EDID_QUIRK('B', 'O', 'E', 0x0771, BIT(EDID_QUIRK_FORCE_6BPC)), 155 156 /* Belinea 10 15 55 */ 157 EDID_QUIRK('M', 'A', 'X', 1516, BIT(EDID_QUIRK_PREFER_LARGE_60)), 158 EDID_QUIRK('M', 'A', 'X', 0x77e, BIT(EDID_QUIRK_PREFER_LARGE_60)), 159 160 /* Envision Peripherals, Inc. EN-7100e */ 161 EDID_QUIRK('E', 'P', 'I', 59264, BIT(EDID_QUIRK_135_CLOCK_TOO_HIGH)), 162 /* Envision EN2028 */ 163 EDID_QUIRK('E', 'P', 'I', 8232, BIT(EDID_QUIRK_PREFER_LARGE_60)), 164 165 /* Funai Electronics PM36B */ 166 EDID_QUIRK('F', 'C', 'M', 13600, BIT(EDID_QUIRK_PREFER_LARGE_75) | 167 BIT(EDID_QUIRK_DETAILED_IN_CM)), 168 169 /* LG 27GP950 */ 170 EDID_QUIRK('G', 'S', 'M', 0x5bbf, BIT(EDID_QUIRK_CAP_DSC_15BPP)), 171 172 /* LG 27GN950 */ 173 EDID_QUIRK('G', 'S', 'M', 0x5b9a, BIT(EDID_QUIRK_CAP_DSC_15BPP)), 174 175 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 176 EDID_QUIRK('L', 'G', 'D', 764, BIT(EDID_QUIRK_FORCE_10BPC)), 177 178 /* LG Philips LCD LP154W01-A5 */ 179 EDID_QUIRK('L', 'P', 'L', 0, BIT(EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE)), 180 EDID_QUIRK('L', 'P', 'L', 0x2a00, BIT(EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE)), 181 182 /* Samsung SyncMaster 205BW. Note: irony */ 183 EDID_QUIRK('S', 'A', 'M', 541, BIT(EDID_QUIRK_DETAILED_SYNC_PP)), 184 /* Samsung SyncMaster 22[5-6]BW */ 185 EDID_QUIRK('S', 'A', 'M', 596, BIT(EDID_QUIRK_PREFER_LARGE_60)), 186 EDID_QUIRK('S', 'A', 'M', 638, BIT(EDID_QUIRK_PREFER_LARGE_60)), 187 188 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 189 EDID_QUIRK('S', 'N', 'Y', 0x2541, BIT(EDID_QUIRK_FORCE_12BPC)), 190 191 /* ViewSonic VA2026w */ 192 EDID_QUIRK('V', 'S', 'C', 5020, BIT(EDID_QUIRK_FORCE_REDUCED_BLANKING)), 193 194 /* Medion MD 30217 PG */ 195 EDID_QUIRK('M', 'E', 'D', 0x7b8, BIT(EDID_QUIRK_PREFER_LARGE_75)), 196 197 /* Lenovo G50 */ 198 EDID_QUIRK('S', 'D', 'C', 18514, BIT(EDID_QUIRK_FORCE_6BPC)), 199 200 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 201 EDID_QUIRK('S', 'E', 'C', 0xd033, BIT(EDID_QUIRK_FORCE_8BPC)), 202 203 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 204 EDID_QUIRK('E', 'T', 'R', 13896, BIT(EDID_QUIRK_FORCE_8BPC)), 205 206 /* Valve Index Headset */ 207 EDID_QUIRK('V', 'L', 'V', 0x91a8, BIT(EDID_QUIRK_NON_DESKTOP)), 208 EDID_QUIRK('V', 'L', 'V', 0x91b0, BIT(EDID_QUIRK_NON_DESKTOP)), 209 EDID_QUIRK('V', 'L', 'V', 0x91b1, BIT(EDID_QUIRK_NON_DESKTOP)), 210 EDID_QUIRK('V', 'L', 'V', 0x91b2, BIT(EDID_QUIRK_NON_DESKTOP)), 211 EDID_QUIRK('V', 'L', 'V', 0x91b3, BIT(EDID_QUIRK_NON_DESKTOP)), 212 EDID_QUIRK('V', 'L', 'V', 0x91b4, BIT(EDID_QUIRK_NON_DESKTOP)), 213 EDID_QUIRK('V', 'L', 'V', 0x91b5, BIT(EDID_QUIRK_NON_DESKTOP)), 214 EDID_QUIRK('V', 'L', 'V', 0x91b6, BIT(EDID_QUIRK_NON_DESKTOP)), 215 EDID_QUIRK('V', 'L', 'V', 0x91b7, BIT(EDID_QUIRK_NON_DESKTOP)), 216 EDID_QUIRK('V', 'L', 'V', 0x91b8, BIT(EDID_QUIRK_NON_DESKTOP)), 217 EDID_QUIRK('V', 'L', 'V', 0x91b9, BIT(EDID_QUIRK_NON_DESKTOP)), 218 EDID_QUIRK('V', 'L', 'V', 0x91ba, BIT(EDID_QUIRK_NON_DESKTOP)), 219 EDID_QUIRK('V', 'L', 'V', 0x91bb, BIT(EDID_QUIRK_NON_DESKTOP)), 220 EDID_QUIRK('V', 'L', 'V', 0x91bc, BIT(EDID_QUIRK_NON_DESKTOP)), 221 EDID_QUIRK('V', 'L', 'V', 0x91bd, BIT(EDID_QUIRK_NON_DESKTOP)), 222 EDID_QUIRK('V', 'L', 'V', 0x91be, BIT(EDID_QUIRK_NON_DESKTOP)), 223 EDID_QUIRK('V', 'L', 'V', 0x91bf, BIT(EDID_QUIRK_NON_DESKTOP)), 224 225 /* HTC Vive and Vive Pro VR Headsets */ 226 EDID_QUIRK('H', 'V', 'R', 0xaa01, BIT(EDID_QUIRK_NON_DESKTOP)), 227 EDID_QUIRK('H', 'V', 'R', 0xaa02, BIT(EDID_QUIRK_NON_DESKTOP)), 228 229 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */ 230 EDID_QUIRK('O', 'V', 'R', 0x0001, BIT(EDID_QUIRK_NON_DESKTOP)), 231 EDID_QUIRK('O', 'V', 'R', 0x0003, BIT(EDID_QUIRK_NON_DESKTOP)), 232 EDID_QUIRK('O', 'V', 'R', 0x0004, BIT(EDID_QUIRK_NON_DESKTOP)), 233 EDID_QUIRK('O', 'V', 'R', 0x0012, BIT(EDID_QUIRK_NON_DESKTOP)), 234 235 /* Windows Mixed Reality Headsets */ 236 EDID_QUIRK('A', 'C', 'R', 0x7fce, BIT(EDID_QUIRK_NON_DESKTOP)), 237 EDID_QUIRK('L', 'E', 'N', 0x0408, BIT(EDID_QUIRK_NON_DESKTOP)), 238 EDID_QUIRK('F', 'U', 'J', 0x1970, BIT(EDID_QUIRK_NON_DESKTOP)), 239 EDID_QUIRK('D', 'E', 'L', 0x7fce, BIT(EDID_QUIRK_NON_DESKTOP)), 240 EDID_QUIRK('S', 'E', 'C', 0x144a, BIT(EDID_QUIRK_NON_DESKTOP)), 241 EDID_QUIRK('A', 'U', 'S', 0xc102, BIT(EDID_QUIRK_NON_DESKTOP)), 242 243 /* Sony PlayStation VR Headset */ 244 EDID_QUIRK('S', 'N', 'Y', 0x0704, BIT(EDID_QUIRK_NON_DESKTOP)), 245 246 /* Sensics VR Headsets */ 247 EDID_QUIRK('S', 'E', 'N', 0x1019, BIT(EDID_QUIRK_NON_DESKTOP)), 248 249 /* OSVR HDK and HDK2 VR Headsets */ 250 EDID_QUIRK('S', 'V', 'R', 0x1019, BIT(EDID_QUIRK_NON_DESKTOP)), 251 EDID_QUIRK('A', 'U', 'O', 0x1111, BIT(EDID_QUIRK_NON_DESKTOP)), 252 253 /* 254 * @drm_edid_internal_quirk entries end here, following with the 255 * @drm_edid_quirk entries. 256 */ 257 258 /* HP ZR24w DP AUX DPCD access requires probing to prevent corruption. */ 259 EDID_QUIRK('H', 'W', 'P', 0x2869, BIT(DRM_EDID_QUIRK_DP_DPCD_PROBE)), 260 }; 261 262 /* 263 * Autogenerated from the DMT spec. 264 * This table is copied from xfree86/modes/xf86EdidModes.c. 265 */ 266 static const struct drm_display_mode drm_dmt_modes[] = { 267 /* 0x01 - 640x350@85Hz */ 268 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 269 736, 832, 0, 350, 382, 385, 445, 0, 270 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 271 /* 0x02 - 640x400@85Hz */ 272 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 273 736, 832, 0, 400, 401, 404, 445, 0, 274 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 275 /* 0x03 - 720x400@85Hz */ 276 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 277 828, 936, 0, 400, 401, 404, 446, 0, 278 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 279 /* 0x04 - 640x480@60Hz */ 280 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 281 752, 800, 0, 480, 490, 492, 525, 0, 282 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 283 /* 0x05 - 640x480@72Hz */ 284 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 285 704, 832, 0, 480, 489, 492, 520, 0, 286 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 287 /* 0x06 - 640x480@75Hz */ 288 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 289 720, 840, 0, 480, 481, 484, 500, 0, 290 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 291 /* 0x07 - 640x480@85Hz */ 292 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 293 752, 832, 0, 480, 481, 484, 509, 0, 294 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 295 /* 0x08 - 800x600@56Hz */ 296 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 297 896, 1024, 0, 600, 601, 603, 625, 0, 298 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 299 /* 0x09 - 800x600@60Hz */ 300 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 301 968, 1056, 0, 600, 601, 605, 628, 0, 302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 303 /* 0x0a - 800x600@72Hz */ 304 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 305 976, 1040, 0, 600, 637, 643, 666, 0, 306 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 307 /* 0x0b - 800x600@75Hz */ 308 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 309 896, 1056, 0, 600, 601, 604, 625, 0, 310 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 311 /* 0x0c - 800x600@85Hz */ 312 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 313 896, 1048, 0, 600, 601, 604, 631, 0, 314 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 315 /* 0x0d - 800x600@120Hz RB */ 316 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 317 880, 960, 0, 600, 603, 607, 636, 0, 318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 319 /* 0x0e - 848x480@60Hz */ 320 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 321 976, 1088, 0, 480, 486, 494, 517, 0, 322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 323 /* 0x0f - 1024x768@43Hz, interlace */ 324 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 325 1208, 1264, 0, 768, 768, 776, 817, 0, 326 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 327 DRM_MODE_FLAG_INTERLACE) }, 328 /* 0x10 - 1024x768@60Hz */ 329 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 330 1184, 1344, 0, 768, 771, 777, 806, 0, 331 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 332 /* 0x11 - 1024x768@70Hz */ 333 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 334 1184, 1328, 0, 768, 771, 777, 806, 0, 335 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 336 /* 0x12 - 1024x768@75Hz */ 337 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 338 1136, 1312, 0, 768, 769, 772, 800, 0, 339 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 340 /* 0x13 - 1024x768@85Hz */ 341 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 342 1168, 1376, 0, 768, 769, 772, 808, 0, 343 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 344 /* 0x14 - 1024x768@120Hz RB */ 345 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 346 1104, 1184, 0, 768, 771, 775, 813, 0, 347 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 348 /* 0x15 - 1152x864@75Hz */ 349 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 350 1344, 1600, 0, 864, 865, 868, 900, 0, 351 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 352 /* 0x55 - 1280x720@60Hz */ 353 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 354 1430, 1650, 0, 720, 725, 730, 750, 0, 355 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 356 /* 0x16 - 1280x768@60Hz RB */ 357 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 358 1360, 1440, 0, 768, 771, 778, 790, 0, 359 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 360 /* 0x17 - 1280x768@60Hz */ 361 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 362 1472, 1664, 0, 768, 771, 778, 798, 0, 363 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 364 /* 0x18 - 1280x768@75Hz */ 365 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 366 1488, 1696, 0, 768, 771, 778, 805, 0, 367 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 368 /* 0x19 - 1280x768@85Hz */ 369 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 370 1496, 1712, 0, 768, 771, 778, 809, 0, 371 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 372 /* 0x1a - 1280x768@120Hz RB */ 373 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 374 1360, 1440, 0, 768, 771, 778, 813, 0, 375 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 376 /* 0x1b - 1280x800@60Hz RB */ 377 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 378 1360, 1440, 0, 800, 803, 809, 823, 0, 379 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 380 /* 0x1c - 1280x800@60Hz */ 381 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 382 1480, 1680, 0, 800, 803, 809, 831, 0, 383 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 384 /* 0x1d - 1280x800@75Hz */ 385 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 386 1488, 1696, 0, 800, 803, 809, 838, 0, 387 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 388 /* 0x1e - 1280x800@85Hz */ 389 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 390 1496, 1712, 0, 800, 803, 809, 843, 0, 391 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 392 /* 0x1f - 1280x800@120Hz RB */ 393 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 394 1360, 1440, 0, 800, 803, 809, 847, 0, 395 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 396 /* 0x20 - 1280x960@60Hz */ 397 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 398 1488, 1800, 0, 960, 961, 964, 1000, 0, 399 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 400 /* 0x21 - 1280x960@85Hz */ 401 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 402 1504, 1728, 0, 960, 961, 964, 1011, 0, 403 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 404 /* 0x22 - 1280x960@120Hz RB */ 405 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 406 1360, 1440, 0, 960, 963, 967, 1017, 0, 407 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 408 /* 0x23 - 1280x1024@60Hz */ 409 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 410 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 411 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 412 /* 0x24 - 1280x1024@75Hz */ 413 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 414 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 415 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 416 /* 0x25 - 1280x1024@85Hz */ 417 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 418 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 419 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 420 /* 0x26 - 1280x1024@120Hz RB */ 421 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 422 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 423 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 424 /* 0x27 - 1360x768@60Hz */ 425 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 426 1536, 1792, 0, 768, 771, 777, 795, 0, 427 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 428 /* 0x28 - 1360x768@120Hz RB */ 429 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 430 1440, 1520, 0, 768, 771, 776, 813, 0, 431 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 432 /* 0x51 - 1366x768@60Hz */ 433 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 434 1579, 1792, 0, 768, 771, 774, 798, 0, 435 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 436 /* 0x56 - 1366x768@60Hz */ 437 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 438 1436, 1500, 0, 768, 769, 772, 800, 0, 439 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 440 /* 0x29 - 1400x1050@60Hz RB */ 441 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 442 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 443 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 444 /* 0x2a - 1400x1050@60Hz */ 445 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 446 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 447 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 448 /* 0x2b - 1400x1050@75Hz */ 449 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 450 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 451 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 452 /* 0x2c - 1400x1050@85Hz */ 453 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 454 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 455 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 456 /* 0x2d - 1400x1050@120Hz RB */ 457 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 458 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 459 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 460 /* 0x2e - 1440x900@60Hz RB */ 461 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 462 1520, 1600, 0, 900, 903, 909, 926, 0, 463 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 464 /* 0x2f - 1440x900@60Hz */ 465 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 466 1672, 1904, 0, 900, 903, 909, 934, 0, 467 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 468 /* 0x30 - 1440x900@75Hz */ 469 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 470 1688, 1936, 0, 900, 903, 909, 942, 0, 471 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 472 /* 0x31 - 1440x900@85Hz */ 473 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 474 1696, 1952, 0, 900, 903, 909, 948, 0, 475 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 476 /* 0x32 - 1440x900@120Hz RB */ 477 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 478 1520, 1600, 0, 900, 903, 909, 953, 0, 479 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 480 /* 0x53 - 1600x900@60Hz */ 481 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 482 1704, 1800, 0, 900, 901, 904, 1000, 0, 483 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 484 /* 0x33 - 1600x1200@60Hz */ 485 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 486 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 487 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 488 /* 0x34 - 1600x1200@65Hz */ 489 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 490 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 491 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 492 /* 0x35 - 1600x1200@70Hz */ 493 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 494 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 495 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 496 /* 0x36 - 1600x1200@75Hz */ 497 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 498 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 499 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 500 /* 0x37 - 1600x1200@85Hz */ 501 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 502 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 503 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 504 /* 0x38 - 1600x1200@120Hz RB */ 505 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 506 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 507 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 508 /* 0x39 - 1680x1050@60Hz RB */ 509 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 510 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 511 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 512 /* 0x3a - 1680x1050@60Hz */ 513 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 514 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 515 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 516 /* 0x3b - 1680x1050@75Hz */ 517 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 518 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 519 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 520 /* 0x3c - 1680x1050@85Hz */ 521 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 522 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 523 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 524 /* 0x3d - 1680x1050@120Hz RB */ 525 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 526 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 527 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 528 /* 0x3e - 1792x1344@60Hz */ 529 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 530 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 531 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 532 /* 0x3f - 1792x1344@75Hz */ 533 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 534 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 535 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 536 /* 0x40 - 1792x1344@120Hz RB */ 537 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 538 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 539 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 540 /* 0x41 - 1856x1392@60Hz */ 541 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 542 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 543 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 544 /* 0x42 - 1856x1392@75Hz */ 545 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 546 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 547 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 548 /* 0x43 - 1856x1392@120Hz RB */ 549 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 550 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 551 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 552 /* 0x52 - 1920x1080@60Hz */ 553 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 554 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 555 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 556 /* 0x44 - 1920x1200@60Hz RB */ 557 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 558 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 559 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 560 /* 0x45 - 1920x1200@60Hz */ 561 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 562 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 563 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 564 /* 0x46 - 1920x1200@75Hz */ 565 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 566 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 567 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 568 /* 0x47 - 1920x1200@85Hz */ 569 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 570 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 571 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 572 /* 0x48 - 1920x1200@120Hz RB */ 573 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 574 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 575 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 576 /* 0x49 - 1920x1440@60Hz */ 577 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 578 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 579 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 580 /* 0x4a - 1920x1440@75Hz */ 581 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 582 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 583 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 584 /* 0x4b - 1920x1440@120Hz RB */ 585 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 586 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 587 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 588 /* 0x54 - 2048x1152@60Hz */ 589 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 590 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 591 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 592 /* 0x4c - 2560x1600@60Hz RB */ 593 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 594 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 595 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 596 /* 0x4d - 2560x1600@60Hz */ 597 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 598 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 599 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 600 /* 0x4e - 2560x1600@75Hz */ 601 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 602 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 603 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 604 /* 0x4f - 2560x1600@85Hz */ 605 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 606 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 607 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 608 /* 0x50 - 2560x1600@120Hz RB */ 609 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 610 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 611 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 612 /* 0x57 - 4096x2160@60Hz RB */ 613 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 614 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 615 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 616 /* 0x58 - 4096x2160@59.94Hz RB */ 617 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 618 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 619 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 620 }; 621 622 /* 623 * These more or less come from the DMT spec. The 720x400 modes are 624 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 625 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 626 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 627 * mode. 628 * 629 * The DMT modes have been fact-checked; the rest are mild guesses. 630 */ 631 static const struct drm_display_mode edid_est_modes[] = { 632 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 633 968, 1056, 0, 600, 601, 605, 628, 0, 634 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 635 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 636 896, 1024, 0, 600, 601, 603, 625, 0, 637 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 638 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 639 720, 840, 0, 480, 481, 484, 500, 0, 640 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 641 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 642 704, 832, 0, 480, 489, 492, 520, 0, 643 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 644 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 645 768, 864, 0, 480, 483, 486, 525, 0, 646 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 647 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 648 752, 800, 0, 480, 490, 492, 525, 0, 649 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 650 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 651 846, 900, 0, 400, 421, 423, 449, 0, 652 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 653 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 654 846, 900, 0, 400, 412, 414, 449, 0, 655 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 656 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 657 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 658 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 659 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 660 1136, 1312, 0, 768, 769, 772, 800, 0, 661 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 662 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 663 1184, 1328, 0, 768, 771, 777, 806, 0, 664 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 665 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 666 1184, 1344, 0, 768, 771, 777, 806, 0, 667 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 668 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 669 1208, 1264, 0, 768, 768, 776, 817, 0, 670 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 671 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 672 928, 1152, 0, 624, 625, 628, 667, 0, 673 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 674 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 675 896, 1056, 0, 600, 601, 604, 625, 0, 676 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 677 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 678 976, 1040, 0, 600, 637, 643, 666, 0, 679 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 680 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 681 1344, 1600, 0, 864, 865, 868, 900, 0, 682 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 683 }; 684 685 struct minimode { 686 short w; 687 short h; 688 short r; 689 short rb; 690 }; 691 692 static const struct minimode est3_modes[] = { 693 /* byte 6 */ 694 { 640, 350, 85, 0 }, 695 { 640, 400, 85, 0 }, 696 { 720, 400, 85, 0 }, 697 { 640, 480, 85, 0 }, 698 { 848, 480, 60, 0 }, 699 { 800, 600, 85, 0 }, 700 { 1024, 768, 85, 0 }, 701 { 1152, 864, 75, 0 }, 702 /* byte 7 */ 703 { 1280, 768, 60, 1 }, 704 { 1280, 768, 60, 0 }, 705 { 1280, 768, 75, 0 }, 706 { 1280, 768, 85, 0 }, 707 { 1280, 960, 60, 0 }, 708 { 1280, 960, 85, 0 }, 709 { 1280, 1024, 60, 0 }, 710 { 1280, 1024, 85, 0 }, 711 /* byte 8 */ 712 { 1360, 768, 60, 0 }, 713 { 1440, 900, 60, 1 }, 714 { 1440, 900, 60, 0 }, 715 { 1440, 900, 75, 0 }, 716 { 1440, 900, 85, 0 }, 717 { 1400, 1050, 60, 1 }, 718 { 1400, 1050, 60, 0 }, 719 { 1400, 1050, 75, 0 }, 720 /* byte 9 */ 721 { 1400, 1050, 85, 0 }, 722 { 1680, 1050, 60, 1 }, 723 { 1680, 1050, 60, 0 }, 724 { 1680, 1050, 75, 0 }, 725 { 1680, 1050, 85, 0 }, 726 { 1600, 1200, 60, 0 }, 727 { 1600, 1200, 65, 0 }, 728 { 1600, 1200, 70, 0 }, 729 /* byte 10 */ 730 { 1600, 1200, 75, 0 }, 731 { 1600, 1200, 85, 0 }, 732 { 1792, 1344, 60, 0 }, 733 { 1792, 1344, 75, 0 }, 734 { 1856, 1392, 60, 0 }, 735 { 1856, 1392, 75, 0 }, 736 { 1920, 1200, 60, 1 }, 737 { 1920, 1200, 60, 0 }, 738 /* byte 11 */ 739 { 1920, 1200, 75, 0 }, 740 { 1920, 1200, 85, 0 }, 741 { 1920, 1440, 60, 0 }, 742 { 1920, 1440, 75, 0 }, 743 }; 744 745 static const struct minimode extra_modes[] = { 746 { 1024, 576, 60, 0 }, 747 { 1366, 768, 60, 0 }, 748 { 1600, 900, 60, 0 }, 749 { 1680, 945, 60, 0 }, 750 { 1920, 1080, 60, 0 }, 751 { 2048, 1152, 60, 0 }, 752 { 2048, 1536, 60, 0 }, 753 }; 754 755 /* 756 * From CEA/CTA-861 spec. 757 * 758 * Do not access directly, instead always use cea_mode_for_vic(). 759 */ 760 static const struct drm_display_mode edid_cea_modes_1[] = { 761 /* 1 - 640x480@60Hz 4:3 */ 762 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 763 752, 800, 0, 480, 490, 492, 525, 0, 764 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 765 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 766 /* 2 - 720x480@60Hz 4:3 */ 767 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 768 798, 858, 0, 480, 489, 495, 525, 0, 769 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 770 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 771 /* 3 - 720x480@60Hz 16:9 */ 772 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 773 798, 858, 0, 480, 489, 495, 525, 0, 774 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 775 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 776 /* 4 - 1280x720@60Hz 16:9 */ 777 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 778 1430, 1650, 0, 720, 725, 730, 750, 0, 779 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 780 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 781 /* 5 - 1920x1080i@60Hz 16:9 */ 782 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 783 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 784 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 785 DRM_MODE_FLAG_INTERLACE), 786 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 787 /* 6 - 720(1440)x480i@60Hz 4:3 */ 788 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 789 801, 858, 0, 480, 488, 494, 525, 0, 790 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 791 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 792 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 793 /* 7 - 720(1440)x480i@60Hz 16:9 */ 794 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 795 801, 858, 0, 480, 488, 494, 525, 0, 796 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 797 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 798 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 799 /* 8 - 720(1440)x240@60Hz 4:3 */ 800 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 801 801, 858, 0, 240, 244, 247, 262, 0, 802 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 803 DRM_MODE_FLAG_DBLCLK), 804 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 805 /* 9 - 720(1440)x240@60Hz 16:9 */ 806 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 807 801, 858, 0, 240, 244, 247, 262, 0, 808 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 809 DRM_MODE_FLAG_DBLCLK), 810 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 811 /* 10 - 2880x480i@60Hz 4:3 */ 812 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 813 3204, 3432, 0, 480, 488, 494, 525, 0, 814 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 815 DRM_MODE_FLAG_INTERLACE), 816 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 817 /* 11 - 2880x480i@60Hz 16:9 */ 818 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 819 3204, 3432, 0, 480, 488, 494, 525, 0, 820 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 821 DRM_MODE_FLAG_INTERLACE), 822 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 823 /* 12 - 2880x240@60Hz 4:3 */ 824 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 825 3204, 3432, 0, 240, 244, 247, 262, 0, 826 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 827 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 828 /* 13 - 2880x240@60Hz 16:9 */ 829 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 830 3204, 3432, 0, 240, 244, 247, 262, 0, 831 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 832 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 833 /* 14 - 1440x480@60Hz 4:3 */ 834 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 835 1596, 1716, 0, 480, 489, 495, 525, 0, 836 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 837 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 838 /* 15 - 1440x480@60Hz 16:9 */ 839 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 840 1596, 1716, 0, 480, 489, 495, 525, 0, 841 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 842 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 843 /* 16 - 1920x1080@60Hz 16:9 */ 844 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 845 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 846 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 847 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 848 /* 17 - 720x576@50Hz 4:3 */ 849 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 850 796, 864, 0, 576, 581, 586, 625, 0, 851 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 852 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 853 /* 18 - 720x576@50Hz 16:9 */ 854 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 855 796, 864, 0, 576, 581, 586, 625, 0, 856 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 857 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 858 /* 19 - 1280x720@50Hz 16:9 */ 859 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 860 1760, 1980, 0, 720, 725, 730, 750, 0, 861 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 862 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 863 /* 20 - 1920x1080i@50Hz 16:9 */ 864 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 865 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 866 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 867 DRM_MODE_FLAG_INTERLACE), 868 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 869 /* 21 - 720(1440)x576i@50Hz 4:3 */ 870 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 871 795, 864, 0, 576, 580, 586, 625, 0, 872 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 873 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 874 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 875 /* 22 - 720(1440)x576i@50Hz 16:9 */ 876 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 877 795, 864, 0, 576, 580, 586, 625, 0, 878 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 879 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 880 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 881 /* 23 - 720(1440)x288@50Hz 4:3 */ 882 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 883 795, 864, 0, 288, 290, 293, 312, 0, 884 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 885 DRM_MODE_FLAG_DBLCLK), 886 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 887 /* 24 - 720(1440)x288@50Hz 16:9 */ 888 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 889 795, 864, 0, 288, 290, 293, 312, 0, 890 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 891 DRM_MODE_FLAG_DBLCLK), 892 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 893 /* 25 - 2880x576i@50Hz 4:3 */ 894 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 895 3180, 3456, 0, 576, 580, 586, 625, 0, 896 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 897 DRM_MODE_FLAG_INTERLACE), 898 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 899 /* 26 - 2880x576i@50Hz 16:9 */ 900 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 901 3180, 3456, 0, 576, 580, 586, 625, 0, 902 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 903 DRM_MODE_FLAG_INTERLACE), 904 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 905 /* 27 - 2880x288@50Hz 4:3 */ 906 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 907 3180, 3456, 0, 288, 290, 293, 312, 0, 908 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 909 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 910 /* 28 - 2880x288@50Hz 16:9 */ 911 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 912 3180, 3456, 0, 288, 290, 293, 312, 0, 913 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 914 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 915 /* 29 - 1440x576@50Hz 4:3 */ 916 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 917 1592, 1728, 0, 576, 581, 586, 625, 0, 918 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 919 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 920 /* 30 - 1440x576@50Hz 16:9 */ 921 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 922 1592, 1728, 0, 576, 581, 586, 625, 0, 923 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 924 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 925 /* 31 - 1920x1080@50Hz 16:9 */ 926 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 927 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 928 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 929 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 930 /* 32 - 1920x1080@24Hz 16:9 */ 931 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 932 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 933 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 934 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 935 /* 33 - 1920x1080@25Hz 16:9 */ 936 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 937 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 938 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 939 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 940 /* 34 - 1920x1080@30Hz 16:9 */ 941 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 942 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 943 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 944 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 945 /* 35 - 2880x480@60Hz 4:3 */ 946 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 947 3192, 3432, 0, 480, 489, 495, 525, 0, 948 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 949 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 950 /* 36 - 2880x480@60Hz 16:9 */ 951 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 952 3192, 3432, 0, 480, 489, 495, 525, 0, 953 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 954 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 955 /* 37 - 2880x576@50Hz 4:3 */ 956 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 957 3184, 3456, 0, 576, 581, 586, 625, 0, 958 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 959 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 960 /* 38 - 2880x576@50Hz 16:9 */ 961 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 962 3184, 3456, 0, 576, 581, 586, 625, 0, 963 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 964 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 965 /* 39 - 1920x1080i@50Hz 16:9 */ 966 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 967 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 968 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 969 DRM_MODE_FLAG_INTERLACE), 970 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 971 /* 40 - 1920x1080i@100Hz 16:9 */ 972 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 973 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 974 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 975 DRM_MODE_FLAG_INTERLACE), 976 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 977 /* 41 - 1280x720@100Hz 16:9 */ 978 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 979 1760, 1980, 0, 720, 725, 730, 750, 0, 980 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 981 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 982 /* 42 - 720x576@100Hz 4:3 */ 983 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 984 796, 864, 0, 576, 581, 586, 625, 0, 985 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 986 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 987 /* 43 - 720x576@100Hz 16:9 */ 988 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 989 796, 864, 0, 576, 581, 586, 625, 0, 990 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 991 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 992 /* 44 - 720(1440)x576i@100Hz 4:3 */ 993 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 994 795, 864, 0, 576, 580, 586, 625, 0, 995 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 996 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 997 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 998 /* 45 - 720(1440)x576i@100Hz 16:9 */ 999 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 1000 795, 864, 0, 576, 580, 586, 625, 0, 1001 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1002 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1003 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1004 /* 46 - 1920x1080i@120Hz 16:9 */ 1005 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1006 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 1007 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 1008 DRM_MODE_FLAG_INTERLACE), 1009 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1010 /* 47 - 1280x720@120Hz 16:9 */ 1011 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1012 1430, 1650, 0, 720, 725, 730, 750, 0, 1013 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1014 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1015 /* 48 - 720x480@120Hz 4:3 */ 1016 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 1017 798, 858, 0, 480, 489, 495, 525, 0, 1018 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1019 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1020 /* 49 - 720x480@120Hz 16:9 */ 1021 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 1022 798, 858, 0, 480, 489, 495, 525, 0, 1023 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1024 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1025 /* 50 - 720(1440)x480i@120Hz 4:3 */ 1026 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 1027 801, 858, 0, 480, 488, 494, 525, 0, 1028 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1029 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1030 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1031 /* 51 - 720(1440)x480i@120Hz 16:9 */ 1032 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 1033 801, 858, 0, 480, 488, 494, 525, 0, 1034 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1035 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1036 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1037 /* 52 - 720x576@200Hz 4:3 */ 1038 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1039 796, 864, 0, 576, 581, 586, 625, 0, 1040 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1041 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1042 /* 53 - 720x576@200Hz 16:9 */ 1043 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1044 796, 864, 0, 576, 581, 586, 625, 0, 1045 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1046 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1047 /* 54 - 720(1440)x576i@200Hz 4:3 */ 1048 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1049 795, 864, 0, 576, 580, 586, 625, 0, 1050 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1051 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1052 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1053 /* 55 - 720(1440)x576i@200Hz 16:9 */ 1054 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1055 795, 864, 0, 576, 580, 586, 625, 0, 1056 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1057 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1058 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1059 /* 56 - 720x480@240Hz 4:3 */ 1060 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1061 798, 858, 0, 480, 489, 495, 525, 0, 1062 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1063 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1064 /* 57 - 720x480@240Hz 16:9 */ 1065 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1066 798, 858, 0, 480, 489, 495, 525, 0, 1067 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1068 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1069 /* 58 - 720(1440)x480i@240Hz 4:3 */ 1070 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1071 801, 858, 0, 480, 488, 494, 525, 0, 1072 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1073 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1074 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1075 /* 59 - 720(1440)x480i@240Hz 16:9 */ 1076 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1077 801, 858, 0, 480, 488, 494, 525, 0, 1078 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1079 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1080 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1081 /* 60 - 1280x720@24Hz 16:9 */ 1082 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1083 3080, 3300, 0, 720, 725, 730, 750, 0, 1084 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1085 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1086 /* 61 - 1280x720@25Hz 16:9 */ 1087 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1088 3740, 3960, 0, 720, 725, 730, 750, 0, 1089 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1090 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1091 /* 62 - 1280x720@30Hz 16:9 */ 1092 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1093 3080, 3300, 0, 720, 725, 730, 750, 0, 1094 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1095 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1096 /* 63 - 1920x1080@120Hz 16:9 */ 1097 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1098 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1099 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1100 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1101 /* 64 - 1920x1080@100Hz 16:9 */ 1102 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1103 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1104 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1105 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1106 /* 65 - 1280x720@24Hz 64:27 */ 1107 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1108 3080, 3300, 0, 720, 725, 730, 750, 0, 1109 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1110 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1111 /* 66 - 1280x720@25Hz 64:27 */ 1112 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1113 3740, 3960, 0, 720, 725, 730, 750, 0, 1114 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1115 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1116 /* 67 - 1280x720@30Hz 64:27 */ 1117 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1118 3080, 3300, 0, 720, 725, 730, 750, 0, 1119 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1120 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1121 /* 68 - 1280x720@50Hz 64:27 */ 1122 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1123 1760, 1980, 0, 720, 725, 730, 750, 0, 1124 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1125 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1126 /* 69 - 1280x720@60Hz 64:27 */ 1127 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1128 1430, 1650, 0, 720, 725, 730, 750, 0, 1129 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1130 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1131 /* 70 - 1280x720@100Hz 64:27 */ 1132 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1133 1760, 1980, 0, 720, 725, 730, 750, 0, 1134 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1135 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1136 /* 71 - 1280x720@120Hz 64:27 */ 1137 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1138 1430, 1650, 0, 720, 725, 730, 750, 0, 1139 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1140 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1141 /* 72 - 1920x1080@24Hz 64:27 */ 1142 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1143 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1144 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1145 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1146 /* 73 - 1920x1080@25Hz 64:27 */ 1147 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1148 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1149 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1150 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1151 /* 74 - 1920x1080@30Hz 64:27 */ 1152 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1153 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1154 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1155 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1156 /* 75 - 1920x1080@50Hz 64:27 */ 1157 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1158 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1159 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1160 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1161 /* 76 - 1920x1080@60Hz 64:27 */ 1162 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1163 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1164 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1165 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1166 /* 77 - 1920x1080@100Hz 64:27 */ 1167 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1168 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1169 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1170 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1171 /* 78 - 1920x1080@120Hz 64:27 */ 1172 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1173 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1174 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1175 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1176 /* 79 - 1680x720@24Hz 64:27 */ 1177 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 1178 3080, 3300, 0, 720, 725, 730, 750, 0, 1179 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1180 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1181 /* 80 - 1680x720@25Hz 64:27 */ 1182 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 1183 2948, 3168, 0, 720, 725, 730, 750, 0, 1184 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1185 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1186 /* 81 - 1680x720@30Hz 64:27 */ 1187 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 1188 2420, 2640, 0, 720, 725, 730, 750, 0, 1189 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1190 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1191 /* 82 - 1680x720@50Hz 64:27 */ 1192 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1193 1980, 2200, 0, 720, 725, 730, 750, 0, 1194 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1195 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1196 /* 83 - 1680x720@60Hz 64:27 */ 1197 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1198 1980, 2200, 0, 720, 725, 730, 750, 0, 1199 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1200 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1201 /* 84 - 1680x720@100Hz 64:27 */ 1202 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1203 1780, 2000, 0, 720, 725, 730, 825, 0, 1204 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1205 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1206 /* 85 - 1680x720@120Hz 64:27 */ 1207 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1208 1780, 2000, 0, 720, 725, 730, 825, 0, 1209 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1210 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1211 /* 86 - 2560x1080@24Hz 64:27 */ 1212 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 1213 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1214 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1215 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1216 /* 87 - 2560x1080@25Hz 64:27 */ 1217 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 1218 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, 1219 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1220 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1221 /* 88 - 2560x1080@30Hz 64:27 */ 1222 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 1223 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, 1224 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1225 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1226 /* 89 - 2560x1080@50Hz 64:27 */ 1227 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 1228 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, 1229 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1230 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1231 /* 90 - 2560x1080@60Hz 64:27 */ 1232 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 1233 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, 1234 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1235 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1236 /* 91 - 2560x1080@100Hz 64:27 */ 1237 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 1238 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, 1239 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1240 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1241 /* 92 - 2560x1080@120Hz 64:27 */ 1242 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 1243 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, 1244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1245 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1246 /* 93 - 3840x2160@24Hz 16:9 */ 1247 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1248 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1249 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1250 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1251 /* 94 - 3840x2160@25Hz 16:9 */ 1252 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1253 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1254 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1255 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1256 /* 95 - 3840x2160@30Hz 16:9 */ 1257 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1258 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1260 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1261 /* 96 - 3840x2160@50Hz 16:9 */ 1262 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1263 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1265 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1266 /* 97 - 3840x2160@60Hz 16:9 */ 1267 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1268 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1269 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1270 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1271 /* 98 - 4096x2160@24Hz 256:135 */ 1272 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1273 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1274 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1275 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1276 /* 99 - 4096x2160@25Hz 256:135 */ 1277 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1278 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1280 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1281 /* 100 - 4096x2160@30Hz 256:135 */ 1282 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1283 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1285 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1286 /* 101 - 4096x2160@50Hz 256:135 */ 1287 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1288 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1289 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1290 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1291 /* 102 - 4096x2160@60Hz 256:135 */ 1292 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1293 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1294 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1295 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1296 /* 103 - 3840x2160@24Hz 64:27 */ 1297 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1298 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1300 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1301 /* 104 - 3840x2160@25Hz 64:27 */ 1302 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1303 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1304 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1305 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1306 /* 105 - 3840x2160@30Hz 64:27 */ 1307 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1308 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1310 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1311 /* 106 - 3840x2160@50Hz 64:27 */ 1312 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1313 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1314 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1315 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1316 /* 107 - 3840x2160@60Hz 64:27 */ 1317 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1318 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1319 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1320 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1321 /* 108 - 1280x720@48Hz 16:9 */ 1322 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1323 2280, 2500, 0, 720, 725, 730, 750, 0, 1324 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1325 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1326 /* 109 - 1280x720@48Hz 64:27 */ 1327 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1328 2280, 2500, 0, 720, 725, 730, 750, 0, 1329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1330 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1331 /* 110 - 1680x720@48Hz 64:27 */ 1332 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490, 1333 2530, 2750, 0, 720, 725, 730, 750, 0, 1334 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1335 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1336 /* 111 - 1920x1080@48Hz 16:9 */ 1337 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1338 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1339 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1340 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1341 /* 112 - 1920x1080@48Hz 64:27 */ 1342 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1343 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1344 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1345 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1346 /* 113 - 2560x1080@48Hz 64:27 */ 1347 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558, 1348 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1349 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1350 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1351 /* 114 - 3840x2160@48Hz 16:9 */ 1352 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1353 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1354 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1355 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1356 /* 115 - 4096x2160@48Hz 256:135 */ 1357 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116, 1358 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1359 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1360 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1361 /* 116 - 3840x2160@48Hz 64:27 */ 1362 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1363 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1364 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1365 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1366 /* 117 - 3840x2160@100Hz 16:9 */ 1367 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1368 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1370 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1371 /* 118 - 3840x2160@120Hz 16:9 */ 1372 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1373 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1374 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1375 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1376 /* 119 - 3840x2160@100Hz 64:27 */ 1377 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1378 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1379 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1380 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1381 /* 120 - 3840x2160@120Hz 64:27 */ 1382 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1383 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1385 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1386 /* 121 - 5120x2160@24Hz 64:27 */ 1387 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116, 1388 7204, 7500, 0, 2160, 2168, 2178, 2200, 0, 1389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1390 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1391 /* 122 - 5120x2160@25Hz 64:27 */ 1392 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816, 1393 6904, 7200, 0, 2160, 2168, 2178, 2200, 0, 1394 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1395 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1396 /* 123 - 5120x2160@30Hz 64:27 */ 1397 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784, 1398 5872, 6000, 0, 2160, 2168, 2178, 2200, 0, 1399 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1400 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1401 /* 124 - 5120x2160@48Hz 64:27 */ 1402 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866, 1403 5954, 6250, 0, 2160, 2168, 2178, 2475, 0, 1404 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1405 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1406 /* 125 - 5120x2160@50Hz 64:27 */ 1407 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216, 1408 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1409 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1410 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1411 /* 126 - 5120x2160@60Hz 64:27 */ 1412 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284, 1413 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1414 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1415 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1416 /* 127 - 5120x2160@100Hz 64:27 */ 1417 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216, 1418 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1419 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1420 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1421 }; 1422 1423 /* 1424 * From CEA/CTA-861 spec. 1425 * 1426 * Do not access directly, instead always use cea_mode_for_vic(). 1427 */ 1428 static const struct drm_display_mode edid_cea_modes_193[] = { 1429 /* 193 - 5120x2160@120Hz 64:27 */ 1430 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284, 1431 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1432 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1433 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1434 /* 194 - 7680x4320@24Hz 16:9 */ 1435 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1436 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1438 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1439 /* 195 - 7680x4320@25Hz 16:9 */ 1440 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1441 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1442 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1443 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1444 /* 196 - 7680x4320@30Hz 16:9 */ 1445 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1446 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1447 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1448 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1449 /* 197 - 7680x4320@48Hz 16:9 */ 1450 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1451 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1452 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1453 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1454 /* 198 - 7680x4320@50Hz 16:9 */ 1455 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1456 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1458 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1459 /* 199 - 7680x4320@60Hz 16:9 */ 1460 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1461 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1462 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1463 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1464 /* 200 - 7680x4320@100Hz 16:9 */ 1465 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1466 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1467 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1468 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1469 /* 201 - 7680x4320@120Hz 16:9 */ 1470 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1471 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1472 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1473 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1474 /* 202 - 7680x4320@24Hz 64:27 */ 1475 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1476 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1478 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1479 /* 203 - 7680x4320@25Hz 64:27 */ 1480 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1481 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1482 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1483 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1484 /* 204 - 7680x4320@30Hz 64:27 */ 1485 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1486 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1487 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1488 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1489 /* 205 - 7680x4320@48Hz 64:27 */ 1490 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1491 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1492 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1493 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1494 /* 206 - 7680x4320@50Hz 64:27 */ 1495 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1496 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1497 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1498 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1499 /* 207 - 7680x4320@60Hz 64:27 */ 1500 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1501 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1502 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1503 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1504 /* 208 - 7680x4320@100Hz 64:27 */ 1505 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1506 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1507 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1508 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1509 /* 209 - 7680x4320@120Hz 64:27 */ 1510 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1511 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1512 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1513 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1514 /* 210 - 10240x4320@24Hz 64:27 */ 1515 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732, 1516 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1518 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1519 /* 211 - 10240x4320@25Hz 64:27 */ 1520 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732, 1521 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1522 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1523 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1524 /* 212 - 10240x4320@30Hz 64:27 */ 1525 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528, 1526 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1527 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1528 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1529 /* 213 - 10240x4320@48Hz 64:27 */ 1530 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732, 1531 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1532 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1533 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1534 /* 214 - 10240x4320@50Hz 64:27 */ 1535 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732, 1536 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1537 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1538 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1539 /* 215 - 10240x4320@60Hz 64:27 */ 1540 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528, 1541 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1542 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1543 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1544 /* 216 - 10240x4320@100Hz 64:27 */ 1545 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432, 1546 12608, 13200, 0, 4320, 4336, 4356, 4500, 0, 1547 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1548 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1549 /* 217 - 10240x4320@120Hz 64:27 */ 1550 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528, 1551 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1553 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1554 /* 218 - 4096x2160@100Hz 256:135 */ 1555 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896, 1556 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1557 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1558 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1559 /* 219 - 4096x2160@120Hz 256:135 */ 1560 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184, 1561 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1562 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1563 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1564 }; 1565 1566 /* 1567 * HDMI 1.4 4k modes. Index using the VIC. 1568 */ 1569 static const struct drm_display_mode edid_4k_modes[] = { 1570 /* 0 - dummy, VICs start at 1 */ 1571 { }, 1572 /* 1 - 3840x2160@30Hz */ 1573 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1574 3840, 4016, 4104, 4400, 0, 1575 2160, 2168, 2178, 2250, 0, 1576 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1577 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1578 /* 2 - 3840x2160@25Hz */ 1579 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1580 3840, 4896, 4984, 5280, 0, 1581 2160, 2168, 2178, 2250, 0, 1582 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1583 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1584 /* 3 - 3840x2160@24Hz */ 1585 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1586 3840, 5116, 5204, 5500, 0, 1587 2160, 2168, 2178, 2250, 0, 1588 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1589 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1590 /* 4 - 4096x2160@24Hz (SMPTE) */ 1591 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1592 4096, 5116, 5204, 5500, 0, 1593 2160, 2168, 2178, 2250, 0, 1594 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1595 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1596 }; 1597 1598 /*** DDC fetch and block validation ***/ 1599 1600 /* 1601 * The opaque EDID type, internal to drm_edid.c. 1602 */ 1603 struct drm_edid { 1604 /* Size allocated for edid */ 1605 size_t size; 1606 const struct edid *edid; 1607 }; 1608 1609 static int edid_hfeeodb_extension_block_count(const struct edid *edid); 1610 1611 static int edid_hfeeodb_block_count(const struct edid *edid) 1612 { 1613 int eeodb = edid_hfeeodb_extension_block_count(edid); 1614 1615 return eeodb ? eeodb + 1 : 0; 1616 } 1617 1618 static int edid_extension_block_count(const struct edid *edid) 1619 { 1620 return edid->extensions; 1621 } 1622 1623 static int edid_block_count(const struct edid *edid) 1624 { 1625 return edid_extension_block_count(edid) + 1; 1626 } 1627 1628 static int edid_size_by_blocks(int num_blocks) 1629 { 1630 return num_blocks * EDID_LENGTH; 1631 } 1632 1633 static int edid_size(const struct edid *edid) 1634 { 1635 return edid_size_by_blocks(edid_block_count(edid)); 1636 } 1637 1638 static const void *edid_block_data(const struct edid *edid, int index) 1639 { 1640 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH); 1641 1642 return edid + index; 1643 } 1644 1645 static const void *edid_extension_block_data(const struct edid *edid, int index) 1646 { 1647 return edid_block_data(edid, index + 1); 1648 } 1649 1650 /* EDID block count indicated in EDID, may exceed allocated size */ 1651 static int __drm_edid_block_count(const struct drm_edid *drm_edid) 1652 { 1653 int num_blocks; 1654 1655 /* Starting point */ 1656 num_blocks = edid_block_count(drm_edid->edid); 1657 1658 /* HF-EEODB override */ 1659 if (drm_edid->size >= edid_size_by_blocks(2)) { 1660 int eeodb; 1661 1662 /* 1663 * Note: HF-EEODB may specify a smaller extension count than the 1664 * regular one. Unlike in buffer allocation, here we can use it. 1665 */ 1666 eeodb = edid_hfeeodb_block_count(drm_edid->edid); 1667 if (eeodb) 1668 num_blocks = eeodb; 1669 } 1670 1671 return num_blocks; 1672 } 1673 1674 /* EDID block count, limited by allocated size */ 1675 static int drm_edid_block_count(const struct drm_edid *drm_edid) 1676 { 1677 /* Limit by allocated size */ 1678 return min(__drm_edid_block_count(drm_edid), 1679 (int)drm_edid->size / EDID_LENGTH); 1680 } 1681 1682 /* EDID extension block count, limited by allocated size */ 1683 static int drm_edid_extension_block_count(const struct drm_edid *drm_edid) 1684 { 1685 return drm_edid_block_count(drm_edid) - 1; 1686 } 1687 1688 static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index) 1689 { 1690 return edid_block_data(drm_edid->edid, index); 1691 } 1692 1693 static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid, 1694 int index) 1695 { 1696 return edid_extension_block_data(drm_edid->edid, index); 1697 } 1698 1699 /* 1700 * Initializer helper for legacy interfaces, where we have no choice but to 1701 * trust edid size. Not for general purpose use. 1702 */ 1703 static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid, 1704 const struct edid *edid) 1705 { 1706 if (!edid) 1707 return NULL; 1708 1709 memset(drm_edid, 0, sizeof(*drm_edid)); 1710 1711 drm_edid->edid = edid; 1712 drm_edid->size = edid_size(edid); 1713 1714 return drm_edid; 1715 } 1716 1717 /* 1718 * EDID base and extension block iterator. 1719 * 1720 * struct drm_edid_iter iter; 1721 * const u8 *block; 1722 * 1723 * drm_edid_iter_begin(drm_edid, &iter); 1724 * drm_edid_iter_for_each(block, &iter) { 1725 * // do stuff with block 1726 * } 1727 * drm_edid_iter_end(&iter); 1728 */ 1729 struct drm_edid_iter { 1730 const struct drm_edid *drm_edid; 1731 1732 /* Current block index. */ 1733 int index; 1734 }; 1735 1736 static void drm_edid_iter_begin(const struct drm_edid *drm_edid, 1737 struct drm_edid_iter *iter) 1738 { 1739 memset(iter, 0, sizeof(*iter)); 1740 1741 iter->drm_edid = drm_edid; 1742 } 1743 1744 static const void *__drm_edid_iter_next(struct drm_edid_iter *iter) 1745 { 1746 const void *block = NULL; 1747 1748 if (!iter->drm_edid) 1749 return NULL; 1750 1751 if (iter->index < drm_edid_block_count(iter->drm_edid)) 1752 block = drm_edid_block_data(iter->drm_edid, iter->index++); 1753 1754 return block; 1755 } 1756 1757 #define drm_edid_iter_for_each(__block, __iter) \ 1758 while (((__block) = __drm_edid_iter_next(__iter))) 1759 1760 static void drm_edid_iter_end(struct drm_edid_iter *iter) 1761 { 1762 memset(iter, 0, sizeof(*iter)); 1763 } 1764 1765 static const u8 edid_header[] = { 1766 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1767 }; 1768 1769 static void edid_header_fix(void *edid) 1770 { 1771 memcpy(edid, edid_header, sizeof(edid_header)); 1772 } 1773 1774 /** 1775 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1776 * @_edid: pointer to raw base EDID block 1777 * 1778 * Sanity check the header of the base EDID block. 1779 * 1780 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1781 */ 1782 int drm_edid_header_is_valid(const void *_edid) 1783 { 1784 const struct edid *edid = _edid; 1785 int i, score = 0; 1786 1787 for (i = 0; i < sizeof(edid_header); i++) { 1788 if (edid->header[i] == edid_header[i]) 1789 score++; 1790 } 1791 1792 return score; 1793 } 1794 EXPORT_SYMBOL(drm_edid_header_is_valid); 1795 1796 static int edid_fixup __read_mostly = 6; 1797 module_param_named(edid_fixup, edid_fixup, int, 0400); 1798 MODULE_PARM_DESC(edid_fixup, 1799 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1800 1801 static int edid_block_compute_checksum(const void *_block) 1802 { 1803 const u8 *block = _block; 1804 int i; 1805 u8 csum = 0, crc = 0; 1806 1807 for (i = 0; i < EDID_LENGTH - 1; i++) 1808 csum += block[i]; 1809 1810 crc = 0x100 - csum; 1811 1812 return crc; 1813 } 1814 1815 static int edid_block_get_checksum(const void *_block) 1816 { 1817 const struct edid *block = _block; 1818 1819 return block->checksum; 1820 } 1821 1822 static int edid_block_tag(const void *_block) 1823 { 1824 const u8 *block = _block; 1825 1826 return block[0]; 1827 } 1828 1829 static bool edid_block_is_zero(const void *edid) 1830 { 1831 return mem_is_zero(edid, EDID_LENGTH); 1832 } 1833 1834 static bool drm_edid_eq(const struct drm_edid *drm_edid, 1835 const void *raw_edid, size_t raw_edid_size) 1836 { 1837 bool edid1_present = drm_edid && drm_edid->edid && drm_edid->size; 1838 bool edid2_present = raw_edid && raw_edid_size; 1839 1840 if (edid1_present != edid2_present) 1841 return false; 1842 1843 if (edid1_present) { 1844 if (drm_edid->size != raw_edid_size) 1845 return false; 1846 1847 if (memcmp(drm_edid->edid, raw_edid, drm_edid->size)) 1848 return false; 1849 } 1850 1851 return true; 1852 } 1853 1854 enum edid_block_status { 1855 EDID_BLOCK_OK = 0, 1856 EDID_BLOCK_READ_FAIL, 1857 EDID_BLOCK_NULL, 1858 EDID_BLOCK_ZERO, 1859 EDID_BLOCK_HEADER_CORRUPT, 1860 EDID_BLOCK_HEADER_REPAIR, 1861 EDID_BLOCK_HEADER_FIXED, 1862 EDID_BLOCK_CHECKSUM, 1863 EDID_BLOCK_VERSION, 1864 }; 1865 1866 static enum edid_block_status edid_block_check(const void *_block, 1867 bool is_base_block) 1868 { 1869 const struct edid *block = _block; 1870 1871 if (!block) 1872 return EDID_BLOCK_NULL; 1873 1874 if (is_base_block) { 1875 int score = drm_edid_header_is_valid(block); 1876 1877 if (score < clamp(edid_fixup, 0, 8)) { 1878 if (edid_block_is_zero(block)) 1879 return EDID_BLOCK_ZERO; 1880 else 1881 return EDID_BLOCK_HEADER_CORRUPT; 1882 } 1883 1884 if (score < 8) 1885 return EDID_BLOCK_HEADER_REPAIR; 1886 } 1887 1888 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) { 1889 if (edid_block_is_zero(block)) 1890 return EDID_BLOCK_ZERO; 1891 else 1892 return EDID_BLOCK_CHECKSUM; 1893 } 1894 1895 if (is_base_block) { 1896 if (block->version != 1) 1897 return EDID_BLOCK_VERSION; 1898 } 1899 1900 return EDID_BLOCK_OK; 1901 } 1902 1903 static bool edid_block_status_valid(enum edid_block_status status, int tag) 1904 { 1905 return status == EDID_BLOCK_OK || 1906 status == EDID_BLOCK_HEADER_FIXED || 1907 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT); 1908 } 1909 1910 static bool edid_block_valid(const void *block, bool base) 1911 { 1912 return edid_block_status_valid(edid_block_check(block, base), 1913 edid_block_tag(block)); 1914 } 1915 1916 static void edid_block_status_print(enum edid_block_status status, 1917 const struct edid *block, 1918 int block_num) 1919 { 1920 switch (status) { 1921 case EDID_BLOCK_OK: 1922 break; 1923 case EDID_BLOCK_READ_FAIL: 1924 pr_debug("EDID block %d read failed\n", block_num); 1925 break; 1926 case EDID_BLOCK_NULL: 1927 pr_debug("EDID block %d pointer is NULL\n", block_num); 1928 break; 1929 case EDID_BLOCK_ZERO: 1930 pr_notice("EDID block %d is all zeroes\n", block_num); 1931 break; 1932 case EDID_BLOCK_HEADER_CORRUPT: 1933 pr_notice("EDID has corrupt header\n"); 1934 break; 1935 case EDID_BLOCK_HEADER_REPAIR: 1936 pr_debug("EDID corrupt header needs repair\n"); 1937 break; 1938 case EDID_BLOCK_HEADER_FIXED: 1939 pr_debug("EDID corrupt header fixed\n"); 1940 break; 1941 case EDID_BLOCK_CHECKSUM: 1942 if (edid_block_status_valid(status, edid_block_tag(block))) { 1943 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n", 1944 block_num, edid_block_tag(block), 1945 edid_block_compute_checksum(block)); 1946 } else { 1947 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n", 1948 block_num, edid_block_tag(block), 1949 edid_block_compute_checksum(block)); 1950 } 1951 break; 1952 case EDID_BLOCK_VERSION: 1953 pr_notice("EDID has major version %d, instead of 1\n", 1954 block->version); 1955 break; 1956 default: 1957 WARN(1, "EDID block %d unknown edid block status code %d\n", 1958 block_num, status); 1959 break; 1960 } 1961 } 1962 1963 static void edid_block_dump(const char *level, const void *block, int block_num) 1964 { 1965 enum edid_block_status status; 1966 char prefix[20]; 1967 1968 status = edid_block_check(block, block_num == 0); 1969 if (status == EDID_BLOCK_ZERO) 1970 sprintf(prefix, "\t[%02x] ZERO ", block_num); 1971 else if (!edid_block_status_valid(status, edid_block_tag(block))) 1972 sprintf(prefix, "\t[%02x] BAD ", block_num); 1973 else 1974 sprintf(prefix, "\t[%02x] GOOD ", block_num); 1975 1976 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1, 1977 block, EDID_LENGTH, false); 1978 } 1979 1980 /* 1981 * Validate a base or extension EDID block and optionally dump bad blocks to 1982 * the console. 1983 */ 1984 static bool drm_edid_block_valid(void *_block, int block_num, bool print_bad_edid, 1985 bool *edid_corrupt) 1986 { 1987 struct edid *block = _block; 1988 enum edid_block_status status; 1989 bool is_base_block = block_num == 0; 1990 bool valid; 1991 1992 if (WARN_ON(!block)) 1993 return false; 1994 1995 status = edid_block_check(block, is_base_block); 1996 if (status == EDID_BLOCK_HEADER_REPAIR) { 1997 DRM_DEBUG_KMS("Fixing EDID header, your hardware may be failing\n"); 1998 edid_header_fix(block); 1999 2000 /* Retry with fixed header, update status if that worked. */ 2001 status = edid_block_check(block, is_base_block); 2002 if (status == EDID_BLOCK_OK) 2003 status = EDID_BLOCK_HEADER_FIXED; 2004 } 2005 2006 if (edid_corrupt) { 2007 /* 2008 * Unknown major version isn't corrupt but we can't use it. Only 2009 * the base block can reset edid_corrupt to false. 2010 */ 2011 if (is_base_block && 2012 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)) 2013 *edid_corrupt = false; 2014 else if (status != EDID_BLOCK_OK) 2015 *edid_corrupt = true; 2016 } 2017 2018 edid_block_status_print(status, block, block_num); 2019 2020 /* Determine whether we can use this block with this status. */ 2021 valid = edid_block_status_valid(status, edid_block_tag(block)); 2022 2023 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) { 2024 pr_notice("Raw EDID:\n"); 2025 edid_block_dump(KERN_NOTICE, block, block_num); 2026 } 2027 2028 return valid; 2029 } 2030 2031 /** 2032 * drm_edid_is_valid - sanity check EDID data 2033 * @edid: EDID data 2034 * 2035 * Sanity-check an entire EDID record (including extensions) 2036 * 2037 * Return: True if the EDID data is valid, false otherwise. 2038 */ 2039 bool drm_edid_is_valid(struct edid *edid) 2040 { 2041 int i; 2042 2043 if (!edid) 2044 return false; 2045 2046 for (i = 0; i < edid_block_count(edid); i++) { 2047 void *block = (void *)edid_block_data(edid, i); 2048 2049 if (!drm_edid_block_valid(block, i, true, NULL)) 2050 return false; 2051 } 2052 2053 return true; 2054 } 2055 EXPORT_SYMBOL(drm_edid_is_valid); 2056 2057 /** 2058 * drm_edid_valid - sanity check EDID data 2059 * @drm_edid: EDID data 2060 * 2061 * Sanity check an EDID. Cross check block count against allocated size and 2062 * checksum the blocks. 2063 * 2064 * Return: True if the EDID data is valid, false otherwise. 2065 */ 2066 bool drm_edid_valid(const struct drm_edid *drm_edid) 2067 { 2068 int i; 2069 2070 if (!drm_edid) 2071 return false; 2072 2073 if (edid_size_by_blocks(__drm_edid_block_count(drm_edid)) != drm_edid->size) 2074 return false; 2075 2076 for (i = 0; i < drm_edid_block_count(drm_edid); i++) { 2077 const void *block = drm_edid_block_data(drm_edid, i); 2078 2079 if (!edid_block_valid(block, i == 0)) 2080 return false; 2081 } 2082 2083 return true; 2084 } 2085 EXPORT_SYMBOL(drm_edid_valid); 2086 2087 static struct edid *edid_filter_invalid_blocks(struct edid *edid, 2088 size_t *alloc_size) 2089 { 2090 struct edid *new; 2091 int i, valid_blocks = 0; 2092 2093 /* 2094 * Note: If the EDID uses HF-EEODB, but has invalid blocks, we'll revert 2095 * back to regular extension count here. We don't want to start 2096 * modifying the HF-EEODB extension too. 2097 */ 2098 for (i = 0; i < edid_block_count(edid); i++) { 2099 const void *src_block = edid_block_data(edid, i); 2100 2101 if (edid_block_valid(src_block, i == 0)) { 2102 void *dst_block = (void *)edid_block_data(edid, valid_blocks); 2103 2104 memmove(dst_block, src_block, EDID_LENGTH); 2105 valid_blocks++; 2106 } 2107 } 2108 2109 /* We already trusted the base block to be valid here... */ 2110 if (WARN_ON(!valid_blocks)) { 2111 kfree(edid); 2112 return NULL; 2113 } 2114 2115 edid->extensions = valid_blocks - 1; 2116 edid->checksum = edid_block_compute_checksum(edid); 2117 2118 *alloc_size = edid_size_by_blocks(valid_blocks); 2119 2120 new = krealloc(edid, *alloc_size, GFP_KERNEL); 2121 if (!new) 2122 kfree(edid); 2123 2124 return new; 2125 } 2126 2127 #define DDC_SEGMENT_ADDR 0x30 2128 /** 2129 * drm_do_probe_ddc_edid() - get EDID information via I2C 2130 * @data: I2C device adapter 2131 * @buf: EDID data buffer to be filled 2132 * @block: 128 byte EDID block to start fetching from 2133 * @len: EDID data buffer length to fetch 2134 * 2135 * Try to fetch EDID information by calling I2C driver functions. 2136 * 2137 * Return: 0 on success or -1 on failure. 2138 */ 2139 static int 2140 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 2141 { 2142 struct i2c_adapter *adapter = data; 2143 unsigned char start = block * EDID_LENGTH; 2144 unsigned char segment = block >> 1; 2145 unsigned char xfers = segment ? 3 : 2; 2146 int ret, retries = 5; 2147 2148 /* 2149 * The core I2C driver will automatically retry the transfer if the 2150 * adapter reports EAGAIN. However, we find that bit-banging transfers 2151 * are susceptible to errors under a heavily loaded machine and 2152 * generate spurious NAKs and timeouts. Retrying the transfer 2153 * of the individual block a few times seems to overcome this. 2154 */ 2155 do { 2156 struct i2c_msg msgs[] = { 2157 { 2158 .addr = DDC_SEGMENT_ADDR, 2159 .flags = 0, 2160 .len = 1, 2161 .buf = &segment, 2162 }, { 2163 .addr = DDC_ADDR, 2164 .flags = 0, 2165 .len = 1, 2166 .buf = &start, 2167 }, { 2168 .addr = DDC_ADDR, 2169 .flags = I2C_M_RD, 2170 .len = len, 2171 .buf = buf, 2172 } 2173 }; 2174 2175 /* 2176 * Avoid sending the segment addr to not upset non-compliant 2177 * DDC monitors. 2178 */ 2179 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 2180 2181 if (ret == -ENXIO) { 2182 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 2183 adapter->name); 2184 break; 2185 } 2186 } while (ret != xfers && --retries); 2187 2188 return ret == xfers ? 0 : -1; 2189 } 2190 2191 static void connector_bad_edid(struct drm_connector *connector, 2192 const struct edid *edid, int num_blocks) 2193 { 2194 int i; 2195 u8 last_block; 2196 2197 /* 2198 * 0x7e in the EDID is the number of extension blocks. The EDID 2199 * is 1 (base block) + num_ext_blocks big. That means we can think 2200 * of 0x7e in the EDID of the _index_ of the last block in the 2201 * combined chunk of memory. 2202 */ 2203 last_block = edid->extensions; 2204 2205 /* Calculate real checksum for the last edid extension block data */ 2206 if (last_block < num_blocks) 2207 connector->real_edid_checksum = 2208 edid_block_compute_checksum(edid + last_block); 2209 2210 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS)) 2211 return; 2212 2213 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID is invalid:\n", 2214 connector->base.id, connector->name); 2215 for (i = 0; i < num_blocks; i++) 2216 edid_block_dump(KERN_DEBUG, edid + i, i); 2217 } 2218 2219 /* Get override or firmware EDID */ 2220 static const struct drm_edid *drm_edid_override_get(struct drm_connector *connector) 2221 { 2222 const struct drm_edid *override = NULL; 2223 2224 mutex_lock(&connector->edid_override_mutex); 2225 2226 if (connector->edid_override) 2227 override = drm_edid_dup(connector->edid_override); 2228 2229 mutex_unlock(&connector->edid_override_mutex); 2230 2231 if (!override) 2232 override = drm_edid_load_firmware(connector); 2233 2234 return IS_ERR(override) ? NULL : override; 2235 } 2236 2237 /* For debugfs edid_override implementation */ 2238 int drm_edid_override_show(struct drm_connector *connector, struct seq_file *m) 2239 { 2240 const struct drm_edid *drm_edid; 2241 2242 mutex_lock(&connector->edid_override_mutex); 2243 2244 drm_edid = connector->edid_override; 2245 if (drm_edid) 2246 seq_write(m, drm_edid->edid, drm_edid->size); 2247 2248 mutex_unlock(&connector->edid_override_mutex); 2249 2250 return 0; 2251 } 2252 2253 /* For debugfs edid_override implementation */ 2254 int drm_edid_override_set(struct drm_connector *connector, const void *edid, 2255 size_t size) 2256 { 2257 const struct drm_edid *drm_edid; 2258 2259 drm_edid = drm_edid_alloc(edid, size); 2260 if (!drm_edid_valid(drm_edid)) { 2261 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override invalid\n", 2262 connector->base.id, connector->name); 2263 drm_edid_free(drm_edid); 2264 return -EINVAL; 2265 } 2266 2267 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override set\n", 2268 connector->base.id, connector->name); 2269 2270 mutex_lock(&connector->edid_override_mutex); 2271 2272 drm_edid_free(connector->edid_override); 2273 connector->edid_override = drm_edid; 2274 2275 mutex_unlock(&connector->edid_override_mutex); 2276 2277 return 0; 2278 } 2279 2280 /* For debugfs edid_override implementation */ 2281 int drm_edid_override_reset(struct drm_connector *connector) 2282 { 2283 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override reset\n", 2284 connector->base.id, connector->name); 2285 2286 mutex_lock(&connector->edid_override_mutex); 2287 2288 drm_edid_free(connector->edid_override); 2289 connector->edid_override = NULL; 2290 2291 mutex_unlock(&connector->edid_override_mutex); 2292 2293 return 0; 2294 } 2295 2296 /** 2297 * drm_edid_override_connector_update - add modes from override/firmware EDID 2298 * @connector: connector we're probing 2299 * 2300 * Add modes from the override/firmware EDID, if available. Only to be used from 2301 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe 2302 * failed during drm_get_edid() and caused the override/firmware EDID to be 2303 * skipped. 2304 * 2305 * Return: The number of modes added or 0 if we couldn't find any. 2306 */ 2307 int drm_edid_override_connector_update(struct drm_connector *connector) 2308 { 2309 const struct drm_edid *override; 2310 int num_modes = 0; 2311 2312 override = drm_edid_override_get(connector); 2313 if (override) { 2314 if (drm_edid_connector_update(connector, override) == 0) 2315 num_modes = drm_edid_connector_add_modes(connector); 2316 2317 drm_edid_free(override); 2318 2319 drm_dbg_kms(connector->dev, 2320 "[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n", 2321 connector->base.id, connector->name, num_modes); 2322 } 2323 2324 return num_modes; 2325 } 2326 EXPORT_SYMBOL(drm_edid_override_connector_update); 2327 2328 typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len); 2329 2330 static enum edid_block_status edid_block_read(void *block, unsigned int block_num, 2331 read_block_fn read_block, 2332 void *context) 2333 { 2334 enum edid_block_status status; 2335 bool is_base_block = block_num == 0; 2336 int try; 2337 2338 for (try = 0; try < 4; try++) { 2339 if (read_block(context, block, block_num, EDID_LENGTH)) 2340 return EDID_BLOCK_READ_FAIL; 2341 2342 status = edid_block_check(block, is_base_block); 2343 if (status == EDID_BLOCK_HEADER_REPAIR) { 2344 edid_header_fix(block); 2345 2346 /* Retry with fixed header, update status if that worked. */ 2347 status = edid_block_check(block, is_base_block); 2348 if (status == EDID_BLOCK_OK) 2349 status = EDID_BLOCK_HEADER_FIXED; 2350 } 2351 2352 if (edid_block_status_valid(status, edid_block_tag(block))) 2353 break; 2354 2355 /* Fail early for unrepairable base block all zeros. */ 2356 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO) 2357 break; 2358 } 2359 2360 return status; 2361 } 2362 2363 static struct edid *_drm_do_get_edid(struct drm_connector *connector, 2364 read_block_fn read_block, void *context, 2365 size_t *size) 2366 { 2367 enum edid_block_status status; 2368 int i, num_blocks, invalid_blocks = 0; 2369 const struct drm_edid *override; 2370 struct edid *edid, *new; 2371 size_t alloc_size = EDID_LENGTH; 2372 2373 override = drm_edid_override_get(connector); 2374 if (override) { 2375 alloc_size = override->size; 2376 edid = kmemdup(override->edid, alloc_size, GFP_KERNEL); 2377 drm_edid_free(override); 2378 if (!edid) 2379 return NULL; 2380 goto ok; 2381 } 2382 2383 edid = kmalloc(alloc_size, GFP_KERNEL); 2384 if (!edid) 2385 return NULL; 2386 2387 status = edid_block_read(edid, 0, read_block, context); 2388 2389 edid_block_status_print(status, edid, 0); 2390 2391 if (status == EDID_BLOCK_READ_FAIL) 2392 goto fail; 2393 2394 /* FIXME: Clarify what a corrupt EDID actually means. */ 2395 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION) 2396 connector->edid_corrupt = false; 2397 else 2398 connector->edid_corrupt = true; 2399 2400 if (!edid_block_status_valid(status, edid_block_tag(edid))) { 2401 if (status == EDID_BLOCK_ZERO) 2402 connector->null_edid_counter++; 2403 2404 connector_bad_edid(connector, edid, 1); 2405 goto fail; 2406 } 2407 2408 if (!edid_extension_block_count(edid)) 2409 goto ok; 2410 2411 alloc_size = edid_size(edid); 2412 new = krealloc(edid, alloc_size, GFP_KERNEL); 2413 if (!new) 2414 goto fail; 2415 edid = new; 2416 2417 num_blocks = edid_block_count(edid); 2418 for (i = 1; i < num_blocks; i++) { 2419 void *block = (void *)edid_block_data(edid, i); 2420 2421 status = edid_block_read(block, i, read_block, context); 2422 2423 edid_block_status_print(status, block, i); 2424 2425 if (!edid_block_status_valid(status, edid_block_tag(block))) { 2426 if (status == EDID_BLOCK_READ_FAIL) 2427 goto fail; 2428 invalid_blocks++; 2429 } else if (i == 1) { 2430 /* 2431 * If the first EDID extension is a CTA extension, and 2432 * the first Data Block is HF-EEODB, override the 2433 * extension block count. 2434 * 2435 * Note: HF-EEODB could specify a smaller extension 2436 * count too, but we can't risk allocating a smaller 2437 * amount. 2438 */ 2439 int eeodb = edid_hfeeodb_block_count(edid); 2440 2441 if (eeodb > num_blocks) { 2442 num_blocks = eeodb; 2443 alloc_size = edid_size_by_blocks(num_blocks); 2444 new = krealloc(edid, alloc_size, GFP_KERNEL); 2445 if (!new) 2446 goto fail; 2447 edid = new; 2448 } 2449 } 2450 } 2451 2452 if (invalid_blocks) { 2453 connector_bad_edid(connector, edid, num_blocks); 2454 2455 edid = edid_filter_invalid_blocks(edid, &alloc_size); 2456 } 2457 2458 ok: 2459 if (size) 2460 *size = alloc_size; 2461 2462 return edid; 2463 2464 fail: 2465 kfree(edid); 2466 return NULL; 2467 } 2468 2469 /** 2470 * drm_edid_raw - Get a pointer to the raw EDID data. 2471 * @drm_edid: drm_edid container 2472 * 2473 * Get a pointer to the raw EDID data. 2474 * 2475 * This is for transition only. Avoid using this like the plague. 2476 * 2477 * Return: Pointer to raw EDID data. 2478 */ 2479 const struct edid *drm_edid_raw(const struct drm_edid *drm_edid) 2480 { 2481 if (!drm_edid || !drm_edid->size) 2482 return NULL; 2483 2484 /* 2485 * Do not return pointers where relying on EDID extension count would 2486 * lead to buffer overflow. 2487 */ 2488 if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size)) 2489 return NULL; 2490 2491 return drm_edid->edid; 2492 } 2493 EXPORT_SYMBOL(drm_edid_raw); 2494 2495 /* Allocate struct drm_edid container *without* duplicating the edid data */ 2496 static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size) 2497 { 2498 struct drm_edid *drm_edid; 2499 2500 if (!edid || !size || size < EDID_LENGTH) 2501 return NULL; 2502 2503 drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL); 2504 if (drm_edid) { 2505 drm_edid->edid = edid; 2506 drm_edid->size = size; 2507 } 2508 2509 return drm_edid; 2510 } 2511 2512 /** 2513 * drm_edid_alloc - Allocate a new drm_edid container 2514 * @edid: Pointer to raw EDID data 2515 * @size: Size of memory allocated for EDID 2516 * 2517 * Allocate a new drm_edid container. Do not calculate edid size from edid, pass 2518 * the actual size that has been allocated for the data. There is no validation 2519 * of the raw EDID data against the size, but at least the EDID base block must 2520 * fit in the buffer. 2521 * 2522 * The returned pointer must be freed using drm_edid_free(). 2523 * 2524 * Return: drm_edid container, or NULL on errors 2525 */ 2526 const struct drm_edid *drm_edid_alloc(const void *edid, size_t size) 2527 { 2528 const struct drm_edid *drm_edid; 2529 2530 if (!edid || !size || size < EDID_LENGTH) 2531 return NULL; 2532 2533 edid = kmemdup(edid, size, GFP_KERNEL); 2534 if (!edid) 2535 return NULL; 2536 2537 drm_edid = _drm_edid_alloc(edid, size); 2538 if (!drm_edid) 2539 kfree(edid); 2540 2541 return drm_edid; 2542 } 2543 EXPORT_SYMBOL(drm_edid_alloc); 2544 2545 /** 2546 * drm_edid_dup - Duplicate a drm_edid container 2547 * @drm_edid: EDID to duplicate 2548 * 2549 * The returned pointer must be freed using drm_edid_free(). 2550 * 2551 * Returns: drm_edid container copy, or NULL on errors 2552 */ 2553 const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid) 2554 { 2555 if (!drm_edid) 2556 return NULL; 2557 2558 return drm_edid_alloc(drm_edid->edid, drm_edid->size); 2559 } 2560 EXPORT_SYMBOL(drm_edid_dup); 2561 2562 /** 2563 * drm_edid_free - Free the drm_edid container 2564 * @drm_edid: EDID to free 2565 */ 2566 void drm_edid_free(const struct drm_edid *drm_edid) 2567 { 2568 if (!drm_edid) 2569 return; 2570 2571 kfree(drm_edid->edid); 2572 kfree(drm_edid); 2573 } 2574 EXPORT_SYMBOL(drm_edid_free); 2575 2576 /** 2577 * drm_probe_ddc() - probe DDC presence 2578 * @adapter: I2C adapter to probe 2579 * 2580 * Return: True on success, false on failure. 2581 */ 2582 bool 2583 drm_probe_ddc(struct i2c_adapter *adapter) 2584 { 2585 unsigned char out; 2586 2587 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 2588 } 2589 EXPORT_SYMBOL(drm_probe_ddc); 2590 2591 /** 2592 * drm_get_edid - get EDID data, if available 2593 * @connector: connector we're probing 2594 * @adapter: I2C adapter to use for DDC 2595 * 2596 * Poke the given I2C channel to grab EDID data if possible. If found, 2597 * attach it to the connector. 2598 * 2599 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2600 */ 2601 struct edid *drm_get_edid(struct drm_connector *connector, 2602 struct i2c_adapter *adapter) 2603 { 2604 struct edid *edid; 2605 2606 if (connector->force == DRM_FORCE_OFF) 2607 return NULL; 2608 2609 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2610 return NULL; 2611 2612 edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL); 2613 drm_connector_update_edid_property(connector, edid); 2614 return edid; 2615 } 2616 EXPORT_SYMBOL(drm_get_edid); 2617 2618 /** 2619 * drm_edid_read_custom - Read EDID data using given EDID block read function 2620 * @connector: Connector to use 2621 * @read_block: EDID block read function 2622 * @context: Private data passed to the block read function 2623 * 2624 * When the I2C adapter connected to the DDC bus is hidden behind a device that 2625 * exposes a different interface to read EDID blocks this function can be used 2626 * to get EDID data using a custom block read function. 2627 * 2628 * As in the general case the DDC bus is accessible by the kernel at the I2C 2629 * level, drivers must make all reasonable efforts to expose it as an I2C 2630 * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing 2631 * this function. 2632 * 2633 * The EDID may be overridden using debugfs override_edid or firmware EDID 2634 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2635 * order. Having either of them bypasses actual EDID reads. 2636 * 2637 * The returned pointer must be freed using drm_edid_free(). 2638 * 2639 * Return: Pointer to EDID, or NULL if probe/read failed. 2640 */ 2641 const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector, 2642 read_block_fn read_block, 2643 void *context) 2644 { 2645 const struct drm_edid *drm_edid; 2646 struct edid *edid; 2647 size_t size = 0; 2648 2649 edid = _drm_do_get_edid(connector, read_block, context, &size); 2650 if (!edid) 2651 return NULL; 2652 2653 /* Sanity check for now */ 2654 drm_WARN_ON(connector->dev, !size); 2655 2656 drm_edid = _drm_edid_alloc(edid, size); 2657 if (!drm_edid) 2658 kfree(edid); 2659 2660 return drm_edid; 2661 } 2662 EXPORT_SYMBOL(drm_edid_read_custom); 2663 2664 /** 2665 * drm_edid_read_ddc - Read EDID data using given I2C adapter 2666 * @connector: Connector to use 2667 * @adapter: I2C adapter to use for DDC 2668 * 2669 * Read EDID using the given I2C adapter. 2670 * 2671 * The EDID may be overridden using debugfs override_edid or firmware EDID 2672 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2673 * order. Having either of them bypasses actual EDID reads. 2674 * 2675 * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and 2676 * using drm_edid_read() instead of this function. 2677 * 2678 * The returned pointer must be freed using drm_edid_free(). 2679 * 2680 * Return: Pointer to EDID, or NULL if probe/read failed. 2681 */ 2682 const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector, 2683 struct i2c_adapter *adapter) 2684 { 2685 const struct drm_edid *drm_edid; 2686 2687 if (connector->force == DRM_FORCE_OFF) 2688 return NULL; 2689 2690 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2691 return NULL; 2692 2693 drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter); 2694 2695 /* Note: Do *not* call connector updates here. */ 2696 2697 return drm_edid; 2698 } 2699 EXPORT_SYMBOL(drm_edid_read_ddc); 2700 2701 /** 2702 * drm_edid_read - Read EDID data using connector's I2C adapter 2703 * @connector: Connector to use 2704 * 2705 * Read EDID using the connector's I2C adapter. 2706 * 2707 * The EDID may be overridden using debugfs override_edid or firmware EDID 2708 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2709 * order. Having either of them bypasses actual EDID reads. 2710 * 2711 * The returned pointer must be freed using drm_edid_free(). 2712 * 2713 * Return: Pointer to EDID, or NULL if probe/read failed. 2714 */ 2715 const struct drm_edid *drm_edid_read(struct drm_connector *connector) 2716 { 2717 if (drm_WARN_ON(connector->dev, !connector->ddc)) 2718 return NULL; 2719 2720 return drm_edid_read_ddc(connector, connector->ddc); 2721 } 2722 EXPORT_SYMBOL(drm_edid_read); 2723 2724 /** 2725 * drm_edid_get_product_id - Get the vendor and product identification 2726 * @drm_edid: EDID 2727 * @id: Where to place the product id 2728 */ 2729 void drm_edid_get_product_id(const struct drm_edid *drm_edid, 2730 struct drm_edid_product_id *id) 2731 { 2732 if (drm_edid && drm_edid->edid && drm_edid->size >= EDID_LENGTH) 2733 memcpy(id, &drm_edid->edid->product_id, sizeof(*id)); 2734 else 2735 memset(id, 0, sizeof(*id)); 2736 } 2737 EXPORT_SYMBOL(drm_edid_get_product_id); 2738 2739 static void decode_date(struct seq_buf *s, const struct drm_edid_product_id *id) 2740 { 2741 int week = id->week_of_manufacture; 2742 int year = id->year_of_manufacture + 1990; 2743 2744 if (week == 0xff) 2745 seq_buf_printf(s, "model year: %d", year); 2746 else if (!week) 2747 seq_buf_printf(s, "year of manufacture: %d", year); 2748 else 2749 seq_buf_printf(s, "week/year of manufacture: %d/%d", week, year); 2750 } 2751 2752 /** 2753 * drm_edid_print_product_id - Print decoded product id to printer 2754 * @p: drm printer 2755 * @id: EDID product id 2756 * @raw: If true, also print the raw hex 2757 * 2758 * See VESA E-EDID 1.4 section 3.4. 2759 */ 2760 void drm_edid_print_product_id(struct drm_printer *p, 2761 const struct drm_edid_product_id *id, bool raw) 2762 { 2763 DECLARE_SEQ_BUF(date, 40); 2764 char vend[4]; 2765 2766 drm_edid_decode_mfg_id(be16_to_cpu(id->manufacturer_name), vend); 2767 2768 decode_date(&date, id); 2769 2770 drm_printf(p, "manufacturer name: %s, product code: %u, serial number: %u, %s\n", 2771 vend, le16_to_cpu(id->product_code), 2772 le32_to_cpu(id->serial_number), seq_buf_str(&date)); 2773 2774 if (raw) 2775 drm_printf(p, "raw product id: %*ph\n", (int)sizeof(*id), id); 2776 2777 WARN_ON(seq_buf_has_overflowed(&date)); 2778 } 2779 EXPORT_SYMBOL(drm_edid_print_product_id); 2780 2781 /** 2782 * drm_edid_get_panel_id - Get a panel's ID from EDID 2783 * @drm_edid: EDID that contains panel ID. 2784 * 2785 * This function uses the first block of the EDID of a panel and (assuming 2786 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value 2787 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's 2788 * supposed to be different for each different modem of panel. 2789 * 2790 * Return: A 32-bit ID that should be different for each make/model of panel. 2791 * See the functions drm_edid_encode_panel_id() and 2792 * drm_edid_decode_panel_id() for some details on the structure of this 2793 * ID. Return 0 if the EDID size is less than a base block. 2794 */ 2795 u32 drm_edid_get_panel_id(const struct drm_edid *drm_edid) 2796 { 2797 const struct edid *edid = drm_edid->edid; 2798 2799 if (drm_edid->size < EDID_LENGTH) 2800 return 0; 2801 2802 /* 2803 * We represent the ID as a 32-bit number so it can easily be compared 2804 * with "==". 2805 * 2806 * NOTE that we deal with endianness differently for the top half 2807 * of this ID than for the bottom half. The bottom half (the product 2808 * id) gets decoded as little endian by the EDID_PRODUCT_ID because 2809 * that's how everyone seems to interpret it. The top half (the mfg_id) 2810 * gets stored as big endian because that makes 2811 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier 2812 * to write (it's easier to extract the ASCII). It doesn't really 2813 * matter, though, as long as the number here is unique. 2814 */ 2815 return (u32)edid->mfg_id[0] << 24 | 2816 (u32)edid->mfg_id[1] << 16 | 2817 (u32)EDID_PRODUCT_ID(edid); 2818 } 2819 EXPORT_SYMBOL(drm_edid_get_panel_id); 2820 2821 /** 2822 * drm_edid_read_base_block - Get a panel's EDID base block 2823 * @adapter: I2C adapter to use for DDC 2824 * 2825 * This function returns the drm_edid containing the first block of the EDID of 2826 * a panel. 2827 * 2828 * This function is intended to be used during early probing on devices where 2829 * more than one panel might be present. Because of its intended use it must 2830 * assume that the EDID of the panel is correct, at least as far as the base 2831 * block is concerned (in other words, we don't process any overrides here). 2832 * 2833 * Caller should call drm_edid_free() after use. 2834 * 2835 * NOTE: it's expected that this function and drm_do_get_edid() will both 2836 * be read the EDID, but there is no caching between them. Since we're only 2837 * reading the first block, hopefully this extra overhead won't be too big. 2838 * 2839 * WARNING: Only use this function when the connector is unknown. For example, 2840 * during the early probe of panel. The EDID read from the function is temporary 2841 * and should be replaced by the full EDID returned from other drm_edid_read. 2842 * 2843 * Return: Pointer to allocated EDID base block, or NULL on any failure. 2844 */ 2845 const struct drm_edid *drm_edid_read_base_block(struct i2c_adapter *adapter) 2846 { 2847 enum edid_block_status status; 2848 void *base_block; 2849 2850 base_block = kzalloc(EDID_LENGTH, GFP_KERNEL); 2851 if (!base_block) 2852 return NULL; 2853 2854 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter); 2855 2856 edid_block_status_print(status, base_block, 0); 2857 2858 if (!edid_block_status_valid(status, edid_block_tag(base_block))) { 2859 edid_block_dump(KERN_NOTICE, base_block, 0); 2860 kfree(base_block); 2861 return NULL; 2862 } 2863 2864 return _drm_edid_alloc(base_block, EDID_LENGTH); 2865 } 2866 EXPORT_SYMBOL(drm_edid_read_base_block); 2867 2868 /** 2869 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 2870 * @connector: connector we're probing 2871 * @adapter: I2C adapter to use for DDC 2872 * 2873 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 2874 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 2875 * switch DDC to the GPU which is retrieving EDID. 2876 * 2877 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2878 */ 2879 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 2880 struct i2c_adapter *adapter) 2881 { 2882 struct drm_device *dev = connector->dev; 2883 struct pci_dev *pdev = to_pci_dev(dev->dev); 2884 struct edid *edid; 2885 2886 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev))) 2887 return NULL; 2888 2889 vga_switcheroo_lock_ddc(pdev); 2890 edid = drm_get_edid(connector, adapter); 2891 vga_switcheroo_unlock_ddc(pdev); 2892 2893 return edid; 2894 } 2895 EXPORT_SYMBOL(drm_get_edid_switcheroo); 2896 2897 /** 2898 * drm_edid_read_switcheroo - get EDID data for a vga_switcheroo output 2899 * @connector: connector we're probing 2900 * @adapter: I2C adapter to use for DDC 2901 * 2902 * Wrapper around drm_edid_read_ddc() for laptops with dual GPUs using one set 2903 * of outputs. The wrapper adds the requisite vga_switcheroo calls to 2904 * temporarily switch DDC to the GPU which is retrieving EDID. 2905 * 2906 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2907 */ 2908 const struct drm_edid *drm_edid_read_switcheroo(struct drm_connector *connector, 2909 struct i2c_adapter *adapter) 2910 { 2911 struct drm_device *dev = connector->dev; 2912 struct pci_dev *pdev = to_pci_dev(dev->dev); 2913 const struct drm_edid *drm_edid; 2914 2915 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev))) 2916 return NULL; 2917 2918 vga_switcheroo_lock_ddc(pdev); 2919 drm_edid = drm_edid_read_ddc(connector, adapter); 2920 vga_switcheroo_unlock_ddc(pdev); 2921 2922 return drm_edid; 2923 } 2924 EXPORT_SYMBOL(drm_edid_read_switcheroo); 2925 2926 /** 2927 * drm_edid_duplicate - duplicate an EDID and the extensions 2928 * @edid: EDID to duplicate 2929 * 2930 * Return: Pointer to duplicated EDID or NULL on allocation failure. 2931 */ 2932 struct edid *drm_edid_duplicate(const struct edid *edid) 2933 { 2934 if (!edid) 2935 return NULL; 2936 2937 return kmemdup(edid, edid_size(edid), GFP_KERNEL); 2938 } 2939 EXPORT_SYMBOL(drm_edid_duplicate); 2940 2941 /*** EDID parsing ***/ 2942 2943 /** 2944 * edid_get_quirks - return quirk flags for a given EDID 2945 * @drm_edid: EDID to process 2946 * 2947 * This tells subsequent routines what fixes they need to apply. 2948 * 2949 * Return: A u32 represents the quirks to apply. 2950 */ 2951 static u32 edid_get_quirks(const struct drm_edid *drm_edid) 2952 { 2953 const struct edid_quirk *quirk; 2954 int i; 2955 2956 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 2957 quirk = &edid_quirk_list[i]; 2958 if (drm_edid_match(drm_edid, &quirk->ident)) 2959 return quirk->quirks; 2960 } 2961 2962 return 0; 2963 } 2964 2965 static bool drm_edid_has_internal_quirk(struct drm_connector *connector, 2966 enum drm_edid_internal_quirk quirk) 2967 { 2968 return connector->display_info.quirks & BIT(quirk); 2969 } 2970 2971 bool drm_edid_has_quirk(struct drm_connector *connector, enum drm_edid_quirk quirk) 2972 { 2973 return connector->display_info.quirks & BIT(quirk); 2974 } 2975 EXPORT_SYMBOL(drm_edid_has_quirk); 2976 2977 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 2978 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 2979 2980 /* 2981 * Walk the mode list for connector, clearing the preferred status on existing 2982 * modes and setting it anew for the right mode ala quirks. 2983 */ 2984 static void edid_fixup_preferred(struct drm_connector *connector) 2985 { 2986 struct drm_display_mode *t, *cur_mode, *preferred_mode; 2987 int target_refresh = 0; 2988 int cur_vrefresh, preferred_vrefresh; 2989 2990 if (list_empty(&connector->probed_modes)) 2991 return; 2992 2993 if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_PREFER_LARGE_60)) 2994 target_refresh = 60; 2995 if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_PREFER_LARGE_75)) 2996 target_refresh = 75; 2997 2998 preferred_mode = list_first_entry(&connector->probed_modes, 2999 struct drm_display_mode, head); 3000 3001 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 3002 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 3003 3004 if (cur_mode == preferred_mode) 3005 continue; 3006 3007 /* Largest mode is preferred */ 3008 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 3009 preferred_mode = cur_mode; 3010 3011 cur_vrefresh = drm_mode_vrefresh(cur_mode); 3012 preferred_vrefresh = drm_mode_vrefresh(preferred_mode); 3013 /* At a given size, try to get closest to target refresh */ 3014 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 3015 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 3016 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 3017 preferred_mode = cur_mode; 3018 } 3019 } 3020 3021 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 3022 } 3023 3024 static bool 3025 mode_is_rb(const struct drm_display_mode *mode) 3026 { 3027 return (mode->htotal - mode->hdisplay == 160) && 3028 (mode->hsync_end - mode->hdisplay == 80) && 3029 (mode->hsync_end - mode->hsync_start == 32) && 3030 (mode->vsync_start - mode->vdisplay == 3); 3031 } 3032 3033 /* 3034 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 3035 * @dev: Device to duplicate against 3036 * @hsize: Mode width 3037 * @vsize: Mode height 3038 * @fresh: Mode refresh rate 3039 * @rb: Mode reduced-blanking-ness 3040 * 3041 * Walk the DMT mode list looking for a match for the given parameters. 3042 * 3043 * Return: A newly allocated copy of the mode, or NULL if not found. 3044 */ 3045 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 3046 int hsize, int vsize, int fresh, 3047 bool rb) 3048 { 3049 int i; 3050 3051 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 3052 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 3053 3054 if (hsize != ptr->hdisplay) 3055 continue; 3056 if (vsize != ptr->vdisplay) 3057 continue; 3058 if (fresh != drm_mode_vrefresh(ptr)) 3059 continue; 3060 if (rb != mode_is_rb(ptr)) 3061 continue; 3062 3063 return drm_mode_duplicate(dev, ptr); 3064 } 3065 3066 return NULL; 3067 } 3068 EXPORT_SYMBOL(drm_mode_find_dmt); 3069 3070 static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type) 3071 { 3072 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0); 3073 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2); 3074 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3); 3075 3076 return descriptor->pixel_clock == 0 && 3077 descriptor->data.other_data.pad1 == 0 && 3078 descriptor->data.other_data.type == type; 3079 } 3080 3081 static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor) 3082 { 3083 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0); 3084 3085 return descriptor->pixel_clock != 0; 3086 } 3087 3088 typedef void detailed_cb(const struct detailed_timing *timing, void *closure); 3089 3090 static void 3091 cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure) 3092 { 3093 int i, n; 3094 u8 d = ext[0x02]; 3095 const u8 *det_base = ext + d; 3096 3097 if (d < 4 || d > 127) 3098 return; 3099 3100 n = (127 - d) / 18; 3101 for (i = 0; i < n; i++) 3102 cb((const struct detailed_timing *)(det_base + 18 * i), closure); 3103 } 3104 3105 static void 3106 vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure) 3107 { 3108 unsigned int i, n = min((int)ext[0x02], 6); 3109 const u8 *det_base = ext + 5; 3110 3111 if (ext[0x01] != 1) 3112 return; /* unknown version */ 3113 3114 for (i = 0; i < n; i++) 3115 cb((const struct detailed_timing *)(det_base + 18 * i), closure); 3116 } 3117 3118 static void drm_for_each_detailed_block(const struct drm_edid *drm_edid, 3119 detailed_cb *cb, void *closure) 3120 { 3121 struct drm_edid_iter edid_iter; 3122 const u8 *ext; 3123 int i; 3124 3125 if (!drm_edid) 3126 return; 3127 3128 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 3129 cb(&drm_edid->edid->detailed_timings[i], closure); 3130 3131 drm_edid_iter_begin(drm_edid, &edid_iter); 3132 drm_edid_iter_for_each(ext, &edid_iter) { 3133 switch (*ext) { 3134 case CEA_EXT: 3135 cea_for_each_detailed_block(ext, cb, closure); 3136 break; 3137 case VTB_EXT: 3138 vtb_for_each_detailed_block(ext, cb, closure); 3139 break; 3140 default: 3141 break; 3142 } 3143 } 3144 drm_edid_iter_end(&edid_iter); 3145 } 3146 3147 static void 3148 is_rb(const struct detailed_timing *descriptor, void *data) 3149 { 3150 bool *res = data; 3151 3152 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 3153 return; 3154 3155 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 3156 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15); 3157 3158 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG && 3159 descriptor->data.other_data.data.range.formula.cvt.flags & DRM_EDID_CVT_FLAGS_REDUCED_BLANKING) 3160 *res = true; 3161 } 3162 3163 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 3164 static bool 3165 drm_monitor_supports_rb(const struct drm_edid *drm_edid) 3166 { 3167 if (drm_edid->edid->revision >= 4) { 3168 bool ret = false; 3169 3170 drm_for_each_detailed_block(drm_edid, is_rb, &ret); 3171 return ret; 3172 } 3173 3174 return drm_edid_is_digital(drm_edid); 3175 } 3176 3177 static void 3178 find_gtf2(const struct detailed_timing *descriptor, void *data) 3179 { 3180 const struct detailed_timing **res = data; 3181 3182 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 3183 return; 3184 3185 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 3186 3187 if (descriptor->data.other_data.data.range.flags == DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG) 3188 *res = descriptor; 3189 } 3190 3191 /* Secondary GTF curve kicks in above some break frequency */ 3192 static int 3193 drm_gtf2_hbreak(const struct drm_edid *drm_edid) 3194 { 3195 const struct detailed_timing *descriptor = NULL; 3196 3197 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3198 3199 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12); 3200 3201 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0; 3202 } 3203 3204 static int 3205 drm_gtf2_2c(const struct drm_edid *drm_edid) 3206 { 3207 const struct detailed_timing *descriptor = NULL; 3208 3209 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3210 3211 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13); 3212 3213 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0; 3214 } 3215 3216 static int 3217 drm_gtf2_m(const struct drm_edid *drm_edid) 3218 { 3219 const struct detailed_timing *descriptor = NULL; 3220 3221 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3222 3223 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14); 3224 3225 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0; 3226 } 3227 3228 static int 3229 drm_gtf2_k(const struct drm_edid *drm_edid) 3230 { 3231 const struct detailed_timing *descriptor = NULL; 3232 3233 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3234 3235 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16); 3236 3237 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0; 3238 } 3239 3240 static int 3241 drm_gtf2_2j(const struct drm_edid *drm_edid) 3242 { 3243 const struct detailed_timing *descriptor = NULL; 3244 3245 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3246 3247 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17); 3248 3249 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0; 3250 } 3251 3252 static void 3253 get_timing_level(const struct detailed_timing *descriptor, void *data) 3254 { 3255 int *res = data; 3256 3257 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 3258 return; 3259 3260 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 3261 3262 switch (descriptor->data.other_data.data.range.flags) { 3263 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG: 3264 *res = LEVEL_GTF; 3265 break; 3266 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG: 3267 *res = LEVEL_GTF2; 3268 break; 3269 case DRM_EDID_CVT_SUPPORT_FLAG: 3270 *res = LEVEL_CVT; 3271 break; 3272 default: 3273 break; 3274 } 3275 } 3276 3277 /* Get standard timing level (CVT/GTF/DMT). */ 3278 static int standard_timing_level(const struct drm_edid *drm_edid) 3279 { 3280 const struct edid *edid = drm_edid->edid; 3281 3282 if (edid->revision >= 4) { 3283 /* 3284 * If the range descriptor doesn't 3285 * indicate otherwise default to CVT 3286 */ 3287 int ret = LEVEL_CVT; 3288 3289 drm_for_each_detailed_block(drm_edid, get_timing_level, &ret); 3290 3291 return ret; 3292 } else if (edid->revision >= 3 && drm_gtf2_hbreak(drm_edid)) { 3293 return LEVEL_GTF2; 3294 } else if (edid->revision >= 2) { 3295 return LEVEL_GTF; 3296 } else { 3297 return LEVEL_DMT; 3298 } 3299 } 3300 3301 /* 3302 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 3303 * monitors fill with ascii space (0x20) instead. 3304 */ 3305 static int 3306 bad_std_timing(u8 a, u8 b) 3307 { 3308 return (a == 0x00 && b == 0x00) || 3309 (a == 0x01 && b == 0x01) || 3310 (a == 0x20 && b == 0x20); 3311 } 3312 3313 static int drm_mode_hsync(const struct drm_display_mode *mode) 3314 { 3315 if (mode->htotal <= 0) 3316 return 0; 3317 3318 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal); 3319 } 3320 3321 static struct drm_display_mode * 3322 drm_gtf2_mode(struct drm_device *dev, 3323 const struct drm_edid *drm_edid, 3324 int hsize, int vsize, int vrefresh_rate) 3325 { 3326 struct drm_display_mode *mode; 3327 3328 /* 3329 * This is potentially wrong if there's ever a monitor with 3330 * more than one ranges section, each claiming a different 3331 * secondary GTF curve. Please don't do that. 3332 */ 3333 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 3334 if (!mode) 3335 return NULL; 3336 3337 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) { 3338 drm_mode_destroy(dev, mode); 3339 mode = drm_gtf_mode_complex(dev, hsize, vsize, 3340 vrefresh_rate, 0, 0, 3341 drm_gtf2_m(drm_edid), 3342 drm_gtf2_2c(drm_edid), 3343 drm_gtf2_k(drm_edid), 3344 drm_gtf2_2j(drm_edid)); 3345 } 3346 3347 return mode; 3348 } 3349 3350 /* 3351 * Take the standard timing params (in this case width, aspect, and refresh) 3352 * and convert them into a real mode using CVT/GTF/DMT. 3353 */ 3354 static struct drm_display_mode *drm_mode_std(struct drm_connector *connector, 3355 const struct drm_edid *drm_edid, 3356 const struct std_timing *t) 3357 { 3358 struct drm_device *dev = connector->dev; 3359 struct drm_display_mode *m, *mode = NULL; 3360 int hsize, vsize; 3361 int vrefresh_rate; 3362 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 3363 >> EDID_TIMING_ASPECT_SHIFT; 3364 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 3365 >> EDID_TIMING_VFREQ_SHIFT; 3366 int timing_level = standard_timing_level(drm_edid); 3367 3368 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 3369 return NULL; 3370 3371 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 3372 hsize = t->hsize * 8 + 248; 3373 /* vrefresh_rate = vfreq + 60 */ 3374 vrefresh_rate = vfreq + 60; 3375 /* the vdisplay is calculated based on the aspect ratio */ 3376 if (aspect_ratio == 0) { 3377 if (drm_edid->edid->revision < 3) 3378 vsize = hsize; 3379 else 3380 vsize = (hsize * 10) / 16; 3381 } else if (aspect_ratio == 1) 3382 vsize = (hsize * 3) / 4; 3383 else if (aspect_ratio == 2) 3384 vsize = (hsize * 4) / 5; 3385 else 3386 vsize = (hsize * 9) / 16; 3387 3388 /* HDTV hack, part 1 */ 3389 if (vrefresh_rate == 60 && 3390 ((hsize == 1360 && vsize == 765) || 3391 (hsize == 1368 && vsize == 769))) { 3392 hsize = 1366; 3393 vsize = 768; 3394 } 3395 3396 /* 3397 * If this connector already has a mode for this size and refresh 3398 * rate (because it came from detailed or CVT info), use that 3399 * instead. This way we don't have to guess at interlace or 3400 * reduced blanking. 3401 */ 3402 list_for_each_entry(m, &connector->probed_modes, head) 3403 if (m->hdisplay == hsize && m->vdisplay == vsize && 3404 drm_mode_vrefresh(m) == vrefresh_rate) 3405 return NULL; 3406 3407 /* HDTV hack, part 2 */ 3408 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 3409 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 3410 false); 3411 if (!mode) 3412 return NULL; 3413 mode->hdisplay = 1366; 3414 mode->hsync_start = mode->hsync_start - 1; 3415 mode->hsync_end = mode->hsync_end - 1; 3416 return mode; 3417 } 3418 3419 /* check whether it can be found in default mode table */ 3420 if (drm_monitor_supports_rb(drm_edid)) { 3421 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 3422 true); 3423 if (mode) 3424 return mode; 3425 } 3426 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 3427 if (mode) 3428 return mode; 3429 3430 /* okay, generate it */ 3431 switch (timing_level) { 3432 case LEVEL_DMT: 3433 break; 3434 case LEVEL_GTF: 3435 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 3436 break; 3437 case LEVEL_GTF2: 3438 mode = drm_gtf2_mode(dev, drm_edid, hsize, vsize, vrefresh_rate); 3439 break; 3440 case LEVEL_CVT: 3441 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 3442 false); 3443 break; 3444 } 3445 return mode; 3446 } 3447 3448 /* 3449 * EDID is delightfully ambiguous about how interlaced modes are to be 3450 * encoded. Our internal representation is of frame height, but some 3451 * HDTV detailed timings are encoded as field height. 3452 * 3453 * The format list here is from CEA, in frame size. Technically we 3454 * should be checking refresh rate too. Whatever. 3455 */ 3456 static void 3457 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 3458 const struct detailed_pixel_timing *pt) 3459 { 3460 int i; 3461 static const struct { 3462 int w, h; 3463 } cea_interlaced[] = { 3464 { 1920, 1080 }, 3465 { 720, 480 }, 3466 { 1440, 480 }, 3467 { 2880, 480 }, 3468 { 720, 576 }, 3469 { 1440, 576 }, 3470 { 2880, 576 }, 3471 }; 3472 3473 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 3474 return; 3475 3476 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 3477 if ((mode->hdisplay == cea_interlaced[i].w) && 3478 (mode->vdisplay == cea_interlaced[i].h / 2)) { 3479 mode->vdisplay *= 2; 3480 mode->vsync_start *= 2; 3481 mode->vsync_end *= 2; 3482 mode->vtotal *= 2; 3483 mode->vtotal |= 1; 3484 } 3485 } 3486 3487 mode->flags |= DRM_MODE_FLAG_INTERLACE; 3488 } 3489 3490 /* 3491 * Create a new mode from an EDID detailed timing section. An EDID detailed 3492 * timing block contains enough info for us to create and return a new struct 3493 * drm_display_mode. 3494 */ 3495 static struct drm_display_mode *drm_mode_detailed(struct drm_connector *connector, 3496 const struct drm_edid *drm_edid, 3497 const struct detailed_timing *timing) 3498 { 3499 struct drm_device *dev = connector->dev; 3500 struct drm_display_mode *mode; 3501 const struct detailed_pixel_timing *pt = &timing->data.pixel_data; 3502 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 3503 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 3504 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 3505 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 3506 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 3507 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 3508 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 3509 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 3510 3511 /* ignore tiny modes */ 3512 if (hactive < 64 || vactive < 64) 3513 return NULL; 3514 3515 if (pt->misc & DRM_EDID_PT_STEREO) { 3516 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Stereo mode not supported\n", 3517 connector->base.id, connector->name); 3518 return NULL; 3519 } 3520 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 3521 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Composite sync not supported\n", 3522 connector->base.id, connector->name); 3523 } 3524 3525 /* it is incorrect if hsync/vsync width is zero */ 3526 if (!hsync_pulse_width || !vsync_pulse_width) { 3527 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Incorrect Detailed timing. Wrong Hsync/Vsync pulse width\n", 3528 connector->base.id, connector->name); 3529 return NULL; 3530 } 3531 3532 if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_FORCE_REDUCED_BLANKING)) { 3533 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 3534 if (!mode) 3535 return NULL; 3536 3537 goto set_size; 3538 } 3539 3540 mode = drm_mode_create(dev); 3541 if (!mode) 3542 return NULL; 3543 3544 if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_135_CLOCK_TOO_HIGH)) 3545 mode->clock = 1088 * 10; 3546 else 3547 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 3548 3549 mode->hdisplay = hactive; 3550 mode->hsync_start = mode->hdisplay + hsync_offset; 3551 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 3552 mode->htotal = mode->hdisplay + hblank; 3553 3554 mode->vdisplay = vactive; 3555 mode->vsync_start = mode->vdisplay + vsync_offset; 3556 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 3557 mode->vtotal = mode->vdisplay + vblank; 3558 3559 /* Some EDIDs have bogus h/vsync_end values */ 3560 if (mode->hsync_end > mode->htotal) { 3561 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing hsync_end %d->%d\n", 3562 connector->base.id, connector->name, 3563 mode->hsync_end, mode->htotal); 3564 mode->hsync_end = mode->htotal; 3565 } 3566 if (mode->vsync_end > mode->vtotal) { 3567 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing vsync_end %d->%d\n", 3568 connector->base.id, connector->name, 3569 mode->vsync_end, mode->vtotal); 3570 mode->vsync_end = mode->vtotal; 3571 } 3572 3573 drm_mode_do_interlace_quirk(mode, pt); 3574 3575 if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_DETAILED_SYNC_PP)) { 3576 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC; 3577 } else { 3578 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 3579 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 3580 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 3581 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 3582 } 3583 3584 set_size: 3585 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 3586 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 3587 3588 if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_DETAILED_IN_CM)) { 3589 mode->width_mm *= 10; 3590 mode->height_mm *= 10; 3591 } 3592 3593 if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE)) { 3594 mode->width_mm = drm_edid->edid->width_cm * 10; 3595 mode->height_mm = drm_edid->edid->height_cm * 10; 3596 } 3597 3598 mode->type = DRM_MODE_TYPE_DRIVER; 3599 drm_mode_set_name(mode); 3600 3601 return mode; 3602 } 3603 3604 static bool 3605 mode_in_hsync_range(const struct drm_display_mode *mode, 3606 const struct edid *edid, const u8 *t) 3607 { 3608 int hsync, hmin, hmax; 3609 3610 hmin = t[7]; 3611 if (edid->revision >= 4) 3612 hmin += ((t[4] & 0x04) ? 255 : 0); 3613 hmax = t[8]; 3614 if (edid->revision >= 4) 3615 hmax += ((t[4] & 0x08) ? 255 : 0); 3616 hsync = drm_mode_hsync(mode); 3617 3618 return (hsync <= hmax && hsync >= hmin); 3619 } 3620 3621 static bool 3622 mode_in_vsync_range(const struct drm_display_mode *mode, 3623 const struct edid *edid, const u8 *t) 3624 { 3625 int vsync, vmin, vmax; 3626 3627 vmin = t[5]; 3628 if (edid->revision >= 4) 3629 vmin += ((t[4] & 0x01) ? 255 : 0); 3630 vmax = t[6]; 3631 if (edid->revision >= 4) 3632 vmax += ((t[4] & 0x02) ? 255 : 0); 3633 vsync = drm_mode_vrefresh(mode); 3634 3635 return (vsync <= vmax && vsync >= vmin); 3636 } 3637 3638 static u32 3639 range_pixel_clock(const struct edid *edid, const u8 *t) 3640 { 3641 /* unspecified */ 3642 if (t[9] == 0 || t[9] == 255) 3643 return 0; 3644 3645 /* 1.4 with CVT support gives us real precision, yay */ 3646 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG) 3647 return (t[9] * 10000) - ((t[12] >> 2) * 250); 3648 3649 /* 1.3 is pathetic, so fuzz up a bit */ 3650 return t[9] * 10000 + 5001; 3651 } 3652 3653 static bool mode_in_range(const struct drm_display_mode *mode, 3654 const struct drm_edid *drm_edid, 3655 const struct detailed_timing *timing) 3656 { 3657 const struct edid *edid = drm_edid->edid; 3658 u32 max_clock; 3659 const u8 *t = (const u8 *)timing; 3660 3661 if (!mode_in_hsync_range(mode, edid, t)) 3662 return false; 3663 3664 if (!mode_in_vsync_range(mode, edid, t)) 3665 return false; 3666 3667 max_clock = range_pixel_clock(edid, t); 3668 if (max_clock) 3669 if (mode->clock > max_clock) 3670 return false; 3671 3672 /* 1.4 max horizontal check */ 3673 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG) 3674 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 3675 return false; 3676 3677 if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid)) 3678 return false; 3679 3680 return true; 3681 } 3682 3683 static bool valid_inferred_mode(const struct drm_connector *connector, 3684 const struct drm_display_mode *mode) 3685 { 3686 const struct drm_display_mode *m; 3687 bool ok = false; 3688 3689 list_for_each_entry(m, &connector->probed_modes, head) { 3690 if (mode->hdisplay == m->hdisplay && 3691 mode->vdisplay == m->vdisplay && 3692 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 3693 return false; /* duplicated */ 3694 if (mode->hdisplay <= m->hdisplay && 3695 mode->vdisplay <= m->vdisplay) 3696 ok = true; 3697 } 3698 return ok; 3699 } 3700 3701 static int drm_dmt_modes_for_range(struct drm_connector *connector, 3702 const struct drm_edid *drm_edid, 3703 const struct detailed_timing *timing) 3704 { 3705 int i, modes = 0; 3706 struct drm_display_mode *newmode; 3707 struct drm_device *dev = connector->dev; 3708 3709 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 3710 if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) && 3711 valid_inferred_mode(connector, drm_dmt_modes + i)) { 3712 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 3713 if (newmode) { 3714 drm_mode_probed_add(connector, newmode); 3715 modes++; 3716 } 3717 } 3718 } 3719 3720 return modes; 3721 } 3722 3723 /* fix up 1366x768 mode from 1368x768; 3724 * GFT/CVT can't express 1366 width which isn't dividable by 8 3725 */ 3726 void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 3727 { 3728 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 3729 mode->hdisplay = 1366; 3730 mode->hsync_start--; 3731 mode->hsync_end--; 3732 drm_mode_set_name(mode); 3733 } 3734 } 3735 3736 static int drm_gtf_modes_for_range(struct drm_connector *connector, 3737 const struct drm_edid *drm_edid, 3738 const struct detailed_timing *timing) 3739 { 3740 int i, modes = 0; 3741 struct drm_display_mode *newmode; 3742 struct drm_device *dev = connector->dev; 3743 3744 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3745 const struct minimode *m = &extra_modes[i]; 3746 3747 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 3748 if (!newmode) 3749 return modes; 3750 3751 drm_mode_fixup_1366x768(newmode); 3752 if (!mode_in_range(newmode, drm_edid, timing) || 3753 !valid_inferred_mode(connector, newmode)) { 3754 drm_mode_destroy(dev, newmode); 3755 continue; 3756 } 3757 3758 drm_mode_probed_add(connector, newmode); 3759 modes++; 3760 } 3761 3762 return modes; 3763 } 3764 3765 static int drm_gtf2_modes_for_range(struct drm_connector *connector, 3766 const struct drm_edid *drm_edid, 3767 const struct detailed_timing *timing) 3768 { 3769 int i, modes = 0; 3770 struct drm_display_mode *newmode; 3771 struct drm_device *dev = connector->dev; 3772 3773 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3774 const struct minimode *m = &extra_modes[i]; 3775 3776 newmode = drm_gtf2_mode(dev, drm_edid, m->w, m->h, m->r); 3777 if (!newmode) 3778 return modes; 3779 3780 drm_mode_fixup_1366x768(newmode); 3781 if (!mode_in_range(newmode, drm_edid, timing) || 3782 !valid_inferred_mode(connector, newmode)) { 3783 drm_mode_destroy(dev, newmode); 3784 continue; 3785 } 3786 3787 drm_mode_probed_add(connector, newmode); 3788 modes++; 3789 } 3790 3791 return modes; 3792 } 3793 3794 static int drm_cvt_modes_for_range(struct drm_connector *connector, 3795 const struct drm_edid *drm_edid, 3796 const struct detailed_timing *timing) 3797 { 3798 int i, modes = 0; 3799 struct drm_display_mode *newmode; 3800 struct drm_device *dev = connector->dev; 3801 bool rb = drm_monitor_supports_rb(drm_edid); 3802 3803 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3804 const struct minimode *m = &extra_modes[i]; 3805 3806 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 3807 if (!newmode) 3808 return modes; 3809 3810 drm_mode_fixup_1366x768(newmode); 3811 if (!mode_in_range(newmode, drm_edid, timing) || 3812 !valid_inferred_mode(connector, newmode)) { 3813 drm_mode_destroy(dev, newmode); 3814 continue; 3815 } 3816 3817 drm_mode_probed_add(connector, newmode); 3818 modes++; 3819 } 3820 3821 return modes; 3822 } 3823 3824 static void 3825 do_inferred_modes(const struct detailed_timing *timing, void *c) 3826 { 3827 struct detailed_mode_closure *closure = c; 3828 const struct detailed_non_pixel *data = &timing->data.other_data; 3829 const struct detailed_data_monitor_range *range = &data->data.range; 3830 3831 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE)) 3832 return; 3833 3834 closure->modes += drm_dmt_modes_for_range(closure->connector, 3835 closure->drm_edid, 3836 timing); 3837 3838 if (closure->drm_edid->edid->revision < 2) 3839 return; /* GTF not defined yet */ 3840 3841 switch (range->flags) { 3842 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG: 3843 closure->modes += drm_gtf2_modes_for_range(closure->connector, 3844 closure->drm_edid, 3845 timing); 3846 break; 3847 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG: 3848 closure->modes += drm_gtf_modes_for_range(closure->connector, 3849 closure->drm_edid, 3850 timing); 3851 break; 3852 case DRM_EDID_CVT_SUPPORT_FLAG: 3853 if (closure->drm_edid->edid->revision < 4) 3854 break; 3855 3856 closure->modes += drm_cvt_modes_for_range(closure->connector, 3857 closure->drm_edid, 3858 timing); 3859 break; 3860 case DRM_EDID_RANGE_LIMITS_ONLY_FLAG: 3861 default: 3862 break; 3863 } 3864 } 3865 3866 static int add_inferred_modes(struct drm_connector *connector, 3867 const struct drm_edid *drm_edid) 3868 { 3869 struct detailed_mode_closure closure = { 3870 .connector = connector, 3871 .drm_edid = drm_edid, 3872 }; 3873 3874 if (drm_edid->edid->revision >= 1) 3875 drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure); 3876 3877 return closure.modes; 3878 } 3879 3880 static int 3881 drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing) 3882 { 3883 int i, j, m, modes = 0; 3884 struct drm_display_mode *mode; 3885 const u8 *est = ((const u8 *)timing) + 6; 3886 3887 for (i = 0; i < 6; i++) { 3888 for (j = 7; j >= 0; j--) { 3889 m = (i * 8) + (7 - j); 3890 if (m >= ARRAY_SIZE(est3_modes)) 3891 break; 3892 if (est[i] & (1 << j)) { 3893 mode = drm_mode_find_dmt(connector->dev, 3894 est3_modes[m].w, 3895 est3_modes[m].h, 3896 est3_modes[m].r, 3897 est3_modes[m].rb); 3898 if (mode) { 3899 drm_mode_probed_add(connector, mode); 3900 modes++; 3901 } 3902 } 3903 } 3904 } 3905 3906 return modes; 3907 } 3908 3909 static void 3910 do_established_modes(const struct detailed_timing *timing, void *c) 3911 { 3912 struct detailed_mode_closure *closure = c; 3913 3914 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS)) 3915 return; 3916 3917 closure->modes += drm_est3_modes(closure->connector, timing); 3918 } 3919 3920 /* 3921 * Get established modes from EDID and add them. Each EDID block contains a 3922 * bitmap of the supported "established modes" list (defined above). Tease them 3923 * out and add them to the global modes list. 3924 */ 3925 static int add_established_modes(struct drm_connector *connector, 3926 const struct drm_edid *drm_edid) 3927 { 3928 struct drm_device *dev = connector->dev; 3929 const struct edid *edid = drm_edid->edid; 3930 unsigned long est_bits = edid->established_timings.t1 | 3931 (edid->established_timings.t2 << 8) | 3932 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 3933 int i, modes = 0; 3934 struct detailed_mode_closure closure = { 3935 .connector = connector, 3936 .drm_edid = drm_edid, 3937 }; 3938 3939 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 3940 if (est_bits & (1<<i)) { 3941 struct drm_display_mode *newmode; 3942 3943 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 3944 if (newmode) { 3945 drm_mode_probed_add(connector, newmode); 3946 modes++; 3947 } 3948 } 3949 } 3950 3951 if (edid->revision >= 1) 3952 drm_for_each_detailed_block(drm_edid, do_established_modes, 3953 &closure); 3954 3955 return modes + closure.modes; 3956 } 3957 3958 static void 3959 do_standard_modes(const struct detailed_timing *timing, void *c) 3960 { 3961 struct detailed_mode_closure *closure = c; 3962 const struct detailed_non_pixel *data = &timing->data.other_data; 3963 struct drm_connector *connector = closure->connector; 3964 int i; 3965 3966 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES)) 3967 return; 3968 3969 for (i = 0; i < 6; i++) { 3970 const struct std_timing *std = &data->data.timings[i]; 3971 struct drm_display_mode *newmode; 3972 3973 newmode = drm_mode_std(connector, closure->drm_edid, std); 3974 if (newmode) { 3975 drm_mode_probed_add(connector, newmode); 3976 closure->modes++; 3977 } 3978 } 3979 } 3980 3981 /* 3982 * Get standard modes from EDID and add them. Standard modes can be calculated 3983 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and 3984 * add them to the list. 3985 */ 3986 static int add_standard_modes(struct drm_connector *connector, 3987 const struct drm_edid *drm_edid) 3988 { 3989 int i, modes = 0; 3990 struct detailed_mode_closure closure = { 3991 .connector = connector, 3992 .drm_edid = drm_edid, 3993 }; 3994 3995 for (i = 0; i < EDID_STD_TIMINGS; i++) { 3996 struct drm_display_mode *newmode; 3997 3998 newmode = drm_mode_std(connector, drm_edid, 3999 &drm_edid->edid->standard_timings[i]); 4000 if (newmode) { 4001 drm_mode_probed_add(connector, newmode); 4002 modes++; 4003 } 4004 } 4005 4006 if (drm_edid->edid->revision >= 1) 4007 drm_for_each_detailed_block(drm_edid, do_standard_modes, 4008 &closure); 4009 4010 /* XXX should also look for standard codes in VTB blocks */ 4011 4012 return modes + closure.modes; 4013 } 4014 4015 static int drm_cvt_modes(struct drm_connector *connector, 4016 const struct detailed_timing *timing) 4017 { 4018 int i, j, modes = 0; 4019 struct drm_display_mode *newmode; 4020 struct drm_device *dev = connector->dev; 4021 const struct cvt_timing *cvt; 4022 static const int rates[] = { 60, 85, 75, 60, 50 }; 4023 const u8 empty[3] = { 0, 0, 0 }; 4024 4025 for (i = 0; i < 4; i++) { 4026 int width, height; 4027 4028 cvt = &(timing->data.other_data.data.cvt[i]); 4029 4030 if (!memcmp(cvt->code, empty, 3)) 4031 continue; 4032 4033 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 4034 switch (cvt->code[1] & 0x0c) { 4035 /* default - because compiler doesn't see that we've enumerated all cases */ 4036 default: 4037 case 0x00: 4038 width = height * 4 / 3; 4039 break; 4040 case 0x04: 4041 width = height * 16 / 9; 4042 break; 4043 case 0x08: 4044 width = height * 16 / 10; 4045 break; 4046 case 0x0c: 4047 width = height * 15 / 9; 4048 break; 4049 } 4050 4051 for (j = 1; j < 5; j++) { 4052 if (cvt->code[2] & (1 << j)) { 4053 newmode = drm_cvt_mode(dev, width, height, 4054 rates[j], j == 0, 4055 false, false); 4056 if (newmode) { 4057 drm_mode_probed_add(connector, newmode); 4058 modes++; 4059 } 4060 } 4061 } 4062 } 4063 4064 return modes; 4065 } 4066 4067 static void 4068 do_cvt_mode(const struct detailed_timing *timing, void *c) 4069 { 4070 struct detailed_mode_closure *closure = c; 4071 4072 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE)) 4073 return; 4074 4075 closure->modes += drm_cvt_modes(closure->connector, timing); 4076 } 4077 4078 static int 4079 add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid) 4080 { 4081 struct detailed_mode_closure closure = { 4082 .connector = connector, 4083 .drm_edid = drm_edid, 4084 }; 4085 4086 if (drm_edid->edid->revision >= 3) 4087 drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure); 4088 4089 /* XXX should also look for CVT codes in VTB blocks */ 4090 4091 return closure.modes; 4092 } 4093 4094 static void fixup_detailed_cea_mode_clock(struct drm_connector *connector, 4095 struct drm_display_mode *mode); 4096 4097 static void 4098 do_detailed_mode(const struct detailed_timing *timing, void *c) 4099 { 4100 struct detailed_mode_closure *closure = c; 4101 struct drm_display_mode *newmode; 4102 4103 if (!is_detailed_timing_descriptor(timing)) 4104 return; 4105 4106 newmode = drm_mode_detailed(closure->connector, 4107 closure->drm_edid, timing); 4108 if (!newmode) 4109 return; 4110 4111 if (closure->preferred) 4112 newmode->type |= DRM_MODE_TYPE_PREFERRED; 4113 4114 /* 4115 * Detailed modes are limited to 10kHz pixel clock resolution, 4116 * so fix up anything that looks like CEA/HDMI mode, but the clock 4117 * is just slightly off. 4118 */ 4119 fixup_detailed_cea_mode_clock(closure->connector, newmode); 4120 4121 drm_mode_probed_add(closure->connector, newmode); 4122 closure->modes++; 4123 closure->preferred = false; 4124 } 4125 4126 /* 4127 * add_detailed_modes - Add modes from detailed timings 4128 * @connector: attached connector 4129 * @drm_edid: EDID block to scan 4130 */ 4131 static int add_detailed_modes(struct drm_connector *connector, 4132 const struct drm_edid *drm_edid) 4133 { 4134 struct detailed_mode_closure closure = { 4135 .connector = connector, 4136 .drm_edid = drm_edid, 4137 }; 4138 4139 if (drm_edid->edid->revision >= 4) 4140 closure.preferred = true; /* first detailed timing is always preferred */ 4141 else 4142 closure.preferred = 4143 drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING; 4144 4145 drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure); 4146 4147 return closure.modes; 4148 } 4149 4150 /* CTA-861-H Table 60 - CTA Tag Codes */ 4151 #define CTA_DB_AUDIO 1 4152 #define CTA_DB_VIDEO 2 4153 #define CTA_DB_VENDOR 3 4154 #define CTA_DB_SPEAKER 4 4155 #define CTA_DB_EXTENDED_TAG 7 4156 4157 /* CTA-861-H Table 62 - CTA Extended Tag Codes */ 4158 #define CTA_EXT_DB_VIDEO_CAP 0 4159 #define CTA_EXT_DB_VENDOR 1 4160 #define CTA_EXT_DB_HDR_STATIC_METADATA 6 4161 #define CTA_EXT_DB_420_VIDEO_DATA 14 4162 #define CTA_EXT_DB_420_VIDEO_CAP_MAP 15 4163 #define CTA_EXT_DB_HF_EEODB 0x78 4164 #define CTA_EXT_DB_HF_SCDB 0x79 4165 4166 #define EDID_BASIC_AUDIO (1 << 6) 4167 #define EDID_CEA_YCRCB444 (1 << 5) 4168 #define EDID_CEA_YCRCB422 (1 << 4) 4169 #define EDID_CEA_VCDB_QS (1 << 6) 4170 4171 /* 4172 * Search EDID for CEA extension block. 4173 * 4174 * FIXME: Prefer not returning pointers to raw EDID data. 4175 */ 4176 const u8 *drm_edid_find_extension(const struct drm_edid *drm_edid, 4177 int ext_id, int *ext_index) 4178 { 4179 const u8 *edid_ext = NULL; 4180 int i; 4181 4182 /* No EDID or EDID extensions */ 4183 if (!drm_edid || !drm_edid_extension_block_count(drm_edid)) 4184 return NULL; 4185 4186 /* Find CEA extension */ 4187 for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) { 4188 edid_ext = drm_edid_extension_block_data(drm_edid, i); 4189 if (edid_block_tag(edid_ext) == ext_id) 4190 break; 4191 } 4192 4193 if (i >= drm_edid_extension_block_count(drm_edid)) 4194 return NULL; 4195 4196 *ext_index = i + 1; 4197 4198 return edid_ext; 4199 } 4200 4201 /* Return true if the EDID has a CTA extension or a DisplayID CTA data block */ 4202 static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid) 4203 { 4204 const struct displayid_block *block; 4205 struct displayid_iter iter; 4206 struct drm_edid_iter edid_iter; 4207 const u8 *ext; 4208 bool found = false; 4209 4210 /* Look for a top level CEA extension block */ 4211 drm_edid_iter_begin(drm_edid, &edid_iter); 4212 drm_edid_iter_for_each(ext, &edid_iter) { 4213 if (ext[0] == CEA_EXT) { 4214 found = true; 4215 break; 4216 } 4217 } 4218 drm_edid_iter_end(&edid_iter); 4219 4220 if (found) 4221 return true; 4222 4223 /* CEA blocks can also be found embedded in a DisplayID block */ 4224 displayid_iter_edid_begin(drm_edid, &iter); 4225 displayid_iter_for_each(block, &iter) { 4226 if (block->tag == DATA_BLOCK_CTA) { 4227 found = true; 4228 break; 4229 } 4230 } 4231 displayid_iter_end(&iter); 4232 4233 return found; 4234 } 4235 4236 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic) 4237 { 4238 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127); 4239 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219); 4240 4241 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1)) 4242 return &edid_cea_modes_1[vic - 1]; 4243 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193)) 4244 return &edid_cea_modes_193[vic - 193]; 4245 return NULL; 4246 } 4247 4248 static u8 cea_num_vics(void) 4249 { 4250 return 193 + ARRAY_SIZE(edid_cea_modes_193); 4251 } 4252 4253 static u8 cea_next_vic(u8 vic) 4254 { 4255 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1)) 4256 vic = 193; 4257 return vic; 4258 } 4259 4260 /* 4261 * Calculate the alternate clock for the CEA mode 4262 * (60Hz vs. 59.94Hz etc.) 4263 */ 4264 static unsigned int 4265 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 4266 { 4267 unsigned int clock = cea_mode->clock; 4268 4269 if (drm_mode_vrefresh(cea_mode) % 6 != 0) 4270 return clock; 4271 4272 /* 4273 * edid_cea_modes contains the 59.94Hz 4274 * variant for 240 and 480 line modes, 4275 * and the 60Hz variant otherwise. 4276 */ 4277 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 4278 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 4279 else 4280 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 4281 4282 return clock; 4283 } 4284 4285 static bool 4286 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 4287 { 4288 /* 4289 * For certain VICs the spec allows the vertical 4290 * front porch to vary by one or two lines. 4291 * 4292 * cea_modes[] stores the variant with the shortest 4293 * vertical front porch. We can adjust the mode to 4294 * get the other variants by simply increasing the 4295 * vertical front porch length. 4296 */ 4297 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 || 4298 cea_mode_for_vic(9)->vtotal != 262 || 4299 cea_mode_for_vic(12)->vtotal != 262 || 4300 cea_mode_for_vic(13)->vtotal != 262 || 4301 cea_mode_for_vic(23)->vtotal != 312 || 4302 cea_mode_for_vic(24)->vtotal != 312 || 4303 cea_mode_for_vic(27)->vtotal != 312 || 4304 cea_mode_for_vic(28)->vtotal != 312); 4305 4306 if (((vic == 8 || vic == 9 || 4307 vic == 12 || vic == 13) && mode->vtotal < 263) || 4308 ((vic == 23 || vic == 24 || 4309 vic == 27 || vic == 28) && mode->vtotal < 314)) { 4310 mode->vsync_start++; 4311 mode->vsync_end++; 4312 mode->vtotal++; 4313 4314 return true; 4315 } 4316 4317 return false; 4318 } 4319 4320 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 4321 unsigned int clock_tolerance) 4322 { 4323 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4324 u8 vic; 4325 4326 if (!to_match->clock) 4327 return 0; 4328 4329 if (to_match->picture_aspect_ratio) 4330 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4331 4332 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 4333 struct drm_display_mode cea_mode; 4334 unsigned int clock1, clock2; 4335 4336 drm_mode_init(&cea_mode, cea_mode_for_vic(vic)); 4337 4338 /* Check both 60Hz and 59.94Hz */ 4339 clock1 = cea_mode.clock; 4340 clock2 = cea_mode_alternate_clock(&cea_mode); 4341 4342 if (abs(to_match->clock - clock1) > clock_tolerance && 4343 abs(to_match->clock - clock2) > clock_tolerance) 4344 continue; 4345 4346 do { 4347 if (drm_mode_match(to_match, &cea_mode, match_flags)) 4348 return vic; 4349 } while (cea_mode_alternate_timings(vic, &cea_mode)); 4350 } 4351 4352 return 0; 4353 } 4354 4355 /** 4356 * drm_match_cea_mode - look for a CEA mode matching given mode 4357 * @to_match: display mode 4358 * 4359 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 4360 * mode. 4361 */ 4362 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 4363 { 4364 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4365 u8 vic; 4366 4367 if (!to_match->clock) 4368 return 0; 4369 4370 if (to_match->picture_aspect_ratio) 4371 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4372 4373 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 4374 struct drm_display_mode cea_mode; 4375 unsigned int clock1, clock2; 4376 4377 drm_mode_init(&cea_mode, cea_mode_for_vic(vic)); 4378 4379 /* Check both 60Hz and 59.94Hz */ 4380 clock1 = cea_mode.clock; 4381 clock2 = cea_mode_alternate_clock(&cea_mode); 4382 4383 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 4384 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 4385 continue; 4386 4387 do { 4388 if (drm_mode_match(to_match, &cea_mode, match_flags)) 4389 return vic; 4390 } while (cea_mode_alternate_timings(vic, &cea_mode)); 4391 } 4392 4393 return 0; 4394 } 4395 EXPORT_SYMBOL(drm_match_cea_mode); 4396 4397 static bool drm_valid_cea_vic(u8 vic) 4398 { 4399 return cea_mode_for_vic(vic) != NULL; 4400 } 4401 4402 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 4403 { 4404 const struct drm_display_mode *mode = cea_mode_for_vic(video_code); 4405 4406 if (mode) 4407 return mode->picture_aspect_ratio; 4408 4409 return HDMI_PICTURE_ASPECT_NONE; 4410 } 4411 4412 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code) 4413 { 4414 return edid_4k_modes[video_code].picture_aspect_ratio; 4415 } 4416 4417 /* 4418 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 4419 * specific block). 4420 */ 4421 static unsigned int 4422 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 4423 { 4424 return cea_mode_alternate_clock(hdmi_mode); 4425 } 4426 4427 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 4428 unsigned int clock_tolerance) 4429 { 4430 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4431 u8 vic; 4432 4433 if (!to_match->clock) 4434 return 0; 4435 4436 if (to_match->picture_aspect_ratio) 4437 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4438 4439 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4440 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4441 unsigned int clock1, clock2; 4442 4443 /* Make sure to also match alternate clocks */ 4444 clock1 = hdmi_mode->clock; 4445 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4446 4447 if (abs(to_match->clock - clock1) > clock_tolerance && 4448 abs(to_match->clock - clock2) > clock_tolerance) 4449 continue; 4450 4451 if (drm_mode_match(to_match, hdmi_mode, match_flags)) 4452 return vic; 4453 } 4454 4455 return 0; 4456 } 4457 4458 /* 4459 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 4460 * @to_match: display mode 4461 * 4462 * An HDMI mode is one defined in the HDMI vendor specific block. 4463 * 4464 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 4465 */ 4466 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 4467 { 4468 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4469 u8 vic; 4470 4471 if (!to_match->clock) 4472 return 0; 4473 4474 if (to_match->picture_aspect_ratio) 4475 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4476 4477 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4478 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4479 unsigned int clock1, clock2; 4480 4481 /* Make sure to also match alternate clocks */ 4482 clock1 = hdmi_mode->clock; 4483 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4484 4485 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 4486 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 4487 drm_mode_match(to_match, hdmi_mode, match_flags)) 4488 return vic; 4489 } 4490 return 0; 4491 } 4492 4493 static bool drm_valid_hdmi_vic(u8 vic) 4494 { 4495 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 4496 } 4497 4498 static int add_alternate_cea_modes(struct drm_connector *connector, 4499 const struct drm_edid *drm_edid) 4500 { 4501 struct drm_device *dev = connector->dev; 4502 struct drm_display_mode *mode, *tmp; 4503 LIST_HEAD(list); 4504 int modes = 0; 4505 4506 /* Don't add CTA modes if the CTA extension block is missing */ 4507 if (!drm_edid_has_cta_extension(drm_edid)) 4508 return 0; 4509 4510 /* 4511 * Go through all probed modes and create a new mode 4512 * with the alternate clock for certain CEA modes. 4513 */ 4514 list_for_each_entry(mode, &connector->probed_modes, head) { 4515 const struct drm_display_mode *cea_mode = NULL; 4516 struct drm_display_mode *newmode; 4517 u8 vic = drm_match_cea_mode(mode); 4518 unsigned int clock1, clock2; 4519 4520 if (drm_valid_cea_vic(vic)) { 4521 cea_mode = cea_mode_for_vic(vic); 4522 clock2 = cea_mode_alternate_clock(cea_mode); 4523 } else { 4524 vic = drm_match_hdmi_mode(mode); 4525 if (drm_valid_hdmi_vic(vic)) { 4526 cea_mode = &edid_4k_modes[vic]; 4527 clock2 = hdmi_mode_alternate_clock(cea_mode); 4528 } 4529 } 4530 4531 if (!cea_mode) 4532 continue; 4533 4534 clock1 = cea_mode->clock; 4535 4536 if (clock1 == clock2) 4537 continue; 4538 4539 if (mode->clock != clock1 && mode->clock != clock2) 4540 continue; 4541 4542 newmode = drm_mode_duplicate(dev, cea_mode); 4543 if (!newmode) 4544 continue; 4545 4546 /* Carry over the stereo flags */ 4547 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 4548 4549 /* 4550 * The current mode could be either variant. Make 4551 * sure to pick the "other" clock for the new mode. 4552 */ 4553 if (mode->clock != clock1) 4554 newmode->clock = clock1; 4555 else 4556 newmode->clock = clock2; 4557 4558 list_add_tail(&newmode->head, &list); 4559 } 4560 4561 list_for_each_entry_safe(mode, tmp, &list, head) { 4562 list_del(&mode->head); 4563 drm_mode_probed_add(connector, mode); 4564 modes++; 4565 } 4566 4567 return modes; 4568 } 4569 4570 static u8 svd_to_vic(u8 svd) 4571 { 4572 /* 0-6 bit vic, 7th bit native mode indicator */ 4573 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 4574 return svd & 127; 4575 4576 return svd; 4577 } 4578 4579 /* 4580 * Return a display mode for the 0-based vic_index'th VIC across all CTA VDBs in 4581 * the EDID, or NULL on errors. 4582 */ 4583 static struct drm_display_mode * 4584 drm_display_mode_from_vic_index(struct drm_connector *connector, int vic_index) 4585 { 4586 const struct drm_display_info *info = &connector->display_info; 4587 struct drm_device *dev = connector->dev; 4588 4589 if (!info->vics || vic_index >= info->vics_len || !info->vics[vic_index]) 4590 return NULL; 4591 4592 return drm_display_mode_from_cea_vic(dev, info->vics[vic_index]); 4593 } 4594 4595 /* 4596 * do_y420vdb_modes - Parse YCBCR 420 only modes 4597 * @connector: connector corresponding to the HDMI sink 4598 * @svds: start of the data block of CEA YCBCR 420 VDB 4599 * @len: length of the CEA YCBCR 420 VDB 4600 * 4601 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 4602 * which contains modes which can be supported in YCBCR 420 4603 * output format only. 4604 */ 4605 static int do_y420vdb_modes(struct drm_connector *connector, 4606 const u8 *svds, u8 svds_len) 4607 { 4608 struct drm_device *dev = connector->dev; 4609 int modes = 0, i; 4610 4611 for (i = 0; i < svds_len; i++) { 4612 u8 vic = svd_to_vic(svds[i]); 4613 struct drm_display_mode *newmode; 4614 4615 if (!drm_valid_cea_vic(vic)) 4616 continue; 4617 4618 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 4619 if (!newmode) 4620 break; 4621 drm_mode_probed_add(connector, newmode); 4622 modes++; 4623 } 4624 4625 return modes; 4626 } 4627 4628 /** 4629 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC 4630 * @dev: DRM device 4631 * @video_code: CEA VIC of the mode 4632 * 4633 * Creates a new mode matching the specified CEA VIC. 4634 * 4635 * Returns: A new drm_display_mode on success or NULL on failure 4636 */ 4637 struct drm_display_mode * 4638 drm_display_mode_from_cea_vic(struct drm_device *dev, 4639 u8 video_code) 4640 { 4641 const struct drm_display_mode *cea_mode; 4642 struct drm_display_mode *newmode; 4643 4644 cea_mode = cea_mode_for_vic(video_code); 4645 if (!cea_mode) 4646 return NULL; 4647 4648 newmode = drm_mode_duplicate(dev, cea_mode); 4649 if (!newmode) 4650 return NULL; 4651 4652 return newmode; 4653 } 4654 EXPORT_SYMBOL(drm_display_mode_from_cea_vic); 4655 4656 /* Add modes based on VICs parsed in parse_cta_vdb() */ 4657 static int add_cta_vdb_modes(struct drm_connector *connector) 4658 { 4659 const struct drm_display_info *info = &connector->display_info; 4660 int i, modes = 0; 4661 4662 if (!info->vics) 4663 return 0; 4664 4665 for (i = 0; i < info->vics_len; i++) { 4666 struct drm_display_mode *mode; 4667 4668 mode = drm_display_mode_from_vic_index(connector, i); 4669 if (mode) { 4670 drm_mode_probed_add(connector, mode); 4671 modes++; 4672 } 4673 } 4674 4675 return modes; 4676 } 4677 4678 struct stereo_mandatory_mode { 4679 int width, height, vrefresh; 4680 unsigned int flags; 4681 }; 4682 4683 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 4684 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4685 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 4686 { 1920, 1080, 50, 4687 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 4688 { 1920, 1080, 60, 4689 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 4690 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4691 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 4692 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4693 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 4694 }; 4695 4696 static bool 4697 stereo_match_mandatory(const struct drm_display_mode *mode, 4698 const struct stereo_mandatory_mode *stereo_mode) 4699 { 4700 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 4701 4702 return mode->hdisplay == stereo_mode->width && 4703 mode->vdisplay == stereo_mode->height && 4704 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 4705 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 4706 } 4707 4708 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 4709 { 4710 struct drm_device *dev = connector->dev; 4711 const struct drm_display_mode *mode; 4712 struct list_head stereo_modes; 4713 int modes = 0, i; 4714 4715 INIT_LIST_HEAD(&stereo_modes); 4716 4717 list_for_each_entry(mode, &connector->probed_modes, head) { 4718 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 4719 const struct stereo_mandatory_mode *mandatory; 4720 struct drm_display_mode *new_mode; 4721 4722 if (!stereo_match_mandatory(mode, 4723 &stereo_mandatory_modes[i])) 4724 continue; 4725 4726 mandatory = &stereo_mandatory_modes[i]; 4727 new_mode = drm_mode_duplicate(dev, mode); 4728 if (!new_mode) 4729 continue; 4730 4731 new_mode->flags |= mandatory->flags; 4732 list_add_tail(&new_mode->head, &stereo_modes); 4733 modes++; 4734 } 4735 } 4736 4737 list_splice_tail(&stereo_modes, &connector->probed_modes); 4738 4739 return modes; 4740 } 4741 4742 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 4743 { 4744 struct drm_device *dev = connector->dev; 4745 struct drm_display_mode *newmode; 4746 4747 if (!drm_valid_hdmi_vic(vic)) { 4748 drm_err(connector->dev, "[CONNECTOR:%d:%s] Unknown HDMI VIC: %d\n", 4749 connector->base.id, connector->name, vic); 4750 return 0; 4751 } 4752 4753 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 4754 if (!newmode) 4755 return 0; 4756 4757 drm_mode_probed_add(connector, newmode); 4758 4759 return 1; 4760 } 4761 4762 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 4763 int vic_index) 4764 { 4765 struct drm_display_mode *newmode; 4766 int modes = 0; 4767 4768 if (structure & (1 << 0)) { 4769 newmode = drm_display_mode_from_vic_index(connector, vic_index); 4770 if (newmode) { 4771 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 4772 drm_mode_probed_add(connector, newmode); 4773 modes++; 4774 } 4775 } 4776 if (structure & (1 << 6)) { 4777 newmode = drm_display_mode_from_vic_index(connector, vic_index); 4778 if (newmode) { 4779 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 4780 drm_mode_probed_add(connector, newmode); 4781 modes++; 4782 } 4783 } 4784 if (structure & (1 << 8)) { 4785 newmode = drm_display_mode_from_vic_index(connector, vic_index); 4786 if (newmode) { 4787 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4788 drm_mode_probed_add(connector, newmode); 4789 modes++; 4790 } 4791 } 4792 4793 return modes; 4794 } 4795 4796 static bool hdmi_vsdb_latency_present(const u8 *db) 4797 { 4798 return db[8] & BIT(7); 4799 } 4800 4801 static bool hdmi_vsdb_i_latency_present(const u8 *db) 4802 { 4803 return hdmi_vsdb_latency_present(db) && db[8] & BIT(6); 4804 } 4805 4806 static int hdmi_vsdb_latency_length(const u8 *db) 4807 { 4808 if (hdmi_vsdb_i_latency_present(db)) 4809 return 4; 4810 else if (hdmi_vsdb_latency_present(db)) 4811 return 2; 4812 else 4813 return 0; 4814 } 4815 4816 /* 4817 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 4818 * @connector: connector corresponding to the HDMI sink 4819 * @db: start of the CEA vendor specific block 4820 * @len: length of the CEA block payload, ie. one can access up to db[len] 4821 * 4822 * Parses the HDMI VSDB looking for modes to add to @connector. This function 4823 * also adds the stereo 3d modes when applicable. 4824 */ 4825 static int 4826 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len) 4827 { 4828 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 4829 u8 vic_len, hdmi_3d_len = 0; 4830 u16 mask; 4831 u16 structure_all; 4832 4833 if (len < 8) 4834 goto out; 4835 4836 /* no HDMI_Video_Present */ 4837 if (!(db[8] & (1 << 5))) 4838 goto out; 4839 4840 offset += hdmi_vsdb_latency_length(db); 4841 4842 /* the declared length is not long enough for the 2 first bytes 4843 * of additional video format capabilities */ 4844 if (len < (8 + offset + 2)) 4845 goto out; 4846 4847 /* 3D_Present */ 4848 offset++; 4849 if (db[8 + offset] & (1 << 7)) { 4850 modes += add_hdmi_mandatory_stereo_modes(connector); 4851 4852 /* 3D_Multi_present */ 4853 multi_present = (db[8 + offset] & 0x60) >> 5; 4854 } 4855 4856 offset++; 4857 vic_len = db[8 + offset] >> 5; 4858 hdmi_3d_len = db[8 + offset] & 0x1f; 4859 4860 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 4861 u8 vic; 4862 4863 vic = db[9 + offset + i]; 4864 modes += add_hdmi_mode(connector, vic); 4865 } 4866 offset += 1 + vic_len; 4867 4868 if (multi_present == 1) 4869 multi_len = 2; 4870 else if (multi_present == 2) 4871 multi_len = 4; 4872 else 4873 multi_len = 0; 4874 4875 if (len < (8 + offset + hdmi_3d_len - 1)) 4876 goto out; 4877 4878 if (hdmi_3d_len < multi_len) 4879 goto out; 4880 4881 if (multi_present == 1 || multi_present == 2) { 4882 /* 3D_Structure_ALL */ 4883 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 4884 4885 /* check if 3D_MASK is present */ 4886 if (multi_present == 2) 4887 mask = (db[10 + offset] << 8) | db[11 + offset]; 4888 else 4889 mask = 0xffff; 4890 4891 for (i = 0; i < 16; i++) { 4892 if (mask & (1 << i)) 4893 modes += add_3d_struct_modes(connector, 4894 structure_all, i); 4895 } 4896 } 4897 4898 offset += multi_len; 4899 4900 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 4901 int vic_index; 4902 struct drm_display_mode *newmode = NULL; 4903 unsigned int newflag = 0; 4904 bool detail_present; 4905 4906 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 4907 4908 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 4909 break; 4910 4911 /* 2D_VIC_order_X */ 4912 vic_index = db[8 + offset + i] >> 4; 4913 4914 /* 3D_Structure_X */ 4915 switch (db[8 + offset + i] & 0x0f) { 4916 case 0: 4917 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 4918 break; 4919 case 6: 4920 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 4921 break; 4922 case 8: 4923 /* 3D_Detail_X */ 4924 if ((db[9 + offset + i] >> 4) == 1) 4925 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4926 break; 4927 } 4928 4929 if (newflag != 0) { 4930 newmode = drm_display_mode_from_vic_index(connector, 4931 vic_index); 4932 4933 if (newmode) { 4934 newmode->flags |= newflag; 4935 drm_mode_probed_add(connector, newmode); 4936 modes++; 4937 } 4938 } 4939 4940 if (detail_present) 4941 i++; 4942 } 4943 4944 out: 4945 return modes; 4946 } 4947 4948 static int 4949 cea_revision(const u8 *cea) 4950 { 4951 /* 4952 * FIXME is this correct for the DispID variant? 4953 * The DispID spec doesn't really specify whether 4954 * this is the revision of the CEA extension or 4955 * the DispID CEA data block. And the only value 4956 * given as an example is 0. 4957 */ 4958 return cea[1]; 4959 } 4960 4961 /* 4962 * CTA Data Block iterator. 4963 * 4964 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID 4965 * CTA Data Blocks. 4966 * 4967 * struct cea_db *db: 4968 * struct cea_db_iter iter; 4969 * 4970 * cea_db_iter_edid_begin(edid, &iter); 4971 * cea_db_iter_for_each(db, &iter) { 4972 * // do stuff with db 4973 * } 4974 * cea_db_iter_end(&iter); 4975 */ 4976 struct cea_db_iter { 4977 struct drm_edid_iter edid_iter; 4978 struct displayid_iter displayid_iter; 4979 4980 /* Current Data Block Collection. */ 4981 const u8 *collection; 4982 4983 /* Current Data Block index in current collection. */ 4984 int index; 4985 4986 /* End index in current collection. */ 4987 int end; 4988 }; 4989 4990 /* CTA-861-H section 7.4 CTA Data BLock Collection */ 4991 struct cea_db { 4992 u8 tag_length; 4993 u8 data[]; 4994 } __packed; 4995 4996 static int cea_db_tag(const struct cea_db *db) 4997 { 4998 return db->tag_length >> 5; 4999 } 5000 5001 static int cea_db_payload_len(const void *_db) 5002 { 5003 /* FIXME: Transition to passing struct cea_db * everywhere. */ 5004 const struct cea_db *db = _db; 5005 5006 return db->tag_length & 0x1f; 5007 } 5008 5009 static const void *cea_db_data(const struct cea_db *db) 5010 { 5011 return db->data; 5012 } 5013 5014 static bool cea_db_is_extended_tag(const struct cea_db *db, int tag) 5015 { 5016 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG && 5017 cea_db_payload_len(db) >= 1 && 5018 db->data[0] == tag; 5019 } 5020 5021 static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui) 5022 { 5023 const u8 *data = cea_db_data(db); 5024 5025 return cea_db_tag(db) == CTA_DB_VENDOR && 5026 cea_db_payload_len(db) >= 3 && 5027 oui(data[2], data[1], data[0]) == vendor_oui; 5028 } 5029 5030 static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid, 5031 struct cea_db_iter *iter) 5032 { 5033 memset(iter, 0, sizeof(*iter)); 5034 5035 drm_edid_iter_begin(drm_edid, &iter->edid_iter); 5036 displayid_iter_edid_begin(drm_edid, &iter->displayid_iter); 5037 } 5038 5039 static const struct cea_db * 5040 __cea_db_iter_current_block(const struct cea_db_iter *iter) 5041 { 5042 const struct cea_db *db; 5043 5044 if (!iter->collection) 5045 return NULL; 5046 5047 db = (const struct cea_db *)&iter->collection[iter->index]; 5048 5049 if (iter->index + sizeof(*db) <= iter->end && 5050 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end) 5051 return db; 5052 5053 return NULL; 5054 } 5055 5056 /* 5057 * References: 5058 * - CTA-861-H section 7.3.3 CTA Extension Version 3 5059 */ 5060 static int cea_db_collection_size(const u8 *cta) 5061 { 5062 u8 d = cta[2]; 5063 5064 if (d < 4 || d > 127) 5065 return 0; 5066 5067 return d - 4; 5068 } 5069 5070 /* 5071 * References: 5072 * - VESA E-EDID v1.4 5073 * - CTA-861-H section 7.3.3 CTA Extension Version 3 5074 */ 5075 static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter) 5076 { 5077 const u8 *ext; 5078 5079 drm_edid_iter_for_each(ext, &iter->edid_iter) { 5080 int size; 5081 5082 /* Only support CTA Extension revision 3+ */ 5083 if (ext[0] != CEA_EXT || cea_revision(ext) < 3) 5084 continue; 5085 5086 size = cea_db_collection_size(ext); 5087 if (!size) 5088 continue; 5089 5090 iter->index = 4; 5091 iter->end = iter->index + size; 5092 5093 return ext; 5094 } 5095 5096 return NULL; 5097 } 5098 5099 /* 5100 * References: 5101 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block 5102 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block 5103 * 5104 * Note that the above do not specify any connection between DisplayID Data 5105 * Block revision and CTA Extension versions. 5106 */ 5107 static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter) 5108 { 5109 const struct displayid_block *block; 5110 5111 displayid_iter_for_each(block, &iter->displayid_iter) { 5112 if (block->tag != DATA_BLOCK_CTA) 5113 continue; 5114 5115 /* 5116 * The displayid iterator has already verified the block bounds 5117 * in displayid_iter_block(). 5118 */ 5119 iter->index = sizeof(*block); 5120 iter->end = iter->index + block->num_bytes; 5121 5122 return block; 5123 } 5124 5125 return NULL; 5126 } 5127 5128 static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter) 5129 { 5130 const struct cea_db *db; 5131 5132 if (iter->collection) { 5133 /* Current collection should always be valid. */ 5134 db = __cea_db_iter_current_block(iter); 5135 if (WARN_ON(!db)) { 5136 iter->collection = NULL; 5137 return NULL; 5138 } 5139 5140 /* Next block in CTA Data Block Collection */ 5141 iter->index += sizeof(*db) + cea_db_payload_len(db); 5142 5143 db = __cea_db_iter_current_block(iter); 5144 if (db) 5145 return db; 5146 } 5147 5148 for (;;) { 5149 /* 5150 * Find the next CTA Data Block Collection. First iterate all 5151 * the EDID CTA Extensions, then all the DisplayID CTA blocks. 5152 * 5153 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID 5154 * Extension, it's recommended that DisplayID extensions are 5155 * exposed after all of the CTA Extensions. 5156 */ 5157 iter->collection = __cea_db_iter_edid_next(iter); 5158 if (!iter->collection) 5159 iter->collection = __cea_db_iter_displayid_next(iter); 5160 5161 if (!iter->collection) 5162 return NULL; 5163 5164 db = __cea_db_iter_current_block(iter); 5165 if (db) 5166 return db; 5167 } 5168 } 5169 5170 #define cea_db_iter_for_each(__db, __iter) \ 5171 while (((__db) = __cea_db_iter_next(__iter))) 5172 5173 static void cea_db_iter_end(struct cea_db_iter *iter) 5174 { 5175 displayid_iter_end(&iter->displayid_iter); 5176 drm_edid_iter_end(&iter->edid_iter); 5177 5178 memset(iter, 0, sizeof(*iter)); 5179 } 5180 5181 static bool cea_db_is_hdmi_vsdb(const struct cea_db *db) 5182 { 5183 return cea_db_is_vendor(db, HDMI_IEEE_OUI) && 5184 cea_db_payload_len(db) >= 5; 5185 } 5186 5187 static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db) 5188 { 5189 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) && 5190 cea_db_payload_len(db) >= 7; 5191 } 5192 5193 static bool cea_db_is_hdmi_forum_eeodb(const void *db) 5194 { 5195 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) && 5196 cea_db_payload_len(db) >= 2; 5197 } 5198 5199 static bool cea_db_is_microsoft_vsdb(const struct cea_db *db) 5200 { 5201 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) && 5202 cea_db_payload_len(db) == 21; 5203 } 5204 5205 static bool cea_db_is_vcdb(const struct cea_db *db) 5206 { 5207 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) && 5208 cea_db_payload_len(db) == 2; 5209 } 5210 5211 static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db) 5212 { 5213 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) && 5214 cea_db_payload_len(db) >= 7; 5215 } 5216 5217 static bool cea_db_is_y420cmdb(const struct cea_db *db) 5218 { 5219 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP); 5220 } 5221 5222 static bool cea_db_is_y420vdb(const struct cea_db *db) 5223 { 5224 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA); 5225 } 5226 5227 static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db) 5228 { 5229 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) && 5230 cea_db_payload_len(db) >= 3; 5231 } 5232 5233 /* 5234 * Get the HF-EEODB override extension block count from EDID. 5235 * 5236 * The passed in EDID may be partially read, as long as it has at least two 5237 * blocks (base block and one extension block) if EDID extension count is > 0. 5238 * 5239 * Note that this is *not* how you should parse CTA Data Blocks in general; this 5240 * is only to handle partially read EDIDs. Normally, use the CTA Data Block 5241 * iterators instead. 5242 * 5243 * References: 5244 * - HDMI 2.1 section 10.3.6 HDMI Forum EDID Extension Override Data Block 5245 */ 5246 static int edid_hfeeodb_extension_block_count(const struct edid *edid) 5247 { 5248 const u8 *cta; 5249 5250 /* No extensions according to base block, no HF-EEODB. */ 5251 if (!edid_extension_block_count(edid)) 5252 return 0; 5253 5254 /* HF-EEODB is always in the first EDID extension block only */ 5255 cta = edid_extension_block_data(edid, 0); 5256 if (edid_block_tag(cta) != CEA_EXT || cea_revision(cta) < 3) 5257 return 0; 5258 5259 /* Need to have the data block collection, and at least 3 bytes. */ 5260 if (cea_db_collection_size(cta) < 3) 5261 return 0; 5262 5263 /* 5264 * Sinks that include the HF-EEODB in their E-EDID shall include one and 5265 * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4 5266 * through 6 of Block 1 of the E-EDID. 5267 */ 5268 if (!cea_db_is_hdmi_forum_eeodb(&cta[4])) 5269 return 0; 5270 5271 return cta[4 + 2]; 5272 } 5273 5274 /* 5275 * CTA-861 YCbCr 4:2:0 Capability Map Data Block (CTA Y420CMDB) 5276 * 5277 * Y420CMDB contains a bitmap which gives the index of CTA modes from CTA VDB, 5278 * which can support YCBCR 420 sampling output also (apart from RGB/YCBCR444 5279 * etc). For example, if the bit 0 in bitmap is set, first mode in VDB can 5280 * support YCBCR420 output too. 5281 */ 5282 static void parse_cta_y420cmdb(struct drm_connector *connector, 5283 const struct cea_db *db, u64 *y420cmdb_map) 5284 { 5285 struct drm_display_info *info = &connector->display_info; 5286 int i, map_len = cea_db_payload_len(db) - 1; 5287 const u8 *data = cea_db_data(db) + 1; 5288 u64 map = 0; 5289 5290 if (map_len == 0) { 5291 /* All CEA modes support ycbcr420 sampling also.*/ 5292 map = U64_MAX; 5293 goto out; 5294 } 5295 5296 /* 5297 * This map indicates which of the existing CEA block modes 5298 * from VDB can support YCBCR420 output too. So if bit=0 is 5299 * set, first mode from VDB can support YCBCR420 output too. 5300 * We will parse and keep this map, before parsing VDB itself 5301 * to avoid going through the same block again and again. 5302 * 5303 * Spec is not clear about max possible size of this block. 5304 * Clamping max bitmap block size at 8 bytes. Every byte can 5305 * address 8 CEA modes, in this way this map can address 5306 * 8*8 = first 64 SVDs. 5307 */ 5308 if (WARN_ON_ONCE(map_len > 8)) 5309 map_len = 8; 5310 5311 for (i = 0; i < map_len; i++) 5312 map |= (u64)data[i] << (8 * i); 5313 5314 out: 5315 if (map) 5316 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; 5317 5318 *y420cmdb_map = map; 5319 } 5320 5321 static int add_cea_modes(struct drm_connector *connector, 5322 const struct drm_edid *drm_edid) 5323 { 5324 const struct cea_db *db; 5325 struct cea_db_iter iter; 5326 int modes; 5327 5328 /* CTA VDB block VICs parsed earlier */ 5329 modes = add_cta_vdb_modes(connector); 5330 5331 cea_db_iter_edid_begin(drm_edid, &iter); 5332 cea_db_iter_for_each(db, &iter) { 5333 if (cea_db_is_hdmi_vsdb(db)) { 5334 modes += do_hdmi_vsdb_modes(connector, (const u8 *)db, 5335 cea_db_payload_len(db)); 5336 } else if (cea_db_is_y420vdb(db)) { 5337 const u8 *vdb420 = cea_db_data(db) + 1; 5338 5339 /* Add 4:2:0(only) modes present in EDID */ 5340 modes += do_y420vdb_modes(connector, vdb420, 5341 cea_db_payload_len(db) - 1); 5342 } 5343 } 5344 cea_db_iter_end(&iter); 5345 5346 return modes; 5347 } 5348 5349 static void fixup_detailed_cea_mode_clock(struct drm_connector *connector, 5350 struct drm_display_mode *mode) 5351 { 5352 const struct drm_display_mode *cea_mode; 5353 int clock1, clock2, clock; 5354 u8 vic; 5355 const char *type; 5356 5357 /* 5358 * allow 5kHz clock difference either way to account for 5359 * the 10kHz clock resolution limit of detailed timings. 5360 */ 5361 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 5362 if (drm_valid_cea_vic(vic)) { 5363 type = "CEA"; 5364 cea_mode = cea_mode_for_vic(vic); 5365 clock1 = cea_mode->clock; 5366 clock2 = cea_mode_alternate_clock(cea_mode); 5367 } else { 5368 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 5369 if (drm_valid_hdmi_vic(vic)) { 5370 type = "HDMI"; 5371 cea_mode = &edid_4k_modes[vic]; 5372 clock1 = cea_mode->clock; 5373 clock2 = hdmi_mode_alternate_clock(cea_mode); 5374 } else { 5375 return; 5376 } 5377 } 5378 5379 /* pick whichever is closest */ 5380 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 5381 clock = clock1; 5382 else 5383 clock = clock2; 5384 5385 if (mode->clock == clock) 5386 return; 5387 5388 drm_dbg_kms(connector->dev, 5389 "[CONNECTOR:%d:%s] detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 5390 connector->base.id, connector->name, 5391 type, vic, mode->clock, clock); 5392 mode->clock = clock; 5393 } 5394 5395 static void drm_calculate_luminance_range(struct drm_connector *connector) 5396 { 5397 struct hdr_static_metadata *hdr_metadata = &connector->hdr_sink_metadata.hdmi_type1; 5398 struct drm_luminance_range_info *luminance_range = 5399 &connector->display_info.luminance_range; 5400 static const u8 pre_computed_values[] = { 5401 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69, 5402 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98 5403 }; 5404 u32 max_avg, min_cll, max, min, q, r; 5405 5406 if (!(hdr_metadata->metadata_type & BIT(HDMI_STATIC_METADATA_TYPE1))) 5407 return; 5408 5409 max_avg = hdr_metadata->max_fall; 5410 min_cll = hdr_metadata->min_cll; 5411 5412 /* 5413 * From the specification (CTA-861-G), for calculating the maximum 5414 * luminance we need to use: 5415 * Luminance = 50*2**(CV/32) 5416 * Where CV is a one-byte value. 5417 * For calculating this expression we may need float point precision; 5418 * to avoid this complexity level, we take advantage that CV is divided 5419 * by a constant. From the Euclids division algorithm, we know that CV 5420 * can be written as: CV = 32*q + r. Next, we replace CV in the 5421 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just 5422 * need to pre-compute the value of r/32. For pre-computing the values 5423 * We just used the following Ruby line: 5424 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round} 5425 * The results of the above expressions can be verified at 5426 * pre_computed_values. 5427 */ 5428 q = max_avg >> 5; 5429 r = max_avg % 32; 5430 max = (1 << q) * pre_computed_values[r]; 5431 5432 /* min luminance: maxLum * (CV/255)^2 / 100 */ 5433 q = DIV_ROUND_CLOSEST(min_cll, 255); 5434 min = max * DIV_ROUND_CLOSEST((q * q), 100); 5435 5436 luminance_range->min_luminance = min; 5437 luminance_range->max_luminance = max; 5438 } 5439 5440 static uint8_t eotf_supported(const u8 *edid_ext) 5441 { 5442 return edid_ext[2] & 5443 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) | 5444 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) | 5445 BIT(HDMI_EOTF_SMPTE_ST2084) | 5446 BIT(HDMI_EOTF_BT_2100_HLG)); 5447 } 5448 5449 static uint8_t hdr_metadata_type(const u8 *edid_ext) 5450 { 5451 return edid_ext[3] & 5452 BIT(HDMI_STATIC_METADATA_TYPE1); 5453 } 5454 5455 static void 5456 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db) 5457 { 5458 u16 len; 5459 5460 len = cea_db_payload_len(db); 5461 5462 connector->hdr_sink_metadata.hdmi_type1.eotf = 5463 eotf_supported(db); 5464 connector->hdr_sink_metadata.hdmi_type1.metadata_type = 5465 hdr_metadata_type(db); 5466 5467 if (len >= 4) 5468 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4]; 5469 if (len >= 5) 5470 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5]; 5471 if (len >= 6) { 5472 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6]; 5473 5474 /* Calculate only when all values are available */ 5475 drm_calculate_luminance_range(connector); 5476 } 5477 } 5478 5479 /* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */ 5480 static void 5481 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 5482 { 5483 u8 len = cea_db_payload_len(db); 5484 5485 if (len >= 6 && (db[6] & (1 << 7))) 5486 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI; 5487 5488 if (len >= 10 && hdmi_vsdb_latency_present(db)) { 5489 connector->latency_present[0] = true; 5490 connector->video_latency[0] = db[9]; 5491 connector->audio_latency[0] = db[10]; 5492 } 5493 5494 if (len >= 12 && hdmi_vsdb_i_latency_present(db)) { 5495 connector->latency_present[1] = true; 5496 connector->video_latency[1] = db[11]; 5497 connector->audio_latency[1] = db[12]; 5498 } 5499 5500 drm_dbg_kms(connector->dev, 5501 "[CONNECTOR:%d:%s] HDMI: latency present %d %d, video latency %d %d, audio latency %d %d\n", 5502 connector->base.id, connector->name, 5503 connector->latency_present[0], connector->latency_present[1], 5504 connector->video_latency[0], connector->video_latency[1], 5505 connector->audio_latency[0], connector->audio_latency[1]); 5506 } 5507 5508 static void 5509 match_identity(const struct detailed_timing *timing, void *data) 5510 { 5511 struct drm_edid_match_closure *closure = data; 5512 unsigned int i; 5513 const char *name = closure->ident->name; 5514 unsigned int name_len = strlen(name); 5515 const char *desc = timing->data.other_data.data.str.str; 5516 unsigned int desc_len = ARRAY_SIZE(timing->data.other_data.data.str.str); 5517 5518 if (name_len > desc_len || 5519 !(is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME) || 5520 is_display_descriptor(timing, EDID_DETAIL_MONITOR_STRING))) 5521 return; 5522 5523 if (strncmp(name, desc, name_len)) 5524 return; 5525 5526 for (i = name_len; i < desc_len; i++) { 5527 if (desc[i] == '\n') 5528 break; 5529 /* Allow white space before EDID string terminator. */ 5530 if (!isspace(desc[i])) 5531 return; 5532 } 5533 5534 closure->matched = true; 5535 } 5536 5537 /** 5538 * drm_edid_match - match drm_edid with given identity 5539 * @drm_edid: EDID 5540 * @ident: the EDID identity to match with 5541 * 5542 * Check if the EDID matches with the given identity. 5543 * 5544 * Return: True if the given identity matched with EDID, false otherwise. 5545 */ 5546 bool drm_edid_match(const struct drm_edid *drm_edid, 5547 const struct drm_edid_ident *ident) 5548 { 5549 if (!drm_edid || drm_edid_get_panel_id(drm_edid) != ident->panel_id) 5550 return false; 5551 5552 /* Match with name only if it's not NULL. */ 5553 if (ident->name) { 5554 struct drm_edid_match_closure closure = { 5555 .ident = ident, 5556 .matched = false, 5557 }; 5558 5559 drm_for_each_detailed_block(drm_edid, match_identity, &closure); 5560 5561 return closure.matched; 5562 } 5563 5564 return true; 5565 } 5566 EXPORT_SYMBOL(drm_edid_match); 5567 5568 static void 5569 monitor_name(const struct detailed_timing *timing, void *data) 5570 { 5571 const char **res = data; 5572 5573 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME)) 5574 return; 5575 5576 *res = timing->data.other_data.data.str.str; 5577 } 5578 5579 static int get_monitor_name(const struct drm_edid *drm_edid, char name[13]) 5580 { 5581 const char *edid_name = NULL; 5582 int mnl; 5583 5584 if (!drm_edid || !name) 5585 return 0; 5586 5587 drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name); 5588 for (mnl = 0; edid_name && mnl < 13; mnl++) { 5589 if (edid_name[mnl] == 0x0a) 5590 break; 5591 5592 name[mnl] = edid_name[mnl]; 5593 } 5594 5595 return mnl; 5596 } 5597 5598 /** 5599 * drm_edid_get_monitor_name - fetch the monitor name from the edid 5600 * @edid: monitor EDID information 5601 * @name: pointer to a character array to hold the name of the monitor 5602 * @bufsize: The size of the name buffer (should be at least 14 chars.) 5603 * 5604 */ 5605 void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize) 5606 { 5607 int name_length = 0; 5608 5609 if (bufsize <= 0) 5610 return; 5611 5612 if (edid) { 5613 char buf[13]; 5614 struct drm_edid drm_edid = { 5615 .edid = edid, 5616 .size = edid_size(edid), 5617 }; 5618 5619 name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1); 5620 memcpy(name, buf, name_length); 5621 } 5622 5623 name[name_length] = '\0'; 5624 } 5625 EXPORT_SYMBOL(drm_edid_get_monitor_name); 5626 5627 static void clear_eld(struct drm_connector *connector) 5628 { 5629 mutex_lock(&connector->eld_mutex); 5630 memset(connector->eld, 0, sizeof(connector->eld)); 5631 mutex_unlock(&connector->eld_mutex); 5632 5633 connector->latency_present[0] = false; 5634 connector->latency_present[1] = false; 5635 connector->video_latency[0] = 0; 5636 connector->audio_latency[0] = 0; 5637 connector->video_latency[1] = 0; 5638 connector->audio_latency[1] = 0; 5639 } 5640 5641 /* 5642 * Get 3-byte SAD buffer from struct cea_sad. 5643 */ 5644 void drm_edid_cta_sad_get(const struct cea_sad *cta_sad, u8 *sad) 5645 { 5646 sad[0] = cta_sad->format << 3 | cta_sad->channels; 5647 sad[1] = cta_sad->freq; 5648 sad[2] = cta_sad->byte2; 5649 } 5650 5651 /* 5652 * Set struct cea_sad from 3-byte SAD buffer. 5653 */ 5654 void drm_edid_cta_sad_set(struct cea_sad *cta_sad, const u8 *sad) 5655 { 5656 cta_sad->format = (sad[0] & 0x78) >> 3; 5657 cta_sad->channels = sad[0] & 0x07; 5658 cta_sad->freq = sad[1] & 0x7f; 5659 cta_sad->byte2 = sad[2]; 5660 } 5661 5662 /* 5663 * drm_edid_to_eld - build ELD from EDID 5664 * @connector: connector corresponding to the HDMI/DP sink 5665 * @drm_edid: EDID to parse 5666 * 5667 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 5668 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 5669 */ 5670 static void drm_edid_to_eld(struct drm_connector *connector, 5671 const struct drm_edid *drm_edid) 5672 { 5673 const struct drm_display_info *info = &connector->display_info; 5674 const struct cea_db *db; 5675 struct cea_db_iter iter; 5676 uint8_t *eld = connector->eld; 5677 int total_sad_count = 0; 5678 int mnl; 5679 5680 if (!drm_edid) 5681 return; 5682 5683 mutex_lock(&connector->eld_mutex); 5684 5685 mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]); 5686 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD monitor %s\n", 5687 connector->base.id, connector->name, 5688 &eld[DRM_ELD_MONITOR_NAME_STRING]); 5689 5690 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT; 5691 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl; 5692 5693 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D; 5694 5695 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0]; 5696 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1]; 5697 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0]; 5698 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1]; 5699 5700 cea_db_iter_edid_begin(drm_edid, &iter); 5701 cea_db_iter_for_each(db, &iter) { 5702 const u8 *data = cea_db_data(db); 5703 int len = cea_db_payload_len(db); 5704 int sad_count; 5705 5706 switch (cea_db_tag(db)) { 5707 case CTA_DB_AUDIO: 5708 /* Audio Data Block, contains SADs */ 5709 sad_count = min(len / 3, 15 - total_sad_count); 5710 if (sad_count >= 1) 5711 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)], 5712 data, sad_count * 3); 5713 total_sad_count += sad_count; 5714 break; 5715 case CTA_DB_SPEAKER: 5716 /* Speaker Allocation Data Block */ 5717 if (len >= 1) 5718 eld[DRM_ELD_SPEAKER] = data[0]; 5719 break; 5720 case CTA_DB_VENDOR: 5721 /* HDMI Vendor-Specific Data Block */ 5722 if (cea_db_is_hdmi_vsdb(db)) 5723 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db); 5724 break; 5725 default: 5726 break; 5727 } 5728 } 5729 cea_db_iter_end(&iter); 5730 5731 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT; 5732 5733 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 5734 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 5735 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 5736 else 5737 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 5738 5739 eld[DRM_ELD_BASELINE_ELD_LEN] = 5740 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 5741 5742 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD size %d, SAD count %d\n", 5743 connector->base.id, connector->name, 5744 drm_eld_size(eld), total_sad_count); 5745 5746 mutex_unlock(&connector->eld_mutex); 5747 } 5748 5749 static int _drm_edid_to_sad(const struct drm_edid *drm_edid, 5750 struct cea_sad **psads) 5751 { 5752 const struct cea_db *db; 5753 struct cea_db_iter iter; 5754 int count = 0; 5755 5756 cea_db_iter_edid_begin(drm_edid, &iter); 5757 cea_db_iter_for_each(db, &iter) { 5758 if (cea_db_tag(db) == CTA_DB_AUDIO) { 5759 struct cea_sad *sads; 5760 int i; 5761 5762 count = cea_db_payload_len(db) / 3; /* SAD is 3B */ 5763 sads = kcalloc(count, sizeof(*sads), GFP_KERNEL); 5764 *psads = sads; 5765 if (!sads) 5766 return -ENOMEM; 5767 for (i = 0; i < count; i++) 5768 drm_edid_cta_sad_set(&sads[i], &db->data[i * 3]); 5769 break; 5770 } 5771 } 5772 cea_db_iter_end(&iter); 5773 5774 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count); 5775 5776 return count; 5777 } 5778 5779 /** 5780 * drm_edid_to_sad - extracts SADs from EDID 5781 * @edid: EDID to parse 5782 * @sads: pointer that will be set to the extracted SADs 5783 * 5784 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 5785 * 5786 * Note: The returned pointer needs to be freed using kfree(). 5787 * 5788 * Return: The number of found SADs or negative number on error. 5789 */ 5790 int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads) 5791 { 5792 struct drm_edid drm_edid; 5793 5794 return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads); 5795 } 5796 EXPORT_SYMBOL(drm_edid_to_sad); 5797 5798 static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid, 5799 u8 **sadb) 5800 { 5801 const struct cea_db *db; 5802 struct cea_db_iter iter; 5803 int count = 0; 5804 5805 cea_db_iter_edid_begin(drm_edid, &iter); 5806 cea_db_iter_for_each(db, &iter) { 5807 if (cea_db_tag(db) == CTA_DB_SPEAKER && 5808 cea_db_payload_len(db) == 3) { 5809 *sadb = kmemdup(db->data, cea_db_payload_len(db), 5810 GFP_KERNEL); 5811 if (!*sadb) 5812 return -ENOMEM; 5813 count = cea_db_payload_len(db); 5814 break; 5815 } 5816 } 5817 cea_db_iter_end(&iter); 5818 5819 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count); 5820 5821 return count; 5822 } 5823 5824 /** 5825 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 5826 * @edid: EDID to parse 5827 * @sadb: pointer to the speaker block 5828 * 5829 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 5830 * 5831 * Note: The returned pointer needs to be freed using kfree(). 5832 * 5833 * Return: The number of found Speaker Allocation Blocks or negative number on 5834 * error. 5835 */ 5836 int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb) 5837 { 5838 struct drm_edid drm_edid; 5839 5840 return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid), 5841 sadb); 5842 } 5843 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 5844 5845 /** 5846 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 5847 * @connector: connector associated with the HDMI/DP sink 5848 * @mode: the display mode 5849 * 5850 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 5851 * the sink doesn't support audio or video. 5852 */ 5853 int drm_av_sync_delay(struct drm_connector *connector, 5854 const struct drm_display_mode *mode) 5855 { 5856 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 5857 int a, v; 5858 5859 if (!connector->latency_present[0]) 5860 return 0; 5861 if (!connector->latency_present[1]) 5862 i = 0; 5863 5864 a = connector->audio_latency[i]; 5865 v = connector->video_latency[i]; 5866 5867 /* 5868 * HDMI/DP sink doesn't support audio or video? 5869 */ 5870 if (a == 255 || v == 255) 5871 return 0; 5872 5873 /* 5874 * Convert raw EDID values to millisecond. 5875 * Treat unknown latency as 0ms. 5876 */ 5877 if (a) 5878 a = min(2 * (a - 1), 500); 5879 if (v) 5880 v = min(2 * (v - 1), 500); 5881 5882 return max(v - a, 0); 5883 } 5884 EXPORT_SYMBOL(drm_av_sync_delay); 5885 5886 static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid) 5887 { 5888 const struct cea_db *db; 5889 struct cea_db_iter iter; 5890 bool hdmi = false; 5891 5892 /* 5893 * Because HDMI identifier is in Vendor Specific Block, 5894 * search it from all data blocks of CEA extension. 5895 */ 5896 cea_db_iter_edid_begin(drm_edid, &iter); 5897 cea_db_iter_for_each(db, &iter) { 5898 if (cea_db_is_hdmi_vsdb(db)) { 5899 hdmi = true; 5900 break; 5901 } 5902 } 5903 cea_db_iter_end(&iter); 5904 5905 return hdmi; 5906 } 5907 5908 /** 5909 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 5910 * @edid: monitor EDID information 5911 * 5912 * Parse the CEA extension according to CEA-861-B. 5913 * 5914 * Drivers that have added the modes parsed from EDID to drm_display_info 5915 * should use &drm_display_info.is_hdmi instead of calling this function. 5916 * 5917 * Return: True if the monitor is HDMI, false if not or unknown. 5918 */ 5919 bool drm_detect_hdmi_monitor(const struct edid *edid) 5920 { 5921 struct drm_edid drm_edid; 5922 5923 return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid)); 5924 } 5925 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 5926 5927 static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid) 5928 { 5929 struct drm_edid_iter edid_iter; 5930 const struct cea_db *db; 5931 struct cea_db_iter iter; 5932 const u8 *edid_ext; 5933 bool has_audio = false; 5934 5935 drm_edid_iter_begin(drm_edid, &edid_iter); 5936 drm_edid_iter_for_each(edid_ext, &edid_iter) { 5937 if (edid_ext[0] == CEA_EXT) { 5938 has_audio = edid_ext[3] & EDID_BASIC_AUDIO; 5939 if (has_audio) 5940 break; 5941 } 5942 } 5943 drm_edid_iter_end(&edid_iter); 5944 5945 if (has_audio) { 5946 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 5947 goto end; 5948 } 5949 5950 cea_db_iter_edid_begin(drm_edid, &iter); 5951 cea_db_iter_for_each(db, &iter) { 5952 if (cea_db_tag(db) == CTA_DB_AUDIO) { 5953 const u8 *data = cea_db_data(db); 5954 int i; 5955 5956 for (i = 0; i < cea_db_payload_len(db); i += 3) 5957 DRM_DEBUG_KMS("CEA audio format %d\n", 5958 (data[i] >> 3) & 0xf); 5959 has_audio = true; 5960 break; 5961 } 5962 } 5963 cea_db_iter_end(&iter); 5964 5965 end: 5966 return has_audio; 5967 } 5968 5969 /** 5970 * drm_detect_monitor_audio - check monitor audio capability 5971 * @edid: EDID block to scan 5972 * 5973 * Monitor should have CEA extension block. 5974 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 5975 * audio' only. If there is any audio extension block and supported 5976 * audio format, assume at least 'basic audio' support, even if 'basic 5977 * audio' is not defined in EDID. 5978 * 5979 * Return: True if the monitor supports audio, false otherwise. 5980 */ 5981 bool drm_detect_monitor_audio(const struct edid *edid) 5982 { 5983 struct drm_edid drm_edid; 5984 5985 return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid)); 5986 } 5987 EXPORT_SYMBOL(drm_detect_monitor_audio); 5988 5989 5990 /** 5991 * drm_default_rgb_quant_range - default RGB quantization range 5992 * @mode: display mode 5993 * 5994 * Determine the default RGB quantization range for the mode, 5995 * as specified in CEA-861. 5996 * 5997 * Return: The default RGB quantization range for the mode 5998 */ 5999 enum hdmi_quantization_range 6000 drm_default_rgb_quant_range(const struct drm_display_mode *mode) 6001 { 6002 /* All CEA modes other than VIC 1 use limited quantization range. */ 6003 return drm_match_cea_mode(mode) > 1 ? 6004 HDMI_QUANTIZATION_RANGE_LIMITED : 6005 HDMI_QUANTIZATION_RANGE_FULL; 6006 } 6007 EXPORT_SYMBOL(drm_default_rgb_quant_range); 6008 6009 /* CTA-861 Video Data Block (CTA VDB) */ 6010 static void parse_cta_vdb(struct drm_connector *connector, const struct cea_db *db) 6011 { 6012 struct drm_display_info *info = &connector->display_info; 6013 int i, vic_index, len = cea_db_payload_len(db); 6014 const u8 *svds = cea_db_data(db); 6015 u8 *vics; 6016 6017 if (!len) 6018 return; 6019 6020 /* Gracefully handle multiple VDBs, however unlikely that is */ 6021 vics = krealloc(info->vics, info->vics_len + len, GFP_KERNEL); 6022 if (!vics) 6023 return; 6024 6025 vic_index = info->vics_len; 6026 info->vics_len += len; 6027 info->vics = vics; 6028 6029 for (i = 0; i < len; i++) { 6030 u8 vic = svd_to_vic(svds[i]); 6031 6032 if (!drm_valid_cea_vic(vic)) 6033 vic = 0; 6034 6035 info->vics[vic_index++] = vic; 6036 } 6037 } 6038 6039 /* 6040 * Update y420_cmdb_modes based on previously parsed CTA VDB and Y420CMDB. 6041 * 6042 * Translate the y420cmdb_map based on VIC indexes to y420_cmdb_modes indexed 6043 * using the VICs themselves. 6044 */ 6045 static void update_cta_y420cmdb(struct drm_connector *connector, u64 y420cmdb_map) 6046 { 6047 struct drm_display_info *info = &connector->display_info; 6048 struct drm_hdmi_info *hdmi = &info->hdmi; 6049 int i, len = min_t(int, info->vics_len, BITS_PER_TYPE(y420cmdb_map)); 6050 6051 for (i = 0; i < len; i++) { 6052 u8 vic = info->vics[i]; 6053 6054 if (vic && y420cmdb_map & BIT_ULL(i)) 6055 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 6056 } 6057 } 6058 6059 static bool cta_vdb_has_vic(const struct drm_connector *connector, u8 vic) 6060 { 6061 const struct drm_display_info *info = &connector->display_info; 6062 int i; 6063 6064 if (!vic || !info->vics) 6065 return false; 6066 6067 for (i = 0; i < info->vics_len; i++) { 6068 if (info->vics[i] == vic) 6069 return true; 6070 } 6071 6072 return false; 6073 } 6074 6075 /* CTA-861-H YCbCr 4:2:0 Video Data Block (CTA Y420VDB) */ 6076 static void parse_cta_y420vdb(struct drm_connector *connector, 6077 const struct cea_db *db) 6078 { 6079 struct drm_display_info *info = &connector->display_info; 6080 struct drm_hdmi_info *hdmi = &info->hdmi; 6081 const u8 *svds = cea_db_data(db) + 1; 6082 int i; 6083 6084 for (i = 0; i < cea_db_payload_len(db) - 1; i++) { 6085 u8 vic = svd_to_vic(svds[i]); 6086 6087 if (!drm_valid_cea_vic(vic)) 6088 continue; 6089 6090 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 6091 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; 6092 } 6093 } 6094 6095 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db) 6096 { 6097 struct drm_display_info *info = &connector->display_info; 6098 6099 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] CEA VCDB 0x%02x\n", 6100 connector->base.id, connector->name, db[2]); 6101 6102 if (db[2] & EDID_CEA_VCDB_QS) 6103 info->rgb_quant_range_selectable = true; 6104 } 6105 6106 static 6107 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane) 6108 { 6109 switch (max_frl_rate) { 6110 case 1: 6111 *max_lanes = 3; 6112 *max_rate_per_lane = 3; 6113 break; 6114 case 2: 6115 *max_lanes = 3; 6116 *max_rate_per_lane = 6; 6117 break; 6118 case 3: 6119 *max_lanes = 4; 6120 *max_rate_per_lane = 6; 6121 break; 6122 case 4: 6123 *max_lanes = 4; 6124 *max_rate_per_lane = 8; 6125 break; 6126 case 5: 6127 *max_lanes = 4; 6128 *max_rate_per_lane = 10; 6129 break; 6130 case 6: 6131 *max_lanes = 4; 6132 *max_rate_per_lane = 12; 6133 break; 6134 case 0: 6135 default: 6136 *max_lanes = 0; 6137 *max_rate_per_lane = 0; 6138 } 6139 } 6140 6141 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 6142 const u8 *db) 6143 { 6144 u8 dc_mask; 6145 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 6146 6147 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 6148 hdmi->y420_dc_modes = dc_mask; 6149 } 6150 6151 static void drm_parse_dsc_info(struct drm_hdmi_dsc_cap *hdmi_dsc, 6152 const u8 *hf_scds) 6153 { 6154 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2; 6155 6156 if (!hdmi_dsc->v_1p2) 6157 return; 6158 6159 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420; 6160 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP; 6161 6162 if (hf_scds[11] & DRM_EDID_DSC_16BPC) 6163 hdmi_dsc->bpc_supported = 16; 6164 else if (hf_scds[11] & DRM_EDID_DSC_12BPC) 6165 hdmi_dsc->bpc_supported = 12; 6166 else if (hf_scds[11] & DRM_EDID_DSC_10BPC) 6167 hdmi_dsc->bpc_supported = 10; 6168 else 6169 /* Supports min 8 BPC if DSC 1.2 is supported*/ 6170 hdmi_dsc->bpc_supported = 8; 6171 6172 if (cea_db_payload_len(hf_scds) >= 12 && hf_scds[12]) { 6173 u8 dsc_max_slices; 6174 u8 dsc_max_frl_rate; 6175 6176 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4; 6177 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes, 6178 &hdmi_dsc->max_frl_rate_per_lane); 6179 6180 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES; 6181 6182 switch (dsc_max_slices) { 6183 case 1: 6184 hdmi_dsc->max_slices = 1; 6185 hdmi_dsc->clk_per_slice = 340; 6186 break; 6187 case 2: 6188 hdmi_dsc->max_slices = 2; 6189 hdmi_dsc->clk_per_slice = 340; 6190 break; 6191 case 3: 6192 hdmi_dsc->max_slices = 4; 6193 hdmi_dsc->clk_per_slice = 340; 6194 break; 6195 case 4: 6196 hdmi_dsc->max_slices = 8; 6197 hdmi_dsc->clk_per_slice = 340; 6198 break; 6199 case 5: 6200 hdmi_dsc->max_slices = 8; 6201 hdmi_dsc->clk_per_slice = 400; 6202 break; 6203 case 6: 6204 hdmi_dsc->max_slices = 12; 6205 hdmi_dsc->clk_per_slice = 400; 6206 break; 6207 case 7: 6208 hdmi_dsc->max_slices = 16; 6209 hdmi_dsc->clk_per_slice = 400; 6210 break; 6211 case 0: 6212 default: 6213 hdmi_dsc->max_slices = 0; 6214 hdmi_dsc->clk_per_slice = 0; 6215 } 6216 } 6217 6218 if (cea_db_payload_len(hf_scds) >= 13 && hf_scds[13]) 6219 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES; 6220 } 6221 6222 /* Sink Capability Data Structure */ 6223 static void drm_parse_hdmi_forum_scds(struct drm_connector *connector, 6224 const u8 *hf_scds) 6225 { 6226 struct drm_display_info *info = &connector->display_info; 6227 struct drm_hdmi_info *hdmi = &info->hdmi; 6228 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap; 6229 int max_tmds_clock = 0; 6230 u8 max_frl_rate = 0; 6231 bool dsc_support = false; 6232 6233 info->has_hdmi_infoframe = true; 6234 6235 if (hf_scds[6] & 0x80) { 6236 hdmi->scdc.supported = true; 6237 if (hf_scds[6] & 0x40) 6238 hdmi->scdc.read_request = true; 6239 } 6240 6241 /* 6242 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 6243 * And as per the spec, three factors confirm this: 6244 * * Availability of a HF-VSDB block in EDID (check) 6245 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 6246 * * SCDC support available (let's check) 6247 * Lets check it out. 6248 */ 6249 6250 if (hf_scds[5]) { 6251 struct drm_scdc *scdc = &hdmi->scdc; 6252 6253 /* max clock is 5000 KHz times block value */ 6254 max_tmds_clock = hf_scds[5] * 5000; 6255 6256 if (max_tmds_clock > 340000) { 6257 info->max_tmds_clock = max_tmds_clock; 6258 } 6259 6260 if (scdc->supported) { 6261 scdc->scrambling.supported = true; 6262 6263 /* Few sinks support scrambling for clocks < 340M */ 6264 if ((hf_scds[6] & 0x8)) 6265 scdc->scrambling.low_rates = true; 6266 } 6267 } 6268 6269 if (hf_scds[7]) { 6270 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4; 6271 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes, 6272 &hdmi->max_frl_rate_per_lane); 6273 } 6274 6275 drm_parse_ycbcr420_deep_color_info(connector, hf_scds); 6276 6277 if (cea_db_payload_len(hf_scds) >= 11 && hf_scds[11]) { 6278 drm_parse_dsc_info(hdmi_dsc, hf_scds); 6279 dsc_support = true; 6280 } 6281 6282 drm_dbg_kms(connector->dev, 6283 "[CONNECTOR:%d:%s] HF-VSDB: max TMDS clock: %d KHz, HDMI 2.1 support: %s, DSC 1.2 support: %s\n", 6284 connector->base.id, connector->name, 6285 max_tmds_clock, str_yes_no(max_frl_rate), str_yes_no(dsc_support)); 6286 } 6287 6288 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 6289 const u8 *hdmi) 6290 { 6291 struct drm_display_info *info = &connector->display_info; 6292 unsigned int dc_bpc = 0; 6293 6294 /* HDMI supports at least 8 bpc */ 6295 info->bpc = 8; 6296 6297 if (cea_db_payload_len(hdmi) < 6) 6298 return; 6299 6300 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 6301 dc_bpc = 10; 6302 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30; 6303 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 30.\n", 6304 connector->base.id, connector->name); 6305 } 6306 6307 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 6308 dc_bpc = 12; 6309 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36; 6310 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 36.\n", 6311 connector->base.id, connector->name); 6312 } 6313 6314 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 6315 dc_bpc = 16; 6316 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48; 6317 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 48.\n", 6318 connector->base.id, connector->name); 6319 } 6320 6321 if (dc_bpc == 0) { 6322 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] No deep color support on this HDMI sink.\n", 6323 connector->base.id, connector->name); 6324 return; 6325 } 6326 6327 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Assigning HDMI sink color depth as %d bpc.\n", 6328 connector->base.id, connector->name, dc_bpc); 6329 info->bpc = dc_bpc; 6330 6331 /* YCRCB444 is optional according to spec. */ 6332 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 6333 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes; 6334 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does YCRCB444 in deep color.\n", 6335 connector->base.id, connector->name); 6336 } 6337 6338 /* 6339 * Spec says that if any deep color mode is supported at all, 6340 * then deep color 36 bit must be supported. 6341 */ 6342 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 6343 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink should do DC_36, but does not!\n", 6344 connector->base.id, connector->name); 6345 } 6346 } 6347 6348 /* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */ 6349 static void 6350 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 6351 { 6352 struct drm_display_info *info = &connector->display_info; 6353 u8 len = cea_db_payload_len(db); 6354 6355 info->is_hdmi = true; 6356 6357 info->source_physical_address = (db[4] << 8) | db[5]; 6358 6359 if (len >= 6) 6360 info->dvi_dual = db[6] & 1; 6361 if (len >= 7) 6362 info->max_tmds_clock = db[7] * 5000; 6363 6364 /* 6365 * Try to infer whether the sink supports HDMI infoframes. 6366 * 6367 * HDMI infoframe support was first added in HDMI 1.4. Assume the sink 6368 * supports infoframes if HDMI_Video_present is set. 6369 */ 6370 if (len >= 8 && db[8] & BIT(5)) 6371 info->has_hdmi_infoframe = true; 6372 6373 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI: DVI dual %d, max TMDS clock %d kHz\n", 6374 connector->base.id, connector->name, 6375 info->dvi_dual, info->max_tmds_clock); 6376 6377 drm_parse_hdmi_deep_color_info(connector, db); 6378 } 6379 6380 /* 6381 * See EDID extension for head-mounted and specialized monitors, specified at: 6382 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension 6383 */ 6384 static void drm_parse_microsoft_vsdb(struct drm_connector *connector, 6385 const u8 *db) 6386 { 6387 struct drm_display_info *info = &connector->display_info; 6388 u8 version = db[4]; 6389 bool desktop_usage = db[5] & BIT(6); 6390 6391 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */ 6392 if (version == 1 || version == 2 || (version == 3 && !desktop_usage)) 6393 info->non_desktop = true; 6394 6395 drm_dbg_kms(connector->dev, 6396 "[CONNECTOR:%d:%s] HMD or specialized display VSDB version %u: 0x%02x\n", 6397 connector->base.id, connector->name, version, db[5]); 6398 } 6399 6400 static void drm_parse_cea_ext(struct drm_connector *connector, 6401 const struct drm_edid *drm_edid) 6402 { 6403 struct drm_display_info *info = &connector->display_info; 6404 struct drm_edid_iter edid_iter; 6405 const struct cea_db *db; 6406 struct cea_db_iter iter; 6407 const u8 *edid_ext; 6408 u64 y420cmdb_map = 0; 6409 6410 drm_edid_iter_begin(drm_edid, &edid_iter); 6411 drm_edid_iter_for_each(edid_ext, &edid_iter) { 6412 if (edid_ext[0] != CEA_EXT) 6413 continue; 6414 6415 if (!info->cea_rev) 6416 info->cea_rev = edid_ext[1]; 6417 6418 if (info->cea_rev != edid_ext[1]) 6419 drm_dbg_kms(connector->dev, 6420 "[CONNECTOR:%d:%s] CEA extension version mismatch %u != %u\n", 6421 connector->base.id, connector->name, 6422 info->cea_rev, edid_ext[1]); 6423 6424 /* The existence of a CTA extension should imply RGB support */ 6425 info->color_formats = DRM_COLOR_FORMAT_RGB444; 6426 if (edid_ext[3] & EDID_CEA_YCRCB444) 6427 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444; 6428 if (edid_ext[3] & EDID_CEA_YCRCB422) 6429 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422; 6430 if (edid_ext[3] & EDID_BASIC_AUDIO) 6431 info->has_audio = true; 6432 6433 } 6434 drm_edid_iter_end(&edid_iter); 6435 6436 cea_db_iter_edid_begin(drm_edid, &iter); 6437 cea_db_iter_for_each(db, &iter) { 6438 /* FIXME: convert parsers to use struct cea_db */ 6439 const u8 *data = (const u8 *)db; 6440 6441 if (cea_db_is_hdmi_vsdb(db)) 6442 drm_parse_hdmi_vsdb_video(connector, data); 6443 else if (cea_db_is_hdmi_forum_vsdb(db) || 6444 cea_db_is_hdmi_forum_scdb(db)) 6445 drm_parse_hdmi_forum_scds(connector, data); 6446 else if (cea_db_is_microsoft_vsdb(db)) 6447 drm_parse_microsoft_vsdb(connector, data); 6448 else if (cea_db_is_y420cmdb(db)) 6449 parse_cta_y420cmdb(connector, db, &y420cmdb_map); 6450 else if (cea_db_is_y420vdb(db)) 6451 parse_cta_y420vdb(connector, db); 6452 else if (cea_db_is_vcdb(db)) 6453 drm_parse_vcdb(connector, data); 6454 else if (cea_db_is_hdmi_hdr_metadata_block(db)) 6455 drm_parse_hdr_metadata_block(connector, data); 6456 else if (cea_db_tag(db) == CTA_DB_VIDEO) 6457 parse_cta_vdb(connector, db); 6458 else if (cea_db_tag(db) == CTA_DB_AUDIO) 6459 info->has_audio = true; 6460 } 6461 cea_db_iter_end(&iter); 6462 6463 if (y420cmdb_map) 6464 update_cta_y420cmdb(connector, y420cmdb_map); 6465 } 6466 6467 static 6468 void get_monitor_range(const struct detailed_timing *timing, void *c) 6469 { 6470 struct detailed_mode_closure *closure = c; 6471 struct drm_display_info *info = &closure->connector->display_info; 6472 struct drm_monitor_range_info *monitor_range = &info->monitor_range; 6473 const struct detailed_non_pixel *data = &timing->data.other_data; 6474 const struct detailed_data_monitor_range *range = &data->data.range; 6475 const struct edid *edid = closure->drm_edid->edid; 6476 6477 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE)) 6478 return; 6479 6480 /* 6481 * These limits are used to determine the VRR refresh 6482 * rate range. Only the "range limits only" variant 6483 * of the range descriptor seems to guarantee that 6484 * any and all timings are accepted by the sink, as 6485 * opposed to just timings conforming to the indicated 6486 * formula (GTF/GTF2/CVT). Thus other variants of the 6487 * range descriptor are not accepted here. 6488 */ 6489 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG) 6490 return; 6491 6492 monitor_range->min_vfreq = range->min_vfreq; 6493 monitor_range->max_vfreq = range->max_vfreq; 6494 6495 if (edid->revision >= 4) { 6496 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ) 6497 monitor_range->min_vfreq += 255; 6498 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ) 6499 monitor_range->max_vfreq += 255; 6500 } 6501 } 6502 6503 static void drm_get_monitor_range(struct drm_connector *connector, 6504 const struct drm_edid *drm_edid) 6505 { 6506 const struct drm_display_info *info = &connector->display_info; 6507 struct detailed_mode_closure closure = { 6508 .connector = connector, 6509 .drm_edid = drm_edid, 6510 }; 6511 6512 if (drm_edid->edid->revision < 4) 6513 return; 6514 6515 if (!(drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ)) 6516 return; 6517 6518 drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure); 6519 6520 drm_dbg_kms(connector->dev, 6521 "[CONNECTOR:%d:%s] Supported Monitor Refresh rate range is %d Hz - %d Hz\n", 6522 connector->base.id, connector->name, 6523 info->monitor_range.min_vfreq, info->monitor_range.max_vfreq); 6524 } 6525 6526 static void drm_parse_vesa_mso_data(struct drm_connector *connector, 6527 const struct displayid_block *block) 6528 { 6529 struct displayid_vesa_vendor_specific_block *vesa = 6530 (struct displayid_vesa_vendor_specific_block *)block; 6531 struct drm_display_info *info = &connector->display_info; 6532 6533 if (block->num_bytes < 3) { 6534 drm_dbg_kms(connector->dev, 6535 "[CONNECTOR:%d:%s] Unexpected vendor block size %u\n", 6536 connector->base.id, connector->name, block->num_bytes); 6537 return; 6538 } 6539 6540 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI) 6541 return; 6542 6543 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) { 6544 drm_dbg_kms(connector->dev, 6545 "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n", 6546 connector->base.id, connector->name); 6547 return; 6548 } 6549 6550 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) { 6551 default: 6552 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n", 6553 connector->base.id, connector->name); 6554 fallthrough; 6555 case 0: 6556 info->mso_stream_count = 0; 6557 break; 6558 case 1: 6559 info->mso_stream_count = 2; /* 2 or 4 links */ 6560 break; 6561 case 2: 6562 info->mso_stream_count = 4; /* 4 links */ 6563 break; 6564 } 6565 6566 if (!info->mso_stream_count) { 6567 info->mso_pixel_overlap = 0; 6568 return; 6569 } 6570 6571 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso); 6572 if (info->mso_pixel_overlap > 8) { 6573 drm_dbg_kms(connector->dev, 6574 "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n", 6575 connector->base.id, connector->name, 6576 info->mso_pixel_overlap); 6577 info->mso_pixel_overlap = 8; 6578 } 6579 6580 drm_dbg_kms(connector->dev, 6581 "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n", 6582 connector->base.id, connector->name, 6583 info->mso_stream_count, info->mso_pixel_overlap); 6584 } 6585 6586 static void drm_update_mso(struct drm_connector *connector, 6587 const struct drm_edid *drm_edid) 6588 { 6589 const struct displayid_block *block; 6590 struct displayid_iter iter; 6591 6592 displayid_iter_edid_begin(drm_edid, &iter); 6593 displayid_iter_for_each(block, &iter) { 6594 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC) 6595 drm_parse_vesa_mso_data(connector, block); 6596 } 6597 displayid_iter_end(&iter); 6598 } 6599 6600 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset 6601 * all of the values which would have been set from EDID 6602 */ 6603 static void drm_reset_display_info(struct drm_connector *connector) 6604 { 6605 struct drm_display_info *info = &connector->display_info; 6606 6607 info->width_mm = 0; 6608 info->height_mm = 0; 6609 6610 info->bpc = 0; 6611 info->color_formats = 0; 6612 info->cea_rev = 0; 6613 info->max_tmds_clock = 0; 6614 info->dvi_dual = false; 6615 info->is_hdmi = false; 6616 info->has_audio = false; 6617 info->has_hdmi_infoframe = false; 6618 info->rgb_quant_range_selectable = false; 6619 memset(&info->hdmi, 0, sizeof(info->hdmi)); 6620 memset(&connector->hdr_sink_metadata, 0, sizeof(connector->hdr_sink_metadata)); 6621 6622 info->edid_hdmi_rgb444_dc_modes = 0; 6623 info->edid_hdmi_ycbcr444_dc_modes = 0; 6624 6625 info->non_desktop = 0; 6626 memset(&info->monitor_range, 0, sizeof(info->monitor_range)); 6627 memset(&info->luminance_range, 0, sizeof(info->luminance_range)); 6628 6629 info->mso_stream_count = 0; 6630 info->mso_pixel_overlap = 0; 6631 info->max_dsc_bpp = 0; 6632 6633 kfree(info->vics); 6634 info->vics = NULL; 6635 info->vics_len = 0; 6636 6637 info->quirks = 0; 6638 6639 info->source_physical_address = CEC_PHYS_ADDR_INVALID; 6640 } 6641 6642 static void update_displayid_info(struct drm_connector *connector, 6643 const struct drm_edid *drm_edid) 6644 { 6645 struct drm_display_info *info = &connector->display_info; 6646 const struct displayid_block *block; 6647 struct displayid_iter iter; 6648 6649 displayid_iter_edid_begin(drm_edid, &iter); 6650 displayid_iter_for_each(block, &iter) { 6651 drm_dbg_kms(connector->dev, 6652 "[CONNECTOR:%d:%s] DisplayID extension version 0x%02x, primary use 0x%02x\n", 6653 connector->base.id, connector->name, 6654 displayid_version(&iter), 6655 displayid_primary_use(&iter)); 6656 if (displayid_version(&iter) == DISPLAY_ID_STRUCTURE_VER_20 && 6657 (displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_VR || 6658 displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_AR)) 6659 info->non_desktop = true; 6660 6661 /* 6662 * We're only interested in the base section here, no need to 6663 * iterate further. 6664 */ 6665 break; 6666 } 6667 displayid_iter_end(&iter); 6668 } 6669 6670 static void update_display_info(struct drm_connector *connector, 6671 const struct drm_edid *drm_edid) 6672 { 6673 struct drm_display_info *info = &connector->display_info; 6674 const struct edid *edid; 6675 6676 drm_reset_display_info(connector); 6677 clear_eld(connector); 6678 6679 if (!drm_edid) 6680 return; 6681 6682 edid = drm_edid->edid; 6683 6684 info->quirks = edid_get_quirks(drm_edid); 6685 6686 info->width_mm = edid->width_cm * 10; 6687 info->height_mm = edid->height_cm * 10; 6688 6689 drm_get_monitor_range(connector, drm_edid); 6690 6691 if (edid->revision < 3) 6692 goto out; 6693 6694 if (!drm_edid_is_digital(drm_edid)) 6695 goto out; 6696 6697 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 6698 drm_parse_cea_ext(connector, drm_edid); 6699 6700 update_displayid_info(connector, drm_edid); 6701 6702 /* 6703 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 6704 * 6705 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 6706 * tells us to assume 8 bpc color depth if the EDID doesn't have 6707 * extensions which tell otherwise. 6708 */ 6709 if (info->bpc == 0 && edid->revision == 3 && 6710 edid->input & DRM_EDID_DIGITAL_DFP_1_X) { 6711 info->bpc = 8; 6712 drm_dbg_kms(connector->dev, 6713 "[CONNECTOR:%d:%s] Assigning DFP sink color depth as %d bpc.\n", 6714 connector->base.id, connector->name, info->bpc); 6715 } 6716 6717 /* Only defined for 1.4 with digital displays */ 6718 if (edid->revision < 4) 6719 goto out; 6720 6721 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 6722 case DRM_EDID_DIGITAL_DEPTH_6: 6723 info->bpc = 6; 6724 break; 6725 case DRM_EDID_DIGITAL_DEPTH_8: 6726 info->bpc = 8; 6727 break; 6728 case DRM_EDID_DIGITAL_DEPTH_10: 6729 info->bpc = 10; 6730 break; 6731 case DRM_EDID_DIGITAL_DEPTH_12: 6732 info->bpc = 12; 6733 break; 6734 case DRM_EDID_DIGITAL_DEPTH_14: 6735 info->bpc = 14; 6736 break; 6737 case DRM_EDID_DIGITAL_DEPTH_16: 6738 info->bpc = 16; 6739 break; 6740 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 6741 default: 6742 info->bpc = 0; 6743 break; 6744 } 6745 6746 drm_dbg_kms(connector->dev, 6747 "[CONNECTOR:%d:%s] Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 6748 connector->base.id, connector->name, info->bpc); 6749 6750 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 6751 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444; 6752 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 6753 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422; 6754 6755 drm_update_mso(connector, drm_edid); 6756 6757 out: 6758 if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_NON_DESKTOP)) { 6759 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Non-desktop display%s\n", 6760 connector->base.id, connector->name, 6761 info->non_desktop ? " (redundant quirk)" : ""); 6762 info->non_desktop = true; 6763 } 6764 6765 if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_CAP_DSC_15BPP)) 6766 info->max_dsc_bpp = 15; 6767 6768 if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_FORCE_6BPC)) 6769 info->bpc = 6; 6770 6771 if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_FORCE_8BPC)) 6772 info->bpc = 8; 6773 6774 if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_FORCE_10BPC)) 6775 info->bpc = 10; 6776 6777 if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_FORCE_12BPC)) 6778 info->bpc = 12; 6779 6780 /* Depends on info->cea_rev set by drm_parse_cea_ext() above */ 6781 drm_edid_to_eld(connector, drm_edid); 6782 } 6783 6784 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 6785 const struct displayid_detailed_timings_1 *timings, 6786 bool type_7) 6787 { 6788 struct drm_display_mode *mode; 6789 unsigned int pixel_clock = (timings->pixel_clock[0] | 6790 (timings->pixel_clock[1] << 8) | 6791 (timings->pixel_clock[2] << 16)) + 1; 6792 unsigned int hactive = le16_to_cpu(timings->hactive) + 1; 6793 unsigned int hblank = le16_to_cpu(timings->hblank) + 1; 6794 unsigned int hsync = (le16_to_cpu(timings->hsync) & 0x7fff) + 1; 6795 unsigned int hsync_width = le16_to_cpu(timings->hsw) + 1; 6796 unsigned int vactive = le16_to_cpu(timings->vactive) + 1; 6797 unsigned int vblank = le16_to_cpu(timings->vblank) + 1; 6798 unsigned int vsync = (le16_to_cpu(timings->vsync) & 0x7fff) + 1; 6799 unsigned int vsync_width = le16_to_cpu(timings->vsw) + 1; 6800 bool hsync_positive = le16_to_cpu(timings->hsync) & (1 << 15); 6801 bool vsync_positive = le16_to_cpu(timings->vsync) & (1 << 15); 6802 6803 mode = drm_mode_create(dev); 6804 if (!mode) 6805 return NULL; 6806 6807 /* resolution is kHz for type VII, and 10 kHz for type I */ 6808 mode->clock = type_7 ? pixel_clock : pixel_clock * 10; 6809 mode->hdisplay = hactive; 6810 mode->hsync_start = mode->hdisplay + hsync; 6811 mode->hsync_end = mode->hsync_start + hsync_width; 6812 mode->htotal = mode->hdisplay + hblank; 6813 6814 mode->vdisplay = vactive; 6815 mode->vsync_start = mode->vdisplay + vsync; 6816 mode->vsync_end = mode->vsync_start + vsync_width; 6817 mode->vtotal = mode->vdisplay + vblank; 6818 6819 mode->flags = 0; 6820 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 6821 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 6822 mode->type = DRM_MODE_TYPE_DRIVER; 6823 6824 if (timings->flags & 0x80) 6825 mode->type |= DRM_MODE_TYPE_PREFERRED; 6826 drm_mode_set_name(mode); 6827 6828 return mode; 6829 } 6830 6831 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 6832 const struct displayid_block *block) 6833 { 6834 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 6835 int i; 6836 int num_timings; 6837 struct drm_display_mode *newmode; 6838 int num_modes = 0; 6839 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING; 6840 /* blocks must be multiple of 20 bytes length */ 6841 if (block->num_bytes % 20) 6842 return 0; 6843 6844 num_timings = block->num_bytes / 20; 6845 for (i = 0; i < num_timings; i++) { 6846 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 6847 6848 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7); 6849 if (!newmode) 6850 continue; 6851 6852 drm_mode_probed_add(connector, newmode); 6853 num_modes++; 6854 } 6855 return num_modes; 6856 } 6857 6858 static struct drm_display_mode *drm_mode_displayid_formula(struct drm_device *dev, 6859 const struct displayid_formula_timings_9 *timings, 6860 bool type_10) 6861 { 6862 struct drm_display_mode *mode; 6863 u16 hactive = le16_to_cpu(timings->hactive) + 1; 6864 u16 vactive = le16_to_cpu(timings->vactive) + 1; 6865 u8 timing_formula = timings->flags & 0x7; 6866 6867 /* TODO: support RB-v2 & RB-v3 */ 6868 if (timing_formula > 1) 6869 return NULL; 6870 6871 /* TODO: support video-optimized refresh rate */ 6872 if (timings->flags & (1 << 4)) 6873 drm_dbg_kms(dev, "Fractional vrefresh is not implemented, proceeding with non-video-optimized refresh rate"); 6874 6875 mode = drm_cvt_mode(dev, hactive, vactive, timings->vrefresh + 1, timing_formula == 1, false, false); 6876 if (!mode) 6877 return NULL; 6878 6879 /* TODO: interpret S3D flags */ 6880 6881 mode->type = DRM_MODE_TYPE_DRIVER; 6882 drm_mode_set_name(mode); 6883 6884 return mode; 6885 } 6886 6887 static int add_displayid_formula_modes(struct drm_connector *connector, 6888 const struct displayid_block *block) 6889 { 6890 const struct displayid_formula_timing_block *formula_block = (struct displayid_formula_timing_block *)block; 6891 int num_timings; 6892 struct drm_display_mode *newmode; 6893 int num_modes = 0; 6894 bool type_10 = block->tag == DATA_BLOCK_2_TYPE_10_FORMULA_TIMING; 6895 int timing_size = 6 + ((formula_block->base.rev & 0x70) >> 4); 6896 6897 /* extended blocks are not supported yet */ 6898 if (timing_size != 6) 6899 return 0; 6900 6901 if (block->num_bytes % timing_size) 6902 return 0; 6903 6904 num_timings = block->num_bytes / timing_size; 6905 for (int i = 0; i < num_timings; i++) { 6906 const struct displayid_formula_timings_9 *timings = &formula_block->timings[i]; 6907 6908 newmode = drm_mode_displayid_formula(connector->dev, timings, type_10); 6909 if (!newmode) 6910 continue; 6911 6912 drm_mode_probed_add(connector, newmode); 6913 num_modes++; 6914 } 6915 return num_modes; 6916 } 6917 6918 static int add_displayid_detailed_modes(struct drm_connector *connector, 6919 const struct drm_edid *drm_edid) 6920 { 6921 const struct displayid_block *block; 6922 struct displayid_iter iter; 6923 int num_modes = 0; 6924 6925 displayid_iter_edid_begin(drm_edid, &iter); 6926 displayid_iter_for_each(block, &iter) { 6927 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING || 6928 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING) 6929 num_modes += add_displayid_detailed_1_modes(connector, block); 6930 else if (block->tag == DATA_BLOCK_2_TYPE_9_FORMULA_TIMING || 6931 block->tag == DATA_BLOCK_2_TYPE_10_FORMULA_TIMING) 6932 num_modes += add_displayid_formula_modes(connector, block); 6933 } 6934 displayid_iter_end(&iter); 6935 6936 return num_modes; 6937 } 6938 6939 static int _drm_edid_connector_add_modes(struct drm_connector *connector, 6940 const struct drm_edid *drm_edid) 6941 { 6942 int num_modes = 0; 6943 6944 if (!drm_edid) 6945 return 0; 6946 6947 /* 6948 * EDID spec says modes should be preferred in this order: 6949 * - preferred detailed mode 6950 * - other detailed modes from base block 6951 * - detailed modes from extension blocks 6952 * - CVT 3-byte code modes 6953 * - standard timing codes 6954 * - established timing codes 6955 * - modes inferred from GTF or CVT range information 6956 * 6957 * We get this pretty much right. 6958 * 6959 * XXX order for additional mode types in extension blocks? 6960 */ 6961 num_modes += add_detailed_modes(connector, drm_edid); 6962 num_modes += add_cvt_modes(connector, drm_edid); 6963 num_modes += add_standard_modes(connector, drm_edid); 6964 num_modes += add_established_modes(connector, drm_edid); 6965 num_modes += add_cea_modes(connector, drm_edid); 6966 num_modes += add_alternate_cea_modes(connector, drm_edid); 6967 num_modes += add_displayid_detailed_modes(connector, drm_edid); 6968 if (drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ) 6969 num_modes += add_inferred_modes(connector, drm_edid); 6970 6971 if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_PREFER_LARGE_60) || 6972 drm_edid_has_internal_quirk(connector, EDID_QUIRK_PREFER_LARGE_75)) 6973 edid_fixup_preferred(connector); 6974 6975 return num_modes; 6976 } 6977 6978 static void _drm_update_tile_info(struct drm_connector *connector, 6979 const struct drm_edid *drm_edid); 6980 6981 static int _drm_edid_connector_property_update(struct drm_connector *connector, 6982 const struct drm_edid *drm_edid) 6983 { 6984 struct drm_device *dev = connector->dev; 6985 int ret; 6986 6987 if (connector->edid_blob_ptr) { 6988 const void *old_edid = connector->edid_blob_ptr->data; 6989 size_t old_edid_size = connector->edid_blob_ptr->length; 6990 6991 if (old_edid && !drm_edid_eq(drm_edid, old_edid, old_edid_size)) { 6992 connector->epoch_counter++; 6993 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n", 6994 connector->base.id, connector->name, 6995 connector->epoch_counter); 6996 } 6997 } 6998 6999 ret = drm_property_replace_global_blob(dev, 7000 &connector->edid_blob_ptr, 7001 drm_edid ? drm_edid->size : 0, 7002 drm_edid ? drm_edid->edid : NULL, 7003 &connector->base, 7004 dev->mode_config.edid_property); 7005 if (ret) { 7006 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n", 7007 connector->base.id, connector->name, ret); 7008 goto out; 7009 } 7010 7011 ret = drm_object_property_set_value(&connector->base, 7012 dev->mode_config.non_desktop_property, 7013 connector->display_info.non_desktop); 7014 if (ret) { 7015 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n", 7016 connector->base.id, connector->name, ret); 7017 goto out; 7018 } 7019 7020 ret = drm_connector_set_tile_property(connector); 7021 if (ret) { 7022 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n", 7023 connector->base.id, connector->name, ret); 7024 goto out; 7025 } 7026 7027 out: 7028 return ret; 7029 } 7030 7031 /* For sysfs edid show implementation */ 7032 ssize_t drm_edid_connector_property_show(struct drm_connector *connector, 7033 char *buf, loff_t off, size_t count) 7034 { 7035 const void *edid; 7036 size_t size; 7037 ssize_t ret = 0; 7038 7039 mutex_lock(&connector->dev->mode_config.mutex); 7040 7041 if (!connector->edid_blob_ptr) 7042 goto unlock; 7043 7044 edid = connector->edid_blob_ptr->data; 7045 size = connector->edid_blob_ptr->length; 7046 if (!edid) 7047 goto unlock; 7048 7049 if (off >= size) 7050 goto unlock; 7051 7052 if (off + count > size) 7053 count = size - off; 7054 7055 memcpy(buf, edid + off, count); 7056 7057 ret = count; 7058 unlock: 7059 mutex_unlock(&connector->dev->mode_config.mutex); 7060 7061 return ret; 7062 } 7063 7064 /** 7065 * drm_edid_connector_update - Update connector information from EDID 7066 * @connector: Connector 7067 * @drm_edid: EDID 7068 * 7069 * Update the connector display info, ELD, HDR metadata, relevant properties, 7070 * etc. from the passed in EDID. 7071 * 7072 * If EDID is NULL, reset the information. 7073 * 7074 * Must be called before calling drm_edid_connector_add_modes(). 7075 * 7076 * Return: 0 on success, negative error on errors. 7077 */ 7078 int drm_edid_connector_update(struct drm_connector *connector, 7079 const struct drm_edid *drm_edid) 7080 { 7081 update_display_info(connector, drm_edid); 7082 7083 _drm_update_tile_info(connector, drm_edid); 7084 7085 return _drm_edid_connector_property_update(connector, drm_edid); 7086 } 7087 EXPORT_SYMBOL(drm_edid_connector_update); 7088 7089 /** 7090 * drm_edid_connector_add_modes - Update probed modes from the EDID property 7091 * @connector: Connector 7092 * 7093 * Add the modes from the previously updated EDID property to the connector 7094 * probed modes list. 7095 * 7096 * drm_edid_connector_update() must have been called before this to update the 7097 * EDID property. 7098 * 7099 * Return: The number of modes added, or 0 if we couldn't find any. 7100 */ 7101 int drm_edid_connector_add_modes(struct drm_connector *connector) 7102 { 7103 const struct drm_edid *drm_edid = NULL; 7104 int count; 7105 7106 if (connector->edid_blob_ptr) 7107 drm_edid = drm_edid_alloc(connector->edid_blob_ptr->data, 7108 connector->edid_blob_ptr->length); 7109 7110 count = _drm_edid_connector_add_modes(connector, drm_edid); 7111 7112 drm_edid_free(drm_edid); 7113 7114 return count; 7115 } 7116 EXPORT_SYMBOL(drm_edid_connector_add_modes); 7117 7118 /** 7119 * drm_connector_update_edid_property - update the edid property of a connector 7120 * @connector: drm connector 7121 * @edid: new value of the edid property 7122 * 7123 * This function creates a new blob modeset object and assigns its id to the 7124 * connector's edid property. 7125 * Since we also parse tile information from EDID's displayID block, we also 7126 * set the connector's tile property here. See drm_connector_set_tile_property() 7127 * for more details. 7128 * 7129 * This function is deprecated. Use drm_edid_connector_update() instead. 7130 * 7131 * Returns: 7132 * Zero on success, negative errno on failure. 7133 */ 7134 int drm_connector_update_edid_property(struct drm_connector *connector, 7135 const struct edid *edid) 7136 { 7137 struct drm_edid drm_edid; 7138 7139 return drm_edid_connector_update(connector, drm_edid_legacy_init(&drm_edid, edid)); 7140 } 7141 EXPORT_SYMBOL(drm_connector_update_edid_property); 7142 7143 /** 7144 * drm_add_edid_modes - add modes from EDID data, if available 7145 * @connector: connector we're probing 7146 * @edid: EDID data 7147 * 7148 * Add the specified modes to the connector's mode list. Also fills out the 7149 * &drm_display_info structure and ELD in @connector with any information which 7150 * can be derived from the edid. 7151 * 7152 * This function is deprecated. Use drm_edid_connector_add_modes() instead. 7153 * 7154 * Return: The number of modes added or 0 if we couldn't find any. 7155 */ 7156 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 7157 { 7158 struct drm_edid _drm_edid; 7159 const struct drm_edid *drm_edid; 7160 7161 if (edid && !drm_edid_is_valid(edid)) { 7162 drm_warn(connector->dev, "[CONNECTOR:%d:%s] EDID invalid.\n", 7163 connector->base.id, connector->name); 7164 edid = NULL; 7165 } 7166 7167 drm_edid = drm_edid_legacy_init(&_drm_edid, edid); 7168 7169 update_display_info(connector, drm_edid); 7170 7171 return _drm_edid_connector_add_modes(connector, drm_edid); 7172 } 7173 EXPORT_SYMBOL(drm_add_edid_modes); 7174 7175 /** 7176 * drm_add_modes_noedid - add modes for the connectors without EDID 7177 * @connector: connector we're probing 7178 * @hdisplay: the horizontal display limit 7179 * @vdisplay: the vertical display limit 7180 * 7181 * Add the specified modes to the connector's mode list. Only when the 7182 * hdisplay/vdisplay is not beyond the given limit, it will be added. 7183 * 7184 * Return: The number of modes added or 0 if we couldn't find any. 7185 */ 7186 int drm_add_modes_noedid(struct drm_connector *connector, 7187 unsigned int hdisplay, unsigned int vdisplay) 7188 { 7189 int i, count = ARRAY_SIZE(drm_dmt_modes), num_modes = 0; 7190 struct drm_display_mode *mode; 7191 struct drm_device *dev = connector->dev; 7192 7193 for (i = 0; i < count; i++) { 7194 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 7195 7196 if (hdisplay && vdisplay) { 7197 /* 7198 * Only when two are valid, they will be used to check 7199 * whether the mode should be added to the mode list of 7200 * the connector. 7201 */ 7202 if (ptr->hdisplay > hdisplay || 7203 ptr->vdisplay > vdisplay) 7204 continue; 7205 } 7206 if (drm_mode_vrefresh(ptr) > 61) 7207 continue; 7208 mode = drm_mode_duplicate(dev, ptr); 7209 if (mode) { 7210 drm_mode_probed_add(connector, mode); 7211 num_modes++; 7212 } 7213 } 7214 return num_modes; 7215 } 7216 EXPORT_SYMBOL(drm_add_modes_noedid); 7217 7218 static bool is_hdmi2_sink(const struct drm_connector *connector) 7219 { 7220 /* 7221 * FIXME: sil-sii8620 doesn't have a connector around when 7222 * we need one, so we have to be prepared for a NULL connector. 7223 */ 7224 if (!connector) 7225 return true; 7226 7227 return connector->display_info.hdmi.scdc.supported || 7228 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420; 7229 } 7230 7231 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector, 7232 const struct drm_display_mode *mode) 7233 { 7234 bool has_hdmi_infoframe = connector ? 7235 connector->display_info.has_hdmi_infoframe : false; 7236 7237 if (!has_hdmi_infoframe) 7238 return 0; 7239 7240 /* No HDMI VIC when signalling 3D video format */ 7241 if (mode->flags & DRM_MODE_FLAG_3D_MASK) 7242 return 0; 7243 7244 return drm_match_hdmi_mode(mode); 7245 } 7246 7247 static u8 drm_mode_cea_vic(const struct drm_connector *connector, 7248 const struct drm_display_mode *mode) 7249 { 7250 /* 7251 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 7252 * we should send its VIC in vendor infoframes, else send the 7253 * VIC in AVI infoframes. Lets check if this mode is present in 7254 * HDMI 1.4b 4K modes 7255 */ 7256 if (drm_mode_hdmi_vic(connector, mode)) 7257 return 0; 7258 7259 return drm_match_cea_mode(mode); 7260 } 7261 7262 /* 7263 * Avoid sending VICs defined in HDMI 2.0 in AVI infoframes to sinks that 7264 * conform to HDMI 1.4. 7265 * 7266 * HDMI 1.4 (CTA-861-D) VIC range: [1..64] 7267 * HDMI 2.0 (CTA-861-F) VIC range: [1..107] 7268 * 7269 * If the sink lists the VIC in CTA VDB, assume it's fine, regardless of HDMI 7270 * version. 7271 */ 7272 static u8 vic_for_avi_infoframe(const struct drm_connector *connector, u8 vic) 7273 { 7274 if (!is_hdmi2_sink(connector) && vic > 64 && 7275 !cta_vdb_has_vic(connector, vic)) 7276 return 0; 7277 7278 return vic; 7279 } 7280 7281 /** 7282 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 7283 * data from a DRM display mode 7284 * @frame: HDMI AVI infoframe 7285 * @connector: the connector 7286 * @mode: DRM display mode 7287 * 7288 * Return: 0 on success or a negative error code on failure. 7289 */ 7290 int 7291 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 7292 const struct drm_connector *connector, 7293 const struct drm_display_mode *mode) 7294 { 7295 enum hdmi_picture_aspect picture_aspect; 7296 u8 vic, hdmi_vic; 7297 7298 if (!frame || !mode) 7299 return -EINVAL; 7300 7301 hdmi_avi_infoframe_init(frame); 7302 7303 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 7304 frame->pixel_repeat = 1; 7305 7306 vic = drm_mode_cea_vic(connector, mode); 7307 hdmi_vic = drm_mode_hdmi_vic(connector, mode); 7308 7309 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 7310 7311 /* 7312 * As some drivers don't support atomic, we can't use connector state. 7313 * So just initialize the frame with default values, just the same way 7314 * as it's done with other properties here. 7315 */ 7316 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; 7317 frame->itc = 0; 7318 7319 /* 7320 * Populate picture aspect ratio from either 7321 * user input (if specified) or from the CEA/HDMI mode lists. 7322 */ 7323 picture_aspect = mode->picture_aspect_ratio; 7324 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) { 7325 if (vic) 7326 picture_aspect = drm_get_cea_aspect_ratio(vic); 7327 else if (hdmi_vic) 7328 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic); 7329 } 7330 7331 /* 7332 * The infoframe can't convey anything but none, 4:3 7333 * and 16:9, so if the user has asked for anything else 7334 * we can only satisfy it by specifying the right VIC. 7335 */ 7336 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { 7337 if (vic) { 7338 if (picture_aspect != drm_get_cea_aspect_ratio(vic)) 7339 return -EINVAL; 7340 } else if (hdmi_vic) { 7341 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic)) 7342 return -EINVAL; 7343 } else { 7344 return -EINVAL; 7345 } 7346 7347 picture_aspect = HDMI_PICTURE_ASPECT_NONE; 7348 } 7349 7350 frame->video_code = vic_for_avi_infoframe(connector, vic); 7351 frame->picture_aspect = picture_aspect; 7352 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 7353 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 7354 7355 return 0; 7356 } 7357 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 7358 7359 /** 7360 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 7361 * quantization range information 7362 * @frame: HDMI AVI infoframe 7363 * @connector: the connector 7364 * @mode: DRM display mode 7365 * @rgb_quant_range: RGB quantization range (Q) 7366 */ 7367 void 7368 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 7369 const struct drm_connector *connector, 7370 const struct drm_display_mode *mode, 7371 enum hdmi_quantization_range rgb_quant_range) 7372 { 7373 const struct drm_display_info *info = &connector->display_info; 7374 7375 /* 7376 * CEA-861: 7377 * "A Source shall not send a non-zero Q value that does not correspond 7378 * to the default RGB Quantization Range for the transmitted Picture 7379 * unless the Sink indicates support for the Q bit in a Video 7380 * Capabilities Data Block." 7381 * 7382 * HDMI 2.0 recommends sending non-zero Q when it does match the 7383 * default RGB quantization range for the mode, even when QS=0. 7384 */ 7385 if (info->rgb_quant_range_selectable || 7386 rgb_quant_range == drm_default_rgb_quant_range(mode)) 7387 frame->quantization_range = rgb_quant_range; 7388 else 7389 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 7390 7391 /* 7392 * CEA-861-F: 7393 * "When transmitting any RGB colorimetry, the Source should set the 7394 * YQ-field to match the RGB Quantization Range being transmitted 7395 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 7396 * set YQ=1) and the Sink shall ignore the YQ-field." 7397 * 7398 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused 7399 * by non-zero YQ when receiving RGB. There doesn't seem to be any 7400 * good way to tell which version of CEA-861 the sink supports, so 7401 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based 7402 * on CEA-861-F. 7403 */ 7404 if (!is_hdmi2_sink(connector) || 7405 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 7406 frame->ycc_quantization_range = 7407 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 7408 else 7409 frame->ycc_quantization_range = 7410 HDMI_YCC_QUANTIZATION_RANGE_FULL; 7411 } 7412 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 7413 7414 static enum hdmi_3d_structure 7415 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 7416 { 7417 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 7418 7419 switch (layout) { 7420 case DRM_MODE_FLAG_3D_FRAME_PACKING: 7421 return HDMI_3D_STRUCTURE_FRAME_PACKING; 7422 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 7423 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 7424 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 7425 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 7426 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 7427 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 7428 case DRM_MODE_FLAG_3D_L_DEPTH: 7429 return HDMI_3D_STRUCTURE_L_DEPTH; 7430 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 7431 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 7432 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 7433 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 7434 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 7435 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 7436 default: 7437 return HDMI_3D_STRUCTURE_INVALID; 7438 } 7439 } 7440 7441 /** 7442 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 7443 * data from a DRM display mode 7444 * @frame: HDMI vendor infoframe 7445 * @connector: the connector 7446 * @mode: DRM display mode 7447 * 7448 * Note that there's is a need to send HDMI vendor infoframes only when using a 7449 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 7450 * function will return -EINVAL, error that can be safely ignored. 7451 * 7452 * Return: 0 on success or a negative error code on failure. 7453 */ 7454 int 7455 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 7456 const struct drm_connector *connector, 7457 const struct drm_display_mode *mode) 7458 { 7459 /* 7460 * FIXME: sil-sii8620 doesn't have a connector around when 7461 * we need one, so we have to be prepared for a NULL connector. 7462 */ 7463 bool has_hdmi_infoframe = connector ? 7464 connector->display_info.has_hdmi_infoframe : false; 7465 int err; 7466 7467 if (!frame || !mode) 7468 return -EINVAL; 7469 7470 if (!has_hdmi_infoframe) 7471 return -EINVAL; 7472 7473 err = hdmi_vendor_infoframe_init(frame); 7474 if (err < 0) 7475 return err; 7476 7477 /* 7478 * Even if it's not absolutely necessary to send the infoframe 7479 * (ie.vic==0 and s3d_struct==0) we will still send it if we 7480 * know that the sink can handle it. This is based on a 7481 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks 7482 * have trouble realizing that they should switch from 3D to 2D 7483 * mode if the source simply stops sending the infoframe when 7484 * it wants to switch from 3D to 2D. 7485 */ 7486 frame->vic = drm_mode_hdmi_vic(connector, mode); 7487 frame->s3d_struct = s3d_structure_from_display_mode(mode); 7488 7489 return 0; 7490 } 7491 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 7492 7493 static void drm_parse_tiled_block(struct drm_connector *connector, 7494 const struct displayid_block *block) 7495 { 7496 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 7497 u16 w, h; 7498 u8 tile_v_loc, tile_h_loc; 7499 u8 num_v_tile, num_h_tile; 7500 struct drm_tile_group *tg; 7501 7502 w = tile->tile_size[0] | tile->tile_size[1] << 8; 7503 h = tile->tile_size[2] | tile->tile_size[3] << 8; 7504 7505 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 7506 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 7507 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 7508 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 7509 7510 connector->has_tile = true; 7511 if (tile->tile_cap & 0x80) 7512 connector->tile_is_single_monitor = true; 7513 7514 connector->num_h_tile = num_h_tile + 1; 7515 connector->num_v_tile = num_v_tile + 1; 7516 connector->tile_h_loc = tile_h_loc; 7517 connector->tile_v_loc = tile_v_loc; 7518 connector->tile_h_size = w + 1; 7519 connector->tile_v_size = h + 1; 7520 7521 drm_dbg_kms(connector->dev, 7522 "[CONNECTOR:%d:%s] tile cap 0x%x, size %dx%d, num tiles %dx%d, location %dx%d, vend %c%c%c", 7523 connector->base.id, connector->name, 7524 tile->tile_cap, 7525 connector->tile_h_size, connector->tile_v_size, 7526 connector->num_h_tile, connector->num_v_tile, 7527 connector->tile_h_loc, connector->tile_v_loc, 7528 tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 7529 7530 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 7531 if (!tg) 7532 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 7533 if (!tg) 7534 return; 7535 7536 if (connector->tile_group != tg) { 7537 /* if we haven't got a pointer, 7538 take the reference, drop ref to old tile group */ 7539 if (connector->tile_group) 7540 drm_mode_put_tile_group(connector->dev, connector->tile_group); 7541 connector->tile_group = tg; 7542 } else { 7543 /* if same tile group, then release the ref we just took. */ 7544 drm_mode_put_tile_group(connector->dev, tg); 7545 } 7546 } 7547 7548 static bool displayid_is_tiled_block(const struct displayid_iter *iter, 7549 const struct displayid_block *block) 7550 { 7551 return (displayid_version(iter) < DISPLAY_ID_STRUCTURE_VER_20 && 7552 block->tag == DATA_BLOCK_TILED_DISPLAY) || 7553 (displayid_version(iter) == DISPLAY_ID_STRUCTURE_VER_20 && 7554 block->tag == DATA_BLOCK_2_TILED_DISPLAY_TOPOLOGY); 7555 } 7556 7557 static void _drm_update_tile_info(struct drm_connector *connector, 7558 const struct drm_edid *drm_edid) 7559 { 7560 const struct displayid_block *block; 7561 struct displayid_iter iter; 7562 7563 connector->has_tile = false; 7564 7565 displayid_iter_edid_begin(drm_edid, &iter); 7566 displayid_iter_for_each(block, &iter) { 7567 if (displayid_is_tiled_block(&iter, block)) 7568 drm_parse_tiled_block(connector, block); 7569 } 7570 displayid_iter_end(&iter); 7571 7572 if (!connector->has_tile && connector->tile_group) { 7573 drm_mode_put_tile_group(connector->dev, connector->tile_group); 7574 connector->tile_group = NULL; 7575 } 7576 } 7577 7578 /** 7579 * drm_edid_is_digital - is digital? 7580 * @drm_edid: The EDID 7581 * 7582 * Return true if input is digital. 7583 */ 7584 bool drm_edid_is_digital(const struct drm_edid *drm_edid) 7585 { 7586 return drm_edid && drm_edid->edid && 7587 drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL; 7588 } 7589 EXPORT_SYMBOL(drm_edid_is_digital); 7590