1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 31 #include <linux/hdmi.h> 32 #include <linux/i2c.h> 33 #include <linux/kernel.h> 34 #include <linux/module.h> 35 #include <linux/slab.h> 36 #include <linux/vga_switcheroo.h> 37 38 #include <drm/drm_displayid.h> 39 #include <drm/drm_drv.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_encoder.h> 42 #include <drm/drm_print.h> 43 #include <drm/drm_scdc_helper.h> 44 45 #include "drm_crtc_internal.h" 46 47 #define version_greater(edid, maj, min) \ 48 (((edid)->version > (maj)) || \ 49 ((edid)->version == (maj) && (edid)->revision > (min))) 50 51 #define EDID_EST_TIMINGS 16 52 #define EDID_STD_TIMINGS 8 53 #define EDID_DETAILED_TIMINGS 4 54 55 /* 56 * EDID blocks out in the wild have a variety of bugs, try to collect 57 * them here (note that userspace may work around broken monitors first, 58 * but fixes should make their way here so that the kernel "just works" 59 * on as many displays as possible). 60 */ 61 62 /* First detailed mode wrong, use largest 60Hz mode */ 63 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 64 /* Reported 135MHz pixel clock is too high, needs adjustment */ 65 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 66 /* Prefer the largest mode at 75 Hz */ 67 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 68 /* Detail timing is in cm not mm */ 69 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 70 /* Detailed timing descriptors have bogus size values, so just take the 71 * maximum size and use that. 72 */ 73 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 74 /* use +hsync +vsync for detailed mode */ 75 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 76 /* Force reduced-blanking timings for detailed modes */ 77 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 78 /* Force 8bpc */ 79 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 80 /* Force 12bpc */ 81 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 82 /* Force 6bpc */ 83 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 84 /* Force 10bpc */ 85 #define EDID_QUIRK_FORCE_10BPC (1 << 11) 86 /* Non desktop display (i.e. HMD) */ 87 #define EDID_QUIRK_NON_DESKTOP (1 << 12) 88 89 struct detailed_mode_closure { 90 struct drm_connector *connector; 91 struct edid *edid; 92 bool preferred; 93 u32 quirks; 94 int modes; 95 }; 96 97 #define LEVEL_DMT 0 98 #define LEVEL_GTF 1 99 #define LEVEL_GTF2 2 100 #define LEVEL_CVT 3 101 102 static const struct edid_quirk { 103 char vendor[4]; 104 int product_id; 105 u32 quirks; 106 } edid_quirk_list[] = { 107 /* Acer AL1706 */ 108 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 109 /* Acer F51 */ 110 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 111 112 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 113 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 114 115 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */ 116 { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC }, 117 118 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 119 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC }, 120 121 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ 122 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC }, 123 124 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ 125 { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC }, 126 127 /* Belinea 10 15 55 */ 128 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 129 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 130 131 /* Envision Peripherals, Inc. EN-7100e */ 132 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 133 /* Envision EN2028 */ 134 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 135 136 /* Funai Electronics PM36B */ 137 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 138 EDID_QUIRK_DETAILED_IN_CM }, 139 140 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 141 { "LGD", 764, EDID_QUIRK_FORCE_10BPC }, 142 143 /* LG Philips LCD LP154W01-A5 */ 144 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 145 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 146 147 /* Samsung SyncMaster 205BW. Note: irony */ 148 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 149 /* Samsung SyncMaster 22[5-6]BW */ 150 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 151 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 152 153 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 154 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 155 156 /* ViewSonic VA2026w */ 157 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 158 159 /* Medion MD 30217 PG */ 160 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 161 162 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 163 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 164 165 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 166 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, 167 168 /* Valve Index Headset */ 169 { "VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP }, 170 { "VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP }, 171 { "VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP }, 172 { "VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP }, 173 { "VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP }, 174 { "VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP }, 175 { "VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP }, 176 { "VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP }, 177 { "VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP }, 178 { "VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP }, 179 { "VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP }, 180 { "VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP }, 181 { "VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP }, 182 { "VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP }, 183 { "VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP }, 184 { "VLV", 0x91be, EDID_QUIRK_NON_DESKTOP }, 185 { "VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP }, 186 187 /* HTC Vive and Vive Pro VR Headsets */ 188 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP }, 189 { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP }, 190 191 /* Oculus Rift DK1, DK2, and CV1 VR Headsets */ 192 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP }, 193 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP }, 194 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP }, 195 196 /* Windows Mixed Reality Headsets */ 197 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP }, 198 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP }, 199 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP }, 200 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP }, 201 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP }, 202 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP }, 203 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP }, 204 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP }, 205 206 /* Sony PlayStation VR Headset */ 207 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP }, 208 209 /* Sensics VR Headsets */ 210 { "SEN", 0x1019, EDID_QUIRK_NON_DESKTOP }, 211 212 /* OSVR HDK and HDK2 VR Headsets */ 213 { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP }, 214 }; 215 216 /* 217 * Autogenerated from the DMT spec. 218 * This table is copied from xfree86/modes/xf86EdidModes.c. 219 */ 220 static const struct drm_display_mode drm_dmt_modes[] = { 221 /* 0x01 - 640x350@85Hz */ 222 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 223 736, 832, 0, 350, 382, 385, 445, 0, 224 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 225 /* 0x02 - 640x400@85Hz */ 226 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 227 736, 832, 0, 400, 401, 404, 445, 0, 228 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 229 /* 0x03 - 720x400@85Hz */ 230 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 231 828, 936, 0, 400, 401, 404, 446, 0, 232 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 233 /* 0x04 - 640x480@60Hz */ 234 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 235 752, 800, 0, 480, 490, 492, 525, 0, 236 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 237 /* 0x05 - 640x480@72Hz */ 238 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 239 704, 832, 0, 480, 489, 492, 520, 0, 240 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 241 /* 0x06 - 640x480@75Hz */ 242 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 243 720, 840, 0, 480, 481, 484, 500, 0, 244 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 245 /* 0x07 - 640x480@85Hz */ 246 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 247 752, 832, 0, 480, 481, 484, 509, 0, 248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 249 /* 0x08 - 800x600@56Hz */ 250 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 251 896, 1024, 0, 600, 601, 603, 625, 0, 252 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 253 /* 0x09 - 800x600@60Hz */ 254 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 255 968, 1056, 0, 600, 601, 605, 628, 0, 256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 257 /* 0x0a - 800x600@72Hz */ 258 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 259 976, 1040, 0, 600, 637, 643, 666, 0, 260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 261 /* 0x0b - 800x600@75Hz */ 262 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 263 896, 1056, 0, 600, 601, 604, 625, 0, 264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 265 /* 0x0c - 800x600@85Hz */ 266 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 267 896, 1048, 0, 600, 601, 604, 631, 0, 268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 269 /* 0x0d - 800x600@120Hz RB */ 270 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 271 880, 960, 0, 600, 603, 607, 636, 0, 272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 273 /* 0x0e - 848x480@60Hz */ 274 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 275 976, 1088, 0, 480, 486, 494, 517, 0, 276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 277 /* 0x0f - 1024x768@43Hz, interlace */ 278 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 279 1208, 1264, 0, 768, 768, 776, 817, 0, 280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 281 DRM_MODE_FLAG_INTERLACE) }, 282 /* 0x10 - 1024x768@60Hz */ 283 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 284 1184, 1344, 0, 768, 771, 777, 806, 0, 285 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 286 /* 0x11 - 1024x768@70Hz */ 287 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 288 1184, 1328, 0, 768, 771, 777, 806, 0, 289 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 290 /* 0x12 - 1024x768@75Hz */ 291 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 292 1136, 1312, 0, 768, 769, 772, 800, 0, 293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 294 /* 0x13 - 1024x768@85Hz */ 295 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 296 1168, 1376, 0, 768, 769, 772, 808, 0, 297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 298 /* 0x14 - 1024x768@120Hz RB */ 299 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 300 1104, 1184, 0, 768, 771, 775, 813, 0, 301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 302 /* 0x15 - 1152x864@75Hz */ 303 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 304 1344, 1600, 0, 864, 865, 868, 900, 0, 305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 306 /* 0x55 - 1280x720@60Hz */ 307 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 308 1430, 1650, 0, 720, 725, 730, 750, 0, 309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 310 /* 0x16 - 1280x768@60Hz RB */ 311 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 312 1360, 1440, 0, 768, 771, 778, 790, 0, 313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 314 /* 0x17 - 1280x768@60Hz */ 315 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 316 1472, 1664, 0, 768, 771, 778, 798, 0, 317 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 318 /* 0x18 - 1280x768@75Hz */ 319 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 320 1488, 1696, 0, 768, 771, 778, 805, 0, 321 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 322 /* 0x19 - 1280x768@85Hz */ 323 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 324 1496, 1712, 0, 768, 771, 778, 809, 0, 325 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 326 /* 0x1a - 1280x768@120Hz RB */ 327 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 328 1360, 1440, 0, 768, 771, 778, 813, 0, 329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 330 /* 0x1b - 1280x800@60Hz RB */ 331 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 332 1360, 1440, 0, 800, 803, 809, 823, 0, 333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 334 /* 0x1c - 1280x800@60Hz */ 335 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 336 1480, 1680, 0, 800, 803, 809, 831, 0, 337 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 338 /* 0x1d - 1280x800@75Hz */ 339 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 340 1488, 1696, 0, 800, 803, 809, 838, 0, 341 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 342 /* 0x1e - 1280x800@85Hz */ 343 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 344 1496, 1712, 0, 800, 803, 809, 843, 0, 345 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 346 /* 0x1f - 1280x800@120Hz RB */ 347 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 348 1360, 1440, 0, 800, 803, 809, 847, 0, 349 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 350 /* 0x20 - 1280x960@60Hz */ 351 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 352 1488, 1800, 0, 960, 961, 964, 1000, 0, 353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 354 /* 0x21 - 1280x960@85Hz */ 355 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 356 1504, 1728, 0, 960, 961, 964, 1011, 0, 357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 358 /* 0x22 - 1280x960@120Hz RB */ 359 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 360 1360, 1440, 0, 960, 963, 967, 1017, 0, 361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 362 /* 0x23 - 1280x1024@60Hz */ 363 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 364 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 366 /* 0x24 - 1280x1024@75Hz */ 367 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 368 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 370 /* 0x25 - 1280x1024@85Hz */ 371 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 372 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 374 /* 0x26 - 1280x1024@120Hz RB */ 375 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 376 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 378 /* 0x27 - 1360x768@60Hz */ 379 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 380 1536, 1792, 0, 768, 771, 777, 795, 0, 381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 382 /* 0x28 - 1360x768@120Hz RB */ 383 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 384 1440, 1520, 0, 768, 771, 776, 813, 0, 385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 386 /* 0x51 - 1366x768@60Hz */ 387 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 388 1579, 1792, 0, 768, 771, 774, 798, 0, 389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 390 /* 0x56 - 1366x768@60Hz */ 391 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 392 1436, 1500, 0, 768, 769, 772, 800, 0, 393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 394 /* 0x29 - 1400x1050@60Hz RB */ 395 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 396 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 398 /* 0x2a - 1400x1050@60Hz */ 399 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 400 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 401 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 402 /* 0x2b - 1400x1050@75Hz */ 403 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 404 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 405 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 406 /* 0x2c - 1400x1050@85Hz */ 407 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 408 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 409 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 410 /* 0x2d - 1400x1050@120Hz RB */ 411 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 412 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 413 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 414 /* 0x2e - 1440x900@60Hz RB */ 415 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 416 1520, 1600, 0, 900, 903, 909, 926, 0, 417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 418 /* 0x2f - 1440x900@60Hz */ 419 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 420 1672, 1904, 0, 900, 903, 909, 934, 0, 421 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 422 /* 0x30 - 1440x900@75Hz */ 423 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 424 1688, 1936, 0, 900, 903, 909, 942, 0, 425 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 426 /* 0x31 - 1440x900@85Hz */ 427 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 428 1696, 1952, 0, 900, 903, 909, 948, 0, 429 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 430 /* 0x32 - 1440x900@120Hz RB */ 431 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 432 1520, 1600, 0, 900, 903, 909, 953, 0, 433 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 434 /* 0x53 - 1600x900@60Hz */ 435 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 436 1704, 1800, 0, 900, 901, 904, 1000, 0, 437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 438 /* 0x33 - 1600x1200@60Hz */ 439 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 440 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 442 /* 0x34 - 1600x1200@65Hz */ 443 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 444 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 446 /* 0x35 - 1600x1200@70Hz */ 447 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 448 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 450 /* 0x36 - 1600x1200@75Hz */ 451 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 452 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 454 /* 0x37 - 1600x1200@85Hz */ 455 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 456 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 458 /* 0x38 - 1600x1200@120Hz RB */ 459 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 460 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 462 /* 0x39 - 1680x1050@60Hz RB */ 463 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 464 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 466 /* 0x3a - 1680x1050@60Hz */ 467 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 468 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 469 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 470 /* 0x3b - 1680x1050@75Hz */ 471 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 472 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 473 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 474 /* 0x3c - 1680x1050@85Hz */ 475 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 476 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 477 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 478 /* 0x3d - 1680x1050@120Hz RB */ 479 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 480 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 482 /* 0x3e - 1792x1344@60Hz */ 483 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 484 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 485 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 486 /* 0x3f - 1792x1344@75Hz */ 487 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 488 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 490 /* 0x40 - 1792x1344@120Hz RB */ 491 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 492 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 494 /* 0x41 - 1856x1392@60Hz */ 495 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 496 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 497 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 498 /* 0x42 - 1856x1392@75Hz */ 499 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 500 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 501 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 502 /* 0x43 - 1856x1392@120Hz RB */ 503 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 504 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 506 /* 0x52 - 1920x1080@60Hz */ 507 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 508 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 509 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 510 /* 0x44 - 1920x1200@60Hz RB */ 511 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 512 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 513 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 514 /* 0x45 - 1920x1200@60Hz */ 515 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 516 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 517 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 518 /* 0x46 - 1920x1200@75Hz */ 519 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 520 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 521 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 522 /* 0x47 - 1920x1200@85Hz */ 523 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 524 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 525 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 526 /* 0x48 - 1920x1200@120Hz RB */ 527 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 528 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 529 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 530 /* 0x49 - 1920x1440@60Hz */ 531 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 532 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 533 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 534 /* 0x4a - 1920x1440@75Hz */ 535 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 536 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 538 /* 0x4b - 1920x1440@120Hz RB */ 539 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 540 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 541 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 542 /* 0x54 - 2048x1152@60Hz */ 543 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 544 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 545 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 546 /* 0x4c - 2560x1600@60Hz RB */ 547 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 548 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 549 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 550 /* 0x4d - 2560x1600@60Hz */ 551 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 552 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 553 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 554 /* 0x4e - 2560x1600@75Hz */ 555 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 556 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 557 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 558 /* 0x4f - 2560x1600@85Hz */ 559 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 560 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 561 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 562 /* 0x50 - 2560x1600@120Hz RB */ 563 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 564 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 566 /* 0x57 - 4096x2160@60Hz RB */ 567 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 568 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 570 /* 0x58 - 4096x2160@59.94Hz RB */ 571 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 572 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 573 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 574 }; 575 576 /* 577 * These more or less come from the DMT spec. The 720x400 modes are 578 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 579 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 580 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 581 * mode. 582 * 583 * The DMT modes have been fact-checked; the rest are mild guesses. 584 */ 585 static const struct drm_display_mode edid_est_modes[] = { 586 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 587 968, 1056, 0, 600, 601, 605, 628, 0, 588 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 589 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 590 896, 1024, 0, 600, 601, 603, 625, 0, 591 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 592 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 593 720, 840, 0, 480, 481, 484, 500, 0, 594 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 595 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 596 704, 832, 0, 480, 489, 492, 520, 0, 597 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 598 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 599 768, 864, 0, 480, 483, 486, 525, 0, 600 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 601 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 602 752, 800, 0, 480, 490, 492, 525, 0, 603 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 604 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 605 846, 900, 0, 400, 421, 423, 449, 0, 606 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 607 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 608 846, 900, 0, 400, 412, 414, 449, 0, 609 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 610 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 611 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 612 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 613 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 614 1136, 1312, 0, 768, 769, 772, 800, 0, 615 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 616 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 617 1184, 1328, 0, 768, 771, 777, 806, 0, 618 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 619 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 620 1184, 1344, 0, 768, 771, 777, 806, 0, 621 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 622 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 623 1208, 1264, 0, 768, 768, 776, 817, 0, 624 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 625 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 626 928, 1152, 0, 624, 625, 628, 667, 0, 627 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 628 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 629 896, 1056, 0, 600, 601, 604, 625, 0, 630 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 631 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 632 976, 1040, 0, 600, 637, 643, 666, 0, 633 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 634 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 635 1344, 1600, 0, 864, 865, 868, 900, 0, 636 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 637 }; 638 639 struct minimode { 640 short w; 641 short h; 642 short r; 643 short rb; 644 }; 645 646 static const struct minimode est3_modes[] = { 647 /* byte 6 */ 648 { 640, 350, 85, 0 }, 649 { 640, 400, 85, 0 }, 650 { 720, 400, 85, 0 }, 651 { 640, 480, 85, 0 }, 652 { 848, 480, 60, 0 }, 653 { 800, 600, 85, 0 }, 654 { 1024, 768, 85, 0 }, 655 { 1152, 864, 75, 0 }, 656 /* byte 7 */ 657 { 1280, 768, 60, 1 }, 658 { 1280, 768, 60, 0 }, 659 { 1280, 768, 75, 0 }, 660 { 1280, 768, 85, 0 }, 661 { 1280, 960, 60, 0 }, 662 { 1280, 960, 85, 0 }, 663 { 1280, 1024, 60, 0 }, 664 { 1280, 1024, 85, 0 }, 665 /* byte 8 */ 666 { 1360, 768, 60, 0 }, 667 { 1440, 900, 60, 1 }, 668 { 1440, 900, 60, 0 }, 669 { 1440, 900, 75, 0 }, 670 { 1440, 900, 85, 0 }, 671 { 1400, 1050, 60, 1 }, 672 { 1400, 1050, 60, 0 }, 673 { 1400, 1050, 75, 0 }, 674 /* byte 9 */ 675 { 1400, 1050, 85, 0 }, 676 { 1680, 1050, 60, 1 }, 677 { 1680, 1050, 60, 0 }, 678 { 1680, 1050, 75, 0 }, 679 { 1680, 1050, 85, 0 }, 680 { 1600, 1200, 60, 0 }, 681 { 1600, 1200, 65, 0 }, 682 { 1600, 1200, 70, 0 }, 683 /* byte 10 */ 684 { 1600, 1200, 75, 0 }, 685 { 1600, 1200, 85, 0 }, 686 { 1792, 1344, 60, 0 }, 687 { 1792, 1344, 75, 0 }, 688 { 1856, 1392, 60, 0 }, 689 { 1856, 1392, 75, 0 }, 690 { 1920, 1200, 60, 1 }, 691 { 1920, 1200, 60, 0 }, 692 /* byte 11 */ 693 { 1920, 1200, 75, 0 }, 694 { 1920, 1200, 85, 0 }, 695 { 1920, 1440, 60, 0 }, 696 { 1920, 1440, 75, 0 }, 697 }; 698 699 static const struct minimode extra_modes[] = { 700 { 1024, 576, 60, 0 }, 701 { 1366, 768, 60, 0 }, 702 { 1600, 900, 60, 0 }, 703 { 1680, 945, 60, 0 }, 704 { 1920, 1080, 60, 0 }, 705 { 2048, 1152, 60, 0 }, 706 { 2048, 1536, 60, 0 }, 707 }; 708 709 /* 710 * Probably taken from CEA-861 spec. 711 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. 712 * 713 * Index using the VIC. 714 */ 715 static const struct drm_display_mode edid_cea_modes[] = { 716 /* 0 - dummy, VICs start at 1 */ 717 { }, 718 /* 1 - 640x480@60Hz 4:3 */ 719 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 720 752, 800, 0, 480, 490, 492, 525, 0, 721 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 722 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 723 /* 2 - 720x480@60Hz 4:3 */ 724 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 725 798, 858, 0, 480, 489, 495, 525, 0, 726 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 727 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 728 /* 3 - 720x480@60Hz 16:9 */ 729 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 730 798, 858, 0, 480, 489, 495, 525, 0, 731 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 732 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 733 /* 4 - 1280x720@60Hz 16:9 */ 734 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 735 1430, 1650, 0, 720, 725, 730, 750, 0, 736 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 737 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 738 /* 5 - 1920x1080i@60Hz 16:9 */ 739 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 740 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 741 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 742 DRM_MODE_FLAG_INTERLACE), 743 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 744 /* 6 - 720(1440)x480i@60Hz 4:3 */ 745 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 746 801, 858, 0, 480, 488, 494, 525, 0, 747 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 748 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 749 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 750 /* 7 - 720(1440)x480i@60Hz 16:9 */ 751 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 752 801, 858, 0, 480, 488, 494, 525, 0, 753 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 754 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 755 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 756 /* 8 - 720(1440)x240@60Hz 4:3 */ 757 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 758 801, 858, 0, 240, 244, 247, 262, 0, 759 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 760 DRM_MODE_FLAG_DBLCLK), 761 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 762 /* 9 - 720(1440)x240@60Hz 16:9 */ 763 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 764 801, 858, 0, 240, 244, 247, 262, 0, 765 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 766 DRM_MODE_FLAG_DBLCLK), 767 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 768 /* 10 - 2880x480i@60Hz 4:3 */ 769 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 770 3204, 3432, 0, 480, 488, 494, 525, 0, 771 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 772 DRM_MODE_FLAG_INTERLACE), 773 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 774 /* 11 - 2880x480i@60Hz 16:9 */ 775 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 776 3204, 3432, 0, 480, 488, 494, 525, 0, 777 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 778 DRM_MODE_FLAG_INTERLACE), 779 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 780 /* 12 - 2880x240@60Hz 4:3 */ 781 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 782 3204, 3432, 0, 240, 244, 247, 262, 0, 783 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 784 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 785 /* 13 - 2880x240@60Hz 16:9 */ 786 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 787 3204, 3432, 0, 240, 244, 247, 262, 0, 788 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 789 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 790 /* 14 - 1440x480@60Hz 4:3 */ 791 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 792 1596, 1716, 0, 480, 489, 495, 525, 0, 793 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 794 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 795 /* 15 - 1440x480@60Hz 16:9 */ 796 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 797 1596, 1716, 0, 480, 489, 495, 525, 0, 798 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 799 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 800 /* 16 - 1920x1080@60Hz 16:9 */ 801 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 802 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 803 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 804 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 805 /* 17 - 720x576@50Hz 4:3 */ 806 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 807 796, 864, 0, 576, 581, 586, 625, 0, 808 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 809 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 810 /* 18 - 720x576@50Hz 16:9 */ 811 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 812 796, 864, 0, 576, 581, 586, 625, 0, 813 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 814 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 815 /* 19 - 1280x720@50Hz 16:9 */ 816 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 817 1760, 1980, 0, 720, 725, 730, 750, 0, 818 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 819 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 820 /* 20 - 1920x1080i@50Hz 16:9 */ 821 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 822 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 823 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 824 DRM_MODE_FLAG_INTERLACE), 825 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 826 /* 21 - 720(1440)x576i@50Hz 4:3 */ 827 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 828 795, 864, 0, 576, 580, 586, 625, 0, 829 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 830 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 831 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 832 /* 22 - 720(1440)x576i@50Hz 16:9 */ 833 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 834 795, 864, 0, 576, 580, 586, 625, 0, 835 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 836 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 837 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 838 /* 23 - 720(1440)x288@50Hz 4:3 */ 839 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 840 795, 864, 0, 288, 290, 293, 312, 0, 841 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 842 DRM_MODE_FLAG_DBLCLK), 843 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 844 /* 24 - 720(1440)x288@50Hz 16:9 */ 845 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 846 795, 864, 0, 288, 290, 293, 312, 0, 847 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 848 DRM_MODE_FLAG_DBLCLK), 849 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 850 /* 25 - 2880x576i@50Hz 4:3 */ 851 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 852 3180, 3456, 0, 576, 580, 586, 625, 0, 853 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 854 DRM_MODE_FLAG_INTERLACE), 855 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 856 /* 26 - 2880x576i@50Hz 16:9 */ 857 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 858 3180, 3456, 0, 576, 580, 586, 625, 0, 859 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 860 DRM_MODE_FLAG_INTERLACE), 861 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 862 /* 27 - 2880x288@50Hz 4:3 */ 863 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 864 3180, 3456, 0, 288, 290, 293, 312, 0, 865 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 866 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 867 /* 28 - 2880x288@50Hz 16:9 */ 868 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 869 3180, 3456, 0, 288, 290, 293, 312, 0, 870 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 871 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 872 /* 29 - 1440x576@50Hz 4:3 */ 873 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 874 1592, 1728, 0, 576, 581, 586, 625, 0, 875 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 876 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 877 /* 30 - 1440x576@50Hz 16:9 */ 878 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 879 1592, 1728, 0, 576, 581, 586, 625, 0, 880 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 881 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 882 /* 31 - 1920x1080@50Hz 16:9 */ 883 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 884 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 885 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 886 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 887 /* 32 - 1920x1080@24Hz 16:9 */ 888 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 889 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 890 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 891 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 892 /* 33 - 1920x1080@25Hz 16:9 */ 893 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 894 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 895 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 896 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 897 /* 34 - 1920x1080@30Hz 16:9 */ 898 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 899 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 900 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 901 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 902 /* 35 - 2880x480@60Hz 4:3 */ 903 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 904 3192, 3432, 0, 480, 489, 495, 525, 0, 905 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 906 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 907 /* 36 - 2880x480@60Hz 16:9 */ 908 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 909 3192, 3432, 0, 480, 489, 495, 525, 0, 910 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 911 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 912 /* 37 - 2880x576@50Hz 4:3 */ 913 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 914 3184, 3456, 0, 576, 581, 586, 625, 0, 915 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 916 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 917 /* 38 - 2880x576@50Hz 16:9 */ 918 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 919 3184, 3456, 0, 576, 581, 586, 625, 0, 920 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 921 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 922 /* 39 - 1920x1080i@50Hz 16:9 */ 923 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 924 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 925 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 926 DRM_MODE_FLAG_INTERLACE), 927 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 928 /* 40 - 1920x1080i@100Hz 16:9 */ 929 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 930 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 931 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 932 DRM_MODE_FLAG_INTERLACE), 933 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 934 /* 41 - 1280x720@100Hz 16:9 */ 935 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 936 1760, 1980, 0, 720, 725, 730, 750, 0, 937 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 938 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 939 /* 42 - 720x576@100Hz 4:3 */ 940 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 941 796, 864, 0, 576, 581, 586, 625, 0, 942 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 943 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 944 /* 43 - 720x576@100Hz 16:9 */ 945 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 946 796, 864, 0, 576, 581, 586, 625, 0, 947 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 948 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 949 /* 44 - 720(1440)x576i@100Hz 4:3 */ 950 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 951 795, 864, 0, 576, 580, 586, 625, 0, 952 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 953 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 954 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 955 /* 45 - 720(1440)x576i@100Hz 16:9 */ 956 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 957 795, 864, 0, 576, 580, 586, 625, 0, 958 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 959 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 960 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 961 /* 46 - 1920x1080i@120Hz 16:9 */ 962 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 963 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 964 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 965 DRM_MODE_FLAG_INTERLACE), 966 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 967 /* 47 - 1280x720@120Hz 16:9 */ 968 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 969 1430, 1650, 0, 720, 725, 730, 750, 0, 970 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 971 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 972 /* 48 - 720x480@120Hz 4:3 */ 973 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 974 798, 858, 0, 480, 489, 495, 525, 0, 975 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 976 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 977 /* 49 - 720x480@120Hz 16:9 */ 978 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 979 798, 858, 0, 480, 489, 495, 525, 0, 980 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 981 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 982 /* 50 - 720(1440)x480i@120Hz 4:3 */ 983 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 984 801, 858, 0, 480, 488, 494, 525, 0, 985 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 986 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 987 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 988 /* 51 - 720(1440)x480i@120Hz 16:9 */ 989 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 990 801, 858, 0, 480, 488, 494, 525, 0, 991 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 992 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 993 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 994 /* 52 - 720x576@200Hz 4:3 */ 995 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 996 796, 864, 0, 576, 581, 586, 625, 0, 997 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 998 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 999 /* 53 - 720x576@200Hz 16:9 */ 1000 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1001 796, 864, 0, 576, 581, 586, 625, 0, 1002 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1003 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1004 /* 54 - 720(1440)x576i@200Hz 4:3 */ 1005 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1006 795, 864, 0, 576, 580, 586, 625, 0, 1007 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1008 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1009 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1010 /* 55 - 720(1440)x576i@200Hz 16:9 */ 1011 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1012 795, 864, 0, 576, 580, 586, 625, 0, 1013 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1014 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1015 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1016 /* 56 - 720x480@240Hz 4:3 */ 1017 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1018 798, 858, 0, 480, 489, 495, 525, 0, 1019 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1020 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1021 /* 57 - 720x480@240Hz 16:9 */ 1022 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1023 798, 858, 0, 480, 489, 495, 525, 0, 1024 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1025 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1026 /* 58 - 720(1440)x480i@240Hz 4:3 */ 1027 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1028 801, 858, 0, 480, 488, 494, 525, 0, 1029 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1030 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1031 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1032 /* 59 - 720(1440)x480i@240Hz 16:9 */ 1033 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1034 801, 858, 0, 480, 488, 494, 525, 0, 1035 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1036 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1037 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1038 /* 60 - 1280x720@24Hz 16:9 */ 1039 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1040 3080, 3300, 0, 720, 725, 730, 750, 0, 1041 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1042 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1043 /* 61 - 1280x720@25Hz 16:9 */ 1044 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1045 3740, 3960, 0, 720, 725, 730, 750, 0, 1046 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1047 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1048 /* 62 - 1280x720@30Hz 16:9 */ 1049 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1050 3080, 3300, 0, 720, 725, 730, 750, 0, 1051 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1052 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1053 /* 63 - 1920x1080@120Hz 16:9 */ 1054 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1055 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1056 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1057 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1058 /* 64 - 1920x1080@100Hz 16:9 */ 1059 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1060 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1061 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1062 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1063 /* 65 - 1280x720@24Hz 64:27 */ 1064 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1065 3080, 3300, 0, 720, 725, 730, 750, 0, 1066 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1067 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1068 /* 66 - 1280x720@25Hz 64:27 */ 1069 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1070 3740, 3960, 0, 720, 725, 730, 750, 0, 1071 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1072 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1073 /* 67 - 1280x720@30Hz 64:27 */ 1074 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1075 3080, 3300, 0, 720, 725, 730, 750, 0, 1076 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1077 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1078 /* 68 - 1280x720@50Hz 64:27 */ 1079 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1080 1760, 1980, 0, 720, 725, 730, 750, 0, 1081 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1082 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1083 /* 69 - 1280x720@60Hz 64:27 */ 1084 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1085 1430, 1650, 0, 720, 725, 730, 750, 0, 1086 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1087 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1088 /* 70 - 1280x720@100Hz 64:27 */ 1089 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1090 1760, 1980, 0, 720, 725, 730, 750, 0, 1091 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1092 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1093 /* 71 - 1280x720@120Hz 64:27 */ 1094 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1095 1430, 1650, 0, 720, 725, 730, 750, 0, 1096 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1097 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1098 /* 72 - 1920x1080@24Hz 64:27 */ 1099 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1100 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1101 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1102 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1103 /* 73 - 1920x1080@25Hz 64:27 */ 1104 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1105 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1106 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1107 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1108 /* 74 - 1920x1080@30Hz 64:27 */ 1109 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1110 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1111 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1112 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1113 /* 75 - 1920x1080@50Hz 64:27 */ 1114 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1115 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1116 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1117 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1118 /* 76 - 1920x1080@60Hz 64:27 */ 1119 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1120 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1121 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1122 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1123 /* 77 - 1920x1080@100Hz 64:27 */ 1124 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1125 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1126 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1127 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1128 /* 78 - 1920x1080@120Hz 64:27 */ 1129 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1130 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1131 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1132 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1133 /* 79 - 1680x720@24Hz 64:27 */ 1134 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 1135 3080, 3300, 0, 720, 725, 730, 750, 0, 1136 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1137 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1138 /* 80 - 1680x720@25Hz 64:27 */ 1139 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 1140 2948, 3168, 0, 720, 725, 730, 750, 0, 1141 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1142 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1143 /* 81 - 1680x720@30Hz 64:27 */ 1144 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 1145 2420, 2640, 0, 720, 725, 730, 750, 0, 1146 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1147 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1148 /* 82 - 1680x720@50Hz 64:27 */ 1149 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1150 1980, 2200, 0, 720, 725, 730, 750, 0, 1151 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1152 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1153 /* 83 - 1680x720@60Hz 64:27 */ 1154 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1155 1980, 2200, 0, 720, 725, 730, 750, 0, 1156 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1157 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1158 /* 84 - 1680x720@100Hz 64:27 */ 1159 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1160 1780, 2000, 0, 720, 725, 730, 825, 0, 1161 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1162 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1163 /* 85 - 1680x720@120Hz 64:27 */ 1164 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1165 1780, 2000, 0, 720, 725, 730, 825, 0, 1166 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1167 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1168 /* 86 - 2560x1080@24Hz 64:27 */ 1169 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 1170 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1171 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1172 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1173 /* 87 - 2560x1080@25Hz 64:27 */ 1174 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 1175 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, 1176 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1177 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1178 /* 88 - 2560x1080@30Hz 64:27 */ 1179 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 1180 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, 1181 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1182 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1183 /* 89 - 2560x1080@50Hz 64:27 */ 1184 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 1185 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, 1186 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1187 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1188 /* 90 - 2560x1080@60Hz 64:27 */ 1189 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 1190 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, 1191 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1192 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1193 /* 91 - 2560x1080@100Hz 64:27 */ 1194 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 1195 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, 1196 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1197 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1198 /* 92 - 2560x1080@120Hz 64:27 */ 1199 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 1200 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, 1201 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1202 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1203 /* 93 - 3840x2160@24Hz 16:9 */ 1204 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1205 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1206 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1207 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1208 /* 94 - 3840x2160@25Hz 16:9 */ 1209 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1210 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1211 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1212 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1213 /* 95 - 3840x2160@30Hz 16:9 */ 1214 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1215 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1216 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1217 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1218 /* 96 - 3840x2160@50Hz 16:9 */ 1219 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1220 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1221 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1222 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1223 /* 97 - 3840x2160@60Hz 16:9 */ 1224 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1225 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1226 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1227 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1228 /* 98 - 4096x2160@24Hz 256:135 */ 1229 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1230 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1231 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1232 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1233 /* 99 - 4096x2160@25Hz 256:135 */ 1234 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1235 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1237 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1238 /* 100 - 4096x2160@30Hz 256:135 */ 1239 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1240 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1241 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1242 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1243 /* 101 - 4096x2160@50Hz 256:135 */ 1244 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1245 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1246 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1247 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1248 /* 102 - 4096x2160@60Hz 256:135 */ 1249 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1250 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1251 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1252 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1253 /* 103 - 3840x2160@24Hz 64:27 */ 1254 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1255 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1257 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1258 /* 104 - 3840x2160@25Hz 64:27 */ 1259 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1260 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1261 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1262 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1263 /* 105 - 3840x2160@30Hz 64:27 */ 1264 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1265 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1266 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1267 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1268 /* 106 - 3840x2160@50Hz 64:27 */ 1269 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1270 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1271 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1272 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1273 /* 107 - 3840x2160@60Hz 64:27 */ 1274 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1275 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1277 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1278 }; 1279 1280 /* 1281 * HDMI 1.4 4k modes. Index using the VIC. 1282 */ 1283 static const struct drm_display_mode edid_4k_modes[] = { 1284 /* 0 - dummy, VICs start at 1 */ 1285 { }, 1286 /* 1 - 3840x2160@30Hz */ 1287 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1288 3840, 4016, 4104, 4400, 0, 1289 2160, 2168, 2178, 2250, 0, 1290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1291 .vrefresh = 30, }, 1292 /* 2 - 3840x2160@25Hz */ 1293 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1294 3840, 4896, 4984, 5280, 0, 1295 2160, 2168, 2178, 2250, 0, 1296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1297 .vrefresh = 25, }, 1298 /* 3 - 3840x2160@24Hz */ 1299 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1300 3840, 5116, 5204, 5500, 0, 1301 2160, 2168, 2178, 2250, 0, 1302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1303 .vrefresh = 24, }, 1304 /* 4 - 4096x2160@24Hz (SMPTE) */ 1305 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1306 4096, 5116, 5204, 5500, 0, 1307 2160, 2168, 2178, 2250, 0, 1308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1309 .vrefresh = 24, }, 1310 }; 1311 1312 /*** DDC fetch and block validation ***/ 1313 1314 static const u8 edid_header[] = { 1315 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1316 }; 1317 1318 /** 1319 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1320 * @raw_edid: pointer to raw base EDID block 1321 * 1322 * Sanity check the header of the base EDID block. 1323 * 1324 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1325 */ 1326 int drm_edid_header_is_valid(const u8 *raw_edid) 1327 { 1328 int i, score = 0; 1329 1330 for (i = 0; i < sizeof(edid_header); i++) 1331 if (raw_edid[i] == edid_header[i]) 1332 score++; 1333 1334 return score; 1335 } 1336 EXPORT_SYMBOL(drm_edid_header_is_valid); 1337 1338 static int edid_fixup __read_mostly = 6; 1339 module_param_named(edid_fixup, edid_fixup, int, 0400); 1340 MODULE_PARM_DESC(edid_fixup, 1341 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1342 1343 static void drm_get_displayid(struct drm_connector *connector, 1344 struct edid *edid); 1345 1346 static int drm_edid_block_checksum(const u8 *raw_edid) 1347 { 1348 int i; 1349 u8 csum = 0; 1350 for (i = 0; i < EDID_LENGTH; i++) 1351 csum += raw_edid[i]; 1352 1353 return csum; 1354 } 1355 1356 static bool drm_edid_is_zero(const u8 *in_edid, int length) 1357 { 1358 if (memchr_inv(in_edid, 0, length)) 1359 return false; 1360 1361 return true; 1362 } 1363 1364 /** 1365 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1366 * @raw_edid: pointer to raw EDID block 1367 * @block: type of block to validate (0 for base, extension otherwise) 1368 * @print_bad_edid: if true, dump bad EDID blocks to the console 1369 * @edid_corrupt: if true, the header or checksum is invalid 1370 * 1371 * Validate a base or extension EDID block and optionally dump bad blocks to 1372 * the console. 1373 * 1374 * Return: True if the block is valid, false otherwise. 1375 */ 1376 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 1377 bool *edid_corrupt) 1378 { 1379 u8 csum; 1380 struct edid *edid = (struct edid *)raw_edid; 1381 1382 if (WARN_ON(!raw_edid)) 1383 return false; 1384 1385 if (edid_fixup > 8 || edid_fixup < 0) 1386 edid_fixup = 6; 1387 1388 if (block == 0) { 1389 int score = drm_edid_header_is_valid(raw_edid); 1390 if (score == 8) { 1391 if (edid_corrupt) 1392 *edid_corrupt = false; 1393 } else if (score >= edid_fixup) { 1394 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 1395 * The corrupt flag needs to be set here otherwise, the 1396 * fix-up code here will correct the problem, the 1397 * checksum is correct and the test fails 1398 */ 1399 if (edid_corrupt) 1400 *edid_corrupt = true; 1401 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1402 memcpy(raw_edid, edid_header, sizeof(edid_header)); 1403 } else { 1404 if (edid_corrupt) 1405 *edid_corrupt = true; 1406 goto bad; 1407 } 1408 } 1409 1410 csum = drm_edid_block_checksum(raw_edid); 1411 if (csum) { 1412 if (edid_corrupt) 1413 *edid_corrupt = true; 1414 1415 /* allow CEA to slide through, switches mangle this */ 1416 if (raw_edid[0] == CEA_EXT) { 1417 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum); 1418 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n"); 1419 } else { 1420 if (print_bad_edid) 1421 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum); 1422 1423 goto bad; 1424 } 1425 } 1426 1427 /* per-block-type checks */ 1428 switch (raw_edid[0]) { 1429 case 0: /* base */ 1430 if (edid->version != 1) { 1431 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version); 1432 goto bad; 1433 } 1434 1435 if (edid->revision > 4) 1436 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1437 break; 1438 1439 default: 1440 break; 1441 } 1442 1443 return true; 1444 1445 bad: 1446 if (print_bad_edid) { 1447 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) { 1448 pr_notice("EDID block is all zeroes\n"); 1449 } else { 1450 pr_notice("Raw EDID:\n"); 1451 print_hex_dump(KERN_NOTICE, 1452 " \t", DUMP_PREFIX_NONE, 16, 1, 1453 raw_edid, EDID_LENGTH, false); 1454 } 1455 } 1456 return false; 1457 } 1458 EXPORT_SYMBOL(drm_edid_block_valid); 1459 1460 /** 1461 * drm_edid_is_valid - sanity check EDID data 1462 * @edid: EDID data 1463 * 1464 * Sanity-check an entire EDID record (including extensions) 1465 * 1466 * Return: True if the EDID data is valid, false otherwise. 1467 */ 1468 bool drm_edid_is_valid(struct edid *edid) 1469 { 1470 int i; 1471 u8 *raw = (u8 *)edid; 1472 1473 if (!edid) 1474 return false; 1475 1476 for (i = 0; i <= edid->extensions; i++) 1477 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL)) 1478 return false; 1479 1480 return true; 1481 } 1482 EXPORT_SYMBOL(drm_edid_is_valid); 1483 1484 #define DDC_SEGMENT_ADDR 0x30 1485 /** 1486 * drm_do_probe_ddc_edid() - get EDID information via I2C 1487 * @data: I2C device adapter 1488 * @buf: EDID data buffer to be filled 1489 * @block: 128 byte EDID block to start fetching from 1490 * @len: EDID data buffer length to fetch 1491 * 1492 * Try to fetch EDID information by calling I2C driver functions. 1493 * 1494 * Return: 0 on success or -1 on failure. 1495 */ 1496 static int 1497 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 1498 { 1499 struct i2c_adapter *adapter = data; 1500 unsigned char start = block * EDID_LENGTH; 1501 unsigned char segment = block >> 1; 1502 unsigned char xfers = segment ? 3 : 2; 1503 int ret, retries = 5; 1504 1505 /* 1506 * The core I2C driver will automatically retry the transfer if the 1507 * adapter reports EAGAIN. However, we find that bit-banging transfers 1508 * are susceptible to errors under a heavily loaded machine and 1509 * generate spurious NAKs and timeouts. Retrying the transfer 1510 * of the individual block a few times seems to overcome this. 1511 */ 1512 do { 1513 struct i2c_msg msgs[] = { 1514 { 1515 .addr = DDC_SEGMENT_ADDR, 1516 .flags = 0, 1517 .len = 1, 1518 .buf = &segment, 1519 }, { 1520 .addr = DDC_ADDR, 1521 .flags = 0, 1522 .len = 1, 1523 .buf = &start, 1524 }, { 1525 .addr = DDC_ADDR, 1526 .flags = I2C_M_RD, 1527 .len = len, 1528 .buf = buf, 1529 } 1530 }; 1531 1532 /* 1533 * Avoid sending the segment addr to not upset non-compliant 1534 * DDC monitors. 1535 */ 1536 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 1537 1538 if (ret == -ENXIO) { 1539 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 1540 adapter->name); 1541 break; 1542 } 1543 } while (ret != xfers && --retries); 1544 1545 return ret == xfers ? 0 : -1; 1546 } 1547 1548 static void connector_bad_edid(struct drm_connector *connector, 1549 u8 *edid, int num_blocks) 1550 { 1551 int i; 1552 1553 if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS)) 1554 return; 1555 1556 dev_warn(connector->dev->dev, 1557 "%s: EDID is invalid:\n", 1558 connector->name); 1559 for (i = 0; i < num_blocks; i++) { 1560 u8 *block = edid + i * EDID_LENGTH; 1561 char prefix[20]; 1562 1563 if (drm_edid_is_zero(block, EDID_LENGTH)) 1564 sprintf(prefix, "\t[%02x] ZERO ", i); 1565 else if (!drm_edid_block_valid(block, i, false, NULL)) 1566 sprintf(prefix, "\t[%02x] BAD ", i); 1567 else 1568 sprintf(prefix, "\t[%02x] GOOD ", i); 1569 1570 print_hex_dump(KERN_WARNING, 1571 prefix, DUMP_PREFIX_NONE, 16, 1, 1572 block, EDID_LENGTH, false); 1573 } 1574 } 1575 1576 /* Get override or firmware EDID */ 1577 static struct edid *drm_get_override_edid(struct drm_connector *connector) 1578 { 1579 struct edid *override = NULL; 1580 1581 if (connector->override_edid) 1582 override = drm_edid_duplicate(connector->edid_blob_ptr->data); 1583 1584 if (!override) 1585 override = drm_load_edid_firmware(connector); 1586 1587 return IS_ERR(override) ? NULL : override; 1588 } 1589 1590 /** 1591 * drm_add_override_edid_modes - add modes from override/firmware EDID 1592 * @connector: connector we're probing 1593 * 1594 * Add modes from the override/firmware EDID, if available. Only to be used from 1595 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe 1596 * failed during drm_get_edid() and caused the override/firmware EDID to be 1597 * skipped. 1598 * 1599 * Return: The number of modes added or 0 if we couldn't find any. 1600 */ 1601 int drm_add_override_edid_modes(struct drm_connector *connector) 1602 { 1603 struct edid *override; 1604 int num_modes = 0; 1605 1606 override = drm_get_override_edid(connector); 1607 if (override) { 1608 drm_connector_update_edid_property(connector, override); 1609 num_modes = drm_add_edid_modes(connector, override); 1610 kfree(override); 1611 1612 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n", 1613 connector->base.id, connector->name, num_modes); 1614 } 1615 1616 return num_modes; 1617 } 1618 EXPORT_SYMBOL(drm_add_override_edid_modes); 1619 1620 /** 1621 * drm_do_get_edid - get EDID data using a custom EDID block read function 1622 * @connector: connector we're probing 1623 * @get_edid_block: EDID block read function 1624 * @data: private data passed to the block read function 1625 * 1626 * When the I2C adapter connected to the DDC bus is hidden behind a device that 1627 * exposes a different interface to read EDID blocks this function can be used 1628 * to get EDID data using a custom block read function. 1629 * 1630 * As in the general case the DDC bus is accessible by the kernel at the I2C 1631 * level, drivers must make all reasonable efforts to expose it as an I2C 1632 * adapter and use drm_get_edid() instead of abusing this function. 1633 * 1634 * The EDID may be overridden using debugfs override_edid or firmare EDID 1635 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority 1636 * order. Having either of them bypasses actual EDID reads. 1637 * 1638 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1639 */ 1640 struct edid *drm_do_get_edid(struct drm_connector *connector, 1641 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 1642 size_t len), 1643 void *data) 1644 { 1645 int i, j = 0, valid_extensions = 0; 1646 u8 *edid, *new; 1647 struct edid *override; 1648 1649 override = drm_get_override_edid(connector); 1650 if (override) 1651 return override; 1652 1653 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) 1654 return NULL; 1655 1656 /* base block fetch */ 1657 for (i = 0; i < 4; i++) { 1658 if (get_edid_block(data, edid, 0, EDID_LENGTH)) 1659 goto out; 1660 if (drm_edid_block_valid(edid, 0, false, 1661 &connector->edid_corrupt)) 1662 break; 1663 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) { 1664 connector->null_edid_counter++; 1665 goto carp; 1666 } 1667 } 1668 if (i == 4) 1669 goto carp; 1670 1671 /* if there's no extensions, we're done */ 1672 valid_extensions = edid[0x7e]; 1673 if (valid_extensions == 0) 1674 return (struct edid *)edid; 1675 1676 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1677 if (!new) 1678 goto out; 1679 edid = new; 1680 1681 for (j = 1; j <= edid[0x7e]; j++) { 1682 u8 *block = edid + j * EDID_LENGTH; 1683 1684 for (i = 0; i < 4; i++) { 1685 if (get_edid_block(data, block, j, EDID_LENGTH)) 1686 goto out; 1687 if (drm_edid_block_valid(block, j, false, NULL)) 1688 break; 1689 } 1690 1691 if (i == 4) 1692 valid_extensions--; 1693 } 1694 1695 if (valid_extensions != edid[0x7e]) { 1696 u8 *base; 1697 1698 connector_bad_edid(connector, edid, edid[0x7e] + 1); 1699 1700 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions; 1701 edid[0x7e] = valid_extensions; 1702 1703 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH, 1704 GFP_KERNEL); 1705 if (!new) 1706 goto out; 1707 1708 base = new; 1709 for (i = 0; i <= edid[0x7e]; i++) { 1710 u8 *block = edid + i * EDID_LENGTH; 1711 1712 if (!drm_edid_block_valid(block, i, false, NULL)) 1713 continue; 1714 1715 memcpy(base, block, EDID_LENGTH); 1716 base += EDID_LENGTH; 1717 } 1718 1719 kfree(edid); 1720 edid = new; 1721 } 1722 1723 return (struct edid *)edid; 1724 1725 carp: 1726 connector_bad_edid(connector, edid, 1); 1727 out: 1728 kfree(edid); 1729 return NULL; 1730 } 1731 EXPORT_SYMBOL_GPL(drm_do_get_edid); 1732 1733 /** 1734 * drm_probe_ddc() - probe DDC presence 1735 * @adapter: I2C adapter to probe 1736 * 1737 * Return: True on success, false on failure. 1738 */ 1739 bool 1740 drm_probe_ddc(struct i2c_adapter *adapter) 1741 { 1742 unsigned char out; 1743 1744 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 1745 } 1746 EXPORT_SYMBOL(drm_probe_ddc); 1747 1748 /** 1749 * drm_get_edid - get EDID data, if available 1750 * @connector: connector we're probing 1751 * @adapter: I2C adapter to use for DDC 1752 * 1753 * Poke the given I2C channel to grab EDID data if possible. If found, 1754 * attach it to the connector. 1755 * 1756 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1757 */ 1758 struct edid *drm_get_edid(struct drm_connector *connector, 1759 struct i2c_adapter *adapter) 1760 { 1761 struct edid *edid; 1762 1763 if (connector->force == DRM_FORCE_OFF) 1764 return NULL; 1765 1766 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 1767 return NULL; 1768 1769 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); 1770 if (edid) 1771 drm_get_displayid(connector, edid); 1772 return edid; 1773 } 1774 EXPORT_SYMBOL(drm_get_edid); 1775 1776 /** 1777 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 1778 * @connector: connector we're probing 1779 * @adapter: I2C adapter to use for DDC 1780 * 1781 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 1782 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 1783 * switch DDC to the GPU which is retrieving EDID. 1784 * 1785 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 1786 */ 1787 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 1788 struct i2c_adapter *adapter) 1789 { 1790 struct pci_dev *pdev = connector->dev->pdev; 1791 struct edid *edid; 1792 1793 vga_switcheroo_lock_ddc(pdev); 1794 edid = drm_get_edid(connector, adapter); 1795 vga_switcheroo_unlock_ddc(pdev); 1796 1797 return edid; 1798 } 1799 EXPORT_SYMBOL(drm_get_edid_switcheroo); 1800 1801 /** 1802 * drm_edid_duplicate - duplicate an EDID and the extensions 1803 * @edid: EDID to duplicate 1804 * 1805 * Return: Pointer to duplicated EDID or NULL on allocation failure. 1806 */ 1807 struct edid *drm_edid_duplicate(const struct edid *edid) 1808 { 1809 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1810 } 1811 EXPORT_SYMBOL(drm_edid_duplicate); 1812 1813 /*** EDID parsing ***/ 1814 1815 /** 1816 * edid_vendor - match a string against EDID's obfuscated vendor field 1817 * @edid: EDID to match 1818 * @vendor: vendor string 1819 * 1820 * Returns true if @vendor is in @edid, false otherwise 1821 */ 1822 static bool edid_vendor(const struct edid *edid, const char *vendor) 1823 { 1824 char edid_vendor[3]; 1825 1826 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 1827 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 1828 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 1829 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 1830 1831 return !strncmp(edid_vendor, vendor, 3); 1832 } 1833 1834 /** 1835 * edid_get_quirks - return quirk flags for a given EDID 1836 * @edid: EDID to process 1837 * 1838 * This tells subsequent routines what fixes they need to apply. 1839 */ 1840 static u32 edid_get_quirks(const struct edid *edid) 1841 { 1842 const struct edid_quirk *quirk; 1843 int i; 1844 1845 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 1846 quirk = &edid_quirk_list[i]; 1847 1848 if (edid_vendor(edid, quirk->vendor) && 1849 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 1850 return quirk->quirks; 1851 } 1852 1853 return 0; 1854 } 1855 1856 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 1857 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 1858 1859 /** 1860 * edid_fixup_preferred - set preferred modes based on quirk list 1861 * @connector: has mode list to fix up 1862 * @quirks: quirks list 1863 * 1864 * Walk the mode list for @connector, clearing the preferred status 1865 * on existing modes and setting it anew for the right mode ala @quirks. 1866 */ 1867 static void edid_fixup_preferred(struct drm_connector *connector, 1868 u32 quirks) 1869 { 1870 struct drm_display_mode *t, *cur_mode, *preferred_mode; 1871 int target_refresh = 0; 1872 int cur_vrefresh, preferred_vrefresh; 1873 1874 if (list_empty(&connector->probed_modes)) 1875 return; 1876 1877 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 1878 target_refresh = 60; 1879 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 1880 target_refresh = 75; 1881 1882 preferred_mode = list_first_entry(&connector->probed_modes, 1883 struct drm_display_mode, head); 1884 1885 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 1886 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 1887 1888 if (cur_mode == preferred_mode) 1889 continue; 1890 1891 /* Largest mode is preferred */ 1892 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 1893 preferred_mode = cur_mode; 1894 1895 cur_vrefresh = cur_mode->vrefresh ? 1896 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode); 1897 preferred_vrefresh = preferred_mode->vrefresh ? 1898 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode); 1899 /* At a given size, try to get closest to target refresh */ 1900 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 1901 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 1902 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 1903 preferred_mode = cur_mode; 1904 } 1905 } 1906 1907 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 1908 } 1909 1910 static bool 1911 mode_is_rb(const struct drm_display_mode *mode) 1912 { 1913 return (mode->htotal - mode->hdisplay == 160) && 1914 (mode->hsync_end - mode->hdisplay == 80) && 1915 (mode->hsync_end - mode->hsync_start == 32) && 1916 (mode->vsync_start - mode->vdisplay == 3); 1917 } 1918 1919 /* 1920 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 1921 * @dev: Device to duplicate against 1922 * @hsize: Mode width 1923 * @vsize: Mode height 1924 * @fresh: Mode refresh rate 1925 * @rb: Mode reduced-blanking-ness 1926 * 1927 * Walk the DMT mode list looking for a match for the given parameters. 1928 * 1929 * Return: A newly allocated copy of the mode, or NULL if not found. 1930 */ 1931 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 1932 int hsize, int vsize, int fresh, 1933 bool rb) 1934 { 1935 int i; 1936 1937 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 1938 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 1939 if (hsize != ptr->hdisplay) 1940 continue; 1941 if (vsize != ptr->vdisplay) 1942 continue; 1943 if (fresh != drm_mode_vrefresh(ptr)) 1944 continue; 1945 if (rb != mode_is_rb(ptr)) 1946 continue; 1947 1948 return drm_mode_duplicate(dev, ptr); 1949 } 1950 1951 return NULL; 1952 } 1953 EXPORT_SYMBOL(drm_mode_find_dmt); 1954 1955 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 1956 1957 static void 1958 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1959 { 1960 int i, n = 0; 1961 u8 d = ext[0x02]; 1962 u8 *det_base = ext + d; 1963 1964 n = (127 - d) / 18; 1965 for (i = 0; i < n; i++) 1966 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1967 } 1968 1969 static void 1970 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1971 { 1972 unsigned int i, n = min((int)ext[0x02], 6); 1973 u8 *det_base = ext + 5; 1974 1975 if (ext[0x01] != 1) 1976 return; /* unknown version */ 1977 1978 for (i = 0; i < n; i++) 1979 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1980 } 1981 1982 static void 1983 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 1984 { 1985 int i; 1986 struct edid *edid = (struct edid *)raw_edid; 1987 1988 if (edid == NULL) 1989 return; 1990 1991 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 1992 cb(&(edid->detailed_timings[i]), closure); 1993 1994 for (i = 1; i <= raw_edid[0x7e]; i++) { 1995 u8 *ext = raw_edid + (i * EDID_LENGTH); 1996 switch (*ext) { 1997 case CEA_EXT: 1998 cea_for_each_detailed_block(ext, cb, closure); 1999 break; 2000 case VTB_EXT: 2001 vtb_for_each_detailed_block(ext, cb, closure); 2002 break; 2003 default: 2004 break; 2005 } 2006 } 2007 } 2008 2009 static void 2010 is_rb(struct detailed_timing *t, void *data) 2011 { 2012 u8 *r = (u8 *)t; 2013 if (r[3] == EDID_DETAIL_MONITOR_RANGE) 2014 if (r[15] & 0x10) 2015 *(bool *)data = true; 2016 } 2017 2018 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 2019 static bool 2020 drm_monitor_supports_rb(struct edid *edid) 2021 { 2022 if (edid->revision >= 4) { 2023 bool ret = false; 2024 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 2025 return ret; 2026 } 2027 2028 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 2029 } 2030 2031 static void 2032 find_gtf2(struct detailed_timing *t, void *data) 2033 { 2034 u8 *r = (u8 *)t; 2035 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) 2036 *(u8 **)data = r; 2037 } 2038 2039 /* Secondary GTF curve kicks in above some break frequency */ 2040 static int 2041 drm_gtf2_hbreak(struct edid *edid) 2042 { 2043 u8 *r = NULL; 2044 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2045 return r ? (r[12] * 2) : 0; 2046 } 2047 2048 static int 2049 drm_gtf2_2c(struct edid *edid) 2050 { 2051 u8 *r = NULL; 2052 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2053 return r ? r[13] : 0; 2054 } 2055 2056 static int 2057 drm_gtf2_m(struct edid *edid) 2058 { 2059 u8 *r = NULL; 2060 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2061 return r ? (r[15] << 8) + r[14] : 0; 2062 } 2063 2064 static int 2065 drm_gtf2_k(struct edid *edid) 2066 { 2067 u8 *r = NULL; 2068 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2069 return r ? r[16] : 0; 2070 } 2071 2072 static int 2073 drm_gtf2_2j(struct edid *edid) 2074 { 2075 u8 *r = NULL; 2076 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2077 return r ? r[17] : 0; 2078 } 2079 2080 /** 2081 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 2082 * @edid: EDID block to scan 2083 */ 2084 static int standard_timing_level(struct edid *edid) 2085 { 2086 if (edid->revision >= 2) { 2087 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 2088 return LEVEL_CVT; 2089 if (drm_gtf2_hbreak(edid)) 2090 return LEVEL_GTF2; 2091 return LEVEL_GTF; 2092 } 2093 return LEVEL_DMT; 2094 } 2095 2096 /* 2097 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 2098 * monitors fill with ascii space (0x20) instead. 2099 */ 2100 static int 2101 bad_std_timing(u8 a, u8 b) 2102 { 2103 return (a == 0x00 && b == 0x00) || 2104 (a == 0x01 && b == 0x01) || 2105 (a == 0x20 && b == 0x20); 2106 } 2107 2108 /** 2109 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 2110 * @connector: connector of for the EDID block 2111 * @edid: EDID block to scan 2112 * @t: standard timing params 2113 * 2114 * Take the standard timing params (in this case width, aspect, and refresh) 2115 * and convert them into a real mode using CVT/GTF/DMT. 2116 */ 2117 static struct drm_display_mode * 2118 drm_mode_std(struct drm_connector *connector, struct edid *edid, 2119 struct std_timing *t) 2120 { 2121 struct drm_device *dev = connector->dev; 2122 struct drm_display_mode *m, *mode = NULL; 2123 int hsize, vsize; 2124 int vrefresh_rate; 2125 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 2126 >> EDID_TIMING_ASPECT_SHIFT; 2127 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 2128 >> EDID_TIMING_VFREQ_SHIFT; 2129 int timing_level = standard_timing_level(edid); 2130 2131 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 2132 return NULL; 2133 2134 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 2135 hsize = t->hsize * 8 + 248; 2136 /* vrefresh_rate = vfreq + 60 */ 2137 vrefresh_rate = vfreq + 60; 2138 /* the vdisplay is calculated based on the aspect ratio */ 2139 if (aspect_ratio == 0) { 2140 if (edid->revision < 3) 2141 vsize = hsize; 2142 else 2143 vsize = (hsize * 10) / 16; 2144 } else if (aspect_ratio == 1) 2145 vsize = (hsize * 3) / 4; 2146 else if (aspect_ratio == 2) 2147 vsize = (hsize * 4) / 5; 2148 else 2149 vsize = (hsize * 9) / 16; 2150 2151 /* HDTV hack, part 1 */ 2152 if (vrefresh_rate == 60 && 2153 ((hsize == 1360 && vsize == 765) || 2154 (hsize == 1368 && vsize == 769))) { 2155 hsize = 1366; 2156 vsize = 768; 2157 } 2158 2159 /* 2160 * If this connector already has a mode for this size and refresh 2161 * rate (because it came from detailed or CVT info), use that 2162 * instead. This way we don't have to guess at interlace or 2163 * reduced blanking. 2164 */ 2165 list_for_each_entry(m, &connector->probed_modes, head) 2166 if (m->hdisplay == hsize && m->vdisplay == vsize && 2167 drm_mode_vrefresh(m) == vrefresh_rate) 2168 return NULL; 2169 2170 /* HDTV hack, part 2 */ 2171 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 2172 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 2173 false); 2174 if (!mode) 2175 return NULL; 2176 mode->hdisplay = 1366; 2177 mode->hsync_start = mode->hsync_start - 1; 2178 mode->hsync_end = mode->hsync_end - 1; 2179 return mode; 2180 } 2181 2182 /* check whether it can be found in default mode table */ 2183 if (drm_monitor_supports_rb(edid)) { 2184 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 2185 true); 2186 if (mode) 2187 return mode; 2188 } 2189 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 2190 if (mode) 2191 return mode; 2192 2193 /* okay, generate it */ 2194 switch (timing_level) { 2195 case LEVEL_DMT: 2196 break; 2197 case LEVEL_GTF: 2198 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2199 break; 2200 case LEVEL_GTF2: 2201 /* 2202 * This is potentially wrong if there's ever a monitor with 2203 * more than one ranges section, each claiming a different 2204 * secondary GTF curve. Please don't do that. 2205 */ 2206 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2207 if (!mode) 2208 return NULL; 2209 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 2210 drm_mode_destroy(dev, mode); 2211 mode = drm_gtf_mode_complex(dev, hsize, vsize, 2212 vrefresh_rate, 0, 0, 2213 drm_gtf2_m(edid), 2214 drm_gtf2_2c(edid), 2215 drm_gtf2_k(edid), 2216 drm_gtf2_2j(edid)); 2217 } 2218 break; 2219 case LEVEL_CVT: 2220 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 2221 false); 2222 break; 2223 } 2224 return mode; 2225 } 2226 2227 /* 2228 * EDID is delightfully ambiguous about how interlaced modes are to be 2229 * encoded. Our internal representation is of frame height, but some 2230 * HDTV detailed timings are encoded as field height. 2231 * 2232 * The format list here is from CEA, in frame size. Technically we 2233 * should be checking refresh rate too. Whatever. 2234 */ 2235 static void 2236 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 2237 struct detailed_pixel_timing *pt) 2238 { 2239 int i; 2240 static const struct { 2241 int w, h; 2242 } cea_interlaced[] = { 2243 { 1920, 1080 }, 2244 { 720, 480 }, 2245 { 1440, 480 }, 2246 { 2880, 480 }, 2247 { 720, 576 }, 2248 { 1440, 576 }, 2249 { 2880, 576 }, 2250 }; 2251 2252 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 2253 return; 2254 2255 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 2256 if ((mode->hdisplay == cea_interlaced[i].w) && 2257 (mode->vdisplay == cea_interlaced[i].h / 2)) { 2258 mode->vdisplay *= 2; 2259 mode->vsync_start *= 2; 2260 mode->vsync_end *= 2; 2261 mode->vtotal *= 2; 2262 mode->vtotal |= 1; 2263 } 2264 } 2265 2266 mode->flags |= DRM_MODE_FLAG_INTERLACE; 2267 } 2268 2269 /** 2270 * drm_mode_detailed - create a new mode from an EDID detailed timing section 2271 * @dev: DRM device (needed to create new mode) 2272 * @edid: EDID block 2273 * @timing: EDID detailed timing info 2274 * @quirks: quirks to apply 2275 * 2276 * An EDID detailed timing block contains enough info for us to create and 2277 * return a new struct drm_display_mode. 2278 */ 2279 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 2280 struct edid *edid, 2281 struct detailed_timing *timing, 2282 u32 quirks) 2283 { 2284 struct drm_display_mode *mode; 2285 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 2286 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 2287 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 2288 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 2289 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 2290 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 2291 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 2292 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 2293 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 2294 2295 /* ignore tiny modes */ 2296 if (hactive < 64 || vactive < 64) 2297 return NULL; 2298 2299 if (pt->misc & DRM_EDID_PT_STEREO) { 2300 DRM_DEBUG_KMS("stereo mode not supported\n"); 2301 return NULL; 2302 } 2303 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 2304 DRM_DEBUG_KMS("composite sync not supported\n"); 2305 } 2306 2307 /* it is incorrect if hsync/vsync width is zero */ 2308 if (!hsync_pulse_width || !vsync_pulse_width) { 2309 DRM_DEBUG_KMS("Incorrect Detailed timing. " 2310 "Wrong Hsync/Vsync pulse width\n"); 2311 return NULL; 2312 } 2313 2314 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 2315 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 2316 if (!mode) 2317 return NULL; 2318 2319 goto set_size; 2320 } 2321 2322 mode = drm_mode_create(dev); 2323 if (!mode) 2324 return NULL; 2325 2326 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 2327 timing->pixel_clock = cpu_to_le16(1088); 2328 2329 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 2330 2331 mode->hdisplay = hactive; 2332 mode->hsync_start = mode->hdisplay + hsync_offset; 2333 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 2334 mode->htotal = mode->hdisplay + hblank; 2335 2336 mode->vdisplay = vactive; 2337 mode->vsync_start = mode->vdisplay + vsync_offset; 2338 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 2339 mode->vtotal = mode->vdisplay + vblank; 2340 2341 /* Some EDIDs have bogus h/vtotal values */ 2342 if (mode->hsync_end > mode->htotal) 2343 mode->htotal = mode->hsync_end + 1; 2344 if (mode->vsync_end > mode->vtotal) 2345 mode->vtotal = mode->vsync_end + 1; 2346 2347 drm_mode_do_interlace_quirk(mode, pt); 2348 2349 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 2350 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; 2351 } 2352 2353 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 2354 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 2355 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 2356 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 2357 2358 set_size: 2359 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 2360 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 2361 2362 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 2363 mode->width_mm *= 10; 2364 mode->height_mm *= 10; 2365 } 2366 2367 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 2368 mode->width_mm = edid->width_cm * 10; 2369 mode->height_mm = edid->height_cm * 10; 2370 } 2371 2372 mode->type = DRM_MODE_TYPE_DRIVER; 2373 mode->vrefresh = drm_mode_vrefresh(mode); 2374 drm_mode_set_name(mode); 2375 2376 return mode; 2377 } 2378 2379 static bool 2380 mode_in_hsync_range(const struct drm_display_mode *mode, 2381 struct edid *edid, u8 *t) 2382 { 2383 int hsync, hmin, hmax; 2384 2385 hmin = t[7]; 2386 if (edid->revision >= 4) 2387 hmin += ((t[4] & 0x04) ? 255 : 0); 2388 hmax = t[8]; 2389 if (edid->revision >= 4) 2390 hmax += ((t[4] & 0x08) ? 255 : 0); 2391 hsync = drm_mode_hsync(mode); 2392 2393 return (hsync <= hmax && hsync >= hmin); 2394 } 2395 2396 static bool 2397 mode_in_vsync_range(const struct drm_display_mode *mode, 2398 struct edid *edid, u8 *t) 2399 { 2400 int vsync, vmin, vmax; 2401 2402 vmin = t[5]; 2403 if (edid->revision >= 4) 2404 vmin += ((t[4] & 0x01) ? 255 : 0); 2405 vmax = t[6]; 2406 if (edid->revision >= 4) 2407 vmax += ((t[4] & 0x02) ? 255 : 0); 2408 vsync = drm_mode_vrefresh(mode); 2409 2410 return (vsync <= vmax && vsync >= vmin); 2411 } 2412 2413 static u32 2414 range_pixel_clock(struct edid *edid, u8 *t) 2415 { 2416 /* unspecified */ 2417 if (t[9] == 0 || t[9] == 255) 2418 return 0; 2419 2420 /* 1.4 with CVT support gives us real precision, yay */ 2421 if (edid->revision >= 4 && t[10] == 0x04) 2422 return (t[9] * 10000) - ((t[12] >> 2) * 250); 2423 2424 /* 1.3 is pathetic, so fuzz up a bit */ 2425 return t[9] * 10000 + 5001; 2426 } 2427 2428 static bool 2429 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 2430 struct detailed_timing *timing) 2431 { 2432 u32 max_clock; 2433 u8 *t = (u8 *)timing; 2434 2435 if (!mode_in_hsync_range(mode, edid, t)) 2436 return false; 2437 2438 if (!mode_in_vsync_range(mode, edid, t)) 2439 return false; 2440 2441 if ((max_clock = range_pixel_clock(edid, t))) 2442 if (mode->clock > max_clock) 2443 return false; 2444 2445 /* 1.4 max horizontal check */ 2446 if (edid->revision >= 4 && t[10] == 0x04) 2447 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 2448 return false; 2449 2450 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 2451 return false; 2452 2453 return true; 2454 } 2455 2456 static bool valid_inferred_mode(const struct drm_connector *connector, 2457 const struct drm_display_mode *mode) 2458 { 2459 const struct drm_display_mode *m; 2460 bool ok = false; 2461 2462 list_for_each_entry(m, &connector->probed_modes, head) { 2463 if (mode->hdisplay == m->hdisplay && 2464 mode->vdisplay == m->vdisplay && 2465 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 2466 return false; /* duplicated */ 2467 if (mode->hdisplay <= m->hdisplay && 2468 mode->vdisplay <= m->vdisplay) 2469 ok = true; 2470 } 2471 return ok; 2472 } 2473 2474 static int 2475 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2476 struct detailed_timing *timing) 2477 { 2478 int i, modes = 0; 2479 struct drm_display_mode *newmode; 2480 struct drm_device *dev = connector->dev; 2481 2482 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2483 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 2484 valid_inferred_mode(connector, drm_dmt_modes + i)) { 2485 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 2486 if (newmode) { 2487 drm_mode_probed_add(connector, newmode); 2488 modes++; 2489 } 2490 } 2491 } 2492 2493 return modes; 2494 } 2495 2496 /* fix up 1366x768 mode from 1368x768; 2497 * GFT/CVT can't express 1366 width which isn't dividable by 8 2498 */ 2499 void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 2500 { 2501 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 2502 mode->hdisplay = 1366; 2503 mode->hsync_start--; 2504 mode->hsync_end--; 2505 drm_mode_set_name(mode); 2506 } 2507 } 2508 2509 static int 2510 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, 2511 struct detailed_timing *timing) 2512 { 2513 int i, modes = 0; 2514 struct drm_display_mode *newmode; 2515 struct drm_device *dev = connector->dev; 2516 2517 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2518 const struct minimode *m = &extra_modes[i]; 2519 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 2520 if (!newmode) 2521 return modes; 2522 2523 drm_mode_fixup_1366x768(newmode); 2524 if (!mode_in_range(newmode, edid, timing) || 2525 !valid_inferred_mode(connector, newmode)) { 2526 drm_mode_destroy(dev, newmode); 2527 continue; 2528 } 2529 2530 drm_mode_probed_add(connector, newmode); 2531 modes++; 2532 } 2533 2534 return modes; 2535 } 2536 2537 static int 2538 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2539 struct detailed_timing *timing) 2540 { 2541 int i, modes = 0; 2542 struct drm_display_mode *newmode; 2543 struct drm_device *dev = connector->dev; 2544 bool rb = drm_monitor_supports_rb(edid); 2545 2546 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2547 const struct minimode *m = &extra_modes[i]; 2548 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 2549 if (!newmode) 2550 return modes; 2551 2552 drm_mode_fixup_1366x768(newmode); 2553 if (!mode_in_range(newmode, edid, timing) || 2554 !valid_inferred_mode(connector, newmode)) { 2555 drm_mode_destroy(dev, newmode); 2556 continue; 2557 } 2558 2559 drm_mode_probed_add(connector, newmode); 2560 modes++; 2561 } 2562 2563 return modes; 2564 } 2565 2566 static void 2567 do_inferred_modes(struct detailed_timing *timing, void *c) 2568 { 2569 struct detailed_mode_closure *closure = c; 2570 struct detailed_non_pixel *data = &timing->data.other_data; 2571 struct detailed_data_monitor_range *range = &data->data.range; 2572 2573 if (data->type != EDID_DETAIL_MONITOR_RANGE) 2574 return; 2575 2576 closure->modes += drm_dmt_modes_for_range(closure->connector, 2577 closure->edid, 2578 timing); 2579 2580 if (!version_greater(closure->edid, 1, 1)) 2581 return; /* GTF not defined yet */ 2582 2583 switch (range->flags) { 2584 case 0x02: /* secondary gtf, XXX could do more */ 2585 case 0x00: /* default gtf */ 2586 closure->modes += drm_gtf_modes_for_range(closure->connector, 2587 closure->edid, 2588 timing); 2589 break; 2590 case 0x04: /* cvt, only in 1.4+ */ 2591 if (!version_greater(closure->edid, 1, 3)) 2592 break; 2593 2594 closure->modes += drm_cvt_modes_for_range(closure->connector, 2595 closure->edid, 2596 timing); 2597 break; 2598 case 0x01: /* just the ranges, no formula */ 2599 default: 2600 break; 2601 } 2602 } 2603 2604 static int 2605 add_inferred_modes(struct drm_connector *connector, struct edid *edid) 2606 { 2607 struct detailed_mode_closure closure = { 2608 .connector = connector, 2609 .edid = edid, 2610 }; 2611 2612 if (version_greater(edid, 1, 0)) 2613 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 2614 &closure); 2615 2616 return closure.modes; 2617 } 2618 2619 static int 2620 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 2621 { 2622 int i, j, m, modes = 0; 2623 struct drm_display_mode *mode; 2624 u8 *est = ((u8 *)timing) + 6; 2625 2626 for (i = 0; i < 6; i++) { 2627 for (j = 7; j >= 0; j--) { 2628 m = (i * 8) + (7 - j); 2629 if (m >= ARRAY_SIZE(est3_modes)) 2630 break; 2631 if (est[i] & (1 << j)) { 2632 mode = drm_mode_find_dmt(connector->dev, 2633 est3_modes[m].w, 2634 est3_modes[m].h, 2635 est3_modes[m].r, 2636 est3_modes[m].rb); 2637 if (mode) { 2638 drm_mode_probed_add(connector, mode); 2639 modes++; 2640 } 2641 } 2642 } 2643 } 2644 2645 return modes; 2646 } 2647 2648 static void 2649 do_established_modes(struct detailed_timing *timing, void *c) 2650 { 2651 struct detailed_mode_closure *closure = c; 2652 struct detailed_non_pixel *data = &timing->data.other_data; 2653 2654 if (data->type == EDID_DETAIL_EST_TIMINGS) 2655 closure->modes += drm_est3_modes(closure->connector, timing); 2656 } 2657 2658 /** 2659 * add_established_modes - get est. modes from EDID and add them 2660 * @connector: connector to add mode(s) to 2661 * @edid: EDID block to scan 2662 * 2663 * Each EDID block contains a bitmap of the supported "established modes" list 2664 * (defined above). Tease them out and add them to the global modes list. 2665 */ 2666 static int 2667 add_established_modes(struct drm_connector *connector, struct edid *edid) 2668 { 2669 struct drm_device *dev = connector->dev; 2670 unsigned long est_bits = edid->established_timings.t1 | 2671 (edid->established_timings.t2 << 8) | 2672 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 2673 int i, modes = 0; 2674 struct detailed_mode_closure closure = { 2675 .connector = connector, 2676 .edid = edid, 2677 }; 2678 2679 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 2680 if (est_bits & (1<<i)) { 2681 struct drm_display_mode *newmode; 2682 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 2683 if (newmode) { 2684 drm_mode_probed_add(connector, newmode); 2685 modes++; 2686 } 2687 } 2688 } 2689 2690 if (version_greater(edid, 1, 0)) 2691 drm_for_each_detailed_block((u8 *)edid, 2692 do_established_modes, &closure); 2693 2694 return modes + closure.modes; 2695 } 2696 2697 static void 2698 do_standard_modes(struct detailed_timing *timing, void *c) 2699 { 2700 struct detailed_mode_closure *closure = c; 2701 struct detailed_non_pixel *data = &timing->data.other_data; 2702 struct drm_connector *connector = closure->connector; 2703 struct edid *edid = closure->edid; 2704 2705 if (data->type == EDID_DETAIL_STD_MODES) { 2706 int i; 2707 for (i = 0; i < 6; i++) { 2708 struct std_timing *std; 2709 struct drm_display_mode *newmode; 2710 2711 std = &data->data.timings[i]; 2712 newmode = drm_mode_std(connector, edid, std); 2713 if (newmode) { 2714 drm_mode_probed_add(connector, newmode); 2715 closure->modes++; 2716 } 2717 } 2718 } 2719 } 2720 2721 /** 2722 * add_standard_modes - get std. modes from EDID and add them 2723 * @connector: connector to add mode(s) to 2724 * @edid: EDID block to scan 2725 * 2726 * Standard modes can be calculated using the appropriate standard (DMT, 2727 * GTF or CVT. Grab them from @edid and add them to the list. 2728 */ 2729 static int 2730 add_standard_modes(struct drm_connector *connector, struct edid *edid) 2731 { 2732 int i, modes = 0; 2733 struct detailed_mode_closure closure = { 2734 .connector = connector, 2735 .edid = edid, 2736 }; 2737 2738 for (i = 0; i < EDID_STD_TIMINGS; i++) { 2739 struct drm_display_mode *newmode; 2740 2741 newmode = drm_mode_std(connector, edid, 2742 &edid->standard_timings[i]); 2743 if (newmode) { 2744 drm_mode_probed_add(connector, newmode); 2745 modes++; 2746 } 2747 } 2748 2749 if (version_greater(edid, 1, 0)) 2750 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 2751 &closure); 2752 2753 /* XXX should also look for standard codes in VTB blocks */ 2754 2755 return modes + closure.modes; 2756 } 2757 2758 static int drm_cvt_modes(struct drm_connector *connector, 2759 struct detailed_timing *timing) 2760 { 2761 int i, j, modes = 0; 2762 struct drm_display_mode *newmode; 2763 struct drm_device *dev = connector->dev; 2764 struct cvt_timing *cvt; 2765 const int rates[] = { 60, 85, 75, 60, 50 }; 2766 const u8 empty[3] = { 0, 0, 0 }; 2767 2768 for (i = 0; i < 4; i++) { 2769 int uninitialized_var(width), height; 2770 cvt = &(timing->data.other_data.data.cvt[i]); 2771 2772 if (!memcmp(cvt->code, empty, 3)) 2773 continue; 2774 2775 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 2776 switch (cvt->code[1] & 0x0c) { 2777 case 0x00: 2778 width = height * 4 / 3; 2779 break; 2780 case 0x04: 2781 width = height * 16 / 9; 2782 break; 2783 case 0x08: 2784 width = height * 16 / 10; 2785 break; 2786 case 0x0c: 2787 width = height * 15 / 9; 2788 break; 2789 } 2790 2791 for (j = 1; j < 5; j++) { 2792 if (cvt->code[2] & (1 << j)) { 2793 newmode = drm_cvt_mode(dev, width, height, 2794 rates[j], j == 0, 2795 false, false); 2796 if (newmode) { 2797 drm_mode_probed_add(connector, newmode); 2798 modes++; 2799 } 2800 } 2801 } 2802 } 2803 2804 return modes; 2805 } 2806 2807 static void 2808 do_cvt_mode(struct detailed_timing *timing, void *c) 2809 { 2810 struct detailed_mode_closure *closure = c; 2811 struct detailed_non_pixel *data = &timing->data.other_data; 2812 2813 if (data->type == EDID_DETAIL_CVT_3BYTE) 2814 closure->modes += drm_cvt_modes(closure->connector, timing); 2815 } 2816 2817 static int 2818 add_cvt_modes(struct drm_connector *connector, struct edid *edid) 2819 { 2820 struct detailed_mode_closure closure = { 2821 .connector = connector, 2822 .edid = edid, 2823 }; 2824 2825 if (version_greater(edid, 1, 2)) 2826 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 2827 2828 /* XXX should also look for CVT codes in VTB blocks */ 2829 2830 return closure.modes; 2831 } 2832 2833 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); 2834 2835 static void 2836 do_detailed_mode(struct detailed_timing *timing, void *c) 2837 { 2838 struct detailed_mode_closure *closure = c; 2839 struct drm_display_mode *newmode; 2840 2841 if (timing->pixel_clock) { 2842 newmode = drm_mode_detailed(closure->connector->dev, 2843 closure->edid, timing, 2844 closure->quirks); 2845 if (!newmode) 2846 return; 2847 2848 if (closure->preferred) 2849 newmode->type |= DRM_MODE_TYPE_PREFERRED; 2850 2851 /* 2852 * Detailed modes are limited to 10kHz pixel clock resolution, 2853 * so fix up anything that looks like CEA/HDMI mode, but the clock 2854 * is just slightly off. 2855 */ 2856 fixup_detailed_cea_mode_clock(newmode); 2857 2858 drm_mode_probed_add(closure->connector, newmode); 2859 closure->modes++; 2860 closure->preferred = false; 2861 } 2862 } 2863 2864 /* 2865 * add_detailed_modes - Add modes from detailed timings 2866 * @connector: attached connector 2867 * @edid: EDID block to scan 2868 * @quirks: quirks to apply 2869 */ 2870 static int 2871 add_detailed_modes(struct drm_connector *connector, struct edid *edid, 2872 u32 quirks) 2873 { 2874 struct detailed_mode_closure closure = { 2875 .connector = connector, 2876 .edid = edid, 2877 .preferred = true, 2878 .quirks = quirks, 2879 }; 2880 2881 if (closure.preferred && !version_greater(edid, 1, 3)) 2882 closure.preferred = 2883 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 2884 2885 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 2886 2887 return closure.modes; 2888 } 2889 2890 #define AUDIO_BLOCK 0x01 2891 #define VIDEO_BLOCK 0x02 2892 #define VENDOR_BLOCK 0x03 2893 #define SPEAKER_BLOCK 0x04 2894 #define HDR_STATIC_METADATA_BLOCK 0x6 2895 #define USE_EXTENDED_TAG 0x07 2896 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00 2897 #define EXT_VIDEO_DATA_BLOCK_420 0x0E 2898 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F 2899 #define EDID_BASIC_AUDIO (1 << 6) 2900 #define EDID_CEA_YCRCB444 (1 << 5) 2901 #define EDID_CEA_YCRCB422 (1 << 4) 2902 #define EDID_CEA_VCDB_QS (1 << 6) 2903 2904 /* 2905 * Search EDID for CEA extension block. 2906 */ 2907 static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id) 2908 { 2909 u8 *edid_ext = NULL; 2910 int i; 2911 2912 /* No EDID or EDID extensions */ 2913 if (edid == NULL || edid->extensions == 0) 2914 return NULL; 2915 2916 /* Find CEA extension */ 2917 for (i = 0; i < edid->extensions; i++) { 2918 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); 2919 if (edid_ext[0] == ext_id) 2920 break; 2921 } 2922 2923 if (i == edid->extensions) 2924 return NULL; 2925 2926 return edid_ext; 2927 } 2928 2929 static u8 *drm_find_cea_extension(const struct edid *edid) 2930 { 2931 return drm_find_edid_extension(edid, CEA_EXT); 2932 } 2933 2934 static u8 *drm_find_displayid_extension(const struct edid *edid) 2935 { 2936 return drm_find_edid_extension(edid, DISPLAYID_EXT); 2937 } 2938 2939 /* 2940 * Calculate the alternate clock for the CEA mode 2941 * (60Hz vs. 59.94Hz etc.) 2942 */ 2943 static unsigned int 2944 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 2945 { 2946 unsigned int clock = cea_mode->clock; 2947 2948 if (cea_mode->vrefresh % 6 != 0) 2949 return clock; 2950 2951 /* 2952 * edid_cea_modes contains the 59.94Hz 2953 * variant for 240 and 480 line modes, 2954 * and the 60Hz variant otherwise. 2955 */ 2956 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 2957 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 2958 else 2959 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 2960 2961 return clock; 2962 } 2963 2964 static bool 2965 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 2966 { 2967 /* 2968 * For certain VICs the spec allows the vertical 2969 * front porch to vary by one or two lines. 2970 * 2971 * cea_modes[] stores the variant with the shortest 2972 * vertical front porch. We can adjust the mode to 2973 * get the other variants by simply increasing the 2974 * vertical front porch length. 2975 */ 2976 BUILD_BUG_ON(edid_cea_modes[8].vtotal != 262 || 2977 edid_cea_modes[9].vtotal != 262 || 2978 edid_cea_modes[12].vtotal != 262 || 2979 edid_cea_modes[13].vtotal != 262 || 2980 edid_cea_modes[23].vtotal != 312 || 2981 edid_cea_modes[24].vtotal != 312 || 2982 edid_cea_modes[27].vtotal != 312 || 2983 edid_cea_modes[28].vtotal != 312); 2984 2985 if (((vic == 8 || vic == 9 || 2986 vic == 12 || vic == 13) && mode->vtotal < 263) || 2987 ((vic == 23 || vic == 24 || 2988 vic == 27 || vic == 28) && mode->vtotal < 314)) { 2989 mode->vsync_start++; 2990 mode->vsync_end++; 2991 mode->vtotal++; 2992 2993 return true; 2994 } 2995 2996 return false; 2997 } 2998 2999 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 3000 unsigned int clock_tolerance) 3001 { 3002 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3003 u8 vic; 3004 3005 if (!to_match->clock) 3006 return 0; 3007 3008 if (to_match->picture_aspect_ratio) 3009 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3010 3011 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 3012 struct drm_display_mode cea_mode = edid_cea_modes[vic]; 3013 unsigned int clock1, clock2; 3014 3015 /* Check both 60Hz and 59.94Hz */ 3016 clock1 = cea_mode.clock; 3017 clock2 = cea_mode_alternate_clock(&cea_mode); 3018 3019 if (abs(to_match->clock - clock1) > clock_tolerance && 3020 abs(to_match->clock - clock2) > clock_tolerance) 3021 continue; 3022 3023 do { 3024 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3025 return vic; 3026 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3027 } 3028 3029 return 0; 3030 } 3031 3032 /** 3033 * drm_match_cea_mode - look for a CEA mode matching given mode 3034 * @to_match: display mode 3035 * 3036 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 3037 * mode. 3038 */ 3039 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 3040 { 3041 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3042 u8 vic; 3043 3044 if (!to_match->clock) 3045 return 0; 3046 3047 if (to_match->picture_aspect_ratio) 3048 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3049 3050 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 3051 struct drm_display_mode cea_mode = edid_cea_modes[vic]; 3052 unsigned int clock1, clock2; 3053 3054 /* Check both 60Hz and 59.94Hz */ 3055 clock1 = cea_mode.clock; 3056 clock2 = cea_mode_alternate_clock(&cea_mode); 3057 3058 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 3059 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 3060 continue; 3061 3062 do { 3063 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3064 return vic; 3065 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3066 } 3067 3068 return 0; 3069 } 3070 EXPORT_SYMBOL(drm_match_cea_mode); 3071 3072 static bool drm_valid_cea_vic(u8 vic) 3073 { 3074 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes); 3075 } 3076 3077 /** 3078 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to 3079 * the input VIC from the CEA mode list 3080 * @video_code: ID given to each of the CEA modes 3081 * 3082 * Returns picture aspect ratio 3083 */ 3084 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 3085 { 3086 return edid_cea_modes[video_code].picture_aspect_ratio; 3087 } 3088 EXPORT_SYMBOL(drm_get_cea_aspect_ratio); 3089 3090 /* 3091 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 3092 * specific block). 3093 * 3094 * It's almost like cea_mode_alternate_clock(), we just need to add an 3095 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this 3096 * one. 3097 */ 3098 static unsigned int 3099 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 3100 { 3101 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) 3102 return hdmi_mode->clock; 3103 3104 return cea_mode_alternate_clock(hdmi_mode); 3105 } 3106 3107 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 3108 unsigned int clock_tolerance) 3109 { 3110 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3111 u8 vic; 3112 3113 if (!to_match->clock) 3114 return 0; 3115 3116 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3117 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3118 unsigned int clock1, clock2; 3119 3120 /* Make sure to also match alternate clocks */ 3121 clock1 = hdmi_mode->clock; 3122 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3123 3124 if (abs(to_match->clock - clock1) > clock_tolerance && 3125 abs(to_match->clock - clock2) > clock_tolerance) 3126 continue; 3127 3128 if (drm_mode_match(to_match, hdmi_mode, match_flags)) 3129 return vic; 3130 } 3131 3132 return 0; 3133 } 3134 3135 /* 3136 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 3137 * @to_match: display mode 3138 * 3139 * An HDMI mode is one defined in the HDMI vendor specific block. 3140 * 3141 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 3142 */ 3143 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 3144 { 3145 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3146 u8 vic; 3147 3148 if (!to_match->clock) 3149 return 0; 3150 3151 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3152 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3153 unsigned int clock1, clock2; 3154 3155 /* Make sure to also match alternate clocks */ 3156 clock1 = hdmi_mode->clock; 3157 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3158 3159 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 3160 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 3161 drm_mode_match(to_match, hdmi_mode, match_flags)) 3162 return vic; 3163 } 3164 return 0; 3165 } 3166 3167 static bool drm_valid_hdmi_vic(u8 vic) 3168 { 3169 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 3170 } 3171 3172 static int 3173 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) 3174 { 3175 struct drm_device *dev = connector->dev; 3176 struct drm_display_mode *mode, *tmp; 3177 LIST_HEAD(list); 3178 int modes = 0; 3179 3180 /* Don't add CEA modes if the CEA extension block is missing */ 3181 if (!drm_find_cea_extension(edid)) 3182 return 0; 3183 3184 /* 3185 * Go through all probed modes and create a new mode 3186 * with the alternate clock for certain CEA modes. 3187 */ 3188 list_for_each_entry(mode, &connector->probed_modes, head) { 3189 const struct drm_display_mode *cea_mode = NULL; 3190 struct drm_display_mode *newmode; 3191 u8 vic = drm_match_cea_mode(mode); 3192 unsigned int clock1, clock2; 3193 3194 if (drm_valid_cea_vic(vic)) { 3195 cea_mode = &edid_cea_modes[vic]; 3196 clock2 = cea_mode_alternate_clock(cea_mode); 3197 } else { 3198 vic = drm_match_hdmi_mode(mode); 3199 if (drm_valid_hdmi_vic(vic)) { 3200 cea_mode = &edid_4k_modes[vic]; 3201 clock2 = hdmi_mode_alternate_clock(cea_mode); 3202 } 3203 } 3204 3205 if (!cea_mode) 3206 continue; 3207 3208 clock1 = cea_mode->clock; 3209 3210 if (clock1 == clock2) 3211 continue; 3212 3213 if (mode->clock != clock1 && mode->clock != clock2) 3214 continue; 3215 3216 newmode = drm_mode_duplicate(dev, cea_mode); 3217 if (!newmode) 3218 continue; 3219 3220 /* Carry over the stereo flags */ 3221 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 3222 3223 /* 3224 * The current mode could be either variant. Make 3225 * sure to pick the "other" clock for the new mode. 3226 */ 3227 if (mode->clock != clock1) 3228 newmode->clock = clock1; 3229 else 3230 newmode->clock = clock2; 3231 3232 list_add_tail(&newmode->head, &list); 3233 } 3234 3235 list_for_each_entry_safe(mode, tmp, &list, head) { 3236 list_del(&mode->head); 3237 drm_mode_probed_add(connector, mode); 3238 modes++; 3239 } 3240 3241 return modes; 3242 } 3243 3244 static u8 svd_to_vic(u8 svd) 3245 { 3246 /* 0-6 bit vic, 7th bit native mode indicator */ 3247 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 3248 return svd & 127; 3249 3250 return svd; 3251 } 3252 3253 static struct drm_display_mode * 3254 drm_display_mode_from_vic_index(struct drm_connector *connector, 3255 const u8 *video_db, u8 video_len, 3256 u8 video_index) 3257 { 3258 struct drm_device *dev = connector->dev; 3259 struct drm_display_mode *newmode; 3260 u8 vic; 3261 3262 if (video_db == NULL || video_index >= video_len) 3263 return NULL; 3264 3265 /* CEA modes are numbered 1..127 */ 3266 vic = svd_to_vic(video_db[video_index]); 3267 if (!drm_valid_cea_vic(vic)) 3268 return NULL; 3269 3270 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]); 3271 if (!newmode) 3272 return NULL; 3273 3274 newmode->vrefresh = 0; 3275 3276 return newmode; 3277 } 3278 3279 /* 3280 * do_y420vdb_modes - Parse YCBCR 420 only modes 3281 * @connector: connector corresponding to the HDMI sink 3282 * @svds: start of the data block of CEA YCBCR 420 VDB 3283 * @len: length of the CEA YCBCR 420 VDB 3284 * 3285 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 3286 * which contains modes which can be supported in YCBCR 420 3287 * output format only. 3288 */ 3289 static int do_y420vdb_modes(struct drm_connector *connector, 3290 const u8 *svds, u8 svds_len) 3291 { 3292 int modes = 0, i; 3293 struct drm_device *dev = connector->dev; 3294 struct drm_display_info *info = &connector->display_info; 3295 struct drm_hdmi_info *hdmi = &info->hdmi; 3296 3297 for (i = 0; i < svds_len; i++) { 3298 u8 vic = svd_to_vic(svds[i]); 3299 struct drm_display_mode *newmode; 3300 3301 if (!drm_valid_cea_vic(vic)) 3302 continue; 3303 3304 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]); 3305 if (!newmode) 3306 break; 3307 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 3308 drm_mode_probed_add(connector, newmode); 3309 modes++; 3310 } 3311 3312 if (modes > 0) 3313 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3314 return modes; 3315 } 3316 3317 /* 3318 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap 3319 * @connector: connector corresponding to the HDMI sink 3320 * @vic: CEA vic for the video mode to be added in the map 3321 * 3322 * Makes an entry for a videomode in the YCBCR 420 bitmap 3323 */ 3324 static void 3325 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd) 3326 { 3327 u8 vic = svd_to_vic(svd); 3328 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3329 3330 if (!drm_valid_cea_vic(vic)) 3331 return; 3332 3333 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 3334 } 3335 3336 static int 3337 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 3338 { 3339 int i, modes = 0; 3340 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3341 3342 for (i = 0; i < len; i++) { 3343 struct drm_display_mode *mode; 3344 mode = drm_display_mode_from_vic_index(connector, db, len, i); 3345 if (mode) { 3346 /* 3347 * YCBCR420 capability block contains a bitmap which 3348 * gives the index of CEA modes from CEA VDB, which 3349 * can support YCBCR 420 sampling output also (apart 3350 * from RGB/YCBCR444 etc). 3351 * For example, if the bit 0 in bitmap is set, 3352 * first mode in VDB can support YCBCR420 output too. 3353 * Add YCBCR420 modes only if sink is HDMI 2.0 capable. 3354 */ 3355 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) 3356 drm_add_cmdb_modes(connector, db[i]); 3357 3358 drm_mode_probed_add(connector, mode); 3359 modes++; 3360 } 3361 } 3362 3363 return modes; 3364 } 3365 3366 struct stereo_mandatory_mode { 3367 int width, height, vrefresh; 3368 unsigned int flags; 3369 }; 3370 3371 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 3372 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3373 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3374 { 1920, 1080, 50, 3375 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3376 { 1920, 1080, 60, 3377 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3378 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3379 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3380 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3381 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 3382 }; 3383 3384 static bool 3385 stereo_match_mandatory(const struct drm_display_mode *mode, 3386 const struct stereo_mandatory_mode *stereo_mode) 3387 { 3388 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 3389 3390 return mode->hdisplay == stereo_mode->width && 3391 mode->vdisplay == stereo_mode->height && 3392 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 3393 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 3394 } 3395 3396 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 3397 { 3398 struct drm_device *dev = connector->dev; 3399 const struct drm_display_mode *mode; 3400 struct list_head stereo_modes; 3401 int modes = 0, i; 3402 3403 INIT_LIST_HEAD(&stereo_modes); 3404 3405 list_for_each_entry(mode, &connector->probed_modes, head) { 3406 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 3407 const struct stereo_mandatory_mode *mandatory; 3408 struct drm_display_mode *new_mode; 3409 3410 if (!stereo_match_mandatory(mode, 3411 &stereo_mandatory_modes[i])) 3412 continue; 3413 3414 mandatory = &stereo_mandatory_modes[i]; 3415 new_mode = drm_mode_duplicate(dev, mode); 3416 if (!new_mode) 3417 continue; 3418 3419 new_mode->flags |= mandatory->flags; 3420 list_add_tail(&new_mode->head, &stereo_modes); 3421 modes++; 3422 } 3423 } 3424 3425 list_splice_tail(&stereo_modes, &connector->probed_modes); 3426 3427 return modes; 3428 } 3429 3430 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 3431 { 3432 struct drm_device *dev = connector->dev; 3433 struct drm_display_mode *newmode; 3434 3435 if (!drm_valid_hdmi_vic(vic)) { 3436 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 3437 return 0; 3438 } 3439 3440 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 3441 if (!newmode) 3442 return 0; 3443 3444 drm_mode_probed_add(connector, newmode); 3445 3446 return 1; 3447 } 3448 3449 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 3450 const u8 *video_db, u8 video_len, u8 video_index) 3451 { 3452 struct drm_display_mode *newmode; 3453 int modes = 0; 3454 3455 if (structure & (1 << 0)) { 3456 newmode = drm_display_mode_from_vic_index(connector, video_db, 3457 video_len, 3458 video_index); 3459 if (newmode) { 3460 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 3461 drm_mode_probed_add(connector, newmode); 3462 modes++; 3463 } 3464 } 3465 if (structure & (1 << 6)) { 3466 newmode = drm_display_mode_from_vic_index(connector, video_db, 3467 video_len, 3468 video_index); 3469 if (newmode) { 3470 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3471 drm_mode_probed_add(connector, newmode); 3472 modes++; 3473 } 3474 } 3475 if (structure & (1 << 8)) { 3476 newmode = drm_display_mode_from_vic_index(connector, video_db, 3477 video_len, 3478 video_index); 3479 if (newmode) { 3480 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3481 drm_mode_probed_add(connector, newmode); 3482 modes++; 3483 } 3484 } 3485 3486 return modes; 3487 } 3488 3489 /* 3490 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 3491 * @connector: connector corresponding to the HDMI sink 3492 * @db: start of the CEA vendor specific block 3493 * @len: length of the CEA block payload, ie. one can access up to db[len] 3494 * 3495 * Parses the HDMI VSDB looking for modes to add to @connector. This function 3496 * also adds the stereo 3d modes when applicable. 3497 */ 3498 static int 3499 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 3500 const u8 *video_db, u8 video_len) 3501 { 3502 struct drm_display_info *info = &connector->display_info; 3503 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 3504 u8 vic_len, hdmi_3d_len = 0; 3505 u16 mask; 3506 u16 structure_all; 3507 3508 if (len < 8) 3509 goto out; 3510 3511 /* no HDMI_Video_Present */ 3512 if (!(db[8] & (1 << 5))) 3513 goto out; 3514 3515 /* Latency_Fields_Present */ 3516 if (db[8] & (1 << 7)) 3517 offset += 2; 3518 3519 /* I_Latency_Fields_Present */ 3520 if (db[8] & (1 << 6)) 3521 offset += 2; 3522 3523 /* the declared length is not long enough for the 2 first bytes 3524 * of additional video format capabilities */ 3525 if (len < (8 + offset + 2)) 3526 goto out; 3527 3528 /* 3D_Present */ 3529 offset++; 3530 if (db[8 + offset] & (1 << 7)) { 3531 modes += add_hdmi_mandatory_stereo_modes(connector); 3532 3533 /* 3D_Multi_present */ 3534 multi_present = (db[8 + offset] & 0x60) >> 5; 3535 } 3536 3537 offset++; 3538 vic_len = db[8 + offset] >> 5; 3539 hdmi_3d_len = db[8 + offset] & 0x1f; 3540 3541 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 3542 u8 vic; 3543 3544 vic = db[9 + offset + i]; 3545 modes += add_hdmi_mode(connector, vic); 3546 } 3547 offset += 1 + vic_len; 3548 3549 if (multi_present == 1) 3550 multi_len = 2; 3551 else if (multi_present == 2) 3552 multi_len = 4; 3553 else 3554 multi_len = 0; 3555 3556 if (len < (8 + offset + hdmi_3d_len - 1)) 3557 goto out; 3558 3559 if (hdmi_3d_len < multi_len) 3560 goto out; 3561 3562 if (multi_present == 1 || multi_present == 2) { 3563 /* 3D_Structure_ALL */ 3564 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 3565 3566 /* check if 3D_MASK is present */ 3567 if (multi_present == 2) 3568 mask = (db[10 + offset] << 8) | db[11 + offset]; 3569 else 3570 mask = 0xffff; 3571 3572 for (i = 0; i < 16; i++) { 3573 if (mask & (1 << i)) 3574 modes += add_3d_struct_modes(connector, 3575 structure_all, 3576 video_db, 3577 video_len, i); 3578 } 3579 } 3580 3581 offset += multi_len; 3582 3583 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 3584 int vic_index; 3585 struct drm_display_mode *newmode = NULL; 3586 unsigned int newflag = 0; 3587 bool detail_present; 3588 3589 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 3590 3591 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 3592 break; 3593 3594 /* 2D_VIC_order_X */ 3595 vic_index = db[8 + offset + i] >> 4; 3596 3597 /* 3D_Structure_X */ 3598 switch (db[8 + offset + i] & 0x0f) { 3599 case 0: 3600 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 3601 break; 3602 case 6: 3603 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3604 break; 3605 case 8: 3606 /* 3D_Detail_X */ 3607 if ((db[9 + offset + i] >> 4) == 1) 3608 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3609 break; 3610 } 3611 3612 if (newflag != 0) { 3613 newmode = drm_display_mode_from_vic_index(connector, 3614 video_db, 3615 video_len, 3616 vic_index); 3617 3618 if (newmode) { 3619 newmode->flags |= newflag; 3620 drm_mode_probed_add(connector, newmode); 3621 modes++; 3622 } 3623 } 3624 3625 if (detail_present) 3626 i++; 3627 } 3628 3629 out: 3630 if (modes > 0) 3631 info->has_hdmi_infoframe = true; 3632 return modes; 3633 } 3634 3635 static int 3636 cea_db_payload_len(const u8 *db) 3637 { 3638 return db[0] & 0x1f; 3639 } 3640 3641 static int 3642 cea_db_extended_tag(const u8 *db) 3643 { 3644 return db[1]; 3645 } 3646 3647 static int 3648 cea_db_tag(const u8 *db) 3649 { 3650 return db[0] >> 5; 3651 } 3652 3653 static int 3654 cea_revision(const u8 *cea) 3655 { 3656 return cea[1]; 3657 } 3658 3659 static int 3660 cea_db_offsets(const u8 *cea, int *start, int *end) 3661 { 3662 /* Data block offset in CEA extension block */ 3663 *start = 4; 3664 *end = cea[2]; 3665 if (*end == 0) 3666 *end = 127; 3667 if (*end < 4 || *end > 127) 3668 return -ERANGE; 3669 return 0; 3670 } 3671 3672 static bool cea_db_is_hdmi_vsdb(const u8 *db) 3673 { 3674 int hdmi_id; 3675 3676 if (cea_db_tag(db) != VENDOR_BLOCK) 3677 return false; 3678 3679 if (cea_db_payload_len(db) < 5) 3680 return false; 3681 3682 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 3683 3684 return hdmi_id == HDMI_IEEE_OUI; 3685 } 3686 3687 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db) 3688 { 3689 unsigned int oui; 3690 3691 if (cea_db_tag(db) != VENDOR_BLOCK) 3692 return false; 3693 3694 if (cea_db_payload_len(db) < 7) 3695 return false; 3696 3697 oui = db[3] << 16 | db[2] << 8 | db[1]; 3698 3699 return oui == HDMI_FORUM_IEEE_OUI; 3700 } 3701 3702 static bool cea_db_is_vcdb(const u8 *db) 3703 { 3704 if (cea_db_tag(db) != USE_EXTENDED_TAG) 3705 return false; 3706 3707 if (cea_db_payload_len(db) != 2) 3708 return false; 3709 3710 if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK) 3711 return false; 3712 3713 return true; 3714 } 3715 3716 static bool cea_db_is_y420cmdb(const u8 *db) 3717 { 3718 if (cea_db_tag(db) != USE_EXTENDED_TAG) 3719 return false; 3720 3721 if (!cea_db_payload_len(db)) 3722 return false; 3723 3724 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB) 3725 return false; 3726 3727 return true; 3728 } 3729 3730 static bool cea_db_is_y420vdb(const u8 *db) 3731 { 3732 if (cea_db_tag(db) != USE_EXTENDED_TAG) 3733 return false; 3734 3735 if (!cea_db_payload_len(db)) 3736 return false; 3737 3738 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420) 3739 return false; 3740 3741 return true; 3742 } 3743 3744 #define for_each_cea_db(cea, i, start, end) \ 3745 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 3746 3747 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector, 3748 const u8 *db) 3749 { 3750 struct drm_display_info *info = &connector->display_info; 3751 struct drm_hdmi_info *hdmi = &info->hdmi; 3752 u8 map_len = cea_db_payload_len(db) - 1; 3753 u8 count; 3754 u64 map = 0; 3755 3756 if (map_len == 0) { 3757 /* All CEA modes support ycbcr420 sampling also.*/ 3758 hdmi->y420_cmdb_map = U64_MAX; 3759 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3760 return; 3761 } 3762 3763 /* 3764 * This map indicates which of the existing CEA block modes 3765 * from VDB can support YCBCR420 output too. So if bit=0 is 3766 * set, first mode from VDB can support YCBCR420 output too. 3767 * We will parse and keep this map, before parsing VDB itself 3768 * to avoid going through the same block again and again. 3769 * 3770 * Spec is not clear about max possible size of this block. 3771 * Clamping max bitmap block size at 8 bytes. Every byte can 3772 * address 8 CEA modes, in this way this map can address 3773 * 8*8 = first 64 SVDs. 3774 */ 3775 if (WARN_ON_ONCE(map_len > 8)) 3776 map_len = 8; 3777 3778 for (count = 0; count < map_len; count++) 3779 map |= (u64)db[2 + count] << (8 * count); 3780 3781 if (map) 3782 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3783 3784 hdmi->y420_cmdb_map = map; 3785 } 3786 3787 static int 3788 add_cea_modes(struct drm_connector *connector, struct edid *edid) 3789 { 3790 const u8 *cea = drm_find_cea_extension(edid); 3791 const u8 *db, *hdmi = NULL, *video = NULL; 3792 u8 dbl, hdmi_len, video_len = 0; 3793 int modes = 0; 3794 3795 if (cea && cea_revision(cea) >= 3) { 3796 int i, start, end; 3797 3798 if (cea_db_offsets(cea, &start, &end)) 3799 return 0; 3800 3801 for_each_cea_db(cea, i, start, end) { 3802 db = &cea[i]; 3803 dbl = cea_db_payload_len(db); 3804 3805 if (cea_db_tag(db) == VIDEO_BLOCK) { 3806 video = db + 1; 3807 video_len = dbl; 3808 modes += do_cea_modes(connector, video, dbl); 3809 } else if (cea_db_is_hdmi_vsdb(db)) { 3810 hdmi = db; 3811 hdmi_len = dbl; 3812 } else if (cea_db_is_y420vdb(db)) { 3813 const u8 *vdb420 = &db[2]; 3814 3815 /* Add 4:2:0(only) modes present in EDID */ 3816 modes += do_y420vdb_modes(connector, 3817 vdb420, 3818 dbl - 1); 3819 } 3820 } 3821 } 3822 3823 /* 3824 * We parse the HDMI VSDB after having added the cea modes as we will 3825 * be patching their flags when the sink supports stereo 3D. 3826 */ 3827 if (hdmi) 3828 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, 3829 video_len); 3830 3831 return modes; 3832 } 3833 3834 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 3835 { 3836 const struct drm_display_mode *cea_mode; 3837 int clock1, clock2, clock; 3838 u8 vic; 3839 const char *type; 3840 3841 /* 3842 * allow 5kHz clock difference either way to account for 3843 * the 10kHz clock resolution limit of detailed timings. 3844 */ 3845 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 3846 if (drm_valid_cea_vic(vic)) { 3847 type = "CEA"; 3848 cea_mode = &edid_cea_modes[vic]; 3849 clock1 = cea_mode->clock; 3850 clock2 = cea_mode_alternate_clock(cea_mode); 3851 } else { 3852 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 3853 if (drm_valid_hdmi_vic(vic)) { 3854 type = "HDMI"; 3855 cea_mode = &edid_4k_modes[vic]; 3856 clock1 = cea_mode->clock; 3857 clock2 = hdmi_mode_alternate_clock(cea_mode); 3858 } else { 3859 return; 3860 } 3861 } 3862 3863 /* pick whichever is closest */ 3864 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 3865 clock = clock1; 3866 else 3867 clock = clock2; 3868 3869 if (mode->clock == clock) 3870 return; 3871 3872 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 3873 type, vic, mode->clock, clock); 3874 mode->clock = clock; 3875 } 3876 3877 static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db) 3878 { 3879 if (cea_db_tag(db) != USE_EXTENDED_TAG) 3880 return false; 3881 3882 if (db[1] != HDR_STATIC_METADATA_BLOCK) 3883 return false; 3884 3885 if (cea_db_payload_len(db) < 3) 3886 return false; 3887 3888 return true; 3889 } 3890 3891 static uint8_t eotf_supported(const u8 *edid_ext) 3892 { 3893 return edid_ext[2] & 3894 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) | 3895 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) | 3896 BIT(HDMI_EOTF_SMPTE_ST2084) | 3897 BIT(HDMI_EOTF_BT_2100_HLG)); 3898 } 3899 3900 static uint8_t hdr_metadata_type(const u8 *edid_ext) 3901 { 3902 return edid_ext[3] & 3903 BIT(HDMI_STATIC_METADATA_TYPE1); 3904 } 3905 3906 static void 3907 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db) 3908 { 3909 u16 len; 3910 3911 len = cea_db_payload_len(db); 3912 3913 connector->hdr_sink_metadata.hdmi_type1.eotf = 3914 eotf_supported(db); 3915 connector->hdr_sink_metadata.hdmi_type1.metadata_type = 3916 hdr_metadata_type(db); 3917 3918 if (len >= 4) 3919 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4]; 3920 if (len >= 5) 3921 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5]; 3922 if (len >= 6) 3923 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6]; 3924 } 3925 3926 static void 3927 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 3928 { 3929 u8 len = cea_db_payload_len(db); 3930 3931 if (len >= 6 && (db[6] & (1 << 7))) 3932 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI; 3933 if (len >= 8) { 3934 connector->latency_present[0] = db[8] >> 7; 3935 connector->latency_present[1] = (db[8] >> 6) & 1; 3936 } 3937 if (len >= 9) 3938 connector->video_latency[0] = db[9]; 3939 if (len >= 10) 3940 connector->audio_latency[0] = db[10]; 3941 if (len >= 11) 3942 connector->video_latency[1] = db[11]; 3943 if (len >= 12) 3944 connector->audio_latency[1] = db[12]; 3945 3946 DRM_DEBUG_KMS("HDMI: latency present %d %d, " 3947 "video latency %d %d, " 3948 "audio latency %d %d\n", 3949 connector->latency_present[0], 3950 connector->latency_present[1], 3951 connector->video_latency[0], 3952 connector->video_latency[1], 3953 connector->audio_latency[0], 3954 connector->audio_latency[1]); 3955 } 3956 3957 static void 3958 monitor_name(struct detailed_timing *t, void *data) 3959 { 3960 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME) 3961 *(u8 **)data = t->data.other_data.data.str.str; 3962 } 3963 3964 static int get_monitor_name(struct edid *edid, char name[13]) 3965 { 3966 char *edid_name = NULL; 3967 int mnl; 3968 3969 if (!edid || !name) 3970 return 0; 3971 3972 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name); 3973 for (mnl = 0; edid_name && mnl < 13; mnl++) { 3974 if (edid_name[mnl] == 0x0a) 3975 break; 3976 3977 name[mnl] = edid_name[mnl]; 3978 } 3979 3980 return mnl; 3981 } 3982 3983 /** 3984 * drm_edid_get_monitor_name - fetch the monitor name from the edid 3985 * @edid: monitor EDID information 3986 * @name: pointer to a character array to hold the name of the monitor 3987 * @bufsize: The size of the name buffer (should be at least 14 chars.) 3988 * 3989 */ 3990 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize) 3991 { 3992 int name_length; 3993 char buf[13]; 3994 3995 if (bufsize <= 0) 3996 return; 3997 3998 name_length = min(get_monitor_name(edid, buf), bufsize - 1); 3999 memcpy(name, buf, name_length); 4000 name[name_length] = '\0'; 4001 } 4002 EXPORT_SYMBOL(drm_edid_get_monitor_name); 4003 4004 static void clear_eld(struct drm_connector *connector) 4005 { 4006 memset(connector->eld, 0, sizeof(connector->eld)); 4007 4008 connector->latency_present[0] = false; 4009 connector->latency_present[1] = false; 4010 connector->video_latency[0] = 0; 4011 connector->audio_latency[0] = 0; 4012 connector->video_latency[1] = 0; 4013 connector->audio_latency[1] = 0; 4014 } 4015 4016 /* 4017 * drm_edid_to_eld - build ELD from EDID 4018 * @connector: connector corresponding to the HDMI/DP sink 4019 * @edid: EDID to parse 4020 * 4021 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 4022 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 4023 */ 4024 static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 4025 { 4026 uint8_t *eld = connector->eld; 4027 u8 *cea; 4028 u8 *db; 4029 int total_sad_count = 0; 4030 int mnl; 4031 int dbl; 4032 4033 clear_eld(connector); 4034 4035 if (!edid) 4036 return; 4037 4038 cea = drm_find_cea_extension(edid); 4039 if (!cea) { 4040 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 4041 return; 4042 } 4043 4044 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]); 4045 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]); 4046 4047 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT; 4048 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl; 4049 4050 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D; 4051 4052 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0]; 4053 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1]; 4054 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0]; 4055 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1]; 4056 4057 if (cea_revision(cea) >= 3) { 4058 int i, start, end; 4059 4060 if (cea_db_offsets(cea, &start, &end)) { 4061 start = 0; 4062 end = 0; 4063 } 4064 4065 for_each_cea_db(cea, i, start, end) { 4066 db = &cea[i]; 4067 dbl = cea_db_payload_len(db); 4068 4069 switch (cea_db_tag(db)) { 4070 int sad_count; 4071 4072 case AUDIO_BLOCK: 4073 /* Audio Data Block, contains SADs */ 4074 sad_count = min(dbl / 3, 15 - total_sad_count); 4075 if (sad_count >= 1) 4076 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)], 4077 &db[1], sad_count * 3); 4078 total_sad_count += sad_count; 4079 break; 4080 case SPEAKER_BLOCK: 4081 /* Speaker Allocation Data Block */ 4082 if (dbl >= 1) 4083 eld[DRM_ELD_SPEAKER] = db[1]; 4084 break; 4085 case VENDOR_BLOCK: 4086 /* HDMI Vendor-Specific Data Block */ 4087 if (cea_db_is_hdmi_vsdb(db)) 4088 drm_parse_hdmi_vsdb_audio(connector, db); 4089 break; 4090 default: 4091 break; 4092 } 4093 } 4094 } 4095 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT; 4096 4097 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 4098 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 4099 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 4100 else 4101 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 4102 4103 eld[DRM_ELD_BASELINE_ELD_LEN] = 4104 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 4105 4106 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", 4107 drm_eld_size(eld), total_sad_count); 4108 } 4109 4110 /** 4111 * drm_edid_to_sad - extracts SADs from EDID 4112 * @edid: EDID to parse 4113 * @sads: pointer that will be set to the extracted SADs 4114 * 4115 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 4116 * 4117 * Note: The returned pointer needs to be freed using kfree(). 4118 * 4119 * Return: The number of found SADs or negative number on error. 4120 */ 4121 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) 4122 { 4123 int count = 0; 4124 int i, start, end, dbl; 4125 u8 *cea; 4126 4127 cea = drm_find_cea_extension(edid); 4128 if (!cea) { 4129 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4130 return -ENOENT; 4131 } 4132 4133 if (cea_revision(cea) < 3) { 4134 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4135 return -ENOTSUPP; 4136 } 4137 4138 if (cea_db_offsets(cea, &start, &end)) { 4139 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4140 return -EPROTO; 4141 } 4142 4143 for_each_cea_db(cea, i, start, end) { 4144 u8 *db = &cea[i]; 4145 4146 if (cea_db_tag(db) == AUDIO_BLOCK) { 4147 int j; 4148 dbl = cea_db_payload_len(db); 4149 4150 count = dbl / 3; /* SAD is 3B */ 4151 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 4152 if (!*sads) 4153 return -ENOMEM; 4154 for (j = 0; j < count; j++) { 4155 u8 *sad = &db[1 + j * 3]; 4156 4157 (*sads)[j].format = (sad[0] & 0x78) >> 3; 4158 (*sads)[j].channels = sad[0] & 0x7; 4159 (*sads)[j].freq = sad[1] & 0x7F; 4160 (*sads)[j].byte2 = sad[2]; 4161 } 4162 break; 4163 } 4164 } 4165 4166 return count; 4167 } 4168 EXPORT_SYMBOL(drm_edid_to_sad); 4169 4170 /** 4171 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 4172 * @edid: EDID to parse 4173 * @sadb: pointer to the speaker block 4174 * 4175 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 4176 * 4177 * Note: The returned pointer needs to be freed using kfree(). 4178 * 4179 * Return: The number of found Speaker Allocation Blocks or negative number on 4180 * error. 4181 */ 4182 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) 4183 { 4184 int count = 0; 4185 int i, start, end, dbl; 4186 const u8 *cea; 4187 4188 cea = drm_find_cea_extension(edid); 4189 if (!cea) { 4190 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4191 return -ENOENT; 4192 } 4193 4194 if (cea_revision(cea) < 3) { 4195 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4196 return -ENOTSUPP; 4197 } 4198 4199 if (cea_db_offsets(cea, &start, &end)) { 4200 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4201 return -EPROTO; 4202 } 4203 4204 for_each_cea_db(cea, i, start, end) { 4205 const u8 *db = &cea[i]; 4206 4207 if (cea_db_tag(db) == SPEAKER_BLOCK) { 4208 dbl = cea_db_payload_len(db); 4209 4210 /* Speaker Allocation Data Block */ 4211 if (dbl == 3) { 4212 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); 4213 if (!*sadb) 4214 return -ENOMEM; 4215 count = dbl; 4216 break; 4217 } 4218 } 4219 } 4220 4221 return count; 4222 } 4223 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 4224 4225 /** 4226 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 4227 * @connector: connector associated with the HDMI/DP sink 4228 * @mode: the display mode 4229 * 4230 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 4231 * the sink doesn't support audio or video. 4232 */ 4233 int drm_av_sync_delay(struct drm_connector *connector, 4234 const struct drm_display_mode *mode) 4235 { 4236 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 4237 int a, v; 4238 4239 if (!connector->latency_present[0]) 4240 return 0; 4241 if (!connector->latency_present[1]) 4242 i = 0; 4243 4244 a = connector->audio_latency[i]; 4245 v = connector->video_latency[i]; 4246 4247 /* 4248 * HDMI/DP sink doesn't support audio or video? 4249 */ 4250 if (a == 255 || v == 255) 4251 return 0; 4252 4253 /* 4254 * Convert raw EDID values to millisecond. 4255 * Treat unknown latency as 0ms. 4256 */ 4257 if (a) 4258 a = min(2 * (a - 1), 500); 4259 if (v) 4260 v = min(2 * (v - 1), 500); 4261 4262 return max(v - a, 0); 4263 } 4264 EXPORT_SYMBOL(drm_av_sync_delay); 4265 4266 /** 4267 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 4268 * @edid: monitor EDID information 4269 * 4270 * Parse the CEA extension according to CEA-861-B. 4271 * 4272 * Return: True if the monitor is HDMI, false if not or unknown. 4273 */ 4274 bool drm_detect_hdmi_monitor(struct edid *edid) 4275 { 4276 u8 *edid_ext; 4277 int i; 4278 int start_offset, end_offset; 4279 4280 edid_ext = drm_find_cea_extension(edid); 4281 if (!edid_ext) 4282 return false; 4283 4284 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4285 return false; 4286 4287 /* 4288 * Because HDMI identifier is in Vendor Specific Block, 4289 * search it from all data blocks of CEA extension. 4290 */ 4291 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4292 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 4293 return true; 4294 } 4295 4296 return false; 4297 } 4298 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 4299 4300 /** 4301 * drm_detect_monitor_audio - check monitor audio capability 4302 * @edid: EDID block to scan 4303 * 4304 * Monitor should have CEA extension block. 4305 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 4306 * audio' only. If there is any audio extension block and supported 4307 * audio format, assume at least 'basic audio' support, even if 'basic 4308 * audio' is not defined in EDID. 4309 * 4310 * Return: True if the monitor supports audio, false otherwise. 4311 */ 4312 bool drm_detect_monitor_audio(struct edid *edid) 4313 { 4314 u8 *edid_ext; 4315 int i, j; 4316 bool has_audio = false; 4317 int start_offset, end_offset; 4318 4319 edid_ext = drm_find_cea_extension(edid); 4320 if (!edid_ext) 4321 goto end; 4322 4323 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 4324 4325 if (has_audio) { 4326 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 4327 goto end; 4328 } 4329 4330 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4331 goto end; 4332 4333 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4334 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 4335 has_audio = true; 4336 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 4337 DRM_DEBUG_KMS("CEA audio format %d\n", 4338 (edid_ext[i + j] >> 3) & 0xf); 4339 goto end; 4340 } 4341 } 4342 end: 4343 return has_audio; 4344 } 4345 EXPORT_SYMBOL(drm_detect_monitor_audio); 4346 4347 4348 /** 4349 * drm_default_rgb_quant_range - default RGB quantization range 4350 * @mode: display mode 4351 * 4352 * Determine the default RGB quantization range for the mode, 4353 * as specified in CEA-861. 4354 * 4355 * Return: The default RGB quantization range for the mode 4356 */ 4357 enum hdmi_quantization_range 4358 drm_default_rgb_quant_range(const struct drm_display_mode *mode) 4359 { 4360 /* All CEA modes other than VIC 1 use limited quantization range. */ 4361 return drm_match_cea_mode(mode) > 1 ? 4362 HDMI_QUANTIZATION_RANGE_LIMITED : 4363 HDMI_QUANTIZATION_RANGE_FULL; 4364 } 4365 EXPORT_SYMBOL(drm_default_rgb_quant_range); 4366 4367 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db) 4368 { 4369 struct drm_display_info *info = &connector->display_info; 4370 4371 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]); 4372 4373 if (db[2] & EDID_CEA_VCDB_QS) 4374 info->rgb_quant_range_selectable = true; 4375 } 4376 4377 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 4378 const u8 *db) 4379 { 4380 u8 dc_mask; 4381 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 4382 4383 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 4384 hdmi->y420_dc_modes = dc_mask; 4385 } 4386 4387 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector, 4388 const u8 *hf_vsdb) 4389 { 4390 struct drm_display_info *display = &connector->display_info; 4391 struct drm_hdmi_info *hdmi = &display->hdmi; 4392 4393 display->has_hdmi_infoframe = true; 4394 4395 if (hf_vsdb[6] & 0x80) { 4396 hdmi->scdc.supported = true; 4397 if (hf_vsdb[6] & 0x40) 4398 hdmi->scdc.read_request = true; 4399 } 4400 4401 /* 4402 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 4403 * And as per the spec, three factors confirm this: 4404 * * Availability of a HF-VSDB block in EDID (check) 4405 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 4406 * * SCDC support available (let's check) 4407 * Lets check it out. 4408 */ 4409 4410 if (hf_vsdb[5]) { 4411 /* max clock is 5000 KHz times block value */ 4412 u32 max_tmds_clock = hf_vsdb[5] * 5000; 4413 struct drm_scdc *scdc = &hdmi->scdc; 4414 4415 if (max_tmds_clock > 340000) { 4416 display->max_tmds_clock = max_tmds_clock; 4417 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n", 4418 display->max_tmds_clock); 4419 } 4420 4421 if (scdc->supported) { 4422 scdc->scrambling.supported = true; 4423 4424 /* Few sinks support scrambling for cloks < 340M */ 4425 if ((hf_vsdb[6] & 0x8)) 4426 scdc->scrambling.low_rates = true; 4427 } 4428 } 4429 4430 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb); 4431 } 4432 4433 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 4434 const u8 *hdmi) 4435 { 4436 struct drm_display_info *info = &connector->display_info; 4437 unsigned int dc_bpc = 0; 4438 4439 /* HDMI supports at least 8 bpc */ 4440 info->bpc = 8; 4441 4442 if (cea_db_payload_len(hdmi) < 6) 4443 return; 4444 4445 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 4446 dc_bpc = 10; 4447 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 4448 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 4449 connector->name); 4450 } 4451 4452 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 4453 dc_bpc = 12; 4454 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 4455 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 4456 connector->name); 4457 } 4458 4459 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 4460 dc_bpc = 16; 4461 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 4462 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 4463 connector->name); 4464 } 4465 4466 if (dc_bpc == 0) { 4467 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 4468 connector->name); 4469 return; 4470 } 4471 4472 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 4473 connector->name, dc_bpc); 4474 info->bpc = dc_bpc; 4475 4476 /* 4477 * Deep color support mandates RGB444 support for all video 4478 * modes and forbids YCRCB422 support for all video modes per 4479 * HDMI 1.3 spec. 4480 */ 4481 info->color_formats = DRM_COLOR_FORMAT_RGB444; 4482 4483 /* YCRCB444 is optional according to spec. */ 4484 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 4485 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4486 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 4487 connector->name); 4488 } 4489 4490 /* 4491 * Spec says that if any deep color mode is supported at all, 4492 * then deep color 36 bit must be supported. 4493 */ 4494 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 4495 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 4496 connector->name); 4497 } 4498 } 4499 4500 static void 4501 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 4502 { 4503 struct drm_display_info *info = &connector->display_info; 4504 u8 len = cea_db_payload_len(db); 4505 4506 if (len >= 6) 4507 info->dvi_dual = db[6] & 1; 4508 if (len >= 7) 4509 info->max_tmds_clock = db[7] * 5000; 4510 4511 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 4512 "max TMDS clock %d kHz\n", 4513 info->dvi_dual, 4514 info->max_tmds_clock); 4515 4516 drm_parse_hdmi_deep_color_info(connector, db); 4517 } 4518 4519 static void drm_parse_cea_ext(struct drm_connector *connector, 4520 const struct edid *edid) 4521 { 4522 struct drm_display_info *info = &connector->display_info; 4523 const u8 *edid_ext; 4524 int i, start, end; 4525 4526 edid_ext = drm_find_cea_extension(edid); 4527 if (!edid_ext) 4528 return; 4529 4530 info->cea_rev = edid_ext[1]; 4531 4532 /* The existence of a CEA block should imply RGB support */ 4533 info->color_formats = DRM_COLOR_FORMAT_RGB444; 4534 if (edid_ext[3] & EDID_CEA_YCRCB444) 4535 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4536 if (edid_ext[3] & EDID_CEA_YCRCB422) 4537 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 4538 4539 if (cea_db_offsets(edid_ext, &start, &end)) 4540 return; 4541 4542 for_each_cea_db(edid_ext, i, start, end) { 4543 const u8 *db = &edid_ext[i]; 4544 4545 if (cea_db_is_hdmi_vsdb(db)) 4546 drm_parse_hdmi_vsdb_video(connector, db); 4547 if (cea_db_is_hdmi_forum_vsdb(db)) 4548 drm_parse_hdmi_forum_vsdb(connector, db); 4549 if (cea_db_is_y420cmdb(db)) 4550 drm_parse_y420cmdb_bitmap(connector, db); 4551 if (cea_db_is_vcdb(db)) 4552 drm_parse_vcdb(connector, db); 4553 if (cea_db_is_hdmi_hdr_metadata_block(db)) 4554 drm_parse_hdr_metadata_block(connector, db); 4555 } 4556 } 4557 4558 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset 4559 * all of the values which would have been set from EDID 4560 */ 4561 void 4562 drm_reset_display_info(struct drm_connector *connector) 4563 { 4564 struct drm_display_info *info = &connector->display_info; 4565 4566 info->width_mm = 0; 4567 info->height_mm = 0; 4568 4569 info->bpc = 0; 4570 info->color_formats = 0; 4571 info->cea_rev = 0; 4572 info->max_tmds_clock = 0; 4573 info->dvi_dual = false; 4574 info->has_hdmi_infoframe = false; 4575 info->rgb_quant_range_selectable = false; 4576 memset(&info->hdmi, 0, sizeof(info->hdmi)); 4577 4578 info->non_desktop = 0; 4579 } 4580 4581 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid) 4582 { 4583 struct drm_display_info *info = &connector->display_info; 4584 4585 u32 quirks = edid_get_quirks(edid); 4586 4587 drm_reset_display_info(connector); 4588 4589 info->width_mm = edid->width_cm * 10; 4590 info->height_mm = edid->height_cm * 10; 4591 4592 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP); 4593 4594 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop); 4595 4596 if (edid->revision < 3) 4597 return quirks; 4598 4599 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 4600 return quirks; 4601 4602 drm_parse_cea_ext(connector, edid); 4603 4604 /* 4605 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 4606 * 4607 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 4608 * tells us to assume 8 bpc color depth if the EDID doesn't have 4609 * extensions which tell otherwise. 4610 */ 4611 if (info->bpc == 0 && edid->revision == 3 && 4612 edid->input & DRM_EDID_DIGITAL_DFP_1_X) { 4613 info->bpc = 8; 4614 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n", 4615 connector->name, info->bpc); 4616 } 4617 4618 /* Only defined for 1.4 with digital displays */ 4619 if (edid->revision < 4) 4620 return quirks; 4621 4622 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 4623 case DRM_EDID_DIGITAL_DEPTH_6: 4624 info->bpc = 6; 4625 break; 4626 case DRM_EDID_DIGITAL_DEPTH_8: 4627 info->bpc = 8; 4628 break; 4629 case DRM_EDID_DIGITAL_DEPTH_10: 4630 info->bpc = 10; 4631 break; 4632 case DRM_EDID_DIGITAL_DEPTH_12: 4633 info->bpc = 12; 4634 break; 4635 case DRM_EDID_DIGITAL_DEPTH_14: 4636 info->bpc = 14; 4637 break; 4638 case DRM_EDID_DIGITAL_DEPTH_16: 4639 info->bpc = 16; 4640 break; 4641 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 4642 default: 4643 info->bpc = 0; 4644 break; 4645 } 4646 4647 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 4648 connector->name, info->bpc); 4649 4650 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 4651 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 4652 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4653 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 4654 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 4655 return quirks; 4656 } 4657 4658 static int validate_displayid(u8 *displayid, int length, int idx) 4659 { 4660 int i; 4661 u8 csum = 0; 4662 struct displayid_hdr *base; 4663 4664 base = (struct displayid_hdr *)&displayid[idx]; 4665 4666 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n", 4667 base->rev, base->bytes, base->prod_id, base->ext_count); 4668 4669 if (base->bytes + 5 > length - idx) 4670 return -EINVAL; 4671 for (i = idx; i <= base->bytes + 5; i++) { 4672 csum += displayid[i]; 4673 } 4674 if (csum) { 4675 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum); 4676 return -EINVAL; 4677 } 4678 return 0; 4679 } 4680 4681 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 4682 struct displayid_detailed_timings_1 *timings) 4683 { 4684 struct drm_display_mode *mode; 4685 unsigned pixel_clock = (timings->pixel_clock[0] | 4686 (timings->pixel_clock[1] << 8) | 4687 (timings->pixel_clock[2] << 16)); 4688 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 4689 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 4690 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 4691 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 4692 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 4693 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 4694 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 4695 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 4696 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 4697 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 4698 mode = drm_mode_create(dev); 4699 if (!mode) 4700 return NULL; 4701 4702 mode->clock = pixel_clock * 10; 4703 mode->hdisplay = hactive; 4704 mode->hsync_start = mode->hdisplay + hsync; 4705 mode->hsync_end = mode->hsync_start + hsync_width; 4706 mode->htotal = mode->hdisplay + hblank; 4707 4708 mode->vdisplay = vactive; 4709 mode->vsync_start = mode->vdisplay + vsync; 4710 mode->vsync_end = mode->vsync_start + vsync_width; 4711 mode->vtotal = mode->vdisplay + vblank; 4712 4713 mode->flags = 0; 4714 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 4715 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 4716 mode->type = DRM_MODE_TYPE_DRIVER; 4717 4718 if (timings->flags & 0x80) 4719 mode->type |= DRM_MODE_TYPE_PREFERRED; 4720 mode->vrefresh = drm_mode_vrefresh(mode); 4721 drm_mode_set_name(mode); 4722 4723 return mode; 4724 } 4725 4726 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 4727 struct displayid_block *block) 4728 { 4729 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 4730 int i; 4731 int num_timings; 4732 struct drm_display_mode *newmode; 4733 int num_modes = 0; 4734 /* blocks must be multiple of 20 bytes length */ 4735 if (block->num_bytes % 20) 4736 return 0; 4737 4738 num_timings = block->num_bytes / 20; 4739 for (i = 0; i < num_timings; i++) { 4740 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 4741 4742 newmode = drm_mode_displayid_detailed(connector->dev, timings); 4743 if (!newmode) 4744 continue; 4745 4746 drm_mode_probed_add(connector, newmode); 4747 num_modes++; 4748 } 4749 return num_modes; 4750 } 4751 4752 static int add_displayid_detailed_modes(struct drm_connector *connector, 4753 struct edid *edid) 4754 { 4755 u8 *displayid; 4756 int ret; 4757 int idx = 1; 4758 int length = EDID_LENGTH; 4759 struct displayid_block *block; 4760 int num_modes = 0; 4761 4762 displayid = drm_find_displayid_extension(edid); 4763 if (!displayid) 4764 return 0; 4765 4766 ret = validate_displayid(displayid, length, idx); 4767 if (ret) 4768 return 0; 4769 4770 idx += sizeof(struct displayid_hdr); 4771 while (block = (struct displayid_block *)&displayid[idx], 4772 idx + sizeof(struct displayid_block) <= length && 4773 idx + sizeof(struct displayid_block) + block->num_bytes <= length && 4774 block->num_bytes > 0) { 4775 idx += block->num_bytes + sizeof(struct displayid_block); 4776 switch (block->tag) { 4777 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 4778 num_modes += add_displayid_detailed_1_modes(connector, block); 4779 break; 4780 } 4781 } 4782 return num_modes; 4783 } 4784 4785 /** 4786 * drm_add_edid_modes - add modes from EDID data, if available 4787 * @connector: connector we're probing 4788 * @edid: EDID data 4789 * 4790 * Add the specified modes to the connector's mode list. Also fills out the 4791 * &drm_display_info structure and ELD in @connector with any information which 4792 * can be derived from the edid. 4793 * 4794 * Return: The number of modes added or 0 if we couldn't find any. 4795 */ 4796 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 4797 { 4798 int num_modes = 0; 4799 u32 quirks; 4800 4801 if (edid == NULL) { 4802 clear_eld(connector); 4803 return 0; 4804 } 4805 if (!drm_edid_is_valid(edid)) { 4806 clear_eld(connector); 4807 dev_warn(connector->dev->dev, "%s: EDID invalid.\n", 4808 connector->name); 4809 return 0; 4810 } 4811 4812 drm_edid_to_eld(connector, edid); 4813 4814 /* 4815 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. 4816 * To avoid multiple parsing of same block, lets parse that map 4817 * from sink info, before parsing CEA modes. 4818 */ 4819 quirks = drm_add_display_info(connector, edid); 4820 4821 /* 4822 * EDID spec says modes should be preferred in this order: 4823 * - preferred detailed mode 4824 * - other detailed modes from base block 4825 * - detailed modes from extension blocks 4826 * - CVT 3-byte code modes 4827 * - standard timing codes 4828 * - established timing codes 4829 * - modes inferred from GTF or CVT range information 4830 * 4831 * We get this pretty much right. 4832 * 4833 * XXX order for additional mode types in extension blocks? 4834 */ 4835 num_modes += add_detailed_modes(connector, edid, quirks); 4836 num_modes += add_cvt_modes(connector, edid); 4837 num_modes += add_standard_modes(connector, edid); 4838 num_modes += add_established_modes(connector, edid); 4839 num_modes += add_cea_modes(connector, edid); 4840 num_modes += add_alternate_cea_modes(connector, edid); 4841 num_modes += add_displayid_detailed_modes(connector, edid); 4842 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 4843 num_modes += add_inferred_modes(connector, edid); 4844 4845 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 4846 edid_fixup_preferred(connector, quirks); 4847 4848 if (quirks & EDID_QUIRK_FORCE_6BPC) 4849 connector->display_info.bpc = 6; 4850 4851 if (quirks & EDID_QUIRK_FORCE_8BPC) 4852 connector->display_info.bpc = 8; 4853 4854 if (quirks & EDID_QUIRK_FORCE_10BPC) 4855 connector->display_info.bpc = 10; 4856 4857 if (quirks & EDID_QUIRK_FORCE_12BPC) 4858 connector->display_info.bpc = 12; 4859 4860 return num_modes; 4861 } 4862 EXPORT_SYMBOL(drm_add_edid_modes); 4863 4864 /** 4865 * drm_add_modes_noedid - add modes for the connectors without EDID 4866 * @connector: connector we're probing 4867 * @hdisplay: the horizontal display limit 4868 * @vdisplay: the vertical display limit 4869 * 4870 * Add the specified modes to the connector's mode list. Only when the 4871 * hdisplay/vdisplay is not beyond the given limit, it will be added. 4872 * 4873 * Return: The number of modes added or 0 if we couldn't find any. 4874 */ 4875 int drm_add_modes_noedid(struct drm_connector *connector, 4876 int hdisplay, int vdisplay) 4877 { 4878 int i, count, num_modes = 0; 4879 struct drm_display_mode *mode; 4880 struct drm_device *dev = connector->dev; 4881 4882 count = ARRAY_SIZE(drm_dmt_modes); 4883 if (hdisplay < 0) 4884 hdisplay = 0; 4885 if (vdisplay < 0) 4886 vdisplay = 0; 4887 4888 for (i = 0; i < count; i++) { 4889 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 4890 if (hdisplay && vdisplay) { 4891 /* 4892 * Only when two are valid, they will be used to check 4893 * whether the mode should be added to the mode list of 4894 * the connector. 4895 */ 4896 if (ptr->hdisplay > hdisplay || 4897 ptr->vdisplay > vdisplay) 4898 continue; 4899 } 4900 if (drm_mode_vrefresh(ptr) > 61) 4901 continue; 4902 mode = drm_mode_duplicate(dev, ptr); 4903 if (mode) { 4904 drm_mode_probed_add(connector, mode); 4905 num_modes++; 4906 } 4907 } 4908 return num_modes; 4909 } 4910 EXPORT_SYMBOL(drm_add_modes_noedid); 4911 4912 /** 4913 * drm_set_preferred_mode - Sets the preferred mode of a connector 4914 * @connector: connector whose mode list should be processed 4915 * @hpref: horizontal resolution of preferred mode 4916 * @vpref: vertical resolution of preferred mode 4917 * 4918 * Marks a mode as preferred if it matches the resolution specified by @hpref 4919 * and @vpref. 4920 */ 4921 void drm_set_preferred_mode(struct drm_connector *connector, 4922 int hpref, int vpref) 4923 { 4924 struct drm_display_mode *mode; 4925 4926 list_for_each_entry(mode, &connector->probed_modes, head) { 4927 if (mode->hdisplay == hpref && 4928 mode->vdisplay == vpref) 4929 mode->type |= DRM_MODE_TYPE_PREFERRED; 4930 } 4931 } 4932 EXPORT_SYMBOL(drm_set_preferred_mode); 4933 4934 static bool is_hdmi2_sink(struct drm_connector *connector) 4935 { 4936 /* 4937 * FIXME: sil-sii8620 doesn't have a connector around when 4938 * we need one, so we have to be prepared for a NULL connector. 4939 */ 4940 if (!connector) 4941 return true; 4942 4943 return connector->display_info.hdmi.scdc.supported || 4944 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420; 4945 } 4946 4947 static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf) 4948 { 4949 return sink_eotf & BIT(output_eotf); 4950 } 4951 4952 /** 4953 * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with 4954 * HDR metadata from userspace 4955 * @frame: HDMI DRM infoframe 4956 * @conn_state: Connector state containing HDR metadata 4957 * 4958 * Return: 0 on success or a negative error code on failure. 4959 */ 4960 int 4961 drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame, 4962 const struct drm_connector_state *conn_state) 4963 { 4964 struct drm_connector *connector; 4965 struct hdr_output_metadata *hdr_metadata; 4966 int err; 4967 4968 if (!frame || !conn_state) 4969 return -EINVAL; 4970 4971 connector = conn_state->connector; 4972 4973 if (!conn_state->hdr_output_metadata) 4974 return -EINVAL; 4975 4976 hdr_metadata = conn_state->hdr_output_metadata->data; 4977 4978 if (!hdr_metadata || !connector) 4979 return -EINVAL; 4980 4981 /* Sink EOTF is Bit map while infoframe is absolute values */ 4982 if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf, 4983 connector->hdr_sink_metadata.hdmi_type1.eotf)) { 4984 DRM_DEBUG_KMS("EOTF Not Supported\n"); 4985 return -EINVAL; 4986 } 4987 4988 err = hdmi_drm_infoframe_init(frame); 4989 if (err < 0) 4990 return err; 4991 4992 frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf; 4993 frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type; 4994 4995 BUILD_BUG_ON(sizeof(frame->display_primaries) != 4996 sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries)); 4997 BUILD_BUG_ON(sizeof(frame->white_point) != 4998 sizeof(hdr_metadata->hdmi_metadata_type1.white_point)); 4999 5000 memcpy(&frame->display_primaries, 5001 &hdr_metadata->hdmi_metadata_type1.display_primaries, 5002 sizeof(frame->display_primaries)); 5003 5004 memcpy(&frame->white_point, 5005 &hdr_metadata->hdmi_metadata_type1.white_point, 5006 sizeof(frame->white_point)); 5007 5008 frame->max_display_mastering_luminance = 5009 hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance; 5010 frame->min_display_mastering_luminance = 5011 hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance; 5012 frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall; 5013 frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll; 5014 5015 return 0; 5016 } 5017 EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata); 5018 5019 /** 5020 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 5021 * data from a DRM display mode 5022 * @frame: HDMI AVI infoframe 5023 * @connector: the connector 5024 * @mode: DRM display mode 5025 * 5026 * Return: 0 on success or a negative error code on failure. 5027 */ 5028 int 5029 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 5030 struct drm_connector *connector, 5031 const struct drm_display_mode *mode) 5032 { 5033 enum hdmi_picture_aspect picture_aspect; 5034 int err; 5035 5036 if (!frame || !mode) 5037 return -EINVAL; 5038 5039 err = hdmi_avi_infoframe_init(frame); 5040 if (err < 0) 5041 return err; 5042 5043 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 5044 frame->pixel_repeat = 1; 5045 5046 frame->video_code = drm_match_cea_mode(mode); 5047 5048 /* 5049 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but 5050 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we 5051 * have to make sure we dont break HDMI 1.4 sinks. 5052 */ 5053 if (!is_hdmi2_sink(connector) && frame->video_code > 64) 5054 frame->video_code = 0; 5055 5056 /* 5057 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 5058 * we should send its VIC in vendor infoframes, else send the 5059 * VIC in AVI infoframes. Lets check if this mode is present in 5060 * HDMI 1.4b 4K modes 5061 */ 5062 if (frame->video_code) { 5063 u8 vendor_if_vic = drm_match_hdmi_mode(mode); 5064 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK; 5065 5066 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d) 5067 frame->video_code = 0; 5068 } 5069 5070 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5071 5072 /* 5073 * As some drivers don't support atomic, we can't use connector state. 5074 * So just initialize the frame with default values, just the same way 5075 * as it's done with other properties here. 5076 */ 5077 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; 5078 frame->itc = 0; 5079 5080 /* 5081 * Populate picture aspect ratio from either 5082 * user input (if specified) or from the CEA mode list. 5083 */ 5084 picture_aspect = mode->picture_aspect_ratio; 5085 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) 5086 picture_aspect = drm_get_cea_aspect_ratio(frame->video_code); 5087 5088 /* 5089 * The infoframe can't convey anything but none, 4:3 5090 * and 16:9, so if the user has asked for anything else 5091 * we can only satisfy it by specifying the right VIC. 5092 */ 5093 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { 5094 if (picture_aspect != 5095 drm_get_cea_aspect_ratio(frame->video_code)) 5096 return -EINVAL; 5097 picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5098 } 5099 5100 frame->picture_aspect = picture_aspect; 5101 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 5102 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 5103 5104 return 0; 5105 } 5106 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 5107 5108 /* HDMI Colorspace Spec Definitions */ 5109 #define FULL_COLORIMETRY_MASK 0x1FF 5110 #define NORMAL_COLORIMETRY_MASK 0x3 5111 #define EXTENDED_COLORIMETRY_MASK 0x7 5112 #define EXTENDED_ACE_COLORIMETRY_MASK 0xF 5113 5114 #define C(x) ((x) << 0) 5115 #define EC(x) ((x) << 2) 5116 #define ACE(x) ((x) << 5) 5117 5118 #define HDMI_COLORIMETRY_NO_DATA 0x0 5119 #define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0)) 5120 #define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0)) 5121 #define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0)) 5122 #define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0)) 5123 #define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0)) 5124 #define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0)) 5125 #define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0)) 5126 #define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0)) 5127 #define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0)) 5128 #define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0)) 5129 #define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0)) 5130 #define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1)) 5131 5132 static const u32 hdmi_colorimetry_val[] = { 5133 [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA, 5134 [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC, 5135 [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC, 5136 [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601, 5137 [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709, 5138 [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601, 5139 [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601, 5140 [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB, 5141 [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC, 5142 [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB, 5143 [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC, 5144 }; 5145 5146 #undef C 5147 #undef EC 5148 #undef ACE 5149 5150 /** 5151 * drm_hdmi_avi_infoframe_colorspace() - fill the HDMI AVI infoframe 5152 * colorspace information 5153 * @frame: HDMI AVI infoframe 5154 * @conn_state: connector state 5155 */ 5156 void 5157 drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame, 5158 const struct drm_connector_state *conn_state) 5159 { 5160 u32 colorimetry_val; 5161 u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK; 5162 5163 if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val)) 5164 colorimetry_val = HDMI_COLORIMETRY_NO_DATA; 5165 else 5166 colorimetry_val = hdmi_colorimetry_val[colorimetry_index]; 5167 5168 frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK; 5169 /* 5170 * ToDo: Extend it for ACE formats as well. Modify the infoframe 5171 * structure and extend it in drivers/video/hdmi 5172 */ 5173 frame->extended_colorimetry = (colorimetry_val >> 2) & 5174 EXTENDED_COLORIMETRY_MASK; 5175 } 5176 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace); 5177 5178 /** 5179 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 5180 * quantization range information 5181 * @frame: HDMI AVI infoframe 5182 * @connector: the connector 5183 * @mode: DRM display mode 5184 * @rgb_quant_range: RGB quantization range (Q) 5185 */ 5186 void 5187 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 5188 struct drm_connector *connector, 5189 const struct drm_display_mode *mode, 5190 enum hdmi_quantization_range rgb_quant_range) 5191 { 5192 const struct drm_display_info *info = &connector->display_info; 5193 5194 /* 5195 * CEA-861: 5196 * "A Source shall not send a non-zero Q value that does not correspond 5197 * to the default RGB Quantization Range for the transmitted Picture 5198 * unless the Sink indicates support for the Q bit in a Video 5199 * Capabilities Data Block." 5200 * 5201 * HDMI 2.0 recommends sending non-zero Q when it does match the 5202 * default RGB quantization range for the mode, even when QS=0. 5203 */ 5204 if (info->rgb_quant_range_selectable || 5205 rgb_quant_range == drm_default_rgb_quant_range(mode)) 5206 frame->quantization_range = rgb_quant_range; 5207 else 5208 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 5209 5210 /* 5211 * CEA-861-F: 5212 * "When transmitting any RGB colorimetry, the Source should set the 5213 * YQ-field to match the RGB Quantization Range being transmitted 5214 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 5215 * set YQ=1) and the Sink shall ignore the YQ-field." 5216 * 5217 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused 5218 * by non-zero YQ when receiving RGB. There doesn't seem to be any 5219 * good way to tell which version of CEA-861 the sink supports, so 5220 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based 5221 * on on CEA-861-F. 5222 */ 5223 if (!is_hdmi2_sink(connector) || 5224 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 5225 frame->ycc_quantization_range = 5226 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 5227 else 5228 frame->ycc_quantization_range = 5229 HDMI_YCC_QUANTIZATION_RANGE_FULL; 5230 } 5231 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 5232 5233 static enum hdmi_3d_structure 5234 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 5235 { 5236 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 5237 5238 switch (layout) { 5239 case DRM_MODE_FLAG_3D_FRAME_PACKING: 5240 return HDMI_3D_STRUCTURE_FRAME_PACKING; 5241 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 5242 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 5243 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 5244 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 5245 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 5246 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 5247 case DRM_MODE_FLAG_3D_L_DEPTH: 5248 return HDMI_3D_STRUCTURE_L_DEPTH; 5249 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 5250 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 5251 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 5252 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 5253 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 5254 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 5255 default: 5256 return HDMI_3D_STRUCTURE_INVALID; 5257 } 5258 } 5259 5260 /** 5261 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 5262 * data from a DRM display mode 5263 * @frame: HDMI vendor infoframe 5264 * @connector: the connector 5265 * @mode: DRM display mode 5266 * 5267 * Note that there's is a need to send HDMI vendor infoframes only when using a 5268 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 5269 * function will return -EINVAL, error that can be safely ignored. 5270 * 5271 * Return: 0 on success or a negative error code on failure. 5272 */ 5273 int 5274 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 5275 struct drm_connector *connector, 5276 const struct drm_display_mode *mode) 5277 { 5278 /* 5279 * FIXME: sil-sii8620 doesn't have a connector around when 5280 * we need one, so we have to be prepared for a NULL connector. 5281 */ 5282 bool has_hdmi_infoframe = connector ? 5283 connector->display_info.has_hdmi_infoframe : false; 5284 int err; 5285 u32 s3d_flags; 5286 u8 vic; 5287 5288 if (!frame || !mode) 5289 return -EINVAL; 5290 5291 if (!has_hdmi_infoframe) 5292 return -EINVAL; 5293 5294 vic = drm_match_hdmi_mode(mode); 5295 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; 5296 5297 /* 5298 * Even if it's not absolutely necessary to send the infoframe 5299 * (ie.vic==0 and s3d_struct==0) we will still send it if we 5300 * know that the sink can handle it. This is based on a 5301 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks 5302 * have trouble realizing that they shuld switch from 3D to 2D 5303 * mode if the source simply stops sending the infoframe when 5304 * it wants to switch from 3D to 2D. 5305 */ 5306 5307 if (vic && s3d_flags) 5308 return -EINVAL; 5309 5310 err = hdmi_vendor_infoframe_init(frame); 5311 if (err < 0) 5312 return err; 5313 5314 frame->vic = vic; 5315 frame->s3d_struct = s3d_structure_from_display_mode(mode); 5316 5317 return 0; 5318 } 5319 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 5320 5321 static int drm_parse_tiled_block(struct drm_connector *connector, 5322 struct displayid_block *block) 5323 { 5324 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 5325 u16 w, h; 5326 u8 tile_v_loc, tile_h_loc; 5327 u8 num_v_tile, num_h_tile; 5328 struct drm_tile_group *tg; 5329 5330 w = tile->tile_size[0] | tile->tile_size[1] << 8; 5331 h = tile->tile_size[2] | tile->tile_size[3] << 8; 5332 5333 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 5334 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 5335 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 5336 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 5337 5338 connector->has_tile = true; 5339 if (tile->tile_cap & 0x80) 5340 connector->tile_is_single_monitor = true; 5341 5342 connector->num_h_tile = num_h_tile + 1; 5343 connector->num_v_tile = num_v_tile + 1; 5344 connector->tile_h_loc = tile_h_loc; 5345 connector->tile_v_loc = tile_v_loc; 5346 connector->tile_h_size = w + 1; 5347 connector->tile_v_size = h + 1; 5348 5349 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); 5350 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); 5351 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", 5352 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); 5353 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 5354 5355 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 5356 if (!tg) { 5357 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 5358 } 5359 if (!tg) 5360 return -ENOMEM; 5361 5362 if (connector->tile_group != tg) { 5363 /* if we haven't got a pointer, 5364 take the reference, drop ref to old tile group */ 5365 if (connector->tile_group) { 5366 drm_mode_put_tile_group(connector->dev, connector->tile_group); 5367 } 5368 connector->tile_group = tg; 5369 } else 5370 /* if same tile group, then release the ref we just took. */ 5371 drm_mode_put_tile_group(connector->dev, tg); 5372 return 0; 5373 } 5374 5375 static int drm_parse_display_id(struct drm_connector *connector, 5376 u8 *displayid, int length, 5377 bool is_edid_extension) 5378 { 5379 /* if this is an EDID extension the first byte will be 0x70 */ 5380 int idx = 0; 5381 struct displayid_block *block; 5382 int ret; 5383 5384 if (is_edid_extension) 5385 idx = 1; 5386 5387 ret = validate_displayid(displayid, length, idx); 5388 if (ret) 5389 return ret; 5390 5391 idx += sizeof(struct displayid_hdr); 5392 while (block = (struct displayid_block *)&displayid[idx], 5393 idx + sizeof(struct displayid_block) <= length && 5394 idx + sizeof(struct displayid_block) + block->num_bytes <= length && 5395 block->num_bytes > 0) { 5396 idx += block->num_bytes + sizeof(struct displayid_block); 5397 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n", 5398 block->tag, block->rev, block->num_bytes); 5399 5400 switch (block->tag) { 5401 case DATA_BLOCK_TILED_DISPLAY: 5402 ret = drm_parse_tiled_block(connector, block); 5403 if (ret) 5404 return ret; 5405 break; 5406 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 5407 /* handled in mode gathering code. */ 5408 break; 5409 default: 5410 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag); 5411 break; 5412 } 5413 } 5414 return 0; 5415 } 5416 5417 static void drm_get_displayid(struct drm_connector *connector, 5418 struct edid *edid) 5419 { 5420 void *displayid = NULL; 5421 int ret; 5422 connector->has_tile = false; 5423 displayid = drm_find_displayid_extension(edid); 5424 if (!displayid) { 5425 /* drop reference to any tile group we had */ 5426 goto out_drop_ref; 5427 } 5428 5429 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true); 5430 if (ret < 0) 5431 goto out_drop_ref; 5432 if (!connector->has_tile) 5433 goto out_drop_ref; 5434 return; 5435 out_drop_ref: 5436 if (connector->tile_group) { 5437 drm_mode_put_tile_group(connector->dev, connector->tile_group); 5438 connector->tile_group = NULL; 5439 } 5440 return; 5441 } 5442