1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 31 #include <linux/bitfield.h> 32 #include <linux/byteorder/generic.h> 33 #include <linux/cec.h> 34 #include <linux/export.h> 35 #include <linux/hdmi.h> 36 #include <linux/i2c.h> 37 #include <linux/kernel.h> 38 #include <linux/module.h> 39 #include <linux/pci.h> 40 #include <linux/seq_buf.h> 41 #include <linux/slab.h> 42 #include <linux/vga_switcheroo.h> 43 44 #include <drm/drm_drv.h> 45 #include <drm/drm_edid.h> 46 #include <drm/drm_eld.h> 47 #include <drm/drm_encoder.h> 48 #include <drm/drm_print.h> 49 50 #include "drm_crtc_internal.h" 51 #include "drm_displayid_internal.h" 52 #include "drm_internal.h" 53 54 static int oui(u8 first, u8 second, u8 third) 55 { 56 return (first << 16) | (second << 8) | third; 57 } 58 59 #define EDID_EST_TIMINGS 16 60 #define EDID_STD_TIMINGS 8 61 #define EDID_DETAILED_TIMINGS 4 62 63 /* 64 * EDID blocks out in the wild have a variety of bugs, try to collect 65 * them here (note that userspace may work around broken monitors first, 66 * but fixes should make their way here so that the kernel "just works" 67 * on as many displays as possible). 68 */ 69 70 /* First detailed mode wrong, use largest 60Hz mode */ 71 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 72 /* Reported 135MHz pixel clock is too high, needs adjustment */ 73 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 74 /* Prefer the largest mode at 75 Hz */ 75 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 76 /* Detail timing is in cm not mm */ 77 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 78 /* Detailed timing descriptors have bogus size values, so just take the 79 * maximum size and use that. 80 */ 81 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 82 /* use +hsync +vsync for detailed mode */ 83 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 84 /* Force reduced-blanking timings for detailed modes */ 85 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 86 /* Force 8bpc */ 87 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 88 /* Force 12bpc */ 89 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 90 /* Force 6bpc */ 91 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 92 /* Force 10bpc */ 93 #define EDID_QUIRK_FORCE_10BPC (1 << 11) 94 /* Non desktop display (i.e. HMD) */ 95 #define EDID_QUIRK_NON_DESKTOP (1 << 12) 96 /* Cap the DSC target bitrate to 15bpp */ 97 #define EDID_QUIRK_CAP_DSC_15BPP (1 << 13) 98 99 #define MICROSOFT_IEEE_OUI 0xca125c 100 101 struct detailed_mode_closure { 102 struct drm_connector *connector; 103 const struct drm_edid *drm_edid; 104 bool preferred; 105 int modes; 106 }; 107 108 struct drm_edid_match_closure { 109 const struct drm_edid_ident *ident; 110 bool matched; 111 }; 112 113 #define LEVEL_DMT 0 114 #define LEVEL_GTF 1 115 #define LEVEL_GTF2 2 116 #define LEVEL_CVT 3 117 118 #define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \ 119 { \ 120 .ident = { \ 121 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, \ 122 vend_chr_2, product_id), \ 123 }, \ 124 .quirks = _quirks \ 125 } 126 127 static const struct edid_quirk { 128 const struct drm_edid_ident ident; 129 u32 quirks; 130 } edid_quirk_list[] = { 131 /* Acer AL1706 */ 132 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60), 133 /* Acer F51 */ 134 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60), 135 136 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 137 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC), 138 139 /* BenQ GW2765 */ 140 EDID_QUIRK('B', 'N', 'Q', 0x78d6, EDID_QUIRK_FORCE_8BPC), 141 142 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */ 143 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC), 144 145 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 146 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC), 147 148 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ 149 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC), 150 151 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ 152 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC), 153 154 /* Belinea 10 15 55 */ 155 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60), 156 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60), 157 158 /* Envision Peripherals, Inc. EN-7100e */ 159 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH), 160 /* Envision EN2028 */ 161 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60), 162 163 /* Funai Electronics PM36B */ 164 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 | 165 EDID_QUIRK_DETAILED_IN_CM), 166 167 /* LG 27GP950 */ 168 EDID_QUIRK('G', 'S', 'M', 0x5bbf, EDID_QUIRK_CAP_DSC_15BPP), 169 170 /* LG 27GN950 */ 171 EDID_QUIRK('G', 'S', 'M', 0x5b9a, EDID_QUIRK_CAP_DSC_15BPP), 172 173 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 174 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC), 175 176 /* LG Philips LCD LP154W01-A5 */ 177 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE), 178 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE), 179 180 /* Samsung SyncMaster 205BW. Note: irony */ 181 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP), 182 /* Samsung SyncMaster 22[5-6]BW */ 183 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60), 184 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60), 185 186 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 187 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC), 188 189 /* ViewSonic VA2026w */ 190 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING), 191 192 /* Medion MD 30217 PG */ 193 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75), 194 195 /* Lenovo G50 */ 196 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC), 197 198 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 199 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC), 200 201 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 202 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC), 203 204 /* Valve Index Headset */ 205 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP), 206 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP), 207 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP), 208 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP), 209 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP), 210 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP), 211 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP), 212 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP), 213 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP), 214 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP), 215 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP), 216 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP), 217 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP), 218 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP), 219 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP), 220 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP), 221 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP), 222 223 /* HTC Vive and Vive Pro VR Headsets */ 224 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP), 225 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP), 226 227 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */ 228 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP), 229 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP), 230 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP), 231 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP), 232 233 /* Windows Mixed Reality Headsets */ 234 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP), 235 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP), 236 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP), 237 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP), 238 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP), 239 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP), 240 241 /* Sony PlayStation VR Headset */ 242 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP), 243 244 /* Sensics VR Headsets */ 245 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP), 246 247 /* OSVR HDK and HDK2 VR Headsets */ 248 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP), 249 EDID_QUIRK('A', 'U', 'O', 0x1111, EDID_QUIRK_NON_DESKTOP), 250 }; 251 252 /* 253 * Autogenerated from the DMT spec. 254 * This table is copied from xfree86/modes/xf86EdidModes.c. 255 */ 256 static const struct drm_display_mode drm_dmt_modes[] = { 257 /* 0x01 - 640x350@85Hz */ 258 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 259 736, 832, 0, 350, 382, 385, 445, 0, 260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 261 /* 0x02 - 640x400@85Hz */ 262 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 263 736, 832, 0, 400, 401, 404, 445, 0, 264 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 265 /* 0x03 - 720x400@85Hz */ 266 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 267 828, 936, 0, 400, 401, 404, 446, 0, 268 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 269 /* 0x04 - 640x480@60Hz */ 270 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 271 752, 800, 0, 480, 490, 492, 525, 0, 272 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 273 /* 0x05 - 640x480@72Hz */ 274 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 275 704, 832, 0, 480, 489, 492, 520, 0, 276 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 277 /* 0x06 - 640x480@75Hz */ 278 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 279 720, 840, 0, 480, 481, 484, 500, 0, 280 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 281 /* 0x07 - 640x480@85Hz */ 282 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 283 752, 832, 0, 480, 481, 484, 509, 0, 284 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 285 /* 0x08 - 800x600@56Hz */ 286 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 287 896, 1024, 0, 600, 601, 603, 625, 0, 288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 289 /* 0x09 - 800x600@60Hz */ 290 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 291 968, 1056, 0, 600, 601, 605, 628, 0, 292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 293 /* 0x0a - 800x600@72Hz */ 294 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 295 976, 1040, 0, 600, 637, 643, 666, 0, 296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 297 /* 0x0b - 800x600@75Hz */ 298 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 299 896, 1056, 0, 600, 601, 604, 625, 0, 300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 301 /* 0x0c - 800x600@85Hz */ 302 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 303 896, 1048, 0, 600, 601, 604, 631, 0, 304 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 305 /* 0x0d - 800x600@120Hz RB */ 306 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 307 880, 960, 0, 600, 603, 607, 636, 0, 308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 309 /* 0x0e - 848x480@60Hz */ 310 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 311 976, 1088, 0, 480, 486, 494, 517, 0, 312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 313 /* 0x0f - 1024x768@43Hz, interlace */ 314 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 315 1208, 1264, 0, 768, 768, 776, 817, 0, 316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 317 DRM_MODE_FLAG_INTERLACE) }, 318 /* 0x10 - 1024x768@60Hz */ 319 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 320 1184, 1344, 0, 768, 771, 777, 806, 0, 321 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 322 /* 0x11 - 1024x768@70Hz */ 323 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 324 1184, 1328, 0, 768, 771, 777, 806, 0, 325 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 326 /* 0x12 - 1024x768@75Hz */ 327 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 328 1136, 1312, 0, 768, 769, 772, 800, 0, 329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 330 /* 0x13 - 1024x768@85Hz */ 331 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 332 1168, 1376, 0, 768, 769, 772, 808, 0, 333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 334 /* 0x14 - 1024x768@120Hz RB */ 335 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 336 1104, 1184, 0, 768, 771, 775, 813, 0, 337 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 338 /* 0x15 - 1152x864@75Hz */ 339 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 340 1344, 1600, 0, 864, 865, 868, 900, 0, 341 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 342 /* 0x55 - 1280x720@60Hz */ 343 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 344 1430, 1650, 0, 720, 725, 730, 750, 0, 345 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 346 /* 0x16 - 1280x768@60Hz RB */ 347 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 348 1360, 1440, 0, 768, 771, 778, 790, 0, 349 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 350 /* 0x17 - 1280x768@60Hz */ 351 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 352 1472, 1664, 0, 768, 771, 778, 798, 0, 353 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 354 /* 0x18 - 1280x768@75Hz */ 355 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 356 1488, 1696, 0, 768, 771, 778, 805, 0, 357 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 358 /* 0x19 - 1280x768@85Hz */ 359 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 360 1496, 1712, 0, 768, 771, 778, 809, 0, 361 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 362 /* 0x1a - 1280x768@120Hz RB */ 363 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 364 1360, 1440, 0, 768, 771, 778, 813, 0, 365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 366 /* 0x1b - 1280x800@60Hz RB */ 367 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 368 1360, 1440, 0, 800, 803, 809, 823, 0, 369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 370 /* 0x1c - 1280x800@60Hz */ 371 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 372 1480, 1680, 0, 800, 803, 809, 831, 0, 373 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 374 /* 0x1d - 1280x800@75Hz */ 375 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 376 1488, 1696, 0, 800, 803, 809, 838, 0, 377 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 378 /* 0x1e - 1280x800@85Hz */ 379 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 380 1496, 1712, 0, 800, 803, 809, 843, 0, 381 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 382 /* 0x1f - 1280x800@120Hz RB */ 383 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 384 1360, 1440, 0, 800, 803, 809, 847, 0, 385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 386 /* 0x20 - 1280x960@60Hz */ 387 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 388 1488, 1800, 0, 960, 961, 964, 1000, 0, 389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 390 /* 0x21 - 1280x960@85Hz */ 391 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 392 1504, 1728, 0, 960, 961, 964, 1011, 0, 393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 394 /* 0x22 - 1280x960@120Hz RB */ 395 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 396 1360, 1440, 0, 960, 963, 967, 1017, 0, 397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 398 /* 0x23 - 1280x1024@60Hz */ 399 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 400 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 402 /* 0x24 - 1280x1024@75Hz */ 403 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 404 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 406 /* 0x25 - 1280x1024@85Hz */ 407 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 408 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 409 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 410 /* 0x26 - 1280x1024@120Hz RB */ 411 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 412 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 413 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 414 /* 0x27 - 1360x768@60Hz */ 415 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 416 1536, 1792, 0, 768, 771, 777, 795, 0, 417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 418 /* 0x28 - 1360x768@120Hz RB */ 419 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 420 1440, 1520, 0, 768, 771, 776, 813, 0, 421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 422 /* 0x51 - 1366x768@60Hz */ 423 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 424 1579, 1792, 0, 768, 771, 774, 798, 0, 425 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 426 /* 0x56 - 1366x768@60Hz */ 427 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 428 1436, 1500, 0, 768, 769, 772, 800, 0, 429 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 430 /* 0x29 - 1400x1050@60Hz RB */ 431 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 432 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 433 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 434 /* 0x2a - 1400x1050@60Hz */ 435 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 436 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 437 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 438 /* 0x2b - 1400x1050@75Hz */ 439 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 440 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 441 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 442 /* 0x2c - 1400x1050@85Hz */ 443 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 444 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 445 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 446 /* 0x2d - 1400x1050@120Hz RB */ 447 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 448 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 450 /* 0x2e - 1440x900@60Hz RB */ 451 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 452 1520, 1600, 0, 900, 903, 909, 926, 0, 453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 454 /* 0x2f - 1440x900@60Hz */ 455 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 456 1672, 1904, 0, 900, 903, 909, 934, 0, 457 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 458 /* 0x30 - 1440x900@75Hz */ 459 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 460 1688, 1936, 0, 900, 903, 909, 942, 0, 461 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 462 /* 0x31 - 1440x900@85Hz */ 463 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 464 1696, 1952, 0, 900, 903, 909, 948, 0, 465 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 466 /* 0x32 - 1440x900@120Hz RB */ 467 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 468 1520, 1600, 0, 900, 903, 909, 953, 0, 469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 470 /* 0x53 - 1600x900@60Hz */ 471 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 472 1704, 1800, 0, 900, 901, 904, 1000, 0, 473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 474 /* 0x33 - 1600x1200@60Hz */ 475 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 476 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 478 /* 0x34 - 1600x1200@65Hz */ 479 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 480 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 482 /* 0x35 - 1600x1200@70Hz */ 483 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 484 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 486 /* 0x36 - 1600x1200@75Hz */ 487 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 488 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 489 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 490 /* 0x37 - 1600x1200@85Hz */ 491 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 492 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 494 /* 0x38 - 1600x1200@120Hz RB */ 495 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 496 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 497 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 498 /* 0x39 - 1680x1050@60Hz RB */ 499 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 500 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 501 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 502 /* 0x3a - 1680x1050@60Hz */ 503 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 504 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 505 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 506 /* 0x3b - 1680x1050@75Hz */ 507 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 508 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 509 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 510 /* 0x3c - 1680x1050@85Hz */ 511 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 512 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 513 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 514 /* 0x3d - 1680x1050@120Hz RB */ 515 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 516 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 518 /* 0x3e - 1792x1344@60Hz */ 519 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 520 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 521 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 522 /* 0x3f - 1792x1344@75Hz */ 523 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 524 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 525 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 526 /* 0x40 - 1792x1344@120Hz RB */ 527 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 528 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 529 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 530 /* 0x41 - 1856x1392@60Hz */ 531 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 532 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 533 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 534 /* 0x42 - 1856x1392@75Hz */ 535 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 536 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 538 /* 0x43 - 1856x1392@120Hz RB */ 539 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 540 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 541 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 542 /* 0x52 - 1920x1080@60Hz */ 543 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 544 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 545 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 546 /* 0x44 - 1920x1200@60Hz RB */ 547 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 548 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 549 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 550 /* 0x45 - 1920x1200@60Hz */ 551 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 552 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 553 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 554 /* 0x46 - 1920x1200@75Hz */ 555 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 556 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 557 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 558 /* 0x47 - 1920x1200@85Hz */ 559 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 560 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 561 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 562 /* 0x48 - 1920x1200@120Hz RB */ 563 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 564 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 566 /* 0x49 - 1920x1440@60Hz */ 567 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 568 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 569 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 570 /* 0x4a - 1920x1440@75Hz */ 571 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 572 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 573 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 574 /* 0x4b - 1920x1440@120Hz RB */ 575 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 576 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 577 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 578 /* 0x54 - 2048x1152@60Hz */ 579 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 580 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 581 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 582 /* 0x4c - 2560x1600@60Hz RB */ 583 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 584 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 585 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 586 /* 0x4d - 2560x1600@60Hz */ 587 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 588 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 589 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 590 /* 0x4e - 2560x1600@75Hz */ 591 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 592 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 593 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 594 /* 0x4f - 2560x1600@85Hz */ 595 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 596 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 597 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 598 /* 0x50 - 2560x1600@120Hz RB */ 599 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 600 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 601 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 602 /* 0x57 - 4096x2160@60Hz RB */ 603 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 604 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 605 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 606 /* 0x58 - 4096x2160@59.94Hz RB */ 607 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 608 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 609 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 610 }; 611 612 /* 613 * These more or less come from the DMT spec. The 720x400 modes are 614 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 615 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 616 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 617 * mode. 618 * 619 * The DMT modes have been fact-checked; the rest are mild guesses. 620 */ 621 static const struct drm_display_mode edid_est_modes[] = { 622 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 623 968, 1056, 0, 600, 601, 605, 628, 0, 624 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 625 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 626 896, 1024, 0, 600, 601, 603, 625, 0, 627 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 628 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 629 720, 840, 0, 480, 481, 484, 500, 0, 630 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 631 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 632 704, 832, 0, 480, 489, 492, 520, 0, 633 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 634 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 635 768, 864, 0, 480, 483, 486, 525, 0, 636 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 637 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 638 752, 800, 0, 480, 490, 492, 525, 0, 639 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 640 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 641 846, 900, 0, 400, 421, 423, 449, 0, 642 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 643 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 644 846, 900, 0, 400, 412, 414, 449, 0, 645 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 646 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 647 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 648 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 649 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 650 1136, 1312, 0, 768, 769, 772, 800, 0, 651 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 652 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 653 1184, 1328, 0, 768, 771, 777, 806, 0, 654 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 655 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 656 1184, 1344, 0, 768, 771, 777, 806, 0, 657 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 658 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 659 1208, 1264, 0, 768, 768, 776, 817, 0, 660 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 661 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 662 928, 1152, 0, 624, 625, 628, 667, 0, 663 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 664 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 665 896, 1056, 0, 600, 601, 604, 625, 0, 666 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 667 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 668 976, 1040, 0, 600, 637, 643, 666, 0, 669 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 670 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 671 1344, 1600, 0, 864, 865, 868, 900, 0, 672 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 673 }; 674 675 struct minimode { 676 short w; 677 short h; 678 short r; 679 short rb; 680 }; 681 682 static const struct minimode est3_modes[] = { 683 /* byte 6 */ 684 { 640, 350, 85, 0 }, 685 { 640, 400, 85, 0 }, 686 { 720, 400, 85, 0 }, 687 { 640, 480, 85, 0 }, 688 { 848, 480, 60, 0 }, 689 { 800, 600, 85, 0 }, 690 { 1024, 768, 85, 0 }, 691 { 1152, 864, 75, 0 }, 692 /* byte 7 */ 693 { 1280, 768, 60, 1 }, 694 { 1280, 768, 60, 0 }, 695 { 1280, 768, 75, 0 }, 696 { 1280, 768, 85, 0 }, 697 { 1280, 960, 60, 0 }, 698 { 1280, 960, 85, 0 }, 699 { 1280, 1024, 60, 0 }, 700 { 1280, 1024, 85, 0 }, 701 /* byte 8 */ 702 { 1360, 768, 60, 0 }, 703 { 1440, 900, 60, 1 }, 704 { 1440, 900, 60, 0 }, 705 { 1440, 900, 75, 0 }, 706 { 1440, 900, 85, 0 }, 707 { 1400, 1050, 60, 1 }, 708 { 1400, 1050, 60, 0 }, 709 { 1400, 1050, 75, 0 }, 710 /* byte 9 */ 711 { 1400, 1050, 85, 0 }, 712 { 1680, 1050, 60, 1 }, 713 { 1680, 1050, 60, 0 }, 714 { 1680, 1050, 75, 0 }, 715 { 1680, 1050, 85, 0 }, 716 { 1600, 1200, 60, 0 }, 717 { 1600, 1200, 65, 0 }, 718 { 1600, 1200, 70, 0 }, 719 /* byte 10 */ 720 { 1600, 1200, 75, 0 }, 721 { 1600, 1200, 85, 0 }, 722 { 1792, 1344, 60, 0 }, 723 { 1792, 1344, 75, 0 }, 724 { 1856, 1392, 60, 0 }, 725 { 1856, 1392, 75, 0 }, 726 { 1920, 1200, 60, 1 }, 727 { 1920, 1200, 60, 0 }, 728 /* byte 11 */ 729 { 1920, 1200, 75, 0 }, 730 { 1920, 1200, 85, 0 }, 731 { 1920, 1440, 60, 0 }, 732 { 1920, 1440, 75, 0 }, 733 }; 734 735 static const struct minimode extra_modes[] = { 736 { 1024, 576, 60, 0 }, 737 { 1366, 768, 60, 0 }, 738 { 1600, 900, 60, 0 }, 739 { 1680, 945, 60, 0 }, 740 { 1920, 1080, 60, 0 }, 741 { 2048, 1152, 60, 0 }, 742 { 2048, 1536, 60, 0 }, 743 }; 744 745 /* 746 * From CEA/CTA-861 spec. 747 * 748 * Do not access directly, instead always use cea_mode_for_vic(). 749 */ 750 static const struct drm_display_mode edid_cea_modes_1[] = { 751 /* 1 - 640x480@60Hz 4:3 */ 752 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 753 752, 800, 0, 480, 490, 492, 525, 0, 754 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 755 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 756 /* 2 - 720x480@60Hz 4:3 */ 757 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 758 798, 858, 0, 480, 489, 495, 525, 0, 759 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 760 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 761 /* 3 - 720x480@60Hz 16:9 */ 762 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 763 798, 858, 0, 480, 489, 495, 525, 0, 764 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 765 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 766 /* 4 - 1280x720@60Hz 16:9 */ 767 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 768 1430, 1650, 0, 720, 725, 730, 750, 0, 769 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 770 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 771 /* 5 - 1920x1080i@60Hz 16:9 */ 772 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 773 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 774 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 775 DRM_MODE_FLAG_INTERLACE), 776 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 777 /* 6 - 720(1440)x480i@60Hz 4:3 */ 778 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 779 801, 858, 0, 480, 488, 494, 525, 0, 780 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 781 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 782 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 783 /* 7 - 720(1440)x480i@60Hz 16:9 */ 784 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 785 801, 858, 0, 480, 488, 494, 525, 0, 786 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 787 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 788 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 789 /* 8 - 720(1440)x240@60Hz 4:3 */ 790 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 791 801, 858, 0, 240, 244, 247, 262, 0, 792 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 793 DRM_MODE_FLAG_DBLCLK), 794 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 795 /* 9 - 720(1440)x240@60Hz 16:9 */ 796 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 797 801, 858, 0, 240, 244, 247, 262, 0, 798 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 799 DRM_MODE_FLAG_DBLCLK), 800 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 801 /* 10 - 2880x480i@60Hz 4:3 */ 802 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 803 3204, 3432, 0, 480, 488, 494, 525, 0, 804 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 805 DRM_MODE_FLAG_INTERLACE), 806 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 807 /* 11 - 2880x480i@60Hz 16:9 */ 808 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 809 3204, 3432, 0, 480, 488, 494, 525, 0, 810 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 811 DRM_MODE_FLAG_INTERLACE), 812 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 813 /* 12 - 2880x240@60Hz 4:3 */ 814 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 815 3204, 3432, 0, 240, 244, 247, 262, 0, 816 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 817 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 818 /* 13 - 2880x240@60Hz 16:9 */ 819 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 820 3204, 3432, 0, 240, 244, 247, 262, 0, 821 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 822 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 823 /* 14 - 1440x480@60Hz 4:3 */ 824 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 825 1596, 1716, 0, 480, 489, 495, 525, 0, 826 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 827 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 828 /* 15 - 1440x480@60Hz 16:9 */ 829 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 830 1596, 1716, 0, 480, 489, 495, 525, 0, 831 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 832 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 833 /* 16 - 1920x1080@60Hz 16:9 */ 834 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 835 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 836 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 837 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 838 /* 17 - 720x576@50Hz 4:3 */ 839 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 840 796, 864, 0, 576, 581, 586, 625, 0, 841 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 842 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 843 /* 18 - 720x576@50Hz 16:9 */ 844 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 845 796, 864, 0, 576, 581, 586, 625, 0, 846 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 847 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 848 /* 19 - 1280x720@50Hz 16:9 */ 849 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 850 1760, 1980, 0, 720, 725, 730, 750, 0, 851 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 852 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 853 /* 20 - 1920x1080i@50Hz 16:9 */ 854 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 855 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 856 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 857 DRM_MODE_FLAG_INTERLACE), 858 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 859 /* 21 - 720(1440)x576i@50Hz 4:3 */ 860 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 861 795, 864, 0, 576, 580, 586, 625, 0, 862 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 863 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 864 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 865 /* 22 - 720(1440)x576i@50Hz 16:9 */ 866 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 867 795, 864, 0, 576, 580, 586, 625, 0, 868 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 869 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 870 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 871 /* 23 - 720(1440)x288@50Hz 4:3 */ 872 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 873 795, 864, 0, 288, 290, 293, 312, 0, 874 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 875 DRM_MODE_FLAG_DBLCLK), 876 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 877 /* 24 - 720(1440)x288@50Hz 16:9 */ 878 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 879 795, 864, 0, 288, 290, 293, 312, 0, 880 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 881 DRM_MODE_FLAG_DBLCLK), 882 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 883 /* 25 - 2880x576i@50Hz 4:3 */ 884 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 885 3180, 3456, 0, 576, 580, 586, 625, 0, 886 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 887 DRM_MODE_FLAG_INTERLACE), 888 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 889 /* 26 - 2880x576i@50Hz 16:9 */ 890 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 891 3180, 3456, 0, 576, 580, 586, 625, 0, 892 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 893 DRM_MODE_FLAG_INTERLACE), 894 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 895 /* 27 - 2880x288@50Hz 4:3 */ 896 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 897 3180, 3456, 0, 288, 290, 293, 312, 0, 898 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 899 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 900 /* 28 - 2880x288@50Hz 16:9 */ 901 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 902 3180, 3456, 0, 288, 290, 293, 312, 0, 903 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 904 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 905 /* 29 - 1440x576@50Hz 4:3 */ 906 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 907 1592, 1728, 0, 576, 581, 586, 625, 0, 908 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 909 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 910 /* 30 - 1440x576@50Hz 16:9 */ 911 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 912 1592, 1728, 0, 576, 581, 586, 625, 0, 913 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 914 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 915 /* 31 - 1920x1080@50Hz 16:9 */ 916 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 917 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 918 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 919 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 920 /* 32 - 1920x1080@24Hz 16:9 */ 921 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 922 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 923 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 924 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 925 /* 33 - 1920x1080@25Hz 16:9 */ 926 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 927 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 928 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 929 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 930 /* 34 - 1920x1080@30Hz 16:9 */ 931 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 932 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 933 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 934 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 935 /* 35 - 2880x480@60Hz 4:3 */ 936 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 937 3192, 3432, 0, 480, 489, 495, 525, 0, 938 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 939 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 940 /* 36 - 2880x480@60Hz 16:9 */ 941 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 942 3192, 3432, 0, 480, 489, 495, 525, 0, 943 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 944 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 945 /* 37 - 2880x576@50Hz 4:3 */ 946 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 947 3184, 3456, 0, 576, 581, 586, 625, 0, 948 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 949 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 950 /* 38 - 2880x576@50Hz 16:9 */ 951 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 952 3184, 3456, 0, 576, 581, 586, 625, 0, 953 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 954 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 955 /* 39 - 1920x1080i@50Hz 16:9 */ 956 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 957 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 958 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 959 DRM_MODE_FLAG_INTERLACE), 960 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 961 /* 40 - 1920x1080i@100Hz 16:9 */ 962 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 963 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 964 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 965 DRM_MODE_FLAG_INTERLACE), 966 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 967 /* 41 - 1280x720@100Hz 16:9 */ 968 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 969 1760, 1980, 0, 720, 725, 730, 750, 0, 970 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 971 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 972 /* 42 - 720x576@100Hz 4:3 */ 973 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 974 796, 864, 0, 576, 581, 586, 625, 0, 975 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 976 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 977 /* 43 - 720x576@100Hz 16:9 */ 978 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 979 796, 864, 0, 576, 581, 586, 625, 0, 980 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 981 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 982 /* 44 - 720(1440)x576i@100Hz 4:3 */ 983 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 984 795, 864, 0, 576, 580, 586, 625, 0, 985 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 986 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 987 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 988 /* 45 - 720(1440)x576i@100Hz 16:9 */ 989 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 990 795, 864, 0, 576, 580, 586, 625, 0, 991 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 992 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 993 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 994 /* 46 - 1920x1080i@120Hz 16:9 */ 995 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 996 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 997 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 998 DRM_MODE_FLAG_INTERLACE), 999 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1000 /* 47 - 1280x720@120Hz 16:9 */ 1001 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1002 1430, 1650, 0, 720, 725, 730, 750, 0, 1003 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1004 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1005 /* 48 - 720x480@120Hz 4:3 */ 1006 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 1007 798, 858, 0, 480, 489, 495, 525, 0, 1008 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1009 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1010 /* 49 - 720x480@120Hz 16:9 */ 1011 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 1012 798, 858, 0, 480, 489, 495, 525, 0, 1013 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1014 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1015 /* 50 - 720(1440)x480i@120Hz 4:3 */ 1016 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 1017 801, 858, 0, 480, 488, 494, 525, 0, 1018 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1019 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1020 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1021 /* 51 - 720(1440)x480i@120Hz 16:9 */ 1022 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 1023 801, 858, 0, 480, 488, 494, 525, 0, 1024 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1025 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1026 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1027 /* 52 - 720x576@200Hz 4:3 */ 1028 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1029 796, 864, 0, 576, 581, 586, 625, 0, 1030 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1031 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1032 /* 53 - 720x576@200Hz 16:9 */ 1033 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1034 796, 864, 0, 576, 581, 586, 625, 0, 1035 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1036 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1037 /* 54 - 720(1440)x576i@200Hz 4:3 */ 1038 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1039 795, 864, 0, 576, 580, 586, 625, 0, 1040 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1041 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1042 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1043 /* 55 - 720(1440)x576i@200Hz 16:9 */ 1044 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1045 795, 864, 0, 576, 580, 586, 625, 0, 1046 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1047 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1048 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1049 /* 56 - 720x480@240Hz 4:3 */ 1050 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1051 798, 858, 0, 480, 489, 495, 525, 0, 1052 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1053 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1054 /* 57 - 720x480@240Hz 16:9 */ 1055 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1056 798, 858, 0, 480, 489, 495, 525, 0, 1057 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1058 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1059 /* 58 - 720(1440)x480i@240Hz 4:3 */ 1060 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1061 801, 858, 0, 480, 488, 494, 525, 0, 1062 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1063 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1064 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1065 /* 59 - 720(1440)x480i@240Hz 16:9 */ 1066 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1067 801, 858, 0, 480, 488, 494, 525, 0, 1068 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1069 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1070 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1071 /* 60 - 1280x720@24Hz 16:9 */ 1072 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1073 3080, 3300, 0, 720, 725, 730, 750, 0, 1074 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1075 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1076 /* 61 - 1280x720@25Hz 16:9 */ 1077 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1078 3740, 3960, 0, 720, 725, 730, 750, 0, 1079 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1080 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1081 /* 62 - 1280x720@30Hz 16:9 */ 1082 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1083 3080, 3300, 0, 720, 725, 730, 750, 0, 1084 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1085 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1086 /* 63 - 1920x1080@120Hz 16:9 */ 1087 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1088 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1089 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1090 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1091 /* 64 - 1920x1080@100Hz 16:9 */ 1092 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1093 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1094 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1095 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1096 /* 65 - 1280x720@24Hz 64:27 */ 1097 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1098 3080, 3300, 0, 720, 725, 730, 750, 0, 1099 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1100 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1101 /* 66 - 1280x720@25Hz 64:27 */ 1102 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1103 3740, 3960, 0, 720, 725, 730, 750, 0, 1104 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1105 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1106 /* 67 - 1280x720@30Hz 64:27 */ 1107 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1108 3080, 3300, 0, 720, 725, 730, 750, 0, 1109 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1110 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1111 /* 68 - 1280x720@50Hz 64:27 */ 1112 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1113 1760, 1980, 0, 720, 725, 730, 750, 0, 1114 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1115 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1116 /* 69 - 1280x720@60Hz 64:27 */ 1117 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1118 1430, 1650, 0, 720, 725, 730, 750, 0, 1119 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1120 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1121 /* 70 - 1280x720@100Hz 64:27 */ 1122 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1123 1760, 1980, 0, 720, 725, 730, 750, 0, 1124 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1125 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1126 /* 71 - 1280x720@120Hz 64:27 */ 1127 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1128 1430, 1650, 0, 720, 725, 730, 750, 0, 1129 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1130 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1131 /* 72 - 1920x1080@24Hz 64:27 */ 1132 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1133 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1134 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1135 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1136 /* 73 - 1920x1080@25Hz 64:27 */ 1137 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1138 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1139 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1140 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1141 /* 74 - 1920x1080@30Hz 64:27 */ 1142 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1143 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1144 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1145 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1146 /* 75 - 1920x1080@50Hz 64:27 */ 1147 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1148 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1149 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1150 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1151 /* 76 - 1920x1080@60Hz 64:27 */ 1152 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1153 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1154 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1155 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1156 /* 77 - 1920x1080@100Hz 64:27 */ 1157 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1158 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1159 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1160 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1161 /* 78 - 1920x1080@120Hz 64:27 */ 1162 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1163 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1164 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1165 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1166 /* 79 - 1680x720@24Hz 64:27 */ 1167 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 1168 3080, 3300, 0, 720, 725, 730, 750, 0, 1169 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1170 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1171 /* 80 - 1680x720@25Hz 64:27 */ 1172 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 1173 2948, 3168, 0, 720, 725, 730, 750, 0, 1174 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1175 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1176 /* 81 - 1680x720@30Hz 64:27 */ 1177 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 1178 2420, 2640, 0, 720, 725, 730, 750, 0, 1179 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1180 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1181 /* 82 - 1680x720@50Hz 64:27 */ 1182 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1183 1980, 2200, 0, 720, 725, 730, 750, 0, 1184 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1185 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1186 /* 83 - 1680x720@60Hz 64:27 */ 1187 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1188 1980, 2200, 0, 720, 725, 730, 750, 0, 1189 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1190 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1191 /* 84 - 1680x720@100Hz 64:27 */ 1192 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1193 1780, 2000, 0, 720, 725, 730, 825, 0, 1194 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1195 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1196 /* 85 - 1680x720@120Hz 64:27 */ 1197 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1198 1780, 2000, 0, 720, 725, 730, 825, 0, 1199 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1200 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1201 /* 86 - 2560x1080@24Hz 64:27 */ 1202 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 1203 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1204 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1205 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1206 /* 87 - 2560x1080@25Hz 64:27 */ 1207 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 1208 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, 1209 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1210 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1211 /* 88 - 2560x1080@30Hz 64:27 */ 1212 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 1213 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, 1214 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1215 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1216 /* 89 - 2560x1080@50Hz 64:27 */ 1217 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 1218 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, 1219 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1220 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1221 /* 90 - 2560x1080@60Hz 64:27 */ 1222 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 1223 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, 1224 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1225 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1226 /* 91 - 2560x1080@100Hz 64:27 */ 1227 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 1228 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, 1229 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1230 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1231 /* 92 - 2560x1080@120Hz 64:27 */ 1232 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 1233 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, 1234 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1235 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1236 /* 93 - 3840x2160@24Hz 16:9 */ 1237 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1238 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1239 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1240 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1241 /* 94 - 3840x2160@25Hz 16:9 */ 1242 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1243 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1245 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1246 /* 95 - 3840x2160@30Hz 16:9 */ 1247 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1248 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1249 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1250 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1251 /* 96 - 3840x2160@50Hz 16:9 */ 1252 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1253 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1254 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1255 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1256 /* 97 - 3840x2160@60Hz 16:9 */ 1257 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1258 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1260 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1261 /* 98 - 4096x2160@24Hz 256:135 */ 1262 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1263 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1265 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1266 /* 99 - 4096x2160@25Hz 256:135 */ 1267 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1268 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1269 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1270 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1271 /* 100 - 4096x2160@30Hz 256:135 */ 1272 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1273 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1274 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1275 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1276 /* 101 - 4096x2160@50Hz 256:135 */ 1277 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1278 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1280 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1281 /* 102 - 4096x2160@60Hz 256:135 */ 1282 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1283 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1285 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1286 /* 103 - 3840x2160@24Hz 64:27 */ 1287 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1288 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1289 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1290 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1291 /* 104 - 3840x2160@25Hz 64:27 */ 1292 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1293 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1294 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1295 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1296 /* 105 - 3840x2160@30Hz 64:27 */ 1297 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1298 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1300 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1301 /* 106 - 3840x2160@50Hz 64:27 */ 1302 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1303 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1304 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1305 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1306 /* 107 - 3840x2160@60Hz 64:27 */ 1307 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1308 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1310 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1311 /* 108 - 1280x720@48Hz 16:9 */ 1312 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1313 2280, 2500, 0, 720, 725, 730, 750, 0, 1314 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1315 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1316 /* 109 - 1280x720@48Hz 64:27 */ 1317 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1318 2280, 2500, 0, 720, 725, 730, 750, 0, 1319 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1320 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1321 /* 110 - 1680x720@48Hz 64:27 */ 1322 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490, 1323 2530, 2750, 0, 720, 725, 730, 750, 0, 1324 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1325 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1326 /* 111 - 1920x1080@48Hz 16:9 */ 1327 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1328 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1330 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1331 /* 112 - 1920x1080@48Hz 64:27 */ 1332 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1333 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1334 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1335 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1336 /* 113 - 2560x1080@48Hz 64:27 */ 1337 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558, 1338 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1339 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1340 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1341 /* 114 - 3840x2160@48Hz 16:9 */ 1342 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1343 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1344 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1345 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1346 /* 115 - 4096x2160@48Hz 256:135 */ 1347 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116, 1348 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1349 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1350 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1351 /* 116 - 3840x2160@48Hz 64:27 */ 1352 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1353 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1354 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1355 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1356 /* 117 - 3840x2160@100Hz 16:9 */ 1357 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1358 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1359 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1360 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1361 /* 118 - 3840x2160@120Hz 16:9 */ 1362 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1363 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1364 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1365 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1366 /* 119 - 3840x2160@100Hz 64:27 */ 1367 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1368 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1370 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1371 /* 120 - 3840x2160@120Hz 64:27 */ 1372 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1373 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1374 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1375 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1376 /* 121 - 5120x2160@24Hz 64:27 */ 1377 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116, 1378 7204, 7500, 0, 2160, 2168, 2178, 2200, 0, 1379 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1380 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1381 /* 122 - 5120x2160@25Hz 64:27 */ 1382 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816, 1383 6904, 7200, 0, 2160, 2168, 2178, 2200, 0, 1384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1385 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1386 /* 123 - 5120x2160@30Hz 64:27 */ 1387 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784, 1388 5872, 6000, 0, 2160, 2168, 2178, 2200, 0, 1389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1390 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1391 /* 124 - 5120x2160@48Hz 64:27 */ 1392 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866, 1393 5954, 6250, 0, 2160, 2168, 2178, 2475, 0, 1394 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1395 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1396 /* 125 - 5120x2160@50Hz 64:27 */ 1397 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216, 1398 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1399 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1400 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1401 /* 126 - 5120x2160@60Hz 64:27 */ 1402 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284, 1403 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1404 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1405 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1406 /* 127 - 5120x2160@100Hz 64:27 */ 1407 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216, 1408 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1409 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1410 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1411 }; 1412 1413 /* 1414 * From CEA/CTA-861 spec. 1415 * 1416 * Do not access directly, instead always use cea_mode_for_vic(). 1417 */ 1418 static const struct drm_display_mode edid_cea_modes_193[] = { 1419 /* 193 - 5120x2160@120Hz 64:27 */ 1420 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284, 1421 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1422 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1423 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1424 /* 194 - 7680x4320@24Hz 16:9 */ 1425 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1426 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1427 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1428 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1429 /* 195 - 7680x4320@25Hz 16:9 */ 1430 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1431 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1432 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1433 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1434 /* 196 - 7680x4320@30Hz 16:9 */ 1435 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1436 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1438 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1439 /* 197 - 7680x4320@48Hz 16:9 */ 1440 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1441 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1442 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1443 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1444 /* 198 - 7680x4320@50Hz 16:9 */ 1445 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1446 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1447 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1448 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1449 /* 199 - 7680x4320@60Hz 16:9 */ 1450 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1451 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1452 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1453 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1454 /* 200 - 7680x4320@100Hz 16:9 */ 1455 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1456 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1458 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1459 /* 201 - 7680x4320@120Hz 16:9 */ 1460 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1461 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1462 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1463 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1464 /* 202 - 7680x4320@24Hz 64:27 */ 1465 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1466 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1467 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1468 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1469 /* 203 - 7680x4320@25Hz 64:27 */ 1470 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1471 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1472 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1473 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1474 /* 204 - 7680x4320@30Hz 64:27 */ 1475 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1476 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1478 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1479 /* 205 - 7680x4320@48Hz 64:27 */ 1480 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1481 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1482 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1483 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1484 /* 206 - 7680x4320@50Hz 64:27 */ 1485 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1486 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1487 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1488 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1489 /* 207 - 7680x4320@60Hz 64:27 */ 1490 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1491 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1492 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1493 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1494 /* 208 - 7680x4320@100Hz 64:27 */ 1495 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1496 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1497 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1498 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1499 /* 209 - 7680x4320@120Hz 64:27 */ 1500 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1501 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1502 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1503 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1504 /* 210 - 10240x4320@24Hz 64:27 */ 1505 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732, 1506 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1507 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1508 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1509 /* 211 - 10240x4320@25Hz 64:27 */ 1510 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732, 1511 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1512 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1513 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1514 /* 212 - 10240x4320@30Hz 64:27 */ 1515 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528, 1516 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1518 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1519 /* 213 - 10240x4320@48Hz 64:27 */ 1520 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732, 1521 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1522 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1523 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1524 /* 214 - 10240x4320@50Hz 64:27 */ 1525 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732, 1526 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1527 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1528 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1529 /* 215 - 10240x4320@60Hz 64:27 */ 1530 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528, 1531 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1532 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1533 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1534 /* 216 - 10240x4320@100Hz 64:27 */ 1535 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432, 1536 12608, 13200, 0, 4320, 4336, 4356, 4500, 0, 1537 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1538 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1539 /* 217 - 10240x4320@120Hz 64:27 */ 1540 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528, 1541 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1542 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1543 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1544 /* 218 - 4096x2160@100Hz 256:135 */ 1545 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896, 1546 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1547 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1548 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1549 /* 219 - 4096x2160@120Hz 256:135 */ 1550 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184, 1551 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1553 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1554 }; 1555 1556 /* 1557 * HDMI 1.4 4k modes. Index using the VIC. 1558 */ 1559 static const struct drm_display_mode edid_4k_modes[] = { 1560 /* 0 - dummy, VICs start at 1 */ 1561 { }, 1562 /* 1 - 3840x2160@30Hz */ 1563 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1564 3840, 4016, 4104, 4400, 0, 1565 2160, 2168, 2178, 2250, 0, 1566 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1567 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1568 /* 2 - 3840x2160@25Hz */ 1569 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1570 3840, 4896, 4984, 5280, 0, 1571 2160, 2168, 2178, 2250, 0, 1572 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1573 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1574 /* 3 - 3840x2160@24Hz */ 1575 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1576 3840, 5116, 5204, 5500, 0, 1577 2160, 2168, 2178, 2250, 0, 1578 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1579 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1580 /* 4 - 4096x2160@24Hz (SMPTE) */ 1581 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1582 4096, 5116, 5204, 5500, 0, 1583 2160, 2168, 2178, 2250, 0, 1584 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1585 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1586 }; 1587 1588 /*** DDC fetch and block validation ***/ 1589 1590 /* 1591 * The opaque EDID type, internal to drm_edid.c. 1592 */ 1593 struct drm_edid { 1594 /* Size allocated for edid */ 1595 size_t size; 1596 const struct edid *edid; 1597 }; 1598 1599 static int edid_hfeeodb_extension_block_count(const struct edid *edid); 1600 1601 static int edid_hfeeodb_block_count(const struct edid *edid) 1602 { 1603 int eeodb = edid_hfeeodb_extension_block_count(edid); 1604 1605 return eeodb ? eeodb + 1 : 0; 1606 } 1607 1608 static int edid_extension_block_count(const struct edid *edid) 1609 { 1610 return edid->extensions; 1611 } 1612 1613 static int edid_block_count(const struct edid *edid) 1614 { 1615 return edid_extension_block_count(edid) + 1; 1616 } 1617 1618 static int edid_size_by_blocks(int num_blocks) 1619 { 1620 return num_blocks * EDID_LENGTH; 1621 } 1622 1623 static int edid_size(const struct edid *edid) 1624 { 1625 return edid_size_by_blocks(edid_block_count(edid)); 1626 } 1627 1628 static const void *edid_block_data(const struct edid *edid, int index) 1629 { 1630 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH); 1631 1632 return edid + index; 1633 } 1634 1635 static const void *edid_extension_block_data(const struct edid *edid, int index) 1636 { 1637 return edid_block_data(edid, index + 1); 1638 } 1639 1640 /* EDID block count indicated in EDID, may exceed allocated size */ 1641 static int __drm_edid_block_count(const struct drm_edid *drm_edid) 1642 { 1643 int num_blocks; 1644 1645 /* Starting point */ 1646 num_blocks = edid_block_count(drm_edid->edid); 1647 1648 /* HF-EEODB override */ 1649 if (drm_edid->size >= edid_size_by_blocks(2)) { 1650 int eeodb; 1651 1652 /* 1653 * Note: HF-EEODB may specify a smaller extension count than the 1654 * regular one. Unlike in buffer allocation, here we can use it. 1655 */ 1656 eeodb = edid_hfeeodb_block_count(drm_edid->edid); 1657 if (eeodb) 1658 num_blocks = eeodb; 1659 } 1660 1661 return num_blocks; 1662 } 1663 1664 /* EDID block count, limited by allocated size */ 1665 static int drm_edid_block_count(const struct drm_edid *drm_edid) 1666 { 1667 /* Limit by allocated size */ 1668 return min(__drm_edid_block_count(drm_edid), 1669 (int)drm_edid->size / EDID_LENGTH); 1670 } 1671 1672 /* EDID extension block count, limited by allocated size */ 1673 static int drm_edid_extension_block_count(const struct drm_edid *drm_edid) 1674 { 1675 return drm_edid_block_count(drm_edid) - 1; 1676 } 1677 1678 static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index) 1679 { 1680 return edid_block_data(drm_edid->edid, index); 1681 } 1682 1683 static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid, 1684 int index) 1685 { 1686 return edid_extension_block_data(drm_edid->edid, index); 1687 } 1688 1689 /* 1690 * Initializer helper for legacy interfaces, where we have no choice but to 1691 * trust edid size. Not for general purpose use. 1692 */ 1693 static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid, 1694 const struct edid *edid) 1695 { 1696 if (!edid) 1697 return NULL; 1698 1699 memset(drm_edid, 0, sizeof(*drm_edid)); 1700 1701 drm_edid->edid = edid; 1702 drm_edid->size = edid_size(edid); 1703 1704 return drm_edid; 1705 } 1706 1707 /* 1708 * EDID base and extension block iterator. 1709 * 1710 * struct drm_edid_iter iter; 1711 * const u8 *block; 1712 * 1713 * drm_edid_iter_begin(drm_edid, &iter); 1714 * drm_edid_iter_for_each(block, &iter) { 1715 * // do stuff with block 1716 * } 1717 * drm_edid_iter_end(&iter); 1718 */ 1719 struct drm_edid_iter { 1720 const struct drm_edid *drm_edid; 1721 1722 /* Current block index. */ 1723 int index; 1724 }; 1725 1726 static void drm_edid_iter_begin(const struct drm_edid *drm_edid, 1727 struct drm_edid_iter *iter) 1728 { 1729 memset(iter, 0, sizeof(*iter)); 1730 1731 iter->drm_edid = drm_edid; 1732 } 1733 1734 static const void *__drm_edid_iter_next(struct drm_edid_iter *iter) 1735 { 1736 const void *block = NULL; 1737 1738 if (!iter->drm_edid) 1739 return NULL; 1740 1741 if (iter->index < drm_edid_block_count(iter->drm_edid)) 1742 block = drm_edid_block_data(iter->drm_edid, iter->index++); 1743 1744 return block; 1745 } 1746 1747 #define drm_edid_iter_for_each(__block, __iter) \ 1748 while (((__block) = __drm_edid_iter_next(__iter))) 1749 1750 static void drm_edid_iter_end(struct drm_edid_iter *iter) 1751 { 1752 memset(iter, 0, sizeof(*iter)); 1753 } 1754 1755 static const u8 edid_header[] = { 1756 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1757 }; 1758 1759 static void edid_header_fix(void *edid) 1760 { 1761 memcpy(edid, edid_header, sizeof(edid_header)); 1762 } 1763 1764 /** 1765 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1766 * @_edid: pointer to raw base EDID block 1767 * 1768 * Sanity check the header of the base EDID block. 1769 * 1770 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1771 */ 1772 int drm_edid_header_is_valid(const void *_edid) 1773 { 1774 const struct edid *edid = _edid; 1775 int i, score = 0; 1776 1777 for (i = 0; i < sizeof(edid_header); i++) { 1778 if (edid->header[i] == edid_header[i]) 1779 score++; 1780 } 1781 1782 return score; 1783 } 1784 EXPORT_SYMBOL(drm_edid_header_is_valid); 1785 1786 static int edid_fixup __read_mostly = 6; 1787 module_param_named(edid_fixup, edid_fixup, int, 0400); 1788 MODULE_PARM_DESC(edid_fixup, 1789 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1790 1791 static int edid_block_compute_checksum(const void *_block) 1792 { 1793 const u8 *block = _block; 1794 int i; 1795 u8 csum = 0, crc = 0; 1796 1797 for (i = 0; i < EDID_LENGTH - 1; i++) 1798 csum += block[i]; 1799 1800 crc = 0x100 - csum; 1801 1802 return crc; 1803 } 1804 1805 static int edid_block_get_checksum(const void *_block) 1806 { 1807 const struct edid *block = _block; 1808 1809 return block->checksum; 1810 } 1811 1812 static int edid_block_tag(const void *_block) 1813 { 1814 const u8 *block = _block; 1815 1816 return block[0]; 1817 } 1818 1819 static bool edid_block_is_zero(const void *edid) 1820 { 1821 return mem_is_zero(edid, EDID_LENGTH); 1822 } 1823 1824 static bool drm_edid_eq(const struct drm_edid *drm_edid, 1825 const void *raw_edid, size_t raw_edid_size) 1826 { 1827 bool edid1_present = drm_edid && drm_edid->edid && drm_edid->size; 1828 bool edid2_present = raw_edid && raw_edid_size; 1829 1830 if (edid1_present != edid2_present) 1831 return false; 1832 1833 if (edid1_present) { 1834 if (drm_edid->size != raw_edid_size) 1835 return false; 1836 1837 if (memcmp(drm_edid->edid, raw_edid, drm_edid->size)) 1838 return false; 1839 } 1840 1841 return true; 1842 } 1843 1844 enum edid_block_status { 1845 EDID_BLOCK_OK = 0, 1846 EDID_BLOCK_READ_FAIL, 1847 EDID_BLOCK_NULL, 1848 EDID_BLOCK_ZERO, 1849 EDID_BLOCK_HEADER_CORRUPT, 1850 EDID_BLOCK_HEADER_REPAIR, 1851 EDID_BLOCK_HEADER_FIXED, 1852 EDID_BLOCK_CHECKSUM, 1853 EDID_BLOCK_VERSION, 1854 }; 1855 1856 static enum edid_block_status edid_block_check(const void *_block, 1857 bool is_base_block) 1858 { 1859 const struct edid *block = _block; 1860 1861 if (!block) 1862 return EDID_BLOCK_NULL; 1863 1864 if (is_base_block) { 1865 int score = drm_edid_header_is_valid(block); 1866 1867 if (score < clamp(edid_fixup, 0, 8)) { 1868 if (edid_block_is_zero(block)) 1869 return EDID_BLOCK_ZERO; 1870 else 1871 return EDID_BLOCK_HEADER_CORRUPT; 1872 } 1873 1874 if (score < 8) 1875 return EDID_BLOCK_HEADER_REPAIR; 1876 } 1877 1878 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) { 1879 if (edid_block_is_zero(block)) 1880 return EDID_BLOCK_ZERO; 1881 else 1882 return EDID_BLOCK_CHECKSUM; 1883 } 1884 1885 if (is_base_block) { 1886 if (block->version != 1) 1887 return EDID_BLOCK_VERSION; 1888 } 1889 1890 return EDID_BLOCK_OK; 1891 } 1892 1893 static bool edid_block_status_valid(enum edid_block_status status, int tag) 1894 { 1895 return status == EDID_BLOCK_OK || 1896 status == EDID_BLOCK_HEADER_FIXED || 1897 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT); 1898 } 1899 1900 static bool edid_block_valid(const void *block, bool base) 1901 { 1902 return edid_block_status_valid(edid_block_check(block, base), 1903 edid_block_tag(block)); 1904 } 1905 1906 static void edid_block_status_print(enum edid_block_status status, 1907 const struct edid *block, 1908 int block_num) 1909 { 1910 switch (status) { 1911 case EDID_BLOCK_OK: 1912 break; 1913 case EDID_BLOCK_READ_FAIL: 1914 pr_debug("EDID block %d read failed\n", block_num); 1915 break; 1916 case EDID_BLOCK_NULL: 1917 pr_debug("EDID block %d pointer is NULL\n", block_num); 1918 break; 1919 case EDID_BLOCK_ZERO: 1920 pr_notice("EDID block %d is all zeroes\n", block_num); 1921 break; 1922 case EDID_BLOCK_HEADER_CORRUPT: 1923 pr_notice("EDID has corrupt header\n"); 1924 break; 1925 case EDID_BLOCK_HEADER_REPAIR: 1926 pr_debug("EDID corrupt header needs repair\n"); 1927 break; 1928 case EDID_BLOCK_HEADER_FIXED: 1929 pr_debug("EDID corrupt header fixed\n"); 1930 break; 1931 case EDID_BLOCK_CHECKSUM: 1932 if (edid_block_status_valid(status, edid_block_tag(block))) { 1933 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n", 1934 block_num, edid_block_tag(block), 1935 edid_block_compute_checksum(block)); 1936 } else { 1937 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n", 1938 block_num, edid_block_tag(block), 1939 edid_block_compute_checksum(block)); 1940 } 1941 break; 1942 case EDID_BLOCK_VERSION: 1943 pr_notice("EDID has major version %d, instead of 1\n", 1944 block->version); 1945 break; 1946 default: 1947 WARN(1, "EDID block %d unknown edid block status code %d\n", 1948 block_num, status); 1949 break; 1950 } 1951 } 1952 1953 static void edid_block_dump(const char *level, const void *block, int block_num) 1954 { 1955 enum edid_block_status status; 1956 char prefix[20]; 1957 1958 status = edid_block_check(block, block_num == 0); 1959 if (status == EDID_BLOCK_ZERO) 1960 sprintf(prefix, "\t[%02x] ZERO ", block_num); 1961 else if (!edid_block_status_valid(status, edid_block_tag(block))) 1962 sprintf(prefix, "\t[%02x] BAD ", block_num); 1963 else 1964 sprintf(prefix, "\t[%02x] GOOD ", block_num); 1965 1966 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1, 1967 block, EDID_LENGTH, false); 1968 } 1969 1970 /* 1971 * Validate a base or extension EDID block and optionally dump bad blocks to 1972 * the console. 1973 */ 1974 static bool drm_edid_block_valid(void *_block, int block_num, bool print_bad_edid, 1975 bool *edid_corrupt) 1976 { 1977 struct edid *block = _block; 1978 enum edid_block_status status; 1979 bool is_base_block = block_num == 0; 1980 bool valid; 1981 1982 if (WARN_ON(!block)) 1983 return false; 1984 1985 status = edid_block_check(block, is_base_block); 1986 if (status == EDID_BLOCK_HEADER_REPAIR) { 1987 DRM_DEBUG_KMS("Fixing EDID header, your hardware may be failing\n"); 1988 edid_header_fix(block); 1989 1990 /* Retry with fixed header, update status if that worked. */ 1991 status = edid_block_check(block, is_base_block); 1992 if (status == EDID_BLOCK_OK) 1993 status = EDID_BLOCK_HEADER_FIXED; 1994 } 1995 1996 if (edid_corrupt) { 1997 /* 1998 * Unknown major version isn't corrupt but we can't use it. Only 1999 * the base block can reset edid_corrupt to false. 2000 */ 2001 if (is_base_block && 2002 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)) 2003 *edid_corrupt = false; 2004 else if (status != EDID_BLOCK_OK) 2005 *edid_corrupt = true; 2006 } 2007 2008 edid_block_status_print(status, block, block_num); 2009 2010 /* Determine whether we can use this block with this status. */ 2011 valid = edid_block_status_valid(status, edid_block_tag(block)); 2012 2013 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) { 2014 pr_notice("Raw EDID:\n"); 2015 edid_block_dump(KERN_NOTICE, block, block_num); 2016 } 2017 2018 return valid; 2019 } 2020 2021 /** 2022 * drm_edid_is_valid - sanity check EDID data 2023 * @edid: EDID data 2024 * 2025 * Sanity-check an entire EDID record (including extensions) 2026 * 2027 * Return: True if the EDID data is valid, false otherwise. 2028 */ 2029 bool drm_edid_is_valid(struct edid *edid) 2030 { 2031 int i; 2032 2033 if (!edid) 2034 return false; 2035 2036 for (i = 0; i < edid_block_count(edid); i++) { 2037 void *block = (void *)edid_block_data(edid, i); 2038 2039 if (!drm_edid_block_valid(block, i, true, NULL)) 2040 return false; 2041 } 2042 2043 return true; 2044 } 2045 EXPORT_SYMBOL(drm_edid_is_valid); 2046 2047 /** 2048 * drm_edid_valid - sanity check EDID data 2049 * @drm_edid: EDID data 2050 * 2051 * Sanity check an EDID. Cross check block count against allocated size and 2052 * checksum the blocks. 2053 * 2054 * Return: True if the EDID data is valid, false otherwise. 2055 */ 2056 bool drm_edid_valid(const struct drm_edid *drm_edid) 2057 { 2058 int i; 2059 2060 if (!drm_edid) 2061 return false; 2062 2063 if (edid_size_by_blocks(__drm_edid_block_count(drm_edid)) != drm_edid->size) 2064 return false; 2065 2066 for (i = 0; i < drm_edid_block_count(drm_edid); i++) { 2067 const void *block = drm_edid_block_data(drm_edid, i); 2068 2069 if (!edid_block_valid(block, i == 0)) 2070 return false; 2071 } 2072 2073 return true; 2074 } 2075 EXPORT_SYMBOL(drm_edid_valid); 2076 2077 static struct edid *edid_filter_invalid_blocks(struct edid *edid, 2078 size_t *alloc_size) 2079 { 2080 struct edid *new; 2081 int i, valid_blocks = 0; 2082 2083 /* 2084 * Note: If the EDID uses HF-EEODB, but has invalid blocks, we'll revert 2085 * back to regular extension count here. We don't want to start 2086 * modifying the HF-EEODB extension too. 2087 */ 2088 for (i = 0; i < edid_block_count(edid); i++) { 2089 const void *src_block = edid_block_data(edid, i); 2090 2091 if (edid_block_valid(src_block, i == 0)) { 2092 void *dst_block = (void *)edid_block_data(edid, valid_blocks); 2093 2094 memmove(dst_block, src_block, EDID_LENGTH); 2095 valid_blocks++; 2096 } 2097 } 2098 2099 /* We already trusted the base block to be valid here... */ 2100 if (WARN_ON(!valid_blocks)) { 2101 kfree(edid); 2102 return NULL; 2103 } 2104 2105 edid->extensions = valid_blocks - 1; 2106 edid->checksum = edid_block_compute_checksum(edid); 2107 2108 *alloc_size = edid_size_by_blocks(valid_blocks); 2109 2110 new = krealloc(edid, *alloc_size, GFP_KERNEL); 2111 if (!new) 2112 kfree(edid); 2113 2114 return new; 2115 } 2116 2117 #define DDC_SEGMENT_ADDR 0x30 2118 /** 2119 * drm_do_probe_ddc_edid() - get EDID information via I2C 2120 * @data: I2C device adapter 2121 * @buf: EDID data buffer to be filled 2122 * @block: 128 byte EDID block to start fetching from 2123 * @len: EDID data buffer length to fetch 2124 * 2125 * Try to fetch EDID information by calling I2C driver functions. 2126 * 2127 * Return: 0 on success or -1 on failure. 2128 */ 2129 static int 2130 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 2131 { 2132 struct i2c_adapter *adapter = data; 2133 unsigned char start = block * EDID_LENGTH; 2134 unsigned char segment = block >> 1; 2135 unsigned char xfers = segment ? 3 : 2; 2136 int ret, retries = 5; 2137 2138 /* 2139 * The core I2C driver will automatically retry the transfer if the 2140 * adapter reports EAGAIN. However, we find that bit-banging transfers 2141 * are susceptible to errors under a heavily loaded machine and 2142 * generate spurious NAKs and timeouts. Retrying the transfer 2143 * of the individual block a few times seems to overcome this. 2144 */ 2145 do { 2146 struct i2c_msg msgs[] = { 2147 { 2148 .addr = DDC_SEGMENT_ADDR, 2149 .flags = 0, 2150 .len = 1, 2151 .buf = &segment, 2152 }, { 2153 .addr = DDC_ADDR, 2154 .flags = 0, 2155 .len = 1, 2156 .buf = &start, 2157 }, { 2158 .addr = DDC_ADDR, 2159 .flags = I2C_M_RD, 2160 .len = len, 2161 .buf = buf, 2162 } 2163 }; 2164 2165 /* 2166 * Avoid sending the segment addr to not upset non-compliant 2167 * DDC monitors. 2168 */ 2169 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 2170 2171 if (ret == -ENXIO) { 2172 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 2173 adapter->name); 2174 break; 2175 } 2176 } while (ret != xfers && --retries); 2177 2178 return ret == xfers ? 0 : -1; 2179 } 2180 2181 static void connector_bad_edid(struct drm_connector *connector, 2182 const struct edid *edid, int num_blocks) 2183 { 2184 int i; 2185 u8 last_block; 2186 2187 /* 2188 * 0x7e in the EDID is the number of extension blocks. The EDID 2189 * is 1 (base block) + num_ext_blocks big. That means we can think 2190 * of 0x7e in the EDID of the _index_ of the last block in the 2191 * combined chunk of memory. 2192 */ 2193 last_block = edid->extensions; 2194 2195 /* Calculate real checksum for the last edid extension block data */ 2196 if (last_block < num_blocks) 2197 connector->real_edid_checksum = 2198 edid_block_compute_checksum(edid + last_block); 2199 2200 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS)) 2201 return; 2202 2203 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID is invalid:\n", 2204 connector->base.id, connector->name); 2205 for (i = 0; i < num_blocks; i++) 2206 edid_block_dump(KERN_DEBUG, edid + i, i); 2207 } 2208 2209 /* Get override or firmware EDID */ 2210 static const struct drm_edid *drm_edid_override_get(struct drm_connector *connector) 2211 { 2212 const struct drm_edid *override = NULL; 2213 2214 mutex_lock(&connector->edid_override_mutex); 2215 2216 if (connector->edid_override) 2217 override = drm_edid_dup(connector->edid_override); 2218 2219 mutex_unlock(&connector->edid_override_mutex); 2220 2221 if (!override) 2222 override = drm_edid_load_firmware(connector); 2223 2224 return IS_ERR(override) ? NULL : override; 2225 } 2226 2227 /* For debugfs edid_override implementation */ 2228 int drm_edid_override_show(struct drm_connector *connector, struct seq_file *m) 2229 { 2230 const struct drm_edid *drm_edid; 2231 2232 mutex_lock(&connector->edid_override_mutex); 2233 2234 drm_edid = connector->edid_override; 2235 if (drm_edid) 2236 seq_write(m, drm_edid->edid, drm_edid->size); 2237 2238 mutex_unlock(&connector->edid_override_mutex); 2239 2240 return 0; 2241 } 2242 2243 /* For debugfs edid_override implementation */ 2244 int drm_edid_override_set(struct drm_connector *connector, const void *edid, 2245 size_t size) 2246 { 2247 const struct drm_edid *drm_edid; 2248 2249 drm_edid = drm_edid_alloc(edid, size); 2250 if (!drm_edid_valid(drm_edid)) { 2251 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override invalid\n", 2252 connector->base.id, connector->name); 2253 drm_edid_free(drm_edid); 2254 return -EINVAL; 2255 } 2256 2257 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override set\n", 2258 connector->base.id, connector->name); 2259 2260 mutex_lock(&connector->edid_override_mutex); 2261 2262 drm_edid_free(connector->edid_override); 2263 connector->edid_override = drm_edid; 2264 2265 mutex_unlock(&connector->edid_override_mutex); 2266 2267 return 0; 2268 } 2269 2270 /* For debugfs edid_override implementation */ 2271 int drm_edid_override_reset(struct drm_connector *connector) 2272 { 2273 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override reset\n", 2274 connector->base.id, connector->name); 2275 2276 mutex_lock(&connector->edid_override_mutex); 2277 2278 drm_edid_free(connector->edid_override); 2279 connector->edid_override = NULL; 2280 2281 mutex_unlock(&connector->edid_override_mutex); 2282 2283 return 0; 2284 } 2285 2286 /** 2287 * drm_edid_override_connector_update - add modes from override/firmware EDID 2288 * @connector: connector we're probing 2289 * 2290 * Add modes from the override/firmware EDID, if available. Only to be used from 2291 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe 2292 * failed during drm_get_edid() and caused the override/firmware EDID to be 2293 * skipped. 2294 * 2295 * Return: The number of modes added or 0 if we couldn't find any. 2296 */ 2297 int drm_edid_override_connector_update(struct drm_connector *connector) 2298 { 2299 const struct drm_edid *override; 2300 int num_modes = 0; 2301 2302 override = drm_edid_override_get(connector); 2303 if (override) { 2304 if (drm_edid_connector_update(connector, override) == 0) 2305 num_modes = drm_edid_connector_add_modes(connector); 2306 2307 drm_edid_free(override); 2308 2309 drm_dbg_kms(connector->dev, 2310 "[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n", 2311 connector->base.id, connector->name, num_modes); 2312 } 2313 2314 return num_modes; 2315 } 2316 EXPORT_SYMBOL(drm_edid_override_connector_update); 2317 2318 typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len); 2319 2320 static enum edid_block_status edid_block_read(void *block, unsigned int block_num, 2321 read_block_fn read_block, 2322 void *context) 2323 { 2324 enum edid_block_status status; 2325 bool is_base_block = block_num == 0; 2326 int try; 2327 2328 for (try = 0; try < 4; try++) { 2329 if (read_block(context, block, block_num, EDID_LENGTH)) 2330 return EDID_BLOCK_READ_FAIL; 2331 2332 status = edid_block_check(block, is_base_block); 2333 if (status == EDID_BLOCK_HEADER_REPAIR) { 2334 edid_header_fix(block); 2335 2336 /* Retry with fixed header, update status if that worked. */ 2337 status = edid_block_check(block, is_base_block); 2338 if (status == EDID_BLOCK_OK) 2339 status = EDID_BLOCK_HEADER_FIXED; 2340 } 2341 2342 if (edid_block_status_valid(status, edid_block_tag(block))) 2343 break; 2344 2345 /* Fail early for unrepairable base block all zeros. */ 2346 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO) 2347 break; 2348 } 2349 2350 return status; 2351 } 2352 2353 static struct edid *_drm_do_get_edid(struct drm_connector *connector, 2354 read_block_fn read_block, void *context, 2355 size_t *size) 2356 { 2357 enum edid_block_status status; 2358 int i, num_blocks, invalid_blocks = 0; 2359 const struct drm_edid *override; 2360 struct edid *edid, *new; 2361 size_t alloc_size = EDID_LENGTH; 2362 2363 override = drm_edid_override_get(connector); 2364 if (override) { 2365 alloc_size = override->size; 2366 edid = kmemdup(override->edid, alloc_size, GFP_KERNEL); 2367 drm_edid_free(override); 2368 if (!edid) 2369 return NULL; 2370 goto ok; 2371 } 2372 2373 edid = kmalloc(alloc_size, GFP_KERNEL); 2374 if (!edid) 2375 return NULL; 2376 2377 status = edid_block_read(edid, 0, read_block, context); 2378 2379 edid_block_status_print(status, edid, 0); 2380 2381 if (status == EDID_BLOCK_READ_FAIL) 2382 goto fail; 2383 2384 /* FIXME: Clarify what a corrupt EDID actually means. */ 2385 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION) 2386 connector->edid_corrupt = false; 2387 else 2388 connector->edid_corrupt = true; 2389 2390 if (!edid_block_status_valid(status, edid_block_tag(edid))) { 2391 if (status == EDID_BLOCK_ZERO) 2392 connector->null_edid_counter++; 2393 2394 connector_bad_edid(connector, edid, 1); 2395 goto fail; 2396 } 2397 2398 if (!edid_extension_block_count(edid)) 2399 goto ok; 2400 2401 alloc_size = edid_size(edid); 2402 new = krealloc(edid, alloc_size, GFP_KERNEL); 2403 if (!new) 2404 goto fail; 2405 edid = new; 2406 2407 num_blocks = edid_block_count(edid); 2408 for (i = 1; i < num_blocks; i++) { 2409 void *block = (void *)edid_block_data(edid, i); 2410 2411 status = edid_block_read(block, i, read_block, context); 2412 2413 edid_block_status_print(status, block, i); 2414 2415 if (!edid_block_status_valid(status, edid_block_tag(block))) { 2416 if (status == EDID_BLOCK_READ_FAIL) 2417 goto fail; 2418 invalid_blocks++; 2419 } else if (i == 1) { 2420 /* 2421 * If the first EDID extension is a CTA extension, and 2422 * the first Data Block is HF-EEODB, override the 2423 * extension block count. 2424 * 2425 * Note: HF-EEODB could specify a smaller extension 2426 * count too, but we can't risk allocating a smaller 2427 * amount. 2428 */ 2429 int eeodb = edid_hfeeodb_block_count(edid); 2430 2431 if (eeodb > num_blocks) { 2432 num_blocks = eeodb; 2433 alloc_size = edid_size_by_blocks(num_blocks); 2434 new = krealloc(edid, alloc_size, GFP_KERNEL); 2435 if (!new) 2436 goto fail; 2437 edid = new; 2438 } 2439 } 2440 } 2441 2442 if (invalid_blocks) { 2443 connector_bad_edid(connector, edid, num_blocks); 2444 2445 edid = edid_filter_invalid_blocks(edid, &alloc_size); 2446 } 2447 2448 ok: 2449 if (size) 2450 *size = alloc_size; 2451 2452 return edid; 2453 2454 fail: 2455 kfree(edid); 2456 return NULL; 2457 } 2458 2459 /** 2460 * drm_edid_raw - Get a pointer to the raw EDID data. 2461 * @drm_edid: drm_edid container 2462 * 2463 * Get a pointer to the raw EDID data. 2464 * 2465 * This is for transition only. Avoid using this like the plague. 2466 * 2467 * Return: Pointer to raw EDID data. 2468 */ 2469 const struct edid *drm_edid_raw(const struct drm_edid *drm_edid) 2470 { 2471 if (!drm_edid || !drm_edid->size) 2472 return NULL; 2473 2474 /* 2475 * Do not return pointers where relying on EDID extension count would 2476 * lead to buffer overflow. 2477 */ 2478 if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size)) 2479 return NULL; 2480 2481 return drm_edid->edid; 2482 } 2483 EXPORT_SYMBOL(drm_edid_raw); 2484 2485 /* Allocate struct drm_edid container *without* duplicating the edid data */ 2486 static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size) 2487 { 2488 struct drm_edid *drm_edid; 2489 2490 if (!edid || !size || size < EDID_LENGTH) 2491 return NULL; 2492 2493 drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL); 2494 if (drm_edid) { 2495 drm_edid->edid = edid; 2496 drm_edid->size = size; 2497 } 2498 2499 return drm_edid; 2500 } 2501 2502 /** 2503 * drm_edid_alloc - Allocate a new drm_edid container 2504 * @edid: Pointer to raw EDID data 2505 * @size: Size of memory allocated for EDID 2506 * 2507 * Allocate a new drm_edid container. Do not calculate edid size from edid, pass 2508 * the actual size that has been allocated for the data. There is no validation 2509 * of the raw EDID data against the size, but at least the EDID base block must 2510 * fit in the buffer. 2511 * 2512 * The returned pointer must be freed using drm_edid_free(). 2513 * 2514 * Return: drm_edid container, or NULL on errors 2515 */ 2516 const struct drm_edid *drm_edid_alloc(const void *edid, size_t size) 2517 { 2518 const struct drm_edid *drm_edid; 2519 2520 if (!edid || !size || size < EDID_LENGTH) 2521 return NULL; 2522 2523 edid = kmemdup(edid, size, GFP_KERNEL); 2524 if (!edid) 2525 return NULL; 2526 2527 drm_edid = _drm_edid_alloc(edid, size); 2528 if (!drm_edid) 2529 kfree(edid); 2530 2531 return drm_edid; 2532 } 2533 EXPORT_SYMBOL(drm_edid_alloc); 2534 2535 /** 2536 * drm_edid_dup - Duplicate a drm_edid container 2537 * @drm_edid: EDID to duplicate 2538 * 2539 * The returned pointer must be freed using drm_edid_free(). 2540 * 2541 * Returns: drm_edid container copy, or NULL on errors 2542 */ 2543 const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid) 2544 { 2545 if (!drm_edid) 2546 return NULL; 2547 2548 return drm_edid_alloc(drm_edid->edid, drm_edid->size); 2549 } 2550 EXPORT_SYMBOL(drm_edid_dup); 2551 2552 /** 2553 * drm_edid_free - Free the drm_edid container 2554 * @drm_edid: EDID to free 2555 */ 2556 void drm_edid_free(const struct drm_edid *drm_edid) 2557 { 2558 if (!drm_edid) 2559 return; 2560 2561 kfree(drm_edid->edid); 2562 kfree(drm_edid); 2563 } 2564 EXPORT_SYMBOL(drm_edid_free); 2565 2566 /** 2567 * drm_probe_ddc() - probe DDC presence 2568 * @adapter: I2C adapter to probe 2569 * 2570 * Return: True on success, false on failure. 2571 */ 2572 bool 2573 drm_probe_ddc(struct i2c_adapter *adapter) 2574 { 2575 unsigned char out; 2576 2577 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 2578 } 2579 EXPORT_SYMBOL(drm_probe_ddc); 2580 2581 /** 2582 * drm_get_edid - get EDID data, if available 2583 * @connector: connector we're probing 2584 * @adapter: I2C adapter to use for DDC 2585 * 2586 * Poke the given I2C channel to grab EDID data if possible. If found, 2587 * attach it to the connector. 2588 * 2589 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2590 */ 2591 struct edid *drm_get_edid(struct drm_connector *connector, 2592 struct i2c_adapter *adapter) 2593 { 2594 struct edid *edid; 2595 2596 if (connector->force == DRM_FORCE_OFF) 2597 return NULL; 2598 2599 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2600 return NULL; 2601 2602 edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL); 2603 drm_connector_update_edid_property(connector, edid); 2604 return edid; 2605 } 2606 EXPORT_SYMBOL(drm_get_edid); 2607 2608 /** 2609 * drm_edid_read_custom - Read EDID data using given EDID block read function 2610 * @connector: Connector to use 2611 * @read_block: EDID block read function 2612 * @context: Private data passed to the block read function 2613 * 2614 * When the I2C adapter connected to the DDC bus is hidden behind a device that 2615 * exposes a different interface to read EDID blocks this function can be used 2616 * to get EDID data using a custom block read function. 2617 * 2618 * As in the general case the DDC bus is accessible by the kernel at the I2C 2619 * level, drivers must make all reasonable efforts to expose it as an I2C 2620 * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing 2621 * this function. 2622 * 2623 * The EDID may be overridden using debugfs override_edid or firmware EDID 2624 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2625 * order. Having either of them bypasses actual EDID reads. 2626 * 2627 * The returned pointer must be freed using drm_edid_free(). 2628 * 2629 * Return: Pointer to EDID, or NULL if probe/read failed. 2630 */ 2631 const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector, 2632 read_block_fn read_block, 2633 void *context) 2634 { 2635 const struct drm_edid *drm_edid; 2636 struct edid *edid; 2637 size_t size = 0; 2638 2639 edid = _drm_do_get_edid(connector, read_block, context, &size); 2640 if (!edid) 2641 return NULL; 2642 2643 /* Sanity check for now */ 2644 drm_WARN_ON(connector->dev, !size); 2645 2646 drm_edid = _drm_edid_alloc(edid, size); 2647 if (!drm_edid) 2648 kfree(edid); 2649 2650 return drm_edid; 2651 } 2652 EXPORT_SYMBOL(drm_edid_read_custom); 2653 2654 /** 2655 * drm_edid_read_ddc - Read EDID data using given I2C adapter 2656 * @connector: Connector to use 2657 * @adapter: I2C adapter to use for DDC 2658 * 2659 * Read EDID using the given I2C adapter. 2660 * 2661 * The EDID may be overridden using debugfs override_edid or firmware EDID 2662 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2663 * order. Having either of them bypasses actual EDID reads. 2664 * 2665 * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and 2666 * using drm_edid_read() instead of this function. 2667 * 2668 * The returned pointer must be freed using drm_edid_free(). 2669 * 2670 * Return: Pointer to EDID, or NULL if probe/read failed. 2671 */ 2672 const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector, 2673 struct i2c_adapter *adapter) 2674 { 2675 const struct drm_edid *drm_edid; 2676 2677 if (connector->force == DRM_FORCE_OFF) 2678 return NULL; 2679 2680 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2681 return NULL; 2682 2683 drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter); 2684 2685 /* Note: Do *not* call connector updates here. */ 2686 2687 return drm_edid; 2688 } 2689 EXPORT_SYMBOL(drm_edid_read_ddc); 2690 2691 /** 2692 * drm_edid_read - Read EDID data using connector's I2C adapter 2693 * @connector: Connector to use 2694 * 2695 * Read EDID using the connector's I2C adapter. 2696 * 2697 * The EDID may be overridden using debugfs override_edid or firmware EDID 2698 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2699 * order. Having either of them bypasses actual EDID reads. 2700 * 2701 * The returned pointer must be freed using drm_edid_free(). 2702 * 2703 * Return: Pointer to EDID, or NULL if probe/read failed. 2704 */ 2705 const struct drm_edid *drm_edid_read(struct drm_connector *connector) 2706 { 2707 if (drm_WARN_ON(connector->dev, !connector->ddc)) 2708 return NULL; 2709 2710 return drm_edid_read_ddc(connector, connector->ddc); 2711 } 2712 EXPORT_SYMBOL(drm_edid_read); 2713 2714 /** 2715 * drm_edid_get_product_id - Get the vendor and product identification 2716 * @drm_edid: EDID 2717 * @id: Where to place the product id 2718 */ 2719 void drm_edid_get_product_id(const struct drm_edid *drm_edid, 2720 struct drm_edid_product_id *id) 2721 { 2722 if (drm_edid && drm_edid->edid && drm_edid->size >= EDID_LENGTH) 2723 memcpy(id, &drm_edid->edid->product_id, sizeof(*id)); 2724 else 2725 memset(id, 0, sizeof(*id)); 2726 } 2727 EXPORT_SYMBOL(drm_edid_get_product_id); 2728 2729 static void decode_date(struct seq_buf *s, const struct drm_edid_product_id *id) 2730 { 2731 int week = id->week_of_manufacture; 2732 int year = id->year_of_manufacture + 1990; 2733 2734 if (week == 0xff) 2735 seq_buf_printf(s, "model year: %d", year); 2736 else if (!week) 2737 seq_buf_printf(s, "year of manufacture: %d", year); 2738 else 2739 seq_buf_printf(s, "week/year of manufacture: %d/%d", week, year); 2740 } 2741 2742 /** 2743 * drm_edid_print_product_id - Print decoded product id to printer 2744 * @p: drm printer 2745 * @id: EDID product id 2746 * @raw: If true, also print the raw hex 2747 * 2748 * See VESA E-EDID 1.4 section 3.4. 2749 */ 2750 void drm_edid_print_product_id(struct drm_printer *p, 2751 const struct drm_edid_product_id *id, bool raw) 2752 { 2753 DECLARE_SEQ_BUF(date, 40); 2754 char vend[4]; 2755 2756 drm_edid_decode_mfg_id(be16_to_cpu(id->manufacturer_name), vend); 2757 2758 decode_date(&date, id); 2759 2760 drm_printf(p, "manufacturer name: %s, product code: %u, serial number: %u, %s\n", 2761 vend, le16_to_cpu(id->product_code), 2762 le32_to_cpu(id->serial_number), seq_buf_str(&date)); 2763 2764 if (raw) 2765 drm_printf(p, "raw product id: %*ph\n", (int)sizeof(*id), id); 2766 2767 WARN_ON(seq_buf_has_overflowed(&date)); 2768 } 2769 EXPORT_SYMBOL(drm_edid_print_product_id); 2770 2771 /** 2772 * drm_edid_get_panel_id - Get a panel's ID from EDID 2773 * @drm_edid: EDID that contains panel ID. 2774 * 2775 * This function uses the first block of the EDID of a panel and (assuming 2776 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value 2777 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's 2778 * supposed to be different for each different modem of panel. 2779 * 2780 * Return: A 32-bit ID that should be different for each make/model of panel. 2781 * See the functions drm_edid_encode_panel_id() and 2782 * drm_edid_decode_panel_id() for some details on the structure of this 2783 * ID. Return 0 if the EDID size is less than a base block. 2784 */ 2785 u32 drm_edid_get_panel_id(const struct drm_edid *drm_edid) 2786 { 2787 const struct edid *edid = drm_edid->edid; 2788 2789 if (drm_edid->size < EDID_LENGTH) 2790 return 0; 2791 2792 /* 2793 * We represent the ID as a 32-bit number so it can easily be compared 2794 * with "==". 2795 * 2796 * NOTE that we deal with endianness differently for the top half 2797 * of this ID than for the bottom half. The bottom half (the product 2798 * id) gets decoded as little endian by the EDID_PRODUCT_ID because 2799 * that's how everyone seems to interpret it. The top half (the mfg_id) 2800 * gets stored as big endian because that makes 2801 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier 2802 * to write (it's easier to extract the ASCII). It doesn't really 2803 * matter, though, as long as the number here is unique. 2804 */ 2805 return (u32)edid->mfg_id[0] << 24 | 2806 (u32)edid->mfg_id[1] << 16 | 2807 (u32)EDID_PRODUCT_ID(edid); 2808 } 2809 EXPORT_SYMBOL(drm_edid_get_panel_id); 2810 2811 /** 2812 * drm_edid_read_base_block - Get a panel's EDID base block 2813 * @adapter: I2C adapter to use for DDC 2814 * 2815 * This function returns the drm_edid containing the first block of the EDID of 2816 * a panel. 2817 * 2818 * This function is intended to be used during early probing on devices where 2819 * more than one panel might be present. Because of its intended use it must 2820 * assume that the EDID of the panel is correct, at least as far as the base 2821 * block is concerned (in other words, we don't process any overrides here). 2822 * 2823 * Caller should call drm_edid_free() after use. 2824 * 2825 * NOTE: it's expected that this function and drm_do_get_edid() will both 2826 * be read the EDID, but there is no caching between them. Since we're only 2827 * reading the first block, hopefully this extra overhead won't be too big. 2828 * 2829 * WARNING: Only use this function when the connector is unknown. For example, 2830 * during the early probe of panel. The EDID read from the function is temporary 2831 * and should be replaced by the full EDID returned from other drm_edid_read. 2832 * 2833 * Return: Pointer to allocated EDID base block, or NULL on any failure. 2834 */ 2835 const struct drm_edid *drm_edid_read_base_block(struct i2c_adapter *adapter) 2836 { 2837 enum edid_block_status status; 2838 void *base_block; 2839 2840 base_block = kzalloc(EDID_LENGTH, GFP_KERNEL); 2841 if (!base_block) 2842 return NULL; 2843 2844 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter); 2845 2846 edid_block_status_print(status, base_block, 0); 2847 2848 if (!edid_block_status_valid(status, edid_block_tag(base_block))) { 2849 edid_block_dump(KERN_NOTICE, base_block, 0); 2850 kfree(base_block); 2851 return NULL; 2852 } 2853 2854 return _drm_edid_alloc(base_block, EDID_LENGTH); 2855 } 2856 EXPORT_SYMBOL(drm_edid_read_base_block); 2857 2858 /** 2859 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 2860 * @connector: connector we're probing 2861 * @adapter: I2C adapter to use for DDC 2862 * 2863 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 2864 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 2865 * switch DDC to the GPU which is retrieving EDID. 2866 * 2867 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2868 */ 2869 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 2870 struct i2c_adapter *adapter) 2871 { 2872 struct drm_device *dev = connector->dev; 2873 struct pci_dev *pdev = to_pci_dev(dev->dev); 2874 struct edid *edid; 2875 2876 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev))) 2877 return NULL; 2878 2879 vga_switcheroo_lock_ddc(pdev); 2880 edid = drm_get_edid(connector, adapter); 2881 vga_switcheroo_unlock_ddc(pdev); 2882 2883 return edid; 2884 } 2885 EXPORT_SYMBOL(drm_get_edid_switcheroo); 2886 2887 /** 2888 * drm_edid_read_switcheroo - get EDID data for a vga_switcheroo output 2889 * @connector: connector we're probing 2890 * @adapter: I2C adapter to use for DDC 2891 * 2892 * Wrapper around drm_edid_read_ddc() for laptops with dual GPUs using one set 2893 * of outputs. The wrapper adds the requisite vga_switcheroo calls to 2894 * temporarily switch DDC to the GPU which is retrieving EDID. 2895 * 2896 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2897 */ 2898 const struct drm_edid *drm_edid_read_switcheroo(struct drm_connector *connector, 2899 struct i2c_adapter *adapter) 2900 { 2901 struct drm_device *dev = connector->dev; 2902 struct pci_dev *pdev = to_pci_dev(dev->dev); 2903 const struct drm_edid *drm_edid; 2904 2905 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev))) 2906 return NULL; 2907 2908 vga_switcheroo_lock_ddc(pdev); 2909 drm_edid = drm_edid_read_ddc(connector, adapter); 2910 vga_switcheroo_unlock_ddc(pdev); 2911 2912 return drm_edid; 2913 } 2914 EXPORT_SYMBOL(drm_edid_read_switcheroo); 2915 2916 /** 2917 * drm_edid_duplicate - duplicate an EDID and the extensions 2918 * @edid: EDID to duplicate 2919 * 2920 * Return: Pointer to duplicated EDID or NULL on allocation failure. 2921 */ 2922 struct edid *drm_edid_duplicate(const struct edid *edid) 2923 { 2924 if (!edid) 2925 return NULL; 2926 2927 return kmemdup(edid, edid_size(edid), GFP_KERNEL); 2928 } 2929 EXPORT_SYMBOL(drm_edid_duplicate); 2930 2931 /*** EDID parsing ***/ 2932 2933 /** 2934 * edid_get_quirks - return quirk flags for a given EDID 2935 * @drm_edid: EDID to process 2936 * 2937 * This tells subsequent routines what fixes they need to apply. 2938 * 2939 * Return: A u32 represents the quirks to apply. 2940 */ 2941 static u32 edid_get_quirks(const struct drm_edid *drm_edid) 2942 { 2943 const struct edid_quirk *quirk; 2944 int i; 2945 2946 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 2947 quirk = &edid_quirk_list[i]; 2948 if (drm_edid_match(drm_edid, &quirk->ident)) 2949 return quirk->quirks; 2950 } 2951 2952 return 0; 2953 } 2954 2955 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 2956 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 2957 2958 /* 2959 * Walk the mode list for connector, clearing the preferred status on existing 2960 * modes and setting it anew for the right mode ala quirks. 2961 */ 2962 static void edid_fixup_preferred(struct drm_connector *connector) 2963 { 2964 const struct drm_display_info *info = &connector->display_info; 2965 struct drm_display_mode *t, *cur_mode, *preferred_mode; 2966 int target_refresh = 0; 2967 int cur_vrefresh, preferred_vrefresh; 2968 2969 if (list_empty(&connector->probed_modes)) 2970 return; 2971 2972 if (info->quirks & EDID_QUIRK_PREFER_LARGE_60) 2973 target_refresh = 60; 2974 if (info->quirks & EDID_QUIRK_PREFER_LARGE_75) 2975 target_refresh = 75; 2976 2977 preferred_mode = list_first_entry(&connector->probed_modes, 2978 struct drm_display_mode, head); 2979 2980 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 2981 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 2982 2983 if (cur_mode == preferred_mode) 2984 continue; 2985 2986 /* Largest mode is preferred */ 2987 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 2988 preferred_mode = cur_mode; 2989 2990 cur_vrefresh = drm_mode_vrefresh(cur_mode); 2991 preferred_vrefresh = drm_mode_vrefresh(preferred_mode); 2992 /* At a given size, try to get closest to target refresh */ 2993 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 2994 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 2995 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 2996 preferred_mode = cur_mode; 2997 } 2998 } 2999 3000 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 3001 } 3002 3003 static bool 3004 mode_is_rb(const struct drm_display_mode *mode) 3005 { 3006 return (mode->htotal - mode->hdisplay == 160) && 3007 (mode->hsync_end - mode->hdisplay == 80) && 3008 (mode->hsync_end - mode->hsync_start == 32) && 3009 (mode->vsync_start - mode->vdisplay == 3); 3010 } 3011 3012 /* 3013 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 3014 * @dev: Device to duplicate against 3015 * @hsize: Mode width 3016 * @vsize: Mode height 3017 * @fresh: Mode refresh rate 3018 * @rb: Mode reduced-blanking-ness 3019 * 3020 * Walk the DMT mode list looking for a match for the given parameters. 3021 * 3022 * Return: A newly allocated copy of the mode, or NULL if not found. 3023 */ 3024 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 3025 int hsize, int vsize, int fresh, 3026 bool rb) 3027 { 3028 int i; 3029 3030 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 3031 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 3032 3033 if (hsize != ptr->hdisplay) 3034 continue; 3035 if (vsize != ptr->vdisplay) 3036 continue; 3037 if (fresh != drm_mode_vrefresh(ptr)) 3038 continue; 3039 if (rb != mode_is_rb(ptr)) 3040 continue; 3041 3042 return drm_mode_duplicate(dev, ptr); 3043 } 3044 3045 return NULL; 3046 } 3047 EXPORT_SYMBOL(drm_mode_find_dmt); 3048 3049 static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type) 3050 { 3051 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0); 3052 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2); 3053 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3); 3054 3055 return descriptor->pixel_clock == 0 && 3056 descriptor->data.other_data.pad1 == 0 && 3057 descriptor->data.other_data.type == type; 3058 } 3059 3060 static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor) 3061 { 3062 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0); 3063 3064 return descriptor->pixel_clock != 0; 3065 } 3066 3067 typedef void detailed_cb(const struct detailed_timing *timing, void *closure); 3068 3069 static void 3070 cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure) 3071 { 3072 int i, n; 3073 u8 d = ext[0x02]; 3074 const u8 *det_base = ext + d; 3075 3076 if (d < 4 || d > 127) 3077 return; 3078 3079 n = (127 - d) / 18; 3080 for (i = 0; i < n; i++) 3081 cb((const struct detailed_timing *)(det_base + 18 * i), closure); 3082 } 3083 3084 static void 3085 vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure) 3086 { 3087 unsigned int i, n = min((int)ext[0x02], 6); 3088 const u8 *det_base = ext + 5; 3089 3090 if (ext[0x01] != 1) 3091 return; /* unknown version */ 3092 3093 for (i = 0; i < n; i++) 3094 cb((const struct detailed_timing *)(det_base + 18 * i), closure); 3095 } 3096 3097 static void drm_for_each_detailed_block(const struct drm_edid *drm_edid, 3098 detailed_cb *cb, void *closure) 3099 { 3100 struct drm_edid_iter edid_iter; 3101 const u8 *ext; 3102 int i; 3103 3104 if (!drm_edid) 3105 return; 3106 3107 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 3108 cb(&drm_edid->edid->detailed_timings[i], closure); 3109 3110 drm_edid_iter_begin(drm_edid, &edid_iter); 3111 drm_edid_iter_for_each(ext, &edid_iter) { 3112 switch (*ext) { 3113 case CEA_EXT: 3114 cea_for_each_detailed_block(ext, cb, closure); 3115 break; 3116 case VTB_EXT: 3117 vtb_for_each_detailed_block(ext, cb, closure); 3118 break; 3119 default: 3120 break; 3121 } 3122 } 3123 drm_edid_iter_end(&edid_iter); 3124 } 3125 3126 static void 3127 is_rb(const struct detailed_timing *descriptor, void *data) 3128 { 3129 bool *res = data; 3130 3131 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 3132 return; 3133 3134 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 3135 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15); 3136 3137 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG && 3138 descriptor->data.other_data.data.range.formula.cvt.flags & DRM_EDID_CVT_FLAGS_REDUCED_BLANKING) 3139 *res = true; 3140 } 3141 3142 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 3143 static bool 3144 drm_monitor_supports_rb(const struct drm_edid *drm_edid) 3145 { 3146 if (drm_edid->edid->revision >= 4) { 3147 bool ret = false; 3148 3149 drm_for_each_detailed_block(drm_edid, is_rb, &ret); 3150 return ret; 3151 } 3152 3153 return drm_edid_is_digital(drm_edid); 3154 } 3155 3156 static void 3157 find_gtf2(const struct detailed_timing *descriptor, void *data) 3158 { 3159 const struct detailed_timing **res = data; 3160 3161 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 3162 return; 3163 3164 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 3165 3166 if (descriptor->data.other_data.data.range.flags == DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG) 3167 *res = descriptor; 3168 } 3169 3170 /* Secondary GTF curve kicks in above some break frequency */ 3171 static int 3172 drm_gtf2_hbreak(const struct drm_edid *drm_edid) 3173 { 3174 const struct detailed_timing *descriptor = NULL; 3175 3176 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3177 3178 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12); 3179 3180 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0; 3181 } 3182 3183 static int 3184 drm_gtf2_2c(const struct drm_edid *drm_edid) 3185 { 3186 const struct detailed_timing *descriptor = NULL; 3187 3188 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3189 3190 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13); 3191 3192 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0; 3193 } 3194 3195 static int 3196 drm_gtf2_m(const struct drm_edid *drm_edid) 3197 { 3198 const struct detailed_timing *descriptor = NULL; 3199 3200 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3201 3202 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14); 3203 3204 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0; 3205 } 3206 3207 static int 3208 drm_gtf2_k(const struct drm_edid *drm_edid) 3209 { 3210 const struct detailed_timing *descriptor = NULL; 3211 3212 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3213 3214 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16); 3215 3216 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0; 3217 } 3218 3219 static int 3220 drm_gtf2_2j(const struct drm_edid *drm_edid) 3221 { 3222 const struct detailed_timing *descriptor = NULL; 3223 3224 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3225 3226 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17); 3227 3228 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0; 3229 } 3230 3231 static void 3232 get_timing_level(const struct detailed_timing *descriptor, void *data) 3233 { 3234 int *res = data; 3235 3236 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 3237 return; 3238 3239 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 3240 3241 switch (descriptor->data.other_data.data.range.flags) { 3242 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG: 3243 *res = LEVEL_GTF; 3244 break; 3245 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG: 3246 *res = LEVEL_GTF2; 3247 break; 3248 case DRM_EDID_CVT_SUPPORT_FLAG: 3249 *res = LEVEL_CVT; 3250 break; 3251 default: 3252 break; 3253 } 3254 } 3255 3256 /* Get standard timing level (CVT/GTF/DMT). */ 3257 static int standard_timing_level(const struct drm_edid *drm_edid) 3258 { 3259 const struct edid *edid = drm_edid->edid; 3260 3261 if (edid->revision >= 4) { 3262 /* 3263 * If the range descriptor doesn't 3264 * indicate otherwise default to CVT 3265 */ 3266 int ret = LEVEL_CVT; 3267 3268 drm_for_each_detailed_block(drm_edid, get_timing_level, &ret); 3269 3270 return ret; 3271 } else if (edid->revision >= 3 && drm_gtf2_hbreak(drm_edid)) { 3272 return LEVEL_GTF2; 3273 } else if (edid->revision >= 2) { 3274 return LEVEL_GTF; 3275 } else { 3276 return LEVEL_DMT; 3277 } 3278 } 3279 3280 /* 3281 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 3282 * monitors fill with ascii space (0x20) instead. 3283 */ 3284 static int 3285 bad_std_timing(u8 a, u8 b) 3286 { 3287 return (a == 0x00 && b == 0x00) || 3288 (a == 0x01 && b == 0x01) || 3289 (a == 0x20 && b == 0x20); 3290 } 3291 3292 static int drm_mode_hsync(const struct drm_display_mode *mode) 3293 { 3294 if (mode->htotal <= 0) 3295 return 0; 3296 3297 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal); 3298 } 3299 3300 static struct drm_display_mode * 3301 drm_gtf2_mode(struct drm_device *dev, 3302 const struct drm_edid *drm_edid, 3303 int hsize, int vsize, int vrefresh_rate) 3304 { 3305 struct drm_display_mode *mode; 3306 3307 /* 3308 * This is potentially wrong if there's ever a monitor with 3309 * more than one ranges section, each claiming a different 3310 * secondary GTF curve. Please don't do that. 3311 */ 3312 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 3313 if (!mode) 3314 return NULL; 3315 3316 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) { 3317 drm_mode_destroy(dev, mode); 3318 mode = drm_gtf_mode_complex(dev, hsize, vsize, 3319 vrefresh_rate, 0, 0, 3320 drm_gtf2_m(drm_edid), 3321 drm_gtf2_2c(drm_edid), 3322 drm_gtf2_k(drm_edid), 3323 drm_gtf2_2j(drm_edid)); 3324 } 3325 3326 return mode; 3327 } 3328 3329 /* 3330 * Take the standard timing params (in this case width, aspect, and refresh) 3331 * and convert them into a real mode using CVT/GTF/DMT. 3332 */ 3333 static struct drm_display_mode *drm_mode_std(struct drm_connector *connector, 3334 const struct drm_edid *drm_edid, 3335 const struct std_timing *t) 3336 { 3337 struct drm_device *dev = connector->dev; 3338 struct drm_display_mode *m, *mode = NULL; 3339 int hsize, vsize; 3340 int vrefresh_rate; 3341 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 3342 >> EDID_TIMING_ASPECT_SHIFT; 3343 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 3344 >> EDID_TIMING_VFREQ_SHIFT; 3345 int timing_level = standard_timing_level(drm_edid); 3346 3347 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 3348 return NULL; 3349 3350 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 3351 hsize = t->hsize * 8 + 248; 3352 /* vrefresh_rate = vfreq + 60 */ 3353 vrefresh_rate = vfreq + 60; 3354 /* the vdisplay is calculated based on the aspect ratio */ 3355 if (aspect_ratio == 0) { 3356 if (drm_edid->edid->revision < 3) 3357 vsize = hsize; 3358 else 3359 vsize = (hsize * 10) / 16; 3360 } else if (aspect_ratio == 1) 3361 vsize = (hsize * 3) / 4; 3362 else if (aspect_ratio == 2) 3363 vsize = (hsize * 4) / 5; 3364 else 3365 vsize = (hsize * 9) / 16; 3366 3367 /* HDTV hack, part 1 */ 3368 if (vrefresh_rate == 60 && 3369 ((hsize == 1360 && vsize == 765) || 3370 (hsize == 1368 && vsize == 769))) { 3371 hsize = 1366; 3372 vsize = 768; 3373 } 3374 3375 /* 3376 * If this connector already has a mode for this size and refresh 3377 * rate (because it came from detailed or CVT info), use that 3378 * instead. This way we don't have to guess at interlace or 3379 * reduced blanking. 3380 */ 3381 list_for_each_entry(m, &connector->probed_modes, head) 3382 if (m->hdisplay == hsize && m->vdisplay == vsize && 3383 drm_mode_vrefresh(m) == vrefresh_rate) 3384 return NULL; 3385 3386 /* HDTV hack, part 2 */ 3387 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 3388 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 3389 false); 3390 if (!mode) 3391 return NULL; 3392 mode->hdisplay = 1366; 3393 mode->hsync_start = mode->hsync_start - 1; 3394 mode->hsync_end = mode->hsync_end - 1; 3395 return mode; 3396 } 3397 3398 /* check whether it can be found in default mode table */ 3399 if (drm_monitor_supports_rb(drm_edid)) { 3400 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 3401 true); 3402 if (mode) 3403 return mode; 3404 } 3405 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 3406 if (mode) 3407 return mode; 3408 3409 /* okay, generate it */ 3410 switch (timing_level) { 3411 case LEVEL_DMT: 3412 break; 3413 case LEVEL_GTF: 3414 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 3415 break; 3416 case LEVEL_GTF2: 3417 mode = drm_gtf2_mode(dev, drm_edid, hsize, vsize, vrefresh_rate); 3418 break; 3419 case LEVEL_CVT: 3420 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 3421 false); 3422 break; 3423 } 3424 return mode; 3425 } 3426 3427 /* 3428 * EDID is delightfully ambiguous about how interlaced modes are to be 3429 * encoded. Our internal representation is of frame height, but some 3430 * HDTV detailed timings are encoded as field height. 3431 * 3432 * The format list here is from CEA, in frame size. Technically we 3433 * should be checking refresh rate too. Whatever. 3434 */ 3435 static void 3436 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 3437 const struct detailed_pixel_timing *pt) 3438 { 3439 int i; 3440 static const struct { 3441 int w, h; 3442 } cea_interlaced[] = { 3443 { 1920, 1080 }, 3444 { 720, 480 }, 3445 { 1440, 480 }, 3446 { 2880, 480 }, 3447 { 720, 576 }, 3448 { 1440, 576 }, 3449 { 2880, 576 }, 3450 }; 3451 3452 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 3453 return; 3454 3455 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 3456 if ((mode->hdisplay == cea_interlaced[i].w) && 3457 (mode->vdisplay == cea_interlaced[i].h / 2)) { 3458 mode->vdisplay *= 2; 3459 mode->vsync_start *= 2; 3460 mode->vsync_end *= 2; 3461 mode->vtotal *= 2; 3462 mode->vtotal |= 1; 3463 } 3464 } 3465 3466 mode->flags |= DRM_MODE_FLAG_INTERLACE; 3467 } 3468 3469 /* 3470 * Create a new mode from an EDID detailed timing section. An EDID detailed 3471 * timing block contains enough info for us to create and return a new struct 3472 * drm_display_mode. 3473 */ 3474 static struct drm_display_mode *drm_mode_detailed(struct drm_connector *connector, 3475 const struct drm_edid *drm_edid, 3476 const struct detailed_timing *timing) 3477 { 3478 const struct drm_display_info *info = &connector->display_info; 3479 struct drm_device *dev = connector->dev; 3480 struct drm_display_mode *mode; 3481 const struct detailed_pixel_timing *pt = &timing->data.pixel_data; 3482 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 3483 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 3484 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 3485 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 3486 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 3487 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 3488 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 3489 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 3490 3491 /* ignore tiny modes */ 3492 if (hactive < 64 || vactive < 64) 3493 return NULL; 3494 3495 if (pt->misc & DRM_EDID_PT_STEREO) { 3496 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Stereo mode not supported\n", 3497 connector->base.id, connector->name); 3498 return NULL; 3499 } 3500 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 3501 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Composite sync not supported\n", 3502 connector->base.id, connector->name); 3503 } 3504 3505 /* it is incorrect if hsync/vsync width is zero */ 3506 if (!hsync_pulse_width || !vsync_pulse_width) { 3507 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Incorrect Detailed timing. Wrong Hsync/Vsync pulse width\n", 3508 connector->base.id, connector->name); 3509 return NULL; 3510 } 3511 3512 if (info->quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 3513 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 3514 if (!mode) 3515 return NULL; 3516 3517 goto set_size; 3518 } 3519 3520 mode = drm_mode_create(dev); 3521 if (!mode) 3522 return NULL; 3523 3524 if (info->quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 3525 mode->clock = 1088 * 10; 3526 else 3527 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 3528 3529 mode->hdisplay = hactive; 3530 mode->hsync_start = mode->hdisplay + hsync_offset; 3531 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 3532 mode->htotal = mode->hdisplay + hblank; 3533 3534 mode->vdisplay = vactive; 3535 mode->vsync_start = mode->vdisplay + vsync_offset; 3536 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 3537 mode->vtotal = mode->vdisplay + vblank; 3538 3539 /* Some EDIDs have bogus h/vsync_end values */ 3540 if (mode->hsync_end > mode->htotal) { 3541 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing hsync_end %d->%d\n", 3542 connector->base.id, connector->name, 3543 mode->hsync_end, mode->htotal); 3544 mode->hsync_end = mode->htotal; 3545 } 3546 if (mode->vsync_end > mode->vtotal) { 3547 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing vsync_end %d->%d\n", 3548 connector->base.id, connector->name, 3549 mode->vsync_end, mode->vtotal); 3550 mode->vsync_end = mode->vtotal; 3551 } 3552 3553 drm_mode_do_interlace_quirk(mode, pt); 3554 3555 if (info->quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 3556 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC; 3557 } else { 3558 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 3559 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 3560 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 3561 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 3562 } 3563 3564 set_size: 3565 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 3566 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 3567 3568 if (info->quirks & EDID_QUIRK_DETAILED_IN_CM) { 3569 mode->width_mm *= 10; 3570 mode->height_mm *= 10; 3571 } 3572 3573 if (info->quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 3574 mode->width_mm = drm_edid->edid->width_cm * 10; 3575 mode->height_mm = drm_edid->edid->height_cm * 10; 3576 } 3577 3578 mode->type = DRM_MODE_TYPE_DRIVER; 3579 drm_mode_set_name(mode); 3580 3581 return mode; 3582 } 3583 3584 static bool 3585 mode_in_hsync_range(const struct drm_display_mode *mode, 3586 const struct edid *edid, const u8 *t) 3587 { 3588 int hsync, hmin, hmax; 3589 3590 hmin = t[7]; 3591 if (edid->revision >= 4) 3592 hmin += ((t[4] & 0x04) ? 255 : 0); 3593 hmax = t[8]; 3594 if (edid->revision >= 4) 3595 hmax += ((t[4] & 0x08) ? 255 : 0); 3596 hsync = drm_mode_hsync(mode); 3597 3598 return (hsync <= hmax && hsync >= hmin); 3599 } 3600 3601 static bool 3602 mode_in_vsync_range(const struct drm_display_mode *mode, 3603 const struct edid *edid, const u8 *t) 3604 { 3605 int vsync, vmin, vmax; 3606 3607 vmin = t[5]; 3608 if (edid->revision >= 4) 3609 vmin += ((t[4] & 0x01) ? 255 : 0); 3610 vmax = t[6]; 3611 if (edid->revision >= 4) 3612 vmax += ((t[4] & 0x02) ? 255 : 0); 3613 vsync = drm_mode_vrefresh(mode); 3614 3615 return (vsync <= vmax && vsync >= vmin); 3616 } 3617 3618 static u32 3619 range_pixel_clock(const struct edid *edid, const u8 *t) 3620 { 3621 /* unspecified */ 3622 if (t[9] == 0 || t[9] == 255) 3623 return 0; 3624 3625 /* 1.4 with CVT support gives us real precision, yay */ 3626 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG) 3627 return (t[9] * 10000) - ((t[12] >> 2) * 250); 3628 3629 /* 1.3 is pathetic, so fuzz up a bit */ 3630 return t[9] * 10000 + 5001; 3631 } 3632 3633 static bool mode_in_range(const struct drm_display_mode *mode, 3634 const struct drm_edid *drm_edid, 3635 const struct detailed_timing *timing) 3636 { 3637 const struct edid *edid = drm_edid->edid; 3638 u32 max_clock; 3639 const u8 *t = (const u8 *)timing; 3640 3641 if (!mode_in_hsync_range(mode, edid, t)) 3642 return false; 3643 3644 if (!mode_in_vsync_range(mode, edid, t)) 3645 return false; 3646 3647 max_clock = range_pixel_clock(edid, t); 3648 if (max_clock) 3649 if (mode->clock > max_clock) 3650 return false; 3651 3652 /* 1.4 max horizontal check */ 3653 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG) 3654 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 3655 return false; 3656 3657 if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid)) 3658 return false; 3659 3660 return true; 3661 } 3662 3663 static bool valid_inferred_mode(const struct drm_connector *connector, 3664 const struct drm_display_mode *mode) 3665 { 3666 const struct drm_display_mode *m; 3667 bool ok = false; 3668 3669 list_for_each_entry(m, &connector->probed_modes, head) { 3670 if (mode->hdisplay == m->hdisplay && 3671 mode->vdisplay == m->vdisplay && 3672 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 3673 return false; /* duplicated */ 3674 if (mode->hdisplay <= m->hdisplay && 3675 mode->vdisplay <= m->vdisplay) 3676 ok = true; 3677 } 3678 return ok; 3679 } 3680 3681 static int drm_dmt_modes_for_range(struct drm_connector *connector, 3682 const struct drm_edid *drm_edid, 3683 const struct detailed_timing *timing) 3684 { 3685 int i, modes = 0; 3686 struct drm_display_mode *newmode; 3687 struct drm_device *dev = connector->dev; 3688 3689 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 3690 if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) && 3691 valid_inferred_mode(connector, drm_dmt_modes + i)) { 3692 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 3693 if (newmode) { 3694 drm_mode_probed_add(connector, newmode); 3695 modes++; 3696 } 3697 } 3698 } 3699 3700 return modes; 3701 } 3702 3703 /* fix up 1366x768 mode from 1368x768; 3704 * GFT/CVT can't express 1366 width which isn't dividable by 8 3705 */ 3706 void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 3707 { 3708 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 3709 mode->hdisplay = 1366; 3710 mode->hsync_start--; 3711 mode->hsync_end--; 3712 drm_mode_set_name(mode); 3713 } 3714 } 3715 3716 static int drm_gtf_modes_for_range(struct drm_connector *connector, 3717 const struct drm_edid *drm_edid, 3718 const struct detailed_timing *timing) 3719 { 3720 int i, modes = 0; 3721 struct drm_display_mode *newmode; 3722 struct drm_device *dev = connector->dev; 3723 3724 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3725 const struct minimode *m = &extra_modes[i]; 3726 3727 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 3728 if (!newmode) 3729 return modes; 3730 3731 drm_mode_fixup_1366x768(newmode); 3732 if (!mode_in_range(newmode, drm_edid, timing) || 3733 !valid_inferred_mode(connector, newmode)) { 3734 drm_mode_destroy(dev, newmode); 3735 continue; 3736 } 3737 3738 drm_mode_probed_add(connector, newmode); 3739 modes++; 3740 } 3741 3742 return modes; 3743 } 3744 3745 static int drm_gtf2_modes_for_range(struct drm_connector *connector, 3746 const struct drm_edid *drm_edid, 3747 const struct detailed_timing *timing) 3748 { 3749 int i, modes = 0; 3750 struct drm_display_mode *newmode; 3751 struct drm_device *dev = connector->dev; 3752 3753 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3754 const struct minimode *m = &extra_modes[i]; 3755 3756 newmode = drm_gtf2_mode(dev, drm_edid, m->w, m->h, m->r); 3757 if (!newmode) 3758 return modes; 3759 3760 drm_mode_fixup_1366x768(newmode); 3761 if (!mode_in_range(newmode, drm_edid, timing) || 3762 !valid_inferred_mode(connector, newmode)) { 3763 drm_mode_destroy(dev, newmode); 3764 continue; 3765 } 3766 3767 drm_mode_probed_add(connector, newmode); 3768 modes++; 3769 } 3770 3771 return modes; 3772 } 3773 3774 static int drm_cvt_modes_for_range(struct drm_connector *connector, 3775 const struct drm_edid *drm_edid, 3776 const struct detailed_timing *timing) 3777 { 3778 int i, modes = 0; 3779 struct drm_display_mode *newmode; 3780 struct drm_device *dev = connector->dev; 3781 bool rb = drm_monitor_supports_rb(drm_edid); 3782 3783 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3784 const struct minimode *m = &extra_modes[i]; 3785 3786 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 3787 if (!newmode) 3788 return modes; 3789 3790 drm_mode_fixup_1366x768(newmode); 3791 if (!mode_in_range(newmode, drm_edid, timing) || 3792 !valid_inferred_mode(connector, newmode)) { 3793 drm_mode_destroy(dev, newmode); 3794 continue; 3795 } 3796 3797 drm_mode_probed_add(connector, newmode); 3798 modes++; 3799 } 3800 3801 return modes; 3802 } 3803 3804 static void 3805 do_inferred_modes(const struct detailed_timing *timing, void *c) 3806 { 3807 struct detailed_mode_closure *closure = c; 3808 const struct detailed_non_pixel *data = &timing->data.other_data; 3809 const struct detailed_data_monitor_range *range = &data->data.range; 3810 3811 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE)) 3812 return; 3813 3814 closure->modes += drm_dmt_modes_for_range(closure->connector, 3815 closure->drm_edid, 3816 timing); 3817 3818 if (closure->drm_edid->edid->revision < 2) 3819 return; /* GTF not defined yet */ 3820 3821 switch (range->flags) { 3822 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG: 3823 closure->modes += drm_gtf2_modes_for_range(closure->connector, 3824 closure->drm_edid, 3825 timing); 3826 break; 3827 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG: 3828 closure->modes += drm_gtf_modes_for_range(closure->connector, 3829 closure->drm_edid, 3830 timing); 3831 break; 3832 case DRM_EDID_CVT_SUPPORT_FLAG: 3833 if (closure->drm_edid->edid->revision < 4) 3834 break; 3835 3836 closure->modes += drm_cvt_modes_for_range(closure->connector, 3837 closure->drm_edid, 3838 timing); 3839 break; 3840 case DRM_EDID_RANGE_LIMITS_ONLY_FLAG: 3841 default: 3842 break; 3843 } 3844 } 3845 3846 static int add_inferred_modes(struct drm_connector *connector, 3847 const struct drm_edid *drm_edid) 3848 { 3849 struct detailed_mode_closure closure = { 3850 .connector = connector, 3851 .drm_edid = drm_edid, 3852 }; 3853 3854 if (drm_edid->edid->revision >= 1) 3855 drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure); 3856 3857 return closure.modes; 3858 } 3859 3860 static int 3861 drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing) 3862 { 3863 int i, j, m, modes = 0; 3864 struct drm_display_mode *mode; 3865 const u8 *est = ((const u8 *)timing) + 6; 3866 3867 for (i = 0; i < 6; i++) { 3868 for (j = 7; j >= 0; j--) { 3869 m = (i * 8) + (7 - j); 3870 if (m >= ARRAY_SIZE(est3_modes)) 3871 break; 3872 if (est[i] & (1 << j)) { 3873 mode = drm_mode_find_dmt(connector->dev, 3874 est3_modes[m].w, 3875 est3_modes[m].h, 3876 est3_modes[m].r, 3877 est3_modes[m].rb); 3878 if (mode) { 3879 drm_mode_probed_add(connector, mode); 3880 modes++; 3881 } 3882 } 3883 } 3884 } 3885 3886 return modes; 3887 } 3888 3889 static void 3890 do_established_modes(const struct detailed_timing *timing, void *c) 3891 { 3892 struct detailed_mode_closure *closure = c; 3893 3894 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS)) 3895 return; 3896 3897 closure->modes += drm_est3_modes(closure->connector, timing); 3898 } 3899 3900 /* 3901 * Get established modes from EDID and add them. Each EDID block contains a 3902 * bitmap of the supported "established modes" list (defined above). Tease them 3903 * out and add them to the global modes list. 3904 */ 3905 static int add_established_modes(struct drm_connector *connector, 3906 const struct drm_edid *drm_edid) 3907 { 3908 struct drm_device *dev = connector->dev; 3909 const struct edid *edid = drm_edid->edid; 3910 unsigned long est_bits = edid->established_timings.t1 | 3911 (edid->established_timings.t2 << 8) | 3912 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 3913 int i, modes = 0; 3914 struct detailed_mode_closure closure = { 3915 .connector = connector, 3916 .drm_edid = drm_edid, 3917 }; 3918 3919 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 3920 if (est_bits & (1<<i)) { 3921 struct drm_display_mode *newmode; 3922 3923 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 3924 if (newmode) { 3925 drm_mode_probed_add(connector, newmode); 3926 modes++; 3927 } 3928 } 3929 } 3930 3931 if (edid->revision >= 1) 3932 drm_for_each_detailed_block(drm_edid, do_established_modes, 3933 &closure); 3934 3935 return modes + closure.modes; 3936 } 3937 3938 static void 3939 do_standard_modes(const struct detailed_timing *timing, void *c) 3940 { 3941 struct detailed_mode_closure *closure = c; 3942 const struct detailed_non_pixel *data = &timing->data.other_data; 3943 struct drm_connector *connector = closure->connector; 3944 int i; 3945 3946 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES)) 3947 return; 3948 3949 for (i = 0; i < 6; i++) { 3950 const struct std_timing *std = &data->data.timings[i]; 3951 struct drm_display_mode *newmode; 3952 3953 newmode = drm_mode_std(connector, closure->drm_edid, std); 3954 if (newmode) { 3955 drm_mode_probed_add(connector, newmode); 3956 closure->modes++; 3957 } 3958 } 3959 } 3960 3961 /* 3962 * Get standard modes from EDID and add them. Standard modes can be calculated 3963 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and 3964 * add them to the list. 3965 */ 3966 static int add_standard_modes(struct drm_connector *connector, 3967 const struct drm_edid *drm_edid) 3968 { 3969 int i, modes = 0; 3970 struct detailed_mode_closure closure = { 3971 .connector = connector, 3972 .drm_edid = drm_edid, 3973 }; 3974 3975 for (i = 0; i < EDID_STD_TIMINGS; i++) { 3976 struct drm_display_mode *newmode; 3977 3978 newmode = drm_mode_std(connector, drm_edid, 3979 &drm_edid->edid->standard_timings[i]); 3980 if (newmode) { 3981 drm_mode_probed_add(connector, newmode); 3982 modes++; 3983 } 3984 } 3985 3986 if (drm_edid->edid->revision >= 1) 3987 drm_for_each_detailed_block(drm_edid, do_standard_modes, 3988 &closure); 3989 3990 /* XXX should also look for standard codes in VTB blocks */ 3991 3992 return modes + closure.modes; 3993 } 3994 3995 static int drm_cvt_modes(struct drm_connector *connector, 3996 const struct detailed_timing *timing) 3997 { 3998 int i, j, modes = 0; 3999 struct drm_display_mode *newmode; 4000 struct drm_device *dev = connector->dev; 4001 const struct cvt_timing *cvt; 4002 static const int rates[] = { 60, 85, 75, 60, 50 }; 4003 const u8 empty[3] = { 0, 0, 0 }; 4004 4005 for (i = 0; i < 4; i++) { 4006 int width, height; 4007 4008 cvt = &(timing->data.other_data.data.cvt[i]); 4009 4010 if (!memcmp(cvt->code, empty, 3)) 4011 continue; 4012 4013 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 4014 switch (cvt->code[1] & 0x0c) { 4015 /* default - because compiler doesn't see that we've enumerated all cases */ 4016 default: 4017 case 0x00: 4018 width = height * 4 / 3; 4019 break; 4020 case 0x04: 4021 width = height * 16 / 9; 4022 break; 4023 case 0x08: 4024 width = height * 16 / 10; 4025 break; 4026 case 0x0c: 4027 width = height * 15 / 9; 4028 break; 4029 } 4030 4031 for (j = 1; j < 5; j++) { 4032 if (cvt->code[2] & (1 << j)) { 4033 newmode = drm_cvt_mode(dev, width, height, 4034 rates[j], j == 0, 4035 false, false); 4036 if (newmode) { 4037 drm_mode_probed_add(connector, newmode); 4038 modes++; 4039 } 4040 } 4041 } 4042 } 4043 4044 return modes; 4045 } 4046 4047 static void 4048 do_cvt_mode(const struct detailed_timing *timing, void *c) 4049 { 4050 struct detailed_mode_closure *closure = c; 4051 4052 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE)) 4053 return; 4054 4055 closure->modes += drm_cvt_modes(closure->connector, timing); 4056 } 4057 4058 static int 4059 add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid) 4060 { 4061 struct detailed_mode_closure closure = { 4062 .connector = connector, 4063 .drm_edid = drm_edid, 4064 }; 4065 4066 if (drm_edid->edid->revision >= 3) 4067 drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure); 4068 4069 /* XXX should also look for CVT codes in VTB blocks */ 4070 4071 return closure.modes; 4072 } 4073 4074 static void fixup_detailed_cea_mode_clock(struct drm_connector *connector, 4075 struct drm_display_mode *mode); 4076 4077 static void 4078 do_detailed_mode(const struct detailed_timing *timing, void *c) 4079 { 4080 struct detailed_mode_closure *closure = c; 4081 struct drm_display_mode *newmode; 4082 4083 if (!is_detailed_timing_descriptor(timing)) 4084 return; 4085 4086 newmode = drm_mode_detailed(closure->connector, 4087 closure->drm_edid, timing); 4088 if (!newmode) 4089 return; 4090 4091 if (closure->preferred) 4092 newmode->type |= DRM_MODE_TYPE_PREFERRED; 4093 4094 /* 4095 * Detailed modes are limited to 10kHz pixel clock resolution, 4096 * so fix up anything that looks like CEA/HDMI mode, but the clock 4097 * is just slightly off. 4098 */ 4099 fixup_detailed_cea_mode_clock(closure->connector, newmode); 4100 4101 drm_mode_probed_add(closure->connector, newmode); 4102 closure->modes++; 4103 closure->preferred = false; 4104 } 4105 4106 /* 4107 * add_detailed_modes - Add modes from detailed timings 4108 * @connector: attached connector 4109 * @drm_edid: EDID block to scan 4110 */ 4111 static int add_detailed_modes(struct drm_connector *connector, 4112 const struct drm_edid *drm_edid) 4113 { 4114 struct detailed_mode_closure closure = { 4115 .connector = connector, 4116 .drm_edid = drm_edid, 4117 }; 4118 4119 if (drm_edid->edid->revision >= 4) 4120 closure.preferred = true; /* first detailed timing is always preferred */ 4121 else 4122 closure.preferred = 4123 drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING; 4124 4125 drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure); 4126 4127 return closure.modes; 4128 } 4129 4130 /* CTA-861-H Table 60 - CTA Tag Codes */ 4131 #define CTA_DB_AUDIO 1 4132 #define CTA_DB_VIDEO 2 4133 #define CTA_DB_VENDOR 3 4134 #define CTA_DB_SPEAKER 4 4135 #define CTA_DB_EXTENDED_TAG 7 4136 4137 /* CTA-861-H Table 62 - CTA Extended Tag Codes */ 4138 #define CTA_EXT_DB_VIDEO_CAP 0 4139 #define CTA_EXT_DB_VENDOR 1 4140 #define CTA_EXT_DB_HDR_STATIC_METADATA 6 4141 #define CTA_EXT_DB_420_VIDEO_DATA 14 4142 #define CTA_EXT_DB_420_VIDEO_CAP_MAP 15 4143 #define CTA_EXT_DB_HF_EEODB 0x78 4144 #define CTA_EXT_DB_HF_SCDB 0x79 4145 4146 #define EDID_BASIC_AUDIO (1 << 6) 4147 #define EDID_CEA_YCRCB444 (1 << 5) 4148 #define EDID_CEA_YCRCB422 (1 << 4) 4149 #define EDID_CEA_VCDB_QS (1 << 6) 4150 4151 /* 4152 * Search EDID for CEA extension block. 4153 * 4154 * FIXME: Prefer not returning pointers to raw EDID data. 4155 */ 4156 const u8 *drm_edid_find_extension(const struct drm_edid *drm_edid, 4157 int ext_id, int *ext_index) 4158 { 4159 const u8 *edid_ext = NULL; 4160 int i; 4161 4162 /* No EDID or EDID extensions */ 4163 if (!drm_edid || !drm_edid_extension_block_count(drm_edid)) 4164 return NULL; 4165 4166 /* Find CEA extension */ 4167 for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) { 4168 edid_ext = drm_edid_extension_block_data(drm_edid, i); 4169 if (edid_block_tag(edid_ext) == ext_id) 4170 break; 4171 } 4172 4173 if (i >= drm_edid_extension_block_count(drm_edid)) 4174 return NULL; 4175 4176 *ext_index = i + 1; 4177 4178 return edid_ext; 4179 } 4180 4181 /* Return true if the EDID has a CTA extension or a DisplayID CTA data block */ 4182 static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid) 4183 { 4184 const struct displayid_block *block; 4185 struct displayid_iter iter; 4186 struct drm_edid_iter edid_iter; 4187 const u8 *ext; 4188 bool found = false; 4189 4190 /* Look for a top level CEA extension block */ 4191 drm_edid_iter_begin(drm_edid, &edid_iter); 4192 drm_edid_iter_for_each(ext, &edid_iter) { 4193 if (ext[0] == CEA_EXT) { 4194 found = true; 4195 break; 4196 } 4197 } 4198 drm_edid_iter_end(&edid_iter); 4199 4200 if (found) 4201 return true; 4202 4203 /* CEA blocks can also be found embedded in a DisplayID block */ 4204 displayid_iter_edid_begin(drm_edid, &iter); 4205 displayid_iter_for_each(block, &iter) { 4206 if (block->tag == DATA_BLOCK_CTA) { 4207 found = true; 4208 break; 4209 } 4210 } 4211 displayid_iter_end(&iter); 4212 4213 return found; 4214 } 4215 4216 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic) 4217 { 4218 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127); 4219 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219); 4220 4221 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1)) 4222 return &edid_cea_modes_1[vic - 1]; 4223 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193)) 4224 return &edid_cea_modes_193[vic - 193]; 4225 return NULL; 4226 } 4227 4228 static u8 cea_num_vics(void) 4229 { 4230 return 193 + ARRAY_SIZE(edid_cea_modes_193); 4231 } 4232 4233 static u8 cea_next_vic(u8 vic) 4234 { 4235 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1)) 4236 vic = 193; 4237 return vic; 4238 } 4239 4240 /* 4241 * Calculate the alternate clock for the CEA mode 4242 * (60Hz vs. 59.94Hz etc.) 4243 */ 4244 static unsigned int 4245 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 4246 { 4247 unsigned int clock = cea_mode->clock; 4248 4249 if (drm_mode_vrefresh(cea_mode) % 6 != 0) 4250 return clock; 4251 4252 /* 4253 * edid_cea_modes contains the 59.94Hz 4254 * variant for 240 and 480 line modes, 4255 * and the 60Hz variant otherwise. 4256 */ 4257 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 4258 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 4259 else 4260 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 4261 4262 return clock; 4263 } 4264 4265 static bool 4266 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 4267 { 4268 /* 4269 * For certain VICs the spec allows the vertical 4270 * front porch to vary by one or two lines. 4271 * 4272 * cea_modes[] stores the variant with the shortest 4273 * vertical front porch. We can adjust the mode to 4274 * get the other variants by simply increasing the 4275 * vertical front porch length. 4276 */ 4277 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 || 4278 cea_mode_for_vic(9)->vtotal != 262 || 4279 cea_mode_for_vic(12)->vtotal != 262 || 4280 cea_mode_for_vic(13)->vtotal != 262 || 4281 cea_mode_for_vic(23)->vtotal != 312 || 4282 cea_mode_for_vic(24)->vtotal != 312 || 4283 cea_mode_for_vic(27)->vtotal != 312 || 4284 cea_mode_for_vic(28)->vtotal != 312); 4285 4286 if (((vic == 8 || vic == 9 || 4287 vic == 12 || vic == 13) && mode->vtotal < 263) || 4288 ((vic == 23 || vic == 24 || 4289 vic == 27 || vic == 28) && mode->vtotal < 314)) { 4290 mode->vsync_start++; 4291 mode->vsync_end++; 4292 mode->vtotal++; 4293 4294 return true; 4295 } 4296 4297 return false; 4298 } 4299 4300 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 4301 unsigned int clock_tolerance) 4302 { 4303 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4304 u8 vic; 4305 4306 if (!to_match->clock) 4307 return 0; 4308 4309 if (to_match->picture_aspect_ratio) 4310 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4311 4312 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 4313 struct drm_display_mode cea_mode; 4314 unsigned int clock1, clock2; 4315 4316 drm_mode_init(&cea_mode, cea_mode_for_vic(vic)); 4317 4318 /* Check both 60Hz and 59.94Hz */ 4319 clock1 = cea_mode.clock; 4320 clock2 = cea_mode_alternate_clock(&cea_mode); 4321 4322 if (abs(to_match->clock - clock1) > clock_tolerance && 4323 abs(to_match->clock - clock2) > clock_tolerance) 4324 continue; 4325 4326 do { 4327 if (drm_mode_match(to_match, &cea_mode, match_flags)) 4328 return vic; 4329 } while (cea_mode_alternate_timings(vic, &cea_mode)); 4330 } 4331 4332 return 0; 4333 } 4334 4335 /** 4336 * drm_match_cea_mode - look for a CEA mode matching given mode 4337 * @to_match: display mode 4338 * 4339 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 4340 * mode. 4341 */ 4342 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 4343 { 4344 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4345 u8 vic; 4346 4347 if (!to_match->clock) 4348 return 0; 4349 4350 if (to_match->picture_aspect_ratio) 4351 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4352 4353 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 4354 struct drm_display_mode cea_mode; 4355 unsigned int clock1, clock2; 4356 4357 drm_mode_init(&cea_mode, cea_mode_for_vic(vic)); 4358 4359 /* Check both 60Hz and 59.94Hz */ 4360 clock1 = cea_mode.clock; 4361 clock2 = cea_mode_alternate_clock(&cea_mode); 4362 4363 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 4364 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 4365 continue; 4366 4367 do { 4368 if (drm_mode_match(to_match, &cea_mode, match_flags)) 4369 return vic; 4370 } while (cea_mode_alternate_timings(vic, &cea_mode)); 4371 } 4372 4373 return 0; 4374 } 4375 EXPORT_SYMBOL(drm_match_cea_mode); 4376 4377 static bool drm_valid_cea_vic(u8 vic) 4378 { 4379 return cea_mode_for_vic(vic) != NULL; 4380 } 4381 4382 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 4383 { 4384 const struct drm_display_mode *mode = cea_mode_for_vic(video_code); 4385 4386 if (mode) 4387 return mode->picture_aspect_ratio; 4388 4389 return HDMI_PICTURE_ASPECT_NONE; 4390 } 4391 4392 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code) 4393 { 4394 return edid_4k_modes[video_code].picture_aspect_ratio; 4395 } 4396 4397 /* 4398 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 4399 * specific block). 4400 */ 4401 static unsigned int 4402 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 4403 { 4404 return cea_mode_alternate_clock(hdmi_mode); 4405 } 4406 4407 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 4408 unsigned int clock_tolerance) 4409 { 4410 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4411 u8 vic; 4412 4413 if (!to_match->clock) 4414 return 0; 4415 4416 if (to_match->picture_aspect_ratio) 4417 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4418 4419 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4420 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4421 unsigned int clock1, clock2; 4422 4423 /* Make sure to also match alternate clocks */ 4424 clock1 = hdmi_mode->clock; 4425 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4426 4427 if (abs(to_match->clock - clock1) > clock_tolerance && 4428 abs(to_match->clock - clock2) > clock_tolerance) 4429 continue; 4430 4431 if (drm_mode_match(to_match, hdmi_mode, match_flags)) 4432 return vic; 4433 } 4434 4435 return 0; 4436 } 4437 4438 /* 4439 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 4440 * @to_match: display mode 4441 * 4442 * An HDMI mode is one defined in the HDMI vendor specific block. 4443 * 4444 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 4445 */ 4446 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 4447 { 4448 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4449 u8 vic; 4450 4451 if (!to_match->clock) 4452 return 0; 4453 4454 if (to_match->picture_aspect_ratio) 4455 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4456 4457 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4458 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4459 unsigned int clock1, clock2; 4460 4461 /* Make sure to also match alternate clocks */ 4462 clock1 = hdmi_mode->clock; 4463 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4464 4465 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 4466 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 4467 drm_mode_match(to_match, hdmi_mode, match_flags)) 4468 return vic; 4469 } 4470 return 0; 4471 } 4472 4473 static bool drm_valid_hdmi_vic(u8 vic) 4474 { 4475 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 4476 } 4477 4478 static int add_alternate_cea_modes(struct drm_connector *connector, 4479 const struct drm_edid *drm_edid) 4480 { 4481 struct drm_device *dev = connector->dev; 4482 struct drm_display_mode *mode, *tmp; 4483 LIST_HEAD(list); 4484 int modes = 0; 4485 4486 /* Don't add CTA modes if the CTA extension block is missing */ 4487 if (!drm_edid_has_cta_extension(drm_edid)) 4488 return 0; 4489 4490 /* 4491 * Go through all probed modes and create a new mode 4492 * with the alternate clock for certain CEA modes. 4493 */ 4494 list_for_each_entry(mode, &connector->probed_modes, head) { 4495 const struct drm_display_mode *cea_mode = NULL; 4496 struct drm_display_mode *newmode; 4497 u8 vic = drm_match_cea_mode(mode); 4498 unsigned int clock1, clock2; 4499 4500 if (drm_valid_cea_vic(vic)) { 4501 cea_mode = cea_mode_for_vic(vic); 4502 clock2 = cea_mode_alternate_clock(cea_mode); 4503 } else { 4504 vic = drm_match_hdmi_mode(mode); 4505 if (drm_valid_hdmi_vic(vic)) { 4506 cea_mode = &edid_4k_modes[vic]; 4507 clock2 = hdmi_mode_alternate_clock(cea_mode); 4508 } 4509 } 4510 4511 if (!cea_mode) 4512 continue; 4513 4514 clock1 = cea_mode->clock; 4515 4516 if (clock1 == clock2) 4517 continue; 4518 4519 if (mode->clock != clock1 && mode->clock != clock2) 4520 continue; 4521 4522 newmode = drm_mode_duplicate(dev, cea_mode); 4523 if (!newmode) 4524 continue; 4525 4526 /* Carry over the stereo flags */ 4527 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 4528 4529 /* 4530 * The current mode could be either variant. Make 4531 * sure to pick the "other" clock for the new mode. 4532 */ 4533 if (mode->clock != clock1) 4534 newmode->clock = clock1; 4535 else 4536 newmode->clock = clock2; 4537 4538 list_add_tail(&newmode->head, &list); 4539 } 4540 4541 list_for_each_entry_safe(mode, tmp, &list, head) { 4542 list_del(&mode->head); 4543 drm_mode_probed_add(connector, mode); 4544 modes++; 4545 } 4546 4547 return modes; 4548 } 4549 4550 static u8 svd_to_vic(u8 svd) 4551 { 4552 /* 0-6 bit vic, 7th bit native mode indicator */ 4553 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 4554 return svd & 127; 4555 4556 return svd; 4557 } 4558 4559 /* 4560 * Return a display mode for the 0-based vic_index'th VIC across all CTA VDBs in 4561 * the EDID, or NULL on errors. 4562 */ 4563 static struct drm_display_mode * 4564 drm_display_mode_from_vic_index(struct drm_connector *connector, int vic_index) 4565 { 4566 const struct drm_display_info *info = &connector->display_info; 4567 struct drm_device *dev = connector->dev; 4568 4569 if (!info->vics || vic_index >= info->vics_len || !info->vics[vic_index]) 4570 return NULL; 4571 4572 return drm_display_mode_from_cea_vic(dev, info->vics[vic_index]); 4573 } 4574 4575 /* 4576 * do_y420vdb_modes - Parse YCBCR 420 only modes 4577 * @connector: connector corresponding to the HDMI sink 4578 * @svds: start of the data block of CEA YCBCR 420 VDB 4579 * @len: length of the CEA YCBCR 420 VDB 4580 * 4581 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 4582 * which contains modes which can be supported in YCBCR 420 4583 * output format only. 4584 */ 4585 static int do_y420vdb_modes(struct drm_connector *connector, 4586 const u8 *svds, u8 svds_len) 4587 { 4588 struct drm_device *dev = connector->dev; 4589 int modes = 0, i; 4590 4591 for (i = 0; i < svds_len; i++) { 4592 u8 vic = svd_to_vic(svds[i]); 4593 struct drm_display_mode *newmode; 4594 4595 if (!drm_valid_cea_vic(vic)) 4596 continue; 4597 4598 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 4599 if (!newmode) 4600 break; 4601 drm_mode_probed_add(connector, newmode); 4602 modes++; 4603 } 4604 4605 return modes; 4606 } 4607 4608 /** 4609 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC 4610 * @dev: DRM device 4611 * @video_code: CEA VIC of the mode 4612 * 4613 * Creates a new mode matching the specified CEA VIC. 4614 * 4615 * Returns: A new drm_display_mode on success or NULL on failure 4616 */ 4617 struct drm_display_mode * 4618 drm_display_mode_from_cea_vic(struct drm_device *dev, 4619 u8 video_code) 4620 { 4621 const struct drm_display_mode *cea_mode; 4622 struct drm_display_mode *newmode; 4623 4624 cea_mode = cea_mode_for_vic(video_code); 4625 if (!cea_mode) 4626 return NULL; 4627 4628 newmode = drm_mode_duplicate(dev, cea_mode); 4629 if (!newmode) 4630 return NULL; 4631 4632 return newmode; 4633 } 4634 EXPORT_SYMBOL(drm_display_mode_from_cea_vic); 4635 4636 /* Add modes based on VICs parsed in parse_cta_vdb() */ 4637 static int add_cta_vdb_modes(struct drm_connector *connector) 4638 { 4639 const struct drm_display_info *info = &connector->display_info; 4640 int i, modes = 0; 4641 4642 if (!info->vics) 4643 return 0; 4644 4645 for (i = 0; i < info->vics_len; i++) { 4646 struct drm_display_mode *mode; 4647 4648 mode = drm_display_mode_from_vic_index(connector, i); 4649 if (mode) { 4650 drm_mode_probed_add(connector, mode); 4651 modes++; 4652 } 4653 } 4654 4655 return modes; 4656 } 4657 4658 struct stereo_mandatory_mode { 4659 int width, height, vrefresh; 4660 unsigned int flags; 4661 }; 4662 4663 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 4664 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4665 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 4666 { 1920, 1080, 50, 4667 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 4668 { 1920, 1080, 60, 4669 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 4670 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4671 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 4672 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4673 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 4674 }; 4675 4676 static bool 4677 stereo_match_mandatory(const struct drm_display_mode *mode, 4678 const struct stereo_mandatory_mode *stereo_mode) 4679 { 4680 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 4681 4682 return mode->hdisplay == stereo_mode->width && 4683 mode->vdisplay == stereo_mode->height && 4684 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 4685 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 4686 } 4687 4688 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 4689 { 4690 struct drm_device *dev = connector->dev; 4691 const struct drm_display_mode *mode; 4692 struct list_head stereo_modes; 4693 int modes = 0, i; 4694 4695 INIT_LIST_HEAD(&stereo_modes); 4696 4697 list_for_each_entry(mode, &connector->probed_modes, head) { 4698 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 4699 const struct stereo_mandatory_mode *mandatory; 4700 struct drm_display_mode *new_mode; 4701 4702 if (!stereo_match_mandatory(mode, 4703 &stereo_mandatory_modes[i])) 4704 continue; 4705 4706 mandatory = &stereo_mandatory_modes[i]; 4707 new_mode = drm_mode_duplicate(dev, mode); 4708 if (!new_mode) 4709 continue; 4710 4711 new_mode->flags |= mandatory->flags; 4712 list_add_tail(&new_mode->head, &stereo_modes); 4713 modes++; 4714 } 4715 } 4716 4717 list_splice_tail(&stereo_modes, &connector->probed_modes); 4718 4719 return modes; 4720 } 4721 4722 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 4723 { 4724 struct drm_device *dev = connector->dev; 4725 struct drm_display_mode *newmode; 4726 4727 if (!drm_valid_hdmi_vic(vic)) { 4728 drm_err(connector->dev, "[CONNECTOR:%d:%s] Unknown HDMI VIC: %d\n", 4729 connector->base.id, connector->name, vic); 4730 return 0; 4731 } 4732 4733 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 4734 if (!newmode) 4735 return 0; 4736 4737 drm_mode_probed_add(connector, newmode); 4738 4739 return 1; 4740 } 4741 4742 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 4743 int vic_index) 4744 { 4745 struct drm_display_mode *newmode; 4746 int modes = 0; 4747 4748 if (structure & (1 << 0)) { 4749 newmode = drm_display_mode_from_vic_index(connector, vic_index); 4750 if (newmode) { 4751 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 4752 drm_mode_probed_add(connector, newmode); 4753 modes++; 4754 } 4755 } 4756 if (structure & (1 << 6)) { 4757 newmode = drm_display_mode_from_vic_index(connector, vic_index); 4758 if (newmode) { 4759 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 4760 drm_mode_probed_add(connector, newmode); 4761 modes++; 4762 } 4763 } 4764 if (structure & (1 << 8)) { 4765 newmode = drm_display_mode_from_vic_index(connector, vic_index); 4766 if (newmode) { 4767 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4768 drm_mode_probed_add(connector, newmode); 4769 modes++; 4770 } 4771 } 4772 4773 return modes; 4774 } 4775 4776 static bool hdmi_vsdb_latency_present(const u8 *db) 4777 { 4778 return db[8] & BIT(7); 4779 } 4780 4781 static bool hdmi_vsdb_i_latency_present(const u8 *db) 4782 { 4783 return hdmi_vsdb_latency_present(db) && db[8] & BIT(6); 4784 } 4785 4786 static int hdmi_vsdb_latency_length(const u8 *db) 4787 { 4788 if (hdmi_vsdb_i_latency_present(db)) 4789 return 4; 4790 else if (hdmi_vsdb_latency_present(db)) 4791 return 2; 4792 else 4793 return 0; 4794 } 4795 4796 /* 4797 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 4798 * @connector: connector corresponding to the HDMI sink 4799 * @db: start of the CEA vendor specific block 4800 * @len: length of the CEA block payload, ie. one can access up to db[len] 4801 * 4802 * Parses the HDMI VSDB looking for modes to add to @connector. This function 4803 * also adds the stereo 3d modes when applicable. 4804 */ 4805 static int 4806 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len) 4807 { 4808 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 4809 u8 vic_len, hdmi_3d_len = 0; 4810 u16 mask; 4811 u16 structure_all; 4812 4813 if (len < 8) 4814 goto out; 4815 4816 /* no HDMI_Video_Present */ 4817 if (!(db[8] & (1 << 5))) 4818 goto out; 4819 4820 offset += hdmi_vsdb_latency_length(db); 4821 4822 /* the declared length is not long enough for the 2 first bytes 4823 * of additional video format capabilities */ 4824 if (len < (8 + offset + 2)) 4825 goto out; 4826 4827 /* 3D_Present */ 4828 offset++; 4829 if (db[8 + offset] & (1 << 7)) { 4830 modes += add_hdmi_mandatory_stereo_modes(connector); 4831 4832 /* 3D_Multi_present */ 4833 multi_present = (db[8 + offset] & 0x60) >> 5; 4834 } 4835 4836 offset++; 4837 vic_len = db[8 + offset] >> 5; 4838 hdmi_3d_len = db[8 + offset] & 0x1f; 4839 4840 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 4841 u8 vic; 4842 4843 vic = db[9 + offset + i]; 4844 modes += add_hdmi_mode(connector, vic); 4845 } 4846 offset += 1 + vic_len; 4847 4848 if (multi_present == 1) 4849 multi_len = 2; 4850 else if (multi_present == 2) 4851 multi_len = 4; 4852 else 4853 multi_len = 0; 4854 4855 if (len < (8 + offset + hdmi_3d_len - 1)) 4856 goto out; 4857 4858 if (hdmi_3d_len < multi_len) 4859 goto out; 4860 4861 if (multi_present == 1 || multi_present == 2) { 4862 /* 3D_Structure_ALL */ 4863 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 4864 4865 /* check if 3D_MASK is present */ 4866 if (multi_present == 2) 4867 mask = (db[10 + offset] << 8) | db[11 + offset]; 4868 else 4869 mask = 0xffff; 4870 4871 for (i = 0; i < 16; i++) { 4872 if (mask & (1 << i)) 4873 modes += add_3d_struct_modes(connector, 4874 structure_all, i); 4875 } 4876 } 4877 4878 offset += multi_len; 4879 4880 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 4881 int vic_index; 4882 struct drm_display_mode *newmode = NULL; 4883 unsigned int newflag = 0; 4884 bool detail_present; 4885 4886 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 4887 4888 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 4889 break; 4890 4891 /* 2D_VIC_order_X */ 4892 vic_index = db[8 + offset + i] >> 4; 4893 4894 /* 3D_Structure_X */ 4895 switch (db[8 + offset + i] & 0x0f) { 4896 case 0: 4897 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 4898 break; 4899 case 6: 4900 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 4901 break; 4902 case 8: 4903 /* 3D_Detail_X */ 4904 if ((db[9 + offset + i] >> 4) == 1) 4905 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4906 break; 4907 } 4908 4909 if (newflag != 0) { 4910 newmode = drm_display_mode_from_vic_index(connector, 4911 vic_index); 4912 4913 if (newmode) { 4914 newmode->flags |= newflag; 4915 drm_mode_probed_add(connector, newmode); 4916 modes++; 4917 } 4918 } 4919 4920 if (detail_present) 4921 i++; 4922 } 4923 4924 out: 4925 return modes; 4926 } 4927 4928 static int 4929 cea_revision(const u8 *cea) 4930 { 4931 /* 4932 * FIXME is this correct for the DispID variant? 4933 * The DispID spec doesn't really specify whether 4934 * this is the revision of the CEA extension or 4935 * the DispID CEA data block. And the only value 4936 * given as an example is 0. 4937 */ 4938 return cea[1]; 4939 } 4940 4941 /* 4942 * CTA Data Block iterator. 4943 * 4944 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID 4945 * CTA Data Blocks. 4946 * 4947 * struct cea_db *db: 4948 * struct cea_db_iter iter; 4949 * 4950 * cea_db_iter_edid_begin(edid, &iter); 4951 * cea_db_iter_for_each(db, &iter) { 4952 * // do stuff with db 4953 * } 4954 * cea_db_iter_end(&iter); 4955 */ 4956 struct cea_db_iter { 4957 struct drm_edid_iter edid_iter; 4958 struct displayid_iter displayid_iter; 4959 4960 /* Current Data Block Collection. */ 4961 const u8 *collection; 4962 4963 /* Current Data Block index in current collection. */ 4964 int index; 4965 4966 /* End index in current collection. */ 4967 int end; 4968 }; 4969 4970 /* CTA-861-H section 7.4 CTA Data BLock Collection */ 4971 struct cea_db { 4972 u8 tag_length; 4973 u8 data[]; 4974 } __packed; 4975 4976 static int cea_db_tag(const struct cea_db *db) 4977 { 4978 return db->tag_length >> 5; 4979 } 4980 4981 static int cea_db_payload_len(const void *_db) 4982 { 4983 /* FIXME: Transition to passing struct cea_db * everywhere. */ 4984 const struct cea_db *db = _db; 4985 4986 return db->tag_length & 0x1f; 4987 } 4988 4989 static const void *cea_db_data(const struct cea_db *db) 4990 { 4991 return db->data; 4992 } 4993 4994 static bool cea_db_is_extended_tag(const struct cea_db *db, int tag) 4995 { 4996 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG && 4997 cea_db_payload_len(db) >= 1 && 4998 db->data[0] == tag; 4999 } 5000 5001 static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui) 5002 { 5003 const u8 *data = cea_db_data(db); 5004 5005 return cea_db_tag(db) == CTA_DB_VENDOR && 5006 cea_db_payload_len(db) >= 3 && 5007 oui(data[2], data[1], data[0]) == vendor_oui; 5008 } 5009 5010 static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid, 5011 struct cea_db_iter *iter) 5012 { 5013 memset(iter, 0, sizeof(*iter)); 5014 5015 drm_edid_iter_begin(drm_edid, &iter->edid_iter); 5016 displayid_iter_edid_begin(drm_edid, &iter->displayid_iter); 5017 } 5018 5019 static const struct cea_db * 5020 __cea_db_iter_current_block(const struct cea_db_iter *iter) 5021 { 5022 const struct cea_db *db; 5023 5024 if (!iter->collection) 5025 return NULL; 5026 5027 db = (const struct cea_db *)&iter->collection[iter->index]; 5028 5029 if (iter->index + sizeof(*db) <= iter->end && 5030 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end) 5031 return db; 5032 5033 return NULL; 5034 } 5035 5036 /* 5037 * References: 5038 * - CTA-861-H section 7.3.3 CTA Extension Version 3 5039 */ 5040 static int cea_db_collection_size(const u8 *cta) 5041 { 5042 u8 d = cta[2]; 5043 5044 if (d < 4 || d > 127) 5045 return 0; 5046 5047 return d - 4; 5048 } 5049 5050 /* 5051 * References: 5052 * - VESA E-EDID v1.4 5053 * - CTA-861-H section 7.3.3 CTA Extension Version 3 5054 */ 5055 static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter) 5056 { 5057 const u8 *ext; 5058 5059 drm_edid_iter_for_each(ext, &iter->edid_iter) { 5060 int size; 5061 5062 /* Only support CTA Extension revision 3+ */ 5063 if (ext[0] != CEA_EXT || cea_revision(ext) < 3) 5064 continue; 5065 5066 size = cea_db_collection_size(ext); 5067 if (!size) 5068 continue; 5069 5070 iter->index = 4; 5071 iter->end = iter->index + size; 5072 5073 return ext; 5074 } 5075 5076 return NULL; 5077 } 5078 5079 /* 5080 * References: 5081 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block 5082 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block 5083 * 5084 * Note that the above do not specify any connection between DisplayID Data 5085 * Block revision and CTA Extension versions. 5086 */ 5087 static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter) 5088 { 5089 const struct displayid_block *block; 5090 5091 displayid_iter_for_each(block, &iter->displayid_iter) { 5092 if (block->tag != DATA_BLOCK_CTA) 5093 continue; 5094 5095 /* 5096 * The displayid iterator has already verified the block bounds 5097 * in displayid_iter_block(). 5098 */ 5099 iter->index = sizeof(*block); 5100 iter->end = iter->index + block->num_bytes; 5101 5102 return block; 5103 } 5104 5105 return NULL; 5106 } 5107 5108 static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter) 5109 { 5110 const struct cea_db *db; 5111 5112 if (iter->collection) { 5113 /* Current collection should always be valid. */ 5114 db = __cea_db_iter_current_block(iter); 5115 if (WARN_ON(!db)) { 5116 iter->collection = NULL; 5117 return NULL; 5118 } 5119 5120 /* Next block in CTA Data Block Collection */ 5121 iter->index += sizeof(*db) + cea_db_payload_len(db); 5122 5123 db = __cea_db_iter_current_block(iter); 5124 if (db) 5125 return db; 5126 } 5127 5128 for (;;) { 5129 /* 5130 * Find the next CTA Data Block Collection. First iterate all 5131 * the EDID CTA Extensions, then all the DisplayID CTA blocks. 5132 * 5133 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID 5134 * Extension, it's recommended that DisplayID extensions are 5135 * exposed after all of the CTA Extensions. 5136 */ 5137 iter->collection = __cea_db_iter_edid_next(iter); 5138 if (!iter->collection) 5139 iter->collection = __cea_db_iter_displayid_next(iter); 5140 5141 if (!iter->collection) 5142 return NULL; 5143 5144 db = __cea_db_iter_current_block(iter); 5145 if (db) 5146 return db; 5147 } 5148 } 5149 5150 #define cea_db_iter_for_each(__db, __iter) \ 5151 while (((__db) = __cea_db_iter_next(__iter))) 5152 5153 static void cea_db_iter_end(struct cea_db_iter *iter) 5154 { 5155 displayid_iter_end(&iter->displayid_iter); 5156 drm_edid_iter_end(&iter->edid_iter); 5157 5158 memset(iter, 0, sizeof(*iter)); 5159 } 5160 5161 static bool cea_db_is_hdmi_vsdb(const struct cea_db *db) 5162 { 5163 return cea_db_is_vendor(db, HDMI_IEEE_OUI) && 5164 cea_db_payload_len(db) >= 5; 5165 } 5166 5167 static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db) 5168 { 5169 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) && 5170 cea_db_payload_len(db) >= 7; 5171 } 5172 5173 static bool cea_db_is_hdmi_forum_eeodb(const void *db) 5174 { 5175 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) && 5176 cea_db_payload_len(db) >= 2; 5177 } 5178 5179 static bool cea_db_is_microsoft_vsdb(const struct cea_db *db) 5180 { 5181 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) && 5182 cea_db_payload_len(db) == 21; 5183 } 5184 5185 static bool cea_db_is_vcdb(const struct cea_db *db) 5186 { 5187 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) && 5188 cea_db_payload_len(db) == 2; 5189 } 5190 5191 static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db) 5192 { 5193 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) && 5194 cea_db_payload_len(db) >= 7; 5195 } 5196 5197 static bool cea_db_is_y420cmdb(const struct cea_db *db) 5198 { 5199 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP); 5200 } 5201 5202 static bool cea_db_is_y420vdb(const struct cea_db *db) 5203 { 5204 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA); 5205 } 5206 5207 static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db) 5208 { 5209 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) && 5210 cea_db_payload_len(db) >= 3; 5211 } 5212 5213 /* 5214 * Get the HF-EEODB override extension block count from EDID. 5215 * 5216 * The passed in EDID may be partially read, as long as it has at least two 5217 * blocks (base block and one extension block) if EDID extension count is > 0. 5218 * 5219 * Note that this is *not* how you should parse CTA Data Blocks in general; this 5220 * is only to handle partially read EDIDs. Normally, use the CTA Data Block 5221 * iterators instead. 5222 * 5223 * References: 5224 * - HDMI 2.1 section 10.3.6 HDMI Forum EDID Extension Override Data Block 5225 */ 5226 static int edid_hfeeodb_extension_block_count(const struct edid *edid) 5227 { 5228 const u8 *cta; 5229 5230 /* No extensions according to base block, no HF-EEODB. */ 5231 if (!edid_extension_block_count(edid)) 5232 return 0; 5233 5234 /* HF-EEODB is always in the first EDID extension block only */ 5235 cta = edid_extension_block_data(edid, 0); 5236 if (edid_block_tag(cta) != CEA_EXT || cea_revision(cta) < 3) 5237 return 0; 5238 5239 /* Need to have the data block collection, and at least 3 bytes. */ 5240 if (cea_db_collection_size(cta) < 3) 5241 return 0; 5242 5243 /* 5244 * Sinks that include the HF-EEODB in their E-EDID shall include one and 5245 * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4 5246 * through 6 of Block 1 of the E-EDID. 5247 */ 5248 if (!cea_db_is_hdmi_forum_eeodb(&cta[4])) 5249 return 0; 5250 5251 return cta[4 + 2]; 5252 } 5253 5254 /* 5255 * CTA-861 YCbCr 4:2:0 Capability Map Data Block (CTA Y420CMDB) 5256 * 5257 * Y420CMDB contains a bitmap which gives the index of CTA modes from CTA VDB, 5258 * which can support YCBCR 420 sampling output also (apart from RGB/YCBCR444 5259 * etc). For example, if the bit 0 in bitmap is set, first mode in VDB can 5260 * support YCBCR420 output too. 5261 */ 5262 static void parse_cta_y420cmdb(struct drm_connector *connector, 5263 const struct cea_db *db, u64 *y420cmdb_map) 5264 { 5265 struct drm_display_info *info = &connector->display_info; 5266 int i, map_len = cea_db_payload_len(db) - 1; 5267 const u8 *data = cea_db_data(db) + 1; 5268 u64 map = 0; 5269 5270 if (map_len == 0) { 5271 /* All CEA modes support ycbcr420 sampling also.*/ 5272 map = U64_MAX; 5273 goto out; 5274 } 5275 5276 /* 5277 * This map indicates which of the existing CEA block modes 5278 * from VDB can support YCBCR420 output too. So if bit=0 is 5279 * set, first mode from VDB can support YCBCR420 output too. 5280 * We will parse and keep this map, before parsing VDB itself 5281 * to avoid going through the same block again and again. 5282 * 5283 * Spec is not clear about max possible size of this block. 5284 * Clamping max bitmap block size at 8 bytes. Every byte can 5285 * address 8 CEA modes, in this way this map can address 5286 * 8*8 = first 64 SVDs. 5287 */ 5288 if (WARN_ON_ONCE(map_len > 8)) 5289 map_len = 8; 5290 5291 for (i = 0; i < map_len; i++) 5292 map |= (u64)data[i] << (8 * i); 5293 5294 out: 5295 if (map) 5296 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; 5297 5298 *y420cmdb_map = map; 5299 } 5300 5301 static int add_cea_modes(struct drm_connector *connector, 5302 const struct drm_edid *drm_edid) 5303 { 5304 const struct cea_db *db; 5305 struct cea_db_iter iter; 5306 int modes; 5307 5308 /* CTA VDB block VICs parsed earlier */ 5309 modes = add_cta_vdb_modes(connector); 5310 5311 cea_db_iter_edid_begin(drm_edid, &iter); 5312 cea_db_iter_for_each(db, &iter) { 5313 if (cea_db_is_hdmi_vsdb(db)) { 5314 modes += do_hdmi_vsdb_modes(connector, (const u8 *)db, 5315 cea_db_payload_len(db)); 5316 } else if (cea_db_is_y420vdb(db)) { 5317 const u8 *vdb420 = cea_db_data(db) + 1; 5318 5319 /* Add 4:2:0(only) modes present in EDID */ 5320 modes += do_y420vdb_modes(connector, vdb420, 5321 cea_db_payload_len(db) - 1); 5322 } 5323 } 5324 cea_db_iter_end(&iter); 5325 5326 return modes; 5327 } 5328 5329 static void fixup_detailed_cea_mode_clock(struct drm_connector *connector, 5330 struct drm_display_mode *mode) 5331 { 5332 const struct drm_display_mode *cea_mode; 5333 int clock1, clock2, clock; 5334 u8 vic; 5335 const char *type; 5336 5337 /* 5338 * allow 5kHz clock difference either way to account for 5339 * the 10kHz clock resolution limit of detailed timings. 5340 */ 5341 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 5342 if (drm_valid_cea_vic(vic)) { 5343 type = "CEA"; 5344 cea_mode = cea_mode_for_vic(vic); 5345 clock1 = cea_mode->clock; 5346 clock2 = cea_mode_alternate_clock(cea_mode); 5347 } else { 5348 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 5349 if (drm_valid_hdmi_vic(vic)) { 5350 type = "HDMI"; 5351 cea_mode = &edid_4k_modes[vic]; 5352 clock1 = cea_mode->clock; 5353 clock2 = hdmi_mode_alternate_clock(cea_mode); 5354 } else { 5355 return; 5356 } 5357 } 5358 5359 /* pick whichever is closest */ 5360 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 5361 clock = clock1; 5362 else 5363 clock = clock2; 5364 5365 if (mode->clock == clock) 5366 return; 5367 5368 drm_dbg_kms(connector->dev, 5369 "[CONNECTOR:%d:%s] detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 5370 connector->base.id, connector->name, 5371 type, vic, mode->clock, clock); 5372 mode->clock = clock; 5373 } 5374 5375 static void drm_calculate_luminance_range(struct drm_connector *connector) 5376 { 5377 const struct hdr_static_metadata *hdr_metadata = 5378 &connector->display_info.hdr_sink_metadata.hdmi_type1; 5379 struct drm_luminance_range_info *luminance_range = 5380 &connector->display_info.luminance_range; 5381 static const u8 pre_computed_values[] = { 5382 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69, 5383 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98 5384 }; 5385 u32 max_avg, min_cll, max, min, q, r; 5386 5387 if (!(hdr_metadata->metadata_type & BIT(HDMI_STATIC_METADATA_TYPE1))) 5388 return; 5389 5390 max_avg = hdr_metadata->max_fall; 5391 min_cll = hdr_metadata->min_cll; 5392 5393 /* 5394 * From the specification (CTA-861-G), for calculating the maximum 5395 * luminance we need to use: 5396 * Luminance = 50*2**(CV/32) 5397 * Where CV is a one-byte value. 5398 * For calculating this expression we may need float point precision; 5399 * to avoid this complexity level, we take advantage that CV is divided 5400 * by a constant. From the Euclids division algorithm, we know that CV 5401 * can be written as: CV = 32*q + r. Next, we replace CV in the 5402 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just 5403 * need to pre-compute the value of r/32. For pre-computing the values 5404 * We just used the following Ruby line: 5405 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round} 5406 * The results of the above expressions can be verified at 5407 * pre_computed_values. 5408 */ 5409 q = max_avg >> 5; 5410 r = max_avg % 32; 5411 max = (1 << q) * pre_computed_values[r]; 5412 5413 /* min luminance: maxLum * (CV/255)^2 / 100 */ 5414 q = DIV_ROUND_CLOSEST(min_cll, 255); 5415 min = max * DIV_ROUND_CLOSEST((q * q), 100); 5416 5417 luminance_range->min_luminance = min; 5418 luminance_range->max_luminance = max; 5419 } 5420 5421 static uint8_t eotf_supported(const u8 *edid_ext) 5422 { 5423 return edid_ext[2] & 5424 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) | 5425 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) | 5426 BIT(HDMI_EOTF_SMPTE_ST2084) | 5427 BIT(HDMI_EOTF_BT_2100_HLG)); 5428 } 5429 5430 static uint8_t hdr_metadata_type(const u8 *edid_ext) 5431 { 5432 return edid_ext[3] & 5433 BIT(HDMI_STATIC_METADATA_TYPE1); 5434 } 5435 5436 static void 5437 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db) 5438 { 5439 struct hdr_static_metadata *hdr_metadata = 5440 &connector->display_info.hdr_sink_metadata.hdmi_type1; 5441 u16 len; 5442 5443 len = cea_db_payload_len(db); 5444 5445 hdr_metadata->eotf = eotf_supported(db); 5446 hdr_metadata->metadata_type = hdr_metadata_type(db); 5447 5448 if (len >= 4) 5449 hdr_metadata->max_cll = db[4]; 5450 if (len >= 5) 5451 hdr_metadata->max_fall = db[5]; 5452 if (len >= 6) { 5453 hdr_metadata->min_cll = db[6]; 5454 5455 /* Calculate only when all values are available */ 5456 drm_calculate_luminance_range(connector); 5457 } 5458 } 5459 5460 /* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */ 5461 static void 5462 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 5463 { 5464 u8 len = cea_db_payload_len(db); 5465 5466 if (len >= 6 && (db[6] & (1 << 7))) 5467 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI; 5468 5469 if (len >= 10 && hdmi_vsdb_latency_present(db)) { 5470 connector->latency_present[0] = true; 5471 connector->video_latency[0] = db[9]; 5472 connector->audio_latency[0] = db[10]; 5473 } 5474 5475 if (len >= 12 && hdmi_vsdb_i_latency_present(db)) { 5476 connector->latency_present[1] = true; 5477 connector->video_latency[1] = db[11]; 5478 connector->audio_latency[1] = db[12]; 5479 } 5480 5481 drm_dbg_kms(connector->dev, 5482 "[CONNECTOR:%d:%s] HDMI: latency present %d %d, video latency %d %d, audio latency %d %d\n", 5483 connector->base.id, connector->name, 5484 connector->latency_present[0], connector->latency_present[1], 5485 connector->video_latency[0], connector->video_latency[1], 5486 connector->audio_latency[0], connector->audio_latency[1]); 5487 } 5488 5489 static void 5490 match_identity(const struct detailed_timing *timing, void *data) 5491 { 5492 struct drm_edid_match_closure *closure = data; 5493 unsigned int i; 5494 const char *name = closure->ident->name; 5495 unsigned int name_len = strlen(name); 5496 const char *desc = timing->data.other_data.data.str.str; 5497 unsigned int desc_len = ARRAY_SIZE(timing->data.other_data.data.str.str); 5498 5499 if (name_len > desc_len || 5500 !(is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME) || 5501 is_display_descriptor(timing, EDID_DETAIL_MONITOR_STRING))) 5502 return; 5503 5504 if (strncmp(name, desc, name_len)) 5505 return; 5506 5507 for (i = name_len; i < desc_len; i++) { 5508 if (desc[i] == '\n') 5509 break; 5510 /* Allow white space before EDID string terminator. */ 5511 if (!isspace(desc[i])) 5512 return; 5513 } 5514 5515 closure->matched = true; 5516 } 5517 5518 /** 5519 * drm_edid_match - match drm_edid with given identity 5520 * @drm_edid: EDID 5521 * @ident: the EDID identity to match with 5522 * 5523 * Check if the EDID matches with the given identity. 5524 * 5525 * Return: True if the given identity matched with EDID, false otherwise. 5526 */ 5527 bool drm_edid_match(const struct drm_edid *drm_edid, 5528 const struct drm_edid_ident *ident) 5529 { 5530 if (!drm_edid || drm_edid_get_panel_id(drm_edid) != ident->panel_id) 5531 return false; 5532 5533 /* Match with name only if it's not NULL. */ 5534 if (ident->name) { 5535 struct drm_edid_match_closure closure = { 5536 .ident = ident, 5537 .matched = false, 5538 }; 5539 5540 drm_for_each_detailed_block(drm_edid, match_identity, &closure); 5541 5542 return closure.matched; 5543 } 5544 5545 return true; 5546 } 5547 EXPORT_SYMBOL(drm_edid_match); 5548 5549 static void 5550 monitor_name(const struct detailed_timing *timing, void *data) 5551 { 5552 const char **res = data; 5553 5554 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME)) 5555 return; 5556 5557 *res = timing->data.other_data.data.str.str; 5558 } 5559 5560 static int get_monitor_name(const struct drm_edid *drm_edid, char name[13]) 5561 { 5562 const char *edid_name = NULL; 5563 int mnl; 5564 5565 if (!drm_edid || !name) 5566 return 0; 5567 5568 drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name); 5569 for (mnl = 0; edid_name && mnl < 13; mnl++) { 5570 if (edid_name[mnl] == 0x0a) 5571 break; 5572 5573 name[mnl] = edid_name[mnl]; 5574 } 5575 5576 return mnl; 5577 } 5578 5579 /** 5580 * drm_edid_get_monitor_name - fetch the monitor name from the edid 5581 * @edid: monitor EDID information 5582 * @name: pointer to a character array to hold the name of the monitor 5583 * @bufsize: The size of the name buffer (should be at least 14 chars.) 5584 * 5585 */ 5586 void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize) 5587 { 5588 int name_length = 0; 5589 5590 if (bufsize <= 0) 5591 return; 5592 5593 if (edid) { 5594 char buf[13]; 5595 struct drm_edid drm_edid = { 5596 .edid = edid, 5597 .size = edid_size(edid), 5598 }; 5599 5600 name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1); 5601 memcpy(name, buf, name_length); 5602 } 5603 5604 name[name_length] = '\0'; 5605 } 5606 EXPORT_SYMBOL(drm_edid_get_monitor_name); 5607 5608 static void clear_eld(struct drm_connector *connector) 5609 { 5610 mutex_lock(&connector->eld_mutex); 5611 memset(connector->eld, 0, sizeof(connector->eld)); 5612 mutex_unlock(&connector->eld_mutex); 5613 5614 connector->latency_present[0] = false; 5615 connector->latency_present[1] = false; 5616 connector->video_latency[0] = 0; 5617 connector->audio_latency[0] = 0; 5618 connector->video_latency[1] = 0; 5619 connector->audio_latency[1] = 0; 5620 } 5621 5622 /* 5623 * Get 3-byte SAD buffer from struct cea_sad. 5624 */ 5625 void drm_edid_cta_sad_get(const struct cea_sad *cta_sad, u8 *sad) 5626 { 5627 sad[0] = cta_sad->format << 3 | cta_sad->channels; 5628 sad[1] = cta_sad->freq; 5629 sad[2] = cta_sad->byte2; 5630 } 5631 5632 /* 5633 * Set struct cea_sad from 3-byte SAD buffer. 5634 */ 5635 void drm_edid_cta_sad_set(struct cea_sad *cta_sad, const u8 *sad) 5636 { 5637 cta_sad->format = (sad[0] & 0x78) >> 3; 5638 cta_sad->channels = sad[0] & 0x07; 5639 cta_sad->freq = sad[1] & 0x7f; 5640 cta_sad->byte2 = sad[2]; 5641 } 5642 5643 /* 5644 * drm_edid_to_eld - build ELD from EDID 5645 * @connector: connector corresponding to the HDMI/DP sink 5646 * @drm_edid: EDID to parse 5647 * 5648 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 5649 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 5650 */ 5651 static void drm_edid_to_eld(struct drm_connector *connector, 5652 const struct drm_edid *drm_edid) 5653 { 5654 const struct drm_display_info *info = &connector->display_info; 5655 const struct cea_db *db; 5656 struct cea_db_iter iter; 5657 uint8_t *eld = connector->eld; 5658 int total_sad_count = 0; 5659 int mnl; 5660 5661 if (!drm_edid) 5662 return; 5663 5664 mutex_lock(&connector->eld_mutex); 5665 5666 mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]); 5667 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD monitor %s\n", 5668 connector->base.id, connector->name, 5669 &eld[DRM_ELD_MONITOR_NAME_STRING]); 5670 5671 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT; 5672 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl; 5673 5674 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D; 5675 5676 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0]; 5677 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1]; 5678 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0]; 5679 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1]; 5680 5681 cea_db_iter_edid_begin(drm_edid, &iter); 5682 cea_db_iter_for_each(db, &iter) { 5683 const u8 *data = cea_db_data(db); 5684 int len = cea_db_payload_len(db); 5685 int sad_count; 5686 5687 switch (cea_db_tag(db)) { 5688 case CTA_DB_AUDIO: 5689 /* Audio Data Block, contains SADs */ 5690 sad_count = min(len / 3, 15 - total_sad_count); 5691 if (sad_count >= 1) 5692 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)], 5693 data, sad_count * 3); 5694 total_sad_count += sad_count; 5695 break; 5696 case CTA_DB_SPEAKER: 5697 /* Speaker Allocation Data Block */ 5698 if (len >= 1) 5699 eld[DRM_ELD_SPEAKER] = data[0]; 5700 break; 5701 case CTA_DB_VENDOR: 5702 /* HDMI Vendor-Specific Data Block */ 5703 if (cea_db_is_hdmi_vsdb(db)) 5704 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db); 5705 break; 5706 default: 5707 break; 5708 } 5709 } 5710 cea_db_iter_end(&iter); 5711 5712 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT; 5713 5714 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 5715 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 5716 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 5717 else 5718 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 5719 5720 eld[DRM_ELD_BASELINE_ELD_LEN] = 5721 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 5722 5723 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD size %d, SAD count %d\n", 5724 connector->base.id, connector->name, 5725 drm_eld_size(eld), total_sad_count); 5726 5727 mutex_unlock(&connector->eld_mutex); 5728 } 5729 5730 static int _drm_edid_to_sad(const struct drm_edid *drm_edid, 5731 struct cea_sad **psads) 5732 { 5733 const struct cea_db *db; 5734 struct cea_db_iter iter; 5735 int count = 0; 5736 5737 cea_db_iter_edid_begin(drm_edid, &iter); 5738 cea_db_iter_for_each(db, &iter) { 5739 if (cea_db_tag(db) == CTA_DB_AUDIO) { 5740 struct cea_sad *sads; 5741 int i; 5742 5743 count = cea_db_payload_len(db) / 3; /* SAD is 3B */ 5744 sads = kcalloc(count, sizeof(*sads), GFP_KERNEL); 5745 *psads = sads; 5746 if (!sads) 5747 return -ENOMEM; 5748 for (i = 0; i < count; i++) 5749 drm_edid_cta_sad_set(&sads[i], &db->data[i * 3]); 5750 break; 5751 } 5752 } 5753 cea_db_iter_end(&iter); 5754 5755 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count); 5756 5757 return count; 5758 } 5759 5760 /** 5761 * drm_edid_to_sad - extracts SADs from EDID 5762 * @edid: EDID to parse 5763 * @sads: pointer that will be set to the extracted SADs 5764 * 5765 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 5766 * 5767 * Note: The returned pointer needs to be freed using kfree(). 5768 * 5769 * Return: The number of found SADs or negative number on error. 5770 */ 5771 int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads) 5772 { 5773 struct drm_edid drm_edid; 5774 5775 return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads); 5776 } 5777 EXPORT_SYMBOL(drm_edid_to_sad); 5778 5779 static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid, 5780 u8 **sadb) 5781 { 5782 const struct cea_db *db; 5783 struct cea_db_iter iter; 5784 int count = 0; 5785 5786 cea_db_iter_edid_begin(drm_edid, &iter); 5787 cea_db_iter_for_each(db, &iter) { 5788 if (cea_db_tag(db) == CTA_DB_SPEAKER && 5789 cea_db_payload_len(db) == 3) { 5790 *sadb = kmemdup(db->data, cea_db_payload_len(db), 5791 GFP_KERNEL); 5792 if (!*sadb) 5793 return -ENOMEM; 5794 count = cea_db_payload_len(db); 5795 break; 5796 } 5797 } 5798 cea_db_iter_end(&iter); 5799 5800 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count); 5801 5802 return count; 5803 } 5804 5805 /** 5806 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 5807 * @edid: EDID to parse 5808 * @sadb: pointer to the speaker block 5809 * 5810 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 5811 * 5812 * Note: The returned pointer needs to be freed using kfree(). 5813 * 5814 * Return: The number of found Speaker Allocation Blocks or negative number on 5815 * error. 5816 */ 5817 int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb) 5818 { 5819 struct drm_edid drm_edid; 5820 5821 return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid), 5822 sadb); 5823 } 5824 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 5825 5826 /** 5827 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 5828 * @connector: connector associated with the HDMI/DP sink 5829 * @mode: the display mode 5830 * 5831 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 5832 * the sink doesn't support audio or video. 5833 */ 5834 int drm_av_sync_delay(struct drm_connector *connector, 5835 const struct drm_display_mode *mode) 5836 { 5837 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 5838 int a, v; 5839 5840 if (!connector->latency_present[0]) 5841 return 0; 5842 if (!connector->latency_present[1]) 5843 i = 0; 5844 5845 a = connector->audio_latency[i]; 5846 v = connector->video_latency[i]; 5847 5848 /* 5849 * HDMI/DP sink doesn't support audio or video? 5850 */ 5851 if (a == 255 || v == 255) 5852 return 0; 5853 5854 /* 5855 * Convert raw EDID values to millisecond. 5856 * Treat unknown latency as 0ms. 5857 */ 5858 if (a) 5859 a = min(2 * (a - 1), 500); 5860 if (v) 5861 v = min(2 * (v - 1), 500); 5862 5863 return max(v - a, 0); 5864 } 5865 EXPORT_SYMBOL(drm_av_sync_delay); 5866 5867 static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid) 5868 { 5869 const struct cea_db *db; 5870 struct cea_db_iter iter; 5871 bool hdmi = false; 5872 5873 /* 5874 * Because HDMI identifier is in Vendor Specific Block, 5875 * search it from all data blocks of CEA extension. 5876 */ 5877 cea_db_iter_edid_begin(drm_edid, &iter); 5878 cea_db_iter_for_each(db, &iter) { 5879 if (cea_db_is_hdmi_vsdb(db)) { 5880 hdmi = true; 5881 break; 5882 } 5883 } 5884 cea_db_iter_end(&iter); 5885 5886 return hdmi; 5887 } 5888 5889 /** 5890 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 5891 * @edid: monitor EDID information 5892 * 5893 * Parse the CEA extension according to CEA-861-B. 5894 * 5895 * Drivers that have added the modes parsed from EDID to drm_display_info 5896 * should use &drm_display_info.is_hdmi instead of calling this function. 5897 * 5898 * Return: True if the monitor is HDMI, false if not or unknown. 5899 */ 5900 bool drm_detect_hdmi_monitor(const struct edid *edid) 5901 { 5902 struct drm_edid drm_edid; 5903 5904 return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid)); 5905 } 5906 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 5907 5908 static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid) 5909 { 5910 struct drm_edid_iter edid_iter; 5911 const struct cea_db *db; 5912 struct cea_db_iter iter; 5913 const u8 *edid_ext; 5914 bool has_audio = false; 5915 5916 drm_edid_iter_begin(drm_edid, &edid_iter); 5917 drm_edid_iter_for_each(edid_ext, &edid_iter) { 5918 if (edid_ext[0] == CEA_EXT) { 5919 has_audio = edid_ext[3] & EDID_BASIC_AUDIO; 5920 if (has_audio) 5921 break; 5922 } 5923 } 5924 drm_edid_iter_end(&edid_iter); 5925 5926 if (has_audio) { 5927 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 5928 goto end; 5929 } 5930 5931 cea_db_iter_edid_begin(drm_edid, &iter); 5932 cea_db_iter_for_each(db, &iter) { 5933 if (cea_db_tag(db) == CTA_DB_AUDIO) { 5934 const u8 *data = cea_db_data(db); 5935 int i; 5936 5937 for (i = 0; i < cea_db_payload_len(db); i += 3) 5938 DRM_DEBUG_KMS("CEA audio format %d\n", 5939 (data[i] >> 3) & 0xf); 5940 has_audio = true; 5941 break; 5942 } 5943 } 5944 cea_db_iter_end(&iter); 5945 5946 end: 5947 return has_audio; 5948 } 5949 5950 /** 5951 * drm_detect_monitor_audio - check monitor audio capability 5952 * @edid: EDID block to scan 5953 * 5954 * Monitor should have CEA extension block. 5955 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 5956 * audio' only. If there is any audio extension block and supported 5957 * audio format, assume at least 'basic audio' support, even if 'basic 5958 * audio' is not defined in EDID. 5959 * 5960 * Return: True if the monitor supports audio, false otherwise. 5961 */ 5962 bool drm_detect_monitor_audio(const struct edid *edid) 5963 { 5964 struct drm_edid drm_edid; 5965 5966 return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid)); 5967 } 5968 EXPORT_SYMBOL(drm_detect_monitor_audio); 5969 5970 5971 /** 5972 * drm_default_rgb_quant_range - default RGB quantization range 5973 * @mode: display mode 5974 * 5975 * Determine the default RGB quantization range for the mode, 5976 * as specified in CEA-861. 5977 * 5978 * Return: The default RGB quantization range for the mode 5979 */ 5980 enum hdmi_quantization_range 5981 drm_default_rgb_quant_range(const struct drm_display_mode *mode) 5982 { 5983 /* All CEA modes other than VIC 1 use limited quantization range. */ 5984 return drm_match_cea_mode(mode) > 1 ? 5985 HDMI_QUANTIZATION_RANGE_LIMITED : 5986 HDMI_QUANTIZATION_RANGE_FULL; 5987 } 5988 EXPORT_SYMBOL(drm_default_rgb_quant_range); 5989 5990 /* CTA-861 Video Data Block (CTA VDB) */ 5991 static void parse_cta_vdb(struct drm_connector *connector, const struct cea_db *db) 5992 { 5993 struct drm_display_info *info = &connector->display_info; 5994 int i, vic_index, len = cea_db_payload_len(db); 5995 const u8 *svds = cea_db_data(db); 5996 u8 *vics; 5997 5998 if (!len) 5999 return; 6000 6001 /* Gracefully handle multiple VDBs, however unlikely that is */ 6002 vics = krealloc(info->vics, info->vics_len + len, GFP_KERNEL); 6003 if (!vics) 6004 return; 6005 6006 vic_index = info->vics_len; 6007 info->vics_len += len; 6008 info->vics = vics; 6009 6010 for (i = 0; i < len; i++) { 6011 u8 vic = svd_to_vic(svds[i]); 6012 6013 if (!drm_valid_cea_vic(vic)) 6014 vic = 0; 6015 6016 info->vics[vic_index++] = vic; 6017 } 6018 } 6019 6020 /* 6021 * Update y420_cmdb_modes based on previously parsed CTA VDB and Y420CMDB. 6022 * 6023 * Translate the y420cmdb_map based on VIC indexes to y420_cmdb_modes indexed 6024 * using the VICs themselves. 6025 */ 6026 static void update_cta_y420cmdb(struct drm_connector *connector, u64 y420cmdb_map) 6027 { 6028 struct drm_display_info *info = &connector->display_info; 6029 struct drm_hdmi_info *hdmi = &info->hdmi; 6030 int i, len = min_t(int, info->vics_len, BITS_PER_TYPE(y420cmdb_map)); 6031 6032 for (i = 0; i < len; i++) { 6033 u8 vic = info->vics[i]; 6034 6035 if (vic && y420cmdb_map & BIT_ULL(i)) 6036 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 6037 } 6038 } 6039 6040 static bool cta_vdb_has_vic(const struct drm_connector *connector, u8 vic) 6041 { 6042 const struct drm_display_info *info = &connector->display_info; 6043 int i; 6044 6045 if (!vic || !info->vics) 6046 return false; 6047 6048 for (i = 0; i < info->vics_len; i++) { 6049 if (info->vics[i] == vic) 6050 return true; 6051 } 6052 6053 return false; 6054 } 6055 6056 /* CTA-861-H YCbCr 4:2:0 Video Data Block (CTA Y420VDB) */ 6057 static void parse_cta_y420vdb(struct drm_connector *connector, 6058 const struct cea_db *db) 6059 { 6060 struct drm_display_info *info = &connector->display_info; 6061 struct drm_hdmi_info *hdmi = &info->hdmi; 6062 const u8 *svds = cea_db_data(db) + 1; 6063 int i; 6064 6065 for (i = 0; i < cea_db_payload_len(db) - 1; i++) { 6066 u8 vic = svd_to_vic(svds[i]); 6067 6068 if (!drm_valid_cea_vic(vic)) 6069 continue; 6070 6071 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 6072 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; 6073 } 6074 } 6075 6076 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db) 6077 { 6078 struct drm_display_info *info = &connector->display_info; 6079 6080 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] CEA VCDB 0x%02x\n", 6081 connector->base.id, connector->name, db[2]); 6082 6083 if (db[2] & EDID_CEA_VCDB_QS) 6084 info->rgb_quant_range_selectable = true; 6085 } 6086 6087 static 6088 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane) 6089 { 6090 switch (max_frl_rate) { 6091 case 1: 6092 *max_lanes = 3; 6093 *max_rate_per_lane = 3; 6094 break; 6095 case 2: 6096 *max_lanes = 3; 6097 *max_rate_per_lane = 6; 6098 break; 6099 case 3: 6100 *max_lanes = 4; 6101 *max_rate_per_lane = 6; 6102 break; 6103 case 4: 6104 *max_lanes = 4; 6105 *max_rate_per_lane = 8; 6106 break; 6107 case 5: 6108 *max_lanes = 4; 6109 *max_rate_per_lane = 10; 6110 break; 6111 case 6: 6112 *max_lanes = 4; 6113 *max_rate_per_lane = 12; 6114 break; 6115 case 0: 6116 default: 6117 *max_lanes = 0; 6118 *max_rate_per_lane = 0; 6119 } 6120 } 6121 6122 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 6123 const u8 *db) 6124 { 6125 u8 dc_mask; 6126 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 6127 6128 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 6129 hdmi->y420_dc_modes = dc_mask; 6130 } 6131 6132 static void drm_parse_dsc_info(struct drm_hdmi_dsc_cap *hdmi_dsc, 6133 const u8 *hf_scds) 6134 { 6135 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2; 6136 6137 if (!hdmi_dsc->v_1p2) 6138 return; 6139 6140 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420; 6141 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP; 6142 6143 if (hf_scds[11] & DRM_EDID_DSC_16BPC) 6144 hdmi_dsc->bpc_supported = 16; 6145 else if (hf_scds[11] & DRM_EDID_DSC_12BPC) 6146 hdmi_dsc->bpc_supported = 12; 6147 else if (hf_scds[11] & DRM_EDID_DSC_10BPC) 6148 hdmi_dsc->bpc_supported = 10; 6149 else 6150 /* Supports min 8 BPC if DSC 1.2 is supported*/ 6151 hdmi_dsc->bpc_supported = 8; 6152 6153 if (cea_db_payload_len(hf_scds) >= 12 && hf_scds[12]) { 6154 u8 dsc_max_slices; 6155 u8 dsc_max_frl_rate; 6156 6157 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4; 6158 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes, 6159 &hdmi_dsc->max_frl_rate_per_lane); 6160 6161 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES; 6162 6163 switch (dsc_max_slices) { 6164 case 1: 6165 hdmi_dsc->max_slices = 1; 6166 hdmi_dsc->clk_per_slice = 340; 6167 break; 6168 case 2: 6169 hdmi_dsc->max_slices = 2; 6170 hdmi_dsc->clk_per_slice = 340; 6171 break; 6172 case 3: 6173 hdmi_dsc->max_slices = 4; 6174 hdmi_dsc->clk_per_slice = 340; 6175 break; 6176 case 4: 6177 hdmi_dsc->max_slices = 8; 6178 hdmi_dsc->clk_per_slice = 340; 6179 break; 6180 case 5: 6181 hdmi_dsc->max_slices = 8; 6182 hdmi_dsc->clk_per_slice = 400; 6183 break; 6184 case 6: 6185 hdmi_dsc->max_slices = 12; 6186 hdmi_dsc->clk_per_slice = 400; 6187 break; 6188 case 7: 6189 hdmi_dsc->max_slices = 16; 6190 hdmi_dsc->clk_per_slice = 400; 6191 break; 6192 case 0: 6193 default: 6194 hdmi_dsc->max_slices = 0; 6195 hdmi_dsc->clk_per_slice = 0; 6196 } 6197 } 6198 6199 if (cea_db_payload_len(hf_scds) >= 13 && hf_scds[13]) 6200 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES; 6201 } 6202 6203 /* Sink Capability Data Structure */ 6204 static void drm_parse_hdmi_forum_scds(struct drm_connector *connector, 6205 const u8 *hf_scds) 6206 { 6207 struct drm_display_info *info = &connector->display_info; 6208 struct drm_hdmi_info *hdmi = &info->hdmi; 6209 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap; 6210 int max_tmds_clock = 0; 6211 u8 max_frl_rate = 0; 6212 bool dsc_support = false; 6213 6214 info->has_hdmi_infoframe = true; 6215 6216 if (hf_scds[6] & 0x80) { 6217 hdmi->scdc.supported = true; 6218 if (hf_scds[6] & 0x40) 6219 hdmi->scdc.read_request = true; 6220 } 6221 6222 /* 6223 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 6224 * And as per the spec, three factors confirm this: 6225 * * Availability of a HF-VSDB block in EDID (check) 6226 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 6227 * * SCDC support available (let's check) 6228 * Lets check it out. 6229 */ 6230 6231 if (hf_scds[5]) { 6232 struct drm_scdc *scdc = &hdmi->scdc; 6233 6234 /* max clock is 5000 KHz times block value */ 6235 max_tmds_clock = hf_scds[5] * 5000; 6236 6237 if (max_tmds_clock > 340000) { 6238 info->max_tmds_clock = max_tmds_clock; 6239 } 6240 6241 if (scdc->supported) { 6242 scdc->scrambling.supported = true; 6243 6244 /* Few sinks support scrambling for clocks < 340M */ 6245 if ((hf_scds[6] & 0x8)) 6246 scdc->scrambling.low_rates = true; 6247 } 6248 } 6249 6250 if (hf_scds[7]) { 6251 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4; 6252 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes, 6253 &hdmi->max_frl_rate_per_lane); 6254 } 6255 6256 drm_parse_ycbcr420_deep_color_info(connector, hf_scds); 6257 6258 if (cea_db_payload_len(hf_scds) >= 11 && hf_scds[11]) { 6259 drm_parse_dsc_info(hdmi_dsc, hf_scds); 6260 dsc_support = true; 6261 } 6262 6263 drm_dbg_kms(connector->dev, 6264 "[CONNECTOR:%d:%s] HF-VSDB: max TMDS clock: %d KHz, HDMI 2.1 support: %s, DSC 1.2 support: %s\n", 6265 connector->base.id, connector->name, 6266 max_tmds_clock, str_yes_no(max_frl_rate), str_yes_no(dsc_support)); 6267 } 6268 6269 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 6270 const u8 *hdmi) 6271 { 6272 struct drm_display_info *info = &connector->display_info; 6273 unsigned int dc_bpc = 0; 6274 6275 /* HDMI supports at least 8 bpc */ 6276 info->bpc = 8; 6277 6278 if (cea_db_payload_len(hdmi) < 6) 6279 return; 6280 6281 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 6282 dc_bpc = 10; 6283 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30; 6284 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 30.\n", 6285 connector->base.id, connector->name); 6286 } 6287 6288 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 6289 dc_bpc = 12; 6290 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36; 6291 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 36.\n", 6292 connector->base.id, connector->name); 6293 } 6294 6295 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 6296 dc_bpc = 16; 6297 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48; 6298 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 48.\n", 6299 connector->base.id, connector->name); 6300 } 6301 6302 if (dc_bpc == 0) { 6303 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] No deep color support on this HDMI sink.\n", 6304 connector->base.id, connector->name); 6305 return; 6306 } 6307 6308 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Assigning HDMI sink color depth as %d bpc.\n", 6309 connector->base.id, connector->name, dc_bpc); 6310 info->bpc = dc_bpc; 6311 6312 /* YCRCB444 is optional according to spec. */ 6313 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 6314 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes; 6315 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does YCRCB444 in deep color.\n", 6316 connector->base.id, connector->name); 6317 } 6318 6319 /* 6320 * Spec says that if any deep color mode is supported at all, 6321 * then deep color 36 bit must be supported. 6322 */ 6323 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 6324 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink should do DC_36, but does not!\n", 6325 connector->base.id, connector->name); 6326 } 6327 } 6328 6329 /* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */ 6330 static void 6331 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 6332 { 6333 struct drm_display_info *info = &connector->display_info; 6334 u8 len = cea_db_payload_len(db); 6335 6336 info->is_hdmi = true; 6337 6338 info->source_physical_address = (db[4] << 8) | db[5]; 6339 6340 if (len >= 6) 6341 info->dvi_dual = db[6] & 1; 6342 if (len >= 7) 6343 info->max_tmds_clock = db[7] * 5000; 6344 6345 /* 6346 * Try to infer whether the sink supports HDMI infoframes. 6347 * 6348 * HDMI infoframe support was first added in HDMI 1.4. Assume the sink 6349 * supports infoframes if HDMI_Video_present is set. 6350 */ 6351 if (len >= 8 && db[8] & BIT(5)) 6352 info->has_hdmi_infoframe = true; 6353 6354 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI: DVI dual %d, max TMDS clock %d kHz\n", 6355 connector->base.id, connector->name, 6356 info->dvi_dual, info->max_tmds_clock); 6357 6358 drm_parse_hdmi_deep_color_info(connector, db); 6359 } 6360 6361 /* 6362 * See EDID extension for head-mounted and specialized monitors, specified at: 6363 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension 6364 */ 6365 static void drm_parse_microsoft_vsdb(struct drm_connector *connector, 6366 const u8 *db) 6367 { 6368 struct drm_display_info *info = &connector->display_info; 6369 u8 version = db[4]; 6370 bool desktop_usage = db[5] & BIT(6); 6371 6372 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */ 6373 if (version == 1 || version == 2 || (version == 3 && !desktop_usage)) 6374 info->non_desktop = true; 6375 6376 drm_dbg_kms(connector->dev, 6377 "[CONNECTOR:%d:%s] HMD or specialized display VSDB version %u: 0x%02x\n", 6378 connector->base.id, connector->name, version, db[5]); 6379 } 6380 6381 static void drm_parse_cea_ext(struct drm_connector *connector, 6382 const struct drm_edid *drm_edid) 6383 { 6384 struct drm_display_info *info = &connector->display_info; 6385 struct drm_edid_iter edid_iter; 6386 const struct cea_db *db; 6387 struct cea_db_iter iter; 6388 const u8 *edid_ext; 6389 u64 y420cmdb_map = 0; 6390 6391 drm_edid_iter_begin(drm_edid, &edid_iter); 6392 drm_edid_iter_for_each(edid_ext, &edid_iter) { 6393 if (edid_ext[0] != CEA_EXT) 6394 continue; 6395 6396 if (!info->cea_rev) 6397 info->cea_rev = edid_ext[1]; 6398 6399 if (info->cea_rev != edid_ext[1]) 6400 drm_dbg_kms(connector->dev, 6401 "[CONNECTOR:%d:%s] CEA extension version mismatch %u != %u\n", 6402 connector->base.id, connector->name, 6403 info->cea_rev, edid_ext[1]); 6404 6405 /* The existence of a CTA extension should imply RGB support */ 6406 info->color_formats = DRM_COLOR_FORMAT_RGB444; 6407 if (edid_ext[3] & EDID_CEA_YCRCB444) 6408 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444; 6409 if (edid_ext[3] & EDID_CEA_YCRCB422) 6410 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422; 6411 if (edid_ext[3] & EDID_BASIC_AUDIO) 6412 info->has_audio = true; 6413 6414 } 6415 drm_edid_iter_end(&edid_iter); 6416 6417 cea_db_iter_edid_begin(drm_edid, &iter); 6418 cea_db_iter_for_each(db, &iter) { 6419 /* FIXME: convert parsers to use struct cea_db */ 6420 const u8 *data = (const u8 *)db; 6421 6422 if (cea_db_is_hdmi_vsdb(db)) 6423 drm_parse_hdmi_vsdb_video(connector, data); 6424 else if (cea_db_is_hdmi_forum_vsdb(db) || 6425 cea_db_is_hdmi_forum_scdb(db)) 6426 drm_parse_hdmi_forum_scds(connector, data); 6427 else if (cea_db_is_microsoft_vsdb(db)) 6428 drm_parse_microsoft_vsdb(connector, data); 6429 else if (cea_db_is_y420cmdb(db)) 6430 parse_cta_y420cmdb(connector, db, &y420cmdb_map); 6431 else if (cea_db_is_y420vdb(db)) 6432 parse_cta_y420vdb(connector, db); 6433 else if (cea_db_is_vcdb(db)) 6434 drm_parse_vcdb(connector, data); 6435 else if (cea_db_is_hdmi_hdr_metadata_block(db)) 6436 drm_parse_hdr_metadata_block(connector, data); 6437 else if (cea_db_tag(db) == CTA_DB_VIDEO) 6438 parse_cta_vdb(connector, db); 6439 else if (cea_db_tag(db) == CTA_DB_AUDIO) 6440 info->has_audio = true; 6441 } 6442 cea_db_iter_end(&iter); 6443 6444 if (y420cmdb_map) 6445 update_cta_y420cmdb(connector, y420cmdb_map); 6446 } 6447 6448 static 6449 void get_monitor_range(const struct detailed_timing *timing, void *c) 6450 { 6451 struct detailed_mode_closure *closure = c; 6452 struct drm_display_info *info = &closure->connector->display_info; 6453 struct drm_monitor_range_info *monitor_range = &info->monitor_range; 6454 const struct detailed_non_pixel *data = &timing->data.other_data; 6455 const struct detailed_data_monitor_range *range = &data->data.range; 6456 const struct edid *edid = closure->drm_edid->edid; 6457 6458 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE)) 6459 return; 6460 6461 /* 6462 * These limits are used to determine the VRR refresh 6463 * rate range. Only the "range limits only" variant 6464 * of the range descriptor seems to guarantee that 6465 * any and all timings are accepted by the sink, as 6466 * opposed to just timings conforming to the indicated 6467 * formula (GTF/GTF2/CVT). Thus other variants of the 6468 * range descriptor are not accepted here. 6469 */ 6470 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG) 6471 return; 6472 6473 monitor_range->min_vfreq = range->min_vfreq; 6474 monitor_range->max_vfreq = range->max_vfreq; 6475 6476 if (edid->revision >= 4) { 6477 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ) 6478 monitor_range->min_vfreq += 255; 6479 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ) 6480 monitor_range->max_vfreq += 255; 6481 } 6482 } 6483 6484 static void drm_get_monitor_range(struct drm_connector *connector, 6485 const struct drm_edid *drm_edid) 6486 { 6487 const struct drm_display_info *info = &connector->display_info; 6488 struct detailed_mode_closure closure = { 6489 .connector = connector, 6490 .drm_edid = drm_edid, 6491 }; 6492 6493 if (drm_edid->edid->revision < 4) 6494 return; 6495 6496 if (!(drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ)) 6497 return; 6498 6499 drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure); 6500 6501 drm_dbg_kms(connector->dev, 6502 "[CONNECTOR:%d:%s] Supported Monitor Refresh rate range is %d Hz - %d Hz\n", 6503 connector->base.id, connector->name, 6504 info->monitor_range.min_vfreq, info->monitor_range.max_vfreq); 6505 } 6506 6507 static void drm_parse_vesa_mso_data(struct drm_connector *connector, 6508 const struct displayid_block *block) 6509 { 6510 struct displayid_vesa_vendor_specific_block *vesa = 6511 (struct displayid_vesa_vendor_specific_block *)block; 6512 struct drm_display_info *info = &connector->display_info; 6513 6514 if (block->num_bytes < 3) { 6515 drm_dbg_kms(connector->dev, 6516 "[CONNECTOR:%d:%s] Unexpected vendor block size %u\n", 6517 connector->base.id, connector->name, block->num_bytes); 6518 return; 6519 } 6520 6521 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI) 6522 return; 6523 6524 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) { 6525 drm_dbg_kms(connector->dev, 6526 "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n", 6527 connector->base.id, connector->name); 6528 return; 6529 } 6530 6531 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) { 6532 default: 6533 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n", 6534 connector->base.id, connector->name); 6535 fallthrough; 6536 case 0: 6537 info->mso_stream_count = 0; 6538 break; 6539 case 1: 6540 info->mso_stream_count = 2; /* 2 or 4 links */ 6541 break; 6542 case 2: 6543 info->mso_stream_count = 4; /* 4 links */ 6544 break; 6545 } 6546 6547 if (!info->mso_stream_count) { 6548 info->mso_pixel_overlap = 0; 6549 return; 6550 } 6551 6552 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso); 6553 if (info->mso_pixel_overlap > 8) { 6554 drm_dbg_kms(connector->dev, 6555 "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n", 6556 connector->base.id, connector->name, 6557 info->mso_pixel_overlap); 6558 info->mso_pixel_overlap = 8; 6559 } 6560 6561 drm_dbg_kms(connector->dev, 6562 "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n", 6563 connector->base.id, connector->name, 6564 info->mso_stream_count, info->mso_pixel_overlap); 6565 } 6566 6567 static void drm_update_mso(struct drm_connector *connector, 6568 const struct drm_edid *drm_edid) 6569 { 6570 const struct displayid_block *block; 6571 struct displayid_iter iter; 6572 6573 displayid_iter_edid_begin(drm_edid, &iter); 6574 displayid_iter_for_each(block, &iter) { 6575 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC) 6576 drm_parse_vesa_mso_data(connector, block); 6577 } 6578 displayid_iter_end(&iter); 6579 } 6580 6581 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset 6582 * all of the values which would have been set from EDID 6583 */ 6584 static void drm_reset_display_info(struct drm_connector *connector) 6585 { 6586 struct drm_display_info *info = &connector->display_info; 6587 6588 info->width_mm = 0; 6589 info->height_mm = 0; 6590 6591 info->bpc = 0; 6592 info->color_formats = 0; 6593 info->cea_rev = 0; 6594 info->max_tmds_clock = 0; 6595 info->dvi_dual = false; 6596 info->is_hdmi = false; 6597 info->has_audio = false; 6598 info->has_hdmi_infoframe = false; 6599 info->rgb_quant_range_selectable = false; 6600 memset(&info->hdmi, 0, sizeof(info->hdmi)); 6601 memset(&info->hdr_sink_metadata, 0, sizeof(info->hdr_sink_metadata)); 6602 6603 info->edid_hdmi_rgb444_dc_modes = 0; 6604 info->edid_hdmi_ycbcr444_dc_modes = 0; 6605 6606 info->non_desktop = 0; 6607 memset(&info->monitor_range, 0, sizeof(info->monitor_range)); 6608 memset(&info->luminance_range, 0, sizeof(info->luminance_range)); 6609 6610 info->mso_stream_count = 0; 6611 info->mso_pixel_overlap = 0; 6612 info->max_dsc_bpp = 0; 6613 6614 kfree(info->vics); 6615 info->vics = NULL; 6616 info->vics_len = 0; 6617 6618 info->quirks = 0; 6619 6620 info->source_physical_address = CEC_PHYS_ADDR_INVALID; 6621 } 6622 6623 static void update_displayid_info(struct drm_connector *connector, 6624 const struct drm_edid *drm_edid) 6625 { 6626 struct drm_display_info *info = &connector->display_info; 6627 const struct displayid_block *block; 6628 struct displayid_iter iter; 6629 6630 displayid_iter_edid_begin(drm_edid, &iter); 6631 displayid_iter_for_each(block, &iter) { 6632 drm_dbg_kms(connector->dev, 6633 "[CONNECTOR:%d:%s] DisplayID extension version 0x%02x, primary use 0x%02x\n", 6634 connector->base.id, connector->name, 6635 displayid_version(&iter), 6636 displayid_primary_use(&iter)); 6637 if (displayid_version(&iter) == DISPLAY_ID_STRUCTURE_VER_20 && 6638 (displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_VR || 6639 displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_AR)) 6640 info->non_desktop = true; 6641 6642 /* 6643 * We're only interested in the base section here, no need to 6644 * iterate further. 6645 */ 6646 break; 6647 } 6648 displayid_iter_end(&iter); 6649 } 6650 6651 static void update_display_info(struct drm_connector *connector, 6652 const struct drm_edid *drm_edid) 6653 { 6654 struct drm_display_info *info = &connector->display_info; 6655 const struct edid *edid; 6656 6657 drm_reset_display_info(connector); 6658 clear_eld(connector); 6659 6660 if (!drm_edid) 6661 return; 6662 6663 edid = drm_edid->edid; 6664 6665 info->quirks = edid_get_quirks(drm_edid); 6666 6667 info->width_mm = edid->width_cm * 10; 6668 info->height_mm = edid->height_cm * 10; 6669 6670 drm_get_monitor_range(connector, drm_edid); 6671 6672 if (edid->revision < 3) 6673 goto out; 6674 6675 if (!drm_edid_is_digital(drm_edid)) 6676 goto out; 6677 6678 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 6679 drm_parse_cea_ext(connector, drm_edid); 6680 6681 update_displayid_info(connector, drm_edid); 6682 6683 /* 6684 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 6685 * 6686 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 6687 * tells us to assume 8 bpc color depth if the EDID doesn't have 6688 * extensions which tell otherwise. 6689 */ 6690 if (info->bpc == 0 && edid->revision == 3 && 6691 edid->input & DRM_EDID_DIGITAL_DFP_1_X) { 6692 info->bpc = 8; 6693 drm_dbg_kms(connector->dev, 6694 "[CONNECTOR:%d:%s] Assigning DFP sink color depth as %d bpc.\n", 6695 connector->base.id, connector->name, info->bpc); 6696 } 6697 6698 /* Only defined for 1.4 with digital displays */ 6699 if (edid->revision < 4) 6700 goto out; 6701 6702 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 6703 case DRM_EDID_DIGITAL_DEPTH_6: 6704 info->bpc = 6; 6705 break; 6706 case DRM_EDID_DIGITAL_DEPTH_8: 6707 info->bpc = 8; 6708 break; 6709 case DRM_EDID_DIGITAL_DEPTH_10: 6710 info->bpc = 10; 6711 break; 6712 case DRM_EDID_DIGITAL_DEPTH_12: 6713 info->bpc = 12; 6714 break; 6715 case DRM_EDID_DIGITAL_DEPTH_14: 6716 info->bpc = 14; 6717 break; 6718 case DRM_EDID_DIGITAL_DEPTH_16: 6719 info->bpc = 16; 6720 break; 6721 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 6722 default: 6723 info->bpc = 0; 6724 break; 6725 } 6726 6727 drm_dbg_kms(connector->dev, 6728 "[CONNECTOR:%d:%s] Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 6729 connector->base.id, connector->name, info->bpc); 6730 6731 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 6732 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444; 6733 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 6734 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422; 6735 6736 drm_update_mso(connector, drm_edid); 6737 6738 out: 6739 if (info->quirks & EDID_QUIRK_NON_DESKTOP) { 6740 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Non-desktop display%s\n", 6741 connector->base.id, connector->name, 6742 info->non_desktop ? " (redundant quirk)" : ""); 6743 info->non_desktop = true; 6744 } 6745 6746 if (info->quirks & EDID_QUIRK_CAP_DSC_15BPP) 6747 info->max_dsc_bpp = 15; 6748 6749 if (info->quirks & EDID_QUIRK_FORCE_6BPC) 6750 info->bpc = 6; 6751 6752 if (info->quirks & EDID_QUIRK_FORCE_8BPC) 6753 info->bpc = 8; 6754 6755 if (info->quirks & EDID_QUIRK_FORCE_10BPC) 6756 info->bpc = 10; 6757 6758 if (info->quirks & EDID_QUIRK_FORCE_12BPC) 6759 info->bpc = 12; 6760 6761 /* Depends on info->cea_rev set by drm_parse_cea_ext() above */ 6762 drm_edid_to_eld(connector, drm_edid); 6763 } 6764 6765 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 6766 const struct displayid_detailed_timings_1 *timings, 6767 bool type_7) 6768 { 6769 struct drm_display_mode *mode; 6770 unsigned int pixel_clock = (timings->pixel_clock[0] | 6771 (timings->pixel_clock[1] << 8) | 6772 (timings->pixel_clock[2] << 16)) + 1; 6773 unsigned int hactive = le16_to_cpu(timings->hactive) + 1; 6774 unsigned int hblank = le16_to_cpu(timings->hblank) + 1; 6775 unsigned int hsync = (le16_to_cpu(timings->hsync) & 0x7fff) + 1; 6776 unsigned int hsync_width = le16_to_cpu(timings->hsw) + 1; 6777 unsigned int vactive = le16_to_cpu(timings->vactive) + 1; 6778 unsigned int vblank = le16_to_cpu(timings->vblank) + 1; 6779 unsigned int vsync = (le16_to_cpu(timings->vsync) & 0x7fff) + 1; 6780 unsigned int vsync_width = le16_to_cpu(timings->vsw) + 1; 6781 bool hsync_positive = le16_to_cpu(timings->hsync) & (1 << 15); 6782 bool vsync_positive = le16_to_cpu(timings->vsync) & (1 << 15); 6783 6784 mode = drm_mode_create(dev); 6785 if (!mode) 6786 return NULL; 6787 6788 /* resolution is kHz for type VII, and 10 kHz for type I */ 6789 mode->clock = type_7 ? pixel_clock : pixel_clock * 10; 6790 mode->hdisplay = hactive; 6791 mode->hsync_start = mode->hdisplay + hsync; 6792 mode->hsync_end = mode->hsync_start + hsync_width; 6793 mode->htotal = mode->hdisplay + hblank; 6794 6795 mode->vdisplay = vactive; 6796 mode->vsync_start = mode->vdisplay + vsync; 6797 mode->vsync_end = mode->vsync_start + vsync_width; 6798 mode->vtotal = mode->vdisplay + vblank; 6799 6800 mode->flags = 0; 6801 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 6802 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 6803 mode->type = DRM_MODE_TYPE_DRIVER; 6804 6805 if (timings->flags & 0x80) 6806 mode->type |= DRM_MODE_TYPE_PREFERRED; 6807 drm_mode_set_name(mode); 6808 6809 return mode; 6810 } 6811 6812 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 6813 const struct displayid_block *block) 6814 { 6815 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 6816 int i; 6817 int num_timings; 6818 struct drm_display_mode *newmode; 6819 int num_modes = 0; 6820 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING; 6821 /* blocks must be multiple of 20 bytes length */ 6822 if (block->num_bytes % 20) 6823 return 0; 6824 6825 num_timings = block->num_bytes / 20; 6826 for (i = 0; i < num_timings; i++) { 6827 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 6828 6829 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7); 6830 if (!newmode) 6831 continue; 6832 6833 drm_mode_probed_add(connector, newmode); 6834 num_modes++; 6835 } 6836 return num_modes; 6837 } 6838 6839 static struct drm_display_mode *drm_mode_displayid_formula(struct drm_device *dev, 6840 const struct displayid_formula_timings_9 *timings, 6841 bool type_10) 6842 { 6843 struct drm_display_mode *mode; 6844 u16 hactive = le16_to_cpu(timings->hactive) + 1; 6845 u16 vactive = le16_to_cpu(timings->vactive) + 1; 6846 u8 timing_formula = timings->flags & 0x7; 6847 6848 /* TODO: support RB-v2 & RB-v3 */ 6849 if (timing_formula > 1) 6850 return NULL; 6851 6852 /* TODO: support video-optimized refresh rate */ 6853 if (timings->flags & (1 << 4)) 6854 drm_dbg_kms(dev, "Fractional vrefresh is not implemented, proceeding with non-video-optimized refresh rate"); 6855 6856 mode = drm_cvt_mode(dev, hactive, vactive, timings->vrefresh + 1, timing_formula == 1, false, false); 6857 if (!mode) 6858 return NULL; 6859 6860 /* TODO: interpret S3D flags */ 6861 6862 mode->type = DRM_MODE_TYPE_DRIVER; 6863 drm_mode_set_name(mode); 6864 6865 return mode; 6866 } 6867 6868 static int add_displayid_formula_modes(struct drm_connector *connector, 6869 const struct displayid_block *block) 6870 { 6871 const struct displayid_formula_timing_block *formula_block = (struct displayid_formula_timing_block *)block; 6872 int num_timings; 6873 struct drm_display_mode *newmode; 6874 int num_modes = 0; 6875 bool type_10 = block->tag == DATA_BLOCK_2_TYPE_10_FORMULA_TIMING; 6876 int timing_size = 6 + ((formula_block->base.rev & 0x70) >> 4); 6877 6878 /* extended blocks are not supported yet */ 6879 if (timing_size != 6) 6880 return 0; 6881 6882 if (block->num_bytes % timing_size) 6883 return 0; 6884 6885 num_timings = block->num_bytes / timing_size; 6886 for (int i = 0; i < num_timings; i++) { 6887 const struct displayid_formula_timings_9 *timings = &formula_block->timings[i]; 6888 6889 newmode = drm_mode_displayid_formula(connector->dev, timings, type_10); 6890 if (!newmode) 6891 continue; 6892 6893 drm_mode_probed_add(connector, newmode); 6894 num_modes++; 6895 } 6896 return num_modes; 6897 } 6898 6899 static int add_displayid_detailed_modes(struct drm_connector *connector, 6900 const struct drm_edid *drm_edid) 6901 { 6902 const struct displayid_block *block; 6903 struct displayid_iter iter; 6904 int num_modes = 0; 6905 6906 displayid_iter_edid_begin(drm_edid, &iter); 6907 displayid_iter_for_each(block, &iter) { 6908 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING || 6909 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING) 6910 num_modes += add_displayid_detailed_1_modes(connector, block); 6911 else if (block->tag == DATA_BLOCK_2_TYPE_9_FORMULA_TIMING || 6912 block->tag == DATA_BLOCK_2_TYPE_10_FORMULA_TIMING) 6913 num_modes += add_displayid_formula_modes(connector, block); 6914 } 6915 displayid_iter_end(&iter); 6916 6917 return num_modes; 6918 } 6919 6920 static int _drm_edid_connector_add_modes(struct drm_connector *connector, 6921 const struct drm_edid *drm_edid) 6922 { 6923 const struct drm_display_info *info = &connector->display_info; 6924 int num_modes = 0; 6925 6926 if (!drm_edid) 6927 return 0; 6928 6929 /* 6930 * EDID spec says modes should be preferred in this order: 6931 * - preferred detailed mode 6932 * - other detailed modes from base block 6933 * - detailed modes from extension blocks 6934 * - CVT 3-byte code modes 6935 * - standard timing codes 6936 * - established timing codes 6937 * - modes inferred from GTF or CVT range information 6938 * 6939 * We get this pretty much right. 6940 * 6941 * XXX order for additional mode types in extension blocks? 6942 */ 6943 num_modes += add_detailed_modes(connector, drm_edid); 6944 num_modes += add_cvt_modes(connector, drm_edid); 6945 num_modes += add_standard_modes(connector, drm_edid); 6946 num_modes += add_established_modes(connector, drm_edid); 6947 num_modes += add_cea_modes(connector, drm_edid); 6948 num_modes += add_alternate_cea_modes(connector, drm_edid); 6949 num_modes += add_displayid_detailed_modes(connector, drm_edid); 6950 if (drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ) 6951 num_modes += add_inferred_modes(connector, drm_edid); 6952 6953 if (info->quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 6954 edid_fixup_preferred(connector); 6955 6956 return num_modes; 6957 } 6958 6959 static void _drm_update_tile_info(struct drm_connector *connector, 6960 const struct drm_edid *drm_edid); 6961 6962 static int _drm_edid_connector_property_update(struct drm_connector *connector, 6963 const struct drm_edid *drm_edid) 6964 { 6965 struct drm_device *dev = connector->dev; 6966 int ret; 6967 6968 if (connector->edid_blob_ptr) { 6969 const void *old_edid = connector->edid_blob_ptr->data; 6970 size_t old_edid_size = connector->edid_blob_ptr->length; 6971 6972 if (old_edid && !drm_edid_eq(drm_edid, old_edid, old_edid_size)) { 6973 connector->epoch_counter++; 6974 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n", 6975 connector->base.id, connector->name, 6976 connector->epoch_counter); 6977 } 6978 } 6979 6980 ret = drm_property_replace_global_blob(dev, 6981 &connector->edid_blob_ptr, 6982 drm_edid ? drm_edid->size : 0, 6983 drm_edid ? drm_edid->edid : NULL, 6984 &connector->base, 6985 dev->mode_config.edid_property); 6986 if (ret) { 6987 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n", 6988 connector->base.id, connector->name, ret); 6989 goto out; 6990 } 6991 6992 ret = drm_object_property_set_value(&connector->base, 6993 dev->mode_config.non_desktop_property, 6994 connector->display_info.non_desktop); 6995 if (ret) { 6996 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n", 6997 connector->base.id, connector->name, ret); 6998 goto out; 6999 } 7000 7001 ret = drm_connector_set_tile_property(connector); 7002 if (ret) { 7003 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n", 7004 connector->base.id, connector->name, ret); 7005 goto out; 7006 } 7007 7008 out: 7009 return ret; 7010 } 7011 7012 /* For sysfs edid show implementation */ 7013 ssize_t drm_edid_connector_property_show(struct drm_connector *connector, 7014 char *buf, loff_t off, size_t count) 7015 { 7016 const void *edid; 7017 size_t size; 7018 ssize_t ret = 0; 7019 7020 mutex_lock(&connector->dev->mode_config.mutex); 7021 7022 if (!connector->edid_blob_ptr) 7023 goto unlock; 7024 7025 edid = connector->edid_blob_ptr->data; 7026 size = connector->edid_blob_ptr->length; 7027 if (!edid) 7028 goto unlock; 7029 7030 if (off >= size) 7031 goto unlock; 7032 7033 if (off + count > size) 7034 count = size - off; 7035 7036 memcpy(buf, edid + off, count); 7037 7038 ret = count; 7039 unlock: 7040 mutex_unlock(&connector->dev->mode_config.mutex); 7041 7042 return ret; 7043 } 7044 7045 /** 7046 * drm_edid_connector_update - Update connector information from EDID 7047 * @connector: Connector 7048 * @drm_edid: EDID 7049 * 7050 * Update the connector display info, ELD, HDR metadata, relevant properties, 7051 * etc. from the passed in EDID. 7052 * 7053 * If EDID is NULL, reset the information. 7054 * 7055 * Must be called before calling drm_edid_connector_add_modes(). 7056 * 7057 * Return: 0 on success, negative error on errors. 7058 */ 7059 int drm_edid_connector_update(struct drm_connector *connector, 7060 const struct drm_edid *drm_edid) 7061 { 7062 update_display_info(connector, drm_edid); 7063 7064 _drm_update_tile_info(connector, drm_edid); 7065 7066 return _drm_edid_connector_property_update(connector, drm_edid); 7067 } 7068 EXPORT_SYMBOL(drm_edid_connector_update); 7069 7070 /** 7071 * drm_edid_connector_add_modes - Update probed modes from the EDID property 7072 * @connector: Connector 7073 * 7074 * Add the modes from the previously updated EDID property to the connector 7075 * probed modes list. 7076 * 7077 * drm_edid_connector_update() must have been called before this to update the 7078 * EDID property. 7079 * 7080 * Return: The number of modes added, or 0 if we couldn't find any. 7081 */ 7082 int drm_edid_connector_add_modes(struct drm_connector *connector) 7083 { 7084 const struct drm_edid *drm_edid = NULL; 7085 int count; 7086 7087 if (connector->edid_blob_ptr) 7088 drm_edid = drm_edid_alloc(connector->edid_blob_ptr->data, 7089 connector->edid_blob_ptr->length); 7090 7091 count = _drm_edid_connector_add_modes(connector, drm_edid); 7092 7093 drm_edid_free(drm_edid); 7094 7095 return count; 7096 } 7097 EXPORT_SYMBOL(drm_edid_connector_add_modes); 7098 7099 /** 7100 * drm_connector_update_edid_property - update the edid property of a connector 7101 * @connector: drm connector 7102 * @edid: new value of the edid property 7103 * 7104 * This function creates a new blob modeset object and assigns its id to the 7105 * connector's edid property. 7106 * Since we also parse tile information from EDID's displayID block, we also 7107 * set the connector's tile property here. See drm_connector_set_tile_property() 7108 * for more details. 7109 * 7110 * This function is deprecated. Use drm_edid_connector_update() instead. 7111 * 7112 * Returns: 7113 * Zero on success, negative errno on failure. 7114 */ 7115 int drm_connector_update_edid_property(struct drm_connector *connector, 7116 const struct edid *edid) 7117 { 7118 struct drm_edid drm_edid; 7119 7120 return drm_edid_connector_update(connector, drm_edid_legacy_init(&drm_edid, edid)); 7121 } 7122 EXPORT_SYMBOL(drm_connector_update_edid_property); 7123 7124 /** 7125 * drm_add_edid_modes - add modes from EDID data, if available 7126 * @connector: connector we're probing 7127 * @edid: EDID data 7128 * 7129 * Add the specified modes to the connector's mode list. Also fills out the 7130 * &drm_display_info structure and ELD in @connector with any information which 7131 * can be derived from the edid. 7132 * 7133 * This function is deprecated. Use drm_edid_connector_add_modes() instead. 7134 * 7135 * Return: The number of modes added or 0 if we couldn't find any. 7136 */ 7137 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 7138 { 7139 struct drm_edid _drm_edid; 7140 const struct drm_edid *drm_edid; 7141 7142 if (edid && !drm_edid_is_valid(edid)) { 7143 drm_warn(connector->dev, "[CONNECTOR:%d:%s] EDID invalid.\n", 7144 connector->base.id, connector->name); 7145 edid = NULL; 7146 } 7147 7148 drm_edid = drm_edid_legacy_init(&_drm_edid, edid); 7149 7150 update_display_info(connector, drm_edid); 7151 7152 return _drm_edid_connector_add_modes(connector, drm_edid); 7153 } 7154 EXPORT_SYMBOL(drm_add_edid_modes); 7155 7156 /** 7157 * drm_add_modes_noedid - add modes for the connectors without EDID 7158 * @connector: connector we're probing 7159 * @hdisplay: the horizontal display limit 7160 * @vdisplay: the vertical display limit 7161 * 7162 * Add the specified modes to the connector's mode list. Only when the 7163 * hdisplay/vdisplay is not beyond the given limit, it will be added. 7164 * 7165 * Return: The number of modes added or 0 if we couldn't find any. 7166 */ 7167 int drm_add_modes_noedid(struct drm_connector *connector, 7168 unsigned int hdisplay, unsigned int vdisplay) 7169 { 7170 int i, count = ARRAY_SIZE(drm_dmt_modes), num_modes = 0; 7171 struct drm_display_mode *mode; 7172 struct drm_device *dev = connector->dev; 7173 7174 for (i = 0; i < count; i++) { 7175 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 7176 7177 if (hdisplay && vdisplay) { 7178 /* 7179 * Only when two are valid, they will be used to check 7180 * whether the mode should be added to the mode list of 7181 * the connector. 7182 */ 7183 if (ptr->hdisplay > hdisplay || 7184 ptr->vdisplay > vdisplay) 7185 continue; 7186 } 7187 if (drm_mode_vrefresh(ptr) > 61) 7188 continue; 7189 mode = drm_mode_duplicate(dev, ptr); 7190 if (mode) { 7191 drm_mode_probed_add(connector, mode); 7192 num_modes++; 7193 } 7194 } 7195 return num_modes; 7196 } 7197 EXPORT_SYMBOL(drm_add_modes_noedid); 7198 7199 static bool is_hdmi2_sink(const struct drm_connector *connector) 7200 { 7201 /* 7202 * FIXME: sil-sii8620 doesn't have a connector around when 7203 * we need one, so we have to be prepared for a NULL connector. 7204 */ 7205 if (!connector) 7206 return true; 7207 7208 return connector->display_info.hdmi.scdc.supported || 7209 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420; 7210 } 7211 7212 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector, 7213 const struct drm_display_mode *mode) 7214 { 7215 bool has_hdmi_infoframe = connector ? 7216 connector->display_info.has_hdmi_infoframe : false; 7217 7218 if (!has_hdmi_infoframe) 7219 return 0; 7220 7221 /* No HDMI VIC when signalling 3D video format */ 7222 if (mode->flags & DRM_MODE_FLAG_3D_MASK) 7223 return 0; 7224 7225 return drm_match_hdmi_mode(mode); 7226 } 7227 7228 static u8 drm_mode_cea_vic(const struct drm_connector *connector, 7229 const struct drm_display_mode *mode) 7230 { 7231 /* 7232 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 7233 * we should send its VIC in vendor infoframes, else send the 7234 * VIC in AVI infoframes. Lets check if this mode is present in 7235 * HDMI 1.4b 4K modes 7236 */ 7237 if (drm_mode_hdmi_vic(connector, mode)) 7238 return 0; 7239 7240 return drm_match_cea_mode(mode); 7241 } 7242 7243 /* 7244 * Avoid sending VICs defined in HDMI 2.0 in AVI infoframes to sinks that 7245 * conform to HDMI 1.4. 7246 * 7247 * HDMI 1.4 (CTA-861-D) VIC range: [1..64] 7248 * HDMI 2.0 (CTA-861-F) VIC range: [1..107] 7249 * 7250 * If the sink lists the VIC in CTA VDB, assume it's fine, regardless of HDMI 7251 * version. 7252 */ 7253 static u8 vic_for_avi_infoframe(const struct drm_connector *connector, u8 vic) 7254 { 7255 if (!is_hdmi2_sink(connector) && vic > 64 && 7256 !cta_vdb_has_vic(connector, vic)) 7257 return 0; 7258 7259 return vic; 7260 } 7261 7262 /** 7263 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 7264 * data from a DRM display mode 7265 * @frame: HDMI AVI infoframe 7266 * @connector: the connector 7267 * @mode: DRM display mode 7268 * 7269 * Return: 0 on success or a negative error code on failure. 7270 */ 7271 int 7272 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 7273 const struct drm_connector *connector, 7274 const struct drm_display_mode *mode) 7275 { 7276 enum hdmi_picture_aspect picture_aspect; 7277 u8 vic, hdmi_vic; 7278 7279 if (!frame || !mode) 7280 return -EINVAL; 7281 7282 hdmi_avi_infoframe_init(frame); 7283 7284 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 7285 frame->pixel_repeat = 1; 7286 7287 vic = drm_mode_cea_vic(connector, mode); 7288 hdmi_vic = drm_mode_hdmi_vic(connector, mode); 7289 7290 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 7291 7292 /* 7293 * As some drivers don't support atomic, we can't use connector state. 7294 * So just initialize the frame with default values, just the same way 7295 * as it's done with other properties here. 7296 */ 7297 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; 7298 frame->itc = 0; 7299 7300 /* 7301 * Populate picture aspect ratio from either 7302 * user input (if specified) or from the CEA/HDMI mode lists. 7303 */ 7304 picture_aspect = mode->picture_aspect_ratio; 7305 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) { 7306 if (vic) 7307 picture_aspect = drm_get_cea_aspect_ratio(vic); 7308 else if (hdmi_vic) 7309 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic); 7310 } 7311 7312 /* 7313 * The infoframe can't convey anything but none, 4:3 7314 * and 16:9, so if the user has asked for anything else 7315 * we can only satisfy it by specifying the right VIC. 7316 */ 7317 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { 7318 if (vic) { 7319 if (picture_aspect != drm_get_cea_aspect_ratio(vic)) 7320 return -EINVAL; 7321 } else if (hdmi_vic) { 7322 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic)) 7323 return -EINVAL; 7324 } else { 7325 return -EINVAL; 7326 } 7327 7328 picture_aspect = HDMI_PICTURE_ASPECT_NONE; 7329 } 7330 7331 frame->video_code = vic_for_avi_infoframe(connector, vic); 7332 frame->picture_aspect = picture_aspect; 7333 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 7334 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 7335 7336 return 0; 7337 } 7338 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 7339 7340 /** 7341 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 7342 * quantization range information 7343 * @frame: HDMI AVI infoframe 7344 * @connector: the connector 7345 * @mode: DRM display mode 7346 * @rgb_quant_range: RGB quantization range (Q) 7347 */ 7348 void 7349 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 7350 const struct drm_connector *connector, 7351 const struct drm_display_mode *mode, 7352 enum hdmi_quantization_range rgb_quant_range) 7353 { 7354 const struct drm_display_info *info = &connector->display_info; 7355 7356 /* 7357 * CEA-861: 7358 * "A Source shall not send a non-zero Q value that does not correspond 7359 * to the default RGB Quantization Range for the transmitted Picture 7360 * unless the Sink indicates support for the Q bit in a Video 7361 * Capabilities Data Block." 7362 * 7363 * HDMI 2.0 recommends sending non-zero Q when it does match the 7364 * default RGB quantization range for the mode, even when QS=0. 7365 */ 7366 if (info->rgb_quant_range_selectable || 7367 rgb_quant_range == drm_default_rgb_quant_range(mode)) 7368 frame->quantization_range = rgb_quant_range; 7369 else 7370 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 7371 7372 /* 7373 * CEA-861-F: 7374 * "When transmitting any RGB colorimetry, the Source should set the 7375 * YQ-field to match the RGB Quantization Range being transmitted 7376 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 7377 * set YQ=1) and the Sink shall ignore the YQ-field." 7378 * 7379 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused 7380 * by non-zero YQ when receiving RGB. There doesn't seem to be any 7381 * good way to tell which version of CEA-861 the sink supports, so 7382 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based 7383 * on CEA-861-F. 7384 */ 7385 if (!is_hdmi2_sink(connector) || 7386 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 7387 frame->ycc_quantization_range = 7388 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 7389 else 7390 frame->ycc_quantization_range = 7391 HDMI_YCC_QUANTIZATION_RANGE_FULL; 7392 } 7393 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 7394 7395 static enum hdmi_3d_structure 7396 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 7397 { 7398 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 7399 7400 switch (layout) { 7401 case DRM_MODE_FLAG_3D_FRAME_PACKING: 7402 return HDMI_3D_STRUCTURE_FRAME_PACKING; 7403 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 7404 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 7405 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 7406 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 7407 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 7408 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 7409 case DRM_MODE_FLAG_3D_L_DEPTH: 7410 return HDMI_3D_STRUCTURE_L_DEPTH; 7411 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 7412 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 7413 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 7414 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 7415 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 7416 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 7417 default: 7418 return HDMI_3D_STRUCTURE_INVALID; 7419 } 7420 } 7421 7422 /** 7423 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 7424 * data from a DRM display mode 7425 * @frame: HDMI vendor infoframe 7426 * @connector: the connector 7427 * @mode: DRM display mode 7428 * 7429 * Note that there's is a need to send HDMI vendor infoframes only when using a 7430 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 7431 * function will return -EINVAL, error that can be safely ignored. 7432 * 7433 * Return: 0 on success or a negative error code on failure. 7434 */ 7435 int 7436 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 7437 const struct drm_connector *connector, 7438 const struct drm_display_mode *mode) 7439 { 7440 /* 7441 * FIXME: sil-sii8620 doesn't have a connector around when 7442 * we need one, so we have to be prepared for a NULL connector. 7443 */ 7444 bool has_hdmi_infoframe = connector ? 7445 connector->display_info.has_hdmi_infoframe : false; 7446 int err; 7447 7448 if (!frame || !mode) 7449 return -EINVAL; 7450 7451 if (!has_hdmi_infoframe) 7452 return -EINVAL; 7453 7454 err = hdmi_vendor_infoframe_init(frame); 7455 if (err < 0) 7456 return err; 7457 7458 /* 7459 * Even if it's not absolutely necessary to send the infoframe 7460 * (ie.vic==0 and s3d_struct==0) we will still send it if we 7461 * know that the sink can handle it. This is based on a 7462 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks 7463 * have trouble realizing that they should switch from 3D to 2D 7464 * mode if the source simply stops sending the infoframe when 7465 * it wants to switch from 3D to 2D. 7466 */ 7467 frame->vic = drm_mode_hdmi_vic(connector, mode); 7468 frame->s3d_struct = s3d_structure_from_display_mode(mode); 7469 7470 return 0; 7471 } 7472 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 7473 7474 static void drm_parse_tiled_block(struct drm_connector *connector, 7475 const struct displayid_block *block) 7476 { 7477 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 7478 u16 w, h; 7479 u8 tile_v_loc, tile_h_loc; 7480 u8 num_v_tile, num_h_tile; 7481 struct drm_tile_group *tg; 7482 7483 w = tile->tile_size[0] | tile->tile_size[1] << 8; 7484 h = tile->tile_size[2] | tile->tile_size[3] << 8; 7485 7486 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 7487 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 7488 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 7489 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 7490 7491 connector->has_tile = true; 7492 if (tile->tile_cap & 0x80) 7493 connector->tile_is_single_monitor = true; 7494 7495 connector->num_h_tile = num_h_tile + 1; 7496 connector->num_v_tile = num_v_tile + 1; 7497 connector->tile_h_loc = tile_h_loc; 7498 connector->tile_v_loc = tile_v_loc; 7499 connector->tile_h_size = w + 1; 7500 connector->tile_v_size = h + 1; 7501 7502 drm_dbg_kms(connector->dev, 7503 "[CONNECTOR:%d:%s] tile cap 0x%x, size %dx%d, num tiles %dx%d, location %dx%d, vend %c%c%c", 7504 connector->base.id, connector->name, 7505 tile->tile_cap, 7506 connector->tile_h_size, connector->tile_v_size, 7507 connector->num_h_tile, connector->num_v_tile, 7508 connector->tile_h_loc, connector->tile_v_loc, 7509 tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 7510 7511 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 7512 if (!tg) 7513 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 7514 if (!tg) 7515 return; 7516 7517 if (connector->tile_group != tg) { 7518 /* if we haven't got a pointer, 7519 take the reference, drop ref to old tile group */ 7520 if (connector->tile_group) 7521 drm_mode_put_tile_group(connector->dev, connector->tile_group); 7522 connector->tile_group = tg; 7523 } else { 7524 /* if same tile group, then release the ref we just took. */ 7525 drm_mode_put_tile_group(connector->dev, tg); 7526 } 7527 } 7528 7529 static bool displayid_is_tiled_block(const struct displayid_iter *iter, 7530 const struct displayid_block *block) 7531 { 7532 return (displayid_version(iter) < DISPLAY_ID_STRUCTURE_VER_20 && 7533 block->tag == DATA_BLOCK_TILED_DISPLAY) || 7534 (displayid_version(iter) == DISPLAY_ID_STRUCTURE_VER_20 && 7535 block->tag == DATA_BLOCK_2_TILED_DISPLAY_TOPOLOGY); 7536 } 7537 7538 static void _drm_update_tile_info(struct drm_connector *connector, 7539 const struct drm_edid *drm_edid) 7540 { 7541 const struct displayid_block *block; 7542 struct displayid_iter iter; 7543 7544 connector->has_tile = false; 7545 7546 displayid_iter_edid_begin(drm_edid, &iter); 7547 displayid_iter_for_each(block, &iter) { 7548 if (displayid_is_tiled_block(&iter, block)) 7549 drm_parse_tiled_block(connector, block); 7550 } 7551 displayid_iter_end(&iter); 7552 7553 if (!connector->has_tile && connector->tile_group) { 7554 drm_mode_put_tile_group(connector->dev, connector->tile_group); 7555 connector->tile_group = NULL; 7556 } 7557 } 7558 7559 /** 7560 * drm_edid_is_digital - is digital? 7561 * @drm_edid: The EDID 7562 * 7563 * Return true if input is digital. 7564 */ 7565 bool drm_edid_is_digital(const struct drm_edid *drm_edid) 7566 { 7567 return drm_edid && drm_edid->edid && 7568 drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL; 7569 } 7570 EXPORT_SYMBOL(drm_edid_is_digital); 7571