1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 31 #include <linux/bitfield.h> 32 #include <linux/cec.h> 33 #include <linux/hdmi.h> 34 #include <linux/i2c.h> 35 #include <linux/kernel.h> 36 #include <linux/module.h> 37 #include <linux/pci.h> 38 #include <linux/slab.h> 39 #include <linux/vga_switcheroo.h> 40 41 #include <drm/drm_displayid.h> 42 #include <drm/drm_drv.h> 43 #include <drm/drm_edid.h> 44 #include <drm/drm_eld.h> 45 #include <drm/drm_encoder.h> 46 #include <drm/drm_print.h> 47 48 #include "drm_crtc_internal.h" 49 #include "drm_internal.h" 50 51 static int oui(u8 first, u8 second, u8 third) 52 { 53 return (first << 16) | (second << 8) | third; 54 } 55 56 #define EDID_EST_TIMINGS 16 57 #define EDID_STD_TIMINGS 8 58 #define EDID_DETAILED_TIMINGS 4 59 60 /* 61 * EDID blocks out in the wild have a variety of bugs, try to collect 62 * them here (note that userspace may work around broken monitors first, 63 * but fixes should make their way here so that the kernel "just works" 64 * on as many displays as possible). 65 */ 66 67 /* First detailed mode wrong, use largest 60Hz mode */ 68 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 69 /* Reported 135MHz pixel clock is too high, needs adjustment */ 70 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 71 /* Prefer the largest mode at 75 Hz */ 72 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 73 /* Detail timing is in cm not mm */ 74 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 75 /* Detailed timing descriptors have bogus size values, so just take the 76 * maximum size and use that. 77 */ 78 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 79 /* use +hsync +vsync for detailed mode */ 80 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 81 /* Force reduced-blanking timings for detailed modes */ 82 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 83 /* Force 8bpc */ 84 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 85 /* Force 12bpc */ 86 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 87 /* Force 6bpc */ 88 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 89 /* Force 10bpc */ 90 #define EDID_QUIRK_FORCE_10BPC (1 << 11) 91 /* Non desktop display (i.e. HMD) */ 92 #define EDID_QUIRK_NON_DESKTOP (1 << 12) 93 /* Cap the DSC target bitrate to 15bpp */ 94 #define EDID_QUIRK_CAP_DSC_15BPP (1 << 13) 95 96 #define MICROSOFT_IEEE_OUI 0xca125c 97 98 struct detailed_mode_closure { 99 struct drm_connector *connector; 100 const struct drm_edid *drm_edid; 101 bool preferred; 102 int modes; 103 }; 104 105 #define LEVEL_DMT 0 106 #define LEVEL_GTF 1 107 #define LEVEL_GTF2 2 108 #define LEVEL_CVT 3 109 110 #define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \ 111 { \ 112 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \ 113 product_id), \ 114 .quirks = _quirks \ 115 } 116 117 static const struct edid_quirk { 118 u32 panel_id; 119 u32 quirks; 120 } edid_quirk_list[] = { 121 /* Acer AL1706 */ 122 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60), 123 /* Acer F51 */ 124 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60), 125 126 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 127 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC), 128 129 /* BenQ GW2765 */ 130 EDID_QUIRK('B', 'N', 'Q', 0x78d6, EDID_QUIRK_FORCE_8BPC), 131 132 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */ 133 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC), 134 135 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 136 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC), 137 138 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ 139 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC), 140 141 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ 142 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC), 143 144 /* Belinea 10 15 55 */ 145 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60), 146 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60), 147 148 /* Envision Peripherals, Inc. EN-7100e */ 149 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH), 150 /* Envision EN2028 */ 151 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60), 152 153 /* Funai Electronics PM36B */ 154 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 | 155 EDID_QUIRK_DETAILED_IN_CM), 156 157 /* LG 27GP950 */ 158 EDID_QUIRK('G', 'S', 'M', 0x5bbf, EDID_QUIRK_CAP_DSC_15BPP), 159 160 /* LG 27GN950 */ 161 EDID_QUIRK('G', 'S', 'M', 0x5b9a, EDID_QUIRK_CAP_DSC_15BPP), 162 163 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 164 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC), 165 166 /* LG Philips LCD LP154W01-A5 */ 167 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE), 168 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE), 169 170 /* Samsung SyncMaster 205BW. Note: irony */ 171 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP), 172 /* Samsung SyncMaster 22[5-6]BW */ 173 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60), 174 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60), 175 176 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 177 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC), 178 179 /* ViewSonic VA2026w */ 180 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING), 181 182 /* Medion MD 30217 PG */ 183 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75), 184 185 /* Lenovo G50 */ 186 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC), 187 188 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 189 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC), 190 191 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 192 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC), 193 194 /* Valve Index Headset */ 195 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP), 196 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP), 197 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP), 198 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP), 199 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP), 200 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP), 201 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP), 202 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP), 203 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP), 204 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP), 205 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP), 206 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP), 207 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP), 208 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP), 209 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP), 210 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP), 211 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP), 212 213 /* HTC Vive and Vive Pro VR Headsets */ 214 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP), 215 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP), 216 217 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */ 218 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP), 219 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP), 220 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP), 221 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP), 222 223 /* Windows Mixed Reality Headsets */ 224 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP), 225 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP), 226 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP), 227 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP), 228 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP), 229 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP), 230 231 /* Sony PlayStation VR Headset */ 232 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP), 233 234 /* Sensics VR Headsets */ 235 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP), 236 237 /* OSVR HDK and HDK2 VR Headsets */ 238 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP), 239 EDID_QUIRK('A', 'U', 'O', 0x1111, EDID_QUIRK_NON_DESKTOP), 240 }; 241 242 /* 243 * Autogenerated from the DMT spec. 244 * This table is copied from xfree86/modes/xf86EdidModes.c. 245 */ 246 static const struct drm_display_mode drm_dmt_modes[] = { 247 /* 0x01 - 640x350@85Hz */ 248 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 249 736, 832, 0, 350, 382, 385, 445, 0, 250 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 251 /* 0x02 - 640x400@85Hz */ 252 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 253 736, 832, 0, 400, 401, 404, 445, 0, 254 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 255 /* 0x03 - 720x400@85Hz */ 256 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 257 828, 936, 0, 400, 401, 404, 446, 0, 258 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 259 /* 0x04 - 640x480@60Hz */ 260 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 261 752, 800, 0, 480, 490, 492, 525, 0, 262 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 263 /* 0x05 - 640x480@72Hz */ 264 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 265 704, 832, 0, 480, 489, 492, 520, 0, 266 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 267 /* 0x06 - 640x480@75Hz */ 268 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 269 720, 840, 0, 480, 481, 484, 500, 0, 270 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 271 /* 0x07 - 640x480@85Hz */ 272 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 273 752, 832, 0, 480, 481, 484, 509, 0, 274 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 275 /* 0x08 - 800x600@56Hz */ 276 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 277 896, 1024, 0, 600, 601, 603, 625, 0, 278 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 279 /* 0x09 - 800x600@60Hz */ 280 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 281 968, 1056, 0, 600, 601, 605, 628, 0, 282 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 283 /* 0x0a - 800x600@72Hz */ 284 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 285 976, 1040, 0, 600, 637, 643, 666, 0, 286 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 287 /* 0x0b - 800x600@75Hz */ 288 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 289 896, 1056, 0, 600, 601, 604, 625, 0, 290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 291 /* 0x0c - 800x600@85Hz */ 292 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 293 896, 1048, 0, 600, 601, 604, 631, 0, 294 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 295 /* 0x0d - 800x600@120Hz RB */ 296 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 297 880, 960, 0, 600, 603, 607, 636, 0, 298 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 299 /* 0x0e - 848x480@60Hz */ 300 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 301 976, 1088, 0, 480, 486, 494, 517, 0, 302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 303 /* 0x0f - 1024x768@43Hz, interlace */ 304 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 305 1208, 1264, 0, 768, 768, 776, 817, 0, 306 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 307 DRM_MODE_FLAG_INTERLACE) }, 308 /* 0x10 - 1024x768@60Hz */ 309 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 310 1184, 1344, 0, 768, 771, 777, 806, 0, 311 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 312 /* 0x11 - 1024x768@70Hz */ 313 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 314 1184, 1328, 0, 768, 771, 777, 806, 0, 315 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 316 /* 0x12 - 1024x768@75Hz */ 317 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 318 1136, 1312, 0, 768, 769, 772, 800, 0, 319 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 320 /* 0x13 - 1024x768@85Hz */ 321 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 322 1168, 1376, 0, 768, 769, 772, 808, 0, 323 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 324 /* 0x14 - 1024x768@120Hz RB */ 325 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 326 1104, 1184, 0, 768, 771, 775, 813, 0, 327 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 328 /* 0x15 - 1152x864@75Hz */ 329 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 330 1344, 1600, 0, 864, 865, 868, 900, 0, 331 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 332 /* 0x55 - 1280x720@60Hz */ 333 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 334 1430, 1650, 0, 720, 725, 730, 750, 0, 335 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 336 /* 0x16 - 1280x768@60Hz RB */ 337 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 338 1360, 1440, 0, 768, 771, 778, 790, 0, 339 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 340 /* 0x17 - 1280x768@60Hz */ 341 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 342 1472, 1664, 0, 768, 771, 778, 798, 0, 343 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 344 /* 0x18 - 1280x768@75Hz */ 345 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 346 1488, 1696, 0, 768, 771, 778, 805, 0, 347 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 348 /* 0x19 - 1280x768@85Hz */ 349 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 350 1496, 1712, 0, 768, 771, 778, 809, 0, 351 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 352 /* 0x1a - 1280x768@120Hz RB */ 353 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 354 1360, 1440, 0, 768, 771, 778, 813, 0, 355 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 356 /* 0x1b - 1280x800@60Hz RB */ 357 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 358 1360, 1440, 0, 800, 803, 809, 823, 0, 359 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 360 /* 0x1c - 1280x800@60Hz */ 361 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 362 1480, 1680, 0, 800, 803, 809, 831, 0, 363 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 364 /* 0x1d - 1280x800@75Hz */ 365 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 366 1488, 1696, 0, 800, 803, 809, 838, 0, 367 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 368 /* 0x1e - 1280x800@85Hz */ 369 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 370 1496, 1712, 0, 800, 803, 809, 843, 0, 371 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 372 /* 0x1f - 1280x800@120Hz RB */ 373 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 374 1360, 1440, 0, 800, 803, 809, 847, 0, 375 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 376 /* 0x20 - 1280x960@60Hz */ 377 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 378 1488, 1800, 0, 960, 961, 964, 1000, 0, 379 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 380 /* 0x21 - 1280x960@85Hz */ 381 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 382 1504, 1728, 0, 960, 961, 964, 1011, 0, 383 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 384 /* 0x22 - 1280x960@120Hz RB */ 385 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 386 1360, 1440, 0, 960, 963, 967, 1017, 0, 387 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 388 /* 0x23 - 1280x1024@60Hz */ 389 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 390 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 391 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 392 /* 0x24 - 1280x1024@75Hz */ 393 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 394 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 395 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 396 /* 0x25 - 1280x1024@85Hz */ 397 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 398 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 399 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 400 /* 0x26 - 1280x1024@120Hz RB */ 401 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 402 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 403 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 404 /* 0x27 - 1360x768@60Hz */ 405 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 406 1536, 1792, 0, 768, 771, 777, 795, 0, 407 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 408 /* 0x28 - 1360x768@120Hz RB */ 409 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 410 1440, 1520, 0, 768, 771, 776, 813, 0, 411 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 412 /* 0x51 - 1366x768@60Hz */ 413 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 414 1579, 1792, 0, 768, 771, 774, 798, 0, 415 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 416 /* 0x56 - 1366x768@60Hz */ 417 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 418 1436, 1500, 0, 768, 769, 772, 800, 0, 419 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 420 /* 0x29 - 1400x1050@60Hz RB */ 421 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 422 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 423 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 424 /* 0x2a - 1400x1050@60Hz */ 425 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 426 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 427 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 428 /* 0x2b - 1400x1050@75Hz */ 429 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 430 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 431 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 432 /* 0x2c - 1400x1050@85Hz */ 433 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 434 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 435 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 436 /* 0x2d - 1400x1050@120Hz RB */ 437 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 438 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 439 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 440 /* 0x2e - 1440x900@60Hz RB */ 441 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 442 1520, 1600, 0, 900, 903, 909, 926, 0, 443 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 444 /* 0x2f - 1440x900@60Hz */ 445 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 446 1672, 1904, 0, 900, 903, 909, 934, 0, 447 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 448 /* 0x30 - 1440x900@75Hz */ 449 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 450 1688, 1936, 0, 900, 903, 909, 942, 0, 451 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 452 /* 0x31 - 1440x900@85Hz */ 453 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 454 1696, 1952, 0, 900, 903, 909, 948, 0, 455 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 456 /* 0x32 - 1440x900@120Hz RB */ 457 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 458 1520, 1600, 0, 900, 903, 909, 953, 0, 459 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 460 /* 0x53 - 1600x900@60Hz */ 461 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 462 1704, 1800, 0, 900, 901, 904, 1000, 0, 463 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 464 /* 0x33 - 1600x1200@60Hz */ 465 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 466 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 467 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 468 /* 0x34 - 1600x1200@65Hz */ 469 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 470 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 471 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 472 /* 0x35 - 1600x1200@70Hz */ 473 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 474 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 475 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 476 /* 0x36 - 1600x1200@75Hz */ 477 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 478 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 479 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 480 /* 0x37 - 1600x1200@85Hz */ 481 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 482 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 483 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 484 /* 0x38 - 1600x1200@120Hz RB */ 485 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 486 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 487 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 488 /* 0x39 - 1680x1050@60Hz RB */ 489 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 490 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 491 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 492 /* 0x3a - 1680x1050@60Hz */ 493 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 494 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 495 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 496 /* 0x3b - 1680x1050@75Hz */ 497 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 498 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 499 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 500 /* 0x3c - 1680x1050@85Hz */ 501 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 502 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 503 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 504 /* 0x3d - 1680x1050@120Hz RB */ 505 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 506 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 507 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 508 /* 0x3e - 1792x1344@60Hz */ 509 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 510 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 511 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 512 /* 0x3f - 1792x1344@75Hz */ 513 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 514 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 515 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 516 /* 0x40 - 1792x1344@120Hz RB */ 517 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 518 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 519 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 520 /* 0x41 - 1856x1392@60Hz */ 521 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 522 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 523 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 524 /* 0x42 - 1856x1392@75Hz */ 525 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 526 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 527 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 528 /* 0x43 - 1856x1392@120Hz RB */ 529 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 530 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 531 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 532 /* 0x52 - 1920x1080@60Hz */ 533 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 534 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 535 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 536 /* 0x44 - 1920x1200@60Hz RB */ 537 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 538 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 539 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 540 /* 0x45 - 1920x1200@60Hz */ 541 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 542 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 543 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 544 /* 0x46 - 1920x1200@75Hz */ 545 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 546 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 547 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 548 /* 0x47 - 1920x1200@85Hz */ 549 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 550 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 551 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 552 /* 0x48 - 1920x1200@120Hz RB */ 553 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 554 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 555 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 556 /* 0x49 - 1920x1440@60Hz */ 557 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 558 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 559 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 560 /* 0x4a - 1920x1440@75Hz */ 561 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 562 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 563 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 564 /* 0x4b - 1920x1440@120Hz RB */ 565 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 566 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 567 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 568 /* 0x54 - 2048x1152@60Hz */ 569 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 570 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 571 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 572 /* 0x4c - 2560x1600@60Hz RB */ 573 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 574 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 575 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 576 /* 0x4d - 2560x1600@60Hz */ 577 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 578 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 579 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 580 /* 0x4e - 2560x1600@75Hz */ 581 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 582 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 583 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 584 /* 0x4f - 2560x1600@85Hz */ 585 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 586 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 587 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 588 /* 0x50 - 2560x1600@120Hz RB */ 589 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 590 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 591 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 592 /* 0x57 - 4096x2160@60Hz RB */ 593 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 594 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 595 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 596 /* 0x58 - 4096x2160@59.94Hz RB */ 597 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 598 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 599 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 600 }; 601 602 /* 603 * These more or less come from the DMT spec. The 720x400 modes are 604 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 605 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 606 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 607 * mode. 608 * 609 * The DMT modes have been fact-checked; the rest are mild guesses. 610 */ 611 static const struct drm_display_mode edid_est_modes[] = { 612 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 613 968, 1056, 0, 600, 601, 605, 628, 0, 614 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 615 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 616 896, 1024, 0, 600, 601, 603, 625, 0, 617 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 618 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 619 720, 840, 0, 480, 481, 484, 500, 0, 620 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 621 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 622 704, 832, 0, 480, 489, 492, 520, 0, 623 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 624 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 625 768, 864, 0, 480, 483, 486, 525, 0, 626 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 627 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 628 752, 800, 0, 480, 490, 492, 525, 0, 629 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 630 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 631 846, 900, 0, 400, 421, 423, 449, 0, 632 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 633 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 634 846, 900, 0, 400, 412, 414, 449, 0, 635 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 636 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 637 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 638 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 639 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 640 1136, 1312, 0, 768, 769, 772, 800, 0, 641 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 642 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 643 1184, 1328, 0, 768, 771, 777, 806, 0, 644 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 645 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 646 1184, 1344, 0, 768, 771, 777, 806, 0, 647 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 648 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 649 1208, 1264, 0, 768, 768, 776, 817, 0, 650 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 651 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 652 928, 1152, 0, 624, 625, 628, 667, 0, 653 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 654 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 655 896, 1056, 0, 600, 601, 604, 625, 0, 656 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 657 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 658 976, 1040, 0, 600, 637, 643, 666, 0, 659 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 660 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 661 1344, 1600, 0, 864, 865, 868, 900, 0, 662 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 663 }; 664 665 struct minimode { 666 short w; 667 short h; 668 short r; 669 short rb; 670 }; 671 672 static const struct minimode est3_modes[] = { 673 /* byte 6 */ 674 { 640, 350, 85, 0 }, 675 { 640, 400, 85, 0 }, 676 { 720, 400, 85, 0 }, 677 { 640, 480, 85, 0 }, 678 { 848, 480, 60, 0 }, 679 { 800, 600, 85, 0 }, 680 { 1024, 768, 85, 0 }, 681 { 1152, 864, 75, 0 }, 682 /* byte 7 */ 683 { 1280, 768, 60, 1 }, 684 { 1280, 768, 60, 0 }, 685 { 1280, 768, 75, 0 }, 686 { 1280, 768, 85, 0 }, 687 { 1280, 960, 60, 0 }, 688 { 1280, 960, 85, 0 }, 689 { 1280, 1024, 60, 0 }, 690 { 1280, 1024, 85, 0 }, 691 /* byte 8 */ 692 { 1360, 768, 60, 0 }, 693 { 1440, 900, 60, 1 }, 694 { 1440, 900, 60, 0 }, 695 { 1440, 900, 75, 0 }, 696 { 1440, 900, 85, 0 }, 697 { 1400, 1050, 60, 1 }, 698 { 1400, 1050, 60, 0 }, 699 { 1400, 1050, 75, 0 }, 700 /* byte 9 */ 701 { 1400, 1050, 85, 0 }, 702 { 1680, 1050, 60, 1 }, 703 { 1680, 1050, 60, 0 }, 704 { 1680, 1050, 75, 0 }, 705 { 1680, 1050, 85, 0 }, 706 { 1600, 1200, 60, 0 }, 707 { 1600, 1200, 65, 0 }, 708 { 1600, 1200, 70, 0 }, 709 /* byte 10 */ 710 { 1600, 1200, 75, 0 }, 711 { 1600, 1200, 85, 0 }, 712 { 1792, 1344, 60, 0 }, 713 { 1792, 1344, 75, 0 }, 714 { 1856, 1392, 60, 0 }, 715 { 1856, 1392, 75, 0 }, 716 { 1920, 1200, 60, 1 }, 717 { 1920, 1200, 60, 0 }, 718 /* byte 11 */ 719 { 1920, 1200, 75, 0 }, 720 { 1920, 1200, 85, 0 }, 721 { 1920, 1440, 60, 0 }, 722 { 1920, 1440, 75, 0 }, 723 }; 724 725 static const struct minimode extra_modes[] = { 726 { 1024, 576, 60, 0 }, 727 { 1366, 768, 60, 0 }, 728 { 1600, 900, 60, 0 }, 729 { 1680, 945, 60, 0 }, 730 { 1920, 1080, 60, 0 }, 731 { 2048, 1152, 60, 0 }, 732 { 2048, 1536, 60, 0 }, 733 }; 734 735 /* 736 * From CEA/CTA-861 spec. 737 * 738 * Do not access directly, instead always use cea_mode_for_vic(). 739 */ 740 static const struct drm_display_mode edid_cea_modes_1[] = { 741 /* 1 - 640x480@60Hz 4:3 */ 742 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 743 752, 800, 0, 480, 490, 492, 525, 0, 744 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 745 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 746 /* 2 - 720x480@60Hz 4:3 */ 747 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 748 798, 858, 0, 480, 489, 495, 525, 0, 749 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 750 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 751 /* 3 - 720x480@60Hz 16:9 */ 752 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 753 798, 858, 0, 480, 489, 495, 525, 0, 754 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 755 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 756 /* 4 - 1280x720@60Hz 16:9 */ 757 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 758 1430, 1650, 0, 720, 725, 730, 750, 0, 759 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 760 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 761 /* 5 - 1920x1080i@60Hz 16:9 */ 762 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 763 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 764 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 765 DRM_MODE_FLAG_INTERLACE), 766 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 767 /* 6 - 720(1440)x480i@60Hz 4:3 */ 768 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 769 801, 858, 0, 480, 488, 494, 525, 0, 770 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 771 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 772 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 773 /* 7 - 720(1440)x480i@60Hz 16:9 */ 774 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 775 801, 858, 0, 480, 488, 494, 525, 0, 776 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 777 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 778 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 779 /* 8 - 720(1440)x240@60Hz 4:3 */ 780 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 781 801, 858, 0, 240, 244, 247, 262, 0, 782 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 783 DRM_MODE_FLAG_DBLCLK), 784 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 785 /* 9 - 720(1440)x240@60Hz 16:9 */ 786 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 787 801, 858, 0, 240, 244, 247, 262, 0, 788 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 789 DRM_MODE_FLAG_DBLCLK), 790 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 791 /* 10 - 2880x480i@60Hz 4:3 */ 792 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 793 3204, 3432, 0, 480, 488, 494, 525, 0, 794 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 795 DRM_MODE_FLAG_INTERLACE), 796 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 797 /* 11 - 2880x480i@60Hz 16:9 */ 798 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 799 3204, 3432, 0, 480, 488, 494, 525, 0, 800 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 801 DRM_MODE_FLAG_INTERLACE), 802 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 803 /* 12 - 2880x240@60Hz 4:3 */ 804 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 805 3204, 3432, 0, 240, 244, 247, 262, 0, 806 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 807 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 808 /* 13 - 2880x240@60Hz 16:9 */ 809 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 810 3204, 3432, 0, 240, 244, 247, 262, 0, 811 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 812 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 813 /* 14 - 1440x480@60Hz 4:3 */ 814 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 815 1596, 1716, 0, 480, 489, 495, 525, 0, 816 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 817 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 818 /* 15 - 1440x480@60Hz 16:9 */ 819 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 820 1596, 1716, 0, 480, 489, 495, 525, 0, 821 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 822 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 823 /* 16 - 1920x1080@60Hz 16:9 */ 824 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 825 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 826 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 827 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 828 /* 17 - 720x576@50Hz 4:3 */ 829 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 830 796, 864, 0, 576, 581, 586, 625, 0, 831 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 832 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 833 /* 18 - 720x576@50Hz 16:9 */ 834 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 835 796, 864, 0, 576, 581, 586, 625, 0, 836 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 837 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 838 /* 19 - 1280x720@50Hz 16:9 */ 839 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 840 1760, 1980, 0, 720, 725, 730, 750, 0, 841 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 842 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 843 /* 20 - 1920x1080i@50Hz 16:9 */ 844 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 845 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 846 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 847 DRM_MODE_FLAG_INTERLACE), 848 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 849 /* 21 - 720(1440)x576i@50Hz 4:3 */ 850 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 851 795, 864, 0, 576, 580, 586, 625, 0, 852 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 853 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 854 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 855 /* 22 - 720(1440)x576i@50Hz 16:9 */ 856 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 857 795, 864, 0, 576, 580, 586, 625, 0, 858 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 859 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 860 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 861 /* 23 - 720(1440)x288@50Hz 4:3 */ 862 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 863 795, 864, 0, 288, 290, 293, 312, 0, 864 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 865 DRM_MODE_FLAG_DBLCLK), 866 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 867 /* 24 - 720(1440)x288@50Hz 16:9 */ 868 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 869 795, 864, 0, 288, 290, 293, 312, 0, 870 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 871 DRM_MODE_FLAG_DBLCLK), 872 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 873 /* 25 - 2880x576i@50Hz 4:3 */ 874 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 875 3180, 3456, 0, 576, 580, 586, 625, 0, 876 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 877 DRM_MODE_FLAG_INTERLACE), 878 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 879 /* 26 - 2880x576i@50Hz 16:9 */ 880 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 881 3180, 3456, 0, 576, 580, 586, 625, 0, 882 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 883 DRM_MODE_FLAG_INTERLACE), 884 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 885 /* 27 - 2880x288@50Hz 4:3 */ 886 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 887 3180, 3456, 0, 288, 290, 293, 312, 0, 888 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 889 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 890 /* 28 - 2880x288@50Hz 16:9 */ 891 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 892 3180, 3456, 0, 288, 290, 293, 312, 0, 893 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 894 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 895 /* 29 - 1440x576@50Hz 4:3 */ 896 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 897 1592, 1728, 0, 576, 581, 586, 625, 0, 898 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 899 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 900 /* 30 - 1440x576@50Hz 16:9 */ 901 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 902 1592, 1728, 0, 576, 581, 586, 625, 0, 903 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 904 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 905 /* 31 - 1920x1080@50Hz 16:9 */ 906 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 907 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 908 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 909 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 910 /* 32 - 1920x1080@24Hz 16:9 */ 911 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 912 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 913 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 914 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 915 /* 33 - 1920x1080@25Hz 16:9 */ 916 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 917 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 918 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 919 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 920 /* 34 - 1920x1080@30Hz 16:9 */ 921 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 922 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 923 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 924 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 925 /* 35 - 2880x480@60Hz 4:3 */ 926 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 927 3192, 3432, 0, 480, 489, 495, 525, 0, 928 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 929 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 930 /* 36 - 2880x480@60Hz 16:9 */ 931 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 932 3192, 3432, 0, 480, 489, 495, 525, 0, 933 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 934 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 935 /* 37 - 2880x576@50Hz 4:3 */ 936 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 937 3184, 3456, 0, 576, 581, 586, 625, 0, 938 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 939 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 940 /* 38 - 2880x576@50Hz 16:9 */ 941 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 942 3184, 3456, 0, 576, 581, 586, 625, 0, 943 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 944 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 945 /* 39 - 1920x1080i@50Hz 16:9 */ 946 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 947 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 948 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 949 DRM_MODE_FLAG_INTERLACE), 950 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 951 /* 40 - 1920x1080i@100Hz 16:9 */ 952 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 953 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 954 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 955 DRM_MODE_FLAG_INTERLACE), 956 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 957 /* 41 - 1280x720@100Hz 16:9 */ 958 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 959 1760, 1980, 0, 720, 725, 730, 750, 0, 960 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 961 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 962 /* 42 - 720x576@100Hz 4:3 */ 963 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 964 796, 864, 0, 576, 581, 586, 625, 0, 965 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 966 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 967 /* 43 - 720x576@100Hz 16:9 */ 968 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 969 796, 864, 0, 576, 581, 586, 625, 0, 970 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 971 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 972 /* 44 - 720(1440)x576i@100Hz 4:3 */ 973 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 974 795, 864, 0, 576, 580, 586, 625, 0, 975 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 976 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 977 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 978 /* 45 - 720(1440)x576i@100Hz 16:9 */ 979 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 980 795, 864, 0, 576, 580, 586, 625, 0, 981 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 982 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 983 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 984 /* 46 - 1920x1080i@120Hz 16:9 */ 985 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 986 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 987 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 988 DRM_MODE_FLAG_INTERLACE), 989 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 990 /* 47 - 1280x720@120Hz 16:9 */ 991 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 992 1430, 1650, 0, 720, 725, 730, 750, 0, 993 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 994 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 995 /* 48 - 720x480@120Hz 4:3 */ 996 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 997 798, 858, 0, 480, 489, 495, 525, 0, 998 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 999 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1000 /* 49 - 720x480@120Hz 16:9 */ 1001 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 1002 798, 858, 0, 480, 489, 495, 525, 0, 1003 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1004 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1005 /* 50 - 720(1440)x480i@120Hz 4:3 */ 1006 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 1007 801, 858, 0, 480, 488, 494, 525, 0, 1008 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1009 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1010 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1011 /* 51 - 720(1440)x480i@120Hz 16:9 */ 1012 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 1013 801, 858, 0, 480, 488, 494, 525, 0, 1014 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1015 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1016 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1017 /* 52 - 720x576@200Hz 4:3 */ 1018 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1019 796, 864, 0, 576, 581, 586, 625, 0, 1020 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1021 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1022 /* 53 - 720x576@200Hz 16:9 */ 1023 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1024 796, 864, 0, 576, 581, 586, 625, 0, 1025 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1026 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1027 /* 54 - 720(1440)x576i@200Hz 4:3 */ 1028 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1029 795, 864, 0, 576, 580, 586, 625, 0, 1030 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1031 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1032 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1033 /* 55 - 720(1440)x576i@200Hz 16:9 */ 1034 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1035 795, 864, 0, 576, 580, 586, 625, 0, 1036 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1037 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1038 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1039 /* 56 - 720x480@240Hz 4:3 */ 1040 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1041 798, 858, 0, 480, 489, 495, 525, 0, 1042 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1043 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1044 /* 57 - 720x480@240Hz 16:9 */ 1045 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1046 798, 858, 0, 480, 489, 495, 525, 0, 1047 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1048 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1049 /* 58 - 720(1440)x480i@240Hz 4:3 */ 1050 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1051 801, 858, 0, 480, 488, 494, 525, 0, 1052 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1053 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1054 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1055 /* 59 - 720(1440)x480i@240Hz 16:9 */ 1056 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1057 801, 858, 0, 480, 488, 494, 525, 0, 1058 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1059 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1060 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1061 /* 60 - 1280x720@24Hz 16:9 */ 1062 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1063 3080, 3300, 0, 720, 725, 730, 750, 0, 1064 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1065 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1066 /* 61 - 1280x720@25Hz 16:9 */ 1067 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1068 3740, 3960, 0, 720, 725, 730, 750, 0, 1069 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1070 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1071 /* 62 - 1280x720@30Hz 16:9 */ 1072 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1073 3080, 3300, 0, 720, 725, 730, 750, 0, 1074 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1075 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1076 /* 63 - 1920x1080@120Hz 16:9 */ 1077 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1078 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1079 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1080 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1081 /* 64 - 1920x1080@100Hz 16:9 */ 1082 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1083 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1084 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1085 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1086 /* 65 - 1280x720@24Hz 64:27 */ 1087 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1088 3080, 3300, 0, 720, 725, 730, 750, 0, 1089 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1090 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1091 /* 66 - 1280x720@25Hz 64:27 */ 1092 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1093 3740, 3960, 0, 720, 725, 730, 750, 0, 1094 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1095 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1096 /* 67 - 1280x720@30Hz 64:27 */ 1097 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1098 3080, 3300, 0, 720, 725, 730, 750, 0, 1099 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1100 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1101 /* 68 - 1280x720@50Hz 64:27 */ 1102 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1103 1760, 1980, 0, 720, 725, 730, 750, 0, 1104 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1105 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1106 /* 69 - 1280x720@60Hz 64:27 */ 1107 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1108 1430, 1650, 0, 720, 725, 730, 750, 0, 1109 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1110 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1111 /* 70 - 1280x720@100Hz 64:27 */ 1112 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1113 1760, 1980, 0, 720, 725, 730, 750, 0, 1114 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1115 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1116 /* 71 - 1280x720@120Hz 64:27 */ 1117 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1118 1430, 1650, 0, 720, 725, 730, 750, 0, 1119 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1120 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1121 /* 72 - 1920x1080@24Hz 64:27 */ 1122 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1123 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1124 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1125 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1126 /* 73 - 1920x1080@25Hz 64:27 */ 1127 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1128 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1129 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1130 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1131 /* 74 - 1920x1080@30Hz 64:27 */ 1132 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1133 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1134 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1135 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1136 /* 75 - 1920x1080@50Hz 64:27 */ 1137 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1138 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1139 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1140 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1141 /* 76 - 1920x1080@60Hz 64:27 */ 1142 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1143 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1144 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1145 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1146 /* 77 - 1920x1080@100Hz 64:27 */ 1147 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1148 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1149 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1150 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1151 /* 78 - 1920x1080@120Hz 64:27 */ 1152 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1153 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1154 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1155 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1156 /* 79 - 1680x720@24Hz 64:27 */ 1157 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 1158 3080, 3300, 0, 720, 725, 730, 750, 0, 1159 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1160 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1161 /* 80 - 1680x720@25Hz 64:27 */ 1162 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 1163 2948, 3168, 0, 720, 725, 730, 750, 0, 1164 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1165 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1166 /* 81 - 1680x720@30Hz 64:27 */ 1167 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 1168 2420, 2640, 0, 720, 725, 730, 750, 0, 1169 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1170 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1171 /* 82 - 1680x720@50Hz 64:27 */ 1172 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1173 1980, 2200, 0, 720, 725, 730, 750, 0, 1174 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1175 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1176 /* 83 - 1680x720@60Hz 64:27 */ 1177 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1178 1980, 2200, 0, 720, 725, 730, 750, 0, 1179 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1180 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1181 /* 84 - 1680x720@100Hz 64:27 */ 1182 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1183 1780, 2000, 0, 720, 725, 730, 825, 0, 1184 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1185 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1186 /* 85 - 1680x720@120Hz 64:27 */ 1187 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1188 1780, 2000, 0, 720, 725, 730, 825, 0, 1189 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1190 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1191 /* 86 - 2560x1080@24Hz 64:27 */ 1192 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 1193 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1194 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1195 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1196 /* 87 - 2560x1080@25Hz 64:27 */ 1197 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 1198 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, 1199 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1200 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1201 /* 88 - 2560x1080@30Hz 64:27 */ 1202 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 1203 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, 1204 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1205 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1206 /* 89 - 2560x1080@50Hz 64:27 */ 1207 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 1208 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, 1209 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1210 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1211 /* 90 - 2560x1080@60Hz 64:27 */ 1212 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 1213 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, 1214 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1215 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1216 /* 91 - 2560x1080@100Hz 64:27 */ 1217 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 1218 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, 1219 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1220 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1221 /* 92 - 2560x1080@120Hz 64:27 */ 1222 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 1223 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, 1224 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1225 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1226 /* 93 - 3840x2160@24Hz 16:9 */ 1227 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1228 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1229 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1230 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1231 /* 94 - 3840x2160@25Hz 16:9 */ 1232 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1233 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1234 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1235 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1236 /* 95 - 3840x2160@30Hz 16:9 */ 1237 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1238 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1239 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1240 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1241 /* 96 - 3840x2160@50Hz 16:9 */ 1242 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1243 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1245 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1246 /* 97 - 3840x2160@60Hz 16:9 */ 1247 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1248 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1249 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1250 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1251 /* 98 - 4096x2160@24Hz 256:135 */ 1252 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1253 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1254 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1255 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1256 /* 99 - 4096x2160@25Hz 256:135 */ 1257 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1258 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1260 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1261 /* 100 - 4096x2160@30Hz 256:135 */ 1262 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1263 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1265 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1266 /* 101 - 4096x2160@50Hz 256:135 */ 1267 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1268 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1269 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1270 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1271 /* 102 - 4096x2160@60Hz 256:135 */ 1272 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1273 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1274 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1275 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1276 /* 103 - 3840x2160@24Hz 64:27 */ 1277 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1278 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1280 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1281 /* 104 - 3840x2160@25Hz 64:27 */ 1282 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1283 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1285 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1286 /* 105 - 3840x2160@30Hz 64:27 */ 1287 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1288 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1289 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1290 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1291 /* 106 - 3840x2160@50Hz 64:27 */ 1292 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1293 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1294 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1295 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1296 /* 107 - 3840x2160@60Hz 64:27 */ 1297 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1298 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1300 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1301 /* 108 - 1280x720@48Hz 16:9 */ 1302 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1303 2280, 2500, 0, 720, 725, 730, 750, 0, 1304 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1305 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1306 /* 109 - 1280x720@48Hz 64:27 */ 1307 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1308 2280, 2500, 0, 720, 725, 730, 750, 0, 1309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1310 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1311 /* 110 - 1680x720@48Hz 64:27 */ 1312 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490, 1313 2530, 2750, 0, 720, 725, 730, 750, 0, 1314 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1315 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1316 /* 111 - 1920x1080@48Hz 16:9 */ 1317 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1318 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1319 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1320 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1321 /* 112 - 1920x1080@48Hz 64:27 */ 1322 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1323 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1324 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1325 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1326 /* 113 - 2560x1080@48Hz 64:27 */ 1327 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558, 1328 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1330 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1331 /* 114 - 3840x2160@48Hz 16:9 */ 1332 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1333 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1334 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1335 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1336 /* 115 - 4096x2160@48Hz 256:135 */ 1337 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116, 1338 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1339 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1340 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1341 /* 116 - 3840x2160@48Hz 64:27 */ 1342 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1343 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1344 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1345 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1346 /* 117 - 3840x2160@100Hz 16:9 */ 1347 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1348 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1349 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1350 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1351 /* 118 - 3840x2160@120Hz 16:9 */ 1352 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1353 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1354 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1355 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1356 /* 119 - 3840x2160@100Hz 64:27 */ 1357 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1358 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1359 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1360 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1361 /* 120 - 3840x2160@120Hz 64:27 */ 1362 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1363 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1364 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1365 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1366 /* 121 - 5120x2160@24Hz 64:27 */ 1367 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116, 1368 7204, 7500, 0, 2160, 2168, 2178, 2200, 0, 1369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1370 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1371 /* 122 - 5120x2160@25Hz 64:27 */ 1372 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816, 1373 6904, 7200, 0, 2160, 2168, 2178, 2200, 0, 1374 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1375 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1376 /* 123 - 5120x2160@30Hz 64:27 */ 1377 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784, 1378 5872, 6000, 0, 2160, 2168, 2178, 2200, 0, 1379 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1380 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1381 /* 124 - 5120x2160@48Hz 64:27 */ 1382 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866, 1383 5954, 6250, 0, 2160, 2168, 2178, 2475, 0, 1384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1385 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1386 /* 125 - 5120x2160@50Hz 64:27 */ 1387 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216, 1388 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1390 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1391 /* 126 - 5120x2160@60Hz 64:27 */ 1392 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284, 1393 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1394 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1395 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1396 /* 127 - 5120x2160@100Hz 64:27 */ 1397 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216, 1398 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1399 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1400 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1401 }; 1402 1403 /* 1404 * From CEA/CTA-861 spec. 1405 * 1406 * Do not access directly, instead always use cea_mode_for_vic(). 1407 */ 1408 static const struct drm_display_mode edid_cea_modes_193[] = { 1409 /* 193 - 5120x2160@120Hz 64:27 */ 1410 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284, 1411 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1412 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1413 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1414 /* 194 - 7680x4320@24Hz 16:9 */ 1415 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1416 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1418 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1419 /* 195 - 7680x4320@25Hz 16:9 */ 1420 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1421 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1422 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1423 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1424 /* 196 - 7680x4320@30Hz 16:9 */ 1425 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1426 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1427 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1428 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1429 /* 197 - 7680x4320@48Hz 16:9 */ 1430 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1431 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1432 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1433 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1434 /* 198 - 7680x4320@50Hz 16:9 */ 1435 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1436 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1438 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1439 /* 199 - 7680x4320@60Hz 16:9 */ 1440 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1441 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1442 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1443 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1444 /* 200 - 7680x4320@100Hz 16:9 */ 1445 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1446 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1447 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1448 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1449 /* 201 - 7680x4320@120Hz 16:9 */ 1450 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1451 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1452 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1453 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1454 /* 202 - 7680x4320@24Hz 64:27 */ 1455 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1456 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1458 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1459 /* 203 - 7680x4320@25Hz 64:27 */ 1460 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1461 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1462 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1463 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1464 /* 204 - 7680x4320@30Hz 64:27 */ 1465 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1466 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1467 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1468 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1469 /* 205 - 7680x4320@48Hz 64:27 */ 1470 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1471 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1472 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1473 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1474 /* 206 - 7680x4320@50Hz 64:27 */ 1475 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1476 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1478 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1479 /* 207 - 7680x4320@60Hz 64:27 */ 1480 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1481 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1482 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1483 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1484 /* 208 - 7680x4320@100Hz 64:27 */ 1485 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1486 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1487 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1488 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1489 /* 209 - 7680x4320@120Hz 64:27 */ 1490 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1491 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1492 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1493 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1494 /* 210 - 10240x4320@24Hz 64:27 */ 1495 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732, 1496 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1497 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1498 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1499 /* 211 - 10240x4320@25Hz 64:27 */ 1500 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732, 1501 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1502 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1503 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1504 /* 212 - 10240x4320@30Hz 64:27 */ 1505 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528, 1506 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1507 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1508 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1509 /* 213 - 10240x4320@48Hz 64:27 */ 1510 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732, 1511 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1512 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1513 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1514 /* 214 - 10240x4320@50Hz 64:27 */ 1515 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732, 1516 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1518 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1519 /* 215 - 10240x4320@60Hz 64:27 */ 1520 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528, 1521 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1522 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1523 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1524 /* 216 - 10240x4320@100Hz 64:27 */ 1525 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432, 1526 12608, 13200, 0, 4320, 4336, 4356, 4500, 0, 1527 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1528 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1529 /* 217 - 10240x4320@120Hz 64:27 */ 1530 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528, 1531 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1532 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1533 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1534 /* 218 - 4096x2160@100Hz 256:135 */ 1535 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896, 1536 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1537 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1538 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1539 /* 219 - 4096x2160@120Hz 256:135 */ 1540 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184, 1541 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1542 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1543 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1544 }; 1545 1546 /* 1547 * HDMI 1.4 4k modes. Index using the VIC. 1548 */ 1549 static const struct drm_display_mode edid_4k_modes[] = { 1550 /* 0 - dummy, VICs start at 1 */ 1551 { }, 1552 /* 1 - 3840x2160@30Hz */ 1553 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1554 3840, 4016, 4104, 4400, 0, 1555 2160, 2168, 2178, 2250, 0, 1556 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1557 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1558 /* 2 - 3840x2160@25Hz */ 1559 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1560 3840, 4896, 4984, 5280, 0, 1561 2160, 2168, 2178, 2250, 0, 1562 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1563 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1564 /* 3 - 3840x2160@24Hz */ 1565 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1566 3840, 5116, 5204, 5500, 0, 1567 2160, 2168, 2178, 2250, 0, 1568 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1569 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1570 /* 4 - 4096x2160@24Hz (SMPTE) */ 1571 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1572 4096, 5116, 5204, 5500, 0, 1573 2160, 2168, 2178, 2250, 0, 1574 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1575 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1576 }; 1577 1578 /*** DDC fetch and block validation ***/ 1579 1580 /* 1581 * The opaque EDID type, internal to drm_edid.c. 1582 */ 1583 struct drm_edid { 1584 /* Size allocated for edid */ 1585 size_t size; 1586 const struct edid *edid; 1587 }; 1588 1589 static int edid_hfeeodb_extension_block_count(const struct edid *edid); 1590 1591 static int edid_hfeeodb_block_count(const struct edid *edid) 1592 { 1593 int eeodb = edid_hfeeodb_extension_block_count(edid); 1594 1595 return eeodb ? eeodb + 1 : 0; 1596 } 1597 1598 static int edid_extension_block_count(const struct edid *edid) 1599 { 1600 return edid->extensions; 1601 } 1602 1603 static int edid_block_count(const struct edid *edid) 1604 { 1605 return edid_extension_block_count(edid) + 1; 1606 } 1607 1608 static int edid_size_by_blocks(int num_blocks) 1609 { 1610 return num_blocks * EDID_LENGTH; 1611 } 1612 1613 static int edid_size(const struct edid *edid) 1614 { 1615 return edid_size_by_blocks(edid_block_count(edid)); 1616 } 1617 1618 static const void *edid_block_data(const struct edid *edid, int index) 1619 { 1620 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH); 1621 1622 return edid + index; 1623 } 1624 1625 static const void *edid_extension_block_data(const struct edid *edid, int index) 1626 { 1627 return edid_block_data(edid, index + 1); 1628 } 1629 1630 /* EDID block count indicated in EDID, may exceed allocated size */ 1631 static int __drm_edid_block_count(const struct drm_edid *drm_edid) 1632 { 1633 int num_blocks; 1634 1635 /* Starting point */ 1636 num_blocks = edid_block_count(drm_edid->edid); 1637 1638 /* HF-EEODB override */ 1639 if (drm_edid->size >= edid_size_by_blocks(2)) { 1640 int eeodb; 1641 1642 /* 1643 * Note: HF-EEODB may specify a smaller extension count than the 1644 * regular one. Unlike in buffer allocation, here we can use it. 1645 */ 1646 eeodb = edid_hfeeodb_block_count(drm_edid->edid); 1647 if (eeodb) 1648 num_blocks = eeodb; 1649 } 1650 1651 return num_blocks; 1652 } 1653 1654 /* EDID block count, limited by allocated size */ 1655 static int drm_edid_block_count(const struct drm_edid *drm_edid) 1656 { 1657 /* Limit by allocated size */ 1658 return min(__drm_edid_block_count(drm_edid), 1659 (int)drm_edid->size / EDID_LENGTH); 1660 } 1661 1662 /* EDID extension block count, limited by allocated size */ 1663 static int drm_edid_extension_block_count(const struct drm_edid *drm_edid) 1664 { 1665 return drm_edid_block_count(drm_edid) - 1; 1666 } 1667 1668 static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index) 1669 { 1670 return edid_block_data(drm_edid->edid, index); 1671 } 1672 1673 static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid, 1674 int index) 1675 { 1676 return edid_extension_block_data(drm_edid->edid, index); 1677 } 1678 1679 /* 1680 * Initializer helper for legacy interfaces, where we have no choice but to 1681 * trust edid size. Not for general purpose use. 1682 */ 1683 static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid, 1684 const struct edid *edid) 1685 { 1686 if (!edid) 1687 return NULL; 1688 1689 memset(drm_edid, 0, sizeof(*drm_edid)); 1690 1691 drm_edid->edid = edid; 1692 drm_edid->size = edid_size(edid); 1693 1694 return drm_edid; 1695 } 1696 1697 /* 1698 * EDID base and extension block iterator. 1699 * 1700 * struct drm_edid_iter iter; 1701 * const u8 *block; 1702 * 1703 * drm_edid_iter_begin(drm_edid, &iter); 1704 * drm_edid_iter_for_each(block, &iter) { 1705 * // do stuff with block 1706 * } 1707 * drm_edid_iter_end(&iter); 1708 */ 1709 struct drm_edid_iter { 1710 const struct drm_edid *drm_edid; 1711 1712 /* Current block index. */ 1713 int index; 1714 }; 1715 1716 static void drm_edid_iter_begin(const struct drm_edid *drm_edid, 1717 struct drm_edid_iter *iter) 1718 { 1719 memset(iter, 0, sizeof(*iter)); 1720 1721 iter->drm_edid = drm_edid; 1722 } 1723 1724 static const void *__drm_edid_iter_next(struct drm_edid_iter *iter) 1725 { 1726 const void *block = NULL; 1727 1728 if (!iter->drm_edid) 1729 return NULL; 1730 1731 if (iter->index < drm_edid_block_count(iter->drm_edid)) 1732 block = drm_edid_block_data(iter->drm_edid, iter->index++); 1733 1734 return block; 1735 } 1736 1737 #define drm_edid_iter_for_each(__block, __iter) \ 1738 while (((__block) = __drm_edid_iter_next(__iter))) 1739 1740 static void drm_edid_iter_end(struct drm_edid_iter *iter) 1741 { 1742 memset(iter, 0, sizeof(*iter)); 1743 } 1744 1745 static const u8 edid_header[] = { 1746 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1747 }; 1748 1749 static void edid_header_fix(void *edid) 1750 { 1751 memcpy(edid, edid_header, sizeof(edid_header)); 1752 } 1753 1754 /** 1755 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1756 * @_edid: pointer to raw base EDID block 1757 * 1758 * Sanity check the header of the base EDID block. 1759 * 1760 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1761 */ 1762 int drm_edid_header_is_valid(const void *_edid) 1763 { 1764 const struct edid *edid = _edid; 1765 int i, score = 0; 1766 1767 for (i = 0; i < sizeof(edid_header); i++) { 1768 if (edid->header[i] == edid_header[i]) 1769 score++; 1770 } 1771 1772 return score; 1773 } 1774 EXPORT_SYMBOL(drm_edid_header_is_valid); 1775 1776 static int edid_fixup __read_mostly = 6; 1777 module_param_named(edid_fixup, edid_fixup, int, 0400); 1778 MODULE_PARM_DESC(edid_fixup, 1779 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1780 1781 static int edid_block_compute_checksum(const void *_block) 1782 { 1783 const u8 *block = _block; 1784 int i; 1785 u8 csum = 0, crc = 0; 1786 1787 for (i = 0; i < EDID_LENGTH - 1; i++) 1788 csum += block[i]; 1789 1790 crc = 0x100 - csum; 1791 1792 return crc; 1793 } 1794 1795 static int edid_block_get_checksum(const void *_block) 1796 { 1797 const struct edid *block = _block; 1798 1799 return block->checksum; 1800 } 1801 1802 static int edid_block_tag(const void *_block) 1803 { 1804 const u8 *block = _block; 1805 1806 return block[0]; 1807 } 1808 1809 static bool edid_block_is_zero(const void *edid) 1810 { 1811 return !memchr_inv(edid, 0, EDID_LENGTH); 1812 } 1813 1814 /** 1815 * drm_edid_are_equal - compare two edid blobs. 1816 * @edid1: pointer to first blob 1817 * @edid2: pointer to second blob 1818 * This helper can be used during probing to determine if 1819 * edid had changed. 1820 */ 1821 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2) 1822 { 1823 int edid1_len, edid2_len; 1824 bool edid1_present = edid1 != NULL; 1825 bool edid2_present = edid2 != NULL; 1826 1827 if (edid1_present != edid2_present) 1828 return false; 1829 1830 if (edid1) { 1831 edid1_len = edid_size(edid1); 1832 edid2_len = edid_size(edid2); 1833 1834 if (edid1_len != edid2_len) 1835 return false; 1836 1837 if (memcmp(edid1, edid2, edid1_len)) 1838 return false; 1839 } 1840 1841 return true; 1842 } 1843 EXPORT_SYMBOL(drm_edid_are_equal); 1844 1845 enum edid_block_status { 1846 EDID_BLOCK_OK = 0, 1847 EDID_BLOCK_READ_FAIL, 1848 EDID_BLOCK_NULL, 1849 EDID_BLOCK_ZERO, 1850 EDID_BLOCK_HEADER_CORRUPT, 1851 EDID_BLOCK_HEADER_REPAIR, 1852 EDID_BLOCK_HEADER_FIXED, 1853 EDID_BLOCK_CHECKSUM, 1854 EDID_BLOCK_VERSION, 1855 }; 1856 1857 static enum edid_block_status edid_block_check(const void *_block, 1858 bool is_base_block) 1859 { 1860 const struct edid *block = _block; 1861 1862 if (!block) 1863 return EDID_BLOCK_NULL; 1864 1865 if (is_base_block) { 1866 int score = drm_edid_header_is_valid(block); 1867 1868 if (score < clamp(edid_fixup, 0, 8)) { 1869 if (edid_block_is_zero(block)) 1870 return EDID_BLOCK_ZERO; 1871 else 1872 return EDID_BLOCK_HEADER_CORRUPT; 1873 } 1874 1875 if (score < 8) 1876 return EDID_BLOCK_HEADER_REPAIR; 1877 } 1878 1879 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) { 1880 if (edid_block_is_zero(block)) 1881 return EDID_BLOCK_ZERO; 1882 else 1883 return EDID_BLOCK_CHECKSUM; 1884 } 1885 1886 if (is_base_block) { 1887 if (block->version != 1) 1888 return EDID_BLOCK_VERSION; 1889 } 1890 1891 return EDID_BLOCK_OK; 1892 } 1893 1894 static bool edid_block_status_valid(enum edid_block_status status, int tag) 1895 { 1896 return status == EDID_BLOCK_OK || 1897 status == EDID_BLOCK_HEADER_FIXED || 1898 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT); 1899 } 1900 1901 static bool edid_block_valid(const void *block, bool base) 1902 { 1903 return edid_block_status_valid(edid_block_check(block, base), 1904 edid_block_tag(block)); 1905 } 1906 1907 static void edid_block_status_print(enum edid_block_status status, 1908 const struct edid *block, 1909 int block_num) 1910 { 1911 switch (status) { 1912 case EDID_BLOCK_OK: 1913 break; 1914 case EDID_BLOCK_READ_FAIL: 1915 pr_debug("EDID block %d read failed\n", block_num); 1916 break; 1917 case EDID_BLOCK_NULL: 1918 pr_debug("EDID block %d pointer is NULL\n", block_num); 1919 break; 1920 case EDID_BLOCK_ZERO: 1921 pr_notice("EDID block %d is all zeroes\n", block_num); 1922 break; 1923 case EDID_BLOCK_HEADER_CORRUPT: 1924 pr_notice("EDID has corrupt header\n"); 1925 break; 1926 case EDID_BLOCK_HEADER_REPAIR: 1927 pr_debug("EDID corrupt header needs repair\n"); 1928 break; 1929 case EDID_BLOCK_HEADER_FIXED: 1930 pr_debug("EDID corrupt header fixed\n"); 1931 break; 1932 case EDID_BLOCK_CHECKSUM: 1933 if (edid_block_status_valid(status, edid_block_tag(block))) { 1934 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n", 1935 block_num, edid_block_tag(block), 1936 edid_block_compute_checksum(block)); 1937 } else { 1938 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n", 1939 block_num, edid_block_tag(block), 1940 edid_block_compute_checksum(block)); 1941 } 1942 break; 1943 case EDID_BLOCK_VERSION: 1944 pr_notice("EDID has major version %d, instead of 1\n", 1945 block->version); 1946 break; 1947 default: 1948 WARN(1, "EDID block %d unknown edid block status code %d\n", 1949 block_num, status); 1950 break; 1951 } 1952 } 1953 1954 static void edid_block_dump(const char *level, const void *block, int block_num) 1955 { 1956 enum edid_block_status status; 1957 char prefix[20]; 1958 1959 status = edid_block_check(block, block_num == 0); 1960 if (status == EDID_BLOCK_ZERO) 1961 sprintf(prefix, "\t[%02x] ZERO ", block_num); 1962 else if (!edid_block_status_valid(status, edid_block_tag(block))) 1963 sprintf(prefix, "\t[%02x] BAD ", block_num); 1964 else 1965 sprintf(prefix, "\t[%02x] GOOD ", block_num); 1966 1967 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1, 1968 block, EDID_LENGTH, false); 1969 } 1970 1971 /** 1972 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1973 * @_block: pointer to raw EDID block 1974 * @block_num: type of block to validate (0 for base, extension otherwise) 1975 * @print_bad_edid: if true, dump bad EDID blocks to the console 1976 * @edid_corrupt: if true, the header or checksum is invalid 1977 * 1978 * Validate a base or extension EDID block and optionally dump bad blocks to 1979 * the console. 1980 * 1981 * Return: True if the block is valid, false otherwise. 1982 */ 1983 bool drm_edid_block_valid(u8 *_block, int block_num, bool print_bad_edid, 1984 bool *edid_corrupt) 1985 { 1986 struct edid *block = (struct edid *)_block; 1987 enum edid_block_status status; 1988 bool is_base_block = block_num == 0; 1989 bool valid; 1990 1991 if (WARN_ON(!block)) 1992 return false; 1993 1994 status = edid_block_check(block, is_base_block); 1995 if (status == EDID_BLOCK_HEADER_REPAIR) { 1996 DRM_DEBUG_KMS("Fixing EDID header, your hardware may be failing\n"); 1997 edid_header_fix(block); 1998 1999 /* Retry with fixed header, update status if that worked. */ 2000 status = edid_block_check(block, is_base_block); 2001 if (status == EDID_BLOCK_OK) 2002 status = EDID_BLOCK_HEADER_FIXED; 2003 } 2004 2005 if (edid_corrupt) { 2006 /* 2007 * Unknown major version isn't corrupt but we can't use it. Only 2008 * the base block can reset edid_corrupt to false. 2009 */ 2010 if (is_base_block && 2011 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)) 2012 *edid_corrupt = false; 2013 else if (status != EDID_BLOCK_OK) 2014 *edid_corrupt = true; 2015 } 2016 2017 edid_block_status_print(status, block, block_num); 2018 2019 /* Determine whether we can use this block with this status. */ 2020 valid = edid_block_status_valid(status, edid_block_tag(block)); 2021 2022 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) { 2023 pr_notice("Raw EDID:\n"); 2024 edid_block_dump(KERN_NOTICE, block, block_num); 2025 } 2026 2027 return valid; 2028 } 2029 EXPORT_SYMBOL(drm_edid_block_valid); 2030 2031 /** 2032 * drm_edid_is_valid - sanity check EDID data 2033 * @edid: EDID data 2034 * 2035 * Sanity-check an entire EDID record (including extensions) 2036 * 2037 * Return: True if the EDID data is valid, false otherwise. 2038 */ 2039 bool drm_edid_is_valid(struct edid *edid) 2040 { 2041 int i; 2042 2043 if (!edid) 2044 return false; 2045 2046 for (i = 0; i < edid_block_count(edid); i++) { 2047 void *block = (void *)edid_block_data(edid, i); 2048 2049 if (!drm_edid_block_valid(block, i, true, NULL)) 2050 return false; 2051 } 2052 2053 return true; 2054 } 2055 EXPORT_SYMBOL(drm_edid_is_valid); 2056 2057 /** 2058 * drm_edid_valid - sanity check EDID data 2059 * @drm_edid: EDID data 2060 * 2061 * Sanity check an EDID. Cross check block count against allocated size and 2062 * checksum the blocks. 2063 * 2064 * Return: True if the EDID data is valid, false otherwise. 2065 */ 2066 bool drm_edid_valid(const struct drm_edid *drm_edid) 2067 { 2068 int i; 2069 2070 if (!drm_edid) 2071 return false; 2072 2073 if (edid_size_by_blocks(__drm_edid_block_count(drm_edid)) != drm_edid->size) 2074 return false; 2075 2076 for (i = 0; i < drm_edid_block_count(drm_edid); i++) { 2077 const void *block = drm_edid_block_data(drm_edid, i); 2078 2079 if (!edid_block_valid(block, i == 0)) 2080 return false; 2081 } 2082 2083 return true; 2084 } 2085 EXPORT_SYMBOL(drm_edid_valid); 2086 2087 static struct edid *edid_filter_invalid_blocks(struct edid *edid, 2088 size_t *alloc_size) 2089 { 2090 struct edid *new; 2091 int i, valid_blocks = 0; 2092 2093 /* 2094 * Note: If the EDID uses HF-EEODB, but has invalid blocks, we'll revert 2095 * back to regular extension count here. We don't want to start 2096 * modifying the HF-EEODB extension too. 2097 */ 2098 for (i = 0; i < edid_block_count(edid); i++) { 2099 const void *src_block = edid_block_data(edid, i); 2100 2101 if (edid_block_valid(src_block, i == 0)) { 2102 void *dst_block = (void *)edid_block_data(edid, valid_blocks); 2103 2104 memmove(dst_block, src_block, EDID_LENGTH); 2105 valid_blocks++; 2106 } 2107 } 2108 2109 /* We already trusted the base block to be valid here... */ 2110 if (WARN_ON(!valid_blocks)) { 2111 kfree(edid); 2112 return NULL; 2113 } 2114 2115 edid->extensions = valid_blocks - 1; 2116 edid->checksum = edid_block_compute_checksum(edid); 2117 2118 *alloc_size = edid_size_by_blocks(valid_blocks); 2119 2120 new = krealloc(edid, *alloc_size, GFP_KERNEL); 2121 if (!new) 2122 kfree(edid); 2123 2124 return new; 2125 } 2126 2127 #define DDC_SEGMENT_ADDR 0x30 2128 /** 2129 * drm_do_probe_ddc_edid() - get EDID information via I2C 2130 * @data: I2C device adapter 2131 * @buf: EDID data buffer to be filled 2132 * @block: 128 byte EDID block to start fetching from 2133 * @len: EDID data buffer length to fetch 2134 * 2135 * Try to fetch EDID information by calling I2C driver functions. 2136 * 2137 * Return: 0 on success or -1 on failure. 2138 */ 2139 static int 2140 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 2141 { 2142 struct i2c_adapter *adapter = data; 2143 unsigned char start = block * EDID_LENGTH; 2144 unsigned char segment = block >> 1; 2145 unsigned char xfers = segment ? 3 : 2; 2146 int ret, retries = 5; 2147 2148 /* 2149 * The core I2C driver will automatically retry the transfer if the 2150 * adapter reports EAGAIN. However, we find that bit-banging transfers 2151 * are susceptible to errors under a heavily loaded machine and 2152 * generate spurious NAKs and timeouts. Retrying the transfer 2153 * of the individual block a few times seems to overcome this. 2154 */ 2155 do { 2156 struct i2c_msg msgs[] = { 2157 { 2158 .addr = DDC_SEGMENT_ADDR, 2159 .flags = 0, 2160 .len = 1, 2161 .buf = &segment, 2162 }, { 2163 .addr = DDC_ADDR, 2164 .flags = 0, 2165 .len = 1, 2166 .buf = &start, 2167 }, { 2168 .addr = DDC_ADDR, 2169 .flags = I2C_M_RD, 2170 .len = len, 2171 .buf = buf, 2172 } 2173 }; 2174 2175 /* 2176 * Avoid sending the segment addr to not upset non-compliant 2177 * DDC monitors. 2178 */ 2179 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 2180 2181 if (ret == -ENXIO) { 2182 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 2183 adapter->name); 2184 break; 2185 } 2186 } while (ret != xfers && --retries); 2187 2188 return ret == xfers ? 0 : -1; 2189 } 2190 2191 static void connector_bad_edid(struct drm_connector *connector, 2192 const struct edid *edid, int num_blocks) 2193 { 2194 int i; 2195 u8 last_block; 2196 2197 /* 2198 * 0x7e in the EDID is the number of extension blocks. The EDID 2199 * is 1 (base block) + num_ext_blocks big. That means we can think 2200 * of 0x7e in the EDID of the _index_ of the last block in the 2201 * combined chunk of memory. 2202 */ 2203 last_block = edid->extensions; 2204 2205 /* Calculate real checksum for the last edid extension block data */ 2206 if (last_block < num_blocks) 2207 connector->real_edid_checksum = 2208 edid_block_compute_checksum(edid + last_block); 2209 2210 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS)) 2211 return; 2212 2213 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID is invalid:\n", 2214 connector->base.id, connector->name); 2215 for (i = 0; i < num_blocks; i++) 2216 edid_block_dump(KERN_DEBUG, edid + i, i); 2217 } 2218 2219 /* Get override or firmware EDID */ 2220 static const struct drm_edid *drm_edid_override_get(struct drm_connector *connector) 2221 { 2222 const struct drm_edid *override = NULL; 2223 2224 mutex_lock(&connector->edid_override_mutex); 2225 2226 if (connector->edid_override) 2227 override = drm_edid_dup(connector->edid_override); 2228 2229 mutex_unlock(&connector->edid_override_mutex); 2230 2231 if (!override) 2232 override = drm_edid_load_firmware(connector); 2233 2234 return IS_ERR(override) ? NULL : override; 2235 } 2236 2237 /* For debugfs edid_override implementation */ 2238 int drm_edid_override_show(struct drm_connector *connector, struct seq_file *m) 2239 { 2240 const struct drm_edid *drm_edid; 2241 2242 mutex_lock(&connector->edid_override_mutex); 2243 2244 drm_edid = connector->edid_override; 2245 if (drm_edid) 2246 seq_write(m, drm_edid->edid, drm_edid->size); 2247 2248 mutex_unlock(&connector->edid_override_mutex); 2249 2250 return 0; 2251 } 2252 2253 /* For debugfs edid_override implementation */ 2254 int drm_edid_override_set(struct drm_connector *connector, const void *edid, 2255 size_t size) 2256 { 2257 const struct drm_edid *drm_edid; 2258 2259 drm_edid = drm_edid_alloc(edid, size); 2260 if (!drm_edid_valid(drm_edid)) { 2261 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override invalid\n", 2262 connector->base.id, connector->name); 2263 drm_edid_free(drm_edid); 2264 return -EINVAL; 2265 } 2266 2267 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override set\n", 2268 connector->base.id, connector->name); 2269 2270 mutex_lock(&connector->edid_override_mutex); 2271 2272 drm_edid_free(connector->edid_override); 2273 connector->edid_override = drm_edid; 2274 2275 mutex_unlock(&connector->edid_override_mutex); 2276 2277 return 0; 2278 } 2279 2280 /* For debugfs edid_override implementation */ 2281 int drm_edid_override_reset(struct drm_connector *connector) 2282 { 2283 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override reset\n", 2284 connector->base.id, connector->name); 2285 2286 mutex_lock(&connector->edid_override_mutex); 2287 2288 drm_edid_free(connector->edid_override); 2289 connector->edid_override = NULL; 2290 2291 mutex_unlock(&connector->edid_override_mutex); 2292 2293 return 0; 2294 } 2295 2296 /** 2297 * drm_edid_override_connector_update - add modes from override/firmware EDID 2298 * @connector: connector we're probing 2299 * 2300 * Add modes from the override/firmware EDID, if available. Only to be used from 2301 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe 2302 * failed during drm_get_edid() and caused the override/firmware EDID to be 2303 * skipped. 2304 * 2305 * Return: The number of modes added or 0 if we couldn't find any. 2306 */ 2307 int drm_edid_override_connector_update(struct drm_connector *connector) 2308 { 2309 const struct drm_edid *override; 2310 int num_modes = 0; 2311 2312 override = drm_edid_override_get(connector); 2313 if (override) { 2314 num_modes = drm_edid_connector_update(connector, override); 2315 2316 drm_edid_free(override); 2317 2318 drm_dbg_kms(connector->dev, 2319 "[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n", 2320 connector->base.id, connector->name, num_modes); 2321 } 2322 2323 return num_modes; 2324 } 2325 EXPORT_SYMBOL(drm_edid_override_connector_update); 2326 2327 typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len); 2328 2329 static enum edid_block_status edid_block_read(void *block, unsigned int block_num, 2330 read_block_fn read_block, 2331 void *context) 2332 { 2333 enum edid_block_status status; 2334 bool is_base_block = block_num == 0; 2335 int try; 2336 2337 for (try = 0; try < 4; try++) { 2338 if (read_block(context, block, block_num, EDID_LENGTH)) 2339 return EDID_BLOCK_READ_FAIL; 2340 2341 status = edid_block_check(block, is_base_block); 2342 if (status == EDID_BLOCK_HEADER_REPAIR) { 2343 edid_header_fix(block); 2344 2345 /* Retry with fixed header, update status if that worked. */ 2346 status = edid_block_check(block, is_base_block); 2347 if (status == EDID_BLOCK_OK) 2348 status = EDID_BLOCK_HEADER_FIXED; 2349 } 2350 2351 if (edid_block_status_valid(status, edid_block_tag(block))) 2352 break; 2353 2354 /* Fail early for unrepairable base block all zeros. */ 2355 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO) 2356 break; 2357 } 2358 2359 return status; 2360 } 2361 2362 static struct edid *_drm_do_get_edid(struct drm_connector *connector, 2363 read_block_fn read_block, void *context, 2364 size_t *size) 2365 { 2366 enum edid_block_status status; 2367 int i, num_blocks, invalid_blocks = 0; 2368 const struct drm_edid *override; 2369 struct edid *edid, *new; 2370 size_t alloc_size = EDID_LENGTH; 2371 2372 override = drm_edid_override_get(connector); 2373 if (override) { 2374 alloc_size = override->size; 2375 edid = kmemdup(override->edid, alloc_size, GFP_KERNEL); 2376 drm_edid_free(override); 2377 if (!edid) 2378 return NULL; 2379 goto ok; 2380 } 2381 2382 edid = kmalloc(alloc_size, GFP_KERNEL); 2383 if (!edid) 2384 return NULL; 2385 2386 status = edid_block_read(edid, 0, read_block, context); 2387 2388 edid_block_status_print(status, edid, 0); 2389 2390 if (status == EDID_BLOCK_READ_FAIL) 2391 goto fail; 2392 2393 /* FIXME: Clarify what a corrupt EDID actually means. */ 2394 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION) 2395 connector->edid_corrupt = false; 2396 else 2397 connector->edid_corrupt = true; 2398 2399 if (!edid_block_status_valid(status, edid_block_tag(edid))) { 2400 if (status == EDID_BLOCK_ZERO) 2401 connector->null_edid_counter++; 2402 2403 connector_bad_edid(connector, edid, 1); 2404 goto fail; 2405 } 2406 2407 if (!edid_extension_block_count(edid)) 2408 goto ok; 2409 2410 alloc_size = edid_size(edid); 2411 new = krealloc(edid, alloc_size, GFP_KERNEL); 2412 if (!new) 2413 goto fail; 2414 edid = new; 2415 2416 num_blocks = edid_block_count(edid); 2417 for (i = 1; i < num_blocks; i++) { 2418 void *block = (void *)edid_block_data(edid, i); 2419 2420 status = edid_block_read(block, i, read_block, context); 2421 2422 edid_block_status_print(status, block, i); 2423 2424 if (!edid_block_status_valid(status, edid_block_tag(block))) { 2425 if (status == EDID_BLOCK_READ_FAIL) 2426 goto fail; 2427 invalid_blocks++; 2428 } else if (i == 1) { 2429 /* 2430 * If the first EDID extension is a CTA extension, and 2431 * the first Data Block is HF-EEODB, override the 2432 * extension block count. 2433 * 2434 * Note: HF-EEODB could specify a smaller extension 2435 * count too, but we can't risk allocating a smaller 2436 * amount. 2437 */ 2438 int eeodb = edid_hfeeodb_block_count(edid); 2439 2440 if (eeodb > num_blocks) { 2441 num_blocks = eeodb; 2442 alloc_size = edid_size_by_blocks(num_blocks); 2443 new = krealloc(edid, alloc_size, GFP_KERNEL); 2444 if (!new) 2445 goto fail; 2446 edid = new; 2447 } 2448 } 2449 } 2450 2451 if (invalid_blocks) { 2452 connector_bad_edid(connector, edid, num_blocks); 2453 2454 edid = edid_filter_invalid_blocks(edid, &alloc_size); 2455 } 2456 2457 ok: 2458 if (size) 2459 *size = alloc_size; 2460 2461 return edid; 2462 2463 fail: 2464 kfree(edid); 2465 return NULL; 2466 } 2467 2468 /** 2469 * drm_do_get_edid - get EDID data using a custom EDID block read function 2470 * @connector: connector we're probing 2471 * @read_block: EDID block read function 2472 * @context: private data passed to the block read function 2473 * 2474 * When the I2C adapter connected to the DDC bus is hidden behind a device that 2475 * exposes a different interface to read EDID blocks this function can be used 2476 * to get EDID data using a custom block read function. 2477 * 2478 * As in the general case the DDC bus is accessible by the kernel at the I2C 2479 * level, drivers must make all reasonable efforts to expose it as an I2C 2480 * adapter and use drm_get_edid() instead of abusing this function. 2481 * 2482 * The EDID may be overridden using debugfs override_edid or firmware EDID 2483 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2484 * order. Having either of them bypasses actual EDID reads. 2485 * 2486 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2487 */ 2488 struct edid *drm_do_get_edid(struct drm_connector *connector, 2489 read_block_fn read_block, 2490 void *context) 2491 { 2492 return _drm_do_get_edid(connector, read_block, context, NULL); 2493 } 2494 EXPORT_SYMBOL_GPL(drm_do_get_edid); 2495 2496 /** 2497 * drm_edid_raw - Get a pointer to the raw EDID data. 2498 * @drm_edid: drm_edid container 2499 * 2500 * Get a pointer to the raw EDID data. 2501 * 2502 * This is for transition only. Avoid using this like the plague. 2503 * 2504 * Return: Pointer to raw EDID data. 2505 */ 2506 const struct edid *drm_edid_raw(const struct drm_edid *drm_edid) 2507 { 2508 if (!drm_edid || !drm_edid->size) 2509 return NULL; 2510 2511 /* 2512 * Do not return pointers where relying on EDID extension count would 2513 * lead to buffer overflow. 2514 */ 2515 if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size)) 2516 return NULL; 2517 2518 return drm_edid->edid; 2519 } 2520 EXPORT_SYMBOL(drm_edid_raw); 2521 2522 /* Allocate struct drm_edid container *without* duplicating the edid data */ 2523 static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size) 2524 { 2525 struct drm_edid *drm_edid; 2526 2527 if (!edid || !size || size < EDID_LENGTH) 2528 return NULL; 2529 2530 drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL); 2531 if (drm_edid) { 2532 drm_edid->edid = edid; 2533 drm_edid->size = size; 2534 } 2535 2536 return drm_edid; 2537 } 2538 2539 /** 2540 * drm_edid_alloc - Allocate a new drm_edid container 2541 * @edid: Pointer to raw EDID data 2542 * @size: Size of memory allocated for EDID 2543 * 2544 * Allocate a new drm_edid container. Do not calculate edid size from edid, pass 2545 * the actual size that has been allocated for the data. There is no validation 2546 * of the raw EDID data against the size, but at least the EDID base block must 2547 * fit in the buffer. 2548 * 2549 * The returned pointer must be freed using drm_edid_free(). 2550 * 2551 * Return: drm_edid container, or NULL on errors 2552 */ 2553 const struct drm_edid *drm_edid_alloc(const void *edid, size_t size) 2554 { 2555 const struct drm_edid *drm_edid; 2556 2557 if (!edid || !size || size < EDID_LENGTH) 2558 return NULL; 2559 2560 edid = kmemdup(edid, size, GFP_KERNEL); 2561 if (!edid) 2562 return NULL; 2563 2564 drm_edid = _drm_edid_alloc(edid, size); 2565 if (!drm_edid) 2566 kfree(edid); 2567 2568 return drm_edid; 2569 } 2570 EXPORT_SYMBOL(drm_edid_alloc); 2571 2572 /** 2573 * drm_edid_dup - Duplicate a drm_edid container 2574 * @drm_edid: EDID to duplicate 2575 * 2576 * The returned pointer must be freed using drm_edid_free(). 2577 * 2578 * Returns: drm_edid container copy, or NULL on errors 2579 */ 2580 const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid) 2581 { 2582 if (!drm_edid) 2583 return NULL; 2584 2585 return drm_edid_alloc(drm_edid->edid, drm_edid->size); 2586 } 2587 EXPORT_SYMBOL(drm_edid_dup); 2588 2589 /** 2590 * drm_edid_free - Free the drm_edid container 2591 * @drm_edid: EDID to free 2592 */ 2593 void drm_edid_free(const struct drm_edid *drm_edid) 2594 { 2595 if (!drm_edid) 2596 return; 2597 2598 kfree(drm_edid->edid); 2599 kfree(drm_edid); 2600 } 2601 EXPORT_SYMBOL(drm_edid_free); 2602 2603 /** 2604 * drm_probe_ddc() - probe DDC presence 2605 * @adapter: I2C adapter to probe 2606 * 2607 * Return: True on success, false on failure. 2608 */ 2609 bool 2610 drm_probe_ddc(struct i2c_adapter *adapter) 2611 { 2612 unsigned char out; 2613 2614 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 2615 } 2616 EXPORT_SYMBOL(drm_probe_ddc); 2617 2618 /** 2619 * drm_get_edid - get EDID data, if available 2620 * @connector: connector we're probing 2621 * @adapter: I2C adapter to use for DDC 2622 * 2623 * Poke the given I2C channel to grab EDID data if possible. If found, 2624 * attach it to the connector. 2625 * 2626 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2627 */ 2628 struct edid *drm_get_edid(struct drm_connector *connector, 2629 struct i2c_adapter *adapter) 2630 { 2631 struct edid *edid; 2632 2633 if (connector->force == DRM_FORCE_OFF) 2634 return NULL; 2635 2636 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2637 return NULL; 2638 2639 edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL); 2640 drm_connector_update_edid_property(connector, edid); 2641 return edid; 2642 } 2643 EXPORT_SYMBOL(drm_get_edid); 2644 2645 /** 2646 * drm_edid_read_custom - Read EDID data using given EDID block read function 2647 * @connector: Connector to use 2648 * @read_block: EDID block read function 2649 * @context: Private data passed to the block read function 2650 * 2651 * When the I2C adapter connected to the DDC bus is hidden behind a device that 2652 * exposes a different interface to read EDID blocks this function can be used 2653 * to get EDID data using a custom block read function. 2654 * 2655 * As in the general case the DDC bus is accessible by the kernel at the I2C 2656 * level, drivers must make all reasonable efforts to expose it as an I2C 2657 * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing 2658 * this function. 2659 * 2660 * The EDID may be overridden using debugfs override_edid or firmware EDID 2661 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2662 * order. Having either of them bypasses actual EDID reads. 2663 * 2664 * The returned pointer must be freed using drm_edid_free(). 2665 * 2666 * Return: Pointer to EDID, or NULL if probe/read failed. 2667 */ 2668 const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector, 2669 read_block_fn read_block, 2670 void *context) 2671 { 2672 const struct drm_edid *drm_edid; 2673 struct edid *edid; 2674 size_t size = 0; 2675 2676 edid = _drm_do_get_edid(connector, read_block, context, &size); 2677 if (!edid) 2678 return NULL; 2679 2680 /* Sanity check for now */ 2681 drm_WARN_ON(connector->dev, !size); 2682 2683 drm_edid = _drm_edid_alloc(edid, size); 2684 if (!drm_edid) 2685 kfree(edid); 2686 2687 return drm_edid; 2688 } 2689 EXPORT_SYMBOL(drm_edid_read_custom); 2690 2691 /** 2692 * drm_edid_read_ddc - Read EDID data using given I2C adapter 2693 * @connector: Connector to use 2694 * @adapter: I2C adapter to use for DDC 2695 * 2696 * Read EDID using the given I2C adapter. 2697 * 2698 * The EDID may be overridden using debugfs override_edid or firmware EDID 2699 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2700 * order. Having either of them bypasses actual EDID reads. 2701 * 2702 * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and 2703 * using drm_edid_read() instead of this function. 2704 * 2705 * The returned pointer must be freed using drm_edid_free(). 2706 * 2707 * Return: Pointer to EDID, or NULL if probe/read failed. 2708 */ 2709 const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector, 2710 struct i2c_adapter *adapter) 2711 { 2712 const struct drm_edid *drm_edid; 2713 2714 if (connector->force == DRM_FORCE_OFF) 2715 return NULL; 2716 2717 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2718 return NULL; 2719 2720 drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter); 2721 2722 /* Note: Do *not* call connector updates here. */ 2723 2724 return drm_edid; 2725 } 2726 EXPORT_SYMBOL(drm_edid_read_ddc); 2727 2728 /** 2729 * drm_edid_read - Read EDID data using connector's I2C adapter 2730 * @connector: Connector to use 2731 * 2732 * Read EDID using the connector's I2C adapter. 2733 * 2734 * The EDID may be overridden using debugfs override_edid or firmware EDID 2735 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2736 * order. Having either of them bypasses actual EDID reads. 2737 * 2738 * The returned pointer must be freed using drm_edid_free(). 2739 * 2740 * Return: Pointer to EDID, or NULL if probe/read failed. 2741 */ 2742 const struct drm_edid *drm_edid_read(struct drm_connector *connector) 2743 { 2744 if (drm_WARN_ON(connector->dev, !connector->ddc)) 2745 return NULL; 2746 2747 return drm_edid_read_ddc(connector, connector->ddc); 2748 } 2749 EXPORT_SYMBOL(drm_edid_read); 2750 2751 static u32 edid_extract_panel_id(const struct edid *edid) 2752 { 2753 /* 2754 * We represent the ID as a 32-bit number so it can easily be compared 2755 * with "==". 2756 * 2757 * NOTE that we deal with endianness differently for the top half 2758 * of this ID than for the bottom half. The bottom half (the product 2759 * id) gets decoded as little endian by the EDID_PRODUCT_ID because 2760 * that's how everyone seems to interpret it. The top half (the mfg_id) 2761 * gets stored as big endian because that makes 2762 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier 2763 * to write (it's easier to extract the ASCII). It doesn't really 2764 * matter, though, as long as the number here is unique. 2765 */ 2766 return (u32)edid->mfg_id[0] << 24 | 2767 (u32)edid->mfg_id[1] << 16 | 2768 (u32)EDID_PRODUCT_ID(edid); 2769 } 2770 2771 /** 2772 * drm_edid_get_panel_id - Get a panel's ID through DDC 2773 * @adapter: I2C adapter to use for DDC 2774 * 2775 * This function reads the first block of the EDID of a panel and (assuming 2776 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value 2777 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's 2778 * supposed to be different for each different modem of panel. 2779 * 2780 * This function is intended to be used during early probing on devices where 2781 * more than one panel might be present. Because of its intended use it must 2782 * assume that the EDID of the panel is correct, at least as far as the ID 2783 * is concerned (in other words, we don't process any overrides here). 2784 * 2785 * NOTE: it's expected that this function and drm_do_get_edid() will both 2786 * be read the EDID, but there is no caching between them. Since we're only 2787 * reading the first block, hopefully this extra overhead won't be too big. 2788 * 2789 * Return: A 32-bit ID that should be different for each make/model of panel. 2790 * See the functions drm_edid_encode_panel_id() and 2791 * drm_edid_decode_panel_id() for some details on the structure of this 2792 * ID. 2793 */ 2794 2795 u32 drm_edid_get_panel_id(struct i2c_adapter *adapter) 2796 { 2797 enum edid_block_status status; 2798 void *base_block; 2799 u32 panel_id = 0; 2800 2801 /* 2802 * There are no manufacturer IDs of 0, so if there is a problem reading 2803 * the EDID then we'll just return 0. 2804 */ 2805 2806 base_block = kzalloc(EDID_LENGTH, GFP_KERNEL); 2807 if (!base_block) 2808 return 0; 2809 2810 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter); 2811 2812 edid_block_status_print(status, base_block, 0); 2813 2814 if (edid_block_status_valid(status, edid_block_tag(base_block))) 2815 panel_id = edid_extract_panel_id(base_block); 2816 else 2817 edid_block_dump(KERN_NOTICE, base_block, 0); 2818 2819 kfree(base_block); 2820 2821 return panel_id; 2822 } 2823 EXPORT_SYMBOL(drm_edid_get_panel_id); 2824 2825 /** 2826 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 2827 * @connector: connector we're probing 2828 * @adapter: I2C adapter to use for DDC 2829 * 2830 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 2831 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 2832 * switch DDC to the GPU which is retrieving EDID. 2833 * 2834 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2835 */ 2836 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 2837 struct i2c_adapter *adapter) 2838 { 2839 struct drm_device *dev = connector->dev; 2840 struct pci_dev *pdev = to_pci_dev(dev->dev); 2841 struct edid *edid; 2842 2843 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev))) 2844 return NULL; 2845 2846 vga_switcheroo_lock_ddc(pdev); 2847 edid = drm_get_edid(connector, adapter); 2848 vga_switcheroo_unlock_ddc(pdev); 2849 2850 return edid; 2851 } 2852 EXPORT_SYMBOL(drm_get_edid_switcheroo); 2853 2854 /** 2855 * drm_edid_read_switcheroo - get EDID data for a vga_switcheroo output 2856 * @connector: connector we're probing 2857 * @adapter: I2C adapter to use for DDC 2858 * 2859 * Wrapper around drm_edid_read_ddc() for laptops with dual GPUs using one set 2860 * of outputs. The wrapper adds the requisite vga_switcheroo calls to 2861 * temporarily switch DDC to the GPU which is retrieving EDID. 2862 * 2863 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2864 */ 2865 const struct drm_edid *drm_edid_read_switcheroo(struct drm_connector *connector, 2866 struct i2c_adapter *adapter) 2867 { 2868 struct drm_device *dev = connector->dev; 2869 struct pci_dev *pdev = to_pci_dev(dev->dev); 2870 const struct drm_edid *drm_edid; 2871 2872 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev))) 2873 return NULL; 2874 2875 vga_switcheroo_lock_ddc(pdev); 2876 drm_edid = drm_edid_read_ddc(connector, adapter); 2877 vga_switcheroo_unlock_ddc(pdev); 2878 2879 return drm_edid; 2880 } 2881 EXPORT_SYMBOL(drm_edid_read_switcheroo); 2882 2883 /** 2884 * drm_edid_duplicate - duplicate an EDID and the extensions 2885 * @edid: EDID to duplicate 2886 * 2887 * Return: Pointer to duplicated EDID or NULL on allocation failure. 2888 */ 2889 struct edid *drm_edid_duplicate(const struct edid *edid) 2890 { 2891 if (!edid) 2892 return NULL; 2893 2894 return kmemdup(edid, edid_size(edid), GFP_KERNEL); 2895 } 2896 EXPORT_SYMBOL(drm_edid_duplicate); 2897 2898 /*** EDID parsing ***/ 2899 2900 /** 2901 * edid_get_quirks - return quirk flags for a given EDID 2902 * @drm_edid: EDID to process 2903 * 2904 * This tells subsequent routines what fixes they need to apply. 2905 */ 2906 static u32 edid_get_quirks(const struct drm_edid *drm_edid) 2907 { 2908 u32 panel_id = edid_extract_panel_id(drm_edid->edid); 2909 const struct edid_quirk *quirk; 2910 int i; 2911 2912 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 2913 quirk = &edid_quirk_list[i]; 2914 if (quirk->panel_id == panel_id) 2915 return quirk->quirks; 2916 } 2917 2918 return 0; 2919 } 2920 2921 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 2922 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 2923 2924 /* 2925 * Walk the mode list for connector, clearing the preferred status on existing 2926 * modes and setting it anew for the right mode ala quirks. 2927 */ 2928 static void edid_fixup_preferred(struct drm_connector *connector) 2929 { 2930 const struct drm_display_info *info = &connector->display_info; 2931 struct drm_display_mode *t, *cur_mode, *preferred_mode; 2932 int target_refresh = 0; 2933 int cur_vrefresh, preferred_vrefresh; 2934 2935 if (list_empty(&connector->probed_modes)) 2936 return; 2937 2938 if (info->quirks & EDID_QUIRK_PREFER_LARGE_60) 2939 target_refresh = 60; 2940 if (info->quirks & EDID_QUIRK_PREFER_LARGE_75) 2941 target_refresh = 75; 2942 2943 preferred_mode = list_first_entry(&connector->probed_modes, 2944 struct drm_display_mode, head); 2945 2946 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 2947 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 2948 2949 if (cur_mode == preferred_mode) 2950 continue; 2951 2952 /* Largest mode is preferred */ 2953 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 2954 preferred_mode = cur_mode; 2955 2956 cur_vrefresh = drm_mode_vrefresh(cur_mode); 2957 preferred_vrefresh = drm_mode_vrefresh(preferred_mode); 2958 /* At a given size, try to get closest to target refresh */ 2959 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 2960 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 2961 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 2962 preferred_mode = cur_mode; 2963 } 2964 } 2965 2966 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 2967 } 2968 2969 static bool 2970 mode_is_rb(const struct drm_display_mode *mode) 2971 { 2972 return (mode->htotal - mode->hdisplay == 160) && 2973 (mode->hsync_end - mode->hdisplay == 80) && 2974 (mode->hsync_end - mode->hsync_start == 32) && 2975 (mode->vsync_start - mode->vdisplay == 3); 2976 } 2977 2978 /* 2979 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 2980 * @dev: Device to duplicate against 2981 * @hsize: Mode width 2982 * @vsize: Mode height 2983 * @fresh: Mode refresh rate 2984 * @rb: Mode reduced-blanking-ness 2985 * 2986 * Walk the DMT mode list looking for a match for the given parameters. 2987 * 2988 * Return: A newly allocated copy of the mode, or NULL if not found. 2989 */ 2990 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 2991 int hsize, int vsize, int fresh, 2992 bool rb) 2993 { 2994 int i; 2995 2996 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2997 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 2998 2999 if (hsize != ptr->hdisplay) 3000 continue; 3001 if (vsize != ptr->vdisplay) 3002 continue; 3003 if (fresh != drm_mode_vrefresh(ptr)) 3004 continue; 3005 if (rb != mode_is_rb(ptr)) 3006 continue; 3007 3008 return drm_mode_duplicate(dev, ptr); 3009 } 3010 3011 return NULL; 3012 } 3013 EXPORT_SYMBOL(drm_mode_find_dmt); 3014 3015 static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type) 3016 { 3017 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0); 3018 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2); 3019 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3); 3020 3021 return descriptor->pixel_clock == 0 && 3022 descriptor->data.other_data.pad1 == 0 && 3023 descriptor->data.other_data.type == type; 3024 } 3025 3026 static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor) 3027 { 3028 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0); 3029 3030 return descriptor->pixel_clock != 0; 3031 } 3032 3033 typedef void detailed_cb(const struct detailed_timing *timing, void *closure); 3034 3035 static void 3036 cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure) 3037 { 3038 int i, n; 3039 u8 d = ext[0x02]; 3040 const u8 *det_base = ext + d; 3041 3042 if (d < 4 || d > 127) 3043 return; 3044 3045 n = (127 - d) / 18; 3046 for (i = 0; i < n; i++) 3047 cb((const struct detailed_timing *)(det_base + 18 * i), closure); 3048 } 3049 3050 static void 3051 vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure) 3052 { 3053 unsigned int i, n = min((int)ext[0x02], 6); 3054 const u8 *det_base = ext + 5; 3055 3056 if (ext[0x01] != 1) 3057 return; /* unknown version */ 3058 3059 for (i = 0; i < n; i++) 3060 cb((const struct detailed_timing *)(det_base + 18 * i), closure); 3061 } 3062 3063 static void drm_for_each_detailed_block(const struct drm_edid *drm_edid, 3064 detailed_cb *cb, void *closure) 3065 { 3066 struct drm_edid_iter edid_iter; 3067 const u8 *ext; 3068 int i; 3069 3070 if (!drm_edid) 3071 return; 3072 3073 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 3074 cb(&drm_edid->edid->detailed_timings[i], closure); 3075 3076 drm_edid_iter_begin(drm_edid, &edid_iter); 3077 drm_edid_iter_for_each(ext, &edid_iter) { 3078 switch (*ext) { 3079 case CEA_EXT: 3080 cea_for_each_detailed_block(ext, cb, closure); 3081 break; 3082 case VTB_EXT: 3083 vtb_for_each_detailed_block(ext, cb, closure); 3084 break; 3085 default: 3086 break; 3087 } 3088 } 3089 drm_edid_iter_end(&edid_iter); 3090 } 3091 3092 static void 3093 is_rb(const struct detailed_timing *descriptor, void *data) 3094 { 3095 bool *res = data; 3096 3097 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 3098 return; 3099 3100 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 3101 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15); 3102 3103 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG && 3104 descriptor->data.other_data.data.range.formula.cvt.flags & DRM_EDID_CVT_FLAGS_REDUCED_BLANKING) 3105 *res = true; 3106 } 3107 3108 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 3109 static bool 3110 drm_monitor_supports_rb(const struct drm_edid *drm_edid) 3111 { 3112 if (drm_edid->edid->revision >= 4) { 3113 bool ret = false; 3114 3115 drm_for_each_detailed_block(drm_edid, is_rb, &ret); 3116 return ret; 3117 } 3118 3119 return drm_edid_is_digital(drm_edid); 3120 } 3121 3122 static void 3123 find_gtf2(const struct detailed_timing *descriptor, void *data) 3124 { 3125 const struct detailed_timing **res = data; 3126 3127 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 3128 return; 3129 3130 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 3131 3132 if (descriptor->data.other_data.data.range.flags == DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG) 3133 *res = descriptor; 3134 } 3135 3136 /* Secondary GTF curve kicks in above some break frequency */ 3137 static int 3138 drm_gtf2_hbreak(const struct drm_edid *drm_edid) 3139 { 3140 const struct detailed_timing *descriptor = NULL; 3141 3142 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3143 3144 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12); 3145 3146 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0; 3147 } 3148 3149 static int 3150 drm_gtf2_2c(const struct drm_edid *drm_edid) 3151 { 3152 const struct detailed_timing *descriptor = NULL; 3153 3154 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3155 3156 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13); 3157 3158 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0; 3159 } 3160 3161 static int 3162 drm_gtf2_m(const struct drm_edid *drm_edid) 3163 { 3164 const struct detailed_timing *descriptor = NULL; 3165 3166 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3167 3168 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14); 3169 3170 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0; 3171 } 3172 3173 static int 3174 drm_gtf2_k(const struct drm_edid *drm_edid) 3175 { 3176 const struct detailed_timing *descriptor = NULL; 3177 3178 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3179 3180 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16); 3181 3182 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0; 3183 } 3184 3185 static int 3186 drm_gtf2_2j(const struct drm_edid *drm_edid) 3187 { 3188 const struct detailed_timing *descriptor = NULL; 3189 3190 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3191 3192 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17); 3193 3194 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0; 3195 } 3196 3197 static void 3198 get_timing_level(const struct detailed_timing *descriptor, void *data) 3199 { 3200 int *res = data; 3201 3202 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 3203 return; 3204 3205 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 3206 3207 switch (descriptor->data.other_data.data.range.flags) { 3208 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG: 3209 *res = LEVEL_GTF; 3210 break; 3211 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG: 3212 *res = LEVEL_GTF2; 3213 break; 3214 case DRM_EDID_CVT_SUPPORT_FLAG: 3215 *res = LEVEL_CVT; 3216 break; 3217 default: 3218 break; 3219 } 3220 } 3221 3222 /* Get standard timing level (CVT/GTF/DMT). */ 3223 static int standard_timing_level(const struct drm_edid *drm_edid) 3224 { 3225 const struct edid *edid = drm_edid->edid; 3226 3227 if (edid->revision >= 4) { 3228 /* 3229 * If the range descriptor doesn't 3230 * indicate otherwise default to CVT 3231 */ 3232 int ret = LEVEL_CVT; 3233 3234 drm_for_each_detailed_block(drm_edid, get_timing_level, &ret); 3235 3236 return ret; 3237 } else if (edid->revision >= 3 && drm_gtf2_hbreak(drm_edid)) { 3238 return LEVEL_GTF2; 3239 } else if (edid->revision >= 2) { 3240 return LEVEL_GTF; 3241 } else { 3242 return LEVEL_DMT; 3243 } 3244 } 3245 3246 /* 3247 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 3248 * monitors fill with ascii space (0x20) instead. 3249 */ 3250 static int 3251 bad_std_timing(u8 a, u8 b) 3252 { 3253 return (a == 0x00 && b == 0x00) || 3254 (a == 0x01 && b == 0x01) || 3255 (a == 0x20 && b == 0x20); 3256 } 3257 3258 static int drm_mode_hsync(const struct drm_display_mode *mode) 3259 { 3260 if (mode->htotal <= 0) 3261 return 0; 3262 3263 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal); 3264 } 3265 3266 static struct drm_display_mode * 3267 drm_gtf2_mode(struct drm_device *dev, 3268 const struct drm_edid *drm_edid, 3269 int hsize, int vsize, int vrefresh_rate) 3270 { 3271 struct drm_display_mode *mode; 3272 3273 /* 3274 * This is potentially wrong if there's ever a monitor with 3275 * more than one ranges section, each claiming a different 3276 * secondary GTF curve. Please don't do that. 3277 */ 3278 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 3279 if (!mode) 3280 return NULL; 3281 3282 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) { 3283 drm_mode_destroy(dev, mode); 3284 mode = drm_gtf_mode_complex(dev, hsize, vsize, 3285 vrefresh_rate, 0, 0, 3286 drm_gtf2_m(drm_edid), 3287 drm_gtf2_2c(drm_edid), 3288 drm_gtf2_k(drm_edid), 3289 drm_gtf2_2j(drm_edid)); 3290 } 3291 3292 return mode; 3293 } 3294 3295 /* 3296 * Take the standard timing params (in this case width, aspect, and refresh) 3297 * and convert them into a real mode using CVT/GTF/DMT. 3298 */ 3299 static struct drm_display_mode *drm_mode_std(struct drm_connector *connector, 3300 const struct drm_edid *drm_edid, 3301 const struct std_timing *t) 3302 { 3303 struct drm_device *dev = connector->dev; 3304 struct drm_display_mode *m, *mode = NULL; 3305 int hsize, vsize; 3306 int vrefresh_rate; 3307 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 3308 >> EDID_TIMING_ASPECT_SHIFT; 3309 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 3310 >> EDID_TIMING_VFREQ_SHIFT; 3311 int timing_level = standard_timing_level(drm_edid); 3312 3313 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 3314 return NULL; 3315 3316 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 3317 hsize = t->hsize * 8 + 248; 3318 /* vrefresh_rate = vfreq + 60 */ 3319 vrefresh_rate = vfreq + 60; 3320 /* the vdisplay is calculated based on the aspect ratio */ 3321 if (aspect_ratio == 0) { 3322 if (drm_edid->edid->revision < 3) 3323 vsize = hsize; 3324 else 3325 vsize = (hsize * 10) / 16; 3326 } else if (aspect_ratio == 1) 3327 vsize = (hsize * 3) / 4; 3328 else if (aspect_ratio == 2) 3329 vsize = (hsize * 4) / 5; 3330 else 3331 vsize = (hsize * 9) / 16; 3332 3333 /* HDTV hack, part 1 */ 3334 if (vrefresh_rate == 60 && 3335 ((hsize == 1360 && vsize == 765) || 3336 (hsize == 1368 && vsize == 769))) { 3337 hsize = 1366; 3338 vsize = 768; 3339 } 3340 3341 /* 3342 * If this connector already has a mode for this size and refresh 3343 * rate (because it came from detailed or CVT info), use that 3344 * instead. This way we don't have to guess at interlace or 3345 * reduced blanking. 3346 */ 3347 list_for_each_entry(m, &connector->probed_modes, head) 3348 if (m->hdisplay == hsize && m->vdisplay == vsize && 3349 drm_mode_vrefresh(m) == vrefresh_rate) 3350 return NULL; 3351 3352 /* HDTV hack, part 2 */ 3353 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 3354 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 3355 false); 3356 if (!mode) 3357 return NULL; 3358 mode->hdisplay = 1366; 3359 mode->hsync_start = mode->hsync_start - 1; 3360 mode->hsync_end = mode->hsync_end - 1; 3361 return mode; 3362 } 3363 3364 /* check whether it can be found in default mode table */ 3365 if (drm_monitor_supports_rb(drm_edid)) { 3366 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 3367 true); 3368 if (mode) 3369 return mode; 3370 } 3371 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 3372 if (mode) 3373 return mode; 3374 3375 /* okay, generate it */ 3376 switch (timing_level) { 3377 case LEVEL_DMT: 3378 break; 3379 case LEVEL_GTF: 3380 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 3381 break; 3382 case LEVEL_GTF2: 3383 mode = drm_gtf2_mode(dev, drm_edid, hsize, vsize, vrefresh_rate); 3384 break; 3385 case LEVEL_CVT: 3386 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 3387 false); 3388 break; 3389 } 3390 return mode; 3391 } 3392 3393 /* 3394 * EDID is delightfully ambiguous about how interlaced modes are to be 3395 * encoded. Our internal representation is of frame height, but some 3396 * HDTV detailed timings are encoded as field height. 3397 * 3398 * The format list here is from CEA, in frame size. Technically we 3399 * should be checking refresh rate too. Whatever. 3400 */ 3401 static void 3402 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 3403 const struct detailed_pixel_timing *pt) 3404 { 3405 int i; 3406 static const struct { 3407 int w, h; 3408 } cea_interlaced[] = { 3409 { 1920, 1080 }, 3410 { 720, 480 }, 3411 { 1440, 480 }, 3412 { 2880, 480 }, 3413 { 720, 576 }, 3414 { 1440, 576 }, 3415 { 2880, 576 }, 3416 }; 3417 3418 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 3419 return; 3420 3421 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 3422 if ((mode->hdisplay == cea_interlaced[i].w) && 3423 (mode->vdisplay == cea_interlaced[i].h / 2)) { 3424 mode->vdisplay *= 2; 3425 mode->vsync_start *= 2; 3426 mode->vsync_end *= 2; 3427 mode->vtotal *= 2; 3428 mode->vtotal |= 1; 3429 } 3430 } 3431 3432 mode->flags |= DRM_MODE_FLAG_INTERLACE; 3433 } 3434 3435 /* 3436 * Create a new mode from an EDID detailed timing section. An EDID detailed 3437 * timing block contains enough info for us to create and return a new struct 3438 * drm_display_mode. 3439 */ 3440 static struct drm_display_mode *drm_mode_detailed(struct drm_connector *connector, 3441 const struct drm_edid *drm_edid, 3442 const struct detailed_timing *timing) 3443 { 3444 const struct drm_display_info *info = &connector->display_info; 3445 struct drm_device *dev = connector->dev; 3446 struct drm_display_mode *mode; 3447 const struct detailed_pixel_timing *pt = &timing->data.pixel_data; 3448 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 3449 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 3450 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 3451 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 3452 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 3453 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 3454 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 3455 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 3456 3457 /* ignore tiny modes */ 3458 if (hactive < 64 || vactive < 64) 3459 return NULL; 3460 3461 if (pt->misc & DRM_EDID_PT_STEREO) { 3462 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Stereo mode not supported\n", 3463 connector->base.id, connector->name); 3464 return NULL; 3465 } 3466 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 3467 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Composite sync not supported\n", 3468 connector->base.id, connector->name); 3469 } 3470 3471 /* it is incorrect if hsync/vsync width is zero */ 3472 if (!hsync_pulse_width || !vsync_pulse_width) { 3473 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Incorrect Detailed timing. Wrong Hsync/Vsync pulse width\n", 3474 connector->base.id, connector->name); 3475 return NULL; 3476 } 3477 3478 if (info->quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 3479 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 3480 if (!mode) 3481 return NULL; 3482 3483 goto set_size; 3484 } 3485 3486 mode = drm_mode_create(dev); 3487 if (!mode) 3488 return NULL; 3489 3490 if (info->quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 3491 mode->clock = 1088 * 10; 3492 else 3493 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 3494 3495 mode->hdisplay = hactive; 3496 mode->hsync_start = mode->hdisplay + hsync_offset; 3497 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 3498 mode->htotal = mode->hdisplay + hblank; 3499 3500 mode->vdisplay = vactive; 3501 mode->vsync_start = mode->vdisplay + vsync_offset; 3502 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 3503 mode->vtotal = mode->vdisplay + vblank; 3504 3505 /* Some EDIDs have bogus h/vsync_end values */ 3506 if (mode->hsync_end > mode->htotal) { 3507 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing hsync_end %d->%d\n", 3508 connector->base.id, connector->name, 3509 mode->hsync_end, mode->htotal); 3510 mode->hsync_end = mode->htotal; 3511 } 3512 if (mode->vsync_end > mode->vtotal) { 3513 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing vsync_end %d->%d\n", 3514 connector->base.id, connector->name, 3515 mode->vsync_end, mode->vtotal); 3516 mode->vsync_end = mode->vtotal; 3517 } 3518 3519 drm_mode_do_interlace_quirk(mode, pt); 3520 3521 if (info->quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 3522 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC; 3523 } else { 3524 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 3525 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 3526 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 3527 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 3528 } 3529 3530 set_size: 3531 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 3532 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 3533 3534 if (info->quirks & EDID_QUIRK_DETAILED_IN_CM) { 3535 mode->width_mm *= 10; 3536 mode->height_mm *= 10; 3537 } 3538 3539 if (info->quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 3540 mode->width_mm = drm_edid->edid->width_cm * 10; 3541 mode->height_mm = drm_edid->edid->height_cm * 10; 3542 } 3543 3544 mode->type = DRM_MODE_TYPE_DRIVER; 3545 drm_mode_set_name(mode); 3546 3547 return mode; 3548 } 3549 3550 static bool 3551 mode_in_hsync_range(const struct drm_display_mode *mode, 3552 const struct edid *edid, const u8 *t) 3553 { 3554 int hsync, hmin, hmax; 3555 3556 hmin = t[7]; 3557 if (edid->revision >= 4) 3558 hmin += ((t[4] & 0x04) ? 255 : 0); 3559 hmax = t[8]; 3560 if (edid->revision >= 4) 3561 hmax += ((t[4] & 0x08) ? 255 : 0); 3562 hsync = drm_mode_hsync(mode); 3563 3564 return (hsync <= hmax && hsync >= hmin); 3565 } 3566 3567 static bool 3568 mode_in_vsync_range(const struct drm_display_mode *mode, 3569 const struct edid *edid, const u8 *t) 3570 { 3571 int vsync, vmin, vmax; 3572 3573 vmin = t[5]; 3574 if (edid->revision >= 4) 3575 vmin += ((t[4] & 0x01) ? 255 : 0); 3576 vmax = t[6]; 3577 if (edid->revision >= 4) 3578 vmax += ((t[4] & 0x02) ? 255 : 0); 3579 vsync = drm_mode_vrefresh(mode); 3580 3581 return (vsync <= vmax && vsync >= vmin); 3582 } 3583 3584 static u32 3585 range_pixel_clock(const struct edid *edid, const u8 *t) 3586 { 3587 /* unspecified */ 3588 if (t[9] == 0 || t[9] == 255) 3589 return 0; 3590 3591 /* 1.4 with CVT support gives us real precision, yay */ 3592 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG) 3593 return (t[9] * 10000) - ((t[12] >> 2) * 250); 3594 3595 /* 1.3 is pathetic, so fuzz up a bit */ 3596 return t[9] * 10000 + 5001; 3597 } 3598 3599 static bool mode_in_range(const struct drm_display_mode *mode, 3600 const struct drm_edid *drm_edid, 3601 const struct detailed_timing *timing) 3602 { 3603 const struct edid *edid = drm_edid->edid; 3604 u32 max_clock; 3605 const u8 *t = (const u8 *)timing; 3606 3607 if (!mode_in_hsync_range(mode, edid, t)) 3608 return false; 3609 3610 if (!mode_in_vsync_range(mode, edid, t)) 3611 return false; 3612 3613 if ((max_clock = range_pixel_clock(edid, t))) 3614 if (mode->clock > max_clock) 3615 return false; 3616 3617 /* 1.4 max horizontal check */ 3618 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG) 3619 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 3620 return false; 3621 3622 if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid)) 3623 return false; 3624 3625 return true; 3626 } 3627 3628 static bool valid_inferred_mode(const struct drm_connector *connector, 3629 const struct drm_display_mode *mode) 3630 { 3631 const struct drm_display_mode *m; 3632 bool ok = false; 3633 3634 list_for_each_entry(m, &connector->probed_modes, head) { 3635 if (mode->hdisplay == m->hdisplay && 3636 mode->vdisplay == m->vdisplay && 3637 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 3638 return false; /* duplicated */ 3639 if (mode->hdisplay <= m->hdisplay && 3640 mode->vdisplay <= m->vdisplay) 3641 ok = true; 3642 } 3643 return ok; 3644 } 3645 3646 static int drm_dmt_modes_for_range(struct drm_connector *connector, 3647 const struct drm_edid *drm_edid, 3648 const struct detailed_timing *timing) 3649 { 3650 int i, modes = 0; 3651 struct drm_display_mode *newmode; 3652 struct drm_device *dev = connector->dev; 3653 3654 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 3655 if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) && 3656 valid_inferred_mode(connector, drm_dmt_modes + i)) { 3657 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 3658 if (newmode) { 3659 drm_mode_probed_add(connector, newmode); 3660 modes++; 3661 } 3662 } 3663 } 3664 3665 return modes; 3666 } 3667 3668 /* fix up 1366x768 mode from 1368x768; 3669 * GFT/CVT can't express 1366 width which isn't dividable by 8 3670 */ 3671 void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 3672 { 3673 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 3674 mode->hdisplay = 1366; 3675 mode->hsync_start--; 3676 mode->hsync_end--; 3677 drm_mode_set_name(mode); 3678 } 3679 } 3680 3681 static int drm_gtf_modes_for_range(struct drm_connector *connector, 3682 const struct drm_edid *drm_edid, 3683 const struct detailed_timing *timing) 3684 { 3685 int i, modes = 0; 3686 struct drm_display_mode *newmode; 3687 struct drm_device *dev = connector->dev; 3688 3689 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3690 const struct minimode *m = &extra_modes[i]; 3691 3692 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 3693 if (!newmode) 3694 return modes; 3695 3696 drm_mode_fixup_1366x768(newmode); 3697 if (!mode_in_range(newmode, drm_edid, timing) || 3698 !valid_inferred_mode(connector, newmode)) { 3699 drm_mode_destroy(dev, newmode); 3700 continue; 3701 } 3702 3703 drm_mode_probed_add(connector, newmode); 3704 modes++; 3705 } 3706 3707 return modes; 3708 } 3709 3710 static int drm_gtf2_modes_for_range(struct drm_connector *connector, 3711 const struct drm_edid *drm_edid, 3712 const struct detailed_timing *timing) 3713 { 3714 int i, modes = 0; 3715 struct drm_display_mode *newmode; 3716 struct drm_device *dev = connector->dev; 3717 3718 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3719 const struct minimode *m = &extra_modes[i]; 3720 3721 newmode = drm_gtf2_mode(dev, drm_edid, m->w, m->h, m->r); 3722 if (!newmode) 3723 return modes; 3724 3725 drm_mode_fixup_1366x768(newmode); 3726 if (!mode_in_range(newmode, drm_edid, timing) || 3727 !valid_inferred_mode(connector, newmode)) { 3728 drm_mode_destroy(dev, newmode); 3729 continue; 3730 } 3731 3732 drm_mode_probed_add(connector, newmode); 3733 modes++; 3734 } 3735 3736 return modes; 3737 } 3738 3739 static int drm_cvt_modes_for_range(struct drm_connector *connector, 3740 const struct drm_edid *drm_edid, 3741 const struct detailed_timing *timing) 3742 { 3743 int i, modes = 0; 3744 struct drm_display_mode *newmode; 3745 struct drm_device *dev = connector->dev; 3746 bool rb = drm_monitor_supports_rb(drm_edid); 3747 3748 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3749 const struct minimode *m = &extra_modes[i]; 3750 3751 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 3752 if (!newmode) 3753 return modes; 3754 3755 drm_mode_fixup_1366x768(newmode); 3756 if (!mode_in_range(newmode, drm_edid, timing) || 3757 !valid_inferred_mode(connector, newmode)) { 3758 drm_mode_destroy(dev, newmode); 3759 continue; 3760 } 3761 3762 drm_mode_probed_add(connector, newmode); 3763 modes++; 3764 } 3765 3766 return modes; 3767 } 3768 3769 static void 3770 do_inferred_modes(const struct detailed_timing *timing, void *c) 3771 { 3772 struct detailed_mode_closure *closure = c; 3773 const struct detailed_non_pixel *data = &timing->data.other_data; 3774 const struct detailed_data_monitor_range *range = &data->data.range; 3775 3776 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE)) 3777 return; 3778 3779 closure->modes += drm_dmt_modes_for_range(closure->connector, 3780 closure->drm_edid, 3781 timing); 3782 3783 if (closure->drm_edid->edid->revision < 2) 3784 return; /* GTF not defined yet */ 3785 3786 switch (range->flags) { 3787 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG: 3788 closure->modes += drm_gtf2_modes_for_range(closure->connector, 3789 closure->drm_edid, 3790 timing); 3791 break; 3792 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG: 3793 closure->modes += drm_gtf_modes_for_range(closure->connector, 3794 closure->drm_edid, 3795 timing); 3796 break; 3797 case DRM_EDID_CVT_SUPPORT_FLAG: 3798 if (closure->drm_edid->edid->revision < 4) 3799 break; 3800 3801 closure->modes += drm_cvt_modes_for_range(closure->connector, 3802 closure->drm_edid, 3803 timing); 3804 break; 3805 case DRM_EDID_RANGE_LIMITS_ONLY_FLAG: 3806 default: 3807 break; 3808 } 3809 } 3810 3811 static int add_inferred_modes(struct drm_connector *connector, 3812 const struct drm_edid *drm_edid) 3813 { 3814 struct detailed_mode_closure closure = { 3815 .connector = connector, 3816 .drm_edid = drm_edid, 3817 }; 3818 3819 if (drm_edid->edid->revision >= 1) 3820 drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure); 3821 3822 return closure.modes; 3823 } 3824 3825 static int 3826 drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing) 3827 { 3828 int i, j, m, modes = 0; 3829 struct drm_display_mode *mode; 3830 const u8 *est = ((const u8 *)timing) + 6; 3831 3832 for (i = 0; i < 6; i++) { 3833 for (j = 7; j >= 0; j--) { 3834 m = (i * 8) + (7 - j); 3835 if (m >= ARRAY_SIZE(est3_modes)) 3836 break; 3837 if (est[i] & (1 << j)) { 3838 mode = drm_mode_find_dmt(connector->dev, 3839 est3_modes[m].w, 3840 est3_modes[m].h, 3841 est3_modes[m].r, 3842 est3_modes[m].rb); 3843 if (mode) { 3844 drm_mode_probed_add(connector, mode); 3845 modes++; 3846 } 3847 } 3848 } 3849 } 3850 3851 return modes; 3852 } 3853 3854 static void 3855 do_established_modes(const struct detailed_timing *timing, void *c) 3856 { 3857 struct detailed_mode_closure *closure = c; 3858 3859 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS)) 3860 return; 3861 3862 closure->modes += drm_est3_modes(closure->connector, timing); 3863 } 3864 3865 /* 3866 * Get established modes from EDID and add them. Each EDID block contains a 3867 * bitmap of the supported "established modes" list (defined above). Tease them 3868 * out and add them to the global modes list. 3869 */ 3870 static int add_established_modes(struct drm_connector *connector, 3871 const struct drm_edid *drm_edid) 3872 { 3873 struct drm_device *dev = connector->dev; 3874 const struct edid *edid = drm_edid->edid; 3875 unsigned long est_bits = edid->established_timings.t1 | 3876 (edid->established_timings.t2 << 8) | 3877 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 3878 int i, modes = 0; 3879 struct detailed_mode_closure closure = { 3880 .connector = connector, 3881 .drm_edid = drm_edid, 3882 }; 3883 3884 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 3885 if (est_bits & (1<<i)) { 3886 struct drm_display_mode *newmode; 3887 3888 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 3889 if (newmode) { 3890 drm_mode_probed_add(connector, newmode); 3891 modes++; 3892 } 3893 } 3894 } 3895 3896 if (edid->revision >= 1) 3897 drm_for_each_detailed_block(drm_edid, do_established_modes, 3898 &closure); 3899 3900 return modes + closure.modes; 3901 } 3902 3903 static void 3904 do_standard_modes(const struct detailed_timing *timing, void *c) 3905 { 3906 struct detailed_mode_closure *closure = c; 3907 const struct detailed_non_pixel *data = &timing->data.other_data; 3908 struct drm_connector *connector = closure->connector; 3909 int i; 3910 3911 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES)) 3912 return; 3913 3914 for (i = 0; i < 6; i++) { 3915 const struct std_timing *std = &data->data.timings[i]; 3916 struct drm_display_mode *newmode; 3917 3918 newmode = drm_mode_std(connector, closure->drm_edid, std); 3919 if (newmode) { 3920 drm_mode_probed_add(connector, newmode); 3921 closure->modes++; 3922 } 3923 } 3924 } 3925 3926 /* 3927 * Get standard modes from EDID and add them. Standard modes can be calculated 3928 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and 3929 * add them to the list. 3930 */ 3931 static int add_standard_modes(struct drm_connector *connector, 3932 const struct drm_edid *drm_edid) 3933 { 3934 int i, modes = 0; 3935 struct detailed_mode_closure closure = { 3936 .connector = connector, 3937 .drm_edid = drm_edid, 3938 }; 3939 3940 for (i = 0; i < EDID_STD_TIMINGS; i++) { 3941 struct drm_display_mode *newmode; 3942 3943 newmode = drm_mode_std(connector, drm_edid, 3944 &drm_edid->edid->standard_timings[i]); 3945 if (newmode) { 3946 drm_mode_probed_add(connector, newmode); 3947 modes++; 3948 } 3949 } 3950 3951 if (drm_edid->edid->revision >= 1) 3952 drm_for_each_detailed_block(drm_edid, do_standard_modes, 3953 &closure); 3954 3955 /* XXX should also look for standard codes in VTB blocks */ 3956 3957 return modes + closure.modes; 3958 } 3959 3960 static int drm_cvt_modes(struct drm_connector *connector, 3961 const struct detailed_timing *timing) 3962 { 3963 int i, j, modes = 0; 3964 struct drm_display_mode *newmode; 3965 struct drm_device *dev = connector->dev; 3966 const struct cvt_timing *cvt; 3967 static const int rates[] = { 60, 85, 75, 60, 50 }; 3968 const u8 empty[3] = { 0, 0, 0 }; 3969 3970 for (i = 0; i < 4; i++) { 3971 int width, height; 3972 3973 cvt = &(timing->data.other_data.data.cvt[i]); 3974 3975 if (!memcmp(cvt->code, empty, 3)) 3976 continue; 3977 3978 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 3979 switch (cvt->code[1] & 0x0c) { 3980 /* default - because compiler doesn't see that we've enumerated all cases */ 3981 default: 3982 case 0x00: 3983 width = height * 4 / 3; 3984 break; 3985 case 0x04: 3986 width = height * 16 / 9; 3987 break; 3988 case 0x08: 3989 width = height * 16 / 10; 3990 break; 3991 case 0x0c: 3992 width = height * 15 / 9; 3993 break; 3994 } 3995 3996 for (j = 1; j < 5; j++) { 3997 if (cvt->code[2] & (1 << j)) { 3998 newmode = drm_cvt_mode(dev, width, height, 3999 rates[j], j == 0, 4000 false, false); 4001 if (newmode) { 4002 drm_mode_probed_add(connector, newmode); 4003 modes++; 4004 } 4005 } 4006 } 4007 } 4008 4009 return modes; 4010 } 4011 4012 static void 4013 do_cvt_mode(const struct detailed_timing *timing, void *c) 4014 { 4015 struct detailed_mode_closure *closure = c; 4016 4017 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE)) 4018 return; 4019 4020 closure->modes += drm_cvt_modes(closure->connector, timing); 4021 } 4022 4023 static int 4024 add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid) 4025 { 4026 struct detailed_mode_closure closure = { 4027 .connector = connector, 4028 .drm_edid = drm_edid, 4029 }; 4030 4031 if (drm_edid->edid->revision >= 3) 4032 drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure); 4033 4034 /* XXX should also look for CVT codes in VTB blocks */ 4035 4036 return closure.modes; 4037 } 4038 4039 static void fixup_detailed_cea_mode_clock(struct drm_connector *connector, 4040 struct drm_display_mode *mode); 4041 4042 static void 4043 do_detailed_mode(const struct detailed_timing *timing, void *c) 4044 { 4045 struct detailed_mode_closure *closure = c; 4046 struct drm_display_mode *newmode; 4047 4048 if (!is_detailed_timing_descriptor(timing)) 4049 return; 4050 4051 newmode = drm_mode_detailed(closure->connector, 4052 closure->drm_edid, timing); 4053 if (!newmode) 4054 return; 4055 4056 if (closure->preferred) 4057 newmode->type |= DRM_MODE_TYPE_PREFERRED; 4058 4059 /* 4060 * Detailed modes are limited to 10kHz pixel clock resolution, 4061 * so fix up anything that looks like CEA/HDMI mode, but the clock 4062 * is just slightly off. 4063 */ 4064 fixup_detailed_cea_mode_clock(closure->connector, newmode); 4065 4066 drm_mode_probed_add(closure->connector, newmode); 4067 closure->modes++; 4068 closure->preferred = false; 4069 } 4070 4071 /* 4072 * add_detailed_modes - Add modes from detailed timings 4073 * @connector: attached connector 4074 * @drm_edid: EDID block to scan 4075 */ 4076 static int add_detailed_modes(struct drm_connector *connector, 4077 const struct drm_edid *drm_edid) 4078 { 4079 struct detailed_mode_closure closure = { 4080 .connector = connector, 4081 .drm_edid = drm_edid, 4082 }; 4083 4084 if (drm_edid->edid->revision >= 4) 4085 closure.preferred = true; /* first detailed timing is always preferred */ 4086 else 4087 closure.preferred = 4088 drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING; 4089 4090 drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure); 4091 4092 return closure.modes; 4093 } 4094 4095 /* CTA-861-H Table 60 - CTA Tag Codes */ 4096 #define CTA_DB_AUDIO 1 4097 #define CTA_DB_VIDEO 2 4098 #define CTA_DB_VENDOR 3 4099 #define CTA_DB_SPEAKER 4 4100 #define CTA_DB_EXTENDED_TAG 7 4101 4102 /* CTA-861-H Table 62 - CTA Extended Tag Codes */ 4103 #define CTA_EXT_DB_VIDEO_CAP 0 4104 #define CTA_EXT_DB_VENDOR 1 4105 #define CTA_EXT_DB_HDR_STATIC_METADATA 6 4106 #define CTA_EXT_DB_420_VIDEO_DATA 14 4107 #define CTA_EXT_DB_420_VIDEO_CAP_MAP 15 4108 #define CTA_EXT_DB_HF_EEODB 0x78 4109 #define CTA_EXT_DB_HF_SCDB 0x79 4110 4111 #define EDID_BASIC_AUDIO (1 << 6) 4112 #define EDID_CEA_YCRCB444 (1 << 5) 4113 #define EDID_CEA_YCRCB422 (1 << 4) 4114 #define EDID_CEA_VCDB_QS (1 << 6) 4115 4116 /* 4117 * Search EDID for CEA extension block. 4118 * 4119 * FIXME: Prefer not returning pointers to raw EDID data. 4120 */ 4121 const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid, 4122 int ext_id, int *ext_index) 4123 { 4124 const u8 *edid_ext = NULL; 4125 int i; 4126 4127 /* No EDID or EDID extensions */ 4128 if (!drm_edid || !drm_edid_extension_block_count(drm_edid)) 4129 return NULL; 4130 4131 /* Find CEA extension */ 4132 for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) { 4133 edid_ext = drm_edid_extension_block_data(drm_edid, i); 4134 if (edid_block_tag(edid_ext) == ext_id) 4135 break; 4136 } 4137 4138 if (i >= drm_edid_extension_block_count(drm_edid)) 4139 return NULL; 4140 4141 *ext_index = i + 1; 4142 4143 return edid_ext; 4144 } 4145 4146 /* Return true if the EDID has a CTA extension or a DisplayID CTA data block */ 4147 static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid) 4148 { 4149 const struct displayid_block *block; 4150 struct displayid_iter iter; 4151 int ext_index = 0; 4152 bool found = false; 4153 4154 /* Look for a top level CEA extension block */ 4155 if (drm_find_edid_extension(drm_edid, CEA_EXT, &ext_index)) 4156 return true; 4157 4158 /* CEA blocks can also be found embedded in a DisplayID block */ 4159 displayid_iter_edid_begin(drm_edid, &iter); 4160 displayid_iter_for_each(block, &iter) { 4161 if (block->tag == DATA_BLOCK_CTA) { 4162 found = true; 4163 break; 4164 } 4165 } 4166 displayid_iter_end(&iter); 4167 4168 return found; 4169 } 4170 4171 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic) 4172 { 4173 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127); 4174 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219); 4175 4176 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1)) 4177 return &edid_cea_modes_1[vic - 1]; 4178 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193)) 4179 return &edid_cea_modes_193[vic - 193]; 4180 return NULL; 4181 } 4182 4183 static u8 cea_num_vics(void) 4184 { 4185 return 193 + ARRAY_SIZE(edid_cea_modes_193); 4186 } 4187 4188 static u8 cea_next_vic(u8 vic) 4189 { 4190 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1)) 4191 vic = 193; 4192 return vic; 4193 } 4194 4195 /* 4196 * Calculate the alternate clock for the CEA mode 4197 * (60Hz vs. 59.94Hz etc.) 4198 */ 4199 static unsigned int 4200 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 4201 { 4202 unsigned int clock = cea_mode->clock; 4203 4204 if (drm_mode_vrefresh(cea_mode) % 6 != 0) 4205 return clock; 4206 4207 /* 4208 * edid_cea_modes contains the 59.94Hz 4209 * variant for 240 and 480 line modes, 4210 * and the 60Hz variant otherwise. 4211 */ 4212 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 4213 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 4214 else 4215 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 4216 4217 return clock; 4218 } 4219 4220 static bool 4221 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 4222 { 4223 /* 4224 * For certain VICs the spec allows the vertical 4225 * front porch to vary by one or two lines. 4226 * 4227 * cea_modes[] stores the variant with the shortest 4228 * vertical front porch. We can adjust the mode to 4229 * get the other variants by simply increasing the 4230 * vertical front porch length. 4231 */ 4232 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 || 4233 cea_mode_for_vic(9)->vtotal != 262 || 4234 cea_mode_for_vic(12)->vtotal != 262 || 4235 cea_mode_for_vic(13)->vtotal != 262 || 4236 cea_mode_for_vic(23)->vtotal != 312 || 4237 cea_mode_for_vic(24)->vtotal != 312 || 4238 cea_mode_for_vic(27)->vtotal != 312 || 4239 cea_mode_for_vic(28)->vtotal != 312); 4240 4241 if (((vic == 8 || vic == 9 || 4242 vic == 12 || vic == 13) && mode->vtotal < 263) || 4243 ((vic == 23 || vic == 24 || 4244 vic == 27 || vic == 28) && mode->vtotal < 314)) { 4245 mode->vsync_start++; 4246 mode->vsync_end++; 4247 mode->vtotal++; 4248 4249 return true; 4250 } 4251 4252 return false; 4253 } 4254 4255 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 4256 unsigned int clock_tolerance) 4257 { 4258 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4259 u8 vic; 4260 4261 if (!to_match->clock) 4262 return 0; 4263 4264 if (to_match->picture_aspect_ratio) 4265 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4266 4267 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 4268 struct drm_display_mode cea_mode; 4269 unsigned int clock1, clock2; 4270 4271 drm_mode_init(&cea_mode, cea_mode_for_vic(vic)); 4272 4273 /* Check both 60Hz and 59.94Hz */ 4274 clock1 = cea_mode.clock; 4275 clock2 = cea_mode_alternate_clock(&cea_mode); 4276 4277 if (abs(to_match->clock - clock1) > clock_tolerance && 4278 abs(to_match->clock - clock2) > clock_tolerance) 4279 continue; 4280 4281 do { 4282 if (drm_mode_match(to_match, &cea_mode, match_flags)) 4283 return vic; 4284 } while (cea_mode_alternate_timings(vic, &cea_mode)); 4285 } 4286 4287 return 0; 4288 } 4289 4290 /** 4291 * drm_match_cea_mode - look for a CEA mode matching given mode 4292 * @to_match: display mode 4293 * 4294 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 4295 * mode. 4296 */ 4297 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 4298 { 4299 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4300 u8 vic; 4301 4302 if (!to_match->clock) 4303 return 0; 4304 4305 if (to_match->picture_aspect_ratio) 4306 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4307 4308 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 4309 struct drm_display_mode cea_mode; 4310 unsigned int clock1, clock2; 4311 4312 drm_mode_init(&cea_mode, cea_mode_for_vic(vic)); 4313 4314 /* Check both 60Hz and 59.94Hz */ 4315 clock1 = cea_mode.clock; 4316 clock2 = cea_mode_alternate_clock(&cea_mode); 4317 4318 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 4319 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 4320 continue; 4321 4322 do { 4323 if (drm_mode_match(to_match, &cea_mode, match_flags)) 4324 return vic; 4325 } while (cea_mode_alternate_timings(vic, &cea_mode)); 4326 } 4327 4328 return 0; 4329 } 4330 EXPORT_SYMBOL(drm_match_cea_mode); 4331 4332 static bool drm_valid_cea_vic(u8 vic) 4333 { 4334 return cea_mode_for_vic(vic) != NULL; 4335 } 4336 4337 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 4338 { 4339 const struct drm_display_mode *mode = cea_mode_for_vic(video_code); 4340 4341 if (mode) 4342 return mode->picture_aspect_ratio; 4343 4344 return HDMI_PICTURE_ASPECT_NONE; 4345 } 4346 4347 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code) 4348 { 4349 return edid_4k_modes[video_code].picture_aspect_ratio; 4350 } 4351 4352 /* 4353 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 4354 * specific block). 4355 */ 4356 static unsigned int 4357 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 4358 { 4359 return cea_mode_alternate_clock(hdmi_mode); 4360 } 4361 4362 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 4363 unsigned int clock_tolerance) 4364 { 4365 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4366 u8 vic; 4367 4368 if (!to_match->clock) 4369 return 0; 4370 4371 if (to_match->picture_aspect_ratio) 4372 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4373 4374 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4375 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4376 unsigned int clock1, clock2; 4377 4378 /* Make sure to also match alternate clocks */ 4379 clock1 = hdmi_mode->clock; 4380 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4381 4382 if (abs(to_match->clock - clock1) > clock_tolerance && 4383 abs(to_match->clock - clock2) > clock_tolerance) 4384 continue; 4385 4386 if (drm_mode_match(to_match, hdmi_mode, match_flags)) 4387 return vic; 4388 } 4389 4390 return 0; 4391 } 4392 4393 /* 4394 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 4395 * @to_match: display mode 4396 * 4397 * An HDMI mode is one defined in the HDMI vendor specific block. 4398 * 4399 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 4400 */ 4401 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 4402 { 4403 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4404 u8 vic; 4405 4406 if (!to_match->clock) 4407 return 0; 4408 4409 if (to_match->picture_aspect_ratio) 4410 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4411 4412 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4413 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4414 unsigned int clock1, clock2; 4415 4416 /* Make sure to also match alternate clocks */ 4417 clock1 = hdmi_mode->clock; 4418 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4419 4420 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 4421 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 4422 drm_mode_match(to_match, hdmi_mode, match_flags)) 4423 return vic; 4424 } 4425 return 0; 4426 } 4427 4428 static bool drm_valid_hdmi_vic(u8 vic) 4429 { 4430 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 4431 } 4432 4433 static int add_alternate_cea_modes(struct drm_connector *connector, 4434 const struct drm_edid *drm_edid) 4435 { 4436 struct drm_device *dev = connector->dev; 4437 struct drm_display_mode *mode, *tmp; 4438 LIST_HEAD(list); 4439 int modes = 0; 4440 4441 /* Don't add CTA modes if the CTA extension block is missing */ 4442 if (!drm_edid_has_cta_extension(drm_edid)) 4443 return 0; 4444 4445 /* 4446 * Go through all probed modes and create a new mode 4447 * with the alternate clock for certain CEA modes. 4448 */ 4449 list_for_each_entry(mode, &connector->probed_modes, head) { 4450 const struct drm_display_mode *cea_mode = NULL; 4451 struct drm_display_mode *newmode; 4452 u8 vic = drm_match_cea_mode(mode); 4453 unsigned int clock1, clock2; 4454 4455 if (drm_valid_cea_vic(vic)) { 4456 cea_mode = cea_mode_for_vic(vic); 4457 clock2 = cea_mode_alternate_clock(cea_mode); 4458 } else { 4459 vic = drm_match_hdmi_mode(mode); 4460 if (drm_valid_hdmi_vic(vic)) { 4461 cea_mode = &edid_4k_modes[vic]; 4462 clock2 = hdmi_mode_alternate_clock(cea_mode); 4463 } 4464 } 4465 4466 if (!cea_mode) 4467 continue; 4468 4469 clock1 = cea_mode->clock; 4470 4471 if (clock1 == clock2) 4472 continue; 4473 4474 if (mode->clock != clock1 && mode->clock != clock2) 4475 continue; 4476 4477 newmode = drm_mode_duplicate(dev, cea_mode); 4478 if (!newmode) 4479 continue; 4480 4481 /* Carry over the stereo flags */ 4482 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 4483 4484 /* 4485 * The current mode could be either variant. Make 4486 * sure to pick the "other" clock for the new mode. 4487 */ 4488 if (mode->clock != clock1) 4489 newmode->clock = clock1; 4490 else 4491 newmode->clock = clock2; 4492 4493 list_add_tail(&newmode->head, &list); 4494 } 4495 4496 list_for_each_entry_safe(mode, tmp, &list, head) { 4497 list_del(&mode->head); 4498 drm_mode_probed_add(connector, mode); 4499 modes++; 4500 } 4501 4502 return modes; 4503 } 4504 4505 static u8 svd_to_vic(u8 svd) 4506 { 4507 /* 0-6 bit vic, 7th bit native mode indicator */ 4508 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 4509 return svd & 127; 4510 4511 return svd; 4512 } 4513 4514 /* 4515 * Return a display mode for the 0-based vic_index'th VIC across all CTA VDBs in 4516 * the EDID, or NULL on errors. 4517 */ 4518 static struct drm_display_mode * 4519 drm_display_mode_from_vic_index(struct drm_connector *connector, int vic_index) 4520 { 4521 const struct drm_display_info *info = &connector->display_info; 4522 struct drm_device *dev = connector->dev; 4523 4524 if (!info->vics || vic_index >= info->vics_len || !info->vics[vic_index]) 4525 return NULL; 4526 4527 return drm_display_mode_from_cea_vic(dev, info->vics[vic_index]); 4528 } 4529 4530 /* 4531 * do_y420vdb_modes - Parse YCBCR 420 only modes 4532 * @connector: connector corresponding to the HDMI sink 4533 * @svds: start of the data block of CEA YCBCR 420 VDB 4534 * @len: length of the CEA YCBCR 420 VDB 4535 * 4536 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 4537 * which contains modes which can be supported in YCBCR 420 4538 * output format only. 4539 */ 4540 static int do_y420vdb_modes(struct drm_connector *connector, 4541 const u8 *svds, u8 svds_len) 4542 { 4543 struct drm_device *dev = connector->dev; 4544 int modes = 0, i; 4545 4546 for (i = 0; i < svds_len; i++) { 4547 u8 vic = svd_to_vic(svds[i]); 4548 struct drm_display_mode *newmode; 4549 4550 if (!drm_valid_cea_vic(vic)) 4551 continue; 4552 4553 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 4554 if (!newmode) 4555 break; 4556 drm_mode_probed_add(connector, newmode); 4557 modes++; 4558 } 4559 4560 return modes; 4561 } 4562 4563 /** 4564 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC 4565 * @dev: DRM device 4566 * @video_code: CEA VIC of the mode 4567 * 4568 * Creates a new mode matching the specified CEA VIC. 4569 * 4570 * Returns: A new drm_display_mode on success or NULL on failure 4571 */ 4572 struct drm_display_mode * 4573 drm_display_mode_from_cea_vic(struct drm_device *dev, 4574 u8 video_code) 4575 { 4576 const struct drm_display_mode *cea_mode; 4577 struct drm_display_mode *newmode; 4578 4579 cea_mode = cea_mode_for_vic(video_code); 4580 if (!cea_mode) 4581 return NULL; 4582 4583 newmode = drm_mode_duplicate(dev, cea_mode); 4584 if (!newmode) 4585 return NULL; 4586 4587 return newmode; 4588 } 4589 EXPORT_SYMBOL(drm_display_mode_from_cea_vic); 4590 4591 /* Add modes based on VICs parsed in parse_cta_vdb() */ 4592 static int add_cta_vdb_modes(struct drm_connector *connector) 4593 { 4594 const struct drm_display_info *info = &connector->display_info; 4595 int i, modes = 0; 4596 4597 if (!info->vics) 4598 return 0; 4599 4600 for (i = 0; i < info->vics_len; i++) { 4601 struct drm_display_mode *mode; 4602 4603 mode = drm_display_mode_from_vic_index(connector, i); 4604 if (mode) { 4605 drm_mode_probed_add(connector, mode); 4606 modes++; 4607 } 4608 } 4609 4610 return modes; 4611 } 4612 4613 struct stereo_mandatory_mode { 4614 int width, height, vrefresh; 4615 unsigned int flags; 4616 }; 4617 4618 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 4619 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4620 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 4621 { 1920, 1080, 50, 4622 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 4623 { 1920, 1080, 60, 4624 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 4625 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4626 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 4627 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4628 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 4629 }; 4630 4631 static bool 4632 stereo_match_mandatory(const struct drm_display_mode *mode, 4633 const struct stereo_mandatory_mode *stereo_mode) 4634 { 4635 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 4636 4637 return mode->hdisplay == stereo_mode->width && 4638 mode->vdisplay == stereo_mode->height && 4639 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 4640 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 4641 } 4642 4643 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 4644 { 4645 struct drm_device *dev = connector->dev; 4646 const struct drm_display_mode *mode; 4647 struct list_head stereo_modes; 4648 int modes = 0, i; 4649 4650 INIT_LIST_HEAD(&stereo_modes); 4651 4652 list_for_each_entry(mode, &connector->probed_modes, head) { 4653 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 4654 const struct stereo_mandatory_mode *mandatory; 4655 struct drm_display_mode *new_mode; 4656 4657 if (!stereo_match_mandatory(mode, 4658 &stereo_mandatory_modes[i])) 4659 continue; 4660 4661 mandatory = &stereo_mandatory_modes[i]; 4662 new_mode = drm_mode_duplicate(dev, mode); 4663 if (!new_mode) 4664 continue; 4665 4666 new_mode->flags |= mandatory->flags; 4667 list_add_tail(&new_mode->head, &stereo_modes); 4668 modes++; 4669 } 4670 } 4671 4672 list_splice_tail(&stereo_modes, &connector->probed_modes); 4673 4674 return modes; 4675 } 4676 4677 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 4678 { 4679 struct drm_device *dev = connector->dev; 4680 struct drm_display_mode *newmode; 4681 4682 if (!drm_valid_hdmi_vic(vic)) { 4683 drm_err(connector->dev, "[CONNECTOR:%d:%s] Unknown HDMI VIC: %d\n", 4684 connector->base.id, connector->name, vic); 4685 return 0; 4686 } 4687 4688 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 4689 if (!newmode) 4690 return 0; 4691 4692 drm_mode_probed_add(connector, newmode); 4693 4694 return 1; 4695 } 4696 4697 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 4698 int vic_index) 4699 { 4700 struct drm_display_mode *newmode; 4701 int modes = 0; 4702 4703 if (structure & (1 << 0)) { 4704 newmode = drm_display_mode_from_vic_index(connector, vic_index); 4705 if (newmode) { 4706 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 4707 drm_mode_probed_add(connector, newmode); 4708 modes++; 4709 } 4710 } 4711 if (structure & (1 << 6)) { 4712 newmode = drm_display_mode_from_vic_index(connector, vic_index); 4713 if (newmode) { 4714 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 4715 drm_mode_probed_add(connector, newmode); 4716 modes++; 4717 } 4718 } 4719 if (structure & (1 << 8)) { 4720 newmode = drm_display_mode_from_vic_index(connector, vic_index); 4721 if (newmode) { 4722 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4723 drm_mode_probed_add(connector, newmode); 4724 modes++; 4725 } 4726 } 4727 4728 return modes; 4729 } 4730 4731 static bool hdmi_vsdb_latency_present(const u8 *db) 4732 { 4733 return db[8] & BIT(7); 4734 } 4735 4736 static bool hdmi_vsdb_i_latency_present(const u8 *db) 4737 { 4738 return hdmi_vsdb_latency_present(db) && db[8] & BIT(6); 4739 } 4740 4741 static int hdmi_vsdb_latency_length(const u8 *db) 4742 { 4743 if (hdmi_vsdb_i_latency_present(db)) 4744 return 4; 4745 else if (hdmi_vsdb_latency_present(db)) 4746 return 2; 4747 else 4748 return 0; 4749 } 4750 4751 /* 4752 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 4753 * @connector: connector corresponding to the HDMI sink 4754 * @db: start of the CEA vendor specific block 4755 * @len: length of the CEA block payload, ie. one can access up to db[len] 4756 * 4757 * Parses the HDMI VSDB looking for modes to add to @connector. This function 4758 * also adds the stereo 3d modes when applicable. 4759 */ 4760 static int 4761 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len) 4762 { 4763 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 4764 u8 vic_len, hdmi_3d_len = 0; 4765 u16 mask; 4766 u16 structure_all; 4767 4768 if (len < 8) 4769 goto out; 4770 4771 /* no HDMI_Video_Present */ 4772 if (!(db[8] & (1 << 5))) 4773 goto out; 4774 4775 offset += hdmi_vsdb_latency_length(db); 4776 4777 /* the declared length is not long enough for the 2 first bytes 4778 * of additional video format capabilities */ 4779 if (len < (8 + offset + 2)) 4780 goto out; 4781 4782 /* 3D_Present */ 4783 offset++; 4784 if (db[8 + offset] & (1 << 7)) { 4785 modes += add_hdmi_mandatory_stereo_modes(connector); 4786 4787 /* 3D_Multi_present */ 4788 multi_present = (db[8 + offset] & 0x60) >> 5; 4789 } 4790 4791 offset++; 4792 vic_len = db[8 + offset] >> 5; 4793 hdmi_3d_len = db[8 + offset] & 0x1f; 4794 4795 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 4796 u8 vic; 4797 4798 vic = db[9 + offset + i]; 4799 modes += add_hdmi_mode(connector, vic); 4800 } 4801 offset += 1 + vic_len; 4802 4803 if (multi_present == 1) 4804 multi_len = 2; 4805 else if (multi_present == 2) 4806 multi_len = 4; 4807 else 4808 multi_len = 0; 4809 4810 if (len < (8 + offset + hdmi_3d_len - 1)) 4811 goto out; 4812 4813 if (hdmi_3d_len < multi_len) 4814 goto out; 4815 4816 if (multi_present == 1 || multi_present == 2) { 4817 /* 3D_Structure_ALL */ 4818 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 4819 4820 /* check if 3D_MASK is present */ 4821 if (multi_present == 2) 4822 mask = (db[10 + offset] << 8) | db[11 + offset]; 4823 else 4824 mask = 0xffff; 4825 4826 for (i = 0; i < 16; i++) { 4827 if (mask & (1 << i)) 4828 modes += add_3d_struct_modes(connector, 4829 structure_all, i); 4830 } 4831 } 4832 4833 offset += multi_len; 4834 4835 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 4836 int vic_index; 4837 struct drm_display_mode *newmode = NULL; 4838 unsigned int newflag = 0; 4839 bool detail_present; 4840 4841 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 4842 4843 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 4844 break; 4845 4846 /* 2D_VIC_order_X */ 4847 vic_index = db[8 + offset + i] >> 4; 4848 4849 /* 3D_Structure_X */ 4850 switch (db[8 + offset + i] & 0x0f) { 4851 case 0: 4852 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 4853 break; 4854 case 6: 4855 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 4856 break; 4857 case 8: 4858 /* 3D_Detail_X */ 4859 if ((db[9 + offset + i] >> 4) == 1) 4860 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4861 break; 4862 } 4863 4864 if (newflag != 0) { 4865 newmode = drm_display_mode_from_vic_index(connector, 4866 vic_index); 4867 4868 if (newmode) { 4869 newmode->flags |= newflag; 4870 drm_mode_probed_add(connector, newmode); 4871 modes++; 4872 } 4873 } 4874 4875 if (detail_present) 4876 i++; 4877 } 4878 4879 out: 4880 return modes; 4881 } 4882 4883 static int 4884 cea_revision(const u8 *cea) 4885 { 4886 /* 4887 * FIXME is this correct for the DispID variant? 4888 * The DispID spec doesn't really specify whether 4889 * this is the revision of the CEA extension or 4890 * the DispID CEA data block. And the only value 4891 * given as an example is 0. 4892 */ 4893 return cea[1]; 4894 } 4895 4896 /* 4897 * CTA Data Block iterator. 4898 * 4899 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID 4900 * CTA Data Blocks. 4901 * 4902 * struct cea_db *db: 4903 * struct cea_db_iter iter; 4904 * 4905 * cea_db_iter_edid_begin(edid, &iter); 4906 * cea_db_iter_for_each(db, &iter) { 4907 * // do stuff with db 4908 * } 4909 * cea_db_iter_end(&iter); 4910 */ 4911 struct cea_db_iter { 4912 struct drm_edid_iter edid_iter; 4913 struct displayid_iter displayid_iter; 4914 4915 /* Current Data Block Collection. */ 4916 const u8 *collection; 4917 4918 /* Current Data Block index in current collection. */ 4919 int index; 4920 4921 /* End index in current collection. */ 4922 int end; 4923 }; 4924 4925 /* CTA-861-H section 7.4 CTA Data BLock Collection */ 4926 struct cea_db { 4927 u8 tag_length; 4928 u8 data[]; 4929 } __packed; 4930 4931 static int cea_db_tag(const struct cea_db *db) 4932 { 4933 return db->tag_length >> 5; 4934 } 4935 4936 static int cea_db_payload_len(const void *_db) 4937 { 4938 /* FIXME: Transition to passing struct cea_db * everywhere. */ 4939 const struct cea_db *db = _db; 4940 4941 return db->tag_length & 0x1f; 4942 } 4943 4944 static const void *cea_db_data(const struct cea_db *db) 4945 { 4946 return db->data; 4947 } 4948 4949 static bool cea_db_is_extended_tag(const struct cea_db *db, int tag) 4950 { 4951 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG && 4952 cea_db_payload_len(db) >= 1 && 4953 db->data[0] == tag; 4954 } 4955 4956 static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui) 4957 { 4958 const u8 *data = cea_db_data(db); 4959 4960 return cea_db_tag(db) == CTA_DB_VENDOR && 4961 cea_db_payload_len(db) >= 3 && 4962 oui(data[2], data[1], data[0]) == vendor_oui; 4963 } 4964 4965 static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid, 4966 struct cea_db_iter *iter) 4967 { 4968 memset(iter, 0, sizeof(*iter)); 4969 4970 drm_edid_iter_begin(drm_edid, &iter->edid_iter); 4971 displayid_iter_edid_begin(drm_edid, &iter->displayid_iter); 4972 } 4973 4974 static const struct cea_db * 4975 __cea_db_iter_current_block(const struct cea_db_iter *iter) 4976 { 4977 const struct cea_db *db; 4978 4979 if (!iter->collection) 4980 return NULL; 4981 4982 db = (const struct cea_db *)&iter->collection[iter->index]; 4983 4984 if (iter->index + sizeof(*db) <= iter->end && 4985 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end) 4986 return db; 4987 4988 return NULL; 4989 } 4990 4991 /* 4992 * References: 4993 * - CTA-861-H section 7.3.3 CTA Extension Version 3 4994 */ 4995 static int cea_db_collection_size(const u8 *cta) 4996 { 4997 u8 d = cta[2]; 4998 4999 if (d < 4 || d > 127) 5000 return 0; 5001 5002 return d - 4; 5003 } 5004 5005 /* 5006 * References: 5007 * - VESA E-EDID v1.4 5008 * - CTA-861-H section 7.3.3 CTA Extension Version 3 5009 */ 5010 static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter) 5011 { 5012 const u8 *ext; 5013 5014 drm_edid_iter_for_each(ext, &iter->edid_iter) { 5015 int size; 5016 5017 /* Only support CTA Extension revision 3+ */ 5018 if (ext[0] != CEA_EXT || cea_revision(ext) < 3) 5019 continue; 5020 5021 size = cea_db_collection_size(ext); 5022 if (!size) 5023 continue; 5024 5025 iter->index = 4; 5026 iter->end = iter->index + size; 5027 5028 return ext; 5029 } 5030 5031 return NULL; 5032 } 5033 5034 /* 5035 * References: 5036 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block 5037 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block 5038 * 5039 * Note that the above do not specify any connection between DisplayID Data 5040 * Block revision and CTA Extension versions. 5041 */ 5042 static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter) 5043 { 5044 const struct displayid_block *block; 5045 5046 displayid_iter_for_each(block, &iter->displayid_iter) { 5047 if (block->tag != DATA_BLOCK_CTA) 5048 continue; 5049 5050 /* 5051 * The displayid iterator has already verified the block bounds 5052 * in displayid_iter_block(). 5053 */ 5054 iter->index = sizeof(*block); 5055 iter->end = iter->index + block->num_bytes; 5056 5057 return block; 5058 } 5059 5060 return NULL; 5061 } 5062 5063 static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter) 5064 { 5065 const struct cea_db *db; 5066 5067 if (iter->collection) { 5068 /* Current collection should always be valid. */ 5069 db = __cea_db_iter_current_block(iter); 5070 if (WARN_ON(!db)) { 5071 iter->collection = NULL; 5072 return NULL; 5073 } 5074 5075 /* Next block in CTA Data Block Collection */ 5076 iter->index += sizeof(*db) + cea_db_payload_len(db); 5077 5078 db = __cea_db_iter_current_block(iter); 5079 if (db) 5080 return db; 5081 } 5082 5083 for (;;) { 5084 /* 5085 * Find the next CTA Data Block Collection. First iterate all 5086 * the EDID CTA Extensions, then all the DisplayID CTA blocks. 5087 * 5088 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID 5089 * Extension, it's recommended that DisplayID extensions are 5090 * exposed after all of the CTA Extensions. 5091 */ 5092 iter->collection = __cea_db_iter_edid_next(iter); 5093 if (!iter->collection) 5094 iter->collection = __cea_db_iter_displayid_next(iter); 5095 5096 if (!iter->collection) 5097 return NULL; 5098 5099 db = __cea_db_iter_current_block(iter); 5100 if (db) 5101 return db; 5102 } 5103 } 5104 5105 #define cea_db_iter_for_each(__db, __iter) \ 5106 while (((__db) = __cea_db_iter_next(__iter))) 5107 5108 static void cea_db_iter_end(struct cea_db_iter *iter) 5109 { 5110 displayid_iter_end(&iter->displayid_iter); 5111 drm_edid_iter_end(&iter->edid_iter); 5112 5113 memset(iter, 0, sizeof(*iter)); 5114 } 5115 5116 static bool cea_db_is_hdmi_vsdb(const struct cea_db *db) 5117 { 5118 return cea_db_is_vendor(db, HDMI_IEEE_OUI) && 5119 cea_db_payload_len(db) >= 5; 5120 } 5121 5122 static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db) 5123 { 5124 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) && 5125 cea_db_payload_len(db) >= 7; 5126 } 5127 5128 static bool cea_db_is_hdmi_forum_eeodb(const void *db) 5129 { 5130 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) && 5131 cea_db_payload_len(db) >= 2; 5132 } 5133 5134 static bool cea_db_is_microsoft_vsdb(const struct cea_db *db) 5135 { 5136 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) && 5137 cea_db_payload_len(db) == 21; 5138 } 5139 5140 static bool cea_db_is_vcdb(const struct cea_db *db) 5141 { 5142 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) && 5143 cea_db_payload_len(db) == 2; 5144 } 5145 5146 static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db) 5147 { 5148 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) && 5149 cea_db_payload_len(db) >= 7; 5150 } 5151 5152 static bool cea_db_is_y420cmdb(const struct cea_db *db) 5153 { 5154 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP); 5155 } 5156 5157 static bool cea_db_is_y420vdb(const struct cea_db *db) 5158 { 5159 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA); 5160 } 5161 5162 static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db) 5163 { 5164 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) && 5165 cea_db_payload_len(db) >= 3; 5166 } 5167 5168 /* 5169 * Get the HF-EEODB override extension block count from EDID. 5170 * 5171 * The passed in EDID may be partially read, as long as it has at least two 5172 * blocks (base block and one extension block) if EDID extension count is > 0. 5173 * 5174 * Note that this is *not* how you should parse CTA Data Blocks in general; this 5175 * is only to handle partially read EDIDs. Normally, use the CTA Data Block 5176 * iterators instead. 5177 * 5178 * References: 5179 * - HDMI 2.1 section 10.3.6 HDMI Forum EDID Extension Override Data Block 5180 */ 5181 static int edid_hfeeodb_extension_block_count(const struct edid *edid) 5182 { 5183 const u8 *cta; 5184 5185 /* No extensions according to base block, no HF-EEODB. */ 5186 if (!edid_extension_block_count(edid)) 5187 return 0; 5188 5189 /* HF-EEODB is always in the first EDID extension block only */ 5190 cta = edid_extension_block_data(edid, 0); 5191 if (edid_block_tag(cta) != CEA_EXT || cea_revision(cta) < 3) 5192 return 0; 5193 5194 /* Need to have the data block collection, and at least 3 bytes. */ 5195 if (cea_db_collection_size(cta) < 3) 5196 return 0; 5197 5198 /* 5199 * Sinks that include the HF-EEODB in their E-EDID shall include one and 5200 * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4 5201 * through 6 of Block 1 of the E-EDID. 5202 */ 5203 if (!cea_db_is_hdmi_forum_eeodb(&cta[4])) 5204 return 0; 5205 5206 return cta[4 + 2]; 5207 } 5208 5209 /* 5210 * CTA-861 YCbCr 4:2:0 Capability Map Data Block (CTA Y420CMDB) 5211 * 5212 * Y420CMDB contains a bitmap which gives the index of CTA modes from CTA VDB, 5213 * which can support YCBCR 420 sampling output also (apart from RGB/YCBCR444 5214 * etc). For example, if the bit 0 in bitmap is set, first mode in VDB can 5215 * support YCBCR420 output too. 5216 */ 5217 static void parse_cta_y420cmdb(struct drm_connector *connector, 5218 const struct cea_db *db, u64 *y420cmdb_map) 5219 { 5220 struct drm_display_info *info = &connector->display_info; 5221 int i, map_len = cea_db_payload_len(db) - 1; 5222 const u8 *data = cea_db_data(db) + 1; 5223 u64 map = 0; 5224 5225 if (map_len == 0) { 5226 /* All CEA modes support ycbcr420 sampling also.*/ 5227 map = U64_MAX; 5228 goto out; 5229 } 5230 5231 /* 5232 * This map indicates which of the existing CEA block modes 5233 * from VDB can support YCBCR420 output too. So if bit=0 is 5234 * set, first mode from VDB can support YCBCR420 output too. 5235 * We will parse and keep this map, before parsing VDB itself 5236 * to avoid going through the same block again and again. 5237 * 5238 * Spec is not clear about max possible size of this block. 5239 * Clamping max bitmap block size at 8 bytes. Every byte can 5240 * address 8 CEA modes, in this way this map can address 5241 * 8*8 = first 64 SVDs. 5242 */ 5243 if (WARN_ON_ONCE(map_len > 8)) 5244 map_len = 8; 5245 5246 for (i = 0; i < map_len; i++) 5247 map |= (u64)data[i] << (8 * i); 5248 5249 out: 5250 if (map) 5251 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; 5252 5253 *y420cmdb_map = map; 5254 } 5255 5256 static int add_cea_modes(struct drm_connector *connector, 5257 const struct drm_edid *drm_edid) 5258 { 5259 const struct cea_db *db; 5260 struct cea_db_iter iter; 5261 int modes; 5262 5263 /* CTA VDB block VICs parsed earlier */ 5264 modes = add_cta_vdb_modes(connector); 5265 5266 cea_db_iter_edid_begin(drm_edid, &iter); 5267 cea_db_iter_for_each(db, &iter) { 5268 if (cea_db_is_hdmi_vsdb(db)) { 5269 modes += do_hdmi_vsdb_modes(connector, (const u8 *)db, 5270 cea_db_payload_len(db)); 5271 } else if (cea_db_is_y420vdb(db)) { 5272 const u8 *vdb420 = cea_db_data(db) + 1; 5273 5274 /* Add 4:2:0(only) modes present in EDID */ 5275 modes += do_y420vdb_modes(connector, vdb420, 5276 cea_db_payload_len(db) - 1); 5277 } 5278 } 5279 cea_db_iter_end(&iter); 5280 5281 return modes; 5282 } 5283 5284 static void fixup_detailed_cea_mode_clock(struct drm_connector *connector, 5285 struct drm_display_mode *mode) 5286 { 5287 const struct drm_display_mode *cea_mode; 5288 int clock1, clock2, clock; 5289 u8 vic; 5290 const char *type; 5291 5292 /* 5293 * allow 5kHz clock difference either way to account for 5294 * the 10kHz clock resolution limit of detailed timings. 5295 */ 5296 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 5297 if (drm_valid_cea_vic(vic)) { 5298 type = "CEA"; 5299 cea_mode = cea_mode_for_vic(vic); 5300 clock1 = cea_mode->clock; 5301 clock2 = cea_mode_alternate_clock(cea_mode); 5302 } else { 5303 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 5304 if (drm_valid_hdmi_vic(vic)) { 5305 type = "HDMI"; 5306 cea_mode = &edid_4k_modes[vic]; 5307 clock1 = cea_mode->clock; 5308 clock2 = hdmi_mode_alternate_clock(cea_mode); 5309 } else { 5310 return; 5311 } 5312 } 5313 5314 /* pick whichever is closest */ 5315 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 5316 clock = clock1; 5317 else 5318 clock = clock2; 5319 5320 if (mode->clock == clock) 5321 return; 5322 5323 drm_dbg_kms(connector->dev, 5324 "[CONNECTOR:%d:%s] detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 5325 connector->base.id, connector->name, 5326 type, vic, mode->clock, clock); 5327 mode->clock = clock; 5328 } 5329 5330 static void drm_calculate_luminance_range(struct drm_connector *connector) 5331 { 5332 struct hdr_static_metadata *hdr_metadata = &connector->hdr_sink_metadata.hdmi_type1; 5333 struct drm_luminance_range_info *luminance_range = 5334 &connector->display_info.luminance_range; 5335 static const u8 pre_computed_values[] = { 5336 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69, 5337 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98 5338 }; 5339 u32 max_avg, min_cll, max, min, q, r; 5340 5341 if (!(hdr_metadata->metadata_type & BIT(HDMI_STATIC_METADATA_TYPE1))) 5342 return; 5343 5344 max_avg = hdr_metadata->max_fall; 5345 min_cll = hdr_metadata->min_cll; 5346 5347 /* 5348 * From the specification (CTA-861-G), for calculating the maximum 5349 * luminance we need to use: 5350 * Luminance = 50*2**(CV/32) 5351 * Where CV is a one-byte value. 5352 * For calculating this expression we may need float point precision; 5353 * to avoid this complexity level, we take advantage that CV is divided 5354 * by a constant. From the Euclids division algorithm, we know that CV 5355 * can be written as: CV = 32*q + r. Next, we replace CV in the 5356 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just 5357 * need to pre-compute the value of r/32. For pre-computing the values 5358 * We just used the following Ruby line: 5359 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round} 5360 * The results of the above expressions can be verified at 5361 * pre_computed_values. 5362 */ 5363 q = max_avg >> 5; 5364 r = max_avg % 32; 5365 max = (1 << q) * pre_computed_values[r]; 5366 5367 /* min luminance: maxLum * (CV/255)^2 / 100 */ 5368 q = DIV_ROUND_CLOSEST(min_cll, 255); 5369 min = max * DIV_ROUND_CLOSEST((q * q), 100); 5370 5371 luminance_range->min_luminance = min; 5372 luminance_range->max_luminance = max; 5373 } 5374 5375 static uint8_t eotf_supported(const u8 *edid_ext) 5376 { 5377 return edid_ext[2] & 5378 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) | 5379 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) | 5380 BIT(HDMI_EOTF_SMPTE_ST2084) | 5381 BIT(HDMI_EOTF_BT_2100_HLG)); 5382 } 5383 5384 static uint8_t hdr_metadata_type(const u8 *edid_ext) 5385 { 5386 return edid_ext[3] & 5387 BIT(HDMI_STATIC_METADATA_TYPE1); 5388 } 5389 5390 static void 5391 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db) 5392 { 5393 u16 len; 5394 5395 len = cea_db_payload_len(db); 5396 5397 connector->hdr_sink_metadata.hdmi_type1.eotf = 5398 eotf_supported(db); 5399 connector->hdr_sink_metadata.hdmi_type1.metadata_type = 5400 hdr_metadata_type(db); 5401 5402 if (len >= 4) 5403 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4]; 5404 if (len >= 5) 5405 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5]; 5406 if (len >= 6) { 5407 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6]; 5408 5409 /* Calculate only when all values are available */ 5410 drm_calculate_luminance_range(connector); 5411 } 5412 } 5413 5414 /* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */ 5415 static void 5416 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 5417 { 5418 u8 len = cea_db_payload_len(db); 5419 5420 if (len >= 6 && (db[6] & (1 << 7))) 5421 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI; 5422 5423 if (len >= 10 && hdmi_vsdb_latency_present(db)) { 5424 connector->latency_present[0] = true; 5425 connector->video_latency[0] = db[9]; 5426 connector->audio_latency[0] = db[10]; 5427 } 5428 5429 if (len >= 12 && hdmi_vsdb_i_latency_present(db)) { 5430 connector->latency_present[1] = true; 5431 connector->video_latency[1] = db[11]; 5432 connector->audio_latency[1] = db[12]; 5433 } 5434 5435 drm_dbg_kms(connector->dev, 5436 "[CONNECTOR:%d:%s] HDMI: latency present %d %d, video latency %d %d, audio latency %d %d\n", 5437 connector->base.id, connector->name, 5438 connector->latency_present[0], connector->latency_present[1], 5439 connector->video_latency[0], connector->video_latency[1], 5440 connector->audio_latency[0], connector->audio_latency[1]); 5441 } 5442 5443 static void 5444 monitor_name(const struct detailed_timing *timing, void *data) 5445 { 5446 const char **res = data; 5447 5448 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME)) 5449 return; 5450 5451 *res = timing->data.other_data.data.str.str; 5452 } 5453 5454 static int get_monitor_name(const struct drm_edid *drm_edid, char name[13]) 5455 { 5456 const char *edid_name = NULL; 5457 int mnl; 5458 5459 if (!drm_edid || !name) 5460 return 0; 5461 5462 drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name); 5463 for (mnl = 0; edid_name && mnl < 13; mnl++) { 5464 if (edid_name[mnl] == 0x0a) 5465 break; 5466 5467 name[mnl] = edid_name[mnl]; 5468 } 5469 5470 return mnl; 5471 } 5472 5473 /** 5474 * drm_edid_get_monitor_name - fetch the monitor name from the edid 5475 * @edid: monitor EDID information 5476 * @name: pointer to a character array to hold the name of the monitor 5477 * @bufsize: The size of the name buffer (should be at least 14 chars.) 5478 * 5479 */ 5480 void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize) 5481 { 5482 int name_length = 0; 5483 5484 if (bufsize <= 0) 5485 return; 5486 5487 if (edid) { 5488 char buf[13]; 5489 struct drm_edid drm_edid = { 5490 .edid = edid, 5491 .size = edid_size(edid), 5492 }; 5493 5494 name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1); 5495 memcpy(name, buf, name_length); 5496 } 5497 5498 name[name_length] = '\0'; 5499 } 5500 EXPORT_SYMBOL(drm_edid_get_monitor_name); 5501 5502 static void clear_eld(struct drm_connector *connector) 5503 { 5504 memset(connector->eld, 0, sizeof(connector->eld)); 5505 5506 connector->latency_present[0] = false; 5507 connector->latency_present[1] = false; 5508 connector->video_latency[0] = 0; 5509 connector->audio_latency[0] = 0; 5510 connector->video_latency[1] = 0; 5511 connector->audio_latency[1] = 0; 5512 } 5513 5514 /* 5515 * Get 3-byte SAD buffer from struct cea_sad. 5516 */ 5517 void drm_edid_cta_sad_get(const struct cea_sad *cta_sad, u8 *sad) 5518 { 5519 sad[0] = cta_sad->format << 3 | cta_sad->channels; 5520 sad[1] = cta_sad->freq; 5521 sad[2] = cta_sad->byte2; 5522 } 5523 5524 /* 5525 * Set struct cea_sad from 3-byte SAD buffer. 5526 */ 5527 void drm_edid_cta_sad_set(struct cea_sad *cta_sad, const u8 *sad) 5528 { 5529 cta_sad->format = (sad[0] & 0x78) >> 3; 5530 cta_sad->channels = sad[0] & 0x07; 5531 cta_sad->freq = sad[1] & 0x7f; 5532 cta_sad->byte2 = sad[2]; 5533 } 5534 5535 /* 5536 * drm_edid_to_eld - build ELD from EDID 5537 * @connector: connector corresponding to the HDMI/DP sink 5538 * @drm_edid: EDID to parse 5539 * 5540 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 5541 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 5542 */ 5543 static void drm_edid_to_eld(struct drm_connector *connector, 5544 const struct drm_edid *drm_edid) 5545 { 5546 const struct drm_display_info *info = &connector->display_info; 5547 const struct cea_db *db; 5548 struct cea_db_iter iter; 5549 uint8_t *eld = connector->eld; 5550 int total_sad_count = 0; 5551 int mnl; 5552 5553 if (!drm_edid) 5554 return; 5555 5556 mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]); 5557 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD monitor %s\n", 5558 connector->base.id, connector->name, 5559 &eld[DRM_ELD_MONITOR_NAME_STRING]); 5560 5561 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT; 5562 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl; 5563 5564 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D; 5565 5566 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0]; 5567 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1]; 5568 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0]; 5569 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1]; 5570 5571 cea_db_iter_edid_begin(drm_edid, &iter); 5572 cea_db_iter_for_each(db, &iter) { 5573 const u8 *data = cea_db_data(db); 5574 int len = cea_db_payload_len(db); 5575 int sad_count; 5576 5577 switch (cea_db_tag(db)) { 5578 case CTA_DB_AUDIO: 5579 /* Audio Data Block, contains SADs */ 5580 sad_count = min(len / 3, 15 - total_sad_count); 5581 if (sad_count >= 1) 5582 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)], 5583 data, sad_count * 3); 5584 total_sad_count += sad_count; 5585 break; 5586 case CTA_DB_SPEAKER: 5587 /* Speaker Allocation Data Block */ 5588 if (len >= 1) 5589 eld[DRM_ELD_SPEAKER] = data[0]; 5590 break; 5591 case CTA_DB_VENDOR: 5592 /* HDMI Vendor-Specific Data Block */ 5593 if (cea_db_is_hdmi_vsdb(db)) 5594 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db); 5595 break; 5596 default: 5597 break; 5598 } 5599 } 5600 cea_db_iter_end(&iter); 5601 5602 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT; 5603 5604 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 5605 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 5606 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 5607 else 5608 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 5609 5610 eld[DRM_ELD_BASELINE_ELD_LEN] = 5611 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 5612 5613 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD size %d, SAD count %d\n", 5614 connector->base.id, connector->name, 5615 drm_eld_size(eld), total_sad_count); 5616 } 5617 5618 static int _drm_edid_to_sad(const struct drm_edid *drm_edid, 5619 struct cea_sad **psads) 5620 { 5621 const struct cea_db *db; 5622 struct cea_db_iter iter; 5623 int count = 0; 5624 5625 cea_db_iter_edid_begin(drm_edid, &iter); 5626 cea_db_iter_for_each(db, &iter) { 5627 if (cea_db_tag(db) == CTA_DB_AUDIO) { 5628 struct cea_sad *sads; 5629 int i; 5630 5631 count = cea_db_payload_len(db) / 3; /* SAD is 3B */ 5632 sads = kcalloc(count, sizeof(*sads), GFP_KERNEL); 5633 *psads = sads; 5634 if (!sads) 5635 return -ENOMEM; 5636 for (i = 0; i < count; i++) 5637 drm_edid_cta_sad_set(&sads[i], &db->data[i * 3]); 5638 break; 5639 } 5640 } 5641 cea_db_iter_end(&iter); 5642 5643 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count); 5644 5645 return count; 5646 } 5647 5648 /** 5649 * drm_edid_to_sad - extracts SADs from EDID 5650 * @edid: EDID to parse 5651 * @sads: pointer that will be set to the extracted SADs 5652 * 5653 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 5654 * 5655 * Note: The returned pointer needs to be freed using kfree(). 5656 * 5657 * Return: The number of found SADs or negative number on error. 5658 */ 5659 int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads) 5660 { 5661 struct drm_edid drm_edid; 5662 5663 return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads); 5664 } 5665 EXPORT_SYMBOL(drm_edid_to_sad); 5666 5667 static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid, 5668 u8 **sadb) 5669 { 5670 const struct cea_db *db; 5671 struct cea_db_iter iter; 5672 int count = 0; 5673 5674 cea_db_iter_edid_begin(drm_edid, &iter); 5675 cea_db_iter_for_each(db, &iter) { 5676 if (cea_db_tag(db) == CTA_DB_SPEAKER && 5677 cea_db_payload_len(db) == 3) { 5678 *sadb = kmemdup(db->data, cea_db_payload_len(db), 5679 GFP_KERNEL); 5680 if (!*sadb) 5681 return -ENOMEM; 5682 count = cea_db_payload_len(db); 5683 break; 5684 } 5685 } 5686 cea_db_iter_end(&iter); 5687 5688 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count); 5689 5690 return count; 5691 } 5692 5693 /** 5694 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 5695 * @edid: EDID to parse 5696 * @sadb: pointer to the speaker block 5697 * 5698 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 5699 * 5700 * Note: The returned pointer needs to be freed using kfree(). 5701 * 5702 * Return: The number of found Speaker Allocation Blocks or negative number on 5703 * error. 5704 */ 5705 int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb) 5706 { 5707 struct drm_edid drm_edid; 5708 5709 return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid), 5710 sadb); 5711 } 5712 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 5713 5714 /** 5715 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 5716 * @connector: connector associated with the HDMI/DP sink 5717 * @mode: the display mode 5718 * 5719 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 5720 * the sink doesn't support audio or video. 5721 */ 5722 int drm_av_sync_delay(struct drm_connector *connector, 5723 const struct drm_display_mode *mode) 5724 { 5725 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 5726 int a, v; 5727 5728 if (!connector->latency_present[0]) 5729 return 0; 5730 if (!connector->latency_present[1]) 5731 i = 0; 5732 5733 a = connector->audio_latency[i]; 5734 v = connector->video_latency[i]; 5735 5736 /* 5737 * HDMI/DP sink doesn't support audio or video? 5738 */ 5739 if (a == 255 || v == 255) 5740 return 0; 5741 5742 /* 5743 * Convert raw EDID values to millisecond. 5744 * Treat unknown latency as 0ms. 5745 */ 5746 if (a) 5747 a = min(2 * (a - 1), 500); 5748 if (v) 5749 v = min(2 * (v - 1), 500); 5750 5751 return max(v - a, 0); 5752 } 5753 EXPORT_SYMBOL(drm_av_sync_delay); 5754 5755 static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid) 5756 { 5757 const struct cea_db *db; 5758 struct cea_db_iter iter; 5759 bool hdmi = false; 5760 5761 /* 5762 * Because HDMI identifier is in Vendor Specific Block, 5763 * search it from all data blocks of CEA extension. 5764 */ 5765 cea_db_iter_edid_begin(drm_edid, &iter); 5766 cea_db_iter_for_each(db, &iter) { 5767 if (cea_db_is_hdmi_vsdb(db)) { 5768 hdmi = true; 5769 break; 5770 } 5771 } 5772 cea_db_iter_end(&iter); 5773 5774 return hdmi; 5775 } 5776 5777 /** 5778 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 5779 * @edid: monitor EDID information 5780 * 5781 * Parse the CEA extension according to CEA-861-B. 5782 * 5783 * Drivers that have added the modes parsed from EDID to drm_display_info 5784 * should use &drm_display_info.is_hdmi instead of calling this function. 5785 * 5786 * Return: True if the monitor is HDMI, false if not or unknown. 5787 */ 5788 bool drm_detect_hdmi_monitor(const struct edid *edid) 5789 { 5790 struct drm_edid drm_edid; 5791 5792 return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid)); 5793 } 5794 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 5795 5796 static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid) 5797 { 5798 struct drm_edid_iter edid_iter; 5799 const struct cea_db *db; 5800 struct cea_db_iter iter; 5801 const u8 *edid_ext; 5802 bool has_audio = false; 5803 5804 drm_edid_iter_begin(drm_edid, &edid_iter); 5805 drm_edid_iter_for_each(edid_ext, &edid_iter) { 5806 if (edid_ext[0] == CEA_EXT) { 5807 has_audio = edid_ext[3] & EDID_BASIC_AUDIO; 5808 if (has_audio) 5809 break; 5810 } 5811 } 5812 drm_edid_iter_end(&edid_iter); 5813 5814 if (has_audio) { 5815 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 5816 goto end; 5817 } 5818 5819 cea_db_iter_edid_begin(drm_edid, &iter); 5820 cea_db_iter_for_each(db, &iter) { 5821 if (cea_db_tag(db) == CTA_DB_AUDIO) { 5822 const u8 *data = cea_db_data(db); 5823 int i; 5824 5825 for (i = 0; i < cea_db_payload_len(db); i += 3) 5826 DRM_DEBUG_KMS("CEA audio format %d\n", 5827 (data[i] >> 3) & 0xf); 5828 has_audio = true; 5829 break; 5830 } 5831 } 5832 cea_db_iter_end(&iter); 5833 5834 end: 5835 return has_audio; 5836 } 5837 5838 /** 5839 * drm_detect_monitor_audio - check monitor audio capability 5840 * @edid: EDID block to scan 5841 * 5842 * Monitor should have CEA extension block. 5843 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 5844 * audio' only. If there is any audio extension block and supported 5845 * audio format, assume at least 'basic audio' support, even if 'basic 5846 * audio' is not defined in EDID. 5847 * 5848 * Return: True if the monitor supports audio, false otherwise. 5849 */ 5850 bool drm_detect_monitor_audio(const struct edid *edid) 5851 { 5852 struct drm_edid drm_edid; 5853 5854 return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid)); 5855 } 5856 EXPORT_SYMBOL(drm_detect_monitor_audio); 5857 5858 5859 /** 5860 * drm_default_rgb_quant_range - default RGB quantization range 5861 * @mode: display mode 5862 * 5863 * Determine the default RGB quantization range for the mode, 5864 * as specified in CEA-861. 5865 * 5866 * Return: The default RGB quantization range for the mode 5867 */ 5868 enum hdmi_quantization_range 5869 drm_default_rgb_quant_range(const struct drm_display_mode *mode) 5870 { 5871 /* All CEA modes other than VIC 1 use limited quantization range. */ 5872 return drm_match_cea_mode(mode) > 1 ? 5873 HDMI_QUANTIZATION_RANGE_LIMITED : 5874 HDMI_QUANTIZATION_RANGE_FULL; 5875 } 5876 EXPORT_SYMBOL(drm_default_rgb_quant_range); 5877 5878 /* CTA-861 Video Data Block (CTA VDB) */ 5879 static void parse_cta_vdb(struct drm_connector *connector, const struct cea_db *db) 5880 { 5881 struct drm_display_info *info = &connector->display_info; 5882 int i, vic_index, len = cea_db_payload_len(db); 5883 const u8 *svds = cea_db_data(db); 5884 u8 *vics; 5885 5886 if (!len) 5887 return; 5888 5889 /* Gracefully handle multiple VDBs, however unlikely that is */ 5890 vics = krealloc(info->vics, info->vics_len + len, GFP_KERNEL); 5891 if (!vics) 5892 return; 5893 5894 vic_index = info->vics_len; 5895 info->vics_len += len; 5896 info->vics = vics; 5897 5898 for (i = 0; i < len; i++) { 5899 u8 vic = svd_to_vic(svds[i]); 5900 5901 if (!drm_valid_cea_vic(vic)) 5902 vic = 0; 5903 5904 info->vics[vic_index++] = vic; 5905 } 5906 } 5907 5908 /* 5909 * Update y420_cmdb_modes based on previously parsed CTA VDB and Y420CMDB. 5910 * 5911 * Translate the y420cmdb_map based on VIC indexes to y420_cmdb_modes indexed 5912 * using the VICs themselves. 5913 */ 5914 static void update_cta_y420cmdb(struct drm_connector *connector, u64 y420cmdb_map) 5915 { 5916 struct drm_display_info *info = &connector->display_info; 5917 struct drm_hdmi_info *hdmi = &info->hdmi; 5918 int i, len = min_t(int, info->vics_len, BITS_PER_TYPE(y420cmdb_map)); 5919 5920 for (i = 0; i < len; i++) { 5921 u8 vic = info->vics[i]; 5922 5923 if (vic && y420cmdb_map & BIT_ULL(i)) 5924 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 5925 } 5926 } 5927 5928 static bool cta_vdb_has_vic(const struct drm_connector *connector, u8 vic) 5929 { 5930 const struct drm_display_info *info = &connector->display_info; 5931 int i; 5932 5933 if (!vic || !info->vics) 5934 return false; 5935 5936 for (i = 0; i < info->vics_len; i++) { 5937 if (info->vics[i] == vic) 5938 return true; 5939 } 5940 5941 return false; 5942 } 5943 5944 /* CTA-861-H YCbCr 4:2:0 Video Data Block (CTA Y420VDB) */ 5945 static void parse_cta_y420vdb(struct drm_connector *connector, 5946 const struct cea_db *db) 5947 { 5948 struct drm_display_info *info = &connector->display_info; 5949 struct drm_hdmi_info *hdmi = &info->hdmi; 5950 const u8 *svds = cea_db_data(db) + 1; 5951 int i; 5952 5953 for (i = 0; i < cea_db_payload_len(db) - 1; i++) { 5954 u8 vic = svd_to_vic(svds[i]); 5955 5956 if (!drm_valid_cea_vic(vic)) 5957 continue; 5958 5959 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 5960 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; 5961 } 5962 } 5963 5964 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db) 5965 { 5966 struct drm_display_info *info = &connector->display_info; 5967 5968 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] CEA VCDB 0x%02x\n", 5969 connector->base.id, connector->name, db[2]); 5970 5971 if (db[2] & EDID_CEA_VCDB_QS) 5972 info->rgb_quant_range_selectable = true; 5973 } 5974 5975 static 5976 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane) 5977 { 5978 switch (max_frl_rate) { 5979 case 1: 5980 *max_lanes = 3; 5981 *max_rate_per_lane = 3; 5982 break; 5983 case 2: 5984 *max_lanes = 3; 5985 *max_rate_per_lane = 6; 5986 break; 5987 case 3: 5988 *max_lanes = 4; 5989 *max_rate_per_lane = 6; 5990 break; 5991 case 4: 5992 *max_lanes = 4; 5993 *max_rate_per_lane = 8; 5994 break; 5995 case 5: 5996 *max_lanes = 4; 5997 *max_rate_per_lane = 10; 5998 break; 5999 case 6: 6000 *max_lanes = 4; 6001 *max_rate_per_lane = 12; 6002 break; 6003 case 0: 6004 default: 6005 *max_lanes = 0; 6006 *max_rate_per_lane = 0; 6007 } 6008 } 6009 6010 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 6011 const u8 *db) 6012 { 6013 u8 dc_mask; 6014 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 6015 6016 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 6017 hdmi->y420_dc_modes = dc_mask; 6018 } 6019 6020 static void drm_parse_dsc_info(struct drm_hdmi_dsc_cap *hdmi_dsc, 6021 const u8 *hf_scds) 6022 { 6023 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2; 6024 6025 if (!hdmi_dsc->v_1p2) 6026 return; 6027 6028 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420; 6029 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP; 6030 6031 if (hf_scds[11] & DRM_EDID_DSC_16BPC) 6032 hdmi_dsc->bpc_supported = 16; 6033 else if (hf_scds[11] & DRM_EDID_DSC_12BPC) 6034 hdmi_dsc->bpc_supported = 12; 6035 else if (hf_scds[11] & DRM_EDID_DSC_10BPC) 6036 hdmi_dsc->bpc_supported = 10; 6037 else 6038 /* Supports min 8 BPC if DSC 1.2 is supported*/ 6039 hdmi_dsc->bpc_supported = 8; 6040 6041 if (cea_db_payload_len(hf_scds) >= 12 && hf_scds[12]) { 6042 u8 dsc_max_slices; 6043 u8 dsc_max_frl_rate; 6044 6045 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4; 6046 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes, 6047 &hdmi_dsc->max_frl_rate_per_lane); 6048 6049 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES; 6050 6051 switch (dsc_max_slices) { 6052 case 1: 6053 hdmi_dsc->max_slices = 1; 6054 hdmi_dsc->clk_per_slice = 340; 6055 break; 6056 case 2: 6057 hdmi_dsc->max_slices = 2; 6058 hdmi_dsc->clk_per_slice = 340; 6059 break; 6060 case 3: 6061 hdmi_dsc->max_slices = 4; 6062 hdmi_dsc->clk_per_slice = 340; 6063 break; 6064 case 4: 6065 hdmi_dsc->max_slices = 8; 6066 hdmi_dsc->clk_per_slice = 340; 6067 break; 6068 case 5: 6069 hdmi_dsc->max_slices = 8; 6070 hdmi_dsc->clk_per_slice = 400; 6071 break; 6072 case 6: 6073 hdmi_dsc->max_slices = 12; 6074 hdmi_dsc->clk_per_slice = 400; 6075 break; 6076 case 7: 6077 hdmi_dsc->max_slices = 16; 6078 hdmi_dsc->clk_per_slice = 400; 6079 break; 6080 case 0: 6081 default: 6082 hdmi_dsc->max_slices = 0; 6083 hdmi_dsc->clk_per_slice = 0; 6084 } 6085 } 6086 6087 if (cea_db_payload_len(hf_scds) >= 13 && hf_scds[13]) 6088 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES; 6089 } 6090 6091 /* Sink Capability Data Structure */ 6092 static void drm_parse_hdmi_forum_scds(struct drm_connector *connector, 6093 const u8 *hf_scds) 6094 { 6095 struct drm_display_info *info = &connector->display_info; 6096 struct drm_hdmi_info *hdmi = &info->hdmi; 6097 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap; 6098 int max_tmds_clock = 0; 6099 u8 max_frl_rate = 0; 6100 bool dsc_support = false; 6101 6102 info->has_hdmi_infoframe = true; 6103 6104 if (hf_scds[6] & 0x80) { 6105 hdmi->scdc.supported = true; 6106 if (hf_scds[6] & 0x40) 6107 hdmi->scdc.read_request = true; 6108 } 6109 6110 /* 6111 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 6112 * And as per the spec, three factors confirm this: 6113 * * Availability of a HF-VSDB block in EDID (check) 6114 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 6115 * * SCDC support available (let's check) 6116 * Lets check it out. 6117 */ 6118 6119 if (hf_scds[5]) { 6120 struct drm_scdc *scdc = &hdmi->scdc; 6121 6122 /* max clock is 5000 KHz times block value */ 6123 max_tmds_clock = hf_scds[5] * 5000; 6124 6125 if (max_tmds_clock > 340000) { 6126 info->max_tmds_clock = max_tmds_clock; 6127 } 6128 6129 if (scdc->supported) { 6130 scdc->scrambling.supported = true; 6131 6132 /* Few sinks support scrambling for clocks < 340M */ 6133 if ((hf_scds[6] & 0x8)) 6134 scdc->scrambling.low_rates = true; 6135 } 6136 } 6137 6138 if (hf_scds[7]) { 6139 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4; 6140 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes, 6141 &hdmi->max_frl_rate_per_lane); 6142 } 6143 6144 drm_parse_ycbcr420_deep_color_info(connector, hf_scds); 6145 6146 if (cea_db_payload_len(hf_scds) >= 11 && hf_scds[11]) { 6147 drm_parse_dsc_info(hdmi_dsc, hf_scds); 6148 dsc_support = true; 6149 } 6150 6151 drm_dbg_kms(connector->dev, 6152 "[CONNECTOR:%d:%s] HF-VSDB: max TMDS clock: %d KHz, HDMI 2.1 support: %s, DSC 1.2 support: %s\n", 6153 connector->base.id, connector->name, 6154 max_tmds_clock, str_yes_no(max_frl_rate), str_yes_no(dsc_support)); 6155 } 6156 6157 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 6158 const u8 *hdmi) 6159 { 6160 struct drm_display_info *info = &connector->display_info; 6161 unsigned int dc_bpc = 0; 6162 6163 /* HDMI supports at least 8 bpc */ 6164 info->bpc = 8; 6165 6166 if (cea_db_payload_len(hdmi) < 6) 6167 return; 6168 6169 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 6170 dc_bpc = 10; 6171 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30; 6172 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 30.\n", 6173 connector->base.id, connector->name); 6174 } 6175 6176 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 6177 dc_bpc = 12; 6178 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36; 6179 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 36.\n", 6180 connector->base.id, connector->name); 6181 } 6182 6183 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 6184 dc_bpc = 16; 6185 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48; 6186 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 48.\n", 6187 connector->base.id, connector->name); 6188 } 6189 6190 if (dc_bpc == 0) { 6191 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] No deep color support on this HDMI sink.\n", 6192 connector->base.id, connector->name); 6193 return; 6194 } 6195 6196 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Assigning HDMI sink color depth as %d bpc.\n", 6197 connector->base.id, connector->name, dc_bpc); 6198 info->bpc = dc_bpc; 6199 6200 /* YCRCB444 is optional according to spec. */ 6201 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 6202 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes; 6203 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does YCRCB444 in deep color.\n", 6204 connector->base.id, connector->name); 6205 } 6206 6207 /* 6208 * Spec says that if any deep color mode is supported at all, 6209 * then deep color 36 bit must be supported. 6210 */ 6211 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 6212 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink should do DC_36, but does not!\n", 6213 connector->base.id, connector->name); 6214 } 6215 } 6216 6217 /* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */ 6218 static void 6219 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 6220 { 6221 struct drm_display_info *info = &connector->display_info; 6222 u8 len = cea_db_payload_len(db); 6223 6224 info->is_hdmi = true; 6225 6226 info->source_physical_address = (db[4] << 8) | db[5]; 6227 6228 if (len >= 6) 6229 info->dvi_dual = db[6] & 1; 6230 if (len >= 7) 6231 info->max_tmds_clock = db[7] * 5000; 6232 6233 /* 6234 * Try to infer whether the sink supports HDMI infoframes. 6235 * 6236 * HDMI infoframe support was first added in HDMI 1.4. Assume the sink 6237 * supports infoframes if HDMI_Video_present is set. 6238 */ 6239 if (len >= 8 && db[8] & BIT(5)) 6240 info->has_hdmi_infoframe = true; 6241 6242 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI: DVI dual %d, max TMDS clock %d kHz\n", 6243 connector->base.id, connector->name, 6244 info->dvi_dual, info->max_tmds_clock); 6245 6246 drm_parse_hdmi_deep_color_info(connector, db); 6247 } 6248 6249 /* 6250 * See EDID extension for head-mounted and specialized monitors, specified at: 6251 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension 6252 */ 6253 static void drm_parse_microsoft_vsdb(struct drm_connector *connector, 6254 const u8 *db) 6255 { 6256 struct drm_display_info *info = &connector->display_info; 6257 u8 version = db[4]; 6258 bool desktop_usage = db[5] & BIT(6); 6259 6260 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */ 6261 if (version == 1 || version == 2 || (version == 3 && !desktop_usage)) 6262 info->non_desktop = true; 6263 6264 drm_dbg_kms(connector->dev, 6265 "[CONNECTOR:%d:%s] HMD or specialized display VSDB version %u: 0x%02x\n", 6266 connector->base.id, connector->name, version, db[5]); 6267 } 6268 6269 static void drm_parse_cea_ext(struct drm_connector *connector, 6270 const struct drm_edid *drm_edid) 6271 { 6272 struct drm_display_info *info = &connector->display_info; 6273 struct drm_edid_iter edid_iter; 6274 const struct cea_db *db; 6275 struct cea_db_iter iter; 6276 const u8 *edid_ext; 6277 u64 y420cmdb_map = 0; 6278 6279 drm_edid_iter_begin(drm_edid, &edid_iter); 6280 drm_edid_iter_for_each(edid_ext, &edid_iter) { 6281 if (edid_ext[0] != CEA_EXT) 6282 continue; 6283 6284 if (!info->cea_rev) 6285 info->cea_rev = edid_ext[1]; 6286 6287 if (info->cea_rev != edid_ext[1]) 6288 drm_dbg_kms(connector->dev, 6289 "[CONNECTOR:%d:%s] CEA extension version mismatch %u != %u\n", 6290 connector->base.id, connector->name, 6291 info->cea_rev, edid_ext[1]); 6292 6293 /* The existence of a CTA extension should imply RGB support */ 6294 info->color_formats = DRM_COLOR_FORMAT_RGB444; 6295 if (edid_ext[3] & EDID_CEA_YCRCB444) 6296 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444; 6297 if (edid_ext[3] & EDID_CEA_YCRCB422) 6298 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422; 6299 if (edid_ext[3] & EDID_BASIC_AUDIO) 6300 info->has_audio = true; 6301 6302 } 6303 drm_edid_iter_end(&edid_iter); 6304 6305 cea_db_iter_edid_begin(drm_edid, &iter); 6306 cea_db_iter_for_each(db, &iter) { 6307 /* FIXME: convert parsers to use struct cea_db */ 6308 const u8 *data = (const u8 *)db; 6309 6310 if (cea_db_is_hdmi_vsdb(db)) 6311 drm_parse_hdmi_vsdb_video(connector, data); 6312 else if (cea_db_is_hdmi_forum_vsdb(db) || 6313 cea_db_is_hdmi_forum_scdb(db)) 6314 drm_parse_hdmi_forum_scds(connector, data); 6315 else if (cea_db_is_microsoft_vsdb(db)) 6316 drm_parse_microsoft_vsdb(connector, data); 6317 else if (cea_db_is_y420cmdb(db)) 6318 parse_cta_y420cmdb(connector, db, &y420cmdb_map); 6319 else if (cea_db_is_y420vdb(db)) 6320 parse_cta_y420vdb(connector, db); 6321 else if (cea_db_is_vcdb(db)) 6322 drm_parse_vcdb(connector, data); 6323 else if (cea_db_is_hdmi_hdr_metadata_block(db)) 6324 drm_parse_hdr_metadata_block(connector, data); 6325 else if (cea_db_tag(db) == CTA_DB_VIDEO) 6326 parse_cta_vdb(connector, db); 6327 else if (cea_db_tag(db) == CTA_DB_AUDIO) 6328 info->has_audio = true; 6329 } 6330 cea_db_iter_end(&iter); 6331 6332 if (y420cmdb_map) 6333 update_cta_y420cmdb(connector, y420cmdb_map); 6334 } 6335 6336 static 6337 void get_monitor_range(const struct detailed_timing *timing, void *c) 6338 { 6339 struct detailed_mode_closure *closure = c; 6340 struct drm_display_info *info = &closure->connector->display_info; 6341 struct drm_monitor_range_info *monitor_range = &info->monitor_range; 6342 const struct detailed_non_pixel *data = &timing->data.other_data; 6343 const struct detailed_data_monitor_range *range = &data->data.range; 6344 const struct edid *edid = closure->drm_edid->edid; 6345 6346 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE)) 6347 return; 6348 6349 /* 6350 * These limits are used to determine the VRR refresh 6351 * rate range. Only the "range limits only" variant 6352 * of the range descriptor seems to guarantee that 6353 * any and all timings are accepted by the sink, as 6354 * opposed to just timings conforming to the indicated 6355 * formula (GTF/GTF2/CVT). Thus other variants of the 6356 * range descriptor are not accepted here. 6357 */ 6358 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG) 6359 return; 6360 6361 monitor_range->min_vfreq = range->min_vfreq; 6362 monitor_range->max_vfreq = range->max_vfreq; 6363 6364 if (edid->revision >= 4) { 6365 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ) 6366 monitor_range->min_vfreq += 255; 6367 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ) 6368 monitor_range->max_vfreq += 255; 6369 } 6370 } 6371 6372 static void drm_get_monitor_range(struct drm_connector *connector, 6373 const struct drm_edid *drm_edid) 6374 { 6375 const struct drm_display_info *info = &connector->display_info; 6376 struct detailed_mode_closure closure = { 6377 .connector = connector, 6378 .drm_edid = drm_edid, 6379 }; 6380 6381 if (drm_edid->edid->revision < 4) 6382 return; 6383 6384 if (!(drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ)) 6385 return; 6386 6387 drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure); 6388 6389 drm_dbg_kms(connector->dev, 6390 "[CONNECTOR:%d:%s] Supported Monitor Refresh rate range is %d Hz - %d Hz\n", 6391 connector->base.id, connector->name, 6392 info->monitor_range.min_vfreq, info->monitor_range.max_vfreq); 6393 } 6394 6395 static void drm_parse_vesa_mso_data(struct drm_connector *connector, 6396 const struct displayid_block *block) 6397 { 6398 struct displayid_vesa_vendor_specific_block *vesa = 6399 (struct displayid_vesa_vendor_specific_block *)block; 6400 struct drm_display_info *info = &connector->display_info; 6401 6402 if (block->num_bytes < 3) { 6403 drm_dbg_kms(connector->dev, 6404 "[CONNECTOR:%d:%s] Unexpected vendor block size %u\n", 6405 connector->base.id, connector->name, block->num_bytes); 6406 return; 6407 } 6408 6409 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI) 6410 return; 6411 6412 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) { 6413 drm_dbg_kms(connector->dev, 6414 "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n", 6415 connector->base.id, connector->name); 6416 return; 6417 } 6418 6419 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) { 6420 default: 6421 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n", 6422 connector->base.id, connector->name); 6423 fallthrough; 6424 case 0: 6425 info->mso_stream_count = 0; 6426 break; 6427 case 1: 6428 info->mso_stream_count = 2; /* 2 or 4 links */ 6429 break; 6430 case 2: 6431 info->mso_stream_count = 4; /* 4 links */ 6432 break; 6433 } 6434 6435 if (!info->mso_stream_count) { 6436 info->mso_pixel_overlap = 0; 6437 return; 6438 } 6439 6440 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso); 6441 if (info->mso_pixel_overlap > 8) { 6442 drm_dbg_kms(connector->dev, 6443 "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n", 6444 connector->base.id, connector->name, 6445 info->mso_pixel_overlap); 6446 info->mso_pixel_overlap = 8; 6447 } 6448 6449 drm_dbg_kms(connector->dev, 6450 "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n", 6451 connector->base.id, connector->name, 6452 info->mso_stream_count, info->mso_pixel_overlap); 6453 } 6454 6455 static void drm_update_mso(struct drm_connector *connector, 6456 const struct drm_edid *drm_edid) 6457 { 6458 const struct displayid_block *block; 6459 struct displayid_iter iter; 6460 6461 displayid_iter_edid_begin(drm_edid, &iter); 6462 displayid_iter_for_each(block, &iter) { 6463 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC) 6464 drm_parse_vesa_mso_data(connector, block); 6465 } 6466 displayid_iter_end(&iter); 6467 } 6468 6469 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset 6470 * all of the values which would have been set from EDID 6471 */ 6472 static void drm_reset_display_info(struct drm_connector *connector) 6473 { 6474 struct drm_display_info *info = &connector->display_info; 6475 6476 info->width_mm = 0; 6477 info->height_mm = 0; 6478 6479 info->bpc = 0; 6480 info->color_formats = 0; 6481 info->cea_rev = 0; 6482 info->max_tmds_clock = 0; 6483 info->dvi_dual = false; 6484 info->is_hdmi = false; 6485 info->has_audio = false; 6486 info->has_hdmi_infoframe = false; 6487 info->rgb_quant_range_selectable = false; 6488 memset(&info->hdmi, 0, sizeof(info->hdmi)); 6489 6490 info->edid_hdmi_rgb444_dc_modes = 0; 6491 info->edid_hdmi_ycbcr444_dc_modes = 0; 6492 6493 info->non_desktop = 0; 6494 memset(&info->monitor_range, 0, sizeof(info->monitor_range)); 6495 memset(&info->luminance_range, 0, sizeof(info->luminance_range)); 6496 6497 info->mso_stream_count = 0; 6498 info->mso_pixel_overlap = 0; 6499 info->max_dsc_bpp = 0; 6500 6501 kfree(info->vics); 6502 info->vics = NULL; 6503 info->vics_len = 0; 6504 6505 info->quirks = 0; 6506 6507 info->source_physical_address = CEC_PHYS_ADDR_INVALID; 6508 } 6509 6510 static void update_displayid_info(struct drm_connector *connector, 6511 const struct drm_edid *drm_edid) 6512 { 6513 struct drm_display_info *info = &connector->display_info; 6514 const struct displayid_block *block; 6515 struct displayid_iter iter; 6516 6517 displayid_iter_edid_begin(drm_edid, &iter); 6518 displayid_iter_for_each(block, &iter) { 6519 if (displayid_version(&iter) == DISPLAY_ID_STRUCTURE_VER_20 && 6520 (displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_VR || 6521 displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_AR)) 6522 info->non_desktop = true; 6523 6524 /* 6525 * We're only interested in the base section here, no need to 6526 * iterate further. 6527 */ 6528 break; 6529 } 6530 displayid_iter_end(&iter); 6531 } 6532 6533 static void update_display_info(struct drm_connector *connector, 6534 const struct drm_edid *drm_edid) 6535 { 6536 struct drm_display_info *info = &connector->display_info; 6537 const struct edid *edid; 6538 6539 drm_reset_display_info(connector); 6540 clear_eld(connector); 6541 6542 if (!drm_edid) 6543 return; 6544 6545 edid = drm_edid->edid; 6546 6547 info->quirks = edid_get_quirks(drm_edid); 6548 6549 info->width_mm = edid->width_cm * 10; 6550 info->height_mm = edid->height_cm * 10; 6551 6552 drm_get_monitor_range(connector, drm_edid); 6553 6554 if (edid->revision < 3) 6555 goto out; 6556 6557 if (!drm_edid_is_digital(drm_edid)) 6558 goto out; 6559 6560 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 6561 drm_parse_cea_ext(connector, drm_edid); 6562 6563 update_displayid_info(connector, drm_edid); 6564 6565 /* 6566 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 6567 * 6568 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 6569 * tells us to assume 8 bpc color depth if the EDID doesn't have 6570 * extensions which tell otherwise. 6571 */ 6572 if (info->bpc == 0 && edid->revision == 3 && 6573 edid->input & DRM_EDID_DIGITAL_DFP_1_X) { 6574 info->bpc = 8; 6575 drm_dbg_kms(connector->dev, 6576 "[CONNECTOR:%d:%s] Assigning DFP sink color depth as %d bpc.\n", 6577 connector->base.id, connector->name, info->bpc); 6578 } 6579 6580 /* Only defined for 1.4 with digital displays */ 6581 if (edid->revision < 4) 6582 goto out; 6583 6584 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 6585 case DRM_EDID_DIGITAL_DEPTH_6: 6586 info->bpc = 6; 6587 break; 6588 case DRM_EDID_DIGITAL_DEPTH_8: 6589 info->bpc = 8; 6590 break; 6591 case DRM_EDID_DIGITAL_DEPTH_10: 6592 info->bpc = 10; 6593 break; 6594 case DRM_EDID_DIGITAL_DEPTH_12: 6595 info->bpc = 12; 6596 break; 6597 case DRM_EDID_DIGITAL_DEPTH_14: 6598 info->bpc = 14; 6599 break; 6600 case DRM_EDID_DIGITAL_DEPTH_16: 6601 info->bpc = 16; 6602 break; 6603 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 6604 default: 6605 info->bpc = 0; 6606 break; 6607 } 6608 6609 drm_dbg_kms(connector->dev, 6610 "[CONNECTOR:%d:%s] Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 6611 connector->base.id, connector->name, info->bpc); 6612 6613 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 6614 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444; 6615 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 6616 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422; 6617 6618 drm_update_mso(connector, drm_edid); 6619 6620 out: 6621 if (info->quirks & EDID_QUIRK_NON_DESKTOP) { 6622 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Non-desktop display%s\n", 6623 connector->base.id, connector->name, 6624 info->non_desktop ? " (redundant quirk)" : ""); 6625 info->non_desktop = true; 6626 } 6627 6628 if (info->quirks & EDID_QUIRK_CAP_DSC_15BPP) 6629 info->max_dsc_bpp = 15; 6630 6631 if (info->quirks & EDID_QUIRK_FORCE_6BPC) 6632 info->bpc = 6; 6633 6634 if (info->quirks & EDID_QUIRK_FORCE_8BPC) 6635 info->bpc = 8; 6636 6637 if (info->quirks & EDID_QUIRK_FORCE_10BPC) 6638 info->bpc = 10; 6639 6640 if (info->quirks & EDID_QUIRK_FORCE_12BPC) 6641 info->bpc = 12; 6642 6643 /* Depends on info->cea_rev set by drm_parse_cea_ext() above */ 6644 drm_edid_to_eld(connector, drm_edid); 6645 } 6646 6647 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 6648 struct displayid_detailed_timings_1 *timings, 6649 bool type_7) 6650 { 6651 struct drm_display_mode *mode; 6652 unsigned pixel_clock = (timings->pixel_clock[0] | 6653 (timings->pixel_clock[1] << 8) | 6654 (timings->pixel_clock[2] << 16)) + 1; 6655 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 6656 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 6657 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 6658 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 6659 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 6660 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 6661 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 6662 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 6663 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 6664 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 6665 6666 mode = drm_mode_create(dev); 6667 if (!mode) 6668 return NULL; 6669 6670 /* resolution is kHz for type VII, and 10 kHz for type I */ 6671 mode->clock = type_7 ? pixel_clock : pixel_clock * 10; 6672 mode->hdisplay = hactive; 6673 mode->hsync_start = mode->hdisplay + hsync; 6674 mode->hsync_end = mode->hsync_start + hsync_width; 6675 mode->htotal = mode->hdisplay + hblank; 6676 6677 mode->vdisplay = vactive; 6678 mode->vsync_start = mode->vdisplay + vsync; 6679 mode->vsync_end = mode->vsync_start + vsync_width; 6680 mode->vtotal = mode->vdisplay + vblank; 6681 6682 mode->flags = 0; 6683 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 6684 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 6685 mode->type = DRM_MODE_TYPE_DRIVER; 6686 6687 if (timings->flags & 0x80) 6688 mode->type |= DRM_MODE_TYPE_PREFERRED; 6689 drm_mode_set_name(mode); 6690 6691 return mode; 6692 } 6693 6694 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 6695 const struct displayid_block *block) 6696 { 6697 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 6698 int i; 6699 int num_timings; 6700 struct drm_display_mode *newmode; 6701 int num_modes = 0; 6702 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING; 6703 /* blocks must be multiple of 20 bytes length */ 6704 if (block->num_bytes % 20) 6705 return 0; 6706 6707 num_timings = block->num_bytes / 20; 6708 for (i = 0; i < num_timings; i++) { 6709 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 6710 6711 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7); 6712 if (!newmode) 6713 continue; 6714 6715 drm_mode_probed_add(connector, newmode); 6716 num_modes++; 6717 } 6718 return num_modes; 6719 } 6720 6721 static int add_displayid_detailed_modes(struct drm_connector *connector, 6722 const struct drm_edid *drm_edid) 6723 { 6724 const struct displayid_block *block; 6725 struct displayid_iter iter; 6726 int num_modes = 0; 6727 6728 displayid_iter_edid_begin(drm_edid, &iter); 6729 displayid_iter_for_each(block, &iter) { 6730 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING || 6731 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING) 6732 num_modes += add_displayid_detailed_1_modes(connector, block); 6733 } 6734 displayid_iter_end(&iter); 6735 6736 return num_modes; 6737 } 6738 6739 static int _drm_edid_connector_add_modes(struct drm_connector *connector, 6740 const struct drm_edid *drm_edid) 6741 { 6742 const struct drm_display_info *info = &connector->display_info; 6743 int num_modes = 0; 6744 6745 if (!drm_edid) 6746 return 0; 6747 6748 /* 6749 * EDID spec says modes should be preferred in this order: 6750 * - preferred detailed mode 6751 * - other detailed modes from base block 6752 * - detailed modes from extension blocks 6753 * - CVT 3-byte code modes 6754 * - standard timing codes 6755 * - established timing codes 6756 * - modes inferred from GTF or CVT range information 6757 * 6758 * We get this pretty much right. 6759 * 6760 * XXX order for additional mode types in extension blocks? 6761 */ 6762 num_modes += add_detailed_modes(connector, drm_edid); 6763 num_modes += add_cvt_modes(connector, drm_edid); 6764 num_modes += add_standard_modes(connector, drm_edid); 6765 num_modes += add_established_modes(connector, drm_edid); 6766 num_modes += add_cea_modes(connector, drm_edid); 6767 num_modes += add_alternate_cea_modes(connector, drm_edid); 6768 num_modes += add_displayid_detailed_modes(connector, drm_edid); 6769 if (drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ) 6770 num_modes += add_inferred_modes(connector, drm_edid); 6771 6772 if (info->quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 6773 edid_fixup_preferred(connector); 6774 6775 return num_modes; 6776 } 6777 6778 static void _drm_update_tile_info(struct drm_connector *connector, 6779 const struct drm_edid *drm_edid); 6780 6781 static int _drm_edid_connector_property_update(struct drm_connector *connector, 6782 const struct drm_edid *drm_edid) 6783 { 6784 struct drm_device *dev = connector->dev; 6785 int ret; 6786 6787 if (connector->edid_blob_ptr) { 6788 const struct edid *old_edid = connector->edid_blob_ptr->data; 6789 6790 if (old_edid) { 6791 if (!drm_edid_are_equal(drm_edid ? drm_edid->edid : NULL, old_edid)) { 6792 connector->epoch_counter++; 6793 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n", 6794 connector->base.id, connector->name, 6795 connector->epoch_counter); 6796 } 6797 } 6798 } 6799 6800 ret = drm_property_replace_global_blob(dev, 6801 &connector->edid_blob_ptr, 6802 drm_edid ? drm_edid->size : 0, 6803 drm_edid ? drm_edid->edid : NULL, 6804 &connector->base, 6805 dev->mode_config.edid_property); 6806 if (ret) { 6807 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n", 6808 connector->base.id, connector->name, ret); 6809 goto out; 6810 } 6811 6812 ret = drm_object_property_set_value(&connector->base, 6813 dev->mode_config.non_desktop_property, 6814 connector->display_info.non_desktop); 6815 if (ret) { 6816 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n", 6817 connector->base.id, connector->name, ret); 6818 goto out; 6819 } 6820 6821 ret = drm_connector_set_tile_property(connector); 6822 if (ret) { 6823 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n", 6824 connector->base.id, connector->name, ret); 6825 goto out; 6826 } 6827 6828 out: 6829 return ret; 6830 } 6831 6832 /** 6833 * drm_edid_connector_update - Update connector information from EDID 6834 * @connector: Connector 6835 * @drm_edid: EDID 6836 * 6837 * Update the connector display info, ELD, HDR metadata, relevant properties, 6838 * etc. from the passed in EDID. 6839 * 6840 * If EDID is NULL, reset the information. 6841 * 6842 * Must be called before calling drm_edid_connector_add_modes(). 6843 * 6844 * Return: 0 on success, negative error on errors. 6845 */ 6846 int drm_edid_connector_update(struct drm_connector *connector, 6847 const struct drm_edid *drm_edid) 6848 { 6849 update_display_info(connector, drm_edid); 6850 6851 _drm_update_tile_info(connector, drm_edid); 6852 6853 return _drm_edid_connector_property_update(connector, drm_edid); 6854 } 6855 EXPORT_SYMBOL(drm_edid_connector_update); 6856 6857 /** 6858 * drm_edid_connector_add_modes - Update probed modes from the EDID property 6859 * @connector: Connector 6860 * 6861 * Add the modes from the previously updated EDID property to the connector 6862 * probed modes list. 6863 * 6864 * drm_edid_connector_update() must have been called before this to update the 6865 * EDID property. 6866 * 6867 * Return: The number of modes added, or 0 if we couldn't find any. 6868 */ 6869 int drm_edid_connector_add_modes(struct drm_connector *connector) 6870 { 6871 const struct drm_edid *drm_edid = NULL; 6872 int count; 6873 6874 if (connector->edid_blob_ptr) 6875 drm_edid = drm_edid_alloc(connector->edid_blob_ptr->data, 6876 connector->edid_blob_ptr->length); 6877 6878 count = _drm_edid_connector_add_modes(connector, drm_edid); 6879 6880 drm_edid_free(drm_edid); 6881 6882 return count; 6883 } 6884 EXPORT_SYMBOL(drm_edid_connector_add_modes); 6885 6886 /** 6887 * drm_connector_update_edid_property - update the edid property of a connector 6888 * @connector: drm connector 6889 * @edid: new value of the edid property 6890 * 6891 * This function creates a new blob modeset object and assigns its id to the 6892 * connector's edid property. 6893 * Since we also parse tile information from EDID's displayID block, we also 6894 * set the connector's tile property here. See drm_connector_set_tile_property() 6895 * for more details. 6896 * 6897 * This function is deprecated. Use drm_edid_connector_update() instead. 6898 * 6899 * Returns: 6900 * Zero on success, negative errno on failure. 6901 */ 6902 int drm_connector_update_edid_property(struct drm_connector *connector, 6903 const struct edid *edid) 6904 { 6905 struct drm_edid drm_edid; 6906 6907 return drm_edid_connector_update(connector, drm_edid_legacy_init(&drm_edid, edid)); 6908 } 6909 EXPORT_SYMBOL(drm_connector_update_edid_property); 6910 6911 /** 6912 * drm_add_edid_modes - add modes from EDID data, if available 6913 * @connector: connector we're probing 6914 * @edid: EDID data 6915 * 6916 * Add the specified modes to the connector's mode list. Also fills out the 6917 * &drm_display_info structure and ELD in @connector with any information which 6918 * can be derived from the edid. 6919 * 6920 * This function is deprecated. Use drm_edid_connector_add_modes() instead. 6921 * 6922 * Return: The number of modes added or 0 if we couldn't find any. 6923 */ 6924 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 6925 { 6926 struct drm_edid _drm_edid; 6927 const struct drm_edid *drm_edid; 6928 6929 if (edid && !drm_edid_is_valid(edid)) { 6930 drm_warn(connector->dev, "[CONNECTOR:%d:%s] EDID invalid.\n", 6931 connector->base.id, connector->name); 6932 edid = NULL; 6933 } 6934 6935 drm_edid = drm_edid_legacy_init(&_drm_edid, edid); 6936 6937 update_display_info(connector, drm_edid); 6938 6939 return _drm_edid_connector_add_modes(connector, drm_edid); 6940 } 6941 EXPORT_SYMBOL(drm_add_edid_modes); 6942 6943 /** 6944 * drm_add_modes_noedid - add modes for the connectors without EDID 6945 * @connector: connector we're probing 6946 * @hdisplay: the horizontal display limit 6947 * @vdisplay: the vertical display limit 6948 * 6949 * Add the specified modes to the connector's mode list. Only when the 6950 * hdisplay/vdisplay is not beyond the given limit, it will be added. 6951 * 6952 * Return: The number of modes added or 0 if we couldn't find any. 6953 */ 6954 int drm_add_modes_noedid(struct drm_connector *connector, 6955 int hdisplay, int vdisplay) 6956 { 6957 int i, count, num_modes = 0; 6958 struct drm_display_mode *mode; 6959 struct drm_device *dev = connector->dev; 6960 6961 count = ARRAY_SIZE(drm_dmt_modes); 6962 if (hdisplay < 0) 6963 hdisplay = 0; 6964 if (vdisplay < 0) 6965 vdisplay = 0; 6966 6967 for (i = 0; i < count; i++) { 6968 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 6969 6970 if (hdisplay && vdisplay) { 6971 /* 6972 * Only when two are valid, they will be used to check 6973 * whether the mode should be added to the mode list of 6974 * the connector. 6975 */ 6976 if (ptr->hdisplay > hdisplay || 6977 ptr->vdisplay > vdisplay) 6978 continue; 6979 } 6980 if (drm_mode_vrefresh(ptr) > 61) 6981 continue; 6982 mode = drm_mode_duplicate(dev, ptr); 6983 if (mode) { 6984 drm_mode_probed_add(connector, mode); 6985 num_modes++; 6986 } 6987 } 6988 return num_modes; 6989 } 6990 EXPORT_SYMBOL(drm_add_modes_noedid); 6991 6992 /** 6993 * drm_set_preferred_mode - Sets the preferred mode of a connector 6994 * @connector: connector whose mode list should be processed 6995 * @hpref: horizontal resolution of preferred mode 6996 * @vpref: vertical resolution of preferred mode 6997 * 6998 * Marks a mode as preferred if it matches the resolution specified by @hpref 6999 * and @vpref. 7000 */ 7001 void drm_set_preferred_mode(struct drm_connector *connector, 7002 int hpref, int vpref) 7003 { 7004 struct drm_display_mode *mode; 7005 7006 list_for_each_entry(mode, &connector->probed_modes, head) { 7007 if (mode->hdisplay == hpref && 7008 mode->vdisplay == vpref) 7009 mode->type |= DRM_MODE_TYPE_PREFERRED; 7010 } 7011 } 7012 EXPORT_SYMBOL(drm_set_preferred_mode); 7013 7014 static bool is_hdmi2_sink(const struct drm_connector *connector) 7015 { 7016 /* 7017 * FIXME: sil-sii8620 doesn't have a connector around when 7018 * we need one, so we have to be prepared for a NULL connector. 7019 */ 7020 if (!connector) 7021 return true; 7022 7023 return connector->display_info.hdmi.scdc.supported || 7024 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420; 7025 } 7026 7027 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector, 7028 const struct drm_display_mode *mode) 7029 { 7030 bool has_hdmi_infoframe = connector ? 7031 connector->display_info.has_hdmi_infoframe : false; 7032 7033 if (!has_hdmi_infoframe) 7034 return 0; 7035 7036 /* No HDMI VIC when signalling 3D video format */ 7037 if (mode->flags & DRM_MODE_FLAG_3D_MASK) 7038 return 0; 7039 7040 return drm_match_hdmi_mode(mode); 7041 } 7042 7043 static u8 drm_mode_cea_vic(const struct drm_connector *connector, 7044 const struct drm_display_mode *mode) 7045 { 7046 /* 7047 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 7048 * we should send its VIC in vendor infoframes, else send the 7049 * VIC in AVI infoframes. Lets check if this mode is present in 7050 * HDMI 1.4b 4K modes 7051 */ 7052 if (drm_mode_hdmi_vic(connector, mode)) 7053 return 0; 7054 7055 return drm_match_cea_mode(mode); 7056 } 7057 7058 /* 7059 * Avoid sending VICs defined in HDMI 2.0 in AVI infoframes to sinks that 7060 * conform to HDMI 1.4. 7061 * 7062 * HDMI 1.4 (CTA-861-D) VIC range: [1..64] 7063 * HDMI 2.0 (CTA-861-F) VIC range: [1..107] 7064 * 7065 * If the sink lists the VIC in CTA VDB, assume it's fine, regardless of HDMI 7066 * version. 7067 */ 7068 static u8 vic_for_avi_infoframe(const struct drm_connector *connector, u8 vic) 7069 { 7070 if (!is_hdmi2_sink(connector) && vic > 64 && 7071 !cta_vdb_has_vic(connector, vic)) 7072 return 0; 7073 7074 return vic; 7075 } 7076 7077 /** 7078 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 7079 * data from a DRM display mode 7080 * @frame: HDMI AVI infoframe 7081 * @connector: the connector 7082 * @mode: DRM display mode 7083 * 7084 * Return: 0 on success or a negative error code on failure. 7085 */ 7086 int 7087 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 7088 const struct drm_connector *connector, 7089 const struct drm_display_mode *mode) 7090 { 7091 enum hdmi_picture_aspect picture_aspect; 7092 u8 vic, hdmi_vic; 7093 7094 if (!frame || !mode) 7095 return -EINVAL; 7096 7097 hdmi_avi_infoframe_init(frame); 7098 7099 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 7100 frame->pixel_repeat = 1; 7101 7102 vic = drm_mode_cea_vic(connector, mode); 7103 hdmi_vic = drm_mode_hdmi_vic(connector, mode); 7104 7105 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 7106 7107 /* 7108 * As some drivers don't support atomic, we can't use connector state. 7109 * So just initialize the frame with default values, just the same way 7110 * as it's done with other properties here. 7111 */ 7112 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; 7113 frame->itc = 0; 7114 7115 /* 7116 * Populate picture aspect ratio from either 7117 * user input (if specified) or from the CEA/HDMI mode lists. 7118 */ 7119 picture_aspect = mode->picture_aspect_ratio; 7120 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) { 7121 if (vic) 7122 picture_aspect = drm_get_cea_aspect_ratio(vic); 7123 else if (hdmi_vic) 7124 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic); 7125 } 7126 7127 /* 7128 * The infoframe can't convey anything but none, 4:3 7129 * and 16:9, so if the user has asked for anything else 7130 * we can only satisfy it by specifying the right VIC. 7131 */ 7132 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { 7133 if (vic) { 7134 if (picture_aspect != drm_get_cea_aspect_ratio(vic)) 7135 return -EINVAL; 7136 } else if (hdmi_vic) { 7137 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic)) 7138 return -EINVAL; 7139 } else { 7140 return -EINVAL; 7141 } 7142 7143 picture_aspect = HDMI_PICTURE_ASPECT_NONE; 7144 } 7145 7146 frame->video_code = vic_for_avi_infoframe(connector, vic); 7147 frame->picture_aspect = picture_aspect; 7148 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 7149 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 7150 7151 return 0; 7152 } 7153 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 7154 7155 /** 7156 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 7157 * quantization range information 7158 * @frame: HDMI AVI infoframe 7159 * @connector: the connector 7160 * @mode: DRM display mode 7161 * @rgb_quant_range: RGB quantization range (Q) 7162 */ 7163 void 7164 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 7165 const struct drm_connector *connector, 7166 const struct drm_display_mode *mode, 7167 enum hdmi_quantization_range rgb_quant_range) 7168 { 7169 const struct drm_display_info *info = &connector->display_info; 7170 7171 /* 7172 * CEA-861: 7173 * "A Source shall not send a non-zero Q value that does not correspond 7174 * to the default RGB Quantization Range for the transmitted Picture 7175 * unless the Sink indicates support for the Q bit in a Video 7176 * Capabilities Data Block." 7177 * 7178 * HDMI 2.0 recommends sending non-zero Q when it does match the 7179 * default RGB quantization range for the mode, even when QS=0. 7180 */ 7181 if (info->rgb_quant_range_selectable || 7182 rgb_quant_range == drm_default_rgb_quant_range(mode)) 7183 frame->quantization_range = rgb_quant_range; 7184 else 7185 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 7186 7187 /* 7188 * CEA-861-F: 7189 * "When transmitting any RGB colorimetry, the Source should set the 7190 * YQ-field to match the RGB Quantization Range being transmitted 7191 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 7192 * set YQ=1) and the Sink shall ignore the YQ-field." 7193 * 7194 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused 7195 * by non-zero YQ when receiving RGB. There doesn't seem to be any 7196 * good way to tell which version of CEA-861 the sink supports, so 7197 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based 7198 * on CEA-861-F. 7199 */ 7200 if (!is_hdmi2_sink(connector) || 7201 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 7202 frame->ycc_quantization_range = 7203 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 7204 else 7205 frame->ycc_quantization_range = 7206 HDMI_YCC_QUANTIZATION_RANGE_FULL; 7207 } 7208 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 7209 7210 static enum hdmi_3d_structure 7211 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 7212 { 7213 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 7214 7215 switch (layout) { 7216 case DRM_MODE_FLAG_3D_FRAME_PACKING: 7217 return HDMI_3D_STRUCTURE_FRAME_PACKING; 7218 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 7219 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 7220 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 7221 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 7222 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 7223 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 7224 case DRM_MODE_FLAG_3D_L_DEPTH: 7225 return HDMI_3D_STRUCTURE_L_DEPTH; 7226 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 7227 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 7228 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 7229 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 7230 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 7231 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 7232 default: 7233 return HDMI_3D_STRUCTURE_INVALID; 7234 } 7235 } 7236 7237 /** 7238 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 7239 * data from a DRM display mode 7240 * @frame: HDMI vendor infoframe 7241 * @connector: the connector 7242 * @mode: DRM display mode 7243 * 7244 * Note that there's is a need to send HDMI vendor infoframes only when using a 7245 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 7246 * function will return -EINVAL, error that can be safely ignored. 7247 * 7248 * Return: 0 on success or a negative error code on failure. 7249 */ 7250 int 7251 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 7252 const struct drm_connector *connector, 7253 const struct drm_display_mode *mode) 7254 { 7255 /* 7256 * FIXME: sil-sii8620 doesn't have a connector around when 7257 * we need one, so we have to be prepared for a NULL connector. 7258 */ 7259 bool has_hdmi_infoframe = connector ? 7260 connector->display_info.has_hdmi_infoframe : false; 7261 int err; 7262 7263 if (!frame || !mode) 7264 return -EINVAL; 7265 7266 if (!has_hdmi_infoframe) 7267 return -EINVAL; 7268 7269 err = hdmi_vendor_infoframe_init(frame); 7270 if (err < 0) 7271 return err; 7272 7273 /* 7274 * Even if it's not absolutely necessary to send the infoframe 7275 * (ie.vic==0 and s3d_struct==0) we will still send it if we 7276 * know that the sink can handle it. This is based on a 7277 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks 7278 * have trouble realizing that they should switch from 3D to 2D 7279 * mode if the source simply stops sending the infoframe when 7280 * it wants to switch from 3D to 2D. 7281 */ 7282 frame->vic = drm_mode_hdmi_vic(connector, mode); 7283 frame->s3d_struct = s3d_structure_from_display_mode(mode); 7284 7285 return 0; 7286 } 7287 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 7288 7289 static void drm_parse_tiled_block(struct drm_connector *connector, 7290 const struct displayid_block *block) 7291 { 7292 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 7293 u16 w, h; 7294 u8 tile_v_loc, tile_h_loc; 7295 u8 num_v_tile, num_h_tile; 7296 struct drm_tile_group *tg; 7297 7298 w = tile->tile_size[0] | tile->tile_size[1] << 8; 7299 h = tile->tile_size[2] | tile->tile_size[3] << 8; 7300 7301 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 7302 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 7303 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 7304 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 7305 7306 connector->has_tile = true; 7307 if (tile->tile_cap & 0x80) 7308 connector->tile_is_single_monitor = true; 7309 7310 connector->num_h_tile = num_h_tile + 1; 7311 connector->num_v_tile = num_v_tile + 1; 7312 connector->tile_h_loc = tile_h_loc; 7313 connector->tile_v_loc = tile_v_loc; 7314 connector->tile_h_size = w + 1; 7315 connector->tile_v_size = h + 1; 7316 7317 drm_dbg_kms(connector->dev, 7318 "[CONNECTOR:%d:%s] tile cap 0x%x, size %dx%d, num tiles %dx%d, location %dx%d, vend %c%c%c", 7319 connector->base.id, connector->name, 7320 tile->tile_cap, 7321 connector->tile_h_size, connector->tile_v_size, 7322 connector->num_h_tile, connector->num_v_tile, 7323 connector->tile_h_loc, connector->tile_v_loc, 7324 tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 7325 7326 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 7327 if (!tg) 7328 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 7329 if (!tg) 7330 return; 7331 7332 if (connector->tile_group != tg) { 7333 /* if we haven't got a pointer, 7334 take the reference, drop ref to old tile group */ 7335 if (connector->tile_group) 7336 drm_mode_put_tile_group(connector->dev, connector->tile_group); 7337 connector->tile_group = tg; 7338 } else { 7339 /* if same tile group, then release the ref we just took. */ 7340 drm_mode_put_tile_group(connector->dev, tg); 7341 } 7342 } 7343 7344 static bool displayid_is_tiled_block(const struct displayid_iter *iter, 7345 const struct displayid_block *block) 7346 { 7347 return (displayid_version(iter) == DISPLAY_ID_STRUCTURE_VER_12 && 7348 block->tag == DATA_BLOCK_TILED_DISPLAY) || 7349 (displayid_version(iter) == DISPLAY_ID_STRUCTURE_VER_20 && 7350 block->tag == DATA_BLOCK_2_TILED_DISPLAY_TOPOLOGY); 7351 } 7352 7353 static void _drm_update_tile_info(struct drm_connector *connector, 7354 const struct drm_edid *drm_edid) 7355 { 7356 const struct displayid_block *block; 7357 struct displayid_iter iter; 7358 7359 connector->has_tile = false; 7360 7361 displayid_iter_edid_begin(drm_edid, &iter); 7362 displayid_iter_for_each(block, &iter) { 7363 if (displayid_is_tiled_block(&iter, block)) 7364 drm_parse_tiled_block(connector, block); 7365 } 7366 displayid_iter_end(&iter); 7367 7368 if (!connector->has_tile && connector->tile_group) { 7369 drm_mode_put_tile_group(connector->dev, connector->tile_group); 7370 connector->tile_group = NULL; 7371 } 7372 } 7373 7374 /** 7375 * drm_edid_is_digital - is digital? 7376 * @drm_edid: The EDID 7377 * 7378 * Return true if input is digital. 7379 */ 7380 bool drm_edid_is_digital(const struct drm_edid *drm_edid) 7381 { 7382 return drm_edid && drm_edid->edid && 7383 drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL; 7384 } 7385 EXPORT_SYMBOL(drm_edid_is_digital); 7386