1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 31 #include <linux/hdmi.h> 32 #include <linux/i2c.h> 33 #include <linux/kernel.h> 34 #include <linux/module.h> 35 #include <linux/slab.h> 36 #include <linux/vga_switcheroo.h> 37 38 #include <drm/drm_displayid.h> 39 #include <drm/drm_drv.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_encoder.h> 42 #include <drm/drm_print.h> 43 #include <drm/drm_scdc_helper.h> 44 45 #include "drm_crtc_internal.h" 46 47 #define version_greater(edid, maj, min) \ 48 (((edid)->version > (maj)) || \ 49 ((edid)->version == (maj) && (edid)->revision > (min))) 50 51 #define EDID_EST_TIMINGS 16 52 #define EDID_STD_TIMINGS 8 53 #define EDID_DETAILED_TIMINGS 4 54 55 /* 56 * EDID blocks out in the wild have a variety of bugs, try to collect 57 * them here (note that userspace may work around broken monitors first, 58 * but fixes should make their way here so that the kernel "just works" 59 * on as many displays as possible). 60 */ 61 62 /* First detailed mode wrong, use largest 60Hz mode */ 63 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 64 /* Reported 135MHz pixel clock is too high, needs adjustment */ 65 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 66 /* Prefer the largest mode at 75 Hz */ 67 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 68 /* Detail timing is in cm not mm */ 69 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 70 /* Detailed timing descriptors have bogus size values, so just take the 71 * maximum size and use that. 72 */ 73 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 74 /* use +hsync +vsync for detailed mode */ 75 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 76 /* Force reduced-blanking timings for detailed modes */ 77 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 78 /* Force 8bpc */ 79 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 80 /* Force 12bpc */ 81 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 82 /* Force 6bpc */ 83 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 84 /* Force 10bpc */ 85 #define EDID_QUIRK_FORCE_10BPC (1 << 11) 86 /* Non desktop display (i.e. HMD) */ 87 #define EDID_QUIRK_NON_DESKTOP (1 << 12) 88 89 struct detailed_mode_closure { 90 struct drm_connector *connector; 91 struct edid *edid; 92 bool preferred; 93 u32 quirks; 94 int modes; 95 }; 96 97 #define LEVEL_DMT 0 98 #define LEVEL_GTF 1 99 #define LEVEL_GTF2 2 100 #define LEVEL_CVT 3 101 102 static const struct edid_quirk { 103 char vendor[4]; 104 int product_id; 105 u32 quirks; 106 } edid_quirk_list[] = { 107 /* Acer AL1706 */ 108 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 109 /* Acer F51 */ 110 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 111 112 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 113 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 114 115 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */ 116 { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC }, 117 118 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 119 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC }, 120 121 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ 122 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC }, 123 124 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ 125 { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC }, 126 127 /* Belinea 10 15 55 */ 128 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 129 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 130 131 /* Envision Peripherals, Inc. EN-7100e */ 132 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 133 /* Envision EN2028 */ 134 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 135 136 /* Funai Electronics PM36B */ 137 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 138 EDID_QUIRK_DETAILED_IN_CM }, 139 140 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 141 { "LGD", 764, EDID_QUIRK_FORCE_10BPC }, 142 143 /* LG Philips LCD LP154W01-A5 */ 144 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 145 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 146 147 /* Samsung SyncMaster 205BW. Note: irony */ 148 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 149 /* Samsung SyncMaster 22[5-6]BW */ 150 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 151 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 152 153 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 154 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 155 156 /* ViewSonic VA2026w */ 157 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 158 159 /* Medion MD 30217 PG */ 160 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 161 162 /* Lenovo G50 */ 163 { "SDC", 18514, EDID_QUIRK_FORCE_6BPC }, 164 165 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 166 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 167 168 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 169 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, 170 171 /* Valve Index Headset */ 172 { "VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP }, 173 { "VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP }, 174 { "VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP }, 175 { "VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP }, 176 { "VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP }, 177 { "VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP }, 178 { "VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP }, 179 { "VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP }, 180 { "VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP }, 181 { "VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP }, 182 { "VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP }, 183 { "VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP }, 184 { "VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP }, 185 { "VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP }, 186 { "VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP }, 187 { "VLV", 0x91be, EDID_QUIRK_NON_DESKTOP }, 188 { "VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP }, 189 190 /* HTC Vive and Vive Pro VR Headsets */ 191 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP }, 192 { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP }, 193 194 /* Oculus Rift DK1, DK2, and CV1 VR Headsets */ 195 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP }, 196 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP }, 197 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP }, 198 199 /* Windows Mixed Reality Headsets */ 200 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP }, 201 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP }, 202 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP }, 203 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP }, 204 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP }, 205 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP }, 206 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP }, 207 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP }, 208 209 /* Sony PlayStation VR Headset */ 210 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP }, 211 212 /* Sensics VR Headsets */ 213 { "SEN", 0x1019, EDID_QUIRK_NON_DESKTOP }, 214 215 /* OSVR HDK and HDK2 VR Headsets */ 216 { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP }, 217 }; 218 219 /* 220 * Autogenerated from the DMT spec. 221 * This table is copied from xfree86/modes/xf86EdidModes.c. 222 */ 223 static const struct drm_display_mode drm_dmt_modes[] = { 224 /* 0x01 - 640x350@85Hz */ 225 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 226 736, 832, 0, 350, 382, 385, 445, 0, 227 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 228 /* 0x02 - 640x400@85Hz */ 229 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 230 736, 832, 0, 400, 401, 404, 445, 0, 231 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 232 /* 0x03 - 720x400@85Hz */ 233 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 234 828, 936, 0, 400, 401, 404, 446, 0, 235 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 236 /* 0x04 - 640x480@60Hz */ 237 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 238 752, 800, 0, 480, 490, 492, 525, 0, 239 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 240 /* 0x05 - 640x480@72Hz */ 241 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 242 704, 832, 0, 480, 489, 492, 520, 0, 243 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 244 /* 0x06 - 640x480@75Hz */ 245 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 246 720, 840, 0, 480, 481, 484, 500, 0, 247 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 248 /* 0x07 - 640x480@85Hz */ 249 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 250 752, 832, 0, 480, 481, 484, 509, 0, 251 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 252 /* 0x08 - 800x600@56Hz */ 253 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 254 896, 1024, 0, 600, 601, 603, 625, 0, 255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 256 /* 0x09 - 800x600@60Hz */ 257 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 258 968, 1056, 0, 600, 601, 605, 628, 0, 259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 260 /* 0x0a - 800x600@72Hz */ 261 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 262 976, 1040, 0, 600, 637, 643, 666, 0, 263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 264 /* 0x0b - 800x600@75Hz */ 265 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 266 896, 1056, 0, 600, 601, 604, 625, 0, 267 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 268 /* 0x0c - 800x600@85Hz */ 269 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 270 896, 1048, 0, 600, 601, 604, 631, 0, 271 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 272 /* 0x0d - 800x600@120Hz RB */ 273 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 274 880, 960, 0, 600, 603, 607, 636, 0, 275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 276 /* 0x0e - 848x480@60Hz */ 277 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 278 976, 1088, 0, 480, 486, 494, 517, 0, 279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 280 /* 0x0f - 1024x768@43Hz, interlace */ 281 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 282 1208, 1264, 0, 768, 768, 776, 817, 0, 283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 284 DRM_MODE_FLAG_INTERLACE) }, 285 /* 0x10 - 1024x768@60Hz */ 286 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 287 1184, 1344, 0, 768, 771, 777, 806, 0, 288 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 289 /* 0x11 - 1024x768@70Hz */ 290 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 291 1184, 1328, 0, 768, 771, 777, 806, 0, 292 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 293 /* 0x12 - 1024x768@75Hz */ 294 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 295 1136, 1312, 0, 768, 769, 772, 800, 0, 296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 297 /* 0x13 - 1024x768@85Hz */ 298 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 299 1168, 1376, 0, 768, 769, 772, 808, 0, 300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 301 /* 0x14 - 1024x768@120Hz RB */ 302 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 303 1104, 1184, 0, 768, 771, 775, 813, 0, 304 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 305 /* 0x15 - 1152x864@75Hz */ 306 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 307 1344, 1600, 0, 864, 865, 868, 900, 0, 308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 309 /* 0x55 - 1280x720@60Hz */ 310 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 311 1430, 1650, 0, 720, 725, 730, 750, 0, 312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 313 /* 0x16 - 1280x768@60Hz RB */ 314 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 315 1360, 1440, 0, 768, 771, 778, 790, 0, 316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 317 /* 0x17 - 1280x768@60Hz */ 318 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 319 1472, 1664, 0, 768, 771, 778, 798, 0, 320 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 321 /* 0x18 - 1280x768@75Hz */ 322 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 323 1488, 1696, 0, 768, 771, 778, 805, 0, 324 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 325 /* 0x19 - 1280x768@85Hz */ 326 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 327 1496, 1712, 0, 768, 771, 778, 809, 0, 328 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 329 /* 0x1a - 1280x768@120Hz RB */ 330 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 331 1360, 1440, 0, 768, 771, 778, 813, 0, 332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 333 /* 0x1b - 1280x800@60Hz RB */ 334 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 335 1360, 1440, 0, 800, 803, 809, 823, 0, 336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 337 /* 0x1c - 1280x800@60Hz */ 338 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 339 1480, 1680, 0, 800, 803, 809, 831, 0, 340 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 341 /* 0x1d - 1280x800@75Hz */ 342 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 343 1488, 1696, 0, 800, 803, 809, 838, 0, 344 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 345 /* 0x1e - 1280x800@85Hz */ 346 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 347 1496, 1712, 0, 800, 803, 809, 843, 0, 348 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 349 /* 0x1f - 1280x800@120Hz RB */ 350 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 351 1360, 1440, 0, 800, 803, 809, 847, 0, 352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 353 /* 0x20 - 1280x960@60Hz */ 354 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 355 1488, 1800, 0, 960, 961, 964, 1000, 0, 356 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 357 /* 0x21 - 1280x960@85Hz */ 358 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 359 1504, 1728, 0, 960, 961, 964, 1011, 0, 360 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 361 /* 0x22 - 1280x960@120Hz RB */ 362 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 363 1360, 1440, 0, 960, 963, 967, 1017, 0, 364 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 365 /* 0x23 - 1280x1024@60Hz */ 366 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 367 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 369 /* 0x24 - 1280x1024@75Hz */ 370 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 371 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 373 /* 0x25 - 1280x1024@85Hz */ 374 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 375 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 377 /* 0x26 - 1280x1024@120Hz RB */ 378 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 379 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 381 /* 0x27 - 1360x768@60Hz */ 382 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 383 1536, 1792, 0, 768, 771, 777, 795, 0, 384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 385 /* 0x28 - 1360x768@120Hz RB */ 386 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 387 1440, 1520, 0, 768, 771, 776, 813, 0, 388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 389 /* 0x51 - 1366x768@60Hz */ 390 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 391 1579, 1792, 0, 768, 771, 774, 798, 0, 392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 393 /* 0x56 - 1366x768@60Hz */ 394 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 395 1436, 1500, 0, 768, 769, 772, 800, 0, 396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 397 /* 0x29 - 1400x1050@60Hz RB */ 398 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 399 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 401 /* 0x2a - 1400x1050@60Hz */ 402 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 403 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 404 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 405 /* 0x2b - 1400x1050@75Hz */ 406 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 407 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 408 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 409 /* 0x2c - 1400x1050@85Hz */ 410 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 411 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 412 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 413 /* 0x2d - 1400x1050@120Hz RB */ 414 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 415 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 417 /* 0x2e - 1440x900@60Hz RB */ 418 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 419 1520, 1600, 0, 900, 903, 909, 926, 0, 420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 421 /* 0x2f - 1440x900@60Hz */ 422 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 423 1672, 1904, 0, 900, 903, 909, 934, 0, 424 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 425 /* 0x30 - 1440x900@75Hz */ 426 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 427 1688, 1936, 0, 900, 903, 909, 942, 0, 428 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 429 /* 0x31 - 1440x900@85Hz */ 430 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 431 1696, 1952, 0, 900, 903, 909, 948, 0, 432 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 433 /* 0x32 - 1440x900@120Hz RB */ 434 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 435 1520, 1600, 0, 900, 903, 909, 953, 0, 436 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 437 /* 0x53 - 1600x900@60Hz */ 438 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 439 1704, 1800, 0, 900, 901, 904, 1000, 0, 440 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 441 /* 0x33 - 1600x1200@60Hz */ 442 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 443 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 444 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 445 /* 0x34 - 1600x1200@65Hz */ 446 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 447 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 448 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 449 /* 0x35 - 1600x1200@70Hz */ 450 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 451 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 452 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 453 /* 0x36 - 1600x1200@75Hz */ 454 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 455 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 457 /* 0x37 - 1600x1200@85Hz */ 458 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 459 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 461 /* 0x38 - 1600x1200@120Hz RB */ 462 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 463 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 464 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 465 /* 0x39 - 1680x1050@60Hz RB */ 466 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 467 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 469 /* 0x3a - 1680x1050@60Hz */ 470 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 471 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 472 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 473 /* 0x3b - 1680x1050@75Hz */ 474 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 475 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 476 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 477 /* 0x3c - 1680x1050@85Hz */ 478 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 479 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 480 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 481 /* 0x3d - 1680x1050@120Hz RB */ 482 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 483 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 485 /* 0x3e - 1792x1344@60Hz */ 486 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 487 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 488 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 489 /* 0x3f - 1792x1344@75Hz */ 490 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 491 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 492 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 493 /* 0x40 - 1792x1344@120Hz RB */ 494 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 495 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 497 /* 0x41 - 1856x1392@60Hz */ 498 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 499 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 500 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 501 /* 0x42 - 1856x1392@75Hz */ 502 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 503 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 504 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 505 /* 0x43 - 1856x1392@120Hz RB */ 506 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 507 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 508 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 509 /* 0x52 - 1920x1080@60Hz */ 510 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 511 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 512 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 513 /* 0x44 - 1920x1200@60Hz RB */ 514 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 515 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 517 /* 0x45 - 1920x1200@60Hz */ 518 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 519 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 520 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 521 /* 0x46 - 1920x1200@75Hz */ 522 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 523 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 524 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 525 /* 0x47 - 1920x1200@85Hz */ 526 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 527 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 528 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 529 /* 0x48 - 1920x1200@120Hz RB */ 530 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 531 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 532 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 533 /* 0x49 - 1920x1440@60Hz */ 534 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 535 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 536 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 537 /* 0x4a - 1920x1440@75Hz */ 538 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 539 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 540 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 541 /* 0x4b - 1920x1440@120Hz RB */ 542 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 543 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 544 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 545 /* 0x54 - 2048x1152@60Hz */ 546 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 547 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 548 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 549 /* 0x4c - 2560x1600@60Hz RB */ 550 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 551 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 553 /* 0x4d - 2560x1600@60Hz */ 554 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 555 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 556 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 557 /* 0x4e - 2560x1600@75Hz */ 558 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 559 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 560 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 561 /* 0x4f - 2560x1600@85Hz */ 562 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 563 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 564 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 565 /* 0x50 - 2560x1600@120Hz RB */ 566 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 567 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 568 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 569 /* 0x57 - 4096x2160@60Hz RB */ 570 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 571 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 572 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 573 /* 0x58 - 4096x2160@59.94Hz RB */ 574 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 575 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 576 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 577 }; 578 579 /* 580 * These more or less come from the DMT spec. The 720x400 modes are 581 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 582 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 583 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 584 * mode. 585 * 586 * The DMT modes have been fact-checked; the rest are mild guesses. 587 */ 588 static const struct drm_display_mode edid_est_modes[] = { 589 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 590 968, 1056, 0, 600, 601, 605, 628, 0, 591 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 592 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 593 896, 1024, 0, 600, 601, 603, 625, 0, 594 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 595 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 596 720, 840, 0, 480, 481, 484, 500, 0, 597 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 598 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 599 704, 832, 0, 480, 489, 492, 520, 0, 600 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 601 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 602 768, 864, 0, 480, 483, 486, 525, 0, 603 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 604 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 605 752, 800, 0, 480, 490, 492, 525, 0, 606 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 607 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 608 846, 900, 0, 400, 421, 423, 449, 0, 609 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 610 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 611 846, 900, 0, 400, 412, 414, 449, 0, 612 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 613 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 614 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 615 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 616 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 617 1136, 1312, 0, 768, 769, 772, 800, 0, 618 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 619 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 620 1184, 1328, 0, 768, 771, 777, 806, 0, 621 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 622 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 623 1184, 1344, 0, 768, 771, 777, 806, 0, 624 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 625 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 626 1208, 1264, 0, 768, 768, 776, 817, 0, 627 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 628 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 629 928, 1152, 0, 624, 625, 628, 667, 0, 630 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 631 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 632 896, 1056, 0, 600, 601, 604, 625, 0, 633 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 634 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 635 976, 1040, 0, 600, 637, 643, 666, 0, 636 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 637 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 638 1344, 1600, 0, 864, 865, 868, 900, 0, 639 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 640 }; 641 642 struct minimode { 643 short w; 644 short h; 645 short r; 646 short rb; 647 }; 648 649 static const struct minimode est3_modes[] = { 650 /* byte 6 */ 651 { 640, 350, 85, 0 }, 652 { 640, 400, 85, 0 }, 653 { 720, 400, 85, 0 }, 654 { 640, 480, 85, 0 }, 655 { 848, 480, 60, 0 }, 656 { 800, 600, 85, 0 }, 657 { 1024, 768, 85, 0 }, 658 { 1152, 864, 75, 0 }, 659 /* byte 7 */ 660 { 1280, 768, 60, 1 }, 661 { 1280, 768, 60, 0 }, 662 { 1280, 768, 75, 0 }, 663 { 1280, 768, 85, 0 }, 664 { 1280, 960, 60, 0 }, 665 { 1280, 960, 85, 0 }, 666 { 1280, 1024, 60, 0 }, 667 { 1280, 1024, 85, 0 }, 668 /* byte 8 */ 669 { 1360, 768, 60, 0 }, 670 { 1440, 900, 60, 1 }, 671 { 1440, 900, 60, 0 }, 672 { 1440, 900, 75, 0 }, 673 { 1440, 900, 85, 0 }, 674 { 1400, 1050, 60, 1 }, 675 { 1400, 1050, 60, 0 }, 676 { 1400, 1050, 75, 0 }, 677 /* byte 9 */ 678 { 1400, 1050, 85, 0 }, 679 { 1680, 1050, 60, 1 }, 680 { 1680, 1050, 60, 0 }, 681 { 1680, 1050, 75, 0 }, 682 { 1680, 1050, 85, 0 }, 683 { 1600, 1200, 60, 0 }, 684 { 1600, 1200, 65, 0 }, 685 { 1600, 1200, 70, 0 }, 686 /* byte 10 */ 687 { 1600, 1200, 75, 0 }, 688 { 1600, 1200, 85, 0 }, 689 { 1792, 1344, 60, 0 }, 690 { 1792, 1344, 75, 0 }, 691 { 1856, 1392, 60, 0 }, 692 { 1856, 1392, 75, 0 }, 693 { 1920, 1200, 60, 1 }, 694 { 1920, 1200, 60, 0 }, 695 /* byte 11 */ 696 { 1920, 1200, 75, 0 }, 697 { 1920, 1200, 85, 0 }, 698 { 1920, 1440, 60, 0 }, 699 { 1920, 1440, 75, 0 }, 700 }; 701 702 static const struct minimode extra_modes[] = { 703 { 1024, 576, 60, 0 }, 704 { 1366, 768, 60, 0 }, 705 { 1600, 900, 60, 0 }, 706 { 1680, 945, 60, 0 }, 707 { 1920, 1080, 60, 0 }, 708 { 2048, 1152, 60, 0 }, 709 { 2048, 1536, 60, 0 }, 710 }; 711 712 /* 713 * Probably taken from CEA-861 spec. 714 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. 715 * 716 * Index using the VIC. 717 */ 718 static const struct drm_display_mode edid_cea_modes[] = { 719 /* 0 - dummy, VICs start at 1 */ 720 { }, 721 /* 1 - 640x480@60Hz 4:3 */ 722 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 723 752, 800, 0, 480, 490, 492, 525, 0, 724 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 725 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 726 /* 2 - 720x480@60Hz 4:3 */ 727 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 728 798, 858, 0, 480, 489, 495, 525, 0, 729 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 730 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 731 /* 3 - 720x480@60Hz 16:9 */ 732 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 733 798, 858, 0, 480, 489, 495, 525, 0, 734 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 735 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 736 /* 4 - 1280x720@60Hz 16:9 */ 737 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 738 1430, 1650, 0, 720, 725, 730, 750, 0, 739 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 740 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 741 /* 5 - 1920x1080i@60Hz 16:9 */ 742 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 743 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 744 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 745 DRM_MODE_FLAG_INTERLACE), 746 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 747 /* 6 - 720(1440)x480i@60Hz 4:3 */ 748 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 749 801, 858, 0, 480, 488, 494, 525, 0, 750 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 751 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 752 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 753 /* 7 - 720(1440)x480i@60Hz 16:9 */ 754 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 755 801, 858, 0, 480, 488, 494, 525, 0, 756 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 757 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 758 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 759 /* 8 - 720(1440)x240@60Hz 4:3 */ 760 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 761 801, 858, 0, 240, 244, 247, 262, 0, 762 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 763 DRM_MODE_FLAG_DBLCLK), 764 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 765 /* 9 - 720(1440)x240@60Hz 16:9 */ 766 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 767 801, 858, 0, 240, 244, 247, 262, 0, 768 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 769 DRM_MODE_FLAG_DBLCLK), 770 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 771 /* 10 - 2880x480i@60Hz 4:3 */ 772 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 773 3204, 3432, 0, 480, 488, 494, 525, 0, 774 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 775 DRM_MODE_FLAG_INTERLACE), 776 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 777 /* 11 - 2880x480i@60Hz 16:9 */ 778 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 779 3204, 3432, 0, 480, 488, 494, 525, 0, 780 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 781 DRM_MODE_FLAG_INTERLACE), 782 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 783 /* 12 - 2880x240@60Hz 4:3 */ 784 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 785 3204, 3432, 0, 240, 244, 247, 262, 0, 786 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 787 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 788 /* 13 - 2880x240@60Hz 16:9 */ 789 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 790 3204, 3432, 0, 240, 244, 247, 262, 0, 791 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 792 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 793 /* 14 - 1440x480@60Hz 4:3 */ 794 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 795 1596, 1716, 0, 480, 489, 495, 525, 0, 796 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 797 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 798 /* 15 - 1440x480@60Hz 16:9 */ 799 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 800 1596, 1716, 0, 480, 489, 495, 525, 0, 801 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 802 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 803 /* 16 - 1920x1080@60Hz 16:9 */ 804 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 805 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 806 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 807 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 808 /* 17 - 720x576@50Hz 4:3 */ 809 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 810 796, 864, 0, 576, 581, 586, 625, 0, 811 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 812 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 813 /* 18 - 720x576@50Hz 16:9 */ 814 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 815 796, 864, 0, 576, 581, 586, 625, 0, 816 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 817 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 818 /* 19 - 1280x720@50Hz 16:9 */ 819 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 820 1760, 1980, 0, 720, 725, 730, 750, 0, 821 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 822 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 823 /* 20 - 1920x1080i@50Hz 16:9 */ 824 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 825 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 826 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 827 DRM_MODE_FLAG_INTERLACE), 828 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 829 /* 21 - 720(1440)x576i@50Hz 4:3 */ 830 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 831 795, 864, 0, 576, 580, 586, 625, 0, 832 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 833 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 834 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 835 /* 22 - 720(1440)x576i@50Hz 16:9 */ 836 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 837 795, 864, 0, 576, 580, 586, 625, 0, 838 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 839 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 840 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 841 /* 23 - 720(1440)x288@50Hz 4:3 */ 842 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 843 795, 864, 0, 288, 290, 293, 312, 0, 844 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 845 DRM_MODE_FLAG_DBLCLK), 846 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 847 /* 24 - 720(1440)x288@50Hz 16:9 */ 848 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 849 795, 864, 0, 288, 290, 293, 312, 0, 850 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 851 DRM_MODE_FLAG_DBLCLK), 852 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 853 /* 25 - 2880x576i@50Hz 4:3 */ 854 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 855 3180, 3456, 0, 576, 580, 586, 625, 0, 856 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 857 DRM_MODE_FLAG_INTERLACE), 858 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 859 /* 26 - 2880x576i@50Hz 16:9 */ 860 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 861 3180, 3456, 0, 576, 580, 586, 625, 0, 862 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 863 DRM_MODE_FLAG_INTERLACE), 864 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 865 /* 27 - 2880x288@50Hz 4:3 */ 866 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 867 3180, 3456, 0, 288, 290, 293, 312, 0, 868 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 869 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 870 /* 28 - 2880x288@50Hz 16:9 */ 871 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 872 3180, 3456, 0, 288, 290, 293, 312, 0, 873 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 874 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 875 /* 29 - 1440x576@50Hz 4:3 */ 876 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 877 1592, 1728, 0, 576, 581, 586, 625, 0, 878 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 879 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 880 /* 30 - 1440x576@50Hz 16:9 */ 881 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 882 1592, 1728, 0, 576, 581, 586, 625, 0, 883 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 884 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 885 /* 31 - 1920x1080@50Hz 16:9 */ 886 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 887 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 888 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 889 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 890 /* 32 - 1920x1080@24Hz 16:9 */ 891 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 892 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 893 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 894 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 895 /* 33 - 1920x1080@25Hz 16:9 */ 896 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 897 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 898 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 899 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 900 /* 34 - 1920x1080@30Hz 16:9 */ 901 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 902 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 903 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 904 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 905 /* 35 - 2880x480@60Hz 4:3 */ 906 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 907 3192, 3432, 0, 480, 489, 495, 525, 0, 908 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 909 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 910 /* 36 - 2880x480@60Hz 16:9 */ 911 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 912 3192, 3432, 0, 480, 489, 495, 525, 0, 913 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 914 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 915 /* 37 - 2880x576@50Hz 4:3 */ 916 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 917 3184, 3456, 0, 576, 581, 586, 625, 0, 918 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 919 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 920 /* 38 - 2880x576@50Hz 16:9 */ 921 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 922 3184, 3456, 0, 576, 581, 586, 625, 0, 923 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 924 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 925 /* 39 - 1920x1080i@50Hz 16:9 */ 926 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 927 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 928 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 929 DRM_MODE_FLAG_INTERLACE), 930 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 931 /* 40 - 1920x1080i@100Hz 16:9 */ 932 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 933 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 934 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 935 DRM_MODE_FLAG_INTERLACE), 936 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 937 /* 41 - 1280x720@100Hz 16:9 */ 938 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 939 1760, 1980, 0, 720, 725, 730, 750, 0, 940 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 941 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 942 /* 42 - 720x576@100Hz 4:3 */ 943 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 944 796, 864, 0, 576, 581, 586, 625, 0, 945 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 946 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 947 /* 43 - 720x576@100Hz 16:9 */ 948 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 949 796, 864, 0, 576, 581, 586, 625, 0, 950 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 951 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 952 /* 44 - 720(1440)x576i@100Hz 4:3 */ 953 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 954 795, 864, 0, 576, 580, 586, 625, 0, 955 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 956 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 957 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 958 /* 45 - 720(1440)x576i@100Hz 16:9 */ 959 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 960 795, 864, 0, 576, 580, 586, 625, 0, 961 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 962 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 963 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 964 /* 46 - 1920x1080i@120Hz 16:9 */ 965 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 966 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 967 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 968 DRM_MODE_FLAG_INTERLACE), 969 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 970 /* 47 - 1280x720@120Hz 16:9 */ 971 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 972 1430, 1650, 0, 720, 725, 730, 750, 0, 973 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 974 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 975 /* 48 - 720x480@120Hz 4:3 */ 976 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 977 798, 858, 0, 480, 489, 495, 525, 0, 978 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 979 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 980 /* 49 - 720x480@120Hz 16:9 */ 981 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 982 798, 858, 0, 480, 489, 495, 525, 0, 983 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 984 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 985 /* 50 - 720(1440)x480i@120Hz 4:3 */ 986 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 987 801, 858, 0, 480, 488, 494, 525, 0, 988 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 989 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 990 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 991 /* 51 - 720(1440)x480i@120Hz 16:9 */ 992 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 993 801, 858, 0, 480, 488, 494, 525, 0, 994 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 995 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 996 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 997 /* 52 - 720x576@200Hz 4:3 */ 998 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 999 796, 864, 0, 576, 581, 586, 625, 0, 1000 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1001 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1002 /* 53 - 720x576@200Hz 16:9 */ 1003 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1004 796, 864, 0, 576, 581, 586, 625, 0, 1005 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1006 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1007 /* 54 - 720(1440)x576i@200Hz 4:3 */ 1008 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1009 795, 864, 0, 576, 580, 586, 625, 0, 1010 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1011 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1012 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1013 /* 55 - 720(1440)x576i@200Hz 16:9 */ 1014 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1015 795, 864, 0, 576, 580, 586, 625, 0, 1016 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1017 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1018 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1019 /* 56 - 720x480@240Hz 4:3 */ 1020 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1021 798, 858, 0, 480, 489, 495, 525, 0, 1022 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1023 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1024 /* 57 - 720x480@240Hz 16:9 */ 1025 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1026 798, 858, 0, 480, 489, 495, 525, 0, 1027 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1028 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1029 /* 58 - 720(1440)x480i@240Hz 4:3 */ 1030 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1031 801, 858, 0, 480, 488, 494, 525, 0, 1032 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1033 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1034 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1035 /* 59 - 720(1440)x480i@240Hz 16:9 */ 1036 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1037 801, 858, 0, 480, 488, 494, 525, 0, 1038 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1039 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1040 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1041 /* 60 - 1280x720@24Hz 16:9 */ 1042 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1043 3080, 3300, 0, 720, 725, 730, 750, 0, 1044 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1045 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1046 /* 61 - 1280x720@25Hz 16:9 */ 1047 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1048 3740, 3960, 0, 720, 725, 730, 750, 0, 1049 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1050 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1051 /* 62 - 1280x720@30Hz 16:9 */ 1052 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1053 3080, 3300, 0, 720, 725, 730, 750, 0, 1054 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1055 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1056 /* 63 - 1920x1080@120Hz 16:9 */ 1057 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1058 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1059 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1060 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1061 /* 64 - 1920x1080@100Hz 16:9 */ 1062 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1063 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1064 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1065 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1066 /* 65 - 1280x720@24Hz 64:27 */ 1067 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1068 3080, 3300, 0, 720, 725, 730, 750, 0, 1069 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1070 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1071 /* 66 - 1280x720@25Hz 64:27 */ 1072 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1073 3740, 3960, 0, 720, 725, 730, 750, 0, 1074 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1075 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1076 /* 67 - 1280x720@30Hz 64:27 */ 1077 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1078 3080, 3300, 0, 720, 725, 730, 750, 0, 1079 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1080 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1081 /* 68 - 1280x720@50Hz 64:27 */ 1082 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1083 1760, 1980, 0, 720, 725, 730, 750, 0, 1084 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1085 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1086 /* 69 - 1280x720@60Hz 64:27 */ 1087 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1088 1430, 1650, 0, 720, 725, 730, 750, 0, 1089 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1090 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1091 /* 70 - 1280x720@100Hz 64:27 */ 1092 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1093 1760, 1980, 0, 720, 725, 730, 750, 0, 1094 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1095 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1096 /* 71 - 1280x720@120Hz 64:27 */ 1097 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1098 1430, 1650, 0, 720, 725, 730, 750, 0, 1099 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1100 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1101 /* 72 - 1920x1080@24Hz 64:27 */ 1102 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1103 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1104 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1105 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1106 /* 73 - 1920x1080@25Hz 64:27 */ 1107 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1108 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1109 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1110 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1111 /* 74 - 1920x1080@30Hz 64:27 */ 1112 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1113 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1114 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1115 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1116 /* 75 - 1920x1080@50Hz 64:27 */ 1117 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1118 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1119 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1120 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1121 /* 76 - 1920x1080@60Hz 64:27 */ 1122 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1123 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1124 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1125 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1126 /* 77 - 1920x1080@100Hz 64:27 */ 1127 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1128 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1129 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1130 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1131 /* 78 - 1920x1080@120Hz 64:27 */ 1132 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1133 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1134 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1135 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1136 /* 79 - 1680x720@24Hz 64:27 */ 1137 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 1138 3080, 3300, 0, 720, 725, 730, 750, 0, 1139 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1140 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1141 /* 80 - 1680x720@25Hz 64:27 */ 1142 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 1143 2948, 3168, 0, 720, 725, 730, 750, 0, 1144 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1145 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1146 /* 81 - 1680x720@30Hz 64:27 */ 1147 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 1148 2420, 2640, 0, 720, 725, 730, 750, 0, 1149 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1150 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1151 /* 82 - 1680x720@50Hz 64:27 */ 1152 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1153 1980, 2200, 0, 720, 725, 730, 750, 0, 1154 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1155 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1156 /* 83 - 1680x720@60Hz 64:27 */ 1157 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1158 1980, 2200, 0, 720, 725, 730, 750, 0, 1159 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1160 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1161 /* 84 - 1680x720@100Hz 64:27 */ 1162 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1163 1780, 2000, 0, 720, 725, 730, 825, 0, 1164 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1165 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1166 /* 85 - 1680x720@120Hz 64:27 */ 1167 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1168 1780, 2000, 0, 720, 725, 730, 825, 0, 1169 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1170 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1171 /* 86 - 2560x1080@24Hz 64:27 */ 1172 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 1173 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1174 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1175 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1176 /* 87 - 2560x1080@25Hz 64:27 */ 1177 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 1178 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, 1179 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1180 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1181 /* 88 - 2560x1080@30Hz 64:27 */ 1182 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 1183 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, 1184 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1185 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1186 /* 89 - 2560x1080@50Hz 64:27 */ 1187 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 1188 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, 1189 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1190 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1191 /* 90 - 2560x1080@60Hz 64:27 */ 1192 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 1193 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, 1194 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1195 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1196 /* 91 - 2560x1080@100Hz 64:27 */ 1197 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 1198 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, 1199 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1200 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1201 /* 92 - 2560x1080@120Hz 64:27 */ 1202 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 1203 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, 1204 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1205 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1206 /* 93 - 3840x2160@24Hz 16:9 */ 1207 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1208 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1209 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1210 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1211 /* 94 - 3840x2160@25Hz 16:9 */ 1212 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1213 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1214 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1215 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1216 /* 95 - 3840x2160@30Hz 16:9 */ 1217 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1218 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1219 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1220 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1221 /* 96 - 3840x2160@50Hz 16:9 */ 1222 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1223 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1224 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1225 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1226 /* 97 - 3840x2160@60Hz 16:9 */ 1227 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1228 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1229 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1230 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1231 /* 98 - 4096x2160@24Hz 256:135 */ 1232 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1233 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1234 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1235 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1236 /* 99 - 4096x2160@25Hz 256:135 */ 1237 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1238 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1239 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1240 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1241 /* 100 - 4096x2160@30Hz 256:135 */ 1242 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1243 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1245 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1246 /* 101 - 4096x2160@50Hz 256:135 */ 1247 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1248 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1249 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1250 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1251 /* 102 - 4096x2160@60Hz 256:135 */ 1252 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1253 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1254 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1255 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1256 /* 103 - 3840x2160@24Hz 64:27 */ 1257 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1258 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1260 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1261 /* 104 - 3840x2160@25Hz 64:27 */ 1262 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1263 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1265 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1266 /* 105 - 3840x2160@30Hz 64:27 */ 1267 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1268 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1269 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1270 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1271 /* 106 - 3840x2160@50Hz 64:27 */ 1272 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1273 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1274 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1275 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1276 /* 107 - 3840x2160@60Hz 64:27 */ 1277 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1278 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1280 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1281 }; 1282 1283 /* 1284 * HDMI 1.4 4k modes. Index using the VIC. 1285 */ 1286 static const struct drm_display_mode edid_4k_modes[] = { 1287 /* 0 - dummy, VICs start at 1 */ 1288 { }, 1289 /* 1 - 3840x2160@30Hz */ 1290 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1291 3840, 4016, 4104, 4400, 0, 1292 2160, 2168, 2178, 2250, 0, 1293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1294 .vrefresh = 30, }, 1295 /* 2 - 3840x2160@25Hz */ 1296 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1297 3840, 4896, 4984, 5280, 0, 1298 2160, 2168, 2178, 2250, 0, 1299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1300 .vrefresh = 25, }, 1301 /* 3 - 3840x2160@24Hz */ 1302 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1303 3840, 5116, 5204, 5500, 0, 1304 2160, 2168, 2178, 2250, 0, 1305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1306 .vrefresh = 24, }, 1307 /* 4 - 4096x2160@24Hz (SMPTE) */ 1308 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1309 4096, 5116, 5204, 5500, 0, 1310 2160, 2168, 2178, 2250, 0, 1311 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1312 .vrefresh = 24, }, 1313 }; 1314 1315 /*** DDC fetch and block validation ***/ 1316 1317 static const u8 edid_header[] = { 1318 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1319 }; 1320 1321 /** 1322 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1323 * @raw_edid: pointer to raw base EDID block 1324 * 1325 * Sanity check the header of the base EDID block. 1326 * 1327 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1328 */ 1329 int drm_edid_header_is_valid(const u8 *raw_edid) 1330 { 1331 int i, score = 0; 1332 1333 for (i = 0; i < sizeof(edid_header); i++) 1334 if (raw_edid[i] == edid_header[i]) 1335 score++; 1336 1337 return score; 1338 } 1339 EXPORT_SYMBOL(drm_edid_header_is_valid); 1340 1341 static int edid_fixup __read_mostly = 6; 1342 module_param_named(edid_fixup, edid_fixup, int, 0400); 1343 MODULE_PARM_DESC(edid_fixup, 1344 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1345 1346 static void drm_get_displayid(struct drm_connector *connector, 1347 struct edid *edid); 1348 static int validate_displayid(u8 *displayid, int length, int idx); 1349 1350 static int drm_edid_block_checksum(const u8 *raw_edid) 1351 { 1352 int i; 1353 u8 csum = 0; 1354 for (i = 0; i < EDID_LENGTH; i++) 1355 csum += raw_edid[i]; 1356 1357 return csum; 1358 } 1359 1360 static bool drm_edid_is_zero(const u8 *in_edid, int length) 1361 { 1362 if (memchr_inv(in_edid, 0, length)) 1363 return false; 1364 1365 return true; 1366 } 1367 1368 /** 1369 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1370 * @raw_edid: pointer to raw EDID block 1371 * @block: type of block to validate (0 for base, extension otherwise) 1372 * @print_bad_edid: if true, dump bad EDID blocks to the console 1373 * @edid_corrupt: if true, the header or checksum is invalid 1374 * 1375 * Validate a base or extension EDID block and optionally dump bad blocks to 1376 * the console. 1377 * 1378 * Return: True if the block is valid, false otherwise. 1379 */ 1380 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 1381 bool *edid_corrupt) 1382 { 1383 u8 csum; 1384 struct edid *edid = (struct edid *)raw_edid; 1385 1386 if (WARN_ON(!raw_edid)) 1387 return false; 1388 1389 if (edid_fixup > 8 || edid_fixup < 0) 1390 edid_fixup = 6; 1391 1392 if (block == 0) { 1393 int score = drm_edid_header_is_valid(raw_edid); 1394 if (score == 8) { 1395 if (edid_corrupt) 1396 *edid_corrupt = false; 1397 } else if (score >= edid_fixup) { 1398 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 1399 * The corrupt flag needs to be set here otherwise, the 1400 * fix-up code here will correct the problem, the 1401 * checksum is correct and the test fails 1402 */ 1403 if (edid_corrupt) 1404 *edid_corrupt = true; 1405 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1406 memcpy(raw_edid, edid_header, sizeof(edid_header)); 1407 } else { 1408 if (edid_corrupt) 1409 *edid_corrupt = true; 1410 goto bad; 1411 } 1412 } 1413 1414 csum = drm_edid_block_checksum(raw_edid); 1415 if (csum) { 1416 if (edid_corrupt) 1417 *edid_corrupt = true; 1418 1419 /* allow CEA to slide through, switches mangle this */ 1420 if (raw_edid[0] == CEA_EXT) { 1421 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum); 1422 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n"); 1423 } else { 1424 if (print_bad_edid) 1425 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum); 1426 1427 goto bad; 1428 } 1429 } 1430 1431 /* per-block-type checks */ 1432 switch (raw_edid[0]) { 1433 case 0: /* base */ 1434 if (edid->version != 1) { 1435 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version); 1436 goto bad; 1437 } 1438 1439 if (edid->revision > 4) 1440 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1441 break; 1442 1443 default: 1444 break; 1445 } 1446 1447 return true; 1448 1449 bad: 1450 if (print_bad_edid) { 1451 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) { 1452 pr_notice("EDID block is all zeroes\n"); 1453 } else { 1454 pr_notice("Raw EDID:\n"); 1455 print_hex_dump(KERN_NOTICE, 1456 " \t", DUMP_PREFIX_NONE, 16, 1, 1457 raw_edid, EDID_LENGTH, false); 1458 } 1459 } 1460 return false; 1461 } 1462 EXPORT_SYMBOL(drm_edid_block_valid); 1463 1464 /** 1465 * drm_edid_is_valid - sanity check EDID data 1466 * @edid: EDID data 1467 * 1468 * Sanity-check an entire EDID record (including extensions) 1469 * 1470 * Return: True if the EDID data is valid, false otherwise. 1471 */ 1472 bool drm_edid_is_valid(struct edid *edid) 1473 { 1474 int i; 1475 u8 *raw = (u8 *)edid; 1476 1477 if (!edid) 1478 return false; 1479 1480 for (i = 0; i <= edid->extensions; i++) 1481 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL)) 1482 return false; 1483 1484 return true; 1485 } 1486 EXPORT_SYMBOL(drm_edid_is_valid); 1487 1488 #define DDC_SEGMENT_ADDR 0x30 1489 /** 1490 * drm_do_probe_ddc_edid() - get EDID information via I2C 1491 * @data: I2C device adapter 1492 * @buf: EDID data buffer to be filled 1493 * @block: 128 byte EDID block to start fetching from 1494 * @len: EDID data buffer length to fetch 1495 * 1496 * Try to fetch EDID information by calling I2C driver functions. 1497 * 1498 * Return: 0 on success or -1 on failure. 1499 */ 1500 static int 1501 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 1502 { 1503 struct i2c_adapter *adapter = data; 1504 unsigned char start = block * EDID_LENGTH; 1505 unsigned char segment = block >> 1; 1506 unsigned char xfers = segment ? 3 : 2; 1507 int ret, retries = 5; 1508 1509 /* 1510 * The core I2C driver will automatically retry the transfer if the 1511 * adapter reports EAGAIN. However, we find that bit-banging transfers 1512 * are susceptible to errors under a heavily loaded machine and 1513 * generate spurious NAKs and timeouts. Retrying the transfer 1514 * of the individual block a few times seems to overcome this. 1515 */ 1516 do { 1517 struct i2c_msg msgs[] = { 1518 { 1519 .addr = DDC_SEGMENT_ADDR, 1520 .flags = 0, 1521 .len = 1, 1522 .buf = &segment, 1523 }, { 1524 .addr = DDC_ADDR, 1525 .flags = 0, 1526 .len = 1, 1527 .buf = &start, 1528 }, { 1529 .addr = DDC_ADDR, 1530 .flags = I2C_M_RD, 1531 .len = len, 1532 .buf = buf, 1533 } 1534 }; 1535 1536 /* 1537 * Avoid sending the segment addr to not upset non-compliant 1538 * DDC monitors. 1539 */ 1540 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 1541 1542 if (ret == -ENXIO) { 1543 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 1544 adapter->name); 1545 break; 1546 } 1547 } while (ret != xfers && --retries); 1548 1549 return ret == xfers ? 0 : -1; 1550 } 1551 1552 static void connector_bad_edid(struct drm_connector *connector, 1553 u8 *edid, int num_blocks) 1554 { 1555 int i; 1556 1557 if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS)) 1558 return; 1559 1560 dev_warn(connector->dev->dev, 1561 "%s: EDID is invalid:\n", 1562 connector->name); 1563 for (i = 0; i < num_blocks; i++) { 1564 u8 *block = edid + i * EDID_LENGTH; 1565 char prefix[20]; 1566 1567 if (drm_edid_is_zero(block, EDID_LENGTH)) 1568 sprintf(prefix, "\t[%02x] ZERO ", i); 1569 else if (!drm_edid_block_valid(block, i, false, NULL)) 1570 sprintf(prefix, "\t[%02x] BAD ", i); 1571 else 1572 sprintf(prefix, "\t[%02x] GOOD ", i); 1573 1574 print_hex_dump(KERN_WARNING, 1575 prefix, DUMP_PREFIX_NONE, 16, 1, 1576 block, EDID_LENGTH, false); 1577 } 1578 } 1579 1580 /* Get override or firmware EDID */ 1581 static struct edid *drm_get_override_edid(struct drm_connector *connector) 1582 { 1583 struct edid *override = NULL; 1584 1585 if (connector->override_edid) 1586 override = drm_edid_duplicate(connector->edid_blob_ptr->data); 1587 1588 if (!override) 1589 override = drm_load_edid_firmware(connector); 1590 1591 return IS_ERR(override) ? NULL : override; 1592 } 1593 1594 /** 1595 * drm_add_override_edid_modes - add modes from override/firmware EDID 1596 * @connector: connector we're probing 1597 * 1598 * Add modes from the override/firmware EDID, if available. Only to be used from 1599 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe 1600 * failed during drm_get_edid() and caused the override/firmware EDID to be 1601 * skipped. 1602 * 1603 * Return: The number of modes added or 0 if we couldn't find any. 1604 */ 1605 int drm_add_override_edid_modes(struct drm_connector *connector) 1606 { 1607 struct edid *override; 1608 int num_modes = 0; 1609 1610 override = drm_get_override_edid(connector); 1611 if (override) { 1612 drm_connector_update_edid_property(connector, override); 1613 num_modes = drm_add_edid_modes(connector, override); 1614 kfree(override); 1615 1616 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n", 1617 connector->base.id, connector->name, num_modes); 1618 } 1619 1620 return num_modes; 1621 } 1622 EXPORT_SYMBOL(drm_add_override_edid_modes); 1623 1624 /** 1625 * drm_do_get_edid - get EDID data using a custom EDID block read function 1626 * @connector: connector we're probing 1627 * @get_edid_block: EDID block read function 1628 * @data: private data passed to the block read function 1629 * 1630 * When the I2C adapter connected to the DDC bus is hidden behind a device that 1631 * exposes a different interface to read EDID blocks this function can be used 1632 * to get EDID data using a custom block read function. 1633 * 1634 * As in the general case the DDC bus is accessible by the kernel at the I2C 1635 * level, drivers must make all reasonable efforts to expose it as an I2C 1636 * adapter and use drm_get_edid() instead of abusing this function. 1637 * 1638 * The EDID may be overridden using debugfs override_edid or firmare EDID 1639 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority 1640 * order. Having either of them bypasses actual EDID reads. 1641 * 1642 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1643 */ 1644 struct edid *drm_do_get_edid(struct drm_connector *connector, 1645 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 1646 size_t len), 1647 void *data) 1648 { 1649 int i, j = 0, valid_extensions = 0; 1650 u8 *edid, *new; 1651 struct edid *override; 1652 1653 override = drm_get_override_edid(connector); 1654 if (override) 1655 return override; 1656 1657 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) 1658 return NULL; 1659 1660 /* base block fetch */ 1661 for (i = 0; i < 4; i++) { 1662 if (get_edid_block(data, edid, 0, EDID_LENGTH)) 1663 goto out; 1664 if (drm_edid_block_valid(edid, 0, false, 1665 &connector->edid_corrupt)) 1666 break; 1667 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) { 1668 connector->null_edid_counter++; 1669 goto carp; 1670 } 1671 } 1672 if (i == 4) 1673 goto carp; 1674 1675 /* if there's no extensions, we're done */ 1676 valid_extensions = edid[0x7e]; 1677 if (valid_extensions == 0) 1678 return (struct edid *)edid; 1679 1680 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1681 if (!new) 1682 goto out; 1683 edid = new; 1684 1685 for (j = 1; j <= edid[0x7e]; j++) { 1686 u8 *block = edid + j * EDID_LENGTH; 1687 1688 for (i = 0; i < 4; i++) { 1689 if (get_edid_block(data, block, j, EDID_LENGTH)) 1690 goto out; 1691 if (drm_edid_block_valid(block, j, false, NULL)) 1692 break; 1693 } 1694 1695 if (i == 4) 1696 valid_extensions--; 1697 } 1698 1699 if (valid_extensions != edid[0x7e]) { 1700 u8 *base; 1701 1702 connector_bad_edid(connector, edid, edid[0x7e] + 1); 1703 1704 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions; 1705 edid[0x7e] = valid_extensions; 1706 1707 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH, 1708 GFP_KERNEL); 1709 if (!new) 1710 goto out; 1711 1712 base = new; 1713 for (i = 0; i <= edid[0x7e]; i++) { 1714 u8 *block = edid + i * EDID_LENGTH; 1715 1716 if (!drm_edid_block_valid(block, i, false, NULL)) 1717 continue; 1718 1719 memcpy(base, block, EDID_LENGTH); 1720 base += EDID_LENGTH; 1721 } 1722 1723 kfree(edid); 1724 edid = new; 1725 } 1726 1727 return (struct edid *)edid; 1728 1729 carp: 1730 connector_bad_edid(connector, edid, 1); 1731 out: 1732 kfree(edid); 1733 return NULL; 1734 } 1735 EXPORT_SYMBOL_GPL(drm_do_get_edid); 1736 1737 /** 1738 * drm_probe_ddc() - probe DDC presence 1739 * @adapter: I2C adapter to probe 1740 * 1741 * Return: True on success, false on failure. 1742 */ 1743 bool 1744 drm_probe_ddc(struct i2c_adapter *adapter) 1745 { 1746 unsigned char out; 1747 1748 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 1749 } 1750 EXPORT_SYMBOL(drm_probe_ddc); 1751 1752 /** 1753 * drm_get_edid - get EDID data, if available 1754 * @connector: connector we're probing 1755 * @adapter: I2C adapter to use for DDC 1756 * 1757 * Poke the given I2C channel to grab EDID data if possible. If found, 1758 * attach it to the connector. 1759 * 1760 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1761 */ 1762 struct edid *drm_get_edid(struct drm_connector *connector, 1763 struct i2c_adapter *adapter) 1764 { 1765 struct edid *edid; 1766 1767 if (connector->force == DRM_FORCE_OFF) 1768 return NULL; 1769 1770 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 1771 return NULL; 1772 1773 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); 1774 if (edid) 1775 drm_get_displayid(connector, edid); 1776 return edid; 1777 } 1778 EXPORT_SYMBOL(drm_get_edid); 1779 1780 /** 1781 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 1782 * @connector: connector we're probing 1783 * @adapter: I2C adapter to use for DDC 1784 * 1785 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 1786 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 1787 * switch DDC to the GPU which is retrieving EDID. 1788 * 1789 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 1790 */ 1791 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 1792 struct i2c_adapter *adapter) 1793 { 1794 struct pci_dev *pdev = connector->dev->pdev; 1795 struct edid *edid; 1796 1797 vga_switcheroo_lock_ddc(pdev); 1798 edid = drm_get_edid(connector, adapter); 1799 vga_switcheroo_unlock_ddc(pdev); 1800 1801 return edid; 1802 } 1803 EXPORT_SYMBOL(drm_get_edid_switcheroo); 1804 1805 /** 1806 * drm_edid_duplicate - duplicate an EDID and the extensions 1807 * @edid: EDID to duplicate 1808 * 1809 * Return: Pointer to duplicated EDID or NULL on allocation failure. 1810 */ 1811 struct edid *drm_edid_duplicate(const struct edid *edid) 1812 { 1813 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1814 } 1815 EXPORT_SYMBOL(drm_edid_duplicate); 1816 1817 /*** EDID parsing ***/ 1818 1819 /** 1820 * edid_vendor - match a string against EDID's obfuscated vendor field 1821 * @edid: EDID to match 1822 * @vendor: vendor string 1823 * 1824 * Returns true if @vendor is in @edid, false otherwise 1825 */ 1826 static bool edid_vendor(const struct edid *edid, const char *vendor) 1827 { 1828 char edid_vendor[3]; 1829 1830 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 1831 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 1832 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 1833 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 1834 1835 return !strncmp(edid_vendor, vendor, 3); 1836 } 1837 1838 /** 1839 * edid_get_quirks - return quirk flags for a given EDID 1840 * @edid: EDID to process 1841 * 1842 * This tells subsequent routines what fixes they need to apply. 1843 */ 1844 static u32 edid_get_quirks(const struct edid *edid) 1845 { 1846 const struct edid_quirk *quirk; 1847 int i; 1848 1849 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 1850 quirk = &edid_quirk_list[i]; 1851 1852 if (edid_vendor(edid, quirk->vendor) && 1853 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 1854 return quirk->quirks; 1855 } 1856 1857 return 0; 1858 } 1859 1860 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 1861 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 1862 1863 /** 1864 * edid_fixup_preferred - set preferred modes based on quirk list 1865 * @connector: has mode list to fix up 1866 * @quirks: quirks list 1867 * 1868 * Walk the mode list for @connector, clearing the preferred status 1869 * on existing modes and setting it anew for the right mode ala @quirks. 1870 */ 1871 static void edid_fixup_preferred(struct drm_connector *connector, 1872 u32 quirks) 1873 { 1874 struct drm_display_mode *t, *cur_mode, *preferred_mode; 1875 int target_refresh = 0; 1876 int cur_vrefresh, preferred_vrefresh; 1877 1878 if (list_empty(&connector->probed_modes)) 1879 return; 1880 1881 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 1882 target_refresh = 60; 1883 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 1884 target_refresh = 75; 1885 1886 preferred_mode = list_first_entry(&connector->probed_modes, 1887 struct drm_display_mode, head); 1888 1889 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 1890 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 1891 1892 if (cur_mode == preferred_mode) 1893 continue; 1894 1895 /* Largest mode is preferred */ 1896 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 1897 preferred_mode = cur_mode; 1898 1899 cur_vrefresh = cur_mode->vrefresh ? 1900 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode); 1901 preferred_vrefresh = preferred_mode->vrefresh ? 1902 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode); 1903 /* At a given size, try to get closest to target refresh */ 1904 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 1905 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 1906 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 1907 preferred_mode = cur_mode; 1908 } 1909 } 1910 1911 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 1912 } 1913 1914 static bool 1915 mode_is_rb(const struct drm_display_mode *mode) 1916 { 1917 return (mode->htotal - mode->hdisplay == 160) && 1918 (mode->hsync_end - mode->hdisplay == 80) && 1919 (mode->hsync_end - mode->hsync_start == 32) && 1920 (mode->vsync_start - mode->vdisplay == 3); 1921 } 1922 1923 /* 1924 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 1925 * @dev: Device to duplicate against 1926 * @hsize: Mode width 1927 * @vsize: Mode height 1928 * @fresh: Mode refresh rate 1929 * @rb: Mode reduced-blanking-ness 1930 * 1931 * Walk the DMT mode list looking for a match for the given parameters. 1932 * 1933 * Return: A newly allocated copy of the mode, or NULL if not found. 1934 */ 1935 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 1936 int hsize, int vsize, int fresh, 1937 bool rb) 1938 { 1939 int i; 1940 1941 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 1942 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 1943 if (hsize != ptr->hdisplay) 1944 continue; 1945 if (vsize != ptr->vdisplay) 1946 continue; 1947 if (fresh != drm_mode_vrefresh(ptr)) 1948 continue; 1949 if (rb != mode_is_rb(ptr)) 1950 continue; 1951 1952 return drm_mode_duplicate(dev, ptr); 1953 } 1954 1955 return NULL; 1956 } 1957 EXPORT_SYMBOL(drm_mode_find_dmt); 1958 1959 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 1960 1961 static void 1962 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1963 { 1964 int i, n = 0; 1965 u8 d = ext[0x02]; 1966 u8 *det_base = ext + d; 1967 1968 n = (127 - d) / 18; 1969 for (i = 0; i < n; i++) 1970 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1971 } 1972 1973 static void 1974 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1975 { 1976 unsigned int i, n = min((int)ext[0x02], 6); 1977 u8 *det_base = ext + 5; 1978 1979 if (ext[0x01] != 1) 1980 return; /* unknown version */ 1981 1982 for (i = 0; i < n; i++) 1983 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1984 } 1985 1986 static void 1987 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 1988 { 1989 int i; 1990 struct edid *edid = (struct edid *)raw_edid; 1991 1992 if (edid == NULL) 1993 return; 1994 1995 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 1996 cb(&(edid->detailed_timings[i]), closure); 1997 1998 for (i = 1; i <= raw_edid[0x7e]; i++) { 1999 u8 *ext = raw_edid + (i * EDID_LENGTH); 2000 switch (*ext) { 2001 case CEA_EXT: 2002 cea_for_each_detailed_block(ext, cb, closure); 2003 break; 2004 case VTB_EXT: 2005 vtb_for_each_detailed_block(ext, cb, closure); 2006 break; 2007 default: 2008 break; 2009 } 2010 } 2011 } 2012 2013 static void 2014 is_rb(struct detailed_timing *t, void *data) 2015 { 2016 u8 *r = (u8 *)t; 2017 if (r[3] == EDID_DETAIL_MONITOR_RANGE) 2018 if (r[15] & 0x10) 2019 *(bool *)data = true; 2020 } 2021 2022 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 2023 static bool 2024 drm_monitor_supports_rb(struct edid *edid) 2025 { 2026 if (edid->revision >= 4) { 2027 bool ret = false; 2028 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 2029 return ret; 2030 } 2031 2032 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 2033 } 2034 2035 static void 2036 find_gtf2(struct detailed_timing *t, void *data) 2037 { 2038 u8 *r = (u8 *)t; 2039 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) 2040 *(u8 **)data = r; 2041 } 2042 2043 /* Secondary GTF curve kicks in above some break frequency */ 2044 static int 2045 drm_gtf2_hbreak(struct edid *edid) 2046 { 2047 u8 *r = NULL; 2048 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2049 return r ? (r[12] * 2) : 0; 2050 } 2051 2052 static int 2053 drm_gtf2_2c(struct edid *edid) 2054 { 2055 u8 *r = NULL; 2056 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2057 return r ? r[13] : 0; 2058 } 2059 2060 static int 2061 drm_gtf2_m(struct edid *edid) 2062 { 2063 u8 *r = NULL; 2064 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2065 return r ? (r[15] << 8) + r[14] : 0; 2066 } 2067 2068 static int 2069 drm_gtf2_k(struct edid *edid) 2070 { 2071 u8 *r = NULL; 2072 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2073 return r ? r[16] : 0; 2074 } 2075 2076 static int 2077 drm_gtf2_2j(struct edid *edid) 2078 { 2079 u8 *r = NULL; 2080 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2081 return r ? r[17] : 0; 2082 } 2083 2084 /** 2085 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 2086 * @edid: EDID block to scan 2087 */ 2088 static int standard_timing_level(struct edid *edid) 2089 { 2090 if (edid->revision >= 2) { 2091 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 2092 return LEVEL_CVT; 2093 if (drm_gtf2_hbreak(edid)) 2094 return LEVEL_GTF2; 2095 return LEVEL_GTF; 2096 } 2097 return LEVEL_DMT; 2098 } 2099 2100 /* 2101 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 2102 * monitors fill with ascii space (0x20) instead. 2103 */ 2104 static int 2105 bad_std_timing(u8 a, u8 b) 2106 { 2107 return (a == 0x00 && b == 0x00) || 2108 (a == 0x01 && b == 0x01) || 2109 (a == 0x20 && b == 0x20); 2110 } 2111 2112 /** 2113 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 2114 * @connector: connector of for the EDID block 2115 * @edid: EDID block to scan 2116 * @t: standard timing params 2117 * 2118 * Take the standard timing params (in this case width, aspect, and refresh) 2119 * and convert them into a real mode using CVT/GTF/DMT. 2120 */ 2121 static struct drm_display_mode * 2122 drm_mode_std(struct drm_connector *connector, struct edid *edid, 2123 struct std_timing *t) 2124 { 2125 struct drm_device *dev = connector->dev; 2126 struct drm_display_mode *m, *mode = NULL; 2127 int hsize, vsize; 2128 int vrefresh_rate; 2129 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 2130 >> EDID_TIMING_ASPECT_SHIFT; 2131 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 2132 >> EDID_TIMING_VFREQ_SHIFT; 2133 int timing_level = standard_timing_level(edid); 2134 2135 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 2136 return NULL; 2137 2138 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 2139 hsize = t->hsize * 8 + 248; 2140 /* vrefresh_rate = vfreq + 60 */ 2141 vrefresh_rate = vfreq + 60; 2142 /* the vdisplay is calculated based on the aspect ratio */ 2143 if (aspect_ratio == 0) { 2144 if (edid->revision < 3) 2145 vsize = hsize; 2146 else 2147 vsize = (hsize * 10) / 16; 2148 } else if (aspect_ratio == 1) 2149 vsize = (hsize * 3) / 4; 2150 else if (aspect_ratio == 2) 2151 vsize = (hsize * 4) / 5; 2152 else 2153 vsize = (hsize * 9) / 16; 2154 2155 /* HDTV hack, part 1 */ 2156 if (vrefresh_rate == 60 && 2157 ((hsize == 1360 && vsize == 765) || 2158 (hsize == 1368 && vsize == 769))) { 2159 hsize = 1366; 2160 vsize = 768; 2161 } 2162 2163 /* 2164 * If this connector already has a mode for this size and refresh 2165 * rate (because it came from detailed or CVT info), use that 2166 * instead. This way we don't have to guess at interlace or 2167 * reduced blanking. 2168 */ 2169 list_for_each_entry(m, &connector->probed_modes, head) 2170 if (m->hdisplay == hsize && m->vdisplay == vsize && 2171 drm_mode_vrefresh(m) == vrefresh_rate) 2172 return NULL; 2173 2174 /* HDTV hack, part 2 */ 2175 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 2176 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 2177 false); 2178 if (!mode) 2179 return NULL; 2180 mode->hdisplay = 1366; 2181 mode->hsync_start = mode->hsync_start - 1; 2182 mode->hsync_end = mode->hsync_end - 1; 2183 return mode; 2184 } 2185 2186 /* check whether it can be found in default mode table */ 2187 if (drm_monitor_supports_rb(edid)) { 2188 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 2189 true); 2190 if (mode) 2191 return mode; 2192 } 2193 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 2194 if (mode) 2195 return mode; 2196 2197 /* okay, generate it */ 2198 switch (timing_level) { 2199 case LEVEL_DMT: 2200 break; 2201 case LEVEL_GTF: 2202 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2203 break; 2204 case LEVEL_GTF2: 2205 /* 2206 * This is potentially wrong if there's ever a monitor with 2207 * more than one ranges section, each claiming a different 2208 * secondary GTF curve. Please don't do that. 2209 */ 2210 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2211 if (!mode) 2212 return NULL; 2213 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 2214 drm_mode_destroy(dev, mode); 2215 mode = drm_gtf_mode_complex(dev, hsize, vsize, 2216 vrefresh_rate, 0, 0, 2217 drm_gtf2_m(edid), 2218 drm_gtf2_2c(edid), 2219 drm_gtf2_k(edid), 2220 drm_gtf2_2j(edid)); 2221 } 2222 break; 2223 case LEVEL_CVT: 2224 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 2225 false); 2226 break; 2227 } 2228 return mode; 2229 } 2230 2231 /* 2232 * EDID is delightfully ambiguous about how interlaced modes are to be 2233 * encoded. Our internal representation is of frame height, but some 2234 * HDTV detailed timings are encoded as field height. 2235 * 2236 * The format list here is from CEA, in frame size. Technically we 2237 * should be checking refresh rate too. Whatever. 2238 */ 2239 static void 2240 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 2241 struct detailed_pixel_timing *pt) 2242 { 2243 int i; 2244 static const struct { 2245 int w, h; 2246 } cea_interlaced[] = { 2247 { 1920, 1080 }, 2248 { 720, 480 }, 2249 { 1440, 480 }, 2250 { 2880, 480 }, 2251 { 720, 576 }, 2252 { 1440, 576 }, 2253 { 2880, 576 }, 2254 }; 2255 2256 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 2257 return; 2258 2259 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 2260 if ((mode->hdisplay == cea_interlaced[i].w) && 2261 (mode->vdisplay == cea_interlaced[i].h / 2)) { 2262 mode->vdisplay *= 2; 2263 mode->vsync_start *= 2; 2264 mode->vsync_end *= 2; 2265 mode->vtotal *= 2; 2266 mode->vtotal |= 1; 2267 } 2268 } 2269 2270 mode->flags |= DRM_MODE_FLAG_INTERLACE; 2271 } 2272 2273 /** 2274 * drm_mode_detailed - create a new mode from an EDID detailed timing section 2275 * @dev: DRM device (needed to create new mode) 2276 * @edid: EDID block 2277 * @timing: EDID detailed timing info 2278 * @quirks: quirks to apply 2279 * 2280 * An EDID detailed timing block contains enough info for us to create and 2281 * return a new struct drm_display_mode. 2282 */ 2283 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 2284 struct edid *edid, 2285 struct detailed_timing *timing, 2286 u32 quirks) 2287 { 2288 struct drm_display_mode *mode; 2289 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 2290 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 2291 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 2292 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 2293 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 2294 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 2295 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 2296 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 2297 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 2298 2299 /* ignore tiny modes */ 2300 if (hactive < 64 || vactive < 64) 2301 return NULL; 2302 2303 if (pt->misc & DRM_EDID_PT_STEREO) { 2304 DRM_DEBUG_KMS("stereo mode not supported\n"); 2305 return NULL; 2306 } 2307 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 2308 DRM_DEBUG_KMS("composite sync not supported\n"); 2309 } 2310 2311 /* it is incorrect if hsync/vsync width is zero */ 2312 if (!hsync_pulse_width || !vsync_pulse_width) { 2313 DRM_DEBUG_KMS("Incorrect Detailed timing. " 2314 "Wrong Hsync/Vsync pulse width\n"); 2315 return NULL; 2316 } 2317 2318 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 2319 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 2320 if (!mode) 2321 return NULL; 2322 2323 goto set_size; 2324 } 2325 2326 mode = drm_mode_create(dev); 2327 if (!mode) 2328 return NULL; 2329 2330 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 2331 timing->pixel_clock = cpu_to_le16(1088); 2332 2333 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 2334 2335 mode->hdisplay = hactive; 2336 mode->hsync_start = mode->hdisplay + hsync_offset; 2337 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 2338 mode->htotal = mode->hdisplay + hblank; 2339 2340 mode->vdisplay = vactive; 2341 mode->vsync_start = mode->vdisplay + vsync_offset; 2342 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 2343 mode->vtotal = mode->vdisplay + vblank; 2344 2345 /* Some EDIDs have bogus h/vtotal values */ 2346 if (mode->hsync_end > mode->htotal) 2347 mode->htotal = mode->hsync_end + 1; 2348 if (mode->vsync_end > mode->vtotal) 2349 mode->vtotal = mode->vsync_end + 1; 2350 2351 drm_mode_do_interlace_quirk(mode, pt); 2352 2353 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 2354 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; 2355 } 2356 2357 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 2358 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 2359 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 2360 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 2361 2362 set_size: 2363 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 2364 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 2365 2366 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 2367 mode->width_mm *= 10; 2368 mode->height_mm *= 10; 2369 } 2370 2371 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 2372 mode->width_mm = edid->width_cm * 10; 2373 mode->height_mm = edid->height_cm * 10; 2374 } 2375 2376 mode->type = DRM_MODE_TYPE_DRIVER; 2377 mode->vrefresh = drm_mode_vrefresh(mode); 2378 drm_mode_set_name(mode); 2379 2380 return mode; 2381 } 2382 2383 static bool 2384 mode_in_hsync_range(const struct drm_display_mode *mode, 2385 struct edid *edid, u8 *t) 2386 { 2387 int hsync, hmin, hmax; 2388 2389 hmin = t[7]; 2390 if (edid->revision >= 4) 2391 hmin += ((t[4] & 0x04) ? 255 : 0); 2392 hmax = t[8]; 2393 if (edid->revision >= 4) 2394 hmax += ((t[4] & 0x08) ? 255 : 0); 2395 hsync = drm_mode_hsync(mode); 2396 2397 return (hsync <= hmax && hsync >= hmin); 2398 } 2399 2400 static bool 2401 mode_in_vsync_range(const struct drm_display_mode *mode, 2402 struct edid *edid, u8 *t) 2403 { 2404 int vsync, vmin, vmax; 2405 2406 vmin = t[5]; 2407 if (edid->revision >= 4) 2408 vmin += ((t[4] & 0x01) ? 255 : 0); 2409 vmax = t[6]; 2410 if (edid->revision >= 4) 2411 vmax += ((t[4] & 0x02) ? 255 : 0); 2412 vsync = drm_mode_vrefresh(mode); 2413 2414 return (vsync <= vmax && vsync >= vmin); 2415 } 2416 2417 static u32 2418 range_pixel_clock(struct edid *edid, u8 *t) 2419 { 2420 /* unspecified */ 2421 if (t[9] == 0 || t[9] == 255) 2422 return 0; 2423 2424 /* 1.4 with CVT support gives us real precision, yay */ 2425 if (edid->revision >= 4 && t[10] == 0x04) 2426 return (t[9] * 10000) - ((t[12] >> 2) * 250); 2427 2428 /* 1.3 is pathetic, so fuzz up a bit */ 2429 return t[9] * 10000 + 5001; 2430 } 2431 2432 static bool 2433 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 2434 struct detailed_timing *timing) 2435 { 2436 u32 max_clock; 2437 u8 *t = (u8 *)timing; 2438 2439 if (!mode_in_hsync_range(mode, edid, t)) 2440 return false; 2441 2442 if (!mode_in_vsync_range(mode, edid, t)) 2443 return false; 2444 2445 if ((max_clock = range_pixel_clock(edid, t))) 2446 if (mode->clock > max_clock) 2447 return false; 2448 2449 /* 1.4 max horizontal check */ 2450 if (edid->revision >= 4 && t[10] == 0x04) 2451 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 2452 return false; 2453 2454 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 2455 return false; 2456 2457 return true; 2458 } 2459 2460 static bool valid_inferred_mode(const struct drm_connector *connector, 2461 const struct drm_display_mode *mode) 2462 { 2463 const struct drm_display_mode *m; 2464 bool ok = false; 2465 2466 list_for_each_entry(m, &connector->probed_modes, head) { 2467 if (mode->hdisplay == m->hdisplay && 2468 mode->vdisplay == m->vdisplay && 2469 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 2470 return false; /* duplicated */ 2471 if (mode->hdisplay <= m->hdisplay && 2472 mode->vdisplay <= m->vdisplay) 2473 ok = true; 2474 } 2475 return ok; 2476 } 2477 2478 static int 2479 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2480 struct detailed_timing *timing) 2481 { 2482 int i, modes = 0; 2483 struct drm_display_mode *newmode; 2484 struct drm_device *dev = connector->dev; 2485 2486 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2487 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 2488 valid_inferred_mode(connector, drm_dmt_modes + i)) { 2489 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 2490 if (newmode) { 2491 drm_mode_probed_add(connector, newmode); 2492 modes++; 2493 } 2494 } 2495 } 2496 2497 return modes; 2498 } 2499 2500 /* fix up 1366x768 mode from 1368x768; 2501 * GFT/CVT can't express 1366 width which isn't dividable by 8 2502 */ 2503 void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 2504 { 2505 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 2506 mode->hdisplay = 1366; 2507 mode->hsync_start--; 2508 mode->hsync_end--; 2509 drm_mode_set_name(mode); 2510 } 2511 } 2512 2513 static int 2514 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, 2515 struct detailed_timing *timing) 2516 { 2517 int i, modes = 0; 2518 struct drm_display_mode *newmode; 2519 struct drm_device *dev = connector->dev; 2520 2521 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2522 const struct minimode *m = &extra_modes[i]; 2523 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 2524 if (!newmode) 2525 return modes; 2526 2527 drm_mode_fixup_1366x768(newmode); 2528 if (!mode_in_range(newmode, edid, timing) || 2529 !valid_inferred_mode(connector, newmode)) { 2530 drm_mode_destroy(dev, newmode); 2531 continue; 2532 } 2533 2534 drm_mode_probed_add(connector, newmode); 2535 modes++; 2536 } 2537 2538 return modes; 2539 } 2540 2541 static int 2542 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2543 struct detailed_timing *timing) 2544 { 2545 int i, modes = 0; 2546 struct drm_display_mode *newmode; 2547 struct drm_device *dev = connector->dev; 2548 bool rb = drm_monitor_supports_rb(edid); 2549 2550 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2551 const struct minimode *m = &extra_modes[i]; 2552 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 2553 if (!newmode) 2554 return modes; 2555 2556 drm_mode_fixup_1366x768(newmode); 2557 if (!mode_in_range(newmode, edid, timing) || 2558 !valid_inferred_mode(connector, newmode)) { 2559 drm_mode_destroy(dev, newmode); 2560 continue; 2561 } 2562 2563 drm_mode_probed_add(connector, newmode); 2564 modes++; 2565 } 2566 2567 return modes; 2568 } 2569 2570 static void 2571 do_inferred_modes(struct detailed_timing *timing, void *c) 2572 { 2573 struct detailed_mode_closure *closure = c; 2574 struct detailed_non_pixel *data = &timing->data.other_data; 2575 struct detailed_data_monitor_range *range = &data->data.range; 2576 2577 if (data->type != EDID_DETAIL_MONITOR_RANGE) 2578 return; 2579 2580 closure->modes += drm_dmt_modes_for_range(closure->connector, 2581 closure->edid, 2582 timing); 2583 2584 if (!version_greater(closure->edid, 1, 1)) 2585 return; /* GTF not defined yet */ 2586 2587 switch (range->flags) { 2588 case 0x02: /* secondary gtf, XXX could do more */ 2589 case 0x00: /* default gtf */ 2590 closure->modes += drm_gtf_modes_for_range(closure->connector, 2591 closure->edid, 2592 timing); 2593 break; 2594 case 0x04: /* cvt, only in 1.4+ */ 2595 if (!version_greater(closure->edid, 1, 3)) 2596 break; 2597 2598 closure->modes += drm_cvt_modes_for_range(closure->connector, 2599 closure->edid, 2600 timing); 2601 break; 2602 case 0x01: /* just the ranges, no formula */ 2603 default: 2604 break; 2605 } 2606 } 2607 2608 static int 2609 add_inferred_modes(struct drm_connector *connector, struct edid *edid) 2610 { 2611 struct detailed_mode_closure closure = { 2612 .connector = connector, 2613 .edid = edid, 2614 }; 2615 2616 if (version_greater(edid, 1, 0)) 2617 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 2618 &closure); 2619 2620 return closure.modes; 2621 } 2622 2623 static int 2624 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 2625 { 2626 int i, j, m, modes = 0; 2627 struct drm_display_mode *mode; 2628 u8 *est = ((u8 *)timing) + 6; 2629 2630 for (i = 0; i < 6; i++) { 2631 for (j = 7; j >= 0; j--) { 2632 m = (i * 8) + (7 - j); 2633 if (m >= ARRAY_SIZE(est3_modes)) 2634 break; 2635 if (est[i] & (1 << j)) { 2636 mode = drm_mode_find_dmt(connector->dev, 2637 est3_modes[m].w, 2638 est3_modes[m].h, 2639 est3_modes[m].r, 2640 est3_modes[m].rb); 2641 if (mode) { 2642 drm_mode_probed_add(connector, mode); 2643 modes++; 2644 } 2645 } 2646 } 2647 } 2648 2649 return modes; 2650 } 2651 2652 static void 2653 do_established_modes(struct detailed_timing *timing, void *c) 2654 { 2655 struct detailed_mode_closure *closure = c; 2656 struct detailed_non_pixel *data = &timing->data.other_data; 2657 2658 if (data->type == EDID_DETAIL_EST_TIMINGS) 2659 closure->modes += drm_est3_modes(closure->connector, timing); 2660 } 2661 2662 /** 2663 * add_established_modes - get est. modes from EDID and add them 2664 * @connector: connector to add mode(s) to 2665 * @edid: EDID block to scan 2666 * 2667 * Each EDID block contains a bitmap of the supported "established modes" list 2668 * (defined above). Tease them out and add them to the global modes list. 2669 */ 2670 static int 2671 add_established_modes(struct drm_connector *connector, struct edid *edid) 2672 { 2673 struct drm_device *dev = connector->dev; 2674 unsigned long est_bits = edid->established_timings.t1 | 2675 (edid->established_timings.t2 << 8) | 2676 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 2677 int i, modes = 0; 2678 struct detailed_mode_closure closure = { 2679 .connector = connector, 2680 .edid = edid, 2681 }; 2682 2683 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 2684 if (est_bits & (1<<i)) { 2685 struct drm_display_mode *newmode; 2686 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 2687 if (newmode) { 2688 drm_mode_probed_add(connector, newmode); 2689 modes++; 2690 } 2691 } 2692 } 2693 2694 if (version_greater(edid, 1, 0)) 2695 drm_for_each_detailed_block((u8 *)edid, 2696 do_established_modes, &closure); 2697 2698 return modes + closure.modes; 2699 } 2700 2701 static void 2702 do_standard_modes(struct detailed_timing *timing, void *c) 2703 { 2704 struct detailed_mode_closure *closure = c; 2705 struct detailed_non_pixel *data = &timing->data.other_data; 2706 struct drm_connector *connector = closure->connector; 2707 struct edid *edid = closure->edid; 2708 2709 if (data->type == EDID_DETAIL_STD_MODES) { 2710 int i; 2711 for (i = 0; i < 6; i++) { 2712 struct std_timing *std; 2713 struct drm_display_mode *newmode; 2714 2715 std = &data->data.timings[i]; 2716 newmode = drm_mode_std(connector, edid, std); 2717 if (newmode) { 2718 drm_mode_probed_add(connector, newmode); 2719 closure->modes++; 2720 } 2721 } 2722 } 2723 } 2724 2725 /** 2726 * add_standard_modes - get std. modes from EDID and add them 2727 * @connector: connector to add mode(s) to 2728 * @edid: EDID block to scan 2729 * 2730 * Standard modes can be calculated using the appropriate standard (DMT, 2731 * GTF or CVT. Grab them from @edid and add them to the list. 2732 */ 2733 static int 2734 add_standard_modes(struct drm_connector *connector, struct edid *edid) 2735 { 2736 int i, modes = 0; 2737 struct detailed_mode_closure closure = { 2738 .connector = connector, 2739 .edid = edid, 2740 }; 2741 2742 for (i = 0; i < EDID_STD_TIMINGS; i++) { 2743 struct drm_display_mode *newmode; 2744 2745 newmode = drm_mode_std(connector, edid, 2746 &edid->standard_timings[i]); 2747 if (newmode) { 2748 drm_mode_probed_add(connector, newmode); 2749 modes++; 2750 } 2751 } 2752 2753 if (version_greater(edid, 1, 0)) 2754 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 2755 &closure); 2756 2757 /* XXX should also look for standard codes in VTB blocks */ 2758 2759 return modes + closure.modes; 2760 } 2761 2762 static int drm_cvt_modes(struct drm_connector *connector, 2763 struct detailed_timing *timing) 2764 { 2765 int i, j, modes = 0; 2766 struct drm_display_mode *newmode; 2767 struct drm_device *dev = connector->dev; 2768 struct cvt_timing *cvt; 2769 const int rates[] = { 60, 85, 75, 60, 50 }; 2770 const u8 empty[3] = { 0, 0, 0 }; 2771 2772 for (i = 0; i < 4; i++) { 2773 int uninitialized_var(width), height; 2774 cvt = &(timing->data.other_data.data.cvt[i]); 2775 2776 if (!memcmp(cvt->code, empty, 3)) 2777 continue; 2778 2779 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 2780 switch (cvt->code[1] & 0x0c) { 2781 case 0x00: 2782 width = height * 4 / 3; 2783 break; 2784 case 0x04: 2785 width = height * 16 / 9; 2786 break; 2787 case 0x08: 2788 width = height * 16 / 10; 2789 break; 2790 case 0x0c: 2791 width = height * 15 / 9; 2792 break; 2793 } 2794 2795 for (j = 1; j < 5; j++) { 2796 if (cvt->code[2] & (1 << j)) { 2797 newmode = drm_cvt_mode(dev, width, height, 2798 rates[j], j == 0, 2799 false, false); 2800 if (newmode) { 2801 drm_mode_probed_add(connector, newmode); 2802 modes++; 2803 } 2804 } 2805 } 2806 } 2807 2808 return modes; 2809 } 2810 2811 static void 2812 do_cvt_mode(struct detailed_timing *timing, void *c) 2813 { 2814 struct detailed_mode_closure *closure = c; 2815 struct detailed_non_pixel *data = &timing->data.other_data; 2816 2817 if (data->type == EDID_DETAIL_CVT_3BYTE) 2818 closure->modes += drm_cvt_modes(closure->connector, timing); 2819 } 2820 2821 static int 2822 add_cvt_modes(struct drm_connector *connector, struct edid *edid) 2823 { 2824 struct detailed_mode_closure closure = { 2825 .connector = connector, 2826 .edid = edid, 2827 }; 2828 2829 if (version_greater(edid, 1, 2)) 2830 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 2831 2832 /* XXX should also look for CVT codes in VTB blocks */ 2833 2834 return closure.modes; 2835 } 2836 2837 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); 2838 2839 static void 2840 do_detailed_mode(struct detailed_timing *timing, void *c) 2841 { 2842 struct detailed_mode_closure *closure = c; 2843 struct drm_display_mode *newmode; 2844 2845 if (timing->pixel_clock) { 2846 newmode = drm_mode_detailed(closure->connector->dev, 2847 closure->edid, timing, 2848 closure->quirks); 2849 if (!newmode) 2850 return; 2851 2852 if (closure->preferred) 2853 newmode->type |= DRM_MODE_TYPE_PREFERRED; 2854 2855 /* 2856 * Detailed modes are limited to 10kHz pixel clock resolution, 2857 * so fix up anything that looks like CEA/HDMI mode, but the clock 2858 * is just slightly off. 2859 */ 2860 fixup_detailed_cea_mode_clock(newmode); 2861 2862 drm_mode_probed_add(closure->connector, newmode); 2863 closure->modes++; 2864 closure->preferred = false; 2865 } 2866 } 2867 2868 /* 2869 * add_detailed_modes - Add modes from detailed timings 2870 * @connector: attached connector 2871 * @edid: EDID block to scan 2872 * @quirks: quirks to apply 2873 */ 2874 static int 2875 add_detailed_modes(struct drm_connector *connector, struct edid *edid, 2876 u32 quirks) 2877 { 2878 struct detailed_mode_closure closure = { 2879 .connector = connector, 2880 .edid = edid, 2881 .preferred = true, 2882 .quirks = quirks, 2883 }; 2884 2885 if (closure.preferred && !version_greater(edid, 1, 3)) 2886 closure.preferred = 2887 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 2888 2889 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 2890 2891 return closure.modes; 2892 } 2893 2894 #define AUDIO_BLOCK 0x01 2895 #define VIDEO_BLOCK 0x02 2896 #define VENDOR_BLOCK 0x03 2897 #define SPEAKER_BLOCK 0x04 2898 #define HDR_STATIC_METADATA_BLOCK 0x6 2899 #define USE_EXTENDED_TAG 0x07 2900 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00 2901 #define EXT_VIDEO_DATA_BLOCK_420 0x0E 2902 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F 2903 #define EDID_BASIC_AUDIO (1 << 6) 2904 #define EDID_CEA_YCRCB444 (1 << 5) 2905 #define EDID_CEA_YCRCB422 (1 << 4) 2906 #define EDID_CEA_VCDB_QS (1 << 6) 2907 2908 /* 2909 * Search EDID for CEA extension block. 2910 */ 2911 static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id) 2912 { 2913 u8 *edid_ext = NULL; 2914 int i; 2915 2916 /* No EDID or EDID extensions */ 2917 if (edid == NULL || edid->extensions == 0) 2918 return NULL; 2919 2920 /* Find CEA extension */ 2921 for (i = 0; i < edid->extensions; i++) { 2922 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); 2923 if (edid_ext[0] == ext_id) 2924 break; 2925 } 2926 2927 if (i == edid->extensions) 2928 return NULL; 2929 2930 return edid_ext; 2931 } 2932 2933 2934 static u8 *drm_find_displayid_extension(const struct edid *edid) 2935 { 2936 return drm_find_edid_extension(edid, DISPLAYID_EXT); 2937 } 2938 2939 static u8 *drm_find_cea_extension(const struct edid *edid) 2940 { 2941 int ret; 2942 int idx = 1; 2943 int length = EDID_LENGTH; 2944 struct displayid_block *block; 2945 u8 *cea; 2946 u8 *displayid; 2947 2948 /* Look for a top level CEA extension block */ 2949 cea = drm_find_edid_extension(edid, CEA_EXT); 2950 if (cea) 2951 return cea; 2952 2953 /* CEA blocks can also be found embedded in a DisplayID block */ 2954 displayid = drm_find_displayid_extension(edid); 2955 if (!displayid) 2956 return NULL; 2957 2958 ret = validate_displayid(displayid, length, idx); 2959 if (ret) 2960 return NULL; 2961 2962 idx += sizeof(struct displayid_hdr); 2963 for_each_displayid_db(displayid, block, idx, length) { 2964 if (block->tag == DATA_BLOCK_CTA) { 2965 cea = (u8 *)block; 2966 break; 2967 } 2968 } 2969 2970 return cea; 2971 } 2972 2973 /* 2974 * Calculate the alternate clock for the CEA mode 2975 * (60Hz vs. 59.94Hz etc.) 2976 */ 2977 static unsigned int 2978 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 2979 { 2980 unsigned int clock = cea_mode->clock; 2981 2982 if (cea_mode->vrefresh % 6 != 0) 2983 return clock; 2984 2985 /* 2986 * edid_cea_modes contains the 59.94Hz 2987 * variant for 240 and 480 line modes, 2988 * and the 60Hz variant otherwise. 2989 */ 2990 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 2991 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 2992 else 2993 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 2994 2995 return clock; 2996 } 2997 2998 static bool 2999 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 3000 { 3001 /* 3002 * For certain VICs the spec allows the vertical 3003 * front porch to vary by one or two lines. 3004 * 3005 * cea_modes[] stores the variant with the shortest 3006 * vertical front porch. We can adjust the mode to 3007 * get the other variants by simply increasing the 3008 * vertical front porch length. 3009 */ 3010 BUILD_BUG_ON(edid_cea_modes[8].vtotal != 262 || 3011 edid_cea_modes[9].vtotal != 262 || 3012 edid_cea_modes[12].vtotal != 262 || 3013 edid_cea_modes[13].vtotal != 262 || 3014 edid_cea_modes[23].vtotal != 312 || 3015 edid_cea_modes[24].vtotal != 312 || 3016 edid_cea_modes[27].vtotal != 312 || 3017 edid_cea_modes[28].vtotal != 312); 3018 3019 if (((vic == 8 || vic == 9 || 3020 vic == 12 || vic == 13) && mode->vtotal < 263) || 3021 ((vic == 23 || vic == 24 || 3022 vic == 27 || vic == 28) && mode->vtotal < 314)) { 3023 mode->vsync_start++; 3024 mode->vsync_end++; 3025 mode->vtotal++; 3026 3027 return true; 3028 } 3029 3030 return false; 3031 } 3032 3033 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 3034 unsigned int clock_tolerance) 3035 { 3036 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3037 u8 vic; 3038 3039 if (!to_match->clock) 3040 return 0; 3041 3042 if (to_match->picture_aspect_ratio) 3043 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3044 3045 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 3046 struct drm_display_mode cea_mode = edid_cea_modes[vic]; 3047 unsigned int clock1, clock2; 3048 3049 /* Check both 60Hz and 59.94Hz */ 3050 clock1 = cea_mode.clock; 3051 clock2 = cea_mode_alternate_clock(&cea_mode); 3052 3053 if (abs(to_match->clock - clock1) > clock_tolerance && 3054 abs(to_match->clock - clock2) > clock_tolerance) 3055 continue; 3056 3057 do { 3058 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3059 return vic; 3060 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3061 } 3062 3063 return 0; 3064 } 3065 3066 /** 3067 * drm_match_cea_mode - look for a CEA mode matching given mode 3068 * @to_match: display mode 3069 * 3070 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 3071 * mode. 3072 */ 3073 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 3074 { 3075 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3076 u8 vic; 3077 3078 if (!to_match->clock) 3079 return 0; 3080 3081 if (to_match->picture_aspect_ratio) 3082 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3083 3084 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 3085 struct drm_display_mode cea_mode = edid_cea_modes[vic]; 3086 unsigned int clock1, clock2; 3087 3088 /* Check both 60Hz and 59.94Hz */ 3089 clock1 = cea_mode.clock; 3090 clock2 = cea_mode_alternate_clock(&cea_mode); 3091 3092 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 3093 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 3094 continue; 3095 3096 do { 3097 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3098 return vic; 3099 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3100 } 3101 3102 return 0; 3103 } 3104 EXPORT_SYMBOL(drm_match_cea_mode); 3105 3106 static bool drm_valid_cea_vic(u8 vic) 3107 { 3108 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes); 3109 } 3110 3111 /** 3112 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to 3113 * the input VIC from the CEA mode list 3114 * @video_code: ID given to each of the CEA modes 3115 * 3116 * Returns picture aspect ratio 3117 */ 3118 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 3119 { 3120 return edid_cea_modes[video_code].picture_aspect_ratio; 3121 } 3122 EXPORT_SYMBOL(drm_get_cea_aspect_ratio); 3123 3124 /* 3125 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 3126 * specific block). 3127 * 3128 * It's almost like cea_mode_alternate_clock(), we just need to add an 3129 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this 3130 * one. 3131 */ 3132 static unsigned int 3133 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 3134 { 3135 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) 3136 return hdmi_mode->clock; 3137 3138 return cea_mode_alternate_clock(hdmi_mode); 3139 } 3140 3141 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 3142 unsigned int clock_tolerance) 3143 { 3144 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3145 u8 vic; 3146 3147 if (!to_match->clock) 3148 return 0; 3149 3150 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3151 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3152 unsigned int clock1, clock2; 3153 3154 /* Make sure to also match alternate clocks */ 3155 clock1 = hdmi_mode->clock; 3156 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3157 3158 if (abs(to_match->clock - clock1) > clock_tolerance && 3159 abs(to_match->clock - clock2) > clock_tolerance) 3160 continue; 3161 3162 if (drm_mode_match(to_match, hdmi_mode, match_flags)) 3163 return vic; 3164 } 3165 3166 return 0; 3167 } 3168 3169 /* 3170 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 3171 * @to_match: display mode 3172 * 3173 * An HDMI mode is one defined in the HDMI vendor specific block. 3174 * 3175 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 3176 */ 3177 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 3178 { 3179 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3180 u8 vic; 3181 3182 if (!to_match->clock) 3183 return 0; 3184 3185 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3186 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3187 unsigned int clock1, clock2; 3188 3189 /* Make sure to also match alternate clocks */ 3190 clock1 = hdmi_mode->clock; 3191 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3192 3193 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 3194 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 3195 drm_mode_match(to_match, hdmi_mode, match_flags)) 3196 return vic; 3197 } 3198 return 0; 3199 } 3200 3201 static bool drm_valid_hdmi_vic(u8 vic) 3202 { 3203 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 3204 } 3205 3206 static int 3207 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) 3208 { 3209 struct drm_device *dev = connector->dev; 3210 struct drm_display_mode *mode, *tmp; 3211 LIST_HEAD(list); 3212 int modes = 0; 3213 3214 /* Don't add CEA modes if the CEA extension block is missing */ 3215 if (!drm_find_cea_extension(edid)) 3216 return 0; 3217 3218 /* 3219 * Go through all probed modes and create a new mode 3220 * with the alternate clock for certain CEA modes. 3221 */ 3222 list_for_each_entry(mode, &connector->probed_modes, head) { 3223 const struct drm_display_mode *cea_mode = NULL; 3224 struct drm_display_mode *newmode; 3225 u8 vic = drm_match_cea_mode(mode); 3226 unsigned int clock1, clock2; 3227 3228 if (drm_valid_cea_vic(vic)) { 3229 cea_mode = &edid_cea_modes[vic]; 3230 clock2 = cea_mode_alternate_clock(cea_mode); 3231 } else { 3232 vic = drm_match_hdmi_mode(mode); 3233 if (drm_valid_hdmi_vic(vic)) { 3234 cea_mode = &edid_4k_modes[vic]; 3235 clock2 = hdmi_mode_alternate_clock(cea_mode); 3236 } 3237 } 3238 3239 if (!cea_mode) 3240 continue; 3241 3242 clock1 = cea_mode->clock; 3243 3244 if (clock1 == clock2) 3245 continue; 3246 3247 if (mode->clock != clock1 && mode->clock != clock2) 3248 continue; 3249 3250 newmode = drm_mode_duplicate(dev, cea_mode); 3251 if (!newmode) 3252 continue; 3253 3254 /* Carry over the stereo flags */ 3255 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 3256 3257 /* 3258 * The current mode could be either variant. Make 3259 * sure to pick the "other" clock for the new mode. 3260 */ 3261 if (mode->clock != clock1) 3262 newmode->clock = clock1; 3263 else 3264 newmode->clock = clock2; 3265 3266 list_add_tail(&newmode->head, &list); 3267 } 3268 3269 list_for_each_entry_safe(mode, tmp, &list, head) { 3270 list_del(&mode->head); 3271 drm_mode_probed_add(connector, mode); 3272 modes++; 3273 } 3274 3275 return modes; 3276 } 3277 3278 static u8 svd_to_vic(u8 svd) 3279 { 3280 /* 0-6 bit vic, 7th bit native mode indicator */ 3281 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 3282 return svd & 127; 3283 3284 return svd; 3285 } 3286 3287 static struct drm_display_mode * 3288 drm_display_mode_from_vic_index(struct drm_connector *connector, 3289 const u8 *video_db, u8 video_len, 3290 u8 video_index) 3291 { 3292 struct drm_device *dev = connector->dev; 3293 struct drm_display_mode *newmode; 3294 u8 vic; 3295 3296 if (video_db == NULL || video_index >= video_len) 3297 return NULL; 3298 3299 /* CEA modes are numbered 1..127 */ 3300 vic = svd_to_vic(video_db[video_index]); 3301 if (!drm_valid_cea_vic(vic)) 3302 return NULL; 3303 3304 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]); 3305 if (!newmode) 3306 return NULL; 3307 3308 newmode->vrefresh = 0; 3309 3310 return newmode; 3311 } 3312 3313 /* 3314 * do_y420vdb_modes - Parse YCBCR 420 only modes 3315 * @connector: connector corresponding to the HDMI sink 3316 * @svds: start of the data block of CEA YCBCR 420 VDB 3317 * @len: length of the CEA YCBCR 420 VDB 3318 * 3319 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 3320 * which contains modes which can be supported in YCBCR 420 3321 * output format only. 3322 */ 3323 static int do_y420vdb_modes(struct drm_connector *connector, 3324 const u8 *svds, u8 svds_len) 3325 { 3326 int modes = 0, i; 3327 struct drm_device *dev = connector->dev; 3328 struct drm_display_info *info = &connector->display_info; 3329 struct drm_hdmi_info *hdmi = &info->hdmi; 3330 3331 for (i = 0; i < svds_len; i++) { 3332 u8 vic = svd_to_vic(svds[i]); 3333 struct drm_display_mode *newmode; 3334 3335 if (!drm_valid_cea_vic(vic)) 3336 continue; 3337 3338 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]); 3339 if (!newmode) 3340 break; 3341 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 3342 drm_mode_probed_add(connector, newmode); 3343 modes++; 3344 } 3345 3346 if (modes > 0) 3347 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3348 return modes; 3349 } 3350 3351 /* 3352 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap 3353 * @connector: connector corresponding to the HDMI sink 3354 * @vic: CEA vic for the video mode to be added in the map 3355 * 3356 * Makes an entry for a videomode in the YCBCR 420 bitmap 3357 */ 3358 static void 3359 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd) 3360 { 3361 u8 vic = svd_to_vic(svd); 3362 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3363 3364 if (!drm_valid_cea_vic(vic)) 3365 return; 3366 3367 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 3368 } 3369 3370 static int 3371 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 3372 { 3373 int i, modes = 0; 3374 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3375 3376 for (i = 0; i < len; i++) { 3377 struct drm_display_mode *mode; 3378 mode = drm_display_mode_from_vic_index(connector, db, len, i); 3379 if (mode) { 3380 /* 3381 * YCBCR420 capability block contains a bitmap which 3382 * gives the index of CEA modes from CEA VDB, which 3383 * can support YCBCR 420 sampling output also (apart 3384 * from RGB/YCBCR444 etc). 3385 * For example, if the bit 0 in bitmap is set, 3386 * first mode in VDB can support YCBCR420 output too. 3387 * Add YCBCR420 modes only if sink is HDMI 2.0 capable. 3388 */ 3389 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) 3390 drm_add_cmdb_modes(connector, db[i]); 3391 3392 drm_mode_probed_add(connector, mode); 3393 modes++; 3394 } 3395 } 3396 3397 return modes; 3398 } 3399 3400 struct stereo_mandatory_mode { 3401 int width, height, vrefresh; 3402 unsigned int flags; 3403 }; 3404 3405 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 3406 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3407 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3408 { 1920, 1080, 50, 3409 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3410 { 1920, 1080, 60, 3411 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3412 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3413 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3414 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3415 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 3416 }; 3417 3418 static bool 3419 stereo_match_mandatory(const struct drm_display_mode *mode, 3420 const struct stereo_mandatory_mode *stereo_mode) 3421 { 3422 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 3423 3424 return mode->hdisplay == stereo_mode->width && 3425 mode->vdisplay == stereo_mode->height && 3426 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 3427 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 3428 } 3429 3430 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 3431 { 3432 struct drm_device *dev = connector->dev; 3433 const struct drm_display_mode *mode; 3434 struct list_head stereo_modes; 3435 int modes = 0, i; 3436 3437 INIT_LIST_HEAD(&stereo_modes); 3438 3439 list_for_each_entry(mode, &connector->probed_modes, head) { 3440 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 3441 const struct stereo_mandatory_mode *mandatory; 3442 struct drm_display_mode *new_mode; 3443 3444 if (!stereo_match_mandatory(mode, 3445 &stereo_mandatory_modes[i])) 3446 continue; 3447 3448 mandatory = &stereo_mandatory_modes[i]; 3449 new_mode = drm_mode_duplicate(dev, mode); 3450 if (!new_mode) 3451 continue; 3452 3453 new_mode->flags |= mandatory->flags; 3454 list_add_tail(&new_mode->head, &stereo_modes); 3455 modes++; 3456 } 3457 } 3458 3459 list_splice_tail(&stereo_modes, &connector->probed_modes); 3460 3461 return modes; 3462 } 3463 3464 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 3465 { 3466 struct drm_device *dev = connector->dev; 3467 struct drm_display_mode *newmode; 3468 3469 if (!drm_valid_hdmi_vic(vic)) { 3470 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 3471 return 0; 3472 } 3473 3474 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 3475 if (!newmode) 3476 return 0; 3477 3478 drm_mode_probed_add(connector, newmode); 3479 3480 return 1; 3481 } 3482 3483 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 3484 const u8 *video_db, u8 video_len, u8 video_index) 3485 { 3486 struct drm_display_mode *newmode; 3487 int modes = 0; 3488 3489 if (structure & (1 << 0)) { 3490 newmode = drm_display_mode_from_vic_index(connector, video_db, 3491 video_len, 3492 video_index); 3493 if (newmode) { 3494 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 3495 drm_mode_probed_add(connector, newmode); 3496 modes++; 3497 } 3498 } 3499 if (structure & (1 << 6)) { 3500 newmode = drm_display_mode_from_vic_index(connector, video_db, 3501 video_len, 3502 video_index); 3503 if (newmode) { 3504 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3505 drm_mode_probed_add(connector, newmode); 3506 modes++; 3507 } 3508 } 3509 if (structure & (1 << 8)) { 3510 newmode = drm_display_mode_from_vic_index(connector, video_db, 3511 video_len, 3512 video_index); 3513 if (newmode) { 3514 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3515 drm_mode_probed_add(connector, newmode); 3516 modes++; 3517 } 3518 } 3519 3520 return modes; 3521 } 3522 3523 /* 3524 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 3525 * @connector: connector corresponding to the HDMI sink 3526 * @db: start of the CEA vendor specific block 3527 * @len: length of the CEA block payload, ie. one can access up to db[len] 3528 * 3529 * Parses the HDMI VSDB looking for modes to add to @connector. This function 3530 * also adds the stereo 3d modes when applicable. 3531 */ 3532 static int 3533 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 3534 const u8 *video_db, u8 video_len) 3535 { 3536 struct drm_display_info *info = &connector->display_info; 3537 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 3538 u8 vic_len, hdmi_3d_len = 0; 3539 u16 mask; 3540 u16 structure_all; 3541 3542 if (len < 8) 3543 goto out; 3544 3545 /* no HDMI_Video_Present */ 3546 if (!(db[8] & (1 << 5))) 3547 goto out; 3548 3549 /* Latency_Fields_Present */ 3550 if (db[8] & (1 << 7)) 3551 offset += 2; 3552 3553 /* I_Latency_Fields_Present */ 3554 if (db[8] & (1 << 6)) 3555 offset += 2; 3556 3557 /* the declared length is not long enough for the 2 first bytes 3558 * of additional video format capabilities */ 3559 if (len < (8 + offset + 2)) 3560 goto out; 3561 3562 /* 3D_Present */ 3563 offset++; 3564 if (db[8 + offset] & (1 << 7)) { 3565 modes += add_hdmi_mandatory_stereo_modes(connector); 3566 3567 /* 3D_Multi_present */ 3568 multi_present = (db[8 + offset] & 0x60) >> 5; 3569 } 3570 3571 offset++; 3572 vic_len = db[8 + offset] >> 5; 3573 hdmi_3d_len = db[8 + offset] & 0x1f; 3574 3575 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 3576 u8 vic; 3577 3578 vic = db[9 + offset + i]; 3579 modes += add_hdmi_mode(connector, vic); 3580 } 3581 offset += 1 + vic_len; 3582 3583 if (multi_present == 1) 3584 multi_len = 2; 3585 else if (multi_present == 2) 3586 multi_len = 4; 3587 else 3588 multi_len = 0; 3589 3590 if (len < (8 + offset + hdmi_3d_len - 1)) 3591 goto out; 3592 3593 if (hdmi_3d_len < multi_len) 3594 goto out; 3595 3596 if (multi_present == 1 || multi_present == 2) { 3597 /* 3D_Structure_ALL */ 3598 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 3599 3600 /* check if 3D_MASK is present */ 3601 if (multi_present == 2) 3602 mask = (db[10 + offset] << 8) | db[11 + offset]; 3603 else 3604 mask = 0xffff; 3605 3606 for (i = 0; i < 16; i++) { 3607 if (mask & (1 << i)) 3608 modes += add_3d_struct_modes(connector, 3609 structure_all, 3610 video_db, 3611 video_len, i); 3612 } 3613 } 3614 3615 offset += multi_len; 3616 3617 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 3618 int vic_index; 3619 struct drm_display_mode *newmode = NULL; 3620 unsigned int newflag = 0; 3621 bool detail_present; 3622 3623 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 3624 3625 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 3626 break; 3627 3628 /* 2D_VIC_order_X */ 3629 vic_index = db[8 + offset + i] >> 4; 3630 3631 /* 3D_Structure_X */ 3632 switch (db[8 + offset + i] & 0x0f) { 3633 case 0: 3634 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 3635 break; 3636 case 6: 3637 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3638 break; 3639 case 8: 3640 /* 3D_Detail_X */ 3641 if ((db[9 + offset + i] >> 4) == 1) 3642 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3643 break; 3644 } 3645 3646 if (newflag != 0) { 3647 newmode = drm_display_mode_from_vic_index(connector, 3648 video_db, 3649 video_len, 3650 vic_index); 3651 3652 if (newmode) { 3653 newmode->flags |= newflag; 3654 drm_mode_probed_add(connector, newmode); 3655 modes++; 3656 } 3657 } 3658 3659 if (detail_present) 3660 i++; 3661 } 3662 3663 out: 3664 if (modes > 0) 3665 info->has_hdmi_infoframe = true; 3666 return modes; 3667 } 3668 3669 static int 3670 cea_db_payload_len(const u8 *db) 3671 { 3672 return db[0] & 0x1f; 3673 } 3674 3675 static int 3676 cea_db_extended_tag(const u8 *db) 3677 { 3678 return db[1]; 3679 } 3680 3681 static int 3682 cea_db_tag(const u8 *db) 3683 { 3684 return db[0] >> 5; 3685 } 3686 3687 static int 3688 cea_revision(const u8 *cea) 3689 { 3690 return cea[1]; 3691 } 3692 3693 static int 3694 cea_db_offsets(const u8 *cea, int *start, int *end) 3695 { 3696 /* DisplayID CTA extension blocks and top-level CEA EDID 3697 * block header definitions differ in the following bytes: 3698 * 1) Byte 2 of the header specifies length differently, 3699 * 2) Byte 3 is only present in the CEA top level block. 3700 * 3701 * The different definitions for byte 2 follow. 3702 * 3703 * DisplayID CTA extension block defines byte 2 as: 3704 * Number of payload bytes 3705 * 3706 * CEA EDID block defines byte 2 as: 3707 * Byte number (decimal) within this block where the 18-byte 3708 * DTDs begin. If no non-DTD data is present in this extension 3709 * block, the value should be set to 04h (the byte after next). 3710 * If set to 00h, there are no DTDs present in this block and 3711 * no non-DTD data. 3712 */ 3713 if (cea[0] == DATA_BLOCK_CTA) { 3714 *start = 3; 3715 *end = *start + cea[2]; 3716 } else if (cea[0] == CEA_EXT) { 3717 /* Data block offset in CEA extension block */ 3718 *start = 4; 3719 *end = cea[2]; 3720 if (*end == 0) 3721 *end = 127; 3722 if (*end < 4 || *end > 127) 3723 return -ERANGE; 3724 } else { 3725 return -ENOTSUPP; 3726 } 3727 3728 return 0; 3729 } 3730 3731 static bool cea_db_is_hdmi_vsdb(const u8 *db) 3732 { 3733 int hdmi_id; 3734 3735 if (cea_db_tag(db) != VENDOR_BLOCK) 3736 return false; 3737 3738 if (cea_db_payload_len(db) < 5) 3739 return false; 3740 3741 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 3742 3743 return hdmi_id == HDMI_IEEE_OUI; 3744 } 3745 3746 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db) 3747 { 3748 unsigned int oui; 3749 3750 if (cea_db_tag(db) != VENDOR_BLOCK) 3751 return false; 3752 3753 if (cea_db_payload_len(db) < 7) 3754 return false; 3755 3756 oui = db[3] << 16 | db[2] << 8 | db[1]; 3757 3758 return oui == HDMI_FORUM_IEEE_OUI; 3759 } 3760 3761 static bool cea_db_is_vcdb(const u8 *db) 3762 { 3763 if (cea_db_tag(db) != USE_EXTENDED_TAG) 3764 return false; 3765 3766 if (cea_db_payload_len(db) != 2) 3767 return false; 3768 3769 if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK) 3770 return false; 3771 3772 return true; 3773 } 3774 3775 static bool cea_db_is_y420cmdb(const u8 *db) 3776 { 3777 if (cea_db_tag(db) != USE_EXTENDED_TAG) 3778 return false; 3779 3780 if (!cea_db_payload_len(db)) 3781 return false; 3782 3783 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB) 3784 return false; 3785 3786 return true; 3787 } 3788 3789 static bool cea_db_is_y420vdb(const u8 *db) 3790 { 3791 if (cea_db_tag(db) != USE_EXTENDED_TAG) 3792 return false; 3793 3794 if (!cea_db_payload_len(db)) 3795 return false; 3796 3797 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420) 3798 return false; 3799 3800 return true; 3801 } 3802 3803 #define for_each_cea_db(cea, i, start, end) \ 3804 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 3805 3806 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector, 3807 const u8 *db) 3808 { 3809 struct drm_display_info *info = &connector->display_info; 3810 struct drm_hdmi_info *hdmi = &info->hdmi; 3811 u8 map_len = cea_db_payload_len(db) - 1; 3812 u8 count; 3813 u64 map = 0; 3814 3815 if (map_len == 0) { 3816 /* All CEA modes support ycbcr420 sampling also.*/ 3817 hdmi->y420_cmdb_map = U64_MAX; 3818 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3819 return; 3820 } 3821 3822 /* 3823 * This map indicates which of the existing CEA block modes 3824 * from VDB can support YCBCR420 output too. So if bit=0 is 3825 * set, first mode from VDB can support YCBCR420 output too. 3826 * We will parse and keep this map, before parsing VDB itself 3827 * to avoid going through the same block again and again. 3828 * 3829 * Spec is not clear about max possible size of this block. 3830 * Clamping max bitmap block size at 8 bytes. Every byte can 3831 * address 8 CEA modes, in this way this map can address 3832 * 8*8 = first 64 SVDs. 3833 */ 3834 if (WARN_ON_ONCE(map_len > 8)) 3835 map_len = 8; 3836 3837 for (count = 0; count < map_len; count++) 3838 map |= (u64)db[2 + count] << (8 * count); 3839 3840 if (map) 3841 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3842 3843 hdmi->y420_cmdb_map = map; 3844 } 3845 3846 static int 3847 add_cea_modes(struct drm_connector *connector, struct edid *edid) 3848 { 3849 const u8 *cea = drm_find_cea_extension(edid); 3850 const u8 *db, *hdmi = NULL, *video = NULL; 3851 u8 dbl, hdmi_len, video_len = 0; 3852 int modes = 0; 3853 3854 if (cea && cea_revision(cea) >= 3) { 3855 int i, start, end; 3856 3857 if (cea_db_offsets(cea, &start, &end)) 3858 return 0; 3859 3860 for_each_cea_db(cea, i, start, end) { 3861 db = &cea[i]; 3862 dbl = cea_db_payload_len(db); 3863 3864 if (cea_db_tag(db) == VIDEO_BLOCK) { 3865 video = db + 1; 3866 video_len = dbl; 3867 modes += do_cea_modes(connector, video, dbl); 3868 } else if (cea_db_is_hdmi_vsdb(db)) { 3869 hdmi = db; 3870 hdmi_len = dbl; 3871 } else if (cea_db_is_y420vdb(db)) { 3872 const u8 *vdb420 = &db[2]; 3873 3874 /* Add 4:2:0(only) modes present in EDID */ 3875 modes += do_y420vdb_modes(connector, 3876 vdb420, 3877 dbl - 1); 3878 } 3879 } 3880 } 3881 3882 /* 3883 * We parse the HDMI VSDB after having added the cea modes as we will 3884 * be patching their flags when the sink supports stereo 3D. 3885 */ 3886 if (hdmi) 3887 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, 3888 video_len); 3889 3890 return modes; 3891 } 3892 3893 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 3894 { 3895 const struct drm_display_mode *cea_mode; 3896 int clock1, clock2, clock; 3897 u8 vic; 3898 const char *type; 3899 3900 /* 3901 * allow 5kHz clock difference either way to account for 3902 * the 10kHz clock resolution limit of detailed timings. 3903 */ 3904 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 3905 if (drm_valid_cea_vic(vic)) { 3906 type = "CEA"; 3907 cea_mode = &edid_cea_modes[vic]; 3908 clock1 = cea_mode->clock; 3909 clock2 = cea_mode_alternate_clock(cea_mode); 3910 } else { 3911 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 3912 if (drm_valid_hdmi_vic(vic)) { 3913 type = "HDMI"; 3914 cea_mode = &edid_4k_modes[vic]; 3915 clock1 = cea_mode->clock; 3916 clock2 = hdmi_mode_alternate_clock(cea_mode); 3917 } else { 3918 return; 3919 } 3920 } 3921 3922 /* pick whichever is closest */ 3923 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 3924 clock = clock1; 3925 else 3926 clock = clock2; 3927 3928 if (mode->clock == clock) 3929 return; 3930 3931 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 3932 type, vic, mode->clock, clock); 3933 mode->clock = clock; 3934 } 3935 3936 static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db) 3937 { 3938 if (cea_db_tag(db) != USE_EXTENDED_TAG) 3939 return false; 3940 3941 if (db[1] != HDR_STATIC_METADATA_BLOCK) 3942 return false; 3943 3944 if (cea_db_payload_len(db) < 3) 3945 return false; 3946 3947 return true; 3948 } 3949 3950 static uint8_t eotf_supported(const u8 *edid_ext) 3951 { 3952 return edid_ext[2] & 3953 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) | 3954 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) | 3955 BIT(HDMI_EOTF_SMPTE_ST2084) | 3956 BIT(HDMI_EOTF_BT_2100_HLG)); 3957 } 3958 3959 static uint8_t hdr_metadata_type(const u8 *edid_ext) 3960 { 3961 return edid_ext[3] & 3962 BIT(HDMI_STATIC_METADATA_TYPE1); 3963 } 3964 3965 static void 3966 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db) 3967 { 3968 u16 len; 3969 3970 len = cea_db_payload_len(db); 3971 3972 connector->hdr_sink_metadata.hdmi_type1.eotf = 3973 eotf_supported(db); 3974 connector->hdr_sink_metadata.hdmi_type1.metadata_type = 3975 hdr_metadata_type(db); 3976 3977 if (len >= 4) 3978 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4]; 3979 if (len >= 5) 3980 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5]; 3981 if (len >= 6) 3982 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6]; 3983 } 3984 3985 static void 3986 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 3987 { 3988 u8 len = cea_db_payload_len(db); 3989 3990 if (len >= 6 && (db[6] & (1 << 7))) 3991 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI; 3992 if (len >= 8) { 3993 connector->latency_present[0] = db[8] >> 7; 3994 connector->latency_present[1] = (db[8] >> 6) & 1; 3995 } 3996 if (len >= 9) 3997 connector->video_latency[0] = db[9]; 3998 if (len >= 10) 3999 connector->audio_latency[0] = db[10]; 4000 if (len >= 11) 4001 connector->video_latency[1] = db[11]; 4002 if (len >= 12) 4003 connector->audio_latency[1] = db[12]; 4004 4005 DRM_DEBUG_KMS("HDMI: latency present %d %d, " 4006 "video latency %d %d, " 4007 "audio latency %d %d\n", 4008 connector->latency_present[0], 4009 connector->latency_present[1], 4010 connector->video_latency[0], 4011 connector->video_latency[1], 4012 connector->audio_latency[0], 4013 connector->audio_latency[1]); 4014 } 4015 4016 static void 4017 monitor_name(struct detailed_timing *t, void *data) 4018 { 4019 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME) 4020 *(u8 **)data = t->data.other_data.data.str.str; 4021 } 4022 4023 static int get_monitor_name(struct edid *edid, char name[13]) 4024 { 4025 char *edid_name = NULL; 4026 int mnl; 4027 4028 if (!edid || !name) 4029 return 0; 4030 4031 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name); 4032 for (mnl = 0; edid_name && mnl < 13; mnl++) { 4033 if (edid_name[mnl] == 0x0a) 4034 break; 4035 4036 name[mnl] = edid_name[mnl]; 4037 } 4038 4039 return mnl; 4040 } 4041 4042 /** 4043 * drm_edid_get_monitor_name - fetch the monitor name from the edid 4044 * @edid: monitor EDID information 4045 * @name: pointer to a character array to hold the name of the monitor 4046 * @bufsize: The size of the name buffer (should be at least 14 chars.) 4047 * 4048 */ 4049 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize) 4050 { 4051 int name_length; 4052 char buf[13]; 4053 4054 if (bufsize <= 0) 4055 return; 4056 4057 name_length = min(get_monitor_name(edid, buf), bufsize - 1); 4058 memcpy(name, buf, name_length); 4059 name[name_length] = '\0'; 4060 } 4061 EXPORT_SYMBOL(drm_edid_get_monitor_name); 4062 4063 static void clear_eld(struct drm_connector *connector) 4064 { 4065 memset(connector->eld, 0, sizeof(connector->eld)); 4066 4067 connector->latency_present[0] = false; 4068 connector->latency_present[1] = false; 4069 connector->video_latency[0] = 0; 4070 connector->audio_latency[0] = 0; 4071 connector->video_latency[1] = 0; 4072 connector->audio_latency[1] = 0; 4073 } 4074 4075 /* 4076 * drm_edid_to_eld - build ELD from EDID 4077 * @connector: connector corresponding to the HDMI/DP sink 4078 * @edid: EDID to parse 4079 * 4080 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 4081 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 4082 */ 4083 static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 4084 { 4085 uint8_t *eld = connector->eld; 4086 u8 *cea; 4087 u8 *db; 4088 int total_sad_count = 0; 4089 int mnl; 4090 int dbl; 4091 4092 clear_eld(connector); 4093 4094 if (!edid) 4095 return; 4096 4097 cea = drm_find_cea_extension(edid); 4098 if (!cea) { 4099 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 4100 return; 4101 } 4102 4103 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]); 4104 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]); 4105 4106 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT; 4107 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl; 4108 4109 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D; 4110 4111 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0]; 4112 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1]; 4113 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0]; 4114 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1]; 4115 4116 if (cea_revision(cea) >= 3) { 4117 int i, start, end; 4118 4119 if (cea_db_offsets(cea, &start, &end)) { 4120 start = 0; 4121 end = 0; 4122 } 4123 4124 for_each_cea_db(cea, i, start, end) { 4125 db = &cea[i]; 4126 dbl = cea_db_payload_len(db); 4127 4128 switch (cea_db_tag(db)) { 4129 int sad_count; 4130 4131 case AUDIO_BLOCK: 4132 /* Audio Data Block, contains SADs */ 4133 sad_count = min(dbl / 3, 15 - total_sad_count); 4134 if (sad_count >= 1) 4135 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)], 4136 &db[1], sad_count * 3); 4137 total_sad_count += sad_count; 4138 break; 4139 case SPEAKER_BLOCK: 4140 /* Speaker Allocation Data Block */ 4141 if (dbl >= 1) 4142 eld[DRM_ELD_SPEAKER] = db[1]; 4143 break; 4144 case VENDOR_BLOCK: 4145 /* HDMI Vendor-Specific Data Block */ 4146 if (cea_db_is_hdmi_vsdb(db)) 4147 drm_parse_hdmi_vsdb_audio(connector, db); 4148 break; 4149 default: 4150 break; 4151 } 4152 } 4153 } 4154 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT; 4155 4156 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 4157 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 4158 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 4159 else 4160 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 4161 4162 eld[DRM_ELD_BASELINE_ELD_LEN] = 4163 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 4164 4165 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", 4166 drm_eld_size(eld), total_sad_count); 4167 } 4168 4169 /** 4170 * drm_edid_to_sad - extracts SADs from EDID 4171 * @edid: EDID to parse 4172 * @sads: pointer that will be set to the extracted SADs 4173 * 4174 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 4175 * 4176 * Note: The returned pointer needs to be freed using kfree(). 4177 * 4178 * Return: The number of found SADs or negative number on error. 4179 */ 4180 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) 4181 { 4182 int count = 0; 4183 int i, start, end, dbl; 4184 u8 *cea; 4185 4186 cea = drm_find_cea_extension(edid); 4187 if (!cea) { 4188 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4189 return -ENOENT; 4190 } 4191 4192 if (cea_revision(cea) < 3) { 4193 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4194 return -ENOTSUPP; 4195 } 4196 4197 if (cea_db_offsets(cea, &start, &end)) { 4198 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4199 return -EPROTO; 4200 } 4201 4202 for_each_cea_db(cea, i, start, end) { 4203 u8 *db = &cea[i]; 4204 4205 if (cea_db_tag(db) == AUDIO_BLOCK) { 4206 int j; 4207 dbl = cea_db_payload_len(db); 4208 4209 count = dbl / 3; /* SAD is 3B */ 4210 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 4211 if (!*sads) 4212 return -ENOMEM; 4213 for (j = 0; j < count; j++) { 4214 u8 *sad = &db[1 + j * 3]; 4215 4216 (*sads)[j].format = (sad[0] & 0x78) >> 3; 4217 (*sads)[j].channels = sad[0] & 0x7; 4218 (*sads)[j].freq = sad[1] & 0x7F; 4219 (*sads)[j].byte2 = sad[2]; 4220 } 4221 break; 4222 } 4223 } 4224 4225 return count; 4226 } 4227 EXPORT_SYMBOL(drm_edid_to_sad); 4228 4229 /** 4230 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 4231 * @edid: EDID to parse 4232 * @sadb: pointer to the speaker block 4233 * 4234 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 4235 * 4236 * Note: The returned pointer needs to be freed using kfree(). 4237 * 4238 * Return: The number of found Speaker Allocation Blocks or negative number on 4239 * error. 4240 */ 4241 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) 4242 { 4243 int count = 0; 4244 int i, start, end, dbl; 4245 const u8 *cea; 4246 4247 cea = drm_find_cea_extension(edid); 4248 if (!cea) { 4249 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4250 return -ENOENT; 4251 } 4252 4253 if (cea_revision(cea) < 3) { 4254 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4255 return -ENOTSUPP; 4256 } 4257 4258 if (cea_db_offsets(cea, &start, &end)) { 4259 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4260 return -EPROTO; 4261 } 4262 4263 for_each_cea_db(cea, i, start, end) { 4264 const u8 *db = &cea[i]; 4265 4266 if (cea_db_tag(db) == SPEAKER_BLOCK) { 4267 dbl = cea_db_payload_len(db); 4268 4269 /* Speaker Allocation Data Block */ 4270 if (dbl == 3) { 4271 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); 4272 if (!*sadb) 4273 return -ENOMEM; 4274 count = dbl; 4275 break; 4276 } 4277 } 4278 } 4279 4280 return count; 4281 } 4282 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 4283 4284 /** 4285 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 4286 * @connector: connector associated with the HDMI/DP sink 4287 * @mode: the display mode 4288 * 4289 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 4290 * the sink doesn't support audio or video. 4291 */ 4292 int drm_av_sync_delay(struct drm_connector *connector, 4293 const struct drm_display_mode *mode) 4294 { 4295 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 4296 int a, v; 4297 4298 if (!connector->latency_present[0]) 4299 return 0; 4300 if (!connector->latency_present[1]) 4301 i = 0; 4302 4303 a = connector->audio_latency[i]; 4304 v = connector->video_latency[i]; 4305 4306 /* 4307 * HDMI/DP sink doesn't support audio or video? 4308 */ 4309 if (a == 255 || v == 255) 4310 return 0; 4311 4312 /* 4313 * Convert raw EDID values to millisecond. 4314 * Treat unknown latency as 0ms. 4315 */ 4316 if (a) 4317 a = min(2 * (a - 1), 500); 4318 if (v) 4319 v = min(2 * (v - 1), 500); 4320 4321 return max(v - a, 0); 4322 } 4323 EXPORT_SYMBOL(drm_av_sync_delay); 4324 4325 /** 4326 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 4327 * @edid: monitor EDID information 4328 * 4329 * Parse the CEA extension according to CEA-861-B. 4330 * 4331 * Return: True if the monitor is HDMI, false if not or unknown. 4332 */ 4333 bool drm_detect_hdmi_monitor(struct edid *edid) 4334 { 4335 u8 *edid_ext; 4336 int i; 4337 int start_offset, end_offset; 4338 4339 edid_ext = drm_find_cea_extension(edid); 4340 if (!edid_ext) 4341 return false; 4342 4343 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4344 return false; 4345 4346 /* 4347 * Because HDMI identifier is in Vendor Specific Block, 4348 * search it from all data blocks of CEA extension. 4349 */ 4350 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4351 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 4352 return true; 4353 } 4354 4355 return false; 4356 } 4357 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 4358 4359 /** 4360 * drm_detect_monitor_audio - check monitor audio capability 4361 * @edid: EDID block to scan 4362 * 4363 * Monitor should have CEA extension block. 4364 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 4365 * audio' only. If there is any audio extension block and supported 4366 * audio format, assume at least 'basic audio' support, even if 'basic 4367 * audio' is not defined in EDID. 4368 * 4369 * Return: True if the monitor supports audio, false otherwise. 4370 */ 4371 bool drm_detect_monitor_audio(struct edid *edid) 4372 { 4373 u8 *edid_ext; 4374 int i, j; 4375 bool has_audio = false; 4376 int start_offset, end_offset; 4377 4378 edid_ext = drm_find_cea_extension(edid); 4379 if (!edid_ext) 4380 goto end; 4381 4382 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 4383 4384 if (has_audio) { 4385 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 4386 goto end; 4387 } 4388 4389 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4390 goto end; 4391 4392 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4393 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 4394 has_audio = true; 4395 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 4396 DRM_DEBUG_KMS("CEA audio format %d\n", 4397 (edid_ext[i + j] >> 3) & 0xf); 4398 goto end; 4399 } 4400 } 4401 end: 4402 return has_audio; 4403 } 4404 EXPORT_SYMBOL(drm_detect_monitor_audio); 4405 4406 4407 /** 4408 * drm_default_rgb_quant_range - default RGB quantization range 4409 * @mode: display mode 4410 * 4411 * Determine the default RGB quantization range for the mode, 4412 * as specified in CEA-861. 4413 * 4414 * Return: The default RGB quantization range for the mode 4415 */ 4416 enum hdmi_quantization_range 4417 drm_default_rgb_quant_range(const struct drm_display_mode *mode) 4418 { 4419 /* All CEA modes other than VIC 1 use limited quantization range. */ 4420 return drm_match_cea_mode(mode) > 1 ? 4421 HDMI_QUANTIZATION_RANGE_LIMITED : 4422 HDMI_QUANTIZATION_RANGE_FULL; 4423 } 4424 EXPORT_SYMBOL(drm_default_rgb_quant_range); 4425 4426 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db) 4427 { 4428 struct drm_display_info *info = &connector->display_info; 4429 4430 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]); 4431 4432 if (db[2] & EDID_CEA_VCDB_QS) 4433 info->rgb_quant_range_selectable = true; 4434 } 4435 4436 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 4437 const u8 *db) 4438 { 4439 u8 dc_mask; 4440 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 4441 4442 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 4443 hdmi->y420_dc_modes = dc_mask; 4444 } 4445 4446 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector, 4447 const u8 *hf_vsdb) 4448 { 4449 struct drm_display_info *display = &connector->display_info; 4450 struct drm_hdmi_info *hdmi = &display->hdmi; 4451 4452 display->has_hdmi_infoframe = true; 4453 4454 if (hf_vsdb[6] & 0x80) { 4455 hdmi->scdc.supported = true; 4456 if (hf_vsdb[6] & 0x40) 4457 hdmi->scdc.read_request = true; 4458 } 4459 4460 /* 4461 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 4462 * And as per the spec, three factors confirm this: 4463 * * Availability of a HF-VSDB block in EDID (check) 4464 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 4465 * * SCDC support available (let's check) 4466 * Lets check it out. 4467 */ 4468 4469 if (hf_vsdb[5]) { 4470 /* max clock is 5000 KHz times block value */ 4471 u32 max_tmds_clock = hf_vsdb[5] * 5000; 4472 struct drm_scdc *scdc = &hdmi->scdc; 4473 4474 if (max_tmds_clock > 340000) { 4475 display->max_tmds_clock = max_tmds_clock; 4476 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n", 4477 display->max_tmds_clock); 4478 } 4479 4480 if (scdc->supported) { 4481 scdc->scrambling.supported = true; 4482 4483 /* Few sinks support scrambling for cloks < 340M */ 4484 if ((hf_vsdb[6] & 0x8)) 4485 scdc->scrambling.low_rates = true; 4486 } 4487 } 4488 4489 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb); 4490 } 4491 4492 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 4493 const u8 *hdmi) 4494 { 4495 struct drm_display_info *info = &connector->display_info; 4496 unsigned int dc_bpc = 0; 4497 4498 /* HDMI supports at least 8 bpc */ 4499 info->bpc = 8; 4500 4501 if (cea_db_payload_len(hdmi) < 6) 4502 return; 4503 4504 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 4505 dc_bpc = 10; 4506 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 4507 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 4508 connector->name); 4509 } 4510 4511 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 4512 dc_bpc = 12; 4513 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 4514 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 4515 connector->name); 4516 } 4517 4518 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 4519 dc_bpc = 16; 4520 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 4521 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 4522 connector->name); 4523 } 4524 4525 if (dc_bpc == 0) { 4526 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 4527 connector->name); 4528 return; 4529 } 4530 4531 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 4532 connector->name, dc_bpc); 4533 info->bpc = dc_bpc; 4534 4535 /* 4536 * Deep color support mandates RGB444 support for all video 4537 * modes and forbids YCRCB422 support for all video modes per 4538 * HDMI 1.3 spec. 4539 */ 4540 info->color_formats = DRM_COLOR_FORMAT_RGB444; 4541 4542 /* YCRCB444 is optional according to spec. */ 4543 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 4544 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4545 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 4546 connector->name); 4547 } 4548 4549 /* 4550 * Spec says that if any deep color mode is supported at all, 4551 * then deep color 36 bit must be supported. 4552 */ 4553 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 4554 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 4555 connector->name); 4556 } 4557 } 4558 4559 static void 4560 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 4561 { 4562 struct drm_display_info *info = &connector->display_info; 4563 u8 len = cea_db_payload_len(db); 4564 4565 if (len >= 6) 4566 info->dvi_dual = db[6] & 1; 4567 if (len >= 7) 4568 info->max_tmds_clock = db[7] * 5000; 4569 4570 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 4571 "max TMDS clock %d kHz\n", 4572 info->dvi_dual, 4573 info->max_tmds_clock); 4574 4575 drm_parse_hdmi_deep_color_info(connector, db); 4576 } 4577 4578 static void drm_parse_cea_ext(struct drm_connector *connector, 4579 const struct edid *edid) 4580 { 4581 struct drm_display_info *info = &connector->display_info; 4582 const u8 *edid_ext; 4583 int i, start, end; 4584 4585 edid_ext = drm_find_cea_extension(edid); 4586 if (!edid_ext) 4587 return; 4588 4589 info->cea_rev = edid_ext[1]; 4590 4591 /* The existence of a CEA block should imply RGB support */ 4592 info->color_formats = DRM_COLOR_FORMAT_RGB444; 4593 if (edid_ext[3] & EDID_CEA_YCRCB444) 4594 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4595 if (edid_ext[3] & EDID_CEA_YCRCB422) 4596 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 4597 4598 if (cea_db_offsets(edid_ext, &start, &end)) 4599 return; 4600 4601 for_each_cea_db(edid_ext, i, start, end) { 4602 const u8 *db = &edid_ext[i]; 4603 4604 if (cea_db_is_hdmi_vsdb(db)) 4605 drm_parse_hdmi_vsdb_video(connector, db); 4606 if (cea_db_is_hdmi_forum_vsdb(db)) 4607 drm_parse_hdmi_forum_vsdb(connector, db); 4608 if (cea_db_is_y420cmdb(db)) 4609 drm_parse_y420cmdb_bitmap(connector, db); 4610 if (cea_db_is_vcdb(db)) 4611 drm_parse_vcdb(connector, db); 4612 if (cea_db_is_hdmi_hdr_metadata_block(db)) 4613 drm_parse_hdr_metadata_block(connector, db); 4614 } 4615 } 4616 4617 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset 4618 * all of the values which would have been set from EDID 4619 */ 4620 void 4621 drm_reset_display_info(struct drm_connector *connector) 4622 { 4623 struct drm_display_info *info = &connector->display_info; 4624 4625 info->width_mm = 0; 4626 info->height_mm = 0; 4627 4628 info->bpc = 0; 4629 info->color_formats = 0; 4630 info->cea_rev = 0; 4631 info->max_tmds_clock = 0; 4632 info->dvi_dual = false; 4633 info->has_hdmi_infoframe = false; 4634 info->rgb_quant_range_selectable = false; 4635 memset(&info->hdmi, 0, sizeof(info->hdmi)); 4636 4637 info->non_desktop = 0; 4638 } 4639 4640 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid) 4641 { 4642 struct drm_display_info *info = &connector->display_info; 4643 4644 u32 quirks = edid_get_quirks(edid); 4645 4646 drm_reset_display_info(connector); 4647 4648 info->width_mm = edid->width_cm * 10; 4649 info->height_mm = edid->height_cm * 10; 4650 4651 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP); 4652 4653 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop); 4654 4655 if (edid->revision < 3) 4656 return quirks; 4657 4658 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 4659 return quirks; 4660 4661 drm_parse_cea_ext(connector, edid); 4662 4663 /* 4664 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 4665 * 4666 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 4667 * tells us to assume 8 bpc color depth if the EDID doesn't have 4668 * extensions which tell otherwise. 4669 */ 4670 if (info->bpc == 0 && edid->revision == 3 && 4671 edid->input & DRM_EDID_DIGITAL_DFP_1_X) { 4672 info->bpc = 8; 4673 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n", 4674 connector->name, info->bpc); 4675 } 4676 4677 /* Only defined for 1.4 with digital displays */ 4678 if (edid->revision < 4) 4679 return quirks; 4680 4681 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 4682 case DRM_EDID_DIGITAL_DEPTH_6: 4683 info->bpc = 6; 4684 break; 4685 case DRM_EDID_DIGITAL_DEPTH_8: 4686 info->bpc = 8; 4687 break; 4688 case DRM_EDID_DIGITAL_DEPTH_10: 4689 info->bpc = 10; 4690 break; 4691 case DRM_EDID_DIGITAL_DEPTH_12: 4692 info->bpc = 12; 4693 break; 4694 case DRM_EDID_DIGITAL_DEPTH_14: 4695 info->bpc = 14; 4696 break; 4697 case DRM_EDID_DIGITAL_DEPTH_16: 4698 info->bpc = 16; 4699 break; 4700 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 4701 default: 4702 info->bpc = 0; 4703 break; 4704 } 4705 4706 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 4707 connector->name, info->bpc); 4708 4709 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 4710 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 4711 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4712 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 4713 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 4714 return quirks; 4715 } 4716 4717 static int validate_displayid(u8 *displayid, int length, int idx) 4718 { 4719 int i; 4720 u8 csum = 0; 4721 struct displayid_hdr *base; 4722 4723 base = (struct displayid_hdr *)&displayid[idx]; 4724 4725 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n", 4726 base->rev, base->bytes, base->prod_id, base->ext_count); 4727 4728 if (base->bytes + 5 > length - idx) 4729 return -EINVAL; 4730 for (i = idx; i <= base->bytes + 5; i++) { 4731 csum += displayid[i]; 4732 } 4733 if (csum) { 4734 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum); 4735 return -EINVAL; 4736 } 4737 return 0; 4738 } 4739 4740 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 4741 struct displayid_detailed_timings_1 *timings) 4742 { 4743 struct drm_display_mode *mode; 4744 unsigned pixel_clock = (timings->pixel_clock[0] | 4745 (timings->pixel_clock[1] << 8) | 4746 (timings->pixel_clock[2] << 16)); 4747 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 4748 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 4749 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 4750 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 4751 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 4752 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 4753 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 4754 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 4755 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 4756 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 4757 mode = drm_mode_create(dev); 4758 if (!mode) 4759 return NULL; 4760 4761 mode->clock = pixel_clock * 10; 4762 mode->hdisplay = hactive; 4763 mode->hsync_start = mode->hdisplay + hsync; 4764 mode->hsync_end = mode->hsync_start + hsync_width; 4765 mode->htotal = mode->hdisplay + hblank; 4766 4767 mode->vdisplay = vactive; 4768 mode->vsync_start = mode->vdisplay + vsync; 4769 mode->vsync_end = mode->vsync_start + vsync_width; 4770 mode->vtotal = mode->vdisplay + vblank; 4771 4772 mode->flags = 0; 4773 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 4774 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 4775 mode->type = DRM_MODE_TYPE_DRIVER; 4776 4777 if (timings->flags & 0x80) 4778 mode->type |= DRM_MODE_TYPE_PREFERRED; 4779 mode->vrefresh = drm_mode_vrefresh(mode); 4780 drm_mode_set_name(mode); 4781 4782 return mode; 4783 } 4784 4785 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 4786 struct displayid_block *block) 4787 { 4788 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 4789 int i; 4790 int num_timings; 4791 struct drm_display_mode *newmode; 4792 int num_modes = 0; 4793 /* blocks must be multiple of 20 bytes length */ 4794 if (block->num_bytes % 20) 4795 return 0; 4796 4797 num_timings = block->num_bytes / 20; 4798 for (i = 0; i < num_timings; i++) { 4799 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 4800 4801 newmode = drm_mode_displayid_detailed(connector->dev, timings); 4802 if (!newmode) 4803 continue; 4804 4805 drm_mode_probed_add(connector, newmode); 4806 num_modes++; 4807 } 4808 return num_modes; 4809 } 4810 4811 static int add_displayid_detailed_modes(struct drm_connector *connector, 4812 struct edid *edid) 4813 { 4814 u8 *displayid; 4815 int ret; 4816 int idx = 1; 4817 int length = EDID_LENGTH; 4818 struct displayid_block *block; 4819 int num_modes = 0; 4820 4821 displayid = drm_find_displayid_extension(edid); 4822 if (!displayid) 4823 return 0; 4824 4825 ret = validate_displayid(displayid, length, idx); 4826 if (ret) 4827 return 0; 4828 4829 idx += sizeof(struct displayid_hdr); 4830 for_each_displayid_db(displayid, block, idx, length) { 4831 switch (block->tag) { 4832 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 4833 num_modes += add_displayid_detailed_1_modes(connector, block); 4834 break; 4835 } 4836 } 4837 return num_modes; 4838 } 4839 4840 /** 4841 * drm_add_edid_modes - add modes from EDID data, if available 4842 * @connector: connector we're probing 4843 * @edid: EDID data 4844 * 4845 * Add the specified modes to the connector's mode list. Also fills out the 4846 * &drm_display_info structure and ELD in @connector with any information which 4847 * can be derived from the edid. 4848 * 4849 * Return: The number of modes added or 0 if we couldn't find any. 4850 */ 4851 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 4852 { 4853 int num_modes = 0; 4854 u32 quirks; 4855 4856 if (edid == NULL) { 4857 clear_eld(connector); 4858 return 0; 4859 } 4860 if (!drm_edid_is_valid(edid)) { 4861 clear_eld(connector); 4862 dev_warn(connector->dev->dev, "%s: EDID invalid.\n", 4863 connector->name); 4864 return 0; 4865 } 4866 4867 drm_edid_to_eld(connector, edid); 4868 4869 /* 4870 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. 4871 * To avoid multiple parsing of same block, lets parse that map 4872 * from sink info, before parsing CEA modes. 4873 */ 4874 quirks = drm_add_display_info(connector, edid); 4875 4876 /* 4877 * EDID spec says modes should be preferred in this order: 4878 * - preferred detailed mode 4879 * - other detailed modes from base block 4880 * - detailed modes from extension blocks 4881 * - CVT 3-byte code modes 4882 * - standard timing codes 4883 * - established timing codes 4884 * - modes inferred from GTF or CVT range information 4885 * 4886 * We get this pretty much right. 4887 * 4888 * XXX order for additional mode types in extension blocks? 4889 */ 4890 num_modes += add_detailed_modes(connector, edid, quirks); 4891 num_modes += add_cvt_modes(connector, edid); 4892 num_modes += add_standard_modes(connector, edid); 4893 num_modes += add_established_modes(connector, edid); 4894 num_modes += add_cea_modes(connector, edid); 4895 num_modes += add_alternate_cea_modes(connector, edid); 4896 num_modes += add_displayid_detailed_modes(connector, edid); 4897 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 4898 num_modes += add_inferred_modes(connector, edid); 4899 4900 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 4901 edid_fixup_preferred(connector, quirks); 4902 4903 if (quirks & EDID_QUIRK_FORCE_6BPC) 4904 connector->display_info.bpc = 6; 4905 4906 if (quirks & EDID_QUIRK_FORCE_8BPC) 4907 connector->display_info.bpc = 8; 4908 4909 if (quirks & EDID_QUIRK_FORCE_10BPC) 4910 connector->display_info.bpc = 10; 4911 4912 if (quirks & EDID_QUIRK_FORCE_12BPC) 4913 connector->display_info.bpc = 12; 4914 4915 return num_modes; 4916 } 4917 EXPORT_SYMBOL(drm_add_edid_modes); 4918 4919 /** 4920 * drm_add_modes_noedid - add modes for the connectors without EDID 4921 * @connector: connector we're probing 4922 * @hdisplay: the horizontal display limit 4923 * @vdisplay: the vertical display limit 4924 * 4925 * Add the specified modes to the connector's mode list. Only when the 4926 * hdisplay/vdisplay is not beyond the given limit, it will be added. 4927 * 4928 * Return: The number of modes added or 0 if we couldn't find any. 4929 */ 4930 int drm_add_modes_noedid(struct drm_connector *connector, 4931 int hdisplay, int vdisplay) 4932 { 4933 int i, count, num_modes = 0; 4934 struct drm_display_mode *mode; 4935 struct drm_device *dev = connector->dev; 4936 4937 count = ARRAY_SIZE(drm_dmt_modes); 4938 if (hdisplay < 0) 4939 hdisplay = 0; 4940 if (vdisplay < 0) 4941 vdisplay = 0; 4942 4943 for (i = 0; i < count; i++) { 4944 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 4945 if (hdisplay && vdisplay) { 4946 /* 4947 * Only when two are valid, they will be used to check 4948 * whether the mode should be added to the mode list of 4949 * the connector. 4950 */ 4951 if (ptr->hdisplay > hdisplay || 4952 ptr->vdisplay > vdisplay) 4953 continue; 4954 } 4955 if (drm_mode_vrefresh(ptr) > 61) 4956 continue; 4957 mode = drm_mode_duplicate(dev, ptr); 4958 if (mode) { 4959 drm_mode_probed_add(connector, mode); 4960 num_modes++; 4961 } 4962 } 4963 return num_modes; 4964 } 4965 EXPORT_SYMBOL(drm_add_modes_noedid); 4966 4967 /** 4968 * drm_set_preferred_mode - Sets the preferred mode of a connector 4969 * @connector: connector whose mode list should be processed 4970 * @hpref: horizontal resolution of preferred mode 4971 * @vpref: vertical resolution of preferred mode 4972 * 4973 * Marks a mode as preferred if it matches the resolution specified by @hpref 4974 * and @vpref. 4975 */ 4976 void drm_set_preferred_mode(struct drm_connector *connector, 4977 int hpref, int vpref) 4978 { 4979 struct drm_display_mode *mode; 4980 4981 list_for_each_entry(mode, &connector->probed_modes, head) { 4982 if (mode->hdisplay == hpref && 4983 mode->vdisplay == vpref) 4984 mode->type |= DRM_MODE_TYPE_PREFERRED; 4985 } 4986 } 4987 EXPORT_SYMBOL(drm_set_preferred_mode); 4988 4989 static bool is_hdmi2_sink(struct drm_connector *connector) 4990 { 4991 /* 4992 * FIXME: sil-sii8620 doesn't have a connector around when 4993 * we need one, so we have to be prepared for a NULL connector. 4994 */ 4995 if (!connector) 4996 return true; 4997 4998 return connector->display_info.hdmi.scdc.supported || 4999 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420; 5000 } 5001 5002 static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf) 5003 { 5004 return sink_eotf & BIT(output_eotf); 5005 } 5006 5007 /** 5008 * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with 5009 * HDR metadata from userspace 5010 * @frame: HDMI DRM infoframe 5011 * @conn_state: Connector state containing HDR metadata 5012 * 5013 * Return: 0 on success or a negative error code on failure. 5014 */ 5015 int 5016 drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame, 5017 const struct drm_connector_state *conn_state) 5018 { 5019 struct drm_connector *connector; 5020 struct hdr_output_metadata *hdr_metadata; 5021 int err; 5022 5023 if (!frame || !conn_state) 5024 return -EINVAL; 5025 5026 connector = conn_state->connector; 5027 5028 if (!conn_state->hdr_output_metadata) 5029 return -EINVAL; 5030 5031 hdr_metadata = conn_state->hdr_output_metadata->data; 5032 5033 if (!hdr_metadata || !connector) 5034 return -EINVAL; 5035 5036 /* Sink EOTF is Bit map while infoframe is absolute values */ 5037 if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf, 5038 connector->hdr_sink_metadata.hdmi_type1.eotf)) { 5039 DRM_DEBUG_KMS("EOTF Not Supported\n"); 5040 return -EINVAL; 5041 } 5042 5043 err = hdmi_drm_infoframe_init(frame); 5044 if (err < 0) 5045 return err; 5046 5047 frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf; 5048 frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type; 5049 5050 BUILD_BUG_ON(sizeof(frame->display_primaries) != 5051 sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries)); 5052 BUILD_BUG_ON(sizeof(frame->white_point) != 5053 sizeof(hdr_metadata->hdmi_metadata_type1.white_point)); 5054 5055 memcpy(&frame->display_primaries, 5056 &hdr_metadata->hdmi_metadata_type1.display_primaries, 5057 sizeof(frame->display_primaries)); 5058 5059 memcpy(&frame->white_point, 5060 &hdr_metadata->hdmi_metadata_type1.white_point, 5061 sizeof(frame->white_point)); 5062 5063 frame->max_display_mastering_luminance = 5064 hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance; 5065 frame->min_display_mastering_luminance = 5066 hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance; 5067 frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall; 5068 frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll; 5069 5070 return 0; 5071 } 5072 EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata); 5073 5074 /** 5075 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 5076 * data from a DRM display mode 5077 * @frame: HDMI AVI infoframe 5078 * @connector: the connector 5079 * @mode: DRM display mode 5080 * 5081 * Return: 0 on success or a negative error code on failure. 5082 */ 5083 int 5084 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 5085 struct drm_connector *connector, 5086 const struct drm_display_mode *mode) 5087 { 5088 enum hdmi_picture_aspect picture_aspect; 5089 int err; 5090 5091 if (!frame || !mode) 5092 return -EINVAL; 5093 5094 err = hdmi_avi_infoframe_init(frame); 5095 if (err < 0) 5096 return err; 5097 5098 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 5099 frame->pixel_repeat = 1; 5100 5101 frame->video_code = drm_match_cea_mode(mode); 5102 5103 /* 5104 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but 5105 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we 5106 * have to make sure we dont break HDMI 1.4 sinks. 5107 */ 5108 if (!is_hdmi2_sink(connector) && frame->video_code > 64) 5109 frame->video_code = 0; 5110 5111 /* 5112 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 5113 * we should send its VIC in vendor infoframes, else send the 5114 * VIC in AVI infoframes. Lets check if this mode is present in 5115 * HDMI 1.4b 4K modes 5116 */ 5117 if (frame->video_code) { 5118 u8 vendor_if_vic = drm_match_hdmi_mode(mode); 5119 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK; 5120 5121 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d) 5122 frame->video_code = 0; 5123 } 5124 5125 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5126 5127 /* 5128 * As some drivers don't support atomic, we can't use connector state. 5129 * So just initialize the frame with default values, just the same way 5130 * as it's done with other properties here. 5131 */ 5132 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; 5133 frame->itc = 0; 5134 5135 /* 5136 * Populate picture aspect ratio from either 5137 * user input (if specified) or from the CEA mode list. 5138 */ 5139 picture_aspect = mode->picture_aspect_ratio; 5140 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) 5141 picture_aspect = drm_get_cea_aspect_ratio(frame->video_code); 5142 5143 /* 5144 * The infoframe can't convey anything but none, 4:3 5145 * and 16:9, so if the user has asked for anything else 5146 * we can only satisfy it by specifying the right VIC. 5147 */ 5148 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { 5149 if (picture_aspect != 5150 drm_get_cea_aspect_ratio(frame->video_code)) 5151 return -EINVAL; 5152 picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5153 } 5154 5155 frame->picture_aspect = picture_aspect; 5156 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 5157 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 5158 5159 return 0; 5160 } 5161 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 5162 5163 /* HDMI Colorspace Spec Definitions */ 5164 #define FULL_COLORIMETRY_MASK 0x1FF 5165 #define NORMAL_COLORIMETRY_MASK 0x3 5166 #define EXTENDED_COLORIMETRY_MASK 0x7 5167 #define EXTENDED_ACE_COLORIMETRY_MASK 0xF 5168 5169 #define C(x) ((x) << 0) 5170 #define EC(x) ((x) << 2) 5171 #define ACE(x) ((x) << 5) 5172 5173 #define HDMI_COLORIMETRY_NO_DATA 0x0 5174 #define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0)) 5175 #define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0)) 5176 #define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0)) 5177 #define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0)) 5178 #define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0)) 5179 #define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0)) 5180 #define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0)) 5181 #define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0)) 5182 #define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0)) 5183 #define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0)) 5184 #define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0)) 5185 #define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1)) 5186 5187 static const u32 hdmi_colorimetry_val[] = { 5188 [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA, 5189 [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC, 5190 [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC, 5191 [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601, 5192 [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709, 5193 [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601, 5194 [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601, 5195 [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB, 5196 [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC, 5197 [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB, 5198 [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC, 5199 }; 5200 5201 #undef C 5202 #undef EC 5203 #undef ACE 5204 5205 /** 5206 * drm_hdmi_avi_infoframe_colorspace() - fill the HDMI AVI infoframe 5207 * colorspace information 5208 * @frame: HDMI AVI infoframe 5209 * @conn_state: connector state 5210 */ 5211 void 5212 drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame, 5213 const struct drm_connector_state *conn_state) 5214 { 5215 u32 colorimetry_val; 5216 u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK; 5217 5218 if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val)) 5219 colorimetry_val = HDMI_COLORIMETRY_NO_DATA; 5220 else 5221 colorimetry_val = hdmi_colorimetry_val[colorimetry_index]; 5222 5223 frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK; 5224 /* 5225 * ToDo: Extend it for ACE formats as well. Modify the infoframe 5226 * structure and extend it in drivers/video/hdmi 5227 */ 5228 frame->extended_colorimetry = (colorimetry_val >> 2) & 5229 EXTENDED_COLORIMETRY_MASK; 5230 } 5231 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace); 5232 5233 /** 5234 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 5235 * quantization range information 5236 * @frame: HDMI AVI infoframe 5237 * @connector: the connector 5238 * @mode: DRM display mode 5239 * @rgb_quant_range: RGB quantization range (Q) 5240 */ 5241 void 5242 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 5243 struct drm_connector *connector, 5244 const struct drm_display_mode *mode, 5245 enum hdmi_quantization_range rgb_quant_range) 5246 { 5247 const struct drm_display_info *info = &connector->display_info; 5248 5249 /* 5250 * CEA-861: 5251 * "A Source shall not send a non-zero Q value that does not correspond 5252 * to the default RGB Quantization Range for the transmitted Picture 5253 * unless the Sink indicates support for the Q bit in a Video 5254 * Capabilities Data Block." 5255 * 5256 * HDMI 2.0 recommends sending non-zero Q when it does match the 5257 * default RGB quantization range for the mode, even when QS=0. 5258 */ 5259 if (info->rgb_quant_range_selectable || 5260 rgb_quant_range == drm_default_rgb_quant_range(mode)) 5261 frame->quantization_range = rgb_quant_range; 5262 else 5263 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 5264 5265 /* 5266 * CEA-861-F: 5267 * "When transmitting any RGB colorimetry, the Source should set the 5268 * YQ-field to match the RGB Quantization Range being transmitted 5269 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 5270 * set YQ=1) and the Sink shall ignore the YQ-field." 5271 * 5272 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused 5273 * by non-zero YQ when receiving RGB. There doesn't seem to be any 5274 * good way to tell which version of CEA-861 the sink supports, so 5275 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based 5276 * on on CEA-861-F. 5277 */ 5278 if (!is_hdmi2_sink(connector) || 5279 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 5280 frame->ycc_quantization_range = 5281 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 5282 else 5283 frame->ycc_quantization_range = 5284 HDMI_YCC_QUANTIZATION_RANGE_FULL; 5285 } 5286 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 5287 5288 static enum hdmi_3d_structure 5289 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 5290 { 5291 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 5292 5293 switch (layout) { 5294 case DRM_MODE_FLAG_3D_FRAME_PACKING: 5295 return HDMI_3D_STRUCTURE_FRAME_PACKING; 5296 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 5297 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 5298 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 5299 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 5300 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 5301 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 5302 case DRM_MODE_FLAG_3D_L_DEPTH: 5303 return HDMI_3D_STRUCTURE_L_DEPTH; 5304 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 5305 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 5306 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 5307 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 5308 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 5309 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 5310 default: 5311 return HDMI_3D_STRUCTURE_INVALID; 5312 } 5313 } 5314 5315 /** 5316 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 5317 * data from a DRM display mode 5318 * @frame: HDMI vendor infoframe 5319 * @connector: the connector 5320 * @mode: DRM display mode 5321 * 5322 * Note that there's is a need to send HDMI vendor infoframes only when using a 5323 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 5324 * function will return -EINVAL, error that can be safely ignored. 5325 * 5326 * Return: 0 on success or a negative error code on failure. 5327 */ 5328 int 5329 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 5330 struct drm_connector *connector, 5331 const struct drm_display_mode *mode) 5332 { 5333 /* 5334 * FIXME: sil-sii8620 doesn't have a connector around when 5335 * we need one, so we have to be prepared for a NULL connector. 5336 */ 5337 bool has_hdmi_infoframe = connector ? 5338 connector->display_info.has_hdmi_infoframe : false; 5339 int err; 5340 u32 s3d_flags; 5341 u8 vic; 5342 5343 if (!frame || !mode) 5344 return -EINVAL; 5345 5346 if (!has_hdmi_infoframe) 5347 return -EINVAL; 5348 5349 vic = drm_match_hdmi_mode(mode); 5350 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; 5351 5352 /* 5353 * Even if it's not absolutely necessary to send the infoframe 5354 * (ie.vic==0 and s3d_struct==0) we will still send it if we 5355 * know that the sink can handle it. This is based on a 5356 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks 5357 * have trouble realizing that they shuld switch from 3D to 2D 5358 * mode if the source simply stops sending the infoframe when 5359 * it wants to switch from 3D to 2D. 5360 */ 5361 5362 if (vic && s3d_flags) 5363 return -EINVAL; 5364 5365 err = hdmi_vendor_infoframe_init(frame); 5366 if (err < 0) 5367 return err; 5368 5369 frame->vic = vic; 5370 frame->s3d_struct = s3d_structure_from_display_mode(mode); 5371 5372 return 0; 5373 } 5374 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 5375 5376 static int drm_parse_tiled_block(struct drm_connector *connector, 5377 struct displayid_block *block) 5378 { 5379 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 5380 u16 w, h; 5381 u8 tile_v_loc, tile_h_loc; 5382 u8 num_v_tile, num_h_tile; 5383 struct drm_tile_group *tg; 5384 5385 w = tile->tile_size[0] | tile->tile_size[1] << 8; 5386 h = tile->tile_size[2] | tile->tile_size[3] << 8; 5387 5388 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 5389 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 5390 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 5391 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 5392 5393 connector->has_tile = true; 5394 if (tile->tile_cap & 0x80) 5395 connector->tile_is_single_monitor = true; 5396 5397 connector->num_h_tile = num_h_tile + 1; 5398 connector->num_v_tile = num_v_tile + 1; 5399 connector->tile_h_loc = tile_h_loc; 5400 connector->tile_v_loc = tile_v_loc; 5401 connector->tile_h_size = w + 1; 5402 connector->tile_v_size = h + 1; 5403 5404 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); 5405 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); 5406 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", 5407 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); 5408 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 5409 5410 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 5411 if (!tg) { 5412 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 5413 } 5414 if (!tg) 5415 return -ENOMEM; 5416 5417 if (connector->tile_group != tg) { 5418 /* if we haven't got a pointer, 5419 take the reference, drop ref to old tile group */ 5420 if (connector->tile_group) { 5421 drm_mode_put_tile_group(connector->dev, connector->tile_group); 5422 } 5423 connector->tile_group = tg; 5424 } else 5425 /* if same tile group, then release the ref we just took. */ 5426 drm_mode_put_tile_group(connector->dev, tg); 5427 return 0; 5428 } 5429 5430 static int drm_parse_display_id(struct drm_connector *connector, 5431 u8 *displayid, int length, 5432 bool is_edid_extension) 5433 { 5434 /* if this is an EDID extension the first byte will be 0x70 */ 5435 int idx = 0; 5436 struct displayid_block *block; 5437 int ret; 5438 5439 if (is_edid_extension) 5440 idx = 1; 5441 5442 ret = validate_displayid(displayid, length, idx); 5443 if (ret) 5444 return ret; 5445 5446 idx += sizeof(struct displayid_hdr); 5447 for_each_displayid_db(displayid, block, idx, length) { 5448 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n", 5449 block->tag, block->rev, block->num_bytes); 5450 5451 switch (block->tag) { 5452 case DATA_BLOCK_TILED_DISPLAY: 5453 ret = drm_parse_tiled_block(connector, block); 5454 if (ret) 5455 return ret; 5456 break; 5457 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 5458 /* handled in mode gathering code. */ 5459 break; 5460 case DATA_BLOCK_CTA: 5461 /* handled in the cea parser code. */ 5462 break; 5463 default: 5464 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag); 5465 break; 5466 } 5467 } 5468 return 0; 5469 } 5470 5471 static void drm_get_displayid(struct drm_connector *connector, 5472 struct edid *edid) 5473 { 5474 void *displayid = NULL; 5475 int ret; 5476 connector->has_tile = false; 5477 displayid = drm_find_displayid_extension(edid); 5478 if (!displayid) { 5479 /* drop reference to any tile group we had */ 5480 goto out_drop_ref; 5481 } 5482 5483 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true); 5484 if (ret < 0) 5485 goto out_drop_ref; 5486 if (!connector->has_tile) 5487 goto out_drop_ref; 5488 return; 5489 out_drop_ref: 5490 if (connector->tile_group) { 5491 drm_mode_put_tile_group(connector->dev, connector->tile_group); 5492 connector->tile_group = NULL; 5493 } 5494 return; 5495 } 5496