1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 #include <linux/kernel.h> 31 #include <linux/slab.h> 32 #include <linux/hdmi.h> 33 #include <linux/i2c.h> 34 #include <linux/module.h> 35 #include <drm/drmP.h> 36 #include <drm/drm_edid.h> 37 #include <drm/drm_displayid.h> 38 39 #define version_greater(edid, maj, min) \ 40 (((edid)->version > (maj)) || \ 41 ((edid)->version == (maj) && (edid)->revision > (min))) 42 43 #define EDID_EST_TIMINGS 16 44 #define EDID_STD_TIMINGS 8 45 #define EDID_DETAILED_TIMINGS 4 46 47 /* 48 * EDID blocks out in the wild have a variety of bugs, try to collect 49 * them here (note that userspace may work around broken monitors first, 50 * but fixes should make their way here so that the kernel "just works" 51 * on as many displays as possible). 52 */ 53 54 /* First detailed mode wrong, use largest 60Hz mode */ 55 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 56 /* Reported 135MHz pixel clock is too high, needs adjustment */ 57 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 58 /* Prefer the largest mode at 75 Hz */ 59 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 60 /* Detail timing is in cm not mm */ 61 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 62 /* Detailed timing descriptors have bogus size values, so just take the 63 * maximum size and use that. 64 */ 65 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 66 /* Monitor forgot to set the first detailed is preferred bit. */ 67 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5) 68 /* use +hsync +vsync for detailed mode */ 69 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 70 /* Force reduced-blanking timings for detailed modes */ 71 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 72 /* Force 8bpc */ 73 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 74 /* Force 12bpc */ 75 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 76 77 struct detailed_mode_closure { 78 struct drm_connector *connector; 79 struct edid *edid; 80 bool preferred; 81 u32 quirks; 82 int modes; 83 }; 84 85 #define LEVEL_DMT 0 86 #define LEVEL_GTF 1 87 #define LEVEL_GTF2 2 88 #define LEVEL_CVT 3 89 90 static struct edid_quirk { 91 char vendor[4]; 92 int product_id; 93 u32 quirks; 94 } edid_quirk_list[] = { 95 /* Acer AL1706 */ 96 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 97 /* Acer F51 */ 98 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 99 /* Unknown Acer */ 100 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 101 102 /* Belinea 10 15 55 */ 103 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 104 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 105 106 /* Envision Peripherals, Inc. EN-7100e */ 107 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 108 /* Envision EN2028 */ 109 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 110 111 /* Funai Electronics PM36B */ 112 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 113 EDID_QUIRK_DETAILED_IN_CM }, 114 115 /* LG Philips LCD LP154W01-A5 */ 116 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 117 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 118 119 /* Philips 107p5 CRT */ 120 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 121 122 /* Proview AY765C */ 123 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 124 125 /* Samsung SyncMaster 205BW. Note: irony */ 126 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 127 /* Samsung SyncMaster 22[5-6]BW */ 128 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 129 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 130 131 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 132 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 133 134 /* ViewSonic VA2026w */ 135 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 136 137 /* Medion MD 30217 PG */ 138 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 139 140 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 141 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 142 }; 143 144 /* 145 * Autogenerated from the DMT spec. 146 * This table is copied from xfree86/modes/xf86EdidModes.c. 147 */ 148 static const struct drm_display_mode drm_dmt_modes[] = { 149 /* 0x01 - 640x350@85Hz */ 150 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 151 736, 832, 0, 350, 382, 385, 445, 0, 152 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 153 /* 0x02 - 640x400@85Hz */ 154 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 155 736, 832, 0, 400, 401, 404, 445, 0, 156 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 157 /* 0x03 - 720x400@85Hz */ 158 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 159 828, 936, 0, 400, 401, 404, 446, 0, 160 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 161 /* 0x04 - 640x480@60Hz */ 162 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 163 752, 800, 0, 480, 490, 492, 525, 0, 164 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 165 /* 0x05 - 640x480@72Hz */ 166 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 167 704, 832, 0, 480, 489, 492, 520, 0, 168 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 169 /* 0x06 - 640x480@75Hz */ 170 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 171 720, 840, 0, 480, 481, 484, 500, 0, 172 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 173 /* 0x07 - 640x480@85Hz */ 174 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 175 752, 832, 0, 480, 481, 484, 509, 0, 176 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 177 /* 0x08 - 800x600@56Hz */ 178 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 179 896, 1024, 0, 600, 601, 603, 625, 0, 180 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 181 /* 0x09 - 800x600@60Hz */ 182 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 183 968, 1056, 0, 600, 601, 605, 628, 0, 184 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 185 /* 0x0a - 800x600@72Hz */ 186 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 187 976, 1040, 0, 600, 637, 643, 666, 0, 188 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 189 /* 0x0b - 800x600@75Hz */ 190 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 191 896, 1056, 0, 600, 601, 604, 625, 0, 192 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 193 /* 0x0c - 800x600@85Hz */ 194 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 195 896, 1048, 0, 600, 601, 604, 631, 0, 196 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 197 /* 0x0d - 800x600@120Hz RB */ 198 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 199 880, 960, 0, 600, 603, 607, 636, 0, 200 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 201 /* 0x0e - 848x480@60Hz */ 202 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 203 976, 1088, 0, 480, 486, 494, 517, 0, 204 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 205 /* 0x0f - 1024x768@43Hz, interlace */ 206 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 207 1208, 1264, 0, 768, 768, 772, 817, 0, 208 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 209 DRM_MODE_FLAG_INTERLACE) }, 210 /* 0x10 - 1024x768@60Hz */ 211 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 212 1184, 1344, 0, 768, 771, 777, 806, 0, 213 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 214 /* 0x11 - 1024x768@70Hz */ 215 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 216 1184, 1328, 0, 768, 771, 777, 806, 0, 217 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 218 /* 0x12 - 1024x768@75Hz */ 219 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 220 1136, 1312, 0, 768, 769, 772, 800, 0, 221 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 222 /* 0x13 - 1024x768@85Hz */ 223 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 224 1168, 1376, 0, 768, 769, 772, 808, 0, 225 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 226 /* 0x14 - 1024x768@120Hz RB */ 227 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 228 1104, 1184, 0, 768, 771, 775, 813, 0, 229 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 230 /* 0x15 - 1152x864@75Hz */ 231 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 232 1344, 1600, 0, 864, 865, 868, 900, 0, 233 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 234 /* 0x55 - 1280x720@60Hz */ 235 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 236 1430, 1650, 0, 720, 725, 730, 750, 0, 237 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 238 /* 0x16 - 1280x768@60Hz RB */ 239 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 240 1360, 1440, 0, 768, 771, 778, 790, 0, 241 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 242 /* 0x17 - 1280x768@60Hz */ 243 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 244 1472, 1664, 0, 768, 771, 778, 798, 0, 245 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 246 /* 0x18 - 1280x768@75Hz */ 247 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 248 1488, 1696, 0, 768, 771, 778, 805, 0, 249 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 250 /* 0x19 - 1280x768@85Hz */ 251 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 252 1496, 1712, 0, 768, 771, 778, 809, 0, 253 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 254 /* 0x1a - 1280x768@120Hz RB */ 255 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 256 1360, 1440, 0, 768, 771, 778, 813, 0, 257 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 258 /* 0x1b - 1280x800@60Hz RB */ 259 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 260 1360, 1440, 0, 800, 803, 809, 823, 0, 261 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 262 /* 0x1c - 1280x800@60Hz */ 263 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 264 1480, 1680, 0, 800, 803, 809, 831, 0, 265 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 266 /* 0x1d - 1280x800@75Hz */ 267 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 268 1488, 1696, 0, 800, 803, 809, 838, 0, 269 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 270 /* 0x1e - 1280x800@85Hz */ 271 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 272 1496, 1712, 0, 800, 803, 809, 843, 0, 273 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 274 /* 0x1f - 1280x800@120Hz RB */ 275 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 276 1360, 1440, 0, 800, 803, 809, 847, 0, 277 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 278 /* 0x20 - 1280x960@60Hz */ 279 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 280 1488, 1800, 0, 960, 961, 964, 1000, 0, 281 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 282 /* 0x21 - 1280x960@85Hz */ 283 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 284 1504, 1728, 0, 960, 961, 964, 1011, 0, 285 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 286 /* 0x22 - 1280x960@120Hz RB */ 287 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 288 1360, 1440, 0, 960, 963, 967, 1017, 0, 289 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 290 /* 0x23 - 1280x1024@60Hz */ 291 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 292 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 294 /* 0x24 - 1280x1024@75Hz */ 295 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 296 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 298 /* 0x25 - 1280x1024@85Hz */ 299 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 300 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 302 /* 0x26 - 1280x1024@120Hz RB */ 303 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 304 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 306 /* 0x27 - 1360x768@60Hz */ 307 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 308 1536, 1792, 0, 768, 771, 777, 795, 0, 309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 310 /* 0x28 - 1360x768@120Hz RB */ 311 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 312 1440, 1520, 0, 768, 771, 776, 813, 0, 313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 314 /* 0x51 - 1366x768@60Hz */ 315 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 316 1579, 1792, 0, 768, 771, 774, 798, 0, 317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 318 /* 0x56 - 1366x768@60Hz */ 319 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 320 1436, 1500, 0, 768, 769, 772, 800, 0, 321 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 322 /* 0x29 - 1400x1050@60Hz RB */ 323 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 324 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 326 /* 0x2a - 1400x1050@60Hz */ 327 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 328 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 329 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 330 /* 0x2b - 1400x1050@75Hz */ 331 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 332 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 333 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 334 /* 0x2c - 1400x1050@85Hz */ 335 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 336 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 337 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 338 /* 0x2d - 1400x1050@120Hz RB */ 339 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 340 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 341 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 342 /* 0x2e - 1440x900@60Hz RB */ 343 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 344 1520, 1600, 0, 900, 903, 909, 926, 0, 345 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 346 /* 0x2f - 1440x900@60Hz */ 347 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 348 1672, 1904, 0, 900, 903, 909, 934, 0, 349 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 350 /* 0x30 - 1440x900@75Hz */ 351 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 352 1688, 1936, 0, 900, 903, 909, 942, 0, 353 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 354 /* 0x31 - 1440x900@85Hz */ 355 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 356 1696, 1952, 0, 900, 903, 909, 948, 0, 357 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 358 /* 0x32 - 1440x900@120Hz RB */ 359 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 360 1520, 1600, 0, 900, 903, 909, 953, 0, 361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 362 /* 0x53 - 1600x900@60Hz */ 363 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 364 1704, 1800, 0, 900, 901, 904, 1000, 0, 365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 366 /* 0x33 - 1600x1200@60Hz */ 367 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 368 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 370 /* 0x34 - 1600x1200@65Hz */ 371 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 372 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 374 /* 0x35 - 1600x1200@70Hz */ 375 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 376 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 378 /* 0x36 - 1600x1200@75Hz */ 379 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 380 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 382 /* 0x37 - 1600x1200@85Hz */ 383 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 384 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 386 /* 0x38 - 1600x1200@120Hz RB */ 387 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 388 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 390 /* 0x39 - 1680x1050@60Hz RB */ 391 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 392 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 394 /* 0x3a - 1680x1050@60Hz */ 395 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 396 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 397 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 398 /* 0x3b - 1680x1050@75Hz */ 399 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 400 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 401 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 402 /* 0x3c - 1680x1050@85Hz */ 403 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 404 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 405 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 406 /* 0x3d - 1680x1050@120Hz RB */ 407 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 408 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 409 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 410 /* 0x3e - 1792x1344@60Hz */ 411 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 412 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 413 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 414 /* 0x3f - 1792x1344@75Hz */ 415 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 416 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 417 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 418 /* 0x40 - 1792x1344@120Hz RB */ 419 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 420 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 422 /* 0x41 - 1856x1392@60Hz */ 423 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 424 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 425 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 426 /* 0x42 - 1856x1392@75Hz */ 427 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 428 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 429 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 430 /* 0x43 - 1856x1392@120Hz RB */ 431 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 432 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 433 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 434 /* 0x52 - 1920x1080@60Hz */ 435 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 436 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 437 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 438 /* 0x44 - 1920x1200@60Hz RB */ 439 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 440 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 442 /* 0x45 - 1920x1200@60Hz */ 443 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 444 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 445 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 446 /* 0x46 - 1920x1200@75Hz */ 447 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 448 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 449 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 450 /* 0x47 - 1920x1200@85Hz */ 451 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 452 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 453 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 454 /* 0x48 - 1920x1200@120Hz RB */ 455 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 456 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 458 /* 0x49 - 1920x1440@60Hz */ 459 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 460 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 461 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 462 /* 0x4a - 1920x1440@75Hz */ 463 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 464 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 465 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 466 /* 0x4b - 1920x1440@120Hz RB */ 467 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 468 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 470 /* 0x54 - 2048x1152@60Hz */ 471 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 472 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 474 /* 0x4c - 2560x1600@60Hz RB */ 475 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 476 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 478 /* 0x4d - 2560x1600@60Hz */ 479 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 480 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 481 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 482 /* 0x4e - 2560x1600@75Hz */ 483 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 484 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 485 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 486 /* 0x4f - 2560x1600@85Hz */ 487 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 488 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 490 /* 0x50 - 2560x1600@120Hz RB */ 491 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 492 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 494 /* 0x57 - 4096x2160@60Hz RB */ 495 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 496 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 497 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 498 /* 0x58 - 4096x2160@59.94Hz RB */ 499 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 500 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 501 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 502 }; 503 504 /* 505 * These more or less come from the DMT spec. The 720x400 modes are 506 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 507 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 508 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 509 * mode. 510 * 511 * The DMT modes have been fact-checked; the rest are mild guesses. 512 */ 513 static const struct drm_display_mode edid_est_modes[] = { 514 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 515 968, 1056, 0, 600, 601, 605, 628, 0, 516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 517 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 518 896, 1024, 0, 600, 601, 603, 625, 0, 519 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 520 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 521 720, 840, 0, 480, 481, 484, 500, 0, 522 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 523 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 524 704, 832, 0, 480, 489, 491, 520, 0, 525 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 526 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 527 768, 864, 0, 480, 483, 486, 525, 0, 528 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 529 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25200, 640, 656, 530 752, 800, 0, 480, 490, 492, 525, 0, 531 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 532 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 533 846, 900, 0, 400, 421, 423, 449, 0, 534 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 535 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 536 846, 900, 0, 400, 412, 414, 449, 0, 537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 538 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 539 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 540 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 541 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78800, 1024, 1040, 542 1136, 1312, 0, 768, 769, 772, 800, 0, 543 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 544 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 545 1184, 1328, 0, 768, 771, 777, 806, 0, 546 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 547 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 548 1184, 1344, 0, 768, 771, 777, 806, 0, 549 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 550 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 551 1208, 1264, 0, 768, 768, 776, 817, 0, 552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 553 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 554 928, 1152, 0, 624, 625, 628, 667, 0, 555 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 556 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 557 896, 1056, 0, 600, 601, 604, 625, 0, 558 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 559 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 560 976, 1040, 0, 600, 637, 643, 666, 0, 561 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 562 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 563 1344, 1600, 0, 864, 865, 868, 900, 0, 564 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 565 }; 566 567 struct minimode { 568 short w; 569 short h; 570 short r; 571 short rb; 572 }; 573 574 static const struct minimode est3_modes[] = { 575 /* byte 6 */ 576 { 640, 350, 85, 0 }, 577 { 640, 400, 85, 0 }, 578 { 720, 400, 85, 0 }, 579 { 640, 480, 85, 0 }, 580 { 848, 480, 60, 0 }, 581 { 800, 600, 85, 0 }, 582 { 1024, 768, 85, 0 }, 583 { 1152, 864, 75, 0 }, 584 /* byte 7 */ 585 { 1280, 768, 60, 1 }, 586 { 1280, 768, 60, 0 }, 587 { 1280, 768, 75, 0 }, 588 { 1280, 768, 85, 0 }, 589 { 1280, 960, 60, 0 }, 590 { 1280, 960, 85, 0 }, 591 { 1280, 1024, 60, 0 }, 592 { 1280, 1024, 85, 0 }, 593 /* byte 8 */ 594 { 1360, 768, 60, 0 }, 595 { 1440, 900, 60, 1 }, 596 { 1440, 900, 60, 0 }, 597 { 1440, 900, 75, 0 }, 598 { 1440, 900, 85, 0 }, 599 { 1400, 1050, 60, 1 }, 600 { 1400, 1050, 60, 0 }, 601 { 1400, 1050, 75, 0 }, 602 /* byte 9 */ 603 { 1400, 1050, 85, 0 }, 604 { 1680, 1050, 60, 1 }, 605 { 1680, 1050, 60, 0 }, 606 { 1680, 1050, 75, 0 }, 607 { 1680, 1050, 85, 0 }, 608 { 1600, 1200, 60, 0 }, 609 { 1600, 1200, 65, 0 }, 610 { 1600, 1200, 70, 0 }, 611 /* byte 10 */ 612 { 1600, 1200, 75, 0 }, 613 { 1600, 1200, 85, 0 }, 614 { 1792, 1344, 60, 0 }, 615 { 1792, 1344, 75, 0 }, 616 { 1856, 1392, 60, 0 }, 617 { 1856, 1392, 75, 0 }, 618 { 1920, 1200, 60, 1 }, 619 { 1920, 1200, 60, 0 }, 620 /* byte 11 */ 621 { 1920, 1200, 75, 0 }, 622 { 1920, 1200, 85, 0 }, 623 { 1920, 1440, 60, 0 }, 624 { 1920, 1440, 75, 0 }, 625 }; 626 627 static const struct minimode extra_modes[] = { 628 { 1024, 576, 60, 0 }, 629 { 1366, 768, 60, 0 }, 630 { 1600, 900, 60, 0 }, 631 { 1680, 945, 60, 0 }, 632 { 1920, 1080, 60, 0 }, 633 { 2048, 1152, 60, 0 }, 634 { 2048, 1536, 60, 0 }, 635 }; 636 637 /* 638 * Probably taken from CEA-861 spec. 639 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. 640 * 641 * Index using the VIC. 642 */ 643 static const struct drm_display_mode edid_cea_modes[] = { 644 /* 0 - dummy, VICs start at 1 */ 645 { }, 646 /* 1 - 640x480@60Hz */ 647 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 648 752, 800, 0, 480, 490, 492, 525, 0, 649 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 650 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 651 /* 2 - 720x480@60Hz */ 652 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 653 798, 858, 0, 480, 489, 495, 525, 0, 654 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 655 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 656 /* 3 - 720x480@60Hz */ 657 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 658 798, 858, 0, 480, 489, 495, 525, 0, 659 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 660 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 661 /* 4 - 1280x720@60Hz */ 662 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 663 1430, 1650, 0, 720, 725, 730, 750, 0, 664 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 665 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 666 /* 5 - 1920x1080i@60Hz */ 667 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 668 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 669 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 670 DRM_MODE_FLAG_INTERLACE), 671 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 672 /* 6 - 720(1440)x480i@60Hz */ 673 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 674 801, 858, 0, 480, 488, 494, 525, 0, 675 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 676 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 677 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 678 /* 7 - 720(1440)x480i@60Hz */ 679 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 680 801, 858, 0, 480, 488, 494, 525, 0, 681 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 682 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 683 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 684 /* 8 - 720(1440)x240@60Hz */ 685 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 686 801, 858, 0, 240, 244, 247, 262, 0, 687 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 688 DRM_MODE_FLAG_DBLCLK), 689 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 690 /* 9 - 720(1440)x240@60Hz */ 691 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 692 801, 858, 0, 240, 244, 247, 262, 0, 693 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 694 DRM_MODE_FLAG_DBLCLK), 695 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 696 /* 10 - 2880x480i@60Hz */ 697 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 698 3204, 3432, 0, 480, 488, 494, 525, 0, 699 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 700 DRM_MODE_FLAG_INTERLACE), 701 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 702 /* 11 - 2880x480i@60Hz */ 703 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 704 3204, 3432, 0, 480, 488, 494, 525, 0, 705 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 706 DRM_MODE_FLAG_INTERLACE), 707 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 708 /* 12 - 2880x240@60Hz */ 709 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 710 3204, 3432, 0, 240, 244, 247, 262, 0, 711 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 712 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 713 /* 13 - 2880x240@60Hz */ 714 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 715 3204, 3432, 0, 240, 244, 247, 262, 0, 716 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 717 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 718 /* 14 - 1440x480@60Hz */ 719 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 720 1596, 1716, 0, 480, 489, 495, 525, 0, 721 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 722 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 723 /* 15 - 1440x480@60Hz */ 724 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 725 1596, 1716, 0, 480, 489, 495, 525, 0, 726 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 727 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 728 /* 16 - 1920x1080@60Hz */ 729 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 730 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 731 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 732 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 733 /* 17 - 720x576@50Hz */ 734 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 735 796, 864, 0, 576, 581, 586, 625, 0, 736 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 737 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 738 /* 18 - 720x576@50Hz */ 739 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 740 796, 864, 0, 576, 581, 586, 625, 0, 741 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 742 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 743 /* 19 - 1280x720@50Hz */ 744 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 745 1760, 1980, 0, 720, 725, 730, 750, 0, 746 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 747 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 748 /* 20 - 1920x1080i@50Hz */ 749 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 750 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 751 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 752 DRM_MODE_FLAG_INTERLACE), 753 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 754 /* 21 - 720(1440)x576i@50Hz */ 755 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 756 795, 864, 0, 576, 580, 586, 625, 0, 757 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 758 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 759 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 760 /* 22 - 720(1440)x576i@50Hz */ 761 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 762 795, 864, 0, 576, 580, 586, 625, 0, 763 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 764 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 765 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 766 /* 23 - 720(1440)x288@50Hz */ 767 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 768 795, 864, 0, 288, 290, 293, 312, 0, 769 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 770 DRM_MODE_FLAG_DBLCLK), 771 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 772 /* 24 - 720(1440)x288@50Hz */ 773 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 774 795, 864, 0, 288, 290, 293, 312, 0, 775 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 776 DRM_MODE_FLAG_DBLCLK), 777 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 778 /* 25 - 2880x576i@50Hz */ 779 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 780 3180, 3456, 0, 576, 580, 586, 625, 0, 781 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 782 DRM_MODE_FLAG_INTERLACE), 783 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 784 /* 26 - 2880x576i@50Hz */ 785 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 786 3180, 3456, 0, 576, 580, 586, 625, 0, 787 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 788 DRM_MODE_FLAG_INTERLACE), 789 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 790 /* 27 - 2880x288@50Hz */ 791 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 792 3180, 3456, 0, 288, 290, 293, 312, 0, 793 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 794 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 795 /* 28 - 2880x288@50Hz */ 796 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 797 3180, 3456, 0, 288, 290, 293, 312, 0, 798 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 799 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 800 /* 29 - 1440x576@50Hz */ 801 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 802 1592, 1728, 0, 576, 581, 586, 625, 0, 803 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 804 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 805 /* 30 - 1440x576@50Hz */ 806 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 807 1592, 1728, 0, 576, 581, 586, 625, 0, 808 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 809 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 810 /* 31 - 1920x1080@50Hz */ 811 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 812 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 813 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 814 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 815 /* 32 - 1920x1080@24Hz */ 816 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 817 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 818 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 819 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 820 /* 33 - 1920x1080@25Hz */ 821 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 822 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 823 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 824 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 825 /* 34 - 1920x1080@30Hz */ 826 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 827 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 828 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 829 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 830 /* 35 - 2880x480@60Hz */ 831 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 832 3192, 3432, 0, 480, 489, 495, 525, 0, 833 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 834 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 835 /* 36 - 2880x480@60Hz */ 836 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 837 3192, 3432, 0, 480, 489, 495, 525, 0, 838 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 839 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 840 /* 37 - 2880x576@50Hz */ 841 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 842 3184, 3456, 0, 576, 581, 586, 625, 0, 843 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 844 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 845 /* 38 - 2880x576@50Hz */ 846 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 847 3184, 3456, 0, 576, 581, 586, 625, 0, 848 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 849 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 850 /* 39 - 1920x1080i@50Hz */ 851 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 852 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 853 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 854 DRM_MODE_FLAG_INTERLACE), 855 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 856 /* 40 - 1920x1080i@100Hz */ 857 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 858 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 859 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 860 DRM_MODE_FLAG_INTERLACE), 861 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 862 /* 41 - 1280x720@100Hz */ 863 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 864 1760, 1980, 0, 720, 725, 730, 750, 0, 865 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 866 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 867 /* 42 - 720x576@100Hz */ 868 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 869 796, 864, 0, 576, 581, 586, 625, 0, 870 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 871 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 872 /* 43 - 720x576@100Hz */ 873 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 874 796, 864, 0, 576, 581, 586, 625, 0, 875 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 876 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 877 /* 44 - 720(1440)x576i@100Hz */ 878 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 879 795, 864, 0, 576, 580, 586, 625, 0, 880 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 881 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 882 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 883 /* 45 - 720(1440)x576i@100Hz */ 884 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 885 795, 864, 0, 576, 580, 586, 625, 0, 886 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 887 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 888 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 889 /* 46 - 1920x1080i@120Hz */ 890 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 891 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 892 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 893 DRM_MODE_FLAG_INTERLACE), 894 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 895 /* 47 - 1280x720@120Hz */ 896 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 897 1430, 1650, 0, 720, 725, 730, 750, 0, 898 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 899 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 900 /* 48 - 720x480@120Hz */ 901 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 902 798, 858, 0, 480, 489, 495, 525, 0, 903 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 904 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 905 /* 49 - 720x480@120Hz */ 906 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 907 798, 858, 0, 480, 489, 495, 525, 0, 908 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 909 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 910 /* 50 - 720(1440)x480i@120Hz */ 911 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 912 801, 858, 0, 480, 488, 494, 525, 0, 913 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 914 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 915 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 916 /* 51 - 720(1440)x480i@120Hz */ 917 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 918 801, 858, 0, 480, 488, 494, 525, 0, 919 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 920 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 921 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 922 /* 52 - 720x576@200Hz */ 923 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 924 796, 864, 0, 576, 581, 586, 625, 0, 925 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 926 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 927 /* 53 - 720x576@200Hz */ 928 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 929 796, 864, 0, 576, 581, 586, 625, 0, 930 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 931 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 932 /* 54 - 720(1440)x576i@200Hz */ 933 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 934 795, 864, 0, 576, 580, 586, 625, 0, 935 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 936 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 937 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 938 /* 55 - 720(1440)x576i@200Hz */ 939 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 940 795, 864, 0, 576, 580, 586, 625, 0, 941 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 942 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 943 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 944 /* 56 - 720x480@240Hz */ 945 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 946 798, 858, 0, 480, 489, 495, 525, 0, 947 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 948 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 949 /* 57 - 720x480@240Hz */ 950 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 951 798, 858, 0, 480, 489, 495, 525, 0, 952 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 953 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 954 /* 58 - 720(1440)x480i@240 */ 955 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 956 801, 858, 0, 480, 488, 494, 525, 0, 957 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 958 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 959 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 960 /* 59 - 720(1440)x480i@240 */ 961 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 962 801, 858, 0, 480, 488, 494, 525, 0, 963 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 964 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 965 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 966 /* 60 - 1280x720@24Hz */ 967 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 968 3080, 3300, 0, 720, 725, 730, 750, 0, 969 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 970 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 971 /* 61 - 1280x720@25Hz */ 972 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 973 3740, 3960, 0, 720, 725, 730, 750, 0, 974 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 975 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 976 /* 62 - 1280x720@30Hz */ 977 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 978 3080, 3300, 0, 720, 725, 730, 750, 0, 979 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 980 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 981 /* 63 - 1920x1080@120Hz */ 982 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 983 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 984 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 985 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 986 /* 64 - 1920x1080@100Hz */ 987 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 988 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 989 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 990 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 991 }; 992 993 /* 994 * HDMI 1.4 4k modes. Index using the VIC. 995 */ 996 static const struct drm_display_mode edid_4k_modes[] = { 997 /* 0 - dummy, VICs start at 1 */ 998 { }, 999 /* 1 - 3840x2160@30Hz */ 1000 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1001 3840, 4016, 4104, 4400, 0, 1002 2160, 2168, 2178, 2250, 0, 1003 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1004 .vrefresh = 30, }, 1005 /* 2 - 3840x2160@25Hz */ 1006 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1007 3840, 4896, 4984, 5280, 0, 1008 2160, 2168, 2178, 2250, 0, 1009 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1010 .vrefresh = 25, }, 1011 /* 3 - 3840x2160@24Hz */ 1012 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1013 3840, 5116, 5204, 5500, 0, 1014 2160, 2168, 2178, 2250, 0, 1015 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1016 .vrefresh = 24, }, 1017 /* 4 - 4096x2160@24Hz (SMPTE) */ 1018 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1019 4096, 5116, 5204, 5500, 0, 1020 2160, 2168, 2178, 2250, 0, 1021 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1022 .vrefresh = 24, }, 1023 }; 1024 1025 /*** DDC fetch and block validation ***/ 1026 1027 static const u8 edid_header[] = { 1028 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1029 }; 1030 1031 /** 1032 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1033 * @raw_edid: pointer to raw base EDID block 1034 * 1035 * Sanity check the header of the base EDID block. 1036 * 1037 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1038 */ 1039 int drm_edid_header_is_valid(const u8 *raw_edid) 1040 { 1041 int i, score = 0; 1042 1043 for (i = 0; i < sizeof(edid_header); i++) 1044 if (raw_edid[i] == edid_header[i]) 1045 score++; 1046 1047 return score; 1048 } 1049 EXPORT_SYMBOL(drm_edid_header_is_valid); 1050 1051 static int edid_fixup __read_mostly = 6; 1052 module_param_named(edid_fixup, edid_fixup, int, 0400); 1053 MODULE_PARM_DESC(edid_fixup, 1054 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1055 1056 static void drm_get_displayid(struct drm_connector *connector, 1057 struct edid *edid); 1058 1059 static int drm_edid_block_checksum(const u8 *raw_edid) 1060 { 1061 int i; 1062 u8 csum = 0; 1063 for (i = 0; i < EDID_LENGTH; i++) 1064 csum += raw_edid[i]; 1065 1066 return csum; 1067 } 1068 1069 static bool drm_edid_is_zero(const u8 *in_edid, int length) 1070 { 1071 if (memchr_inv(in_edid, 0, length)) 1072 return false; 1073 1074 return true; 1075 } 1076 1077 /** 1078 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1079 * @raw_edid: pointer to raw EDID block 1080 * @block: type of block to validate (0 for base, extension otherwise) 1081 * @print_bad_edid: if true, dump bad EDID blocks to the console 1082 * @edid_corrupt: if true, the header or checksum is invalid 1083 * 1084 * Validate a base or extension EDID block and optionally dump bad blocks to 1085 * the console. 1086 * 1087 * Return: True if the block is valid, false otherwise. 1088 */ 1089 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 1090 bool *edid_corrupt) 1091 { 1092 u8 csum; 1093 struct edid *edid = (struct edid *)raw_edid; 1094 1095 if (WARN_ON(!raw_edid)) 1096 return false; 1097 1098 if (edid_fixup > 8 || edid_fixup < 0) 1099 edid_fixup = 6; 1100 1101 if (block == 0) { 1102 int score = drm_edid_header_is_valid(raw_edid); 1103 if (score == 8) { 1104 if (edid_corrupt) 1105 *edid_corrupt = false; 1106 } else if (score >= edid_fixup) { 1107 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 1108 * The corrupt flag needs to be set here otherwise, the 1109 * fix-up code here will correct the problem, the 1110 * checksum is correct and the test fails 1111 */ 1112 if (edid_corrupt) 1113 *edid_corrupt = true; 1114 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1115 memcpy(raw_edid, edid_header, sizeof(edid_header)); 1116 } else { 1117 if (edid_corrupt) 1118 *edid_corrupt = true; 1119 goto bad; 1120 } 1121 } 1122 1123 csum = drm_edid_block_checksum(raw_edid); 1124 if (csum) { 1125 if (print_bad_edid) { 1126 DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum); 1127 } 1128 1129 if (edid_corrupt) 1130 *edid_corrupt = true; 1131 1132 /* allow CEA to slide through, switches mangle this */ 1133 if (raw_edid[0] != 0x02) 1134 goto bad; 1135 } 1136 1137 /* per-block-type checks */ 1138 switch (raw_edid[0]) { 1139 case 0: /* base */ 1140 if (edid->version != 1) { 1141 DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version); 1142 goto bad; 1143 } 1144 1145 if (edid->revision > 4) 1146 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1147 break; 1148 1149 default: 1150 break; 1151 } 1152 1153 return true; 1154 1155 bad: 1156 if (print_bad_edid) { 1157 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) { 1158 printk(KERN_ERR "EDID block is all zeroes\n"); 1159 } else { 1160 printk(KERN_ERR "Raw EDID:\n"); 1161 print_hex_dump(KERN_ERR, " \t", DUMP_PREFIX_NONE, 16, 1, 1162 raw_edid, EDID_LENGTH, false); 1163 } 1164 } 1165 return false; 1166 } 1167 EXPORT_SYMBOL(drm_edid_block_valid); 1168 1169 /** 1170 * drm_edid_is_valid - sanity check EDID data 1171 * @edid: EDID data 1172 * 1173 * Sanity-check an entire EDID record (including extensions) 1174 * 1175 * Return: True if the EDID data is valid, false otherwise. 1176 */ 1177 bool drm_edid_is_valid(struct edid *edid) 1178 { 1179 int i; 1180 u8 *raw = (u8 *)edid; 1181 1182 if (!edid) 1183 return false; 1184 1185 for (i = 0; i <= edid->extensions; i++) 1186 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL)) 1187 return false; 1188 1189 return true; 1190 } 1191 EXPORT_SYMBOL(drm_edid_is_valid); 1192 1193 #define DDC_SEGMENT_ADDR 0x30 1194 /** 1195 * drm_do_probe_ddc_edid() - get EDID information via I2C 1196 * @data: I2C device adapter 1197 * @buf: EDID data buffer to be filled 1198 * @block: 128 byte EDID block to start fetching from 1199 * @len: EDID data buffer length to fetch 1200 * 1201 * Try to fetch EDID information by calling I2C driver functions. 1202 * 1203 * Return: 0 on success or -1 on failure. 1204 */ 1205 static int 1206 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 1207 { 1208 struct i2c_adapter *adapter = data; 1209 unsigned char start = block * EDID_LENGTH; 1210 unsigned char segment = block >> 1; 1211 unsigned char xfers = segment ? 3 : 2; 1212 int ret, retries = 5; 1213 1214 /* 1215 * The core I2C driver will automatically retry the transfer if the 1216 * adapter reports EAGAIN. However, we find that bit-banging transfers 1217 * are susceptible to errors under a heavily loaded machine and 1218 * generate spurious NAKs and timeouts. Retrying the transfer 1219 * of the individual block a few times seems to overcome this. 1220 */ 1221 do { 1222 struct i2c_msg msgs[] = { 1223 { 1224 .addr = DDC_SEGMENT_ADDR, 1225 .flags = 0, 1226 .len = 1, 1227 .buf = &segment, 1228 }, { 1229 .addr = DDC_ADDR, 1230 .flags = 0, 1231 .len = 1, 1232 .buf = &start, 1233 }, { 1234 .addr = DDC_ADDR, 1235 .flags = I2C_M_RD, 1236 .len = len, 1237 .buf = buf, 1238 } 1239 }; 1240 1241 /* 1242 * Avoid sending the segment addr to not upset non-compliant 1243 * DDC monitors. 1244 */ 1245 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 1246 1247 if (ret == -ENXIO) { 1248 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 1249 adapter->name); 1250 break; 1251 } 1252 } while (ret != xfers && --retries); 1253 1254 return ret == xfers ? 0 : -1; 1255 } 1256 1257 /** 1258 * drm_do_get_edid - get EDID data using a custom EDID block read function 1259 * @connector: connector we're probing 1260 * @get_edid_block: EDID block read function 1261 * @data: private data passed to the block read function 1262 * 1263 * When the I2C adapter connected to the DDC bus is hidden behind a device that 1264 * exposes a different interface to read EDID blocks this function can be used 1265 * to get EDID data using a custom block read function. 1266 * 1267 * As in the general case the DDC bus is accessible by the kernel at the I2C 1268 * level, drivers must make all reasonable efforts to expose it as an I2C 1269 * adapter and use drm_get_edid() instead of abusing this function. 1270 * 1271 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1272 */ 1273 struct edid *drm_do_get_edid(struct drm_connector *connector, 1274 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 1275 size_t len), 1276 void *data) 1277 { 1278 int i, j = 0, valid_extensions = 0; 1279 u8 *block, *new; 1280 bool print_bad_edid = !connector->bad_edid_counter || (drm_debug & DRM_UT_KMS); 1281 1282 if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) 1283 return NULL; 1284 1285 /* base block fetch */ 1286 for (i = 0; i < 4; i++) { 1287 if (get_edid_block(data, block, 0, EDID_LENGTH)) 1288 goto out; 1289 if (drm_edid_block_valid(block, 0, print_bad_edid, 1290 &connector->edid_corrupt)) 1291 break; 1292 if (i == 0 && drm_edid_is_zero(block, EDID_LENGTH)) { 1293 connector->null_edid_counter++; 1294 goto carp; 1295 } 1296 } 1297 if (i == 4) 1298 goto carp; 1299 1300 /* if there's no extensions, we're done */ 1301 if (block[0x7e] == 0) 1302 return (struct edid *)block; 1303 1304 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL); 1305 if (!new) 1306 goto out; 1307 block = new; 1308 1309 for (j = 1; j <= block[0x7e]; j++) { 1310 for (i = 0; i < 4; i++) { 1311 if (get_edid_block(data, 1312 block + (valid_extensions + 1) * EDID_LENGTH, 1313 j, EDID_LENGTH)) 1314 goto out; 1315 if (drm_edid_block_valid(block + (valid_extensions + 1) 1316 * EDID_LENGTH, j, 1317 print_bad_edid, 1318 NULL)) { 1319 valid_extensions++; 1320 break; 1321 } 1322 } 1323 1324 if (i == 4 && print_bad_edid) { 1325 dev_warn(connector->dev->dev, 1326 "%s: Ignoring invalid EDID block %d.\n", 1327 connector->name, j); 1328 1329 connector->bad_edid_counter++; 1330 } 1331 } 1332 1333 if (valid_extensions != block[0x7e]) { 1334 block[EDID_LENGTH-1] += block[0x7e] - valid_extensions; 1335 block[0x7e] = valid_extensions; 1336 new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1337 if (!new) 1338 goto out; 1339 block = new; 1340 } 1341 1342 return (struct edid *)block; 1343 1344 carp: 1345 if (print_bad_edid) { 1346 dev_warn(connector->dev->dev, "%s: EDID block %d invalid.\n", 1347 connector->name, j); 1348 } 1349 connector->bad_edid_counter++; 1350 1351 out: 1352 kfree(block); 1353 return NULL; 1354 } 1355 EXPORT_SYMBOL_GPL(drm_do_get_edid); 1356 1357 /** 1358 * drm_probe_ddc() - probe DDC presence 1359 * @adapter: I2C adapter to probe 1360 * 1361 * Return: True on success, false on failure. 1362 */ 1363 bool 1364 drm_probe_ddc(struct i2c_adapter *adapter) 1365 { 1366 unsigned char out; 1367 1368 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 1369 } 1370 EXPORT_SYMBOL(drm_probe_ddc); 1371 1372 /** 1373 * drm_get_edid - get EDID data, if available 1374 * @connector: connector we're probing 1375 * @adapter: I2C adapter to use for DDC 1376 * 1377 * Poke the given I2C channel to grab EDID data if possible. If found, 1378 * attach it to the connector. 1379 * 1380 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1381 */ 1382 struct edid *drm_get_edid(struct drm_connector *connector, 1383 struct i2c_adapter *adapter) 1384 { 1385 struct edid *edid; 1386 1387 if (!drm_probe_ddc(adapter)) 1388 return NULL; 1389 1390 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); 1391 if (edid) 1392 drm_get_displayid(connector, edid); 1393 return edid; 1394 } 1395 EXPORT_SYMBOL(drm_get_edid); 1396 1397 /** 1398 * drm_edid_duplicate - duplicate an EDID and the extensions 1399 * @edid: EDID to duplicate 1400 * 1401 * Return: Pointer to duplicated EDID or NULL on allocation failure. 1402 */ 1403 struct edid *drm_edid_duplicate(const struct edid *edid) 1404 { 1405 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1406 } 1407 EXPORT_SYMBOL(drm_edid_duplicate); 1408 1409 /*** EDID parsing ***/ 1410 1411 /** 1412 * edid_vendor - match a string against EDID's obfuscated vendor field 1413 * @edid: EDID to match 1414 * @vendor: vendor string 1415 * 1416 * Returns true if @vendor is in @edid, false otherwise 1417 */ 1418 static bool edid_vendor(struct edid *edid, char *vendor) 1419 { 1420 char edid_vendor[3]; 1421 1422 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 1423 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 1424 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 1425 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 1426 1427 return !strncmp(edid_vendor, vendor, 3); 1428 } 1429 1430 /** 1431 * edid_get_quirks - return quirk flags for a given EDID 1432 * @edid: EDID to process 1433 * 1434 * This tells subsequent routines what fixes they need to apply. 1435 */ 1436 static u32 edid_get_quirks(struct edid *edid) 1437 { 1438 struct edid_quirk *quirk; 1439 int i; 1440 1441 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 1442 quirk = &edid_quirk_list[i]; 1443 1444 if (edid_vendor(edid, quirk->vendor) && 1445 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 1446 return quirk->quirks; 1447 } 1448 1449 return 0; 1450 } 1451 1452 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 1453 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 1454 1455 /** 1456 * edid_fixup_preferred - set preferred modes based on quirk list 1457 * @connector: has mode list to fix up 1458 * @quirks: quirks list 1459 * 1460 * Walk the mode list for @connector, clearing the preferred status 1461 * on existing modes and setting it anew for the right mode ala @quirks. 1462 */ 1463 static void edid_fixup_preferred(struct drm_connector *connector, 1464 u32 quirks) 1465 { 1466 struct drm_display_mode *t, *cur_mode, *preferred_mode; 1467 int target_refresh = 0; 1468 int cur_vrefresh, preferred_vrefresh; 1469 1470 if (list_empty(&connector->probed_modes)) 1471 return; 1472 1473 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 1474 target_refresh = 60; 1475 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 1476 target_refresh = 75; 1477 1478 preferred_mode = list_first_entry(&connector->probed_modes, 1479 struct drm_display_mode, head); 1480 1481 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 1482 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 1483 1484 if (cur_mode == preferred_mode) 1485 continue; 1486 1487 /* Largest mode is preferred */ 1488 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 1489 preferred_mode = cur_mode; 1490 1491 cur_vrefresh = cur_mode->vrefresh ? 1492 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode); 1493 preferred_vrefresh = preferred_mode->vrefresh ? 1494 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode); 1495 /* At a given size, try to get closest to target refresh */ 1496 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 1497 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 1498 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 1499 preferred_mode = cur_mode; 1500 } 1501 } 1502 1503 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 1504 } 1505 1506 static bool 1507 mode_is_rb(const struct drm_display_mode *mode) 1508 { 1509 return (mode->htotal - mode->hdisplay == 160) && 1510 (mode->hsync_end - mode->hdisplay == 80) && 1511 (mode->hsync_end - mode->hsync_start == 32) && 1512 (mode->vsync_start - mode->vdisplay == 3); 1513 } 1514 1515 /* 1516 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 1517 * @dev: Device to duplicate against 1518 * @hsize: Mode width 1519 * @vsize: Mode height 1520 * @fresh: Mode refresh rate 1521 * @rb: Mode reduced-blanking-ness 1522 * 1523 * Walk the DMT mode list looking for a match for the given parameters. 1524 * 1525 * Return: A newly allocated copy of the mode, or NULL if not found. 1526 */ 1527 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 1528 int hsize, int vsize, int fresh, 1529 bool rb) 1530 { 1531 int i; 1532 1533 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 1534 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 1535 if (hsize != ptr->hdisplay) 1536 continue; 1537 if (vsize != ptr->vdisplay) 1538 continue; 1539 if (fresh != drm_mode_vrefresh(ptr)) 1540 continue; 1541 if (rb != mode_is_rb(ptr)) 1542 continue; 1543 1544 return drm_mode_duplicate(dev, ptr); 1545 } 1546 1547 return NULL; 1548 } 1549 EXPORT_SYMBOL(drm_mode_find_dmt); 1550 1551 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 1552 1553 static void 1554 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1555 { 1556 int i, n = 0; 1557 u8 d = ext[0x02]; 1558 u8 *det_base = ext + d; 1559 1560 n = (127 - d) / 18; 1561 for (i = 0; i < n; i++) 1562 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1563 } 1564 1565 static void 1566 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1567 { 1568 unsigned int i, n = min((int)ext[0x02], 6); 1569 u8 *det_base = ext + 5; 1570 1571 if (ext[0x01] != 1) 1572 return; /* unknown version */ 1573 1574 for (i = 0; i < n; i++) 1575 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1576 } 1577 1578 static void 1579 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 1580 { 1581 int i; 1582 struct edid *edid = (struct edid *)raw_edid; 1583 1584 if (edid == NULL) 1585 return; 1586 1587 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 1588 cb(&(edid->detailed_timings[i]), closure); 1589 1590 for (i = 1; i <= raw_edid[0x7e]; i++) { 1591 u8 *ext = raw_edid + (i * EDID_LENGTH); 1592 switch (*ext) { 1593 case CEA_EXT: 1594 cea_for_each_detailed_block(ext, cb, closure); 1595 break; 1596 case VTB_EXT: 1597 vtb_for_each_detailed_block(ext, cb, closure); 1598 break; 1599 default: 1600 break; 1601 } 1602 } 1603 } 1604 1605 static void 1606 is_rb(struct detailed_timing *t, void *data) 1607 { 1608 u8 *r = (u8 *)t; 1609 if (r[3] == EDID_DETAIL_MONITOR_RANGE) 1610 if (r[15] & 0x10) 1611 *(bool *)data = true; 1612 } 1613 1614 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 1615 static bool 1616 drm_monitor_supports_rb(struct edid *edid) 1617 { 1618 if (edid->revision >= 4) { 1619 bool ret = false; 1620 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 1621 return ret; 1622 } 1623 1624 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 1625 } 1626 1627 static void 1628 find_gtf2(struct detailed_timing *t, void *data) 1629 { 1630 u8 *r = (u8 *)t; 1631 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) 1632 *(u8 **)data = r; 1633 } 1634 1635 /* Secondary GTF curve kicks in above some break frequency */ 1636 static int 1637 drm_gtf2_hbreak(struct edid *edid) 1638 { 1639 u8 *r = NULL; 1640 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1641 return r ? (r[12] * 2) : 0; 1642 } 1643 1644 static int 1645 drm_gtf2_2c(struct edid *edid) 1646 { 1647 u8 *r = NULL; 1648 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1649 return r ? r[13] : 0; 1650 } 1651 1652 static int 1653 drm_gtf2_m(struct edid *edid) 1654 { 1655 u8 *r = NULL; 1656 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1657 return r ? (r[15] << 8) + r[14] : 0; 1658 } 1659 1660 static int 1661 drm_gtf2_k(struct edid *edid) 1662 { 1663 u8 *r = NULL; 1664 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1665 return r ? r[16] : 0; 1666 } 1667 1668 static int 1669 drm_gtf2_2j(struct edid *edid) 1670 { 1671 u8 *r = NULL; 1672 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1673 return r ? r[17] : 0; 1674 } 1675 1676 /** 1677 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 1678 * @edid: EDID block to scan 1679 */ 1680 static int standard_timing_level(struct edid *edid) 1681 { 1682 if (edid->revision >= 2) { 1683 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 1684 return LEVEL_CVT; 1685 if (drm_gtf2_hbreak(edid)) 1686 return LEVEL_GTF2; 1687 return LEVEL_GTF; 1688 } 1689 return LEVEL_DMT; 1690 } 1691 1692 /* 1693 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 1694 * monitors fill with ascii space (0x20) instead. 1695 */ 1696 static int 1697 bad_std_timing(u8 a, u8 b) 1698 { 1699 return (a == 0x00 && b == 0x00) || 1700 (a == 0x01 && b == 0x01) || 1701 (a == 0x20 && b == 0x20); 1702 } 1703 1704 /** 1705 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 1706 * @connector: connector of for the EDID block 1707 * @edid: EDID block to scan 1708 * @t: standard timing params 1709 * 1710 * Take the standard timing params (in this case width, aspect, and refresh) 1711 * and convert them into a real mode using CVT/GTF/DMT. 1712 */ 1713 static struct drm_display_mode * 1714 drm_mode_std(struct drm_connector *connector, struct edid *edid, 1715 struct std_timing *t) 1716 { 1717 struct drm_device *dev = connector->dev; 1718 struct drm_display_mode *m, *mode = NULL; 1719 int hsize, vsize; 1720 int vrefresh_rate; 1721 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 1722 >> EDID_TIMING_ASPECT_SHIFT; 1723 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 1724 >> EDID_TIMING_VFREQ_SHIFT; 1725 int timing_level = standard_timing_level(edid); 1726 1727 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 1728 return NULL; 1729 1730 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 1731 hsize = t->hsize * 8 + 248; 1732 /* vrefresh_rate = vfreq + 60 */ 1733 vrefresh_rate = vfreq + 60; 1734 /* the vdisplay is calculated based on the aspect ratio */ 1735 if (aspect_ratio == 0) { 1736 if (edid->revision < 3) 1737 vsize = hsize; 1738 else 1739 vsize = (hsize * 10) / 16; 1740 } else if (aspect_ratio == 1) 1741 vsize = (hsize * 3) / 4; 1742 else if (aspect_ratio == 2) 1743 vsize = (hsize * 4) / 5; 1744 else 1745 vsize = (hsize * 9) / 16; 1746 1747 /* HDTV hack, part 1 */ 1748 if (vrefresh_rate == 60 && 1749 ((hsize == 1360 && vsize == 765) || 1750 (hsize == 1368 && vsize == 769))) { 1751 hsize = 1366; 1752 vsize = 768; 1753 } 1754 1755 /* 1756 * If this connector already has a mode for this size and refresh 1757 * rate (because it came from detailed or CVT info), use that 1758 * instead. This way we don't have to guess at interlace or 1759 * reduced blanking. 1760 */ 1761 list_for_each_entry(m, &connector->probed_modes, head) 1762 if (m->hdisplay == hsize && m->vdisplay == vsize && 1763 drm_mode_vrefresh(m) == vrefresh_rate) 1764 return NULL; 1765 1766 /* HDTV hack, part 2 */ 1767 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 1768 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 1769 false); 1770 mode->hdisplay = 1366; 1771 mode->hsync_start = mode->hsync_start - 1; 1772 mode->hsync_end = mode->hsync_end - 1; 1773 return mode; 1774 } 1775 1776 /* check whether it can be found in default mode table */ 1777 if (drm_monitor_supports_rb(edid)) { 1778 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 1779 true); 1780 if (mode) 1781 return mode; 1782 } 1783 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 1784 if (mode) 1785 return mode; 1786 1787 /* okay, generate it */ 1788 switch (timing_level) { 1789 case LEVEL_DMT: 1790 break; 1791 case LEVEL_GTF: 1792 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 1793 break; 1794 case LEVEL_GTF2: 1795 /* 1796 * This is potentially wrong if there's ever a monitor with 1797 * more than one ranges section, each claiming a different 1798 * secondary GTF curve. Please don't do that. 1799 */ 1800 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 1801 if (!mode) 1802 return NULL; 1803 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 1804 drm_mode_destroy(dev, mode); 1805 mode = drm_gtf_mode_complex(dev, hsize, vsize, 1806 vrefresh_rate, 0, 0, 1807 drm_gtf2_m(edid), 1808 drm_gtf2_2c(edid), 1809 drm_gtf2_k(edid), 1810 drm_gtf2_2j(edid)); 1811 } 1812 break; 1813 case LEVEL_CVT: 1814 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 1815 false); 1816 break; 1817 } 1818 return mode; 1819 } 1820 1821 /* 1822 * EDID is delightfully ambiguous about how interlaced modes are to be 1823 * encoded. Our internal representation is of frame height, but some 1824 * HDTV detailed timings are encoded as field height. 1825 * 1826 * The format list here is from CEA, in frame size. Technically we 1827 * should be checking refresh rate too. Whatever. 1828 */ 1829 static void 1830 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 1831 struct detailed_pixel_timing *pt) 1832 { 1833 int i; 1834 static const struct { 1835 int w, h; 1836 } cea_interlaced[] = { 1837 { 1920, 1080 }, 1838 { 720, 480 }, 1839 { 1440, 480 }, 1840 { 2880, 480 }, 1841 { 720, 576 }, 1842 { 1440, 576 }, 1843 { 2880, 576 }, 1844 }; 1845 1846 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 1847 return; 1848 1849 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 1850 if ((mode->hdisplay == cea_interlaced[i].w) && 1851 (mode->vdisplay == cea_interlaced[i].h / 2)) { 1852 mode->vdisplay *= 2; 1853 mode->vsync_start *= 2; 1854 mode->vsync_end *= 2; 1855 mode->vtotal *= 2; 1856 mode->vtotal |= 1; 1857 } 1858 } 1859 1860 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1861 } 1862 1863 /** 1864 * drm_mode_detailed - create a new mode from an EDID detailed timing section 1865 * @dev: DRM device (needed to create new mode) 1866 * @edid: EDID block 1867 * @timing: EDID detailed timing info 1868 * @quirks: quirks to apply 1869 * 1870 * An EDID detailed timing block contains enough info for us to create and 1871 * return a new struct drm_display_mode. 1872 */ 1873 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 1874 struct edid *edid, 1875 struct detailed_timing *timing, 1876 u32 quirks) 1877 { 1878 struct drm_display_mode *mode; 1879 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 1880 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 1881 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 1882 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 1883 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 1884 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 1885 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 1886 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 1887 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 1888 1889 /* ignore tiny modes */ 1890 if (hactive < 64 || vactive < 64) 1891 return NULL; 1892 1893 if (pt->misc & DRM_EDID_PT_STEREO) { 1894 DRM_DEBUG_KMS("stereo mode not supported\n"); 1895 return NULL; 1896 } 1897 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 1898 DRM_DEBUG_KMS("composite sync not supported\n"); 1899 } 1900 1901 /* it is incorrect if hsync/vsync width is zero */ 1902 if (!hsync_pulse_width || !vsync_pulse_width) { 1903 DRM_DEBUG_KMS("Incorrect Detailed timing. " 1904 "Wrong Hsync/Vsync pulse width\n"); 1905 return NULL; 1906 } 1907 1908 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 1909 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 1910 if (!mode) 1911 return NULL; 1912 1913 goto set_size; 1914 } 1915 1916 mode = drm_mode_create(dev); 1917 if (!mode) 1918 return NULL; 1919 1920 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 1921 timing->pixel_clock = cpu_to_le16(1088); 1922 1923 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 1924 1925 mode->hdisplay = hactive; 1926 mode->hsync_start = mode->hdisplay + hsync_offset; 1927 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 1928 mode->htotal = mode->hdisplay + hblank; 1929 1930 mode->vdisplay = vactive; 1931 mode->vsync_start = mode->vdisplay + vsync_offset; 1932 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 1933 mode->vtotal = mode->vdisplay + vblank; 1934 1935 /* Some EDIDs have bogus h/vtotal values */ 1936 if (mode->hsync_end > mode->htotal) 1937 mode->htotal = mode->hsync_end + 1; 1938 if (mode->vsync_end > mode->vtotal) 1939 mode->vtotal = mode->vsync_end + 1; 1940 1941 drm_mode_do_interlace_quirk(mode, pt); 1942 1943 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 1944 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; 1945 } 1946 1947 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 1948 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 1949 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 1950 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 1951 1952 set_size: 1953 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 1954 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 1955 1956 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 1957 mode->width_mm *= 10; 1958 mode->height_mm *= 10; 1959 } 1960 1961 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 1962 mode->width_mm = edid->width_cm * 10; 1963 mode->height_mm = edid->height_cm * 10; 1964 } 1965 1966 mode->type = DRM_MODE_TYPE_DRIVER; 1967 mode->vrefresh = drm_mode_vrefresh(mode); 1968 drm_mode_set_name(mode); 1969 1970 return mode; 1971 } 1972 1973 static bool 1974 mode_in_hsync_range(const struct drm_display_mode *mode, 1975 struct edid *edid, u8 *t) 1976 { 1977 int hsync, hmin, hmax; 1978 1979 hmin = t[7]; 1980 if (edid->revision >= 4) 1981 hmin += ((t[4] & 0x04) ? 255 : 0); 1982 hmax = t[8]; 1983 if (edid->revision >= 4) 1984 hmax += ((t[4] & 0x08) ? 255 : 0); 1985 hsync = drm_mode_hsync(mode); 1986 1987 return (hsync <= hmax && hsync >= hmin); 1988 } 1989 1990 static bool 1991 mode_in_vsync_range(const struct drm_display_mode *mode, 1992 struct edid *edid, u8 *t) 1993 { 1994 int vsync, vmin, vmax; 1995 1996 vmin = t[5]; 1997 if (edid->revision >= 4) 1998 vmin += ((t[4] & 0x01) ? 255 : 0); 1999 vmax = t[6]; 2000 if (edid->revision >= 4) 2001 vmax += ((t[4] & 0x02) ? 255 : 0); 2002 vsync = drm_mode_vrefresh(mode); 2003 2004 return (vsync <= vmax && vsync >= vmin); 2005 } 2006 2007 static u32 2008 range_pixel_clock(struct edid *edid, u8 *t) 2009 { 2010 /* unspecified */ 2011 if (t[9] == 0 || t[9] == 255) 2012 return 0; 2013 2014 /* 1.4 with CVT support gives us real precision, yay */ 2015 if (edid->revision >= 4 && t[10] == 0x04) 2016 return (t[9] * 10000) - ((t[12] >> 2) * 250); 2017 2018 /* 1.3 is pathetic, so fuzz up a bit */ 2019 return t[9] * 10000 + 5001; 2020 } 2021 2022 static bool 2023 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 2024 struct detailed_timing *timing) 2025 { 2026 u32 max_clock; 2027 u8 *t = (u8 *)timing; 2028 2029 if (!mode_in_hsync_range(mode, edid, t)) 2030 return false; 2031 2032 if (!mode_in_vsync_range(mode, edid, t)) 2033 return false; 2034 2035 if ((max_clock = range_pixel_clock(edid, t))) 2036 if (mode->clock > max_clock) 2037 return false; 2038 2039 /* 1.4 max horizontal check */ 2040 if (edid->revision >= 4 && t[10] == 0x04) 2041 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 2042 return false; 2043 2044 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 2045 return false; 2046 2047 return true; 2048 } 2049 2050 static bool valid_inferred_mode(const struct drm_connector *connector, 2051 const struct drm_display_mode *mode) 2052 { 2053 const struct drm_display_mode *m; 2054 bool ok = false; 2055 2056 list_for_each_entry(m, &connector->probed_modes, head) { 2057 if (mode->hdisplay == m->hdisplay && 2058 mode->vdisplay == m->vdisplay && 2059 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 2060 return false; /* duplicated */ 2061 if (mode->hdisplay <= m->hdisplay && 2062 mode->vdisplay <= m->vdisplay) 2063 ok = true; 2064 } 2065 return ok; 2066 } 2067 2068 static int 2069 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2070 struct detailed_timing *timing) 2071 { 2072 int i, modes = 0; 2073 struct drm_display_mode *newmode; 2074 struct drm_device *dev = connector->dev; 2075 2076 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2077 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 2078 valid_inferred_mode(connector, drm_dmt_modes + i)) { 2079 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 2080 if (newmode) { 2081 drm_mode_probed_add(connector, newmode); 2082 modes++; 2083 } 2084 } 2085 } 2086 2087 return modes; 2088 } 2089 2090 /* fix up 1366x768 mode from 1368x768; 2091 * GFT/CVT can't express 1366 width which isn't dividable by 8 2092 */ 2093 static void fixup_mode_1366x768(struct drm_display_mode *mode) 2094 { 2095 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 2096 mode->hdisplay = 1366; 2097 mode->hsync_start--; 2098 mode->hsync_end--; 2099 drm_mode_set_name(mode); 2100 } 2101 } 2102 2103 static int 2104 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, 2105 struct detailed_timing *timing) 2106 { 2107 int i, modes = 0; 2108 struct drm_display_mode *newmode; 2109 struct drm_device *dev = connector->dev; 2110 2111 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2112 const struct minimode *m = &extra_modes[i]; 2113 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 2114 if (!newmode) 2115 return modes; 2116 2117 fixup_mode_1366x768(newmode); 2118 if (!mode_in_range(newmode, edid, timing) || 2119 !valid_inferred_mode(connector, newmode)) { 2120 drm_mode_destroy(dev, newmode); 2121 continue; 2122 } 2123 2124 drm_mode_probed_add(connector, newmode); 2125 modes++; 2126 } 2127 2128 return modes; 2129 } 2130 2131 static int 2132 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2133 struct detailed_timing *timing) 2134 { 2135 int i, modes = 0; 2136 struct drm_display_mode *newmode; 2137 struct drm_device *dev = connector->dev; 2138 bool rb = drm_monitor_supports_rb(edid); 2139 2140 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2141 const struct minimode *m = &extra_modes[i]; 2142 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 2143 if (!newmode) 2144 return modes; 2145 2146 fixup_mode_1366x768(newmode); 2147 if (!mode_in_range(newmode, edid, timing) || 2148 !valid_inferred_mode(connector, newmode)) { 2149 drm_mode_destroy(dev, newmode); 2150 continue; 2151 } 2152 2153 drm_mode_probed_add(connector, newmode); 2154 modes++; 2155 } 2156 2157 return modes; 2158 } 2159 2160 static void 2161 do_inferred_modes(struct detailed_timing *timing, void *c) 2162 { 2163 struct detailed_mode_closure *closure = c; 2164 struct detailed_non_pixel *data = &timing->data.other_data; 2165 struct detailed_data_monitor_range *range = &data->data.range; 2166 2167 if (data->type != EDID_DETAIL_MONITOR_RANGE) 2168 return; 2169 2170 closure->modes += drm_dmt_modes_for_range(closure->connector, 2171 closure->edid, 2172 timing); 2173 2174 if (!version_greater(closure->edid, 1, 1)) 2175 return; /* GTF not defined yet */ 2176 2177 switch (range->flags) { 2178 case 0x02: /* secondary gtf, XXX could do more */ 2179 case 0x00: /* default gtf */ 2180 closure->modes += drm_gtf_modes_for_range(closure->connector, 2181 closure->edid, 2182 timing); 2183 break; 2184 case 0x04: /* cvt, only in 1.4+ */ 2185 if (!version_greater(closure->edid, 1, 3)) 2186 break; 2187 2188 closure->modes += drm_cvt_modes_for_range(closure->connector, 2189 closure->edid, 2190 timing); 2191 break; 2192 case 0x01: /* just the ranges, no formula */ 2193 default: 2194 break; 2195 } 2196 } 2197 2198 static int 2199 add_inferred_modes(struct drm_connector *connector, struct edid *edid) 2200 { 2201 struct detailed_mode_closure closure = { 2202 .connector = connector, 2203 .edid = edid, 2204 }; 2205 2206 if (version_greater(edid, 1, 0)) 2207 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 2208 &closure); 2209 2210 return closure.modes; 2211 } 2212 2213 static int 2214 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 2215 { 2216 int i, j, m, modes = 0; 2217 struct drm_display_mode *mode; 2218 u8 *est = ((u8 *)timing) + 5; 2219 2220 for (i = 0; i < 6; i++) { 2221 for (j = 7; j >= 0; j--) { 2222 m = (i * 8) + (7 - j); 2223 if (m >= ARRAY_SIZE(est3_modes)) 2224 break; 2225 if (est[i] & (1 << j)) { 2226 mode = drm_mode_find_dmt(connector->dev, 2227 est3_modes[m].w, 2228 est3_modes[m].h, 2229 est3_modes[m].r, 2230 est3_modes[m].rb); 2231 if (mode) { 2232 drm_mode_probed_add(connector, mode); 2233 modes++; 2234 } 2235 } 2236 } 2237 } 2238 2239 return modes; 2240 } 2241 2242 static void 2243 do_established_modes(struct detailed_timing *timing, void *c) 2244 { 2245 struct detailed_mode_closure *closure = c; 2246 struct detailed_non_pixel *data = &timing->data.other_data; 2247 2248 if (data->type == EDID_DETAIL_EST_TIMINGS) 2249 closure->modes += drm_est3_modes(closure->connector, timing); 2250 } 2251 2252 /** 2253 * add_established_modes - get est. modes from EDID and add them 2254 * @connector: connector to add mode(s) to 2255 * @edid: EDID block to scan 2256 * 2257 * Each EDID block contains a bitmap of the supported "established modes" list 2258 * (defined above). Tease them out and add them to the global modes list. 2259 */ 2260 static int 2261 add_established_modes(struct drm_connector *connector, struct edid *edid) 2262 { 2263 struct drm_device *dev = connector->dev; 2264 unsigned long est_bits = edid->established_timings.t1 | 2265 (edid->established_timings.t2 << 8) | 2266 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 2267 int i, modes = 0; 2268 struct detailed_mode_closure closure = { 2269 .connector = connector, 2270 .edid = edid, 2271 }; 2272 2273 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 2274 if (est_bits & (1<<i)) { 2275 struct drm_display_mode *newmode; 2276 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 2277 if (newmode) { 2278 drm_mode_probed_add(connector, newmode); 2279 modes++; 2280 } 2281 } 2282 } 2283 2284 if (version_greater(edid, 1, 0)) 2285 drm_for_each_detailed_block((u8 *)edid, 2286 do_established_modes, &closure); 2287 2288 return modes + closure.modes; 2289 } 2290 2291 static void 2292 do_standard_modes(struct detailed_timing *timing, void *c) 2293 { 2294 struct detailed_mode_closure *closure = c; 2295 struct detailed_non_pixel *data = &timing->data.other_data; 2296 struct drm_connector *connector = closure->connector; 2297 struct edid *edid = closure->edid; 2298 2299 if (data->type == EDID_DETAIL_STD_MODES) { 2300 int i; 2301 for (i = 0; i < 6; i++) { 2302 struct std_timing *std; 2303 struct drm_display_mode *newmode; 2304 2305 std = &data->data.timings[i]; 2306 newmode = drm_mode_std(connector, edid, std); 2307 if (newmode) { 2308 drm_mode_probed_add(connector, newmode); 2309 closure->modes++; 2310 } 2311 } 2312 } 2313 } 2314 2315 /** 2316 * add_standard_modes - get std. modes from EDID and add them 2317 * @connector: connector to add mode(s) to 2318 * @edid: EDID block to scan 2319 * 2320 * Standard modes can be calculated using the appropriate standard (DMT, 2321 * GTF or CVT. Grab them from @edid and add them to the list. 2322 */ 2323 static int 2324 add_standard_modes(struct drm_connector *connector, struct edid *edid) 2325 { 2326 int i, modes = 0; 2327 struct detailed_mode_closure closure = { 2328 .connector = connector, 2329 .edid = edid, 2330 }; 2331 2332 for (i = 0; i < EDID_STD_TIMINGS; i++) { 2333 struct drm_display_mode *newmode; 2334 2335 newmode = drm_mode_std(connector, edid, 2336 &edid->standard_timings[i]); 2337 if (newmode) { 2338 drm_mode_probed_add(connector, newmode); 2339 modes++; 2340 } 2341 } 2342 2343 if (version_greater(edid, 1, 0)) 2344 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 2345 &closure); 2346 2347 /* XXX should also look for standard codes in VTB blocks */ 2348 2349 return modes + closure.modes; 2350 } 2351 2352 static int drm_cvt_modes(struct drm_connector *connector, 2353 struct detailed_timing *timing) 2354 { 2355 int i, j, modes = 0; 2356 struct drm_display_mode *newmode; 2357 struct drm_device *dev = connector->dev; 2358 struct cvt_timing *cvt; 2359 const int rates[] = { 60, 85, 75, 60, 50 }; 2360 const u8 empty[3] = { 0, 0, 0 }; 2361 2362 for (i = 0; i < 4; i++) { 2363 int uninitialized_var(width), height; 2364 cvt = &(timing->data.other_data.data.cvt[i]); 2365 2366 if (!memcmp(cvt->code, empty, 3)) 2367 continue; 2368 2369 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 2370 switch (cvt->code[1] & 0x0c) { 2371 case 0x00: 2372 width = height * 4 / 3; 2373 break; 2374 case 0x04: 2375 width = height * 16 / 9; 2376 break; 2377 case 0x08: 2378 width = height * 16 / 10; 2379 break; 2380 case 0x0c: 2381 width = height * 15 / 9; 2382 break; 2383 } 2384 2385 for (j = 1; j < 5; j++) { 2386 if (cvt->code[2] & (1 << j)) { 2387 newmode = drm_cvt_mode(dev, width, height, 2388 rates[j], j == 0, 2389 false, false); 2390 if (newmode) { 2391 drm_mode_probed_add(connector, newmode); 2392 modes++; 2393 } 2394 } 2395 } 2396 } 2397 2398 return modes; 2399 } 2400 2401 static void 2402 do_cvt_mode(struct detailed_timing *timing, void *c) 2403 { 2404 struct detailed_mode_closure *closure = c; 2405 struct detailed_non_pixel *data = &timing->data.other_data; 2406 2407 if (data->type == EDID_DETAIL_CVT_3BYTE) 2408 closure->modes += drm_cvt_modes(closure->connector, timing); 2409 } 2410 2411 static int 2412 add_cvt_modes(struct drm_connector *connector, struct edid *edid) 2413 { 2414 struct detailed_mode_closure closure = { 2415 .connector = connector, 2416 .edid = edid, 2417 }; 2418 2419 if (version_greater(edid, 1, 2)) 2420 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 2421 2422 /* XXX should also look for CVT codes in VTB blocks */ 2423 2424 return closure.modes; 2425 } 2426 2427 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); 2428 2429 static void 2430 do_detailed_mode(struct detailed_timing *timing, void *c) 2431 { 2432 struct detailed_mode_closure *closure = c; 2433 struct drm_display_mode *newmode; 2434 2435 if (timing->pixel_clock) { 2436 newmode = drm_mode_detailed(closure->connector->dev, 2437 closure->edid, timing, 2438 closure->quirks); 2439 if (!newmode) 2440 return; 2441 2442 if (closure->preferred) 2443 newmode->type |= DRM_MODE_TYPE_PREFERRED; 2444 2445 /* 2446 * Detailed modes are limited to 10kHz pixel clock resolution, 2447 * so fix up anything that looks like CEA/HDMI mode, but the clock 2448 * is just slightly off. 2449 */ 2450 fixup_detailed_cea_mode_clock(newmode); 2451 2452 drm_mode_probed_add(closure->connector, newmode); 2453 closure->modes++; 2454 closure->preferred = 0; 2455 } 2456 } 2457 2458 /* 2459 * add_detailed_modes - Add modes from detailed timings 2460 * @connector: attached connector 2461 * @edid: EDID block to scan 2462 * @quirks: quirks to apply 2463 */ 2464 static int 2465 add_detailed_modes(struct drm_connector *connector, struct edid *edid, 2466 u32 quirks) 2467 { 2468 struct detailed_mode_closure closure = { 2469 .connector = connector, 2470 .edid = edid, 2471 .preferred = 1, 2472 .quirks = quirks, 2473 }; 2474 2475 if (closure.preferred && !version_greater(edid, 1, 3)) 2476 closure.preferred = 2477 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 2478 2479 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 2480 2481 return closure.modes; 2482 } 2483 2484 #define AUDIO_BLOCK 0x01 2485 #define VIDEO_BLOCK 0x02 2486 #define VENDOR_BLOCK 0x03 2487 #define SPEAKER_BLOCK 0x04 2488 #define VIDEO_CAPABILITY_BLOCK 0x07 2489 #define EDID_BASIC_AUDIO (1 << 6) 2490 #define EDID_CEA_YCRCB444 (1 << 5) 2491 #define EDID_CEA_YCRCB422 (1 << 4) 2492 #define EDID_CEA_VCDB_QS (1 << 6) 2493 2494 /* 2495 * Search EDID for CEA extension block. 2496 */ 2497 static u8 *drm_find_edid_extension(struct edid *edid, int ext_id) 2498 { 2499 u8 *edid_ext = NULL; 2500 int i; 2501 2502 /* No EDID or EDID extensions */ 2503 if (edid == NULL || edid->extensions == 0) 2504 return NULL; 2505 2506 /* Find CEA extension */ 2507 for (i = 0; i < edid->extensions; i++) { 2508 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); 2509 if (edid_ext[0] == ext_id) 2510 break; 2511 } 2512 2513 if (i == edid->extensions) 2514 return NULL; 2515 2516 return edid_ext; 2517 } 2518 2519 static u8 *drm_find_cea_extension(struct edid *edid) 2520 { 2521 return drm_find_edid_extension(edid, CEA_EXT); 2522 } 2523 2524 static u8 *drm_find_displayid_extension(struct edid *edid) 2525 { 2526 return drm_find_edid_extension(edid, DISPLAYID_EXT); 2527 } 2528 2529 /* 2530 * Calculate the alternate clock for the CEA mode 2531 * (60Hz vs. 59.94Hz etc.) 2532 */ 2533 static unsigned int 2534 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 2535 { 2536 unsigned int clock = cea_mode->clock; 2537 2538 if (cea_mode->vrefresh % 6 != 0) 2539 return clock; 2540 2541 /* 2542 * edid_cea_modes contains the 59.94Hz 2543 * variant for 240 and 480 line modes, 2544 * and the 60Hz variant otherwise. 2545 */ 2546 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 2547 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 2548 else 2549 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 2550 2551 return clock; 2552 } 2553 2554 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 2555 unsigned int clock_tolerance) 2556 { 2557 u8 vic; 2558 2559 if (!to_match->clock) 2560 return 0; 2561 2562 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 2563 const struct drm_display_mode *cea_mode = &edid_cea_modes[vic]; 2564 unsigned int clock1, clock2; 2565 2566 /* Check both 60Hz and 59.94Hz */ 2567 clock1 = cea_mode->clock; 2568 clock2 = cea_mode_alternate_clock(cea_mode); 2569 2570 if (abs(to_match->clock - clock1) > clock_tolerance && 2571 abs(to_match->clock - clock2) > clock_tolerance) 2572 continue; 2573 2574 if (drm_mode_equal_no_clocks(to_match, cea_mode)) 2575 return vic; 2576 } 2577 2578 return 0; 2579 } 2580 2581 /** 2582 * drm_match_cea_mode - look for a CEA mode matching given mode 2583 * @to_match: display mode 2584 * 2585 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 2586 * mode. 2587 */ 2588 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 2589 { 2590 u8 vic; 2591 2592 if (!to_match->clock) 2593 return 0; 2594 2595 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 2596 const struct drm_display_mode *cea_mode = &edid_cea_modes[vic]; 2597 unsigned int clock1, clock2; 2598 2599 /* Check both 60Hz and 59.94Hz */ 2600 clock1 = cea_mode->clock; 2601 clock2 = cea_mode_alternate_clock(cea_mode); 2602 2603 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 2604 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 2605 drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode)) 2606 return vic; 2607 } 2608 return 0; 2609 } 2610 EXPORT_SYMBOL(drm_match_cea_mode); 2611 2612 static bool drm_valid_cea_vic(u8 vic) 2613 { 2614 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes); 2615 } 2616 2617 /** 2618 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to 2619 * the input VIC from the CEA mode list 2620 * @video_code: ID given to each of the CEA modes 2621 * 2622 * Returns picture aspect ratio 2623 */ 2624 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 2625 { 2626 return edid_cea_modes[video_code].picture_aspect_ratio; 2627 } 2628 EXPORT_SYMBOL(drm_get_cea_aspect_ratio); 2629 2630 /* 2631 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 2632 * specific block). 2633 * 2634 * It's almost like cea_mode_alternate_clock(), we just need to add an 2635 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this 2636 * one. 2637 */ 2638 static unsigned int 2639 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 2640 { 2641 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) 2642 return hdmi_mode->clock; 2643 2644 return cea_mode_alternate_clock(hdmi_mode); 2645 } 2646 2647 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 2648 unsigned int clock_tolerance) 2649 { 2650 u8 vic; 2651 2652 if (!to_match->clock) 2653 return 0; 2654 2655 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 2656 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 2657 unsigned int clock1, clock2; 2658 2659 /* Make sure to also match alternate clocks */ 2660 clock1 = hdmi_mode->clock; 2661 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 2662 2663 if (abs(to_match->clock - clock1) > clock_tolerance && 2664 abs(to_match->clock - clock2) > clock_tolerance) 2665 continue; 2666 2667 if (drm_mode_equal_no_clocks(to_match, hdmi_mode)) 2668 return vic; 2669 } 2670 2671 return 0; 2672 } 2673 2674 /* 2675 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 2676 * @to_match: display mode 2677 * 2678 * An HDMI mode is one defined in the HDMI vendor specific block. 2679 * 2680 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 2681 */ 2682 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 2683 { 2684 u8 vic; 2685 2686 if (!to_match->clock) 2687 return 0; 2688 2689 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 2690 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 2691 unsigned int clock1, clock2; 2692 2693 /* Make sure to also match alternate clocks */ 2694 clock1 = hdmi_mode->clock; 2695 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 2696 2697 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 2698 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 2699 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode)) 2700 return vic; 2701 } 2702 return 0; 2703 } 2704 2705 static bool drm_valid_hdmi_vic(u8 vic) 2706 { 2707 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 2708 } 2709 2710 static int 2711 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) 2712 { 2713 struct drm_device *dev = connector->dev; 2714 struct drm_display_mode *mode, *tmp; 2715 LIST_HEAD(list); 2716 int modes = 0; 2717 2718 /* Don't add CEA modes if the CEA extension block is missing */ 2719 if (!drm_find_cea_extension(edid)) 2720 return 0; 2721 2722 /* 2723 * Go through all probed modes and create a new mode 2724 * with the alternate clock for certain CEA modes. 2725 */ 2726 list_for_each_entry(mode, &connector->probed_modes, head) { 2727 const struct drm_display_mode *cea_mode = NULL; 2728 struct drm_display_mode *newmode; 2729 u8 vic = drm_match_cea_mode(mode); 2730 unsigned int clock1, clock2; 2731 2732 if (drm_valid_cea_vic(vic)) { 2733 cea_mode = &edid_cea_modes[vic]; 2734 clock2 = cea_mode_alternate_clock(cea_mode); 2735 } else { 2736 vic = drm_match_hdmi_mode(mode); 2737 if (drm_valid_hdmi_vic(vic)) { 2738 cea_mode = &edid_4k_modes[vic]; 2739 clock2 = hdmi_mode_alternate_clock(cea_mode); 2740 } 2741 } 2742 2743 if (!cea_mode) 2744 continue; 2745 2746 clock1 = cea_mode->clock; 2747 2748 if (clock1 == clock2) 2749 continue; 2750 2751 if (mode->clock != clock1 && mode->clock != clock2) 2752 continue; 2753 2754 newmode = drm_mode_duplicate(dev, cea_mode); 2755 if (!newmode) 2756 continue; 2757 2758 /* Carry over the stereo flags */ 2759 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 2760 2761 /* 2762 * The current mode could be either variant. Make 2763 * sure to pick the "other" clock for the new mode. 2764 */ 2765 if (mode->clock != clock1) 2766 newmode->clock = clock1; 2767 else 2768 newmode->clock = clock2; 2769 2770 list_add_tail(&newmode->head, &list); 2771 } 2772 2773 list_for_each_entry_safe(mode, tmp, &list, head) { 2774 list_del(&mode->head); 2775 drm_mode_probed_add(connector, mode); 2776 modes++; 2777 } 2778 2779 return modes; 2780 } 2781 2782 static struct drm_display_mode * 2783 drm_display_mode_from_vic_index(struct drm_connector *connector, 2784 const u8 *video_db, u8 video_len, 2785 u8 video_index) 2786 { 2787 struct drm_device *dev = connector->dev; 2788 struct drm_display_mode *newmode; 2789 u8 vic; 2790 2791 if (video_db == NULL || video_index >= video_len) 2792 return NULL; 2793 2794 /* CEA modes are numbered 1..127 */ 2795 vic = (video_db[video_index] & 127); 2796 if (!drm_valid_cea_vic(vic)) 2797 return NULL; 2798 2799 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]); 2800 if (!newmode) 2801 return NULL; 2802 2803 newmode->vrefresh = 0; 2804 2805 return newmode; 2806 } 2807 2808 static int 2809 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 2810 { 2811 int i, modes = 0; 2812 2813 for (i = 0; i < len; i++) { 2814 struct drm_display_mode *mode; 2815 mode = drm_display_mode_from_vic_index(connector, db, len, i); 2816 if (mode) { 2817 drm_mode_probed_add(connector, mode); 2818 modes++; 2819 } 2820 } 2821 2822 return modes; 2823 } 2824 2825 struct stereo_mandatory_mode { 2826 int width, height, vrefresh; 2827 unsigned int flags; 2828 }; 2829 2830 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 2831 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2832 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2833 { 1920, 1080, 50, 2834 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2835 { 1920, 1080, 60, 2836 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2837 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2838 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2839 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2840 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 2841 }; 2842 2843 static bool 2844 stereo_match_mandatory(const struct drm_display_mode *mode, 2845 const struct stereo_mandatory_mode *stereo_mode) 2846 { 2847 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 2848 2849 return mode->hdisplay == stereo_mode->width && 2850 mode->vdisplay == stereo_mode->height && 2851 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 2852 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 2853 } 2854 2855 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 2856 { 2857 struct drm_device *dev = connector->dev; 2858 const struct drm_display_mode *mode; 2859 struct list_head stereo_modes; 2860 int modes = 0, i; 2861 2862 INIT_LIST_HEAD(&stereo_modes); 2863 2864 list_for_each_entry(mode, &connector->probed_modes, head) { 2865 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 2866 const struct stereo_mandatory_mode *mandatory; 2867 struct drm_display_mode *new_mode; 2868 2869 if (!stereo_match_mandatory(mode, 2870 &stereo_mandatory_modes[i])) 2871 continue; 2872 2873 mandatory = &stereo_mandatory_modes[i]; 2874 new_mode = drm_mode_duplicate(dev, mode); 2875 if (!new_mode) 2876 continue; 2877 2878 new_mode->flags |= mandatory->flags; 2879 list_add_tail(&new_mode->head, &stereo_modes); 2880 modes++; 2881 } 2882 } 2883 2884 list_splice_tail(&stereo_modes, &connector->probed_modes); 2885 2886 return modes; 2887 } 2888 2889 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 2890 { 2891 struct drm_device *dev = connector->dev; 2892 struct drm_display_mode *newmode; 2893 2894 if (!drm_valid_hdmi_vic(vic)) { 2895 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 2896 return 0; 2897 } 2898 2899 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 2900 if (!newmode) 2901 return 0; 2902 2903 drm_mode_probed_add(connector, newmode); 2904 2905 return 1; 2906 } 2907 2908 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 2909 const u8 *video_db, u8 video_len, u8 video_index) 2910 { 2911 struct drm_display_mode *newmode; 2912 int modes = 0; 2913 2914 if (structure & (1 << 0)) { 2915 newmode = drm_display_mode_from_vic_index(connector, video_db, 2916 video_len, 2917 video_index); 2918 if (newmode) { 2919 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 2920 drm_mode_probed_add(connector, newmode); 2921 modes++; 2922 } 2923 } 2924 if (structure & (1 << 6)) { 2925 newmode = drm_display_mode_from_vic_index(connector, video_db, 2926 video_len, 2927 video_index); 2928 if (newmode) { 2929 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 2930 drm_mode_probed_add(connector, newmode); 2931 modes++; 2932 } 2933 } 2934 if (structure & (1 << 8)) { 2935 newmode = drm_display_mode_from_vic_index(connector, video_db, 2936 video_len, 2937 video_index); 2938 if (newmode) { 2939 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 2940 drm_mode_probed_add(connector, newmode); 2941 modes++; 2942 } 2943 } 2944 2945 return modes; 2946 } 2947 2948 /* 2949 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 2950 * @connector: connector corresponding to the HDMI sink 2951 * @db: start of the CEA vendor specific block 2952 * @len: length of the CEA block payload, ie. one can access up to db[len] 2953 * 2954 * Parses the HDMI VSDB looking for modes to add to @connector. This function 2955 * also adds the stereo 3d modes when applicable. 2956 */ 2957 static int 2958 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 2959 const u8 *video_db, u8 video_len) 2960 { 2961 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 2962 u8 vic_len, hdmi_3d_len = 0; 2963 u16 mask; 2964 u16 structure_all; 2965 2966 if (len < 8) 2967 goto out; 2968 2969 /* no HDMI_Video_Present */ 2970 if (!(db[8] & (1 << 5))) 2971 goto out; 2972 2973 /* Latency_Fields_Present */ 2974 if (db[8] & (1 << 7)) 2975 offset += 2; 2976 2977 /* I_Latency_Fields_Present */ 2978 if (db[8] & (1 << 6)) 2979 offset += 2; 2980 2981 /* the declared length is not long enough for the 2 first bytes 2982 * of additional video format capabilities */ 2983 if (len < (8 + offset + 2)) 2984 goto out; 2985 2986 /* 3D_Present */ 2987 offset++; 2988 if (db[8 + offset] & (1 << 7)) { 2989 modes += add_hdmi_mandatory_stereo_modes(connector); 2990 2991 /* 3D_Multi_present */ 2992 multi_present = (db[8 + offset] & 0x60) >> 5; 2993 } 2994 2995 offset++; 2996 vic_len = db[8 + offset] >> 5; 2997 hdmi_3d_len = db[8 + offset] & 0x1f; 2998 2999 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 3000 u8 vic; 3001 3002 vic = db[9 + offset + i]; 3003 modes += add_hdmi_mode(connector, vic); 3004 } 3005 offset += 1 + vic_len; 3006 3007 if (multi_present == 1) 3008 multi_len = 2; 3009 else if (multi_present == 2) 3010 multi_len = 4; 3011 else 3012 multi_len = 0; 3013 3014 if (len < (8 + offset + hdmi_3d_len - 1)) 3015 goto out; 3016 3017 if (hdmi_3d_len < multi_len) 3018 goto out; 3019 3020 if (multi_present == 1 || multi_present == 2) { 3021 /* 3D_Structure_ALL */ 3022 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 3023 3024 /* check if 3D_MASK is present */ 3025 if (multi_present == 2) 3026 mask = (db[10 + offset] << 8) | db[11 + offset]; 3027 else 3028 mask = 0xffff; 3029 3030 for (i = 0; i < 16; i++) { 3031 if (mask & (1 << i)) 3032 modes += add_3d_struct_modes(connector, 3033 structure_all, 3034 video_db, 3035 video_len, i); 3036 } 3037 } 3038 3039 offset += multi_len; 3040 3041 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 3042 int vic_index; 3043 struct drm_display_mode *newmode = NULL; 3044 unsigned int newflag = 0; 3045 bool detail_present; 3046 3047 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 3048 3049 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 3050 break; 3051 3052 /* 2D_VIC_order_X */ 3053 vic_index = db[8 + offset + i] >> 4; 3054 3055 /* 3D_Structure_X */ 3056 switch (db[8 + offset + i] & 0x0f) { 3057 case 0: 3058 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 3059 break; 3060 case 6: 3061 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3062 break; 3063 case 8: 3064 /* 3D_Detail_X */ 3065 if ((db[9 + offset + i] >> 4) == 1) 3066 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3067 break; 3068 } 3069 3070 if (newflag != 0) { 3071 newmode = drm_display_mode_from_vic_index(connector, 3072 video_db, 3073 video_len, 3074 vic_index); 3075 3076 if (newmode) { 3077 newmode->flags |= newflag; 3078 drm_mode_probed_add(connector, newmode); 3079 modes++; 3080 } 3081 } 3082 3083 if (detail_present) 3084 i++; 3085 } 3086 3087 out: 3088 return modes; 3089 } 3090 3091 static int 3092 cea_db_payload_len(const u8 *db) 3093 { 3094 return db[0] & 0x1f; 3095 } 3096 3097 static int 3098 cea_db_tag(const u8 *db) 3099 { 3100 return db[0] >> 5; 3101 } 3102 3103 static int 3104 cea_revision(const u8 *cea) 3105 { 3106 return cea[1]; 3107 } 3108 3109 static int 3110 cea_db_offsets(const u8 *cea, int *start, int *end) 3111 { 3112 /* Data block offset in CEA extension block */ 3113 *start = 4; 3114 *end = cea[2]; 3115 if (*end == 0) 3116 *end = 127; 3117 if (*end < 4 || *end > 127) 3118 return -ERANGE; 3119 return 0; 3120 } 3121 3122 static bool cea_db_is_hdmi_vsdb(const u8 *db) 3123 { 3124 int hdmi_id; 3125 3126 if (cea_db_tag(db) != VENDOR_BLOCK) 3127 return false; 3128 3129 if (cea_db_payload_len(db) < 5) 3130 return false; 3131 3132 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 3133 3134 return hdmi_id == HDMI_IEEE_OUI; 3135 } 3136 3137 #define for_each_cea_db(cea, i, start, end) \ 3138 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 3139 3140 static int 3141 add_cea_modes(struct drm_connector *connector, struct edid *edid) 3142 { 3143 const u8 *cea = drm_find_cea_extension(edid); 3144 const u8 *db, *hdmi = NULL, *video = NULL; 3145 u8 dbl, hdmi_len, video_len = 0; 3146 int modes = 0; 3147 3148 if (cea && cea_revision(cea) >= 3) { 3149 int i, start, end; 3150 3151 if (cea_db_offsets(cea, &start, &end)) 3152 return 0; 3153 3154 for_each_cea_db(cea, i, start, end) { 3155 db = &cea[i]; 3156 dbl = cea_db_payload_len(db); 3157 3158 if (cea_db_tag(db) == VIDEO_BLOCK) { 3159 video = db + 1; 3160 video_len = dbl; 3161 modes += do_cea_modes(connector, video, dbl); 3162 } 3163 else if (cea_db_is_hdmi_vsdb(db)) { 3164 hdmi = db; 3165 hdmi_len = dbl; 3166 } 3167 } 3168 } 3169 3170 /* 3171 * We parse the HDMI VSDB after having added the cea modes as we will 3172 * be patching their flags when the sink supports stereo 3D. 3173 */ 3174 if (hdmi) 3175 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, 3176 video_len); 3177 3178 return modes; 3179 } 3180 3181 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 3182 { 3183 const struct drm_display_mode *cea_mode; 3184 int clock1, clock2, clock; 3185 u8 vic; 3186 const char *type; 3187 3188 /* 3189 * allow 5kHz clock difference either way to account for 3190 * the 10kHz clock resolution limit of detailed timings. 3191 */ 3192 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 3193 if (drm_valid_cea_vic(vic)) { 3194 type = "CEA"; 3195 cea_mode = &edid_cea_modes[vic]; 3196 clock1 = cea_mode->clock; 3197 clock2 = cea_mode_alternate_clock(cea_mode); 3198 } else { 3199 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 3200 if (drm_valid_hdmi_vic(vic)) { 3201 type = "HDMI"; 3202 cea_mode = &edid_4k_modes[vic]; 3203 clock1 = cea_mode->clock; 3204 clock2 = hdmi_mode_alternate_clock(cea_mode); 3205 } else { 3206 return; 3207 } 3208 } 3209 3210 /* pick whichever is closest */ 3211 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 3212 clock = clock1; 3213 else 3214 clock = clock2; 3215 3216 if (mode->clock == clock) 3217 return; 3218 3219 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 3220 type, vic, mode->clock, clock); 3221 mode->clock = clock; 3222 } 3223 3224 static void 3225 parse_hdmi_vsdb(struct drm_connector *connector, const u8 *db) 3226 { 3227 u8 len = cea_db_payload_len(db); 3228 3229 if (len >= 6) { 3230 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */ 3231 connector->dvi_dual = db[6] & 1; 3232 } 3233 if (len >= 7) 3234 connector->max_tmds_clock = db[7] * 5; 3235 if (len >= 8) { 3236 connector->latency_present[0] = db[8] >> 7; 3237 connector->latency_present[1] = (db[8] >> 6) & 1; 3238 } 3239 if (len >= 9) 3240 connector->video_latency[0] = db[9]; 3241 if (len >= 10) 3242 connector->audio_latency[0] = db[10]; 3243 if (len >= 11) 3244 connector->video_latency[1] = db[11]; 3245 if (len >= 12) 3246 connector->audio_latency[1] = db[12]; 3247 3248 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 3249 "max TMDS clock %d, " 3250 "latency present %d %d, " 3251 "video latency %d %d, " 3252 "audio latency %d %d\n", 3253 connector->dvi_dual, 3254 connector->max_tmds_clock, 3255 (int) connector->latency_present[0], 3256 (int) connector->latency_present[1], 3257 connector->video_latency[0], 3258 connector->video_latency[1], 3259 connector->audio_latency[0], 3260 connector->audio_latency[1]); 3261 } 3262 3263 static void 3264 monitor_name(struct detailed_timing *t, void *data) 3265 { 3266 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME) 3267 *(u8 **)data = t->data.other_data.data.str.str; 3268 } 3269 3270 /** 3271 * drm_edid_to_eld - build ELD from EDID 3272 * @connector: connector corresponding to the HDMI/DP sink 3273 * @edid: EDID to parse 3274 * 3275 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 3276 * Conn_Type, HDCP and Port_ID ELD fields are left for the graphics driver to 3277 * fill in. 3278 */ 3279 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 3280 { 3281 uint8_t *eld = connector->eld; 3282 u8 *cea; 3283 u8 *name; 3284 u8 *db; 3285 int sad_count = 0; 3286 int mnl; 3287 int dbl; 3288 3289 memset(eld, 0, sizeof(connector->eld)); 3290 3291 cea = drm_find_cea_extension(edid); 3292 if (!cea) { 3293 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 3294 return; 3295 } 3296 3297 name = NULL; 3298 drm_for_each_detailed_block((u8 *)edid, monitor_name, &name); 3299 for (mnl = 0; name && mnl < 13; mnl++) { 3300 if (name[mnl] == 0x0a) 3301 break; 3302 eld[20 + mnl] = name[mnl]; 3303 } 3304 eld[4] = (cea[1] << 5) | mnl; 3305 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20); 3306 3307 eld[0] = 2 << 3; /* ELD version: 2 */ 3308 3309 eld[16] = edid->mfg_id[0]; 3310 eld[17] = edid->mfg_id[1]; 3311 eld[18] = edid->prod_code[0]; 3312 eld[19] = edid->prod_code[1]; 3313 3314 if (cea_revision(cea) >= 3) { 3315 int i, start, end; 3316 3317 if (cea_db_offsets(cea, &start, &end)) { 3318 start = 0; 3319 end = 0; 3320 } 3321 3322 for_each_cea_db(cea, i, start, end) { 3323 db = &cea[i]; 3324 dbl = cea_db_payload_len(db); 3325 3326 switch (cea_db_tag(db)) { 3327 case AUDIO_BLOCK: 3328 /* Audio Data Block, contains SADs */ 3329 sad_count = dbl / 3; 3330 if (dbl >= 1) 3331 memcpy(eld + 20 + mnl, &db[1], dbl); 3332 break; 3333 case SPEAKER_BLOCK: 3334 /* Speaker Allocation Data Block */ 3335 if (dbl >= 1) 3336 eld[7] = db[1]; 3337 break; 3338 case VENDOR_BLOCK: 3339 /* HDMI Vendor-Specific Data Block */ 3340 if (cea_db_is_hdmi_vsdb(db)) 3341 parse_hdmi_vsdb(connector, db); 3342 break; 3343 default: 3344 break; 3345 } 3346 } 3347 } 3348 eld[5] |= sad_count << 4; 3349 3350 eld[DRM_ELD_BASELINE_ELD_LEN] = 3351 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 3352 3353 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", 3354 drm_eld_size(eld), sad_count); 3355 } 3356 EXPORT_SYMBOL(drm_edid_to_eld); 3357 3358 /** 3359 * drm_edid_to_sad - extracts SADs from EDID 3360 * @edid: EDID to parse 3361 * @sads: pointer that will be set to the extracted SADs 3362 * 3363 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 3364 * 3365 * Note: The returned pointer needs to be freed using kfree(). 3366 * 3367 * Return: The number of found SADs or negative number on error. 3368 */ 3369 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) 3370 { 3371 int count = 0; 3372 int i, start, end, dbl; 3373 u8 *cea; 3374 3375 cea = drm_find_cea_extension(edid); 3376 if (!cea) { 3377 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 3378 return -ENOENT; 3379 } 3380 3381 if (cea_revision(cea) < 3) { 3382 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 3383 return -ENOTSUPP; 3384 } 3385 3386 if (cea_db_offsets(cea, &start, &end)) { 3387 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 3388 return -EPROTO; 3389 } 3390 3391 for_each_cea_db(cea, i, start, end) { 3392 u8 *db = &cea[i]; 3393 3394 if (cea_db_tag(db) == AUDIO_BLOCK) { 3395 int j; 3396 dbl = cea_db_payload_len(db); 3397 3398 count = dbl / 3; /* SAD is 3B */ 3399 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 3400 if (!*sads) 3401 return -ENOMEM; 3402 for (j = 0; j < count; j++) { 3403 u8 *sad = &db[1 + j * 3]; 3404 3405 (*sads)[j].format = (sad[0] & 0x78) >> 3; 3406 (*sads)[j].channels = sad[0] & 0x7; 3407 (*sads)[j].freq = sad[1] & 0x7F; 3408 (*sads)[j].byte2 = sad[2]; 3409 } 3410 break; 3411 } 3412 } 3413 3414 return count; 3415 } 3416 EXPORT_SYMBOL(drm_edid_to_sad); 3417 3418 /** 3419 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 3420 * @edid: EDID to parse 3421 * @sadb: pointer to the speaker block 3422 * 3423 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 3424 * 3425 * Note: The returned pointer needs to be freed using kfree(). 3426 * 3427 * Return: The number of found Speaker Allocation Blocks or negative number on 3428 * error. 3429 */ 3430 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) 3431 { 3432 int count = 0; 3433 int i, start, end, dbl; 3434 const u8 *cea; 3435 3436 cea = drm_find_cea_extension(edid); 3437 if (!cea) { 3438 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 3439 return -ENOENT; 3440 } 3441 3442 if (cea_revision(cea) < 3) { 3443 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 3444 return -ENOTSUPP; 3445 } 3446 3447 if (cea_db_offsets(cea, &start, &end)) { 3448 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 3449 return -EPROTO; 3450 } 3451 3452 for_each_cea_db(cea, i, start, end) { 3453 const u8 *db = &cea[i]; 3454 3455 if (cea_db_tag(db) == SPEAKER_BLOCK) { 3456 dbl = cea_db_payload_len(db); 3457 3458 /* Speaker Allocation Data Block */ 3459 if (dbl == 3) { 3460 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); 3461 if (!*sadb) 3462 return -ENOMEM; 3463 count = dbl; 3464 break; 3465 } 3466 } 3467 } 3468 3469 return count; 3470 } 3471 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 3472 3473 /** 3474 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 3475 * @connector: connector associated with the HDMI/DP sink 3476 * @mode: the display mode 3477 * 3478 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 3479 * the sink doesn't support audio or video. 3480 */ 3481 int drm_av_sync_delay(struct drm_connector *connector, 3482 const struct drm_display_mode *mode) 3483 { 3484 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 3485 int a, v; 3486 3487 if (!connector->latency_present[0]) 3488 return 0; 3489 if (!connector->latency_present[1]) 3490 i = 0; 3491 3492 a = connector->audio_latency[i]; 3493 v = connector->video_latency[i]; 3494 3495 /* 3496 * HDMI/DP sink doesn't support audio or video? 3497 */ 3498 if (a == 255 || v == 255) 3499 return 0; 3500 3501 /* 3502 * Convert raw EDID values to millisecond. 3503 * Treat unknown latency as 0ms. 3504 */ 3505 if (a) 3506 a = min(2 * (a - 1), 500); 3507 if (v) 3508 v = min(2 * (v - 1), 500); 3509 3510 return max(v - a, 0); 3511 } 3512 EXPORT_SYMBOL(drm_av_sync_delay); 3513 3514 /** 3515 * drm_select_eld - select one ELD from multiple HDMI/DP sinks 3516 * @encoder: the encoder just changed display mode 3517 * 3518 * It's possible for one encoder to be associated with multiple HDMI/DP sinks. 3519 * The policy is now hard coded to simply use the first HDMI/DP sink's ELD. 3520 * 3521 * Return: The connector associated with the first HDMI/DP sink that has ELD 3522 * attached to it. 3523 */ 3524 struct drm_connector *drm_select_eld(struct drm_encoder *encoder) 3525 { 3526 struct drm_connector *connector; 3527 struct drm_device *dev = encoder->dev; 3528 3529 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); 3530 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); 3531 3532 drm_for_each_connector(connector, dev) 3533 if (connector->encoder == encoder && connector->eld[0]) 3534 return connector; 3535 3536 return NULL; 3537 } 3538 EXPORT_SYMBOL(drm_select_eld); 3539 3540 /** 3541 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 3542 * @edid: monitor EDID information 3543 * 3544 * Parse the CEA extension according to CEA-861-B. 3545 * 3546 * Return: True if the monitor is HDMI, false if not or unknown. 3547 */ 3548 bool drm_detect_hdmi_monitor(struct edid *edid) 3549 { 3550 u8 *edid_ext; 3551 int i; 3552 int start_offset, end_offset; 3553 3554 edid_ext = drm_find_cea_extension(edid); 3555 if (!edid_ext) 3556 return false; 3557 3558 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3559 return false; 3560 3561 /* 3562 * Because HDMI identifier is in Vendor Specific Block, 3563 * search it from all data blocks of CEA extension. 3564 */ 3565 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3566 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 3567 return true; 3568 } 3569 3570 return false; 3571 } 3572 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 3573 3574 /** 3575 * drm_detect_monitor_audio - check monitor audio capability 3576 * @edid: EDID block to scan 3577 * 3578 * Monitor should have CEA extension block. 3579 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 3580 * audio' only. If there is any audio extension block and supported 3581 * audio format, assume at least 'basic audio' support, even if 'basic 3582 * audio' is not defined in EDID. 3583 * 3584 * Return: True if the monitor supports audio, false otherwise. 3585 */ 3586 bool drm_detect_monitor_audio(struct edid *edid) 3587 { 3588 u8 *edid_ext; 3589 int i, j; 3590 bool has_audio = false; 3591 int start_offset, end_offset; 3592 3593 edid_ext = drm_find_cea_extension(edid); 3594 if (!edid_ext) 3595 goto end; 3596 3597 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 3598 3599 if (has_audio) { 3600 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 3601 goto end; 3602 } 3603 3604 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3605 goto end; 3606 3607 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3608 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 3609 has_audio = true; 3610 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 3611 DRM_DEBUG_KMS("CEA audio format %d\n", 3612 (edid_ext[i + j] >> 3) & 0xf); 3613 goto end; 3614 } 3615 } 3616 end: 3617 return has_audio; 3618 } 3619 EXPORT_SYMBOL(drm_detect_monitor_audio); 3620 3621 /** 3622 * drm_rgb_quant_range_selectable - is RGB quantization range selectable? 3623 * @edid: EDID block to scan 3624 * 3625 * Check whether the monitor reports the RGB quantization range selection 3626 * as supported. The AVI infoframe can then be used to inform the monitor 3627 * which quantization range (full or limited) is used. 3628 * 3629 * Return: True if the RGB quantization range is selectable, false otherwise. 3630 */ 3631 bool drm_rgb_quant_range_selectable(struct edid *edid) 3632 { 3633 u8 *edid_ext; 3634 int i, start, end; 3635 3636 edid_ext = drm_find_cea_extension(edid); 3637 if (!edid_ext) 3638 return false; 3639 3640 if (cea_db_offsets(edid_ext, &start, &end)) 3641 return false; 3642 3643 for_each_cea_db(edid_ext, i, start, end) { 3644 if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK && 3645 cea_db_payload_len(&edid_ext[i]) == 2) { 3646 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]); 3647 return edid_ext[i + 2] & EDID_CEA_VCDB_QS; 3648 } 3649 } 3650 3651 return false; 3652 } 3653 EXPORT_SYMBOL(drm_rgb_quant_range_selectable); 3654 3655 /** 3656 * drm_assign_hdmi_deep_color_info - detect whether monitor supports 3657 * hdmi deep color modes and update drm_display_info if so. 3658 * @edid: monitor EDID information 3659 * @info: Updated with maximum supported deep color bpc and color format 3660 * if deep color supported. 3661 * @connector: DRM connector, used only for debug output 3662 * 3663 * Parse the CEA extension according to CEA-861-B. 3664 * Return true if HDMI deep color supported, false if not or unknown. 3665 */ 3666 static bool drm_assign_hdmi_deep_color_info(struct edid *edid, 3667 struct drm_display_info *info, 3668 struct drm_connector *connector) 3669 { 3670 u8 *edid_ext, *hdmi; 3671 int i; 3672 int start_offset, end_offset; 3673 unsigned int dc_bpc = 0; 3674 3675 edid_ext = drm_find_cea_extension(edid); 3676 if (!edid_ext) 3677 return false; 3678 3679 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3680 return false; 3681 3682 /* 3683 * Because HDMI identifier is in Vendor Specific Block, 3684 * search it from all data blocks of CEA extension. 3685 */ 3686 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3687 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) { 3688 /* HDMI supports at least 8 bpc */ 3689 info->bpc = 8; 3690 3691 hdmi = &edid_ext[i]; 3692 if (cea_db_payload_len(hdmi) < 6) 3693 return false; 3694 3695 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 3696 dc_bpc = 10; 3697 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 3698 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 3699 connector->name); 3700 } 3701 3702 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 3703 dc_bpc = 12; 3704 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 3705 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 3706 connector->name); 3707 } 3708 3709 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 3710 dc_bpc = 16; 3711 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 3712 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 3713 connector->name); 3714 } 3715 3716 if (dc_bpc > 0) { 3717 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 3718 connector->name, dc_bpc); 3719 info->bpc = dc_bpc; 3720 3721 /* 3722 * Deep color support mandates RGB444 support for all video 3723 * modes and forbids YCRCB422 support for all video modes per 3724 * HDMI 1.3 spec. 3725 */ 3726 info->color_formats = DRM_COLOR_FORMAT_RGB444; 3727 3728 /* YCRCB444 is optional according to spec. */ 3729 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 3730 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3731 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 3732 connector->name); 3733 } 3734 3735 /* 3736 * Spec says that if any deep color mode is supported at all, 3737 * then deep color 36 bit must be supported. 3738 */ 3739 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 3740 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 3741 connector->name); 3742 } 3743 3744 return true; 3745 } 3746 else { 3747 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 3748 connector->name); 3749 } 3750 } 3751 } 3752 3753 return false; 3754 } 3755 3756 /** 3757 * drm_add_display_info - pull display info out if present 3758 * @edid: EDID data 3759 * @info: display info (attached to connector) 3760 * @connector: connector whose edid is used to build display info 3761 * 3762 * Grab any available display info and stuff it into the drm_display_info 3763 * structure that's part of the connector. Useful for tracking bpp and 3764 * color spaces. 3765 */ 3766 static void drm_add_display_info(struct edid *edid, 3767 struct drm_display_info *info, 3768 struct drm_connector *connector) 3769 { 3770 u8 *edid_ext; 3771 3772 info->width_mm = edid->width_cm * 10; 3773 info->height_mm = edid->height_cm * 10; 3774 3775 /* driver figures it out in this case */ 3776 info->bpc = 0; 3777 info->color_formats = 0; 3778 3779 if (edid->revision < 3) 3780 return; 3781 3782 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 3783 return; 3784 3785 /* Get data from CEA blocks if present */ 3786 edid_ext = drm_find_cea_extension(edid); 3787 if (edid_ext) { 3788 info->cea_rev = edid_ext[1]; 3789 3790 /* The existence of a CEA block should imply RGB support */ 3791 info->color_formats = DRM_COLOR_FORMAT_RGB444; 3792 if (edid_ext[3] & EDID_CEA_YCRCB444) 3793 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3794 if (edid_ext[3] & EDID_CEA_YCRCB422) 3795 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3796 } 3797 3798 /* HDMI deep color modes supported? Assign to info, if so */ 3799 drm_assign_hdmi_deep_color_info(edid, info, connector); 3800 3801 /* Only defined for 1.4 with digital displays */ 3802 if (edid->revision < 4) 3803 return; 3804 3805 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 3806 case DRM_EDID_DIGITAL_DEPTH_6: 3807 info->bpc = 6; 3808 break; 3809 case DRM_EDID_DIGITAL_DEPTH_8: 3810 info->bpc = 8; 3811 break; 3812 case DRM_EDID_DIGITAL_DEPTH_10: 3813 info->bpc = 10; 3814 break; 3815 case DRM_EDID_DIGITAL_DEPTH_12: 3816 info->bpc = 12; 3817 break; 3818 case DRM_EDID_DIGITAL_DEPTH_14: 3819 info->bpc = 14; 3820 break; 3821 case DRM_EDID_DIGITAL_DEPTH_16: 3822 info->bpc = 16; 3823 break; 3824 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 3825 default: 3826 info->bpc = 0; 3827 break; 3828 } 3829 3830 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 3831 connector->name, info->bpc); 3832 3833 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 3834 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 3835 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3836 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 3837 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3838 } 3839 3840 /** 3841 * drm_add_edid_modes - add modes from EDID data, if available 3842 * @connector: connector we're probing 3843 * @edid: EDID data 3844 * 3845 * Add the specified modes to the connector's mode list. 3846 * 3847 * Return: The number of modes added or 0 if we couldn't find any. 3848 */ 3849 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 3850 { 3851 int num_modes = 0; 3852 u32 quirks; 3853 3854 if (edid == NULL) { 3855 return 0; 3856 } 3857 if (!drm_edid_is_valid(edid)) { 3858 dev_warn(connector->dev->dev, "%s: EDID invalid.\n", 3859 connector->name); 3860 return 0; 3861 } 3862 3863 quirks = edid_get_quirks(edid); 3864 3865 /* 3866 * EDID spec says modes should be preferred in this order: 3867 * - preferred detailed mode 3868 * - other detailed modes from base block 3869 * - detailed modes from extension blocks 3870 * - CVT 3-byte code modes 3871 * - standard timing codes 3872 * - established timing codes 3873 * - modes inferred from GTF or CVT range information 3874 * 3875 * We get this pretty much right. 3876 * 3877 * XXX order for additional mode types in extension blocks? 3878 */ 3879 num_modes += add_detailed_modes(connector, edid, quirks); 3880 num_modes += add_cvt_modes(connector, edid); 3881 num_modes += add_standard_modes(connector, edid); 3882 num_modes += add_established_modes(connector, edid); 3883 num_modes += add_cea_modes(connector, edid); 3884 num_modes += add_alternate_cea_modes(connector, edid); 3885 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 3886 num_modes += add_inferred_modes(connector, edid); 3887 3888 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 3889 edid_fixup_preferred(connector, quirks); 3890 3891 drm_add_display_info(edid, &connector->display_info, connector); 3892 3893 if (quirks & EDID_QUIRK_FORCE_8BPC) 3894 connector->display_info.bpc = 8; 3895 3896 if (quirks & EDID_QUIRK_FORCE_12BPC) 3897 connector->display_info.bpc = 12; 3898 3899 return num_modes; 3900 } 3901 EXPORT_SYMBOL(drm_add_edid_modes); 3902 3903 /** 3904 * drm_add_modes_noedid - add modes for the connectors without EDID 3905 * @connector: connector we're probing 3906 * @hdisplay: the horizontal display limit 3907 * @vdisplay: the vertical display limit 3908 * 3909 * Add the specified modes to the connector's mode list. Only when the 3910 * hdisplay/vdisplay is not beyond the given limit, it will be added. 3911 * 3912 * Return: The number of modes added or 0 if we couldn't find any. 3913 */ 3914 int drm_add_modes_noedid(struct drm_connector *connector, 3915 int hdisplay, int vdisplay) 3916 { 3917 int i, count, num_modes = 0; 3918 struct drm_display_mode *mode; 3919 struct drm_device *dev = connector->dev; 3920 3921 count = ARRAY_SIZE(drm_dmt_modes); 3922 if (hdisplay < 0) 3923 hdisplay = 0; 3924 if (vdisplay < 0) 3925 vdisplay = 0; 3926 3927 for (i = 0; i < count; i++) { 3928 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 3929 if (hdisplay && vdisplay) { 3930 /* 3931 * Only when two are valid, they will be used to check 3932 * whether the mode should be added to the mode list of 3933 * the connector. 3934 */ 3935 if (ptr->hdisplay > hdisplay || 3936 ptr->vdisplay > vdisplay) 3937 continue; 3938 } 3939 if (drm_mode_vrefresh(ptr) > 61) 3940 continue; 3941 mode = drm_mode_duplicate(dev, ptr); 3942 if (mode) { 3943 drm_mode_probed_add(connector, mode); 3944 num_modes++; 3945 } 3946 } 3947 return num_modes; 3948 } 3949 EXPORT_SYMBOL(drm_add_modes_noedid); 3950 3951 /** 3952 * drm_set_preferred_mode - Sets the preferred mode of a connector 3953 * @connector: connector whose mode list should be processed 3954 * @hpref: horizontal resolution of preferred mode 3955 * @vpref: vertical resolution of preferred mode 3956 * 3957 * Marks a mode as preferred if it matches the resolution specified by @hpref 3958 * and @vpref. 3959 */ 3960 void drm_set_preferred_mode(struct drm_connector *connector, 3961 int hpref, int vpref) 3962 { 3963 struct drm_display_mode *mode; 3964 3965 list_for_each_entry(mode, &connector->probed_modes, head) { 3966 if (mode->hdisplay == hpref && 3967 mode->vdisplay == vpref) 3968 mode->type |= DRM_MODE_TYPE_PREFERRED; 3969 } 3970 } 3971 EXPORT_SYMBOL(drm_set_preferred_mode); 3972 3973 /** 3974 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 3975 * data from a DRM display mode 3976 * @frame: HDMI AVI infoframe 3977 * @mode: DRM display mode 3978 * 3979 * Return: 0 on success or a negative error code on failure. 3980 */ 3981 int 3982 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 3983 const struct drm_display_mode *mode) 3984 { 3985 int err; 3986 3987 if (!frame || !mode) 3988 return -EINVAL; 3989 3990 err = hdmi_avi_infoframe_init(frame); 3991 if (err < 0) 3992 return err; 3993 3994 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 3995 frame->pixel_repeat = 1; 3996 3997 frame->video_code = drm_match_cea_mode(mode); 3998 3999 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 4000 4001 /* 4002 * Populate picture aspect ratio from either 4003 * user input (if specified) or from the CEA mode list. 4004 */ 4005 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 || 4006 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9) 4007 frame->picture_aspect = mode->picture_aspect_ratio; 4008 else if (frame->video_code > 0) 4009 frame->picture_aspect = drm_get_cea_aspect_ratio( 4010 frame->video_code); 4011 4012 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 4013 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 4014 4015 return 0; 4016 } 4017 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 4018 4019 static enum hdmi_3d_structure 4020 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 4021 { 4022 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 4023 4024 switch (layout) { 4025 case DRM_MODE_FLAG_3D_FRAME_PACKING: 4026 return HDMI_3D_STRUCTURE_FRAME_PACKING; 4027 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 4028 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 4029 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 4030 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 4031 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 4032 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 4033 case DRM_MODE_FLAG_3D_L_DEPTH: 4034 return HDMI_3D_STRUCTURE_L_DEPTH; 4035 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 4036 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 4037 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 4038 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 4039 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 4040 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 4041 default: 4042 return HDMI_3D_STRUCTURE_INVALID; 4043 } 4044 } 4045 4046 /** 4047 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 4048 * data from a DRM display mode 4049 * @frame: HDMI vendor infoframe 4050 * @mode: DRM display mode 4051 * 4052 * Note that there's is a need to send HDMI vendor infoframes only when using a 4053 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 4054 * function will return -EINVAL, error that can be safely ignored. 4055 * 4056 * Return: 0 on success or a negative error code on failure. 4057 */ 4058 int 4059 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 4060 const struct drm_display_mode *mode) 4061 { 4062 int err; 4063 u32 s3d_flags; 4064 u8 vic; 4065 4066 if (!frame || !mode) 4067 return -EINVAL; 4068 4069 vic = drm_match_hdmi_mode(mode); 4070 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; 4071 4072 if (!vic && !s3d_flags) 4073 return -EINVAL; 4074 4075 if (vic && s3d_flags) 4076 return -EINVAL; 4077 4078 err = hdmi_vendor_infoframe_init(frame); 4079 if (err < 0) 4080 return err; 4081 4082 if (vic) 4083 frame->vic = vic; 4084 else 4085 frame->s3d_struct = s3d_structure_from_display_mode(mode); 4086 4087 return 0; 4088 } 4089 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 4090 4091 static int drm_parse_display_id(struct drm_connector *connector, 4092 u8 *displayid, int length, 4093 bool is_edid_extension) 4094 { 4095 /* if this is an EDID extension the first byte will be 0x70 */ 4096 int idx = 0; 4097 struct displayid_hdr *base; 4098 struct displayid_block *block; 4099 u8 csum = 0; 4100 int i; 4101 4102 if (is_edid_extension) 4103 idx = 1; 4104 4105 base = (struct displayid_hdr *)&displayid[idx]; 4106 4107 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n", 4108 base->rev, base->bytes, base->prod_id, base->ext_count); 4109 4110 if (base->bytes + 5 > length - idx) 4111 return -EINVAL; 4112 4113 for (i = idx; i <= base->bytes + 5; i++) { 4114 csum += displayid[i]; 4115 } 4116 if (csum) { 4117 DRM_ERROR("DisplayID checksum invalid, remainder is %d\n", csum); 4118 return -EINVAL; 4119 } 4120 4121 block = (struct displayid_block *)&displayid[idx + 4]; 4122 DRM_DEBUG_KMS("block id %d, rev %d, len %d\n", 4123 block->tag, block->rev, block->num_bytes); 4124 4125 switch (block->tag) { 4126 case DATA_BLOCK_TILED_DISPLAY: { 4127 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 4128 4129 u16 w, h; 4130 u8 tile_v_loc, tile_h_loc; 4131 u8 num_v_tile, num_h_tile; 4132 struct drm_tile_group *tg; 4133 4134 w = tile->tile_size[0] | tile->tile_size[1] << 8; 4135 h = tile->tile_size[2] | tile->tile_size[3] << 8; 4136 4137 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 4138 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 4139 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 4140 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 4141 4142 connector->has_tile = true; 4143 if (tile->tile_cap & 0x80) 4144 connector->tile_is_single_monitor = true; 4145 4146 connector->num_h_tile = num_h_tile + 1; 4147 connector->num_v_tile = num_v_tile + 1; 4148 connector->tile_h_loc = tile_h_loc; 4149 connector->tile_v_loc = tile_v_loc; 4150 connector->tile_h_size = w + 1; 4151 connector->tile_v_size = h + 1; 4152 4153 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); 4154 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); 4155 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", 4156 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); 4157 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 4158 4159 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 4160 if (!tg) { 4161 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 4162 } 4163 if (!tg) 4164 return -ENOMEM; 4165 4166 if (connector->tile_group != tg) { 4167 /* if we haven't got a pointer, 4168 take the reference, drop ref to old tile group */ 4169 if (connector->tile_group) { 4170 drm_mode_put_tile_group(connector->dev, connector->tile_group); 4171 } 4172 connector->tile_group = tg; 4173 } else 4174 /* if same tile group, then release the ref we just took. */ 4175 drm_mode_put_tile_group(connector->dev, tg); 4176 } 4177 break; 4178 default: 4179 printk("unknown displayid tag %d\n", block->tag); 4180 break; 4181 } 4182 return 0; 4183 } 4184 4185 static void drm_get_displayid(struct drm_connector *connector, 4186 struct edid *edid) 4187 { 4188 void *displayid = NULL; 4189 int ret; 4190 connector->has_tile = false; 4191 displayid = drm_find_displayid_extension(edid); 4192 if (!displayid) { 4193 /* drop reference to any tile group we had */ 4194 goto out_drop_ref; 4195 } 4196 4197 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true); 4198 if (ret < 0) 4199 goto out_drop_ref; 4200 if (!connector->has_tile) 4201 goto out_drop_ref; 4202 return; 4203 out_drop_ref: 4204 if (connector->tile_group) { 4205 drm_mode_put_tile_group(connector->dev, connector->tile_group); 4206 connector->tile_group = NULL; 4207 } 4208 return; 4209 } 4210