1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 31 #include <linux/bitfield.h> 32 #include <linux/hdmi.h> 33 #include <linux/i2c.h> 34 #include <linux/kernel.h> 35 #include <linux/module.h> 36 #include <linux/pci.h> 37 #include <linux/slab.h> 38 #include <linux/vga_switcheroo.h> 39 40 #include <drm/drm_displayid.h> 41 #include <drm/drm_drv.h> 42 #include <drm/drm_edid.h> 43 #include <drm/drm_encoder.h> 44 #include <drm/drm_print.h> 45 46 #include "drm_crtc_internal.h" 47 48 static int oui(u8 first, u8 second, u8 third) 49 { 50 return (first << 16) | (second << 8) | third; 51 } 52 53 #define EDID_EST_TIMINGS 16 54 #define EDID_STD_TIMINGS 8 55 #define EDID_DETAILED_TIMINGS 4 56 57 /* 58 * EDID blocks out in the wild have a variety of bugs, try to collect 59 * them here (note that userspace may work around broken monitors first, 60 * but fixes should make their way here so that the kernel "just works" 61 * on as many displays as possible). 62 */ 63 64 /* First detailed mode wrong, use largest 60Hz mode */ 65 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 66 /* Reported 135MHz pixel clock is too high, needs adjustment */ 67 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 68 /* Prefer the largest mode at 75 Hz */ 69 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 70 /* Detail timing is in cm not mm */ 71 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 72 /* Detailed timing descriptors have bogus size values, so just take the 73 * maximum size and use that. 74 */ 75 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 76 /* use +hsync +vsync for detailed mode */ 77 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 78 /* Force reduced-blanking timings for detailed modes */ 79 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 80 /* Force 8bpc */ 81 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 82 /* Force 12bpc */ 83 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 84 /* Force 6bpc */ 85 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 86 /* Force 10bpc */ 87 #define EDID_QUIRK_FORCE_10BPC (1 << 11) 88 /* Non desktop display (i.e. HMD) */ 89 #define EDID_QUIRK_NON_DESKTOP (1 << 12) 90 /* Cap the DSC target bitrate to 15bpp */ 91 #define EDID_QUIRK_CAP_DSC_15BPP (1 << 13) 92 93 #define MICROSOFT_IEEE_OUI 0xca125c 94 95 struct detailed_mode_closure { 96 struct drm_connector *connector; 97 const struct drm_edid *drm_edid; 98 bool preferred; 99 int modes; 100 }; 101 102 #define LEVEL_DMT 0 103 #define LEVEL_GTF 1 104 #define LEVEL_GTF2 2 105 #define LEVEL_CVT 3 106 107 #define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \ 108 { \ 109 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \ 110 product_id), \ 111 .quirks = _quirks \ 112 } 113 114 static const struct edid_quirk { 115 u32 panel_id; 116 u32 quirks; 117 } edid_quirk_list[] = { 118 /* Acer AL1706 */ 119 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60), 120 /* Acer F51 */ 121 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60), 122 123 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 124 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC), 125 126 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */ 127 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC), 128 129 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 130 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC), 131 132 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ 133 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC), 134 135 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ 136 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC), 137 138 /* Belinea 10 15 55 */ 139 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60), 140 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60), 141 142 /* Envision Peripherals, Inc. EN-7100e */ 143 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH), 144 /* Envision EN2028 */ 145 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60), 146 147 /* Funai Electronics PM36B */ 148 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 | 149 EDID_QUIRK_DETAILED_IN_CM), 150 151 /* LG 27GP950 */ 152 EDID_QUIRK('G', 'S', 'M', 0x5bbf, EDID_QUIRK_CAP_DSC_15BPP), 153 154 /* LG 27GN950 */ 155 EDID_QUIRK('G', 'S', 'M', 0x5b9a, EDID_QUIRK_CAP_DSC_15BPP), 156 157 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 158 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC), 159 160 /* LG Philips LCD LP154W01-A5 */ 161 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE), 162 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE), 163 164 /* Samsung SyncMaster 205BW. Note: irony */ 165 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP), 166 /* Samsung SyncMaster 22[5-6]BW */ 167 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60), 168 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60), 169 170 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 171 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC), 172 173 /* ViewSonic VA2026w */ 174 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING), 175 176 /* Medion MD 30217 PG */ 177 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75), 178 179 /* Lenovo G50 */ 180 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC), 181 182 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 183 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC), 184 185 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 186 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC), 187 188 /* Valve Index Headset */ 189 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP), 190 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP), 191 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP), 192 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP), 193 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP), 194 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP), 195 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP), 196 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP), 197 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP), 198 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP), 199 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP), 200 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP), 201 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP), 202 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP), 203 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP), 204 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP), 205 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP), 206 207 /* HTC Vive and Vive Pro VR Headsets */ 208 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP), 209 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP), 210 211 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */ 212 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP), 213 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP), 214 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP), 215 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP), 216 217 /* Windows Mixed Reality Headsets */ 218 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP), 219 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP), 220 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP), 221 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP), 222 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP), 223 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP), 224 225 /* Sony PlayStation VR Headset */ 226 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP), 227 228 /* Sensics VR Headsets */ 229 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP), 230 231 /* OSVR HDK and HDK2 VR Headsets */ 232 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP), 233 EDID_QUIRK('A', 'U', 'O', 0x1111, EDID_QUIRK_NON_DESKTOP), 234 }; 235 236 /* 237 * Autogenerated from the DMT spec. 238 * This table is copied from xfree86/modes/xf86EdidModes.c. 239 */ 240 static const struct drm_display_mode drm_dmt_modes[] = { 241 /* 0x01 - 640x350@85Hz */ 242 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 243 736, 832, 0, 350, 382, 385, 445, 0, 244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 245 /* 0x02 - 640x400@85Hz */ 246 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 247 736, 832, 0, 400, 401, 404, 445, 0, 248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 249 /* 0x03 - 720x400@85Hz */ 250 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 251 828, 936, 0, 400, 401, 404, 446, 0, 252 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 253 /* 0x04 - 640x480@60Hz */ 254 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 255 752, 800, 0, 480, 490, 492, 525, 0, 256 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 257 /* 0x05 - 640x480@72Hz */ 258 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 259 704, 832, 0, 480, 489, 492, 520, 0, 260 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 261 /* 0x06 - 640x480@75Hz */ 262 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 263 720, 840, 0, 480, 481, 484, 500, 0, 264 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 265 /* 0x07 - 640x480@85Hz */ 266 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 267 752, 832, 0, 480, 481, 484, 509, 0, 268 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 269 /* 0x08 - 800x600@56Hz */ 270 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 271 896, 1024, 0, 600, 601, 603, 625, 0, 272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 273 /* 0x09 - 800x600@60Hz */ 274 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 275 968, 1056, 0, 600, 601, 605, 628, 0, 276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 277 /* 0x0a - 800x600@72Hz */ 278 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 279 976, 1040, 0, 600, 637, 643, 666, 0, 280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 281 /* 0x0b - 800x600@75Hz */ 282 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 283 896, 1056, 0, 600, 601, 604, 625, 0, 284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 285 /* 0x0c - 800x600@85Hz */ 286 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 287 896, 1048, 0, 600, 601, 604, 631, 0, 288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 289 /* 0x0d - 800x600@120Hz RB */ 290 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 291 880, 960, 0, 600, 603, 607, 636, 0, 292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 293 /* 0x0e - 848x480@60Hz */ 294 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 295 976, 1088, 0, 480, 486, 494, 517, 0, 296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 297 /* 0x0f - 1024x768@43Hz, interlace */ 298 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 299 1208, 1264, 0, 768, 768, 776, 817, 0, 300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 301 DRM_MODE_FLAG_INTERLACE) }, 302 /* 0x10 - 1024x768@60Hz */ 303 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 304 1184, 1344, 0, 768, 771, 777, 806, 0, 305 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 306 /* 0x11 - 1024x768@70Hz */ 307 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 308 1184, 1328, 0, 768, 771, 777, 806, 0, 309 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 310 /* 0x12 - 1024x768@75Hz */ 311 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 312 1136, 1312, 0, 768, 769, 772, 800, 0, 313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 314 /* 0x13 - 1024x768@85Hz */ 315 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 316 1168, 1376, 0, 768, 769, 772, 808, 0, 317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 318 /* 0x14 - 1024x768@120Hz RB */ 319 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 320 1104, 1184, 0, 768, 771, 775, 813, 0, 321 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 322 /* 0x15 - 1152x864@75Hz */ 323 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 324 1344, 1600, 0, 864, 865, 868, 900, 0, 325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 326 /* 0x55 - 1280x720@60Hz */ 327 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 328 1430, 1650, 0, 720, 725, 730, 750, 0, 329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 330 /* 0x16 - 1280x768@60Hz RB */ 331 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 332 1360, 1440, 0, 768, 771, 778, 790, 0, 333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 334 /* 0x17 - 1280x768@60Hz */ 335 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 336 1472, 1664, 0, 768, 771, 778, 798, 0, 337 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 338 /* 0x18 - 1280x768@75Hz */ 339 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 340 1488, 1696, 0, 768, 771, 778, 805, 0, 341 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 342 /* 0x19 - 1280x768@85Hz */ 343 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 344 1496, 1712, 0, 768, 771, 778, 809, 0, 345 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 346 /* 0x1a - 1280x768@120Hz RB */ 347 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 348 1360, 1440, 0, 768, 771, 778, 813, 0, 349 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 350 /* 0x1b - 1280x800@60Hz RB */ 351 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 352 1360, 1440, 0, 800, 803, 809, 823, 0, 353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 354 /* 0x1c - 1280x800@60Hz */ 355 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 356 1480, 1680, 0, 800, 803, 809, 831, 0, 357 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 358 /* 0x1d - 1280x800@75Hz */ 359 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 360 1488, 1696, 0, 800, 803, 809, 838, 0, 361 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 362 /* 0x1e - 1280x800@85Hz */ 363 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 364 1496, 1712, 0, 800, 803, 809, 843, 0, 365 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 366 /* 0x1f - 1280x800@120Hz RB */ 367 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 368 1360, 1440, 0, 800, 803, 809, 847, 0, 369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 370 /* 0x20 - 1280x960@60Hz */ 371 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 372 1488, 1800, 0, 960, 961, 964, 1000, 0, 373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 374 /* 0x21 - 1280x960@85Hz */ 375 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 376 1504, 1728, 0, 960, 961, 964, 1011, 0, 377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 378 /* 0x22 - 1280x960@120Hz RB */ 379 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 380 1360, 1440, 0, 960, 963, 967, 1017, 0, 381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 382 /* 0x23 - 1280x1024@60Hz */ 383 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 384 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 386 /* 0x24 - 1280x1024@75Hz */ 387 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 388 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 390 /* 0x25 - 1280x1024@85Hz */ 391 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 392 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 394 /* 0x26 - 1280x1024@120Hz RB */ 395 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 396 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 398 /* 0x27 - 1360x768@60Hz */ 399 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 400 1536, 1792, 0, 768, 771, 777, 795, 0, 401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 402 /* 0x28 - 1360x768@120Hz RB */ 403 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 404 1440, 1520, 0, 768, 771, 776, 813, 0, 405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 406 /* 0x51 - 1366x768@60Hz */ 407 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 408 1579, 1792, 0, 768, 771, 774, 798, 0, 409 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 410 /* 0x56 - 1366x768@60Hz */ 411 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 412 1436, 1500, 0, 768, 769, 772, 800, 0, 413 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 414 /* 0x29 - 1400x1050@60Hz RB */ 415 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 416 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 418 /* 0x2a - 1400x1050@60Hz */ 419 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 420 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 421 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 422 /* 0x2b - 1400x1050@75Hz */ 423 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 424 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 425 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 426 /* 0x2c - 1400x1050@85Hz */ 427 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 428 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 429 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 430 /* 0x2d - 1400x1050@120Hz RB */ 431 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 432 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 433 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 434 /* 0x2e - 1440x900@60Hz RB */ 435 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 436 1520, 1600, 0, 900, 903, 909, 926, 0, 437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 438 /* 0x2f - 1440x900@60Hz */ 439 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 440 1672, 1904, 0, 900, 903, 909, 934, 0, 441 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 442 /* 0x30 - 1440x900@75Hz */ 443 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 444 1688, 1936, 0, 900, 903, 909, 942, 0, 445 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 446 /* 0x31 - 1440x900@85Hz */ 447 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 448 1696, 1952, 0, 900, 903, 909, 948, 0, 449 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 450 /* 0x32 - 1440x900@120Hz RB */ 451 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 452 1520, 1600, 0, 900, 903, 909, 953, 0, 453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 454 /* 0x53 - 1600x900@60Hz */ 455 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 456 1704, 1800, 0, 900, 901, 904, 1000, 0, 457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 458 /* 0x33 - 1600x1200@60Hz */ 459 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 460 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 462 /* 0x34 - 1600x1200@65Hz */ 463 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 464 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 466 /* 0x35 - 1600x1200@70Hz */ 467 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 468 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 470 /* 0x36 - 1600x1200@75Hz */ 471 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 472 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 474 /* 0x37 - 1600x1200@85Hz */ 475 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 476 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 478 /* 0x38 - 1600x1200@120Hz RB */ 479 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 480 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 482 /* 0x39 - 1680x1050@60Hz RB */ 483 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 484 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 486 /* 0x3a - 1680x1050@60Hz */ 487 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 488 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 490 /* 0x3b - 1680x1050@75Hz */ 491 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 492 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 493 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 494 /* 0x3c - 1680x1050@85Hz */ 495 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 496 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 497 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 498 /* 0x3d - 1680x1050@120Hz RB */ 499 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 500 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 501 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 502 /* 0x3e - 1792x1344@60Hz */ 503 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 504 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 505 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 506 /* 0x3f - 1792x1344@75Hz */ 507 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 508 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 509 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 510 /* 0x40 - 1792x1344@120Hz RB */ 511 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 512 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 513 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 514 /* 0x41 - 1856x1392@60Hz */ 515 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 516 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 517 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 518 /* 0x42 - 1856x1392@75Hz */ 519 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 520 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 521 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 522 /* 0x43 - 1856x1392@120Hz RB */ 523 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 524 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 525 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 526 /* 0x52 - 1920x1080@60Hz */ 527 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 528 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 529 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 530 /* 0x44 - 1920x1200@60Hz RB */ 531 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 532 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 533 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 534 /* 0x45 - 1920x1200@60Hz */ 535 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 536 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 538 /* 0x46 - 1920x1200@75Hz */ 539 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 540 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 541 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 542 /* 0x47 - 1920x1200@85Hz */ 543 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 544 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 545 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 546 /* 0x48 - 1920x1200@120Hz RB */ 547 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 548 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 549 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 550 /* 0x49 - 1920x1440@60Hz */ 551 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 552 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 553 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 554 /* 0x4a - 1920x1440@75Hz */ 555 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 556 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 557 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 558 /* 0x4b - 1920x1440@120Hz RB */ 559 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 560 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 561 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 562 /* 0x54 - 2048x1152@60Hz */ 563 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 564 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 566 /* 0x4c - 2560x1600@60Hz RB */ 567 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 568 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 570 /* 0x4d - 2560x1600@60Hz */ 571 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 572 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 573 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 574 /* 0x4e - 2560x1600@75Hz */ 575 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 576 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 577 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 578 /* 0x4f - 2560x1600@85Hz */ 579 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 580 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 581 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 582 /* 0x50 - 2560x1600@120Hz RB */ 583 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 584 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 585 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 586 /* 0x57 - 4096x2160@60Hz RB */ 587 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 588 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 589 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 590 /* 0x58 - 4096x2160@59.94Hz RB */ 591 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 592 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 593 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 594 }; 595 596 /* 597 * These more or less come from the DMT spec. The 720x400 modes are 598 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 599 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 600 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 601 * mode. 602 * 603 * The DMT modes have been fact-checked; the rest are mild guesses. 604 */ 605 static const struct drm_display_mode edid_est_modes[] = { 606 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 607 968, 1056, 0, 600, 601, 605, 628, 0, 608 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 609 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 610 896, 1024, 0, 600, 601, 603, 625, 0, 611 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 612 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 613 720, 840, 0, 480, 481, 484, 500, 0, 614 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 615 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 616 704, 832, 0, 480, 489, 492, 520, 0, 617 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 618 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 619 768, 864, 0, 480, 483, 486, 525, 0, 620 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 621 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 622 752, 800, 0, 480, 490, 492, 525, 0, 623 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 624 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 625 846, 900, 0, 400, 421, 423, 449, 0, 626 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 627 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 628 846, 900, 0, 400, 412, 414, 449, 0, 629 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 630 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 631 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 632 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 633 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 634 1136, 1312, 0, 768, 769, 772, 800, 0, 635 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 636 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 637 1184, 1328, 0, 768, 771, 777, 806, 0, 638 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 639 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 640 1184, 1344, 0, 768, 771, 777, 806, 0, 641 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 642 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 643 1208, 1264, 0, 768, 768, 776, 817, 0, 644 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 645 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 646 928, 1152, 0, 624, 625, 628, 667, 0, 647 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 648 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 649 896, 1056, 0, 600, 601, 604, 625, 0, 650 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 651 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 652 976, 1040, 0, 600, 637, 643, 666, 0, 653 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 654 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 655 1344, 1600, 0, 864, 865, 868, 900, 0, 656 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 657 }; 658 659 struct minimode { 660 short w; 661 short h; 662 short r; 663 short rb; 664 }; 665 666 static const struct minimode est3_modes[] = { 667 /* byte 6 */ 668 { 640, 350, 85, 0 }, 669 { 640, 400, 85, 0 }, 670 { 720, 400, 85, 0 }, 671 { 640, 480, 85, 0 }, 672 { 848, 480, 60, 0 }, 673 { 800, 600, 85, 0 }, 674 { 1024, 768, 85, 0 }, 675 { 1152, 864, 75, 0 }, 676 /* byte 7 */ 677 { 1280, 768, 60, 1 }, 678 { 1280, 768, 60, 0 }, 679 { 1280, 768, 75, 0 }, 680 { 1280, 768, 85, 0 }, 681 { 1280, 960, 60, 0 }, 682 { 1280, 960, 85, 0 }, 683 { 1280, 1024, 60, 0 }, 684 { 1280, 1024, 85, 0 }, 685 /* byte 8 */ 686 { 1360, 768, 60, 0 }, 687 { 1440, 900, 60, 1 }, 688 { 1440, 900, 60, 0 }, 689 { 1440, 900, 75, 0 }, 690 { 1440, 900, 85, 0 }, 691 { 1400, 1050, 60, 1 }, 692 { 1400, 1050, 60, 0 }, 693 { 1400, 1050, 75, 0 }, 694 /* byte 9 */ 695 { 1400, 1050, 85, 0 }, 696 { 1680, 1050, 60, 1 }, 697 { 1680, 1050, 60, 0 }, 698 { 1680, 1050, 75, 0 }, 699 { 1680, 1050, 85, 0 }, 700 { 1600, 1200, 60, 0 }, 701 { 1600, 1200, 65, 0 }, 702 { 1600, 1200, 70, 0 }, 703 /* byte 10 */ 704 { 1600, 1200, 75, 0 }, 705 { 1600, 1200, 85, 0 }, 706 { 1792, 1344, 60, 0 }, 707 { 1792, 1344, 75, 0 }, 708 { 1856, 1392, 60, 0 }, 709 { 1856, 1392, 75, 0 }, 710 { 1920, 1200, 60, 1 }, 711 { 1920, 1200, 60, 0 }, 712 /* byte 11 */ 713 { 1920, 1200, 75, 0 }, 714 { 1920, 1200, 85, 0 }, 715 { 1920, 1440, 60, 0 }, 716 { 1920, 1440, 75, 0 }, 717 }; 718 719 static const struct minimode extra_modes[] = { 720 { 1024, 576, 60, 0 }, 721 { 1366, 768, 60, 0 }, 722 { 1600, 900, 60, 0 }, 723 { 1680, 945, 60, 0 }, 724 { 1920, 1080, 60, 0 }, 725 { 2048, 1152, 60, 0 }, 726 { 2048, 1536, 60, 0 }, 727 }; 728 729 /* 730 * From CEA/CTA-861 spec. 731 * 732 * Do not access directly, instead always use cea_mode_for_vic(). 733 */ 734 static const struct drm_display_mode edid_cea_modes_1[] = { 735 /* 1 - 640x480@60Hz 4:3 */ 736 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 737 752, 800, 0, 480, 490, 492, 525, 0, 738 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 739 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 740 /* 2 - 720x480@60Hz 4:3 */ 741 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 742 798, 858, 0, 480, 489, 495, 525, 0, 743 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 744 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 745 /* 3 - 720x480@60Hz 16:9 */ 746 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 747 798, 858, 0, 480, 489, 495, 525, 0, 748 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 749 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 750 /* 4 - 1280x720@60Hz 16:9 */ 751 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 752 1430, 1650, 0, 720, 725, 730, 750, 0, 753 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 754 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 755 /* 5 - 1920x1080i@60Hz 16:9 */ 756 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 757 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 758 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 759 DRM_MODE_FLAG_INTERLACE), 760 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 761 /* 6 - 720(1440)x480i@60Hz 4:3 */ 762 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 763 801, 858, 0, 480, 488, 494, 525, 0, 764 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 765 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 766 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 767 /* 7 - 720(1440)x480i@60Hz 16:9 */ 768 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 769 801, 858, 0, 480, 488, 494, 525, 0, 770 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 771 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 772 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 773 /* 8 - 720(1440)x240@60Hz 4:3 */ 774 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 775 801, 858, 0, 240, 244, 247, 262, 0, 776 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 777 DRM_MODE_FLAG_DBLCLK), 778 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 779 /* 9 - 720(1440)x240@60Hz 16:9 */ 780 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 781 801, 858, 0, 240, 244, 247, 262, 0, 782 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 783 DRM_MODE_FLAG_DBLCLK), 784 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 785 /* 10 - 2880x480i@60Hz 4:3 */ 786 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 787 3204, 3432, 0, 480, 488, 494, 525, 0, 788 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 789 DRM_MODE_FLAG_INTERLACE), 790 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 791 /* 11 - 2880x480i@60Hz 16:9 */ 792 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 793 3204, 3432, 0, 480, 488, 494, 525, 0, 794 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 795 DRM_MODE_FLAG_INTERLACE), 796 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 797 /* 12 - 2880x240@60Hz 4:3 */ 798 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 799 3204, 3432, 0, 240, 244, 247, 262, 0, 800 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 801 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 802 /* 13 - 2880x240@60Hz 16:9 */ 803 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 804 3204, 3432, 0, 240, 244, 247, 262, 0, 805 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 806 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 807 /* 14 - 1440x480@60Hz 4:3 */ 808 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 809 1596, 1716, 0, 480, 489, 495, 525, 0, 810 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 811 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 812 /* 15 - 1440x480@60Hz 16:9 */ 813 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 814 1596, 1716, 0, 480, 489, 495, 525, 0, 815 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 816 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 817 /* 16 - 1920x1080@60Hz 16:9 */ 818 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 819 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 820 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 821 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 822 /* 17 - 720x576@50Hz 4:3 */ 823 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 824 796, 864, 0, 576, 581, 586, 625, 0, 825 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 826 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 827 /* 18 - 720x576@50Hz 16:9 */ 828 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 829 796, 864, 0, 576, 581, 586, 625, 0, 830 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 831 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 832 /* 19 - 1280x720@50Hz 16:9 */ 833 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 834 1760, 1980, 0, 720, 725, 730, 750, 0, 835 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 836 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 837 /* 20 - 1920x1080i@50Hz 16:9 */ 838 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 839 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 840 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 841 DRM_MODE_FLAG_INTERLACE), 842 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 843 /* 21 - 720(1440)x576i@50Hz 4:3 */ 844 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 845 795, 864, 0, 576, 580, 586, 625, 0, 846 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 847 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 848 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 849 /* 22 - 720(1440)x576i@50Hz 16:9 */ 850 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 851 795, 864, 0, 576, 580, 586, 625, 0, 852 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 853 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 854 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 855 /* 23 - 720(1440)x288@50Hz 4:3 */ 856 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 857 795, 864, 0, 288, 290, 293, 312, 0, 858 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 859 DRM_MODE_FLAG_DBLCLK), 860 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 861 /* 24 - 720(1440)x288@50Hz 16:9 */ 862 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 863 795, 864, 0, 288, 290, 293, 312, 0, 864 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 865 DRM_MODE_FLAG_DBLCLK), 866 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 867 /* 25 - 2880x576i@50Hz 4:3 */ 868 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 869 3180, 3456, 0, 576, 580, 586, 625, 0, 870 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 871 DRM_MODE_FLAG_INTERLACE), 872 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 873 /* 26 - 2880x576i@50Hz 16:9 */ 874 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 875 3180, 3456, 0, 576, 580, 586, 625, 0, 876 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 877 DRM_MODE_FLAG_INTERLACE), 878 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 879 /* 27 - 2880x288@50Hz 4:3 */ 880 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 881 3180, 3456, 0, 288, 290, 293, 312, 0, 882 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 883 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 884 /* 28 - 2880x288@50Hz 16:9 */ 885 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 886 3180, 3456, 0, 288, 290, 293, 312, 0, 887 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 888 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 889 /* 29 - 1440x576@50Hz 4:3 */ 890 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 891 1592, 1728, 0, 576, 581, 586, 625, 0, 892 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 893 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 894 /* 30 - 1440x576@50Hz 16:9 */ 895 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 896 1592, 1728, 0, 576, 581, 586, 625, 0, 897 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 898 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 899 /* 31 - 1920x1080@50Hz 16:9 */ 900 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 901 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 902 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 903 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 904 /* 32 - 1920x1080@24Hz 16:9 */ 905 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 906 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 907 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 908 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 909 /* 33 - 1920x1080@25Hz 16:9 */ 910 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 911 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 912 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 913 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 914 /* 34 - 1920x1080@30Hz 16:9 */ 915 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 916 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 917 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 918 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 919 /* 35 - 2880x480@60Hz 4:3 */ 920 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 921 3192, 3432, 0, 480, 489, 495, 525, 0, 922 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 923 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 924 /* 36 - 2880x480@60Hz 16:9 */ 925 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 926 3192, 3432, 0, 480, 489, 495, 525, 0, 927 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 928 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 929 /* 37 - 2880x576@50Hz 4:3 */ 930 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 931 3184, 3456, 0, 576, 581, 586, 625, 0, 932 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 933 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 934 /* 38 - 2880x576@50Hz 16:9 */ 935 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 936 3184, 3456, 0, 576, 581, 586, 625, 0, 937 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 938 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 939 /* 39 - 1920x1080i@50Hz 16:9 */ 940 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 941 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 942 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 943 DRM_MODE_FLAG_INTERLACE), 944 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 945 /* 40 - 1920x1080i@100Hz 16:9 */ 946 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 947 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 948 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 949 DRM_MODE_FLAG_INTERLACE), 950 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 951 /* 41 - 1280x720@100Hz 16:9 */ 952 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 953 1760, 1980, 0, 720, 725, 730, 750, 0, 954 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 955 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 956 /* 42 - 720x576@100Hz 4:3 */ 957 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 958 796, 864, 0, 576, 581, 586, 625, 0, 959 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 960 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 961 /* 43 - 720x576@100Hz 16:9 */ 962 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 963 796, 864, 0, 576, 581, 586, 625, 0, 964 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 965 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 966 /* 44 - 720(1440)x576i@100Hz 4:3 */ 967 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 968 795, 864, 0, 576, 580, 586, 625, 0, 969 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 970 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 971 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 972 /* 45 - 720(1440)x576i@100Hz 16:9 */ 973 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 974 795, 864, 0, 576, 580, 586, 625, 0, 975 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 976 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 977 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 978 /* 46 - 1920x1080i@120Hz 16:9 */ 979 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 980 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 981 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 982 DRM_MODE_FLAG_INTERLACE), 983 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 984 /* 47 - 1280x720@120Hz 16:9 */ 985 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 986 1430, 1650, 0, 720, 725, 730, 750, 0, 987 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 988 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 989 /* 48 - 720x480@120Hz 4:3 */ 990 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 991 798, 858, 0, 480, 489, 495, 525, 0, 992 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 993 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 994 /* 49 - 720x480@120Hz 16:9 */ 995 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 996 798, 858, 0, 480, 489, 495, 525, 0, 997 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 998 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 999 /* 50 - 720(1440)x480i@120Hz 4:3 */ 1000 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 1001 801, 858, 0, 480, 488, 494, 525, 0, 1002 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1003 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1004 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1005 /* 51 - 720(1440)x480i@120Hz 16:9 */ 1006 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 1007 801, 858, 0, 480, 488, 494, 525, 0, 1008 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1009 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1010 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1011 /* 52 - 720x576@200Hz 4:3 */ 1012 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1013 796, 864, 0, 576, 581, 586, 625, 0, 1014 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1015 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1016 /* 53 - 720x576@200Hz 16:9 */ 1017 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1018 796, 864, 0, 576, 581, 586, 625, 0, 1019 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1020 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1021 /* 54 - 720(1440)x576i@200Hz 4:3 */ 1022 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1023 795, 864, 0, 576, 580, 586, 625, 0, 1024 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1025 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1026 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1027 /* 55 - 720(1440)x576i@200Hz 16:9 */ 1028 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1029 795, 864, 0, 576, 580, 586, 625, 0, 1030 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1031 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1032 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1033 /* 56 - 720x480@240Hz 4:3 */ 1034 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1035 798, 858, 0, 480, 489, 495, 525, 0, 1036 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1037 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1038 /* 57 - 720x480@240Hz 16:9 */ 1039 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1040 798, 858, 0, 480, 489, 495, 525, 0, 1041 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1042 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1043 /* 58 - 720(1440)x480i@240Hz 4:3 */ 1044 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1045 801, 858, 0, 480, 488, 494, 525, 0, 1046 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1047 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1048 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1049 /* 59 - 720(1440)x480i@240Hz 16:9 */ 1050 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1051 801, 858, 0, 480, 488, 494, 525, 0, 1052 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1053 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1054 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1055 /* 60 - 1280x720@24Hz 16:9 */ 1056 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1057 3080, 3300, 0, 720, 725, 730, 750, 0, 1058 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1059 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1060 /* 61 - 1280x720@25Hz 16:9 */ 1061 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1062 3740, 3960, 0, 720, 725, 730, 750, 0, 1063 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1064 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1065 /* 62 - 1280x720@30Hz 16:9 */ 1066 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1067 3080, 3300, 0, 720, 725, 730, 750, 0, 1068 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1069 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1070 /* 63 - 1920x1080@120Hz 16:9 */ 1071 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1072 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1073 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1074 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1075 /* 64 - 1920x1080@100Hz 16:9 */ 1076 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1077 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1078 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1079 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1080 /* 65 - 1280x720@24Hz 64:27 */ 1081 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1082 3080, 3300, 0, 720, 725, 730, 750, 0, 1083 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1084 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1085 /* 66 - 1280x720@25Hz 64:27 */ 1086 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1087 3740, 3960, 0, 720, 725, 730, 750, 0, 1088 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1089 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1090 /* 67 - 1280x720@30Hz 64:27 */ 1091 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1092 3080, 3300, 0, 720, 725, 730, 750, 0, 1093 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1094 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1095 /* 68 - 1280x720@50Hz 64:27 */ 1096 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1097 1760, 1980, 0, 720, 725, 730, 750, 0, 1098 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1099 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1100 /* 69 - 1280x720@60Hz 64:27 */ 1101 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1102 1430, 1650, 0, 720, 725, 730, 750, 0, 1103 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1104 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1105 /* 70 - 1280x720@100Hz 64:27 */ 1106 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1107 1760, 1980, 0, 720, 725, 730, 750, 0, 1108 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1109 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1110 /* 71 - 1280x720@120Hz 64:27 */ 1111 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1112 1430, 1650, 0, 720, 725, 730, 750, 0, 1113 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1114 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1115 /* 72 - 1920x1080@24Hz 64:27 */ 1116 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1117 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1118 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1119 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1120 /* 73 - 1920x1080@25Hz 64:27 */ 1121 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1122 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1123 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1124 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1125 /* 74 - 1920x1080@30Hz 64:27 */ 1126 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1127 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1128 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1129 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1130 /* 75 - 1920x1080@50Hz 64:27 */ 1131 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1132 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1133 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1134 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1135 /* 76 - 1920x1080@60Hz 64:27 */ 1136 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1137 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1138 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1139 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1140 /* 77 - 1920x1080@100Hz 64:27 */ 1141 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1142 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1143 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1144 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1145 /* 78 - 1920x1080@120Hz 64:27 */ 1146 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1147 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1148 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1149 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1150 /* 79 - 1680x720@24Hz 64:27 */ 1151 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 1152 3080, 3300, 0, 720, 725, 730, 750, 0, 1153 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1154 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1155 /* 80 - 1680x720@25Hz 64:27 */ 1156 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 1157 2948, 3168, 0, 720, 725, 730, 750, 0, 1158 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1159 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1160 /* 81 - 1680x720@30Hz 64:27 */ 1161 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 1162 2420, 2640, 0, 720, 725, 730, 750, 0, 1163 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1164 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1165 /* 82 - 1680x720@50Hz 64:27 */ 1166 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1167 1980, 2200, 0, 720, 725, 730, 750, 0, 1168 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1169 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1170 /* 83 - 1680x720@60Hz 64:27 */ 1171 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1172 1980, 2200, 0, 720, 725, 730, 750, 0, 1173 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1174 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1175 /* 84 - 1680x720@100Hz 64:27 */ 1176 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1177 1780, 2000, 0, 720, 725, 730, 825, 0, 1178 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1179 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1180 /* 85 - 1680x720@120Hz 64:27 */ 1181 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1182 1780, 2000, 0, 720, 725, 730, 825, 0, 1183 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1184 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1185 /* 86 - 2560x1080@24Hz 64:27 */ 1186 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 1187 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1188 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1189 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1190 /* 87 - 2560x1080@25Hz 64:27 */ 1191 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 1192 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, 1193 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1194 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1195 /* 88 - 2560x1080@30Hz 64:27 */ 1196 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 1197 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, 1198 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1199 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1200 /* 89 - 2560x1080@50Hz 64:27 */ 1201 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 1202 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, 1203 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1204 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1205 /* 90 - 2560x1080@60Hz 64:27 */ 1206 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 1207 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, 1208 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1209 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1210 /* 91 - 2560x1080@100Hz 64:27 */ 1211 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 1212 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, 1213 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1214 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1215 /* 92 - 2560x1080@120Hz 64:27 */ 1216 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 1217 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, 1218 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1219 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1220 /* 93 - 3840x2160@24Hz 16:9 */ 1221 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1222 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1223 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1224 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1225 /* 94 - 3840x2160@25Hz 16:9 */ 1226 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1227 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1229 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1230 /* 95 - 3840x2160@30Hz 16:9 */ 1231 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1232 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1233 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1234 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1235 /* 96 - 3840x2160@50Hz 16:9 */ 1236 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1237 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1239 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1240 /* 97 - 3840x2160@60Hz 16:9 */ 1241 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1242 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1243 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1244 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1245 /* 98 - 4096x2160@24Hz 256:135 */ 1246 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1247 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1249 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1250 /* 99 - 4096x2160@25Hz 256:135 */ 1251 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1252 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1253 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1254 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1255 /* 100 - 4096x2160@30Hz 256:135 */ 1256 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1257 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1258 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1259 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1260 /* 101 - 4096x2160@50Hz 256:135 */ 1261 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1262 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1264 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1265 /* 102 - 4096x2160@60Hz 256:135 */ 1266 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1267 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1269 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1270 /* 103 - 3840x2160@24Hz 64:27 */ 1271 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1272 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1274 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1275 /* 104 - 3840x2160@25Hz 64:27 */ 1276 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1277 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1278 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1279 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1280 /* 105 - 3840x2160@30Hz 64:27 */ 1281 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1282 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1284 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1285 /* 106 - 3840x2160@50Hz 64:27 */ 1286 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1287 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1289 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1290 /* 107 - 3840x2160@60Hz 64:27 */ 1291 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1292 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1294 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1295 /* 108 - 1280x720@48Hz 16:9 */ 1296 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1297 2280, 2500, 0, 720, 725, 730, 750, 0, 1298 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1299 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1300 /* 109 - 1280x720@48Hz 64:27 */ 1301 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1302 2280, 2500, 0, 720, 725, 730, 750, 0, 1303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1304 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1305 /* 110 - 1680x720@48Hz 64:27 */ 1306 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490, 1307 2530, 2750, 0, 720, 725, 730, 750, 0, 1308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1309 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1310 /* 111 - 1920x1080@48Hz 16:9 */ 1311 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1312 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1314 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1315 /* 112 - 1920x1080@48Hz 64:27 */ 1316 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1317 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1319 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1320 /* 113 - 2560x1080@48Hz 64:27 */ 1321 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558, 1322 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1323 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1324 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1325 /* 114 - 3840x2160@48Hz 16:9 */ 1326 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1327 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1329 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1330 /* 115 - 4096x2160@48Hz 256:135 */ 1331 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116, 1332 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1334 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1335 /* 116 - 3840x2160@48Hz 64:27 */ 1336 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1337 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1338 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1339 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1340 /* 117 - 3840x2160@100Hz 16:9 */ 1341 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1342 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1343 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1344 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1345 /* 118 - 3840x2160@120Hz 16:9 */ 1346 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1347 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1348 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1349 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1350 /* 119 - 3840x2160@100Hz 64:27 */ 1351 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1352 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1354 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1355 /* 120 - 3840x2160@120Hz 64:27 */ 1356 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1357 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1358 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1359 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1360 /* 121 - 5120x2160@24Hz 64:27 */ 1361 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116, 1362 7204, 7500, 0, 2160, 2168, 2178, 2200, 0, 1363 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1364 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1365 /* 122 - 5120x2160@25Hz 64:27 */ 1366 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816, 1367 6904, 7200, 0, 2160, 2168, 2178, 2200, 0, 1368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1369 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1370 /* 123 - 5120x2160@30Hz 64:27 */ 1371 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784, 1372 5872, 6000, 0, 2160, 2168, 2178, 2200, 0, 1373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1374 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1375 /* 124 - 5120x2160@48Hz 64:27 */ 1376 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866, 1377 5954, 6250, 0, 2160, 2168, 2178, 2475, 0, 1378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1379 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1380 /* 125 - 5120x2160@50Hz 64:27 */ 1381 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216, 1382 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1383 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1384 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1385 /* 126 - 5120x2160@60Hz 64:27 */ 1386 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284, 1387 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1389 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1390 /* 127 - 5120x2160@100Hz 64:27 */ 1391 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216, 1392 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1394 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1395 }; 1396 1397 /* 1398 * From CEA/CTA-861 spec. 1399 * 1400 * Do not access directly, instead always use cea_mode_for_vic(). 1401 */ 1402 static const struct drm_display_mode edid_cea_modes_193[] = { 1403 /* 193 - 5120x2160@120Hz 64:27 */ 1404 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284, 1405 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1406 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1407 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1408 /* 194 - 7680x4320@24Hz 16:9 */ 1409 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1410 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1411 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1412 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1413 /* 195 - 7680x4320@25Hz 16:9 */ 1414 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1415 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1417 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1418 /* 196 - 7680x4320@30Hz 16:9 */ 1419 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1420 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1422 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1423 /* 197 - 7680x4320@48Hz 16:9 */ 1424 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1425 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1426 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1427 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1428 /* 198 - 7680x4320@50Hz 16:9 */ 1429 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1430 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1431 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1432 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1433 /* 199 - 7680x4320@60Hz 16:9 */ 1434 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1435 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1436 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1437 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1438 /* 200 - 7680x4320@100Hz 16:9 */ 1439 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1440 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1442 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1443 /* 201 - 7680x4320@120Hz 16:9 */ 1444 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1445 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1446 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1447 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1448 /* 202 - 7680x4320@24Hz 64:27 */ 1449 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1450 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1451 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1452 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1453 /* 203 - 7680x4320@25Hz 64:27 */ 1454 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1455 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1457 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1458 /* 204 - 7680x4320@30Hz 64:27 */ 1459 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1460 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1462 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1463 /* 205 - 7680x4320@48Hz 64:27 */ 1464 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1465 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1467 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1468 /* 206 - 7680x4320@50Hz 64:27 */ 1469 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1470 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1471 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1472 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1473 /* 207 - 7680x4320@60Hz 64:27 */ 1474 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1475 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1477 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1478 /* 208 - 7680x4320@100Hz 64:27 */ 1479 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1480 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1482 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1483 /* 209 - 7680x4320@120Hz 64:27 */ 1484 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1485 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1486 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1487 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1488 /* 210 - 10240x4320@24Hz 64:27 */ 1489 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732, 1490 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1491 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1492 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1493 /* 211 - 10240x4320@25Hz 64:27 */ 1494 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732, 1495 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1497 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1498 /* 212 - 10240x4320@30Hz 64:27 */ 1499 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528, 1500 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1501 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1502 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1503 /* 213 - 10240x4320@48Hz 64:27 */ 1504 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732, 1505 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1506 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1507 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1508 /* 214 - 10240x4320@50Hz 64:27 */ 1509 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732, 1510 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1511 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1512 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1513 /* 215 - 10240x4320@60Hz 64:27 */ 1514 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528, 1515 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1517 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1518 /* 216 - 10240x4320@100Hz 64:27 */ 1519 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432, 1520 12608, 13200, 0, 4320, 4336, 4356, 4500, 0, 1521 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1522 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1523 /* 217 - 10240x4320@120Hz 64:27 */ 1524 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528, 1525 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1526 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1527 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1528 /* 218 - 4096x2160@100Hz 256:135 */ 1529 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896, 1530 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1531 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1532 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1533 /* 219 - 4096x2160@120Hz 256:135 */ 1534 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184, 1535 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1536 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1537 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1538 }; 1539 1540 /* 1541 * HDMI 1.4 4k modes. Index using the VIC. 1542 */ 1543 static const struct drm_display_mode edid_4k_modes[] = { 1544 /* 0 - dummy, VICs start at 1 */ 1545 { }, 1546 /* 1 - 3840x2160@30Hz */ 1547 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1548 3840, 4016, 4104, 4400, 0, 1549 2160, 2168, 2178, 2250, 0, 1550 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1551 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1552 /* 2 - 3840x2160@25Hz */ 1553 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1554 3840, 4896, 4984, 5280, 0, 1555 2160, 2168, 2178, 2250, 0, 1556 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1557 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1558 /* 3 - 3840x2160@24Hz */ 1559 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1560 3840, 5116, 5204, 5500, 0, 1561 2160, 2168, 2178, 2250, 0, 1562 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1563 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1564 /* 4 - 4096x2160@24Hz (SMPTE) */ 1565 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1566 4096, 5116, 5204, 5500, 0, 1567 2160, 2168, 2178, 2250, 0, 1568 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1569 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1570 }; 1571 1572 /*** DDC fetch and block validation ***/ 1573 1574 /* 1575 * The opaque EDID type, internal to drm_edid.c. 1576 */ 1577 struct drm_edid { 1578 /* Size allocated for edid */ 1579 size_t size; 1580 const struct edid *edid; 1581 }; 1582 1583 static int edid_hfeeodb_extension_block_count(const struct edid *edid); 1584 1585 static int edid_hfeeodb_block_count(const struct edid *edid) 1586 { 1587 int eeodb = edid_hfeeodb_extension_block_count(edid); 1588 1589 return eeodb ? eeodb + 1 : 0; 1590 } 1591 1592 static int edid_extension_block_count(const struct edid *edid) 1593 { 1594 return edid->extensions; 1595 } 1596 1597 static int edid_block_count(const struct edid *edid) 1598 { 1599 return edid_extension_block_count(edid) + 1; 1600 } 1601 1602 static int edid_size_by_blocks(int num_blocks) 1603 { 1604 return num_blocks * EDID_LENGTH; 1605 } 1606 1607 static int edid_size(const struct edid *edid) 1608 { 1609 return edid_size_by_blocks(edid_block_count(edid)); 1610 } 1611 1612 static const void *edid_block_data(const struct edid *edid, int index) 1613 { 1614 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH); 1615 1616 return edid + index; 1617 } 1618 1619 static const void *edid_extension_block_data(const struct edid *edid, int index) 1620 { 1621 return edid_block_data(edid, index + 1); 1622 } 1623 1624 /* EDID block count indicated in EDID, may exceed allocated size */ 1625 static int __drm_edid_block_count(const struct drm_edid *drm_edid) 1626 { 1627 int num_blocks; 1628 1629 /* Starting point */ 1630 num_blocks = edid_block_count(drm_edid->edid); 1631 1632 /* HF-EEODB override */ 1633 if (drm_edid->size >= edid_size_by_blocks(2)) { 1634 int eeodb; 1635 1636 /* 1637 * Note: HF-EEODB may specify a smaller extension count than the 1638 * regular one. Unlike in buffer allocation, here we can use it. 1639 */ 1640 eeodb = edid_hfeeodb_block_count(drm_edid->edid); 1641 if (eeodb) 1642 num_blocks = eeodb; 1643 } 1644 1645 return num_blocks; 1646 } 1647 1648 /* EDID block count, limited by allocated size */ 1649 static int drm_edid_block_count(const struct drm_edid *drm_edid) 1650 { 1651 /* Limit by allocated size */ 1652 return min(__drm_edid_block_count(drm_edid), 1653 (int)drm_edid->size / EDID_LENGTH); 1654 } 1655 1656 /* EDID extension block count, limited by allocated size */ 1657 static int drm_edid_extension_block_count(const struct drm_edid *drm_edid) 1658 { 1659 return drm_edid_block_count(drm_edid) - 1; 1660 } 1661 1662 static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index) 1663 { 1664 return edid_block_data(drm_edid->edid, index); 1665 } 1666 1667 static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid, 1668 int index) 1669 { 1670 return edid_extension_block_data(drm_edid->edid, index); 1671 } 1672 1673 /* 1674 * Initializer helper for legacy interfaces, where we have no choice but to 1675 * trust edid size. Not for general purpose use. 1676 */ 1677 static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid, 1678 const struct edid *edid) 1679 { 1680 if (!edid) 1681 return NULL; 1682 1683 memset(drm_edid, 0, sizeof(*drm_edid)); 1684 1685 drm_edid->edid = edid; 1686 drm_edid->size = edid_size(edid); 1687 1688 return drm_edid; 1689 } 1690 1691 /* 1692 * EDID base and extension block iterator. 1693 * 1694 * struct drm_edid_iter iter; 1695 * const u8 *block; 1696 * 1697 * drm_edid_iter_begin(drm_edid, &iter); 1698 * drm_edid_iter_for_each(block, &iter) { 1699 * // do stuff with block 1700 * } 1701 * drm_edid_iter_end(&iter); 1702 */ 1703 struct drm_edid_iter { 1704 const struct drm_edid *drm_edid; 1705 1706 /* Current block index. */ 1707 int index; 1708 }; 1709 1710 static void drm_edid_iter_begin(const struct drm_edid *drm_edid, 1711 struct drm_edid_iter *iter) 1712 { 1713 memset(iter, 0, sizeof(*iter)); 1714 1715 iter->drm_edid = drm_edid; 1716 } 1717 1718 static const void *__drm_edid_iter_next(struct drm_edid_iter *iter) 1719 { 1720 const void *block = NULL; 1721 1722 if (!iter->drm_edid) 1723 return NULL; 1724 1725 if (iter->index < drm_edid_block_count(iter->drm_edid)) 1726 block = drm_edid_block_data(iter->drm_edid, iter->index++); 1727 1728 return block; 1729 } 1730 1731 #define drm_edid_iter_for_each(__block, __iter) \ 1732 while (((__block) = __drm_edid_iter_next(__iter))) 1733 1734 static void drm_edid_iter_end(struct drm_edid_iter *iter) 1735 { 1736 memset(iter, 0, sizeof(*iter)); 1737 } 1738 1739 static const u8 edid_header[] = { 1740 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1741 }; 1742 1743 static void edid_header_fix(void *edid) 1744 { 1745 memcpy(edid, edid_header, sizeof(edid_header)); 1746 } 1747 1748 /** 1749 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1750 * @_edid: pointer to raw base EDID block 1751 * 1752 * Sanity check the header of the base EDID block. 1753 * 1754 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1755 */ 1756 int drm_edid_header_is_valid(const void *_edid) 1757 { 1758 const struct edid *edid = _edid; 1759 int i, score = 0; 1760 1761 for (i = 0; i < sizeof(edid_header); i++) { 1762 if (edid->header[i] == edid_header[i]) 1763 score++; 1764 } 1765 1766 return score; 1767 } 1768 EXPORT_SYMBOL(drm_edid_header_is_valid); 1769 1770 static int edid_fixup __read_mostly = 6; 1771 module_param_named(edid_fixup, edid_fixup, int, 0400); 1772 MODULE_PARM_DESC(edid_fixup, 1773 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1774 1775 static int edid_block_compute_checksum(const void *_block) 1776 { 1777 const u8 *block = _block; 1778 int i; 1779 u8 csum = 0, crc = 0; 1780 1781 for (i = 0; i < EDID_LENGTH - 1; i++) 1782 csum += block[i]; 1783 1784 crc = 0x100 - csum; 1785 1786 return crc; 1787 } 1788 1789 static int edid_block_get_checksum(const void *_block) 1790 { 1791 const struct edid *block = _block; 1792 1793 return block->checksum; 1794 } 1795 1796 static int edid_block_tag(const void *_block) 1797 { 1798 const u8 *block = _block; 1799 1800 return block[0]; 1801 } 1802 1803 static bool edid_block_is_zero(const void *edid) 1804 { 1805 return !memchr_inv(edid, 0, EDID_LENGTH); 1806 } 1807 1808 /** 1809 * drm_edid_are_equal - compare two edid blobs. 1810 * @edid1: pointer to first blob 1811 * @edid2: pointer to second blob 1812 * This helper can be used during probing to determine if 1813 * edid had changed. 1814 */ 1815 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2) 1816 { 1817 int edid1_len, edid2_len; 1818 bool edid1_present = edid1 != NULL; 1819 bool edid2_present = edid2 != NULL; 1820 1821 if (edid1_present != edid2_present) 1822 return false; 1823 1824 if (edid1) { 1825 edid1_len = edid_size(edid1); 1826 edid2_len = edid_size(edid2); 1827 1828 if (edid1_len != edid2_len) 1829 return false; 1830 1831 if (memcmp(edid1, edid2, edid1_len)) 1832 return false; 1833 } 1834 1835 return true; 1836 } 1837 EXPORT_SYMBOL(drm_edid_are_equal); 1838 1839 enum edid_block_status { 1840 EDID_BLOCK_OK = 0, 1841 EDID_BLOCK_READ_FAIL, 1842 EDID_BLOCK_NULL, 1843 EDID_BLOCK_ZERO, 1844 EDID_BLOCK_HEADER_CORRUPT, 1845 EDID_BLOCK_HEADER_REPAIR, 1846 EDID_BLOCK_HEADER_FIXED, 1847 EDID_BLOCK_CHECKSUM, 1848 EDID_BLOCK_VERSION, 1849 }; 1850 1851 static enum edid_block_status edid_block_check(const void *_block, 1852 bool is_base_block) 1853 { 1854 const struct edid *block = _block; 1855 1856 if (!block) 1857 return EDID_BLOCK_NULL; 1858 1859 if (is_base_block) { 1860 int score = drm_edid_header_is_valid(block); 1861 1862 if (score < clamp(edid_fixup, 0, 8)) { 1863 if (edid_block_is_zero(block)) 1864 return EDID_BLOCK_ZERO; 1865 else 1866 return EDID_BLOCK_HEADER_CORRUPT; 1867 } 1868 1869 if (score < 8) 1870 return EDID_BLOCK_HEADER_REPAIR; 1871 } 1872 1873 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) { 1874 if (edid_block_is_zero(block)) 1875 return EDID_BLOCK_ZERO; 1876 else 1877 return EDID_BLOCK_CHECKSUM; 1878 } 1879 1880 if (is_base_block) { 1881 if (block->version != 1) 1882 return EDID_BLOCK_VERSION; 1883 } 1884 1885 return EDID_BLOCK_OK; 1886 } 1887 1888 static bool edid_block_status_valid(enum edid_block_status status, int tag) 1889 { 1890 return status == EDID_BLOCK_OK || 1891 status == EDID_BLOCK_HEADER_FIXED || 1892 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT); 1893 } 1894 1895 static bool edid_block_valid(const void *block, bool base) 1896 { 1897 return edid_block_status_valid(edid_block_check(block, base), 1898 edid_block_tag(block)); 1899 } 1900 1901 static void edid_block_status_print(enum edid_block_status status, 1902 const struct edid *block, 1903 int block_num) 1904 { 1905 switch (status) { 1906 case EDID_BLOCK_OK: 1907 break; 1908 case EDID_BLOCK_READ_FAIL: 1909 pr_debug("EDID block %d read failed\n", block_num); 1910 break; 1911 case EDID_BLOCK_NULL: 1912 pr_debug("EDID block %d pointer is NULL\n", block_num); 1913 break; 1914 case EDID_BLOCK_ZERO: 1915 pr_notice("EDID block %d is all zeroes\n", block_num); 1916 break; 1917 case EDID_BLOCK_HEADER_CORRUPT: 1918 pr_notice("EDID has corrupt header\n"); 1919 break; 1920 case EDID_BLOCK_HEADER_REPAIR: 1921 pr_debug("EDID corrupt header needs repair\n"); 1922 break; 1923 case EDID_BLOCK_HEADER_FIXED: 1924 pr_debug("EDID corrupt header fixed\n"); 1925 break; 1926 case EDID_BLOCK_CHECKSUM: 1927 if (edid_block_status_valid(status, edid_block_tag(block))) { 1928 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n", 1929 block_num, edid_block_tag(block), 1930 edid_block_compute_checksum(block)); 1931 } else { 1932 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n", 1933 block_num, edid_block_tag(block), 1934 edid_block_compute_checksum(block)); 1935 } 1936 break; 1937 case EDID_BLOCK_VERSION: 1938 pr_notice("EDID has major version %d, instead of 1\n", 1939 block->version); 1940 break; 1941 default: 1942 WARN(1, "EDID block %d unknown edid block status code %d\n", 1943 block_num, status); 1944 break; 1945 } 1946 } 1947 1948 static void edid_block_dump(const char *level, const void *block, int block_num) 1949 { 1950 enum edid_block_status status; 1951 char prefix[20]; 1952 1953 status = edid_block_check(block, block_num == 0); 1954 if (status == EDID_BLOCK_ZERO) 1955 sprintf(prefix, "\t[%02x] ZERO ", block_num); 1956 else if (!edid_block_status_valid(status, edid_block_tag(block))) 1957 sprintf(prefix, "\t[%02x] BAD ", block_num); 1958 else 1959 sprintf(prefix, "\t[%02x] GOOD ", block_num); 1960 1961 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1, 1962 block, EDID_LENGTH, false); 1963 } 1964 1965 /** 1966 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1967 * @_block: pointer to raw EDID block 1968 * @block_num: type of block to validate (0 for base, extension otherwise) 1969 * @print_bad_edid: if true, dump bad EDID blocks to the console 1970 * @edid_corrupt: if true, the header or checksum is invalid 1971 * 1972 * Validate a base or extension EDID block and optionally dump bad blocks to 1973 * the console. 1974 * 1975 * Return: True if the block is valid, false otherwise. 1976 */ 1977 bool drm_edid_block_valid(u8 *_block, int block_num, bool print_bad_edid, 1978 bool *edid_corrupt) 1979 { 1980 struct edid *block = (struct edid *)_block; 1981 enum edid_block_status status; 1982 bool is_base_block = block_num == 0; 1983 bool valid; 1984 1985 if (WARN_ON(!block)) 1986 return false; 1987 1988 status = edid_block_check(block, is_base_block); 1989 if (status == EDID_BLOCK_HEADER_REPAIR) { 1990 DRM_DEBUG_KMS("Fixing EDID header, your hardware may be failing\n"); 1991 edid_header_fix(block); 1992 1993 /* Retry with fixed header, update status if that worked. */ 1994 status = edid_block_check(block, is_base_block); 1995 if (status == EDID_BLOCK_OK) 1996 status = EDID_BLOCK_HEADER_FIXED; 1997 } 1998 1999 if (edid_corrupt) { 2000 /* 2001 * Unknown major version isn't corrupt but we can't use it. Only 2002 * the base block can reset edid_corrupt to false. 2003 */ 2004 if (is_base_block && 2005 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)) 2006 *edid_corrupt = false; 2007 else if (status != EDID_BLOCK_OK) 2008 *edid_corrupt = true; 2009 } 2010 2011 edid_block_status_print(status, block, block_num); 2012 2013 /* Determine whether we can use this block with this status. */ 2014 valid = edid_block_status_valid(status, edid_block_tag(block)); 2015 2016 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) { 2017 pr_notice("Raw EDID:\n"); 2018 edid_block_dump(KERN_NOTICE, block, block_num); 2019 } 2020 2021 return valid; 2022 } 2023 EXPORT_SYMBOL(drm_edid_block_valid); 2024 2025 /** 2026 * drm_edid_is_valid - sanity check EDID data 2027 * @edid: EDID data 2028 * 2029 * Sanity-check an entire EDID record (including extensions) 2030 * 2031 * Return: True if the EDID data is valid, false otherwise. 2032 */ 2033 bool drm_edid_is_valid(struct edid *edid) 2034 { 2035 int i; 2036 2037 if (!edid) 2038 return false; 2039 2040 for (i = 0; i < edid_block_count(edid); i++) { 2041 void *block = (void *)edid_block_data(edid, i); 2042 2043 if (!drm_edid_block_valid(block, i, true, NULL)) 2044 return false; 2045 } 2046 2047 return true; 2048 } 2049 EXPORT_SYMBOL(drm_edid_is_valid); 2050 2051 /** 2052 * drm_edid_valid - sanity check EDID data 2053 * @drm_edid: EDID data 2054 * 2055 * Sanity check an EDID. Cross check block count against allocated size and 2056 * checksum the blocks. 2057 * 2058 * Return: True if the EDID data is valid, false otherwise. 2059 */ 2060 bool drm_edid_valid(const struct drm_edid *drm_edid) 2061 { 2062 int i; 2063 2064 if (!drm_edid) 2065 return false; 2066 2067 if (edid_size_by_blocks(__drm_edid_block_count(drm_edid)) != drm_edid->size) 2068 return false; 2069 2070 for (i = 0; i < drm_edid_block_count(drm_edid); i++) { 2071 const void *block = drm_edid_block_data(drm_edid, i); 2072 2073 if (!edid_block_valid(block, i == 0)) 2074 return false; 2075 } 2076 2077 return true; 2078 } 2079 EXPORT_SYMBOL(drm_edid_valid); 2080 2081 static struct edid *edid_filter_invalid_blocks(struct edid *edid, 2082 size_t *alloc_size) 2083 { 2084 struct edid *new; 2085 int i, valid_blocks = 0; 2086 2087 /* 2088 * Note: If the EDID uses HF-EEODB, but has invalid blocks, we'll revert 2089 * back to regular extension count here. We don't want to start 2090 * modifying the HF-EEODB extension too. 2091 */ 2092 for (i = 0; i < edid_block_count(edid); i++) { 2093 const void *src_block = edid_block_data(edid, i); 2094 2095 if (edid_block_valid(src_block, i == 0)) { 2096 void *dst_block = (void *)edid_block_data(edid, valid_blocks); 2097 2098 memmove(dst_block, src_block, EDID_LENGTH); 2099 valid_blocks++; 2100 } 2101 } 2102 2103 /* We already trusted the base block to be valid here... */ 2104 if (WARN_ON(!valid_blocks)) { 2105 kfree(edid); 2106 return NULL; 2107 } 2108 2109 edid->extensions = valid_blocks - 1; 2110 edid->checksum = edid_block_compute_checksum(edid); 2111 2112 *alloc_size = edid_size_by_blocks(valid_blocks); 2113 2114 new = krealloc(edid, *alloc_size, GFP_KERNEL); 2115 if (!new) 2116 kfree(edid); 2117 2118 return new; 2119 } 2120 2121 #define DDC_SEGMENT_ADDR 0x30 2122 /** 2123 * drm_do_probe_ddc_edid() - get EDID information via I2C 2124 * @data: I2C device adapter 2125 * @buf: EDID data buffer to be filled 2126 * @block: 128 byte EDID block to start fetching from 2127 * @len: EDID data buffer length to fetch 2128 * 2129 * Try to fetch EDID information by calling I2C driver functions. 2130 * 2131 * Return: 0 on success or -1 on failure. 2132 */ 2133 static int 2134 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 2135 { 2136 struct i2c_adapter *adapter = data; 2137 unsigned char start = block * EDID_LENGTH; 2138 unsigned char segment = block >> 1; 2139 unsigned char xfers = segment ? 3 : 2; 2140 int ret, retries = 5; 2141 2142 /* 2143 * The core I2C driver will automatically retry the transfer if the 2144 * adapter reports EAGAIN. However, we find that bit-banging transfers 2145 * are susceptible to errors under a heavily loaded machine and 2146 * generate spurious NAKs and timeouts. Retrying the transfer 2147 * of the individual block a few times seems to overcome this. 2148 */ 2149 do { 2150 struct i2c_msg msgs[] = { 2151 { 2152 .addr = DDC_SEGMENT_ADDR, 2153 .flags = 0, 2154 .len = 1, 2155 .buf = &segment, 2156 }, { 2157 .addr = DDC_ADDR, 2158 .flags = 0, 2159 .len = 1, 2160 .buf = &start, 2161 }, { 2162 .addr = DDC_ADDR, 2163 .flags = I2C_M_RD, 2164 .len = len, 2165 .buf = buf, 2166 } 2167 }; 2168 2169 /* 2170 * Avoid sending the segment addr to not upset non-compliant 2171 * DDC monitors. 2172 */ 2173 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 2174 2175 if (ret == -ENXIO) { 2176 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 2177 adapter->name); 2178 break; 2179 } 2180 } while (ret != xfers && --retries); 2181 2182 return ret == xfers ? 0 : -1; 2183 } 2184 2185 static void connector_bad_edid(struct drm_connector *connector, 2186 const struct edid *edid, int num_blocks) 2187 { 2188 int i; 2189 u8 last_block; 2190 2191 /* 2192 * 0x7e in the EDID is the number of extension blocks. The EDID 2193 * is 1 (base block) + num_ext_blocks big. That means we can think 2194 * of 0x7e in the EDID of the _index_ of the last block in the 2195 * combined chunk of memory. 2196 */ 2197 last_block = edid->extensions; 2198 2199 /* Calculate real checksum for the last edid extension block data */ 2200 if (last_block < num_blocks) 2201 connector->real_edid_checksum = 2202 edid_block_compute_checksum(edid + last_block); 2203 2204 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS)) 2205 return; 2206 2207 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID is invalid:\n", 2208 connector->base.id, connector->name); 2209 for (i = 0; i < num_blocks; i++) 2210 edid_block_dump(KERN_DEBUG, edid + i, i); 2211 } 2212 2213 /* Get override or firmware EDID */ 2214 static const struct drm_edid *drm_edid_override_get(struct drm_connector *connector) 2215 { 2216 const struct drm_edid *override = NULL; 2217 2218 mutex_lock(&connector->edid_override_mutex); 2219 2220 if (connector->edid_override) 2221 override = drm_edid_dup(connector->edid_override); 2222 2223 mutex_unlock(&connector->edid_override_mutex); 2224 2225 if (!override) 2226 override = drm_edid_load_firmware(connector); 2227 2228 return IS_ERR(override) ? NULL : override; 2229 } 2230 2231 /* For debugfs edid_override implementation */ 2232 int drm_edid_override_show(struct drm_connector *connector, struct seq_file *m) 2233 { 2234 const struct drm_edid *drm_edid; 2235 2236 mutex_lock(&connector->edid_override_mutex); 2237 2238 drm_edid = connector->edid_override; 2239 if (drm_edid) 2240 seq_write(m, drm_edid->edid, drm_edid->size); 2241 2242 mutex_unlock(&connector->edid_override_mutex); 2243 2244 return 0; 2245 } 2246 2247 /* For debugfs edid_override implementation */ 2248 int drm_edid_override_set(struct drm_connector *connector, const void *edid, 2249 size_t size) 2250 { 2251 const struct drm_edid *drm_edid; 2252 2253 drm_edid = drm_edid_alloc(edid, size); 2254 if (!drm_edid_valid(drm_edid)) { 2255 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override invalid\n", 2256 connector->base.id, connector->name); 2257 drm_edid_free(drm_edid); 2258 return -EINVAL; 2259 } 2260 2261 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override set\n", 2262 connector->base.id, connector->name); 2263 2264 mutex_lock(&connector->edid_override_mutex); 2265 2266 drm_edid_free(connector->edid_override); 2267 connector->edid_override = drm_edid; 2268 2269 mutex_unlock(&connector->edid_override_mutex); 2270 2271 return 0; 2272 } 2273 2274 /* For debugfs edid_override implementation */ 2275 int drm_edid_override_reset(struct drm_connector *connector) 2276 { 2277 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override reset\n", 2278 connector->base.id, connector->name); 2279 2280 mutex_lock(&connector->edid_override_mutex); 2281 2282 drm_edid_free(connector->edid_override); 2283 connector->edid_override = NULL; 2284 2285 mutex_unlock(&connector->edid_override_mutex); 2286 2287 return 0; 2288 } 2289 2290 /** 2291 * drm_edid_override_connector_update - add modes from override/firmware EDID 2292 * @connector: connector we're probing 2293 * 2294 * Add modes from the override/firmware EDID, if available. Only to be used from 2295 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe 2296 * failed during drm_get_edid() and caused the override/firmware EDID to be 2297 * skipped. 2298 * 2299 * Return: The number of modes added or 0 if we couldn't find any. 2300 */ 2301 int drm_edid_override_connector_update(struct drm_connector *connector) 2302 { 2303 const struct drm_edid *override; 2304 int num_modes = 0; 2305 2306 override = drm_edid_override_get(connector); 2307 if (override) { 2308 num_modes = drm_edid_connector_update(connector, override); 2309 2310 drm_edid_free(override); 2311 2312 drm_dbg_kms(connector->dev, 2313 "[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n", 2314 connector->base.id, connector->name, num_modes); 2315 } 2316 2317 return num_modes; 2318 } 2319 EXPORT_SYMBOL(drm_edid_override_connector_update); 2320 2321 typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len); 2322 2323 static enum edid_block_status edid_block_read(void *block, unsigned int block_num, 2324 read_block_fn read_block, 2325 void *context) 2326 { 2327 enum edid_block_status status; 2328 bool is_base_block = block_num == 0; 2329 int try; 2330 2331 for (try = 0; try < 4; try++) { 2332 if (read_block(context, block, block_num, EDID_LENGTH)) 2333 return EDID_BLOCK_READ_FAIL; 2334 2335 status = edid_block_check(block, is_base_block); 2336 if (status == EDID_BLOCK_HEADER_REPAIR) { 2337 edid_header_fix(block); 2338 2339 /* Retry with fixed header, update status if that worked. */ 2340 status = edid_block_check(block, is_base_block); 2341 if (status == EDID_BLOCK_OK) 2342 status = EDID_BLOCK_HEADER_FIXED; 2343 } 2344 2345 if (edid_block_status_valid(status, edid_block_tag(block))) 2346 break; 2347 2348 /* Fail early for unrepairable base block all zeros. */ 2349 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO) 2350 break; 2351 } 2352 2353 return status; 2354 } 2355 2356 static struct edid *_drm_do_get_edid(struct drm_connector *connector, 2357 read_block_fn read_block, void *context, 2358 size_t *size) 2359 { 2360 enum edid_block_status status; 2361 int i, num_blocks, invalid_blocks = 0; 2362 const struct drm_edid *override; 2363 struct edid *edid, *new; 2364 size_t alloc_size = EDID_LENGTH; 2365 2366 override = drm_edid_override_get(connector); 2367 if (override) { 2368 alloc_size = override->size; 2369 edid = kmemdup(override->edid, alloc_size, GFP_KERNEL); 2370 drm_edid_free(override); 2371 if (!edid) 2372 return NULL; 2373 goto ok; 2374 } 2375 2376 edid = kmalloc(alloc_size, GFP_KERNEL); 2377 if (!edid) 2378 return NULL; 2379 2380 status = edid_block_read(edid, 0, read_block, context); 2381 2382 edid_block_status_print(status, edid, 0); 2383 2384 if (status == EDID_BLOCK_READ_FAIL) 2385 goto fail; 2386 2387 /* FIXME: Clarify what a corrupt EDID actually means. */ 2388 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION) 2389 connector->edid_corrupt = false; 2390 else 2391 connector->edid_corrupt = true; 2392 2393 if (!edid_block_status_valid(status, edid_block_tag(edid))) { 2394 if (status == EDID_BLOCK_ZERO) 2395 connector->null_edid_counter++; 2396 2397 connector_bad_edid(connector, edid, 1); 2398 goto fail; 2399 } 2400 2401 if (!edid_extension_block_count(edid)) 2402 goto ok; 2403 2404 alloc_size = edid_size(edid); 2405 new = krealloc(edid, alloc_size, GFP_KERNEL); 2406 if (!new) 2407 goto fail; 2408 edid = new; 2409 2410 num_blocks = edid_block_count(edid); 2411 for (i = 1; i < num_blocks; i++) { 2412 void *block = (void *)edid_block_data(edid, i); 2413 2414 status = edid_block_read(block, i, read_block, context); 2415 2416 edid_block_status_print(status, block, i); 2417 2418 if (!edid_block_status_valid(status, edid_block_tag(block))) { 2419 if (status == EDID_BLOCK_READ_FAIL) 2420 goto fail; 2421 invalid_blocks++; 2422 } else if (i == 1) { 2423 /* 2424 * If the first EDID extension is a CTA extension, and 2425 * the first Data Block is HF-EEODB, override the 2426 * extension block count. 2427 * 2428 * Note: HF-EEODB could specify a smaller extension 2429 * count too, but we can't risk allocating a smaller 2430 * amount. 2431 */ 2432 int eeodb = edid_hfeeodb_block_count(edid); 2433 2434 if (eeodb > num_blocks) { 2435 num_blocks = eeodb; 2436 alloc_size = edid_size_by_blocks(num_blocks); 2437 new = krealloc(edid, alloc_size, GFP_KERNEL); 2438 if (!new) 2439 goto fail; 2440 edid = new; 2441 } 2442 } 2443 } 2444 2445 if (invalid_blocks) { 2446 connector_bad_edid(connector, edid, num_blocks); 2447 2448 edid = edid_filter_invalid_blocks(edid, &alloc_size); 2449 } 2450 2451 ok: 2452 if (size) 2453 *size = alloc_size; 2454 2455 return edid; 2456 2457 fail: 2458 kfree(edid); 2459 return NULL; 2460 } 2461 2462 /** 2463 * drm_do_get_edid - get EDID data using a custom EDID block read function 2464 * @connector: connector we're probing 2465 * @read_block: EDID block read function 2466 * @context: private data passed to the block read function 2467 * 2468 * When the I2C adapter connected to the DDC bus is hidden behind a device that 2469 * exposes a different interface to read EDID blocks this function can be used 2470 * to get EDID data using a custom block read function. 2471 * 2472 * As in the general case the DDC bus is accessible by the kernel at the I2C 2473 * level, drivers must make all reasonable efforts to expose it as an I2C 2474 * adapter and use drm_get_edid() instead of abusing this function. 2475 * 2476 * The EDID may be overridden using debugfs override_edid or firmware EDID 2477 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2478 * order. Having either of them bypasses actual EDID reads. 2479 * 2480 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2481 */ 2482 struct edid *drm_do_get_edid(struct drm_connector *connector, 2483 read_block_fn read_block, 2484 void *context) 2485 { 2486 return _drm_do_get_edid(connector, read_block, context, NULL); 2487 } 2488 EXPORT_SYMBOL_GPL(drm_do_get_edid); 2489 2490 /** 2491 * drm_edid_raw - Get a pointer to the raw EDID data. 2492 * @drm_edid: drm_edid container 2493 * 2494 * Get a pointer to the raw EDID data. 2495 * 2496 * This is for transition only. Avoid using this like the plague. 2497 * 2498 * Return: Pointer to raw EDID data. 2499 */ 2500 const struct edid *drm_edid_raw(const struct drm_edid *drm_edid) 2501 { 2502 if (!drm_edid || !drm_edid->size) 2503 return NULL; 2504 2505 /* 2506 * Do not return pointers where relying on EDID extension count would 2507 * lead to buffer overflow. 2508 */ 2509 if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size)) 2510 return NULL; 2511 2512 return drm_edid->edid; 2513 } 2514 EXPORT_SYMBOL(drm_edid_raw); 2515 2516 /* Allocate struct drm_edid container *without* duplicating the edid data */ 2517 static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size) 2518 { 2519 struct drm_edid *drm_edid; 2520 2521 if (!edid || !size || size < EDID_LENGTH) 2522 return NULL; 2523 2524 drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL); 2525 if (drm_edid) { 2526 drm_edid->edid = edid; 2527 drm_edid->size = size; 2528 } 2529 2530 return drm_edid; 2531 } 2532 2533 /** 2534 * drm_edid_alloc - Allocate a new drm_edid container 2535 * @edid: Pointer to raw EDID data 2536 * @size: Size of memory allocated for EDID 2537 * 2538 * Allocate a new drm_edid container. Do not calculate edid size from edid, pass 2539 * the actual size that has been allocated for the data. There is no validation 2540 * of the raw EDID data against the size, but at least the EDID base block must 2541 * fit in the buffer. 2542 * 2543 * The returned pointer must be freed using drm_edid_free(). 2544 * 2545 * Return: drm_edid container, or NULL on errors 2546 */ 2547 const struct drm_edid *drm_edid_alloc(const void *edid, size_t size) 2548 { 2549 const struct drm_edid *drm_edid; 2550 2551 if (!edid || !size || size < EDID_LENGTH) 2552 return NULL; 2553 2554 edid = kmemdup(edid, size, GFP_KERNEL); 2555 if (!edid) 2556 return NULL; 2557 2558 drm_edid = _drm_edid_alloc(edid, size); 2559 if (!drm_edid) 2560 kfree(edid); 2561 2562 return drm_edid; 2563 } 2564 EXPORT_SYMBOL(drm_edid_alloc); 2565 2566 /** 2567 * drm_edid_dup - Duplicate a drm_edid container 2568 * @drm_edid: EDID to duplicate 2569 * 2570 * The returned pointer must be freed using drm_edid_free(). 2571 * 2572 * Returns: drm_edid container copy, or NULL on errors 2573 */ 2574 const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid) 2575 { 2576 if (!drm_edid) 2577 return NULL; 2578 2579 return drm_edid_alloc(drm_edid->edid, drm_edid->size); 2580 } 2581 EXPORT_SYMBOL(drm_edid_dup); 2582 2583 /** 2584 * drm_edid_free - Free the drm_edid container 2585 * @drm_edid: EDID to free 2586 */ 2587 void drm_edid_free(const struct drm_edid *drm_edid) 2588 { 2589 if (!drm_edid) 2590 return; 2591 2592 kfree(drm_edid->edid); 2593 kfree(drm_edid); 2594 } 2595 EXPORT_SYMBOL(drm_edid_free); 2596 2597 /** 2598 * drm_probe_ddc() - probe DDC presence 2599 * @adapter: I2C adapter to probe 2600 * 2601 * Return: True on success, false on failure. 2602 */ 2603 bool 2604 drm_probe_ddc(struct i2c_adapter *adapter) 2605 { 2606 unsigned char out; 2607 2608 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 2609 } 2610 EXPORT_SYMBOL(drm_probe_ddc); 2611 2612 /** 2613 * drm_get_edid - get EDID data, if available 2614 * @connector: connector we're probing 2615 * @adapter: I2C adapter to use for DDC 2616 * 2617 * Poke the given I2C channel to grab EDID data if possible. If found, 2618 * attach it to the connector. 2619 * 2620 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2621 */ 2622 struct edid *drm_get_edid(struct drm_connector *connector, 2623 struct i2c_adapter *adapter) 2624 { 2625 struct edid *edid; 2626 2627 if (connector->force == DRM_FORCE_OFF) 2628 return NULL; 2629 2630 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2631 return NULL; 2632 2633 edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL); 2634 drm_connector_update_edid_property(connector, edid); 2635 return edid; 2636 } 2637 EXPORT_SYMBOL(drm_get_edid); 2638 2639 /** 2640 * drm_edid_read_custom - Read EDID data using given EDID block read function 2641 * @connector: Connector to use 2642 * @read_block: EDID block read function 2643 * @context: Private data passed to the block read function 2644 * 2645 * When the I2C adapter connected to the DDC bus is hidden behind a device that 2646 * exposes a different interface to read EDID blocks this function can be used 2647 * to get EDID data using a custom block read function. 2648 * 2649 * As in the general case the DDC bus is accessible by the kernel at the I2C 2650 * level, drivers must make all reasonable efforts to expose it as an I2C 2651 * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing 2652 * this function. 2653 * 2654 * The EDID may be overridden using debugfs override_edid or firmware EDID 2655 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2656 * order. Having either of them bypasses actual EDID reads. 2657 * 2658 * The returned pointer must be freed using drm_edid_free(). 2659 * 2660 * Return: Pointer to EDID, or NULL if probe/read failed. 2661 */ 2662 const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector, 2663 read_block_fn read_block, 2664 void *context) 2665 { 2666 const struct drm_edid *drm_edid; 2667 struct edid *edid; 2668 size_t size = 0; 2669 2670 edid = _drm_do_get_edid(connector, read_block, context, &size); 2671 if (!edid) 2672 return NULL; 2673 2674 /* Sanity check for now */ 2675 drm_WARN_ON(connector->dev, !size); 2676 2677 drm_edid = _drm_edid_alloc(edid, size); 2678 if (!drm_edid) 2679 kfree(edid); 2680 2681 return drm_edid; 2682 } 2683 EXPORT_SYMBOL(drm_edid_read_custom); 2684 2685 /** 2686 * drm_edid_read_ddc - Read EDID data using given I2C adapter 2687 * @connector: Connector to use 2688 * @adapter: I2C adapter to use for DDC 2689 * 2690 * Read EDID using the given I2C adapter. 2691 * 2692 * The EDID may be overridden using debugfs override_edid or firmware EDID 2693 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2694 * order. Having either of them bypasses actual EDID reads. 2695 * 2696 * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and 2697 * using drm_edid_read() instead of this function. 2698 * 2699 * The returned pointer must be freed using drm_edid_free(). 2700 * 2701 * Return: Pointer to EDID, or NULL if probe/read failed. 2702 */ 2703 const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector, 2704 struct i2c_adapter *adapter) 2705 { 2706 const struct drm_edid *drm_edid; 2707 2708 if (connector->force == DRM_FORCE_OFF) 2709 return NULL; 2710 2711 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2712 return NULL; 2713 2714 drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter); 2715 2716 /* Note: Do *not* call connector updates here. */ 2717 2718 return drm_edid; 2719 } 2720 EXPORT_SYMBOL(drm_edid_read_ddc); 2721 2722 /** 2723 * drm_edid_read - Read EDID data using connector's I2C adapter 2724 * @connector: Connector to use 2725 * 2726 * Read EDID using the connector's I2C adapter. 2727 * 2728 * The EDID may be overridden using debugfs override_edid or firmware EDID 2729 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2730 * order. Having either of them bypasses actual EDID reads. 2731 * 2732 * The returned pointer must be freed using drm_edid_free(). 2733 * 2734 * Return: Pointer to EDID, or NULL if probe/read failed. 2735 */ 2736 const struct drm_edid *drm_edid_read(struct drm_connector *connector) 2737 { 2738 if (drm_WARN_ON(connector->dev, !connector->ddc)) 2739 return NULL; 2740 2741 return drm_edid_read_ddc(connector, connector->ddc); 2742 } 2743 EXPORT_SYMBOL(drm_edid_read); 2744 2745 static u32 edid_extract_panel_id(const struct edid *edid) 2746 { 2747 /* 2748 * We represent the ID as a 32-bit number so it can easily be compared 2749 * with "==". 2750 * 2751 * NOTE that we deal with endianness differently for the top half 2752 * of this ID than for the bottom half. The bottom half (the product 2753 * id) gets decoded as little endian by the EDID_PRODUCT_ID because 2754 * that's how everyone seems to interpret it. The top half (the mfg_id) 2755 * gets stored as big endian because that makes 2756 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier 2757 * to write (it's easier to extract the ASCII). It doesn't really 2758 * matter, though, as long as the number here is unique. 2759 */ 2760 return (u32)edid->mfg_id[0] << 24 | 2761 (u32)edid->mfg_id[1] << 16 | 2762 (u32)EDID_PRODUCT_ID(edid); 2763 } 2764 2765 /** 2766 * drm_edid_get_panel_id - Get a panel's ID through DDC 2767 * @adapter: I2C adapter to use for DDC 2768 * 2769 * This function reads the first block of the EDID of a panel and (assuming 2770 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value 2771 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's 2772 * supposed to be different for each different modem of panel. 2773 * 2774 * This function is intended to be used during early probing on devices where 2775 * more than one panel might be present. Because of its intended use it must 2776 * assume that the EDID of the panel is correct, at least as far as the ID 2777 * is concerned (in other words, we don't process any overrides here). 2778 * 2779 * NOTE: it's expected that this function and drm_do_get_edid() will both 2780 * be read the EDID, but there is no caching between them. Since we're only 2781 * reading the first block, hopefully this extra overhead won't be too big. 2782 * 2783 * Return: A 32-bit ID that should be different for each make/model of panel. 2784 * See the functions drm_edid_encode_panel_id() and 2785 * drm_edid_decode_panel_id() for some details on the structure of this 2786 * ID. 2787 */ 2788 2789 u32 drm_edid_get_panel_id(struct i2c_adapter *adapter) 2790 { 2791 enum edid_block_status status; 2792 void *base_block; 2793 u32 panel_id = 0; 2794 2795 /* 2796 * There are no manufacturer IDs of 0, so if there is a problem reading 2797 * the EDID then we'll just return 0. 2798 */ 2799 2800 base_block = kzalloc(EDID_LENGTH, GFP_KERNEL); 2801 if (!base_block) 2802 return 0; 2803 2804 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter); 2805 2806 edid_block_status_print(status, base_block, 0); 2807 2808 if (edid_block_status_valid(status, edid_block_tag(base_block))) 2809 panel_id = edid_extract_panel_id(base_block); 2810 else 2811 edid_block_dump(KERN_NOTICE, base_block, 0); 2812 2813 kfree(base_block); 2814 2815 return panel_id; 2816 } 2817 EXPORT_SYMBOL(drm_edid_get_panel_id); 2818 2819 /** 2820 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 2821 * @connector: connector we're probing 2822 * @adapter: I2C adapter to use for DDC 2823 * 2824 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 2825 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 2826 * switch DDC to the GPU which is retrieving EDID. 2827 * 2828 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2829 */ 2830 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 2831 struct i2c_adapter *adapter) 2832 { 2833 struct drm_device *dev = connector->dev; 2834 struct pci_dev *pdev = to_pci_dev(dev->dev); 2835 struct edid *edid; 2836 2837 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev))) 2838 return NULL; 2839 2840 vga_switcheroo_lock_ddc(pdev); 2841 edid = drm_get_edid(connector, adapter); 2842 vga_switcheroo_unlock_ddc(pdev); 2843 2844 return edid; 2845 } 2846 EXPORT_SYMBOL(drm_get_edid_switcheroo); 2847 2848 /** 2849 * drm_edid_read_switcheroo - get EDID data for a vga_switcheroo output 2850 * @connector: connector we're probing 2851 * @adapter: I2C adapter to use for DDC 2852 * 2853 * Wrapper around drm_edid_read_ddc() for laptops with dual GPUs using one set 2854 * of outputs. The wrapper adds the requisite vga_switcheroo calls to 2855 * temporarily switch DDC to the GPU which is retrieving EDID. 2856 * 2857 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2858 */ 2859 const struct drm_edid *drm_edid_read_switcheroo(struct drm_connector *connector, 2860 struct i2c_adapter *adapter) 2861 { 2862 struct drm_device *dev = connector->dev; 2863 struct pci_dev *pdev = to_pci_dev(dev->dev); 2864 const struct drm_edid *drm_edid; 2865 2866 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev))) 2867 return NULL; 2868 2869 vga_switcheroo_lock_ddc(pdev); 2870 drm_edid = drm_edid_read_ddc(connector, adapter); 2871 vga_switcheroo_unlock_ddc(pdev); 2872 2873 return drm_edid; 2874 } 2875 EXPORT_SYMBOL(drm_edid_read_switcheroo); 2876 2877 /** 2878 * drm_edid_duplicate - duplicate an EDID and the extensions 2879 * @edid: EDID to duplicate 2880 * 2881 * Return: Pointer to duplicated EDID or NULL on allocation failure. 2882 */ 2883 struct edid *drm_edid_duplicate(const struct edid *edid) 2884 { 2885 if (!edid) 2886 return NULL; 2887 2888 return kmemdup(edid, edid_size(edid), GFP_KERNEL); 2889 } 2890 EXPORT_SYMBOL(drm_edid_duplicate); 2891 2892 /*** EDID parsing ***/ 2893 2894 /** 2895 * edid_get_quirks - return quirk flags for a given EDID 2896 * @drm_edid: EDID to process 2897 * 2898 * This tells subsequent routines what fixes they need to apply. 2899 */ 2900 static u32 edid_get_quirks(const struct drm_edid *drm_edid) 2901 { 2902 u32 panel_id = edid_extract_panel_id(drm_edid->edid); 2903 const struct edid_quirk *quirk; 2904 int i; 2905 2906 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 2907 quirk = &edid_quirk_list[i]; 2908 if (quirk->panel_id == panel_id) 2909 return quirk->quirks; 2910 } 2911 2912 return 0; 2913 } 2914 2915 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 2916 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 2917 2918 /* 2919 * Walk the mode list for connector, clearing the preferred status on existing 2920 * modes and setting it anew for the right mode ala quirks. 2921 */ 2922 static void edid_fixup_preferred(struct drm_connector *connector) 2923 { 2924 const struct drm_display_info *info = &connector->display_info; 2925 struct drm_display_mode *t, *cur_mode, *preferred_mode; 2926 int target_refresh = 0; 2927 int cur_vrefresh, preferred_vrefresh; 2928 2929 if (list_empty(&connector->probed_modes)) 2930 return; 2931 2932 if (info->quirks & EDID_QUIRK_PREFER_LARGE_60) 2933 target_refresh = 60; 2934 if (info->quirks & EDID_QUIRK_PREFER_LARGE_75) 2935 target_refresh = 75; 2936 2937 preferred_mode = list_first_entry(&connector->probed_modes, 2938 struct drm_display_mode, head); 2939 2940 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 2941 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 2942 2943 if (cur_mode == preferred_mode) 2944 continue; 2945 2946 /* Largest mode is preferred */ 2947 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 2948 preferred_mode = cur_mode; 2949 2950 cur_vrefresh = drm_mode_vrefresh(cur_mode); 2951 preferred_vrefresh = drm_mode_vrefresh(preferred_mode); 2952 /* At a given size, try to get closest to target refresh */ 2953 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 2954 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 2955 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 2956 preferred_mode = cur_mode; 2957 } 2958 } 2959 2960 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 2961 } 2962 2963 static bool 2964 mode_is_rb(const struct drm_display_mode *mode) 2965 { 2966 return (mode->htotal - mode->hdisplay == 160) && 2967 (mode->hsync_end - mode->hdisplay == 80) && 2968 (mode->hsync_end - mode->hsync_start == 32) && 2969 (mode->vsync_start - mode->vdisplay == 3); 2970 } 2971 2972 /* 2973 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 2974 * @dev: Device to duplicate against 2975 * @hsize: Mode width 2976 * @vsize: Mode height 2977 * @fresh: Mode refresh rate 2978 * @rb: Mode reduced-blanking-ness 2979 * 2980 * Walk the DMT mode list looking for a match for the given parameters. 2981 * 2982 * Return: A newly allocated copy of the mode, or NULL if not found. 2983 */ 2984 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 2985 int hsize, int vsize, int fresh, 2986 bool rb) 2987 { 2988 int i; 2989 2990 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2991 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 2992 2993 if (hsize != ptr->hdisplay) 2994 continue; 2995 if (vsize != ptr->vdisplay) 2996 continue; 2997 if (fresh != drm_mode_vrefresh(ptr)) 2998 continue; 2999 if (rb != mode_is_rb(ptr)) 3000 continue; 3001 3002 return drm_mode_duplicate(dev, ptr); 3003 } 3004 3005 return NULL; 3006 } 3007 EXPORT_SYMBOL(drm_mode_find_dmt); 3008 3009 static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type) 3010 { 3011 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0); 3012 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2); 3013 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3); 3014 3015 return descriptor->pixel_clock == 0 && 3016 descriptor->data.other_data.pad1 == 0 && 3017 descriptor->data.other_data.type == type; 3018 } 3019 3020 static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor) 3021 { 3022 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0); 3023 3024 return descriptor->pixel_clock != 0; 3025 } 3026 3027 typedef void detailed_cb(const struct detailed_timing *timing, void *closure); 3028 3029 static void 3030 cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure) 3031 { 3032 int i, n; 3033 u8 d = ext[0x02]; 3034 const u8 *det_base = ext + d; 3035 3036 if (d < 4 || d > 127) 3037 return; 3038 3039 n = (127 - d) / 18; 3040 for (i = 0; i < n; i++) 3041 cb((const struct detailed_timing *)(det_base + 18 * i), closure); 3042 } 3043 3044 static void 3045 vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure) 3046 { 3047 unsigned int i, n = min((int)ext[0x02], 6); 3048 const u8 *det_base = ext + 5; 3049 3050 if (ext[0x01] != 1) 3051 return; /* unknown version */ 3052 3053 for (i = 0; i < n; i++) 3054 cb((const struct detailed_timing *)(det_base + 18 * i), closure); 3055 } 3056 3057 static void drm_for_each_detailed_block(const struct drm_edid *drm_edid, 3058 detailed_cb *cb, void *closure) 3059 { 3060 struct drm_edid_iter edid_iter; 3061 const u8 *ext; 3062 int i; 3063 3064 if (!drm_edid) 3065 return; 3066 3067 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 3068 cb(&drm_edid->edid->detailed_timings[i], closure); 3069 3070 drm_edid_iter_begin(drm_edid, &edid_iter); 3071 drm_edid_iter_for_each(ext, &edid_iter) { 3072 switch (*ext) { 3073 case CEA_EXT: 3074 cea_for_each_detailed_block(ext, cb, closure); 3075 break; 3076 case VTB_EXT: 3077 vtb_for_each_detailed_block(ext, cb, closure); 3078 break; 3079 default: 3080 break; 3081 } 3082 } 3083 drm_edid_iter_end(&edid_iter); 3084 } 3085 3086 static void 3087 is_rb(const struct detailed_timing *descriptor, void *data) 3088 { 3089 bool *res = data; 3090 3091 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 3092 return; 3093 3094 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 3095 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15); 3096 3097 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG && 3098 descriptor->data.other_data.data.range.formula.cvt.flags & DRM_EDID_CVT_FLAGS_REDUCED_BLANKING) 3099 *res = true; 3100 } 3101 3102 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 3103 static bool 3104 drm_monitor_supports_rb(const struct drm_edid *drm_edid) 3105 { 3106 if (drm_edid->edid->revision >= 4) { 3107 bool ret = false; 3108 3109 drm_for_each_detailed_block(drm_edid, is_rb, &ret); 3110 return ret; 3111 } 3112 3113 return ((drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 3114 } 3115 3116 static void 3117 find_gtf2(const struct detailed_timing *descriptor, void *data) 3118 { 3119 const struct detailed_timing **res = data; 3120 3121 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 3122 return; 3123 3124 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 3125 3126 if (descriptor->data.other_data.data.range.flags == DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG) 3127 *res = descriptor; 3128 } 3129 3130 /* Secondary GTF curve kicks in above some break frequency */ 3131 static int 3132 drm_gtf2_hbreak(const struct drm_edid *drm_edid) 3133 { 3134 const struct detailed_timing *descriptor = NULL; 3135 3136 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3137 3138 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12); 3139 3140 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0; 3141 } 3142 3143 static int 3144 drm_gtf2_2c(const struct drm_edid *drm_edid) 3145 { 3146 const struct detailed_timing *descriptor = NULL; 3147 3148 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3149 3150 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13); 3151 3152 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0; 3153 } 3154 3155 static int 3156 drm_gtf2_m(const struct drm_edid *drm_edid) 3157 { 3158 const struct detailed_timing *descriptor = NULL; 3159 3160 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3161 3162 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14); 3163 3164 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0; 3165 } 3166 3167 static int 3168 drm_gtf2_k(const struct drm_edid *drm_edid) 3169 { 3170 const struct detailed_timing *descriptor = NULL; 3171 3172 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3173 3174 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16); 3175 3176 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0; 3177 } 3178 3179 static int 3180 drm_gtf2_2j(const struct drm_edid *drm_edid) 3181 { 3182 const struct detailed_timing *descriptor = NULL; 3183 3184 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3185 3186 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17); 3187 3188 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0; 3189 } 3190 3191 static void 3192 get_timing_level(const struct detailed_timing *descriptor, void *data) 3193 { 3194 int *res = data; 3195 3196 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 3197 return; 3198 3199 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 3200 3201 switch (descriptor->data.other_data.data.range.flags) { 3202 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG: 3203 *res = LEVEL_GTF; 3204 break; 3205 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG: 3206 *res = LEVEL_GTF2; 3207 break; 3208 case DRM_EDID_CVT_SUPPORT_FLAG: 3209 *res = LEVEL_CVT; 3210 break; 3211 default: 3212 break; 3213 } 3214 } 3215 3216 /* Get standard timing level (CVT/GTF/DMT). */ 3217 static int standard_timing_level(const struct drm_edid *drm_edid) 3218 { 3219 const struct edid *edid = drm_edid->edid; 3220 3221 if (edid->revision >= 4) { 3222 /* 3223 * If the range descriptor doesn't 3224 * indicate otherwise default to CVT 3225 */ 3226 int ret = LEVEL_CVT; 3227 3228 drm_for_each_detailed_block(drm_edid, get_timing_level, &ret); 3229 3230 return ret; 3231 } else if (edid->revision >= 3 && drm_gtf2_hbreak(drm_edid)) { 3232 return LEVEL_GTF2; 3233 } else if (edid->revision >= 2) { 3234 return LEVEL_GTF; 3235 } else { 3236 return LEVEL_DMT; 3237 } 3238 } 3239 3240 /* 3241 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 3242 * monitors fill with ascii space (0x20) instead. 3243 */ 3244 static int 3245 bad_std_timing(u8 a, u8 b) 3246 { 3247 return (a == 0x00 && b == 0x00) || 3248 (a == 0x01 && b == 0x01) || 3249 (a == 0x20 && b == 0x20); 3250 } 3251 3252 static int drm_mode_hsync(const struct drm_display_mode *mode) 3253 { 3254 if (mode->htotal <= 0) 3255 return 0; 3256 3257 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal); 3258 } 3259 3260 static struct drm_display_mode * 3261 drm_gtf2_mode(struct drm_device *dev, 3262 const struct drm_edid *drm_edid, 3263 int hsize, int vsize, int vrefresh_rate) 3264 { 3265 struct drm_display_mode *mode; 3266 3267 /* 3268 * This is potentially wrong if there's ever a monitor with 3269 * more than one ranges section, each claiming a different 3270 * secondary GTF curve. Please don't do that. 3271 */ 3272 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 3273 if (!mode) 3274 return NULL; 3275 3276 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) { 3277 drm_mode_destroy(dev, mode); 3278 mode = drm_gtf_mode_complex(dev, hsize, vsize, 3279 vrefresh_rate, 0, 0, 3280 drm_gtf2_m(drm_edid), 3281 drm_gtf2_2c(drm_edid), 3282 drm_gtf2_k(drm_edid), 3283 drm_gtf2_2j(drm_edid)); 3284 } 3285 3286 return mode; 3287 } 3288 3289 /* 3290 * Take the standard timing params (in this case width, aspect, and refresh) 3291 * and convert them into a real mode using CVT/GTF/DMT. 3292 */ 3293 static struct drm_display_mode *drm_mode_std(struct drm_connector *connector, 3294 const struct drm_edid *drm_edid, 3295 const struct std_timing *t) 3296 { 3297 struct drm_device *dev = connector->dev; 3298 struct drm_display_mode *m, *mode = NULL; 3299 int hsize, vsize; 3300 int vrefresh_rate; 3301 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 3302 >> EDID_TIMING_ASPECT_SHIFT; 3303 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 3304 >> EDID_TIMING_VFREQ_SHIFT; 3305 int timing_level = standard_timing_level(drm_edid); 3306 3307 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 3308 return NULL; 3309 3310 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 3311 hsize = t->hsize * 8 + 248; 3312 /* vrefresh_rate = vfreq + 60 */ 3313 vrefresh_rate = vfreq + 60; 3314 /* the vdisplay is calculated based on the aspect ratio */ 3315 if (aspect_ratio == 0) { 3316 if (drm_edid->edid->revision < 3) 3317 vsize = hsize; 3318 else 3319 vsize = (hsize * 10) / 16; 3320 } else if (aspect_ratio == 1) 3321 vsize = (hsize * 3) / 4; 3322 else if (aspect_ratio == 2) 3323 vsize = (hsize * 4) / 5; 3324 else 3325 vsize = (hsize * 9) / 16; 3326 3327 /* HDTV hack, part 1 */ 3328 if (vrefresh_rate == 60 && 3329 ((hsize == 1360 && vsize == 765) || 3330 (hsize == 1368 && vsize == 769))) { 3331 hsize = 1366; 3332 vsize = 768; 3333 } 3334 3335 /* 3336 * If this connector already has a mode for this size and refresh 3337 * rate (because it came from detailed or CVT info), use that 3338 * instead. This way we don't have to guess at interlace or 3339 * reduced blanking. 3340 */ 3341 list_for_each_entry(m, &connector->probed_modes, head) 3342 if (m->hdisplay == hsize && m->vdisplay == vsize && 3343 drm_mode_vrefresh(m) == vrefresh_rate) 3344 return NULL; 3345 3346 /* HDTV hack, part 2 */ 3347 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 3348 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 3349 false); 3350 if (!mode) 3351 return NULL; 3352 mode->hdisplay = 1366; 3353 mode->hsync_start = mode->hsync_start - 1; 3354 mode->hsync_end = mode->hsync_end - 1; 3355 return mode; 3356 } 3357 3358 /* check whether it can be found in default mode table */ 3359 if (drm_monitor_supports_rb(drm_edid)) { 3360 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 3361 true); 3362 if (mode) 3363 return mode; 3364 } 3365 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 3366 if (mode) 3367 return mode; 3368 3369 /* okay, generate it */ 3370 switch (timing_level) { 3371 case LEVEL_DMT: 3372 break; 3373 case LEVEL_GTF: 3374 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 3375 break; 3376 case LEVEL_GTF2: 3377 mode = drm_gtf2_mode(dev, drm_edid, hsize, vsize, vrefresh_rate); 3378 break; 3379 case LEVEL_CVT: 3380 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 3381 false); 3382 break; 3383 } 3384 return mode; 3385 } 3386 3387 /* 3388 * EDID is delightfully ambiguous about how interlaced modes are to be 3389 * encoded. Our internal representation is of frame height, but some 3390 * HDTV detailed timings are encoded as field height. 3391 * 3392 * The format list here is from CEA, in frame size. Technically we 3393 * should be checking refresh rate too. Whatever. 3394 */ 3395 static void 3396 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 3397 const struct detailed_pixel_timing *pt) 3398 { 3399 int i; 3400 static const struct { 3401 int w, h; 3402 } cea_interlaced[] = { 3403 { 1920, 1080 }, 3404 { 720, 480 }, 3405 { 1440, 480 }, 3406 { 2880, 480 }, 3407 { 720, 576 }, 3408 { 1440, 576 }, 3409 { 2880, 576 }, 3410 }; 3411 3412 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 3413 return; 3414 3415 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 3416 if ((mode->hdisplay == cea_interlaced[i].w) && 3417 (mode->vdisplay == cea_interlaced[i].h / 2)) { 3418 mode->vdisplay *= 2; 3419 mode->vsync_start *= 2; 3420 mode->vsync_end *= 2; 3421 mode->vtotal *= 2; 3422 mode->vtotal |= 1; 3423 } 3424 } 3425 3426 mode->flags |= DRM_MODE_FLAG_INTERLACE; 3427 } 3428 3429 /* 3430 * Create a new mode from an EDID detailed timing section. An EDID detailed 3431 * timing block contains enough info for us to create and return a new struct 3432 * drm_display_mode. 3433 */ 3434 static struct drm_display_mode *drm_mode_detailed(struct drm_connector *connector, 3435 const struct drm_edid *drm_edid, 3436 const struct detailed_timing *timing) 3437 { 3438 const struct drm_display_info *info = &connector->display_info; 3439 struct drm_device *dev = connector->dev; 3440 struct drm_display_mode *mode; 3441 const struct detailed_pixel_timing *pt = &timing->data.pixel_data; 3442 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 3443 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 3444 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 3445 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 3446 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 3447 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 3448 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 3449 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 3450 3451 /* ignore tiny modes */ 3452 if (hactive < 64 || vactive < 64) 3453 return NULL; 3454 3455 if (pt->misc & DRM_EDID_PT_STEREO) { 3456 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Stereo mode not supported\n", 3457 connector->base.id, connector->name); 3458 return NULL; 3459 } 3460 3461 /* it is incorrect if hsync/vsync width is zero */ 3462 if (!hsync_pulse_width || !vsync_pulse_width) { 3463 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Incorrect Detailed timing. Wrong Hsync/Vsync pulse width\n", 3464 connector->base.id, connector->name); 3465 return NULL; 3466 } 3467 3468 if (info->quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 3469 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 3470 if (!mode) 3471 return NULL; 3472 3473 goto set_size; 3474 } 3475 3476 mode = drm_mode_create(dev); 3477 if (!mode) 3478 return NULL; 3479 3480 if (info->quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 3481 mode->clock = 1088 * 10; 3482 else 3483 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 3484 3485 mode->hdisplay = hactive; 3486 mode->hsync_start = mode->hdisplay + hsync_offset; 3487 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 3488 mode->htotal = mode->hdisplay + hblank; 3489 3490 mode->vdisplay = vactive; 3491 mode->vsync_start = mode->vdisplay + vsync_offset; 3492 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 3493 mode->vtotal = mode->vdisplay + vblank; 3494 3495 /* Some EDIDs have bogus h/vsync_end values */ 3496 if (mode->hsync_end > mode->htotal) { 3497 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing hsync_end %d->%d\n", 3498 connector->base.id, connector->name, 3499 mode->hsync_end, mode->htotal); 3500 mode->hsync_end = mode->htotal; 3501 } 3502 if (mode->vsync_end > mode->vtotal) { 3503 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing vsync_end %d->%d\n", 3504 connector->base.id, connector->name, 3505 mode->vsync_end, mode->vtotal); 3506 mode->vsync_end = mode->vtotal; 3507 } 3508 3509 drm_mode_do_interlace_quirk(mode, pt); 3510 3511 if (info->quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 3512 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC; 3513 } else { 3514 switch (pt->misc & DRM_EDID_PT_SYNC_MASK) { 3515 case DRM_EDID_PT_ANALOG_CSYNC: 3516 case DRM_EDID_PT_BIPOLAR_ANALOG_CSYNC: 3517 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Analog composite sync!\n", 3518 connector->base.id, connector->name); 3519 mode->flags |= DRM_MODE_FLAG_CSYNC | DRM_MODE_FLAG_NCSYNC; 3520 break; 3521 case DRM_EDID_PT_DIGITAL_CSYNC: 3522 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Digital composite sync!\n", 3523 connector->base.id, connector->name); 3524 mode->flags |= DRM_MODE_FLAG_CSYNC; 3525 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 3526 DRM_MODE_FLAG_PCSYNC : DRM_MODE_FLAG_NCSYNC; 3527 break; 3528 case DRM_EDID_PT_DIGITAL_SEPARATE_SYNC: 3529 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 3530 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 3531 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 3532 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 3533 break; 3534 } 3535 } 3536 3537 set_size: 3538 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 3539 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 3540 3541 if (info->quirks & EDID_QUIRK_DETAILED_IN_CM) { 3542 mode->width_mm *= 10; 3543 mode->height_mm *= 10; 3544 } 3545 3546 if (info->quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 3547 mode->width_mm = drm_edid->edid->width_cm * 10; 3548 mode->height_mm = drm_edid->edid->height_cm * 10; 3549 } 3550 3551 mode->type = DRM_MODE_TYPE_DRIVER; 3552 drm_mode_set_name(mode); 3553 3554 return mode; 3555 } 3556 3557 static bool 3558 mode_in_hsync_range(const struct drm_display_mode *mode, 3559 const struct edid *edid, const u8 *t) 3560 { 3561 int hsync, hmin, hmax; 3562 3563 hmin = t[7]; 3564 if (edid->revision >= 4) 3565 hmin += ((t[4] & 0x04) ? 255 : 0); 3566 hmax = t[8]; 3567 if (edid->revision >= 4) 3568 hmax += ((t[4] & 0x08) ? 255 : 0); 3569 hsync = drm_mode_hsync(mode); 3570 3571 return (hsync <= hmax && hsync >= hmin); 3572 } 3573 3574 static bool 3575 mode_in_vsync_range(const struct drm_display_mode *mode, 3576 const struct edid *edid, const u8 *t) 3577 { 3578 int vsync, vmin, vmax; 3579 3580 vmin = t[5]; 3581 if (edid->revision >= 4) 3582 vmin += ((t[4] & 0x01) ? 255 : 0); 3583 vmax = t[6]; 3584 if (edid->revision >= 4) 3585 vmax += ((t[4] & 0x02) ? 255 : 0); 3586 vsync = drm_mode_vrefresh(mode); 3587 3588 return (vsync <= vmax && vsync >= vmin); 3589 } 3590 3591 static u32 3592 range_pixel_clock(const struct edid *edid, const u8 *t) 3593 { 3594 /* unspecified */ 3595 if (t[9] == 0 || t[9] == 255) 3596 return 0; 3597 3598 /* 1.4 with CVT support gives us real precision, yay */ 3599 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG) 3600 return (t[9] * 10000) - ((t[12] >> 2) * 250); 3601 3602 /* 1.3 is pathetic, so fuzz up a bit */ 3603 return t[9] * 10000 + 5001; 3604 } 3605 3606 static bool mode_in_range(const struct drm_display_mode *mode, 3607 const struct drm_edid *drm_edid, 3608 const struct detailed_timing *timing) 3609 { 3610 const struct edid *edid = drm_edid->edid; 3611 u32 max_clock; 3612 const u8 *t = (const u8 *)timing; 3613 3614 if (!mode_in_hsync_range(mode, edid, t)) 3615 return false; 3616 3617 if (!mode_in_vsync_range(mode, edid, t)) 3618 return false; 3619 3620 if ((max_clock = range_pixel_clock(edid, t))) 3621 if (mode->clock > max_clock) 3622 return false; 3623 3624 /* 1.4 max horizontal check */ 3625 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG) 3626 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 3627 return false; 3628 3629 if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid)) 3630 return false; 3631 3632 return true; 3633 } 3634 3635 static bool valid_inferred_mode(const struct drm_connector *connector, 3636 const struct drm_display_mode *mode) 3637 { 3638 const struct drm_display_mode *m; 3639 bool ok = false; 3640 3641 list_for_each_entry(m, &connector->probed_modes, head) { 3642 if (mode->hdisplay == m->hdisplay && 3643 mode->vdisplay == m->vdisplay && 3644 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 3645 return false; /* duplicated */ 3646 if (mode->hdisplay <= m->hdisplay && 3647 mode->vdisplay <= m->vdisplay) 3648 ok = true; 3649 } 3650 return ok; 3651 } 3652 3653 static int drm_dmt_modes_for_range(struct drm_connector *connector, 3654 const struct drm_edid *drm_edid, 3655 const struct detailed_timing *timing) 3656 { 3657 int i, modes = 0; 3658 struct drm_display_mode *newmode; 3659 struct drm_device *dev = connector->dev; 3660 3661 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 3662 if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) && 3663 valid_inferred_mode(connector, drm_dmt_modes + i)) { 3664 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 3665 if (newmode) { 3666 drm_mode_probed_add(connector, newmode); 3667 modes++; 3668 } 3669 } 3670 } 3671 3672 return modes; 3673 } 3674 3675 /* fix up 1366x768 mode from 1368x768; 3676 * GFT/CVT can't express 1366 width which isn't dividable by 8 3677 */ 3678 void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 3679 { 3680 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 3681 mode->hdisplay = 1366; 3682 mode->hsync_start--; 3683 mode->hsync_end--; 3684 drm_mode_set_name(mode); 3685 } 3686 } 3687 3688 static int drm_gtf_modes_for_range(struct drm_connector *connector, 3689 const struct drm_edid *drm_edid, 3690 const struct detailed_timing *timing) 3691 { 3692 int i, modes = 0; 3693 struct drm_display_mode *newmode; 3694 struct drm_device *dev = connector->dev; 3695 3696 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3697 const struct minimode *m = &extra_modes[i]; 3698 3699 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 3700 if (!newmode) 3701 return modes; 3702 3703 drm_mode_fixup_1366x768(newmode); 3704 if (!mode_in_range(newmode, drm_edid, timing) || 3705 !valid_inferred_mode(connector, newmode)) { 3706 drm_mode_destroy(dev, newmode); 3707 continue; 3708 } 3709 3710 drm_mode_probed_add(connector, newmode); 3711 modes++; 3712 } 3713 3714 return modes; 3715 } 3716 3717 static int drm_gtf2_modes_for_range(struct drm_connector *connector, 3718 const struct drm_edid *drm_edid, 3719 const struct detailed_timing *timing) 3720 { 3721 int i, modes = 0; 3722 struct drm_display_mode *newmode; 3723 struct drm_device *dev = connector->dev; 3724 3725 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3726 const struct minimode *m = &extra_modes[i]; 3727 3728 newmode = drm_gtf2_mode(dev, drm_edid, m->w, m->h, m->r); 3729 if (!newmode) 3730 return modes; 3731 3732 drm_mode_fixup_1366x768(newmode); 3733 if (!mode_in_range(newmode, drm_edid, timing) || 3734 !valid_inferred_mode(connector, newmode)) { 3735 drm_mode_destroy(dev, newmode); 3736 continue; 3737 } 3738 3739 drm_mode_probed_add(connector, newmode); 3740 modes++; 3741 } 3742 3743 return modes; 3744 } 3745 3746 static int drm_cvt_modes_for_range(struct drm_connector *connector, 3747 const struct drm_edid *drm_edid, 3748 const struct detailed_timing *timing) 3749 { 3750 int i, modes = 0; 3751 struct drm_display_mode *newmode; 3752 struct drm_device *dev = connector->dev; 3753 bool rb = drm_monitor_supports_rb(drm_edid); 3754 3755 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3756 const struct minimode *m = &extra_modes[i]; 3757 3758 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 3759 if (!newmode) 3760 return modes; 3761 3762 drm_mode_fixup_1366x768(newmode); 3763 if (!mode_in_range(newmode, drm_edid, timing) || 3764 !valid_inferred_mode(connector, newmode)) { 3765 drm_mode_destroy(dev, newmode); 3766 continue; 3767 } 3768 3769 drm_mode_probed_add(connector, newmode); 3770 modes++; 3771 } 3772 3773 return modes; 3774 } 3775 3776 static void 3777 do_inferred_modes(const struct detailed_timing *timing, void *c) 3778 { 3779 struct detailed_mode_closure *closure = c; 3780 const struct detailed_non_pixel *data = &timing->data.other_data; 3781 const struct detailed_data_monitor_range *range = &data->data.range; 3782 3783 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE)) 3784 return; 3785 3786 closure->modes += drm_dmt_modes_for_range(closure->connector, 3787 closure->drm_edid, 3788 timing); 3789 3790 if (closure->drm_edid->edid->revision < 2) 3791 return; /* GTF not defined yet */ 3792 3793 switch (range->flags) { 3794 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG: 3795 closure->modes += drm_gtf2_modes_for_range(closure->connector, 3796 closure->drm_edid, 3797 timing); 3798 break; 3799 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG: 3800 closure->modes += drm_gtf_modes_for_range(closure->connector, 3801 closure->drm_edid, 3802 timing); 3803 break; 3804 case DRM_EDID_CVT_SUPPORT_FLAG: 3805 if (closure->drm_edid->edid->revision < 4) 3806 break; 3807 3808 closure->modes += drm_cvt_modes_for_range(closure->connector, 3809 closure->drm_edid, 3810 timing); 3811 break; 3812 case DRM_EDID_RANGE_LIMITS_ONLY_FLAG: 3813 default: 3814 break; 3815 } 3816 } 3817 3818 static int add_inferred_modes(struct drm_connector *connector, 3819 const struct drm_edid *drm_edid) 3820 { 3821 struct detailed_mode_closure closure = { 3822 .connector = connector, 3823 .drm_edid = drm_edid, 3824 }; 3825 3826 if (drm_edid->edid->revision >= 1) 3827 drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure); 3828 3829 return closure.modes; 3830 } 3831 3832 static int 3833 drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing) 3834 { 3835 int i, j, m, modes = 0; 3836 struct drm_display_mode *mode; 3837 const u8 *est = ((const u8 *)timing) + 6; 3838 3839 for (i = 0; i < 6; i++) { 3840 for (j = 7; j >= 0; j--) { 3841 m = (i * 8) + (7 - j); 3842 if (m >= ARRAY_SIZE(est3_modes)) 3843 break; 3844 if (est[i] & (1 << j)) { 3845 mode = drm_mode_find_dmt(connector->dev, 3846 est3_modes[m].w, 3847 est3_modes[m].h, 3848 est3_modes[m].r, 3849 est3_modes[m].rb); 3850 if (mode) { 3851 drm_mode_probed_add(connector, mode); 3852 modes++; 3853 } 3854 } 3855 } 3856 } 3857 3858 return modes; 3859 } 3860 3861 static void 3862 do_established_modes(const struct detailed_timing *timing, void *c) 3863 { 3864 struct detailed_mode_closure *closure = c; 3865 3866 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS)) 3867 return; 3868 3869 closure->modes += drm_est3_modes(closure->connector, timing); 3870 } 3871 3872 /* 3873 * Get established modes from EDID and add them. Each EDID block contains a 3874 * bitmap of the supported "established modes" list (defined above). Tease them 3875 * out and add them to the global modes list. 3876 */ 3877 static int add_established_modes(struct drm_connector *connector, 3878 const struct drm_edid *drm_edid) 3879 { 3880 struct drm_device *dev = connector->dev; 3881 const struct edid *edid = drm_edid->edid; 3882 unsigned long est_bits = edid->established_timings.t1 | 3883 (edid->established_timings.t2 << 8) | 3884 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 3885 int i, modes = 0; 3886 struct detailed_mode_closure closure = { 3887 .connector = connector, 3888 .drm_edid = drm_edid, 3889 }; 3890 3891 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 3892 if (est_bits & (1<<i)) { 3893 struct drm_display_mode *newmode; 3894 3895 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 3896 if (newmode) { 3897 drm_mode_probed_add(connector, newmode); 3898 modes++; 3899 } 3900 } 3901 } 3902 3903 if (edid->revision >= 1) 3904 drm_for_each_detailed_block(drm_edid, do_established_modes, 3905 &closure); 3906 3907 return modes + closure.modes; 3908 } 3909 3910 static void 3911 do_standard_modes(const struct detailed_timing *timing, void *c) 3912 { 3913 struct detailed_mode_closure *closure = c; 3914 const struct detailed_non_pixel *data = &timing->data.other_data; 3915 struct drm_connector *connector = closure->connector; 3916 int i; 3917 3918 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES)) 3919 return; 3920 3921 for (i = 0; i < 6; i++) { 3922 const struct std_timing *std = &data->data.timings[i]; 3923 struct drm_display_mode *newmode; 3924 3925 newmode = drm_mode_std(connector, closure->drm_edid, std); 3926 if (newmode) { 3927 drm_mode_probed_add(connector, newmode); 3928 closure->modes++; 3929 } 3930 } 3931 } 3932 3933 /* 3934 * Get standard modes from EDID and add them. Standard modes can be calculated 3935 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and 3936 * add them to the list. 3937 */ 3938 static int add_standard_modes(struct drm_connector *connector, 3939 const struct drm_edid *drm_edid) 3940 { 3941 int i, modes = 0; 3942 struct detailed_mode_closure closure = { 3943 .connector = connector, 3944 .drm_edid = drm_edid, 3945 }; 3946 3947 for (i = 0; i < EDID_STD_TIMINGS; i++) { 3948 struct drm_display_mode *newmode; 3949 3950 newmode = drm_mode_std(connector, drm_edid, 3951 &drm_edid->edid->standard_timings[i]); 3952 if (newmode) { 3953 drm_mode_probed_add(connector, newmode); 3954 modes++; 3955 } 3956 } 3957 3958 if (drm_edid->edid->revision >= 1) 3959 drm_for_each_detailed_block(drm_edid, do_standard_modes, 3960 &closure); 3961 3962 /* XXX should also look for standard codes in VTB blocks */ 3963 3964 return modes + closure.modes; 3965 } 3966 3967 static int drm_cvt_modes(struct drm_connector *connector, 3968 const struct detailed_timing *timing) 3969 { 3970 int i, j, modes = 0; 3971 struct drm_display_mode *newmode; 3972 struct drm_device *dev = connector->dev; 3973 const struct cvt_timing *cvt; 3974 static const int rates[] = { 60, 85, 75, 60, 50 }; 3975 const u8 empty[3] = { 0, 0, 0 }; 3976 3977 for (i = 0; i < 4; i++) { 3978 int width, height; 3979 3980 cvt = &(timing->data.other_data.data.cvt[i]); 3981 3982 if (!memcmp(cvt->code, empty, 3)) 3983 continue; 3984 3985 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 3986 switch (cvt->code[1] & 0x0c) { 3987 /* default - because compiler doesn't see that we've enumerated all cases */ 3988 default: 3989 case 0x00: 3990 width = height * 4 / 3; 3991 break; 3992 case 0x04: 3993 width = height * 16 / 9; 3994 break; 3995 case 0x08: 3996 width = height * 16 / 10; 3997 break; 3998 case 0x0c: 3999 width = height * 15 / 9; 4000 break; 4001 } 4002 4003 for (j = 1; j < 5; j++) { 4004 if (cvt->code[2] & (1 << j)) { 4005 newmode = drm_cvt_mode(dev, width, height, 4006 rates[j], j == 0, 4007 false, false); 4008 if (newmode) { 4009 drm_mode_probed_add(connector, newmode); 4010 modes++; 4011 } 4012 } 4013 } 4014 } 4015 4016 return modes; 4017 } 4018 4019 static void 4020 do_cvt_mode(const struct detailed_timing *timing, void *c) 4021 { 4022 struct detailed_mode_closure *closure = c; 4023 4024 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE)) 4025 return; 4026 4027 closure->modes += drm_cvt_modes(closure->connector, timing); 4028 } 4029 4030 static int 4031 add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid) 4032 { 4033 struct detailed_mode_closure closure = { 4034 .connector = connector, 4035 .drm_edid = drm_edid, 4036 }; 4037 4038 if (drm_edid->edid->revision >= 3) 4039 drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure); 4040 4041 /* XXX should also look for CVT codes in VTB blocks */ 4042 4043 return closure.modes; 4044 } 4045 4046 static void fixup_detailed_cea_mode_clock(struct drm_connector *connector, 4047 struct drm_display_mode *mode); 4048 4049 static void 4050 do_detailed_mode(const struct detailed_timing *timing, void *c) 4051 { 4052 struct detailed_mode_closure *closure = c; 4053 struct drm_display_mode *newmode; 4054 4055 if (!is_detailed_timing_descriptor(timing)) 4056 return; 4057 4058 newmode = drm_mode_detailed(closure->connector, 4059 closure->drm_edid, timing); 4060 if (!newmode) 4061 return; 4062 4063 if (closure->preferred) 4064 newmode->type |= DRM_MODE_TYPE_PREFERRED; 4065 4066 /* 4067 * Detailed modes are limited to 10kHz pixel clock resolution, 4068 * so fix up anything that looks like CEA/HDMI mode, but the clock 4069 * is just slightly off. 4070 */ 4071 fixup_detailed_cea_mode_clock(closure->connector, newmode); 4072 4073 drm_mode_probed_add(closure->connector, newmode); 4074 closure->modes++; 4075 closure->preferred = false; 4076 } 4077 4078 /* 4079 * add_detailed_modes - Add modes from detailed timings 4080 * @connector: attached connector 4081 * @drm_edid: EDID block to scan 4082 */ 4083 static int add_detailed_modes(struct drm_connector *connector, 4084 const struct drm_edid *drm_edid) 4085 { 4086 struct detailed_mode_closure closure = { 4087 .connector = connector, 4088 .drm_edid = drm_edid, 4089 }; 4090 4091 if (drm_edid->edid->revision >= 4) 4092 closure.preferred = true; /* first detailed timing is always preferred */ 4093 else 4094 closure.preferred = 4095 drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING; 4096 4097 drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure); 4098 4099 return closure.modes; 4100 } 4101 4102 /* CTA-861-H Table 60 - CTA Tag Codes */ 4103 #define CTA_DB_AUDIO 1 4104 #define CTA_DB_VIDEO 2 4105 #define CTA_DB_VENDOR 3 4106 #define CTA_DB_SPEAKER 4 4107 #define CTA_DB_EXTENDED_TAG 7 4108 4109 /* CTA-861-H Table 62 - CTA Extended Tag Codes */ 4110 #define CTA_EXT_DB_VIDEO_CAP 0 4111 #define CTA_EXT_DB_VENDOR 1 4112 #define CTA_EXT_DB_HDR_STATIC_METADATA 6 4113 #define CTA_EXT_DB_420_VIDEO_DATA 14 4114 #define CTA_EXT_DB_420_VIDEO_CAP_MAP 15 4115 #define CTA_EXT_DB_HF_EEODB 0x78 4116 #define CTA_EXT_DB_HF_SCDB 0x79 4117 4118 #define EDID_BASIC_AUDIO (1 << 6) 4119 #define EDID_CEA_YCRCB444 (1 << 5) 4120 #define EDID_CEA_YCRCB422 (1 << 4) 4121 #define EDID_CEA_VCDB_QS (1 << 6) 4122 4123 /* 4124 * Search EDID for CEA extension block. 4125 * 4126 * FIXME: Prefer not returning pointers to raw EDID data. 4127 */ 4128 const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid, 4129 int ext_id, int *ext_index) 4130 { 4131 const u8 *edid_ext = NULL; 4132 int i; 4133 4134 /* No EDID or EDID extensions */ 4135 if (!drm_edid || !drm_edid_extension_block_count(drm_edid)) 4136 return NULL; 4137 4138 /* Find CEA extension */ 4139 for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) { 4140 edid_ext = drm_edid_extension_block_data(drm_edid, i); 4141 if (edid_block_tag(edid_ext) == ext_id) 4142 break; 4143 } 4144 4145 if (i >= drm_edid_extension_block_count(drm_edid)) 4146 return NULL; 4147 4148 *ext_index = i + 1; 4149 4150 return edid_ext; 4151 } 4152 4153 /* Return true if the EDID has a CTA extension or a DisplayID CTA data block */ 4154 static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid) 4155 { 4156 const struct displayid_block *block; 4157 struct displayid_iter iter; 4158 int ext_index = 0; 4159 bool found = false; 4160 4161 /* Look for a top level CEA extension block */ 4162 if (drm_find_edid_extension(drm_edid, CEA_EXT, &ext_index)) 4163 return true; 4164 4165 /* CEA blocks can also be found embedded in a DisplayID block */ 4166 displayid_iter_edid_begin(drm_edid, &iter); 4167 displayid_iter_for_each(block, &iter) { 4168 if (block->tag == DATA_BLOCK_CTA) { 4169 found = true; 4170 break; 4171 } 4172 } 4173 displayid_iter_end(&iter); 4174 4175 return found; 4176 } 4177 4178 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic) 4179 { 4180 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127); 4181 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219); 4182 4183 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1)) 4184 return &edid_cea_modes_1[vic - 1]; 4185 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193)) 4186 return &edid_cea_modes_193[vic - 193]; 4187 return NULL; 4188 } 4189 4190 static u8 cea_num_vics(void) 4191 { 4192 return 193 + ARRAY_SIZE(edid_cea_modes_193); 4193 } 4194 4195 static u8 cea_next_vic(u8 vic) 4196 { 4197 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1)) 4198 vic = 193; 4199 return vic; 4200 } 4201 4202 /* 4203 * Calculate the alternate clock for the CEA mode 4204 * (60Hz vs. 59.94Hz etc.) 4205 */ 4206 static unsigned int 4207 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 4208 { 4209 unsigned int clock = cea_mode->clock; 4210 4211 if (drm_mode_vrefresh(cea_mode) % 6 != 0) 4212 return clock; 4213 4214 /* 4215 * edid_cea_modes contains the 59.94Hz 4216 * variant for 240 and 480 line modes, 4217 * and the 60Hz variant otherwise. 4218 */ 4219 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 4220 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 4221 else 4222 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 4223 4224 return clock; 4225 } 4226 4227 static bool 4228 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 4229 { 4230 /* 4231 * For certain VICs the spec allows the vertical 4232 * front porch to vary by one or two lines. 4233 * 4234 * cea_modes[] stores the variant with the shortest 4235 * vertical front porch. We can adjust the mode to 4236 * get the other variants by simply increasing the 4237 * vertical front porch length. 4238 */ 4239 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 || 4240 cea_mode_for_vic(9)->vtotal != 262 || 4241 cea_mode_for_vic(12)->vtotal != 262 || 4242 cea_mode_for_vic(13)->vtotal != 262 || 4243 cea_mode_for_vic(23)->vtotal != 312 || 4244 cea_mode_for_vic(24)->vtotal != 312 || 4245 cea_mode_for_vic(27)->vtotal != 312 || 4246 cea_mode_for_vic(28)->vtotal != 312); 4247 4248 if (((vic == 8 || vic == 9 || 4249 vic == 12 || vic == 13) && mode->vtotal < 263) || 4250 ((vic == 23 || vic == 24 || 4251 vic == 27 || vic == 28) && mode->vtotal < 314)) { 4252 mode->vsync_start++; 4253 mode->vsync_end++; 4254 mode->vtotal++; 4255 4256 return true; 4257 } 4258 4259 return false; 4260 } 4261 4262 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 4263 unsigned int clock_tolerance) 4264 { 4265 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4266 u8 vic; 4267 4268 if (!to_match->clock) 4269 return 0; 4270 4271 if (to_match->picture_aspect_ratio) 4272 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4273 4274 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 4275 struct drm_display_mode cea_mode; 4276 unsigned int clock1, clock2; 4277 4278 drm_mode_init(&cea_mode, cea_mode_for_vic(vic)); 4279 4280 /* Check both 60Hz and 59.94Hz */ 4281 clock1 = cea_mode.clock; 4282 clock2 = cea_mode_alternate_clock(&cea_mode); 4283 4284 if (abs(to_match->clock - clock1) > clock_tolerance && 4285 abs(to_match->clock - clock2) > clock_tolerance) 4286 continue; 4287 4288 do { 4289 if (drm_mode_match(to_match, &cea_mode, match_flags)) 4290 return vic; 4291 } while (cea_mode_alternate_timings(vic, &cea_mode)); 4292 } 4293 4294 return 0; 4295 } 4296 4297 /** 4298 * drm_match_cea_mode - look for a CEA mode matching given mode 4299 * @to_match: display mode 4300 * 4301 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 4302 * mode. 4303 */ 4304 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 4305 { 4306 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4307 u8 vic; 4308 4309 if (!to_match->clock) 4310 return 0; 4311 4312 if (to_match->picture_aspect_ratio) 4313 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4314 4315 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 4316 struct drm_display_mode cea_mode; 4317 unsigned int clock1, clock2; 4318 4319 drm_mode_init(&cea_mode, cea_mode_for_vic(vic)); 4320 4321 /* Check both 60Hz and 59.94Hz */ 4322 clock1 = cea_mode.clock; 4323 clock2 = cea_mode_alternate_clock(&cea_mode); 4324 4325 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 4326 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 4327 continue; 4328 4329 do { 4330 if (drm_mode_match(to_match, &cea_mode, match_flags)) 4331 return vic; 4332 } while (cea_mode_alternate_timings(vic, &cea_mode)); 4333 } 4334 4335 return 0; 4336 } 4337 EXPORT_SYMBOL(drm_match_cea_mode); 4338 4339 static bool drm_valid_cea_vic(u8 vic) 4340 { 4341 return cea_mode_for_vic(vic) != NULL; 4342 } 4343 4344 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 4345 { 4346 const struct drm_display_mode *mode = cea_mode_for_vic(video_code); 4347 4348 if (mode) 4349 return mode->picture_aspect_ratio; 4350 4351 return HDMI_PICTURE_ASPECT_NONE; 4352 } 4353 4354 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code) 4355 { 4356 return edid_4k_modes[video_code].picture_aspect_ratio; 4357 } 4358 4359 /* 4360 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 4361 * specific block). 4362 */ 4363 static unsigned int 4364 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 4365 { 4366 return cea_mode_alternate_clock(hdmi_mode); 4367 } 4368 4369 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 4370 unsigned int clock_tolerance) 4371 { 4372 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4373 u8 vic; 4374 4375 if (!to_match->clock) 4376 return 0; 4377 4378 if (to_match->picture_aspect_ratio) 4379 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4380 4381 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4382 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4383 unsigned int clock1, clock2; 4384 4385 /* Make sure to also match alternate clocks */ 4386 clock1 = hdmi_mode->clock; 4387 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4388 4389 if (abs(to_match->clock - clock1) > clock_tolerance && 4390 abs(to_match->clock - clock2) > clock_tolerance) 4391 continue; 4392 4393 if (drm_mode_match(to_match, hdmi_mode, match_flags)) 4394 return vic; 4395 } 4396 4397 return 0; 4398 } 4399 4400 /* 4401 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 4402 * @to_match: display mode 4403 * 4404 * An HDMI mode is one defined in the HDMI vendor specific block. 4405 * 4406 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 4407 */ 4408 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 4409 { 4410 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4411 u8 vic; 4412 4413 if (!to_match->clock) 4414 return 0; 4415 4416 if (to_match->picture_aspect_ratio) 4417 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4418 4419 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4420 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4421 unsigned int clock1, clock2; 4422 4423 /* Make sure to also match alternate clocks */ 4424 clock1 = hdmi_mode->clock; 4425 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4426 4427 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 4428 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 4429 drm_mode_match(to_match, hdmi_mode, match_flags)) 4430 return vic; 4431 } 4432 return 0; 4433 } 4434 4435 static bool drm_valid_hdmi_vic(u8 vic) 4436 { 4437 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 4438 } 4439 4440 static int add_alternate_cea_modes(struct drm_connector *connector, 4441 const struct drm_edid *drm_edid) 4442 { 4443 struct drm_device *dev = connector->dev; 4444 struct drm_display_mode *mode, *tmp; 4445 LIST_HEAD(list); 4446 int modes = 0; 4447 4448 /* Don't add CTA modes if the CTA extension block is missing */ 4449 if (!drm_edid_has_cta_extension(drm_edid)) 4450 return 0; 4451 4452 /* 4453 * Go through all probed modes and create a new mode 4454 * with the alternate clock for certain CEA modes. 4455 */ 4456 list_for_each_entry(mode, &connector->probed_modes, head) { 4457 const struct drm_display_mode *cea_mode = NULL; 4458 struct drm_display_mode *newmode; 4459 u8 vic = drm_match_cea_mode(mode); 4460 unsigned int clock1, clock2; 4461 4462 if (drm_valid_cea_vic(vic)) { 4463 cea_mode = cea_mode_for_vic(vic); 4464 clock2 = cea_mode_alternate_clock(cea_mode); 4465 } else { 4466 vic = drm_match_hdmi_mode(mode); 4467 if (drm_valid_hdmi_vic(vic)) { 4468 cea_mode = &edid_4k_modes[vic]; 4469 clock2 = hdmi_mode_alternate_clock(cea_mode); 4470 } 4471 } 4472 4473 if (!cea_mode) 4474 continue; 4475 4476 clock1 = cea_mode->clock; 4477 4478 if (clock1 == clock2) 4479 continue; 4480 4481 if (mode->clock != clock1 && mode->clock != clock2) 4482 continue; 4483 4484 newmode = drm_mode_duplicate(dev, cea_mode); 4485 if (!newmode) 4486 continue; 4487 4488 /* Carry over the stereo flags */ 4489 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 4490 4491 /* 4492 * The current mode could be either variant. Make 4493 * sure to pick the "other" clock for the new mode. 4494 */ 4495 if (mode->clock != clock1) 4496 newmode->clock = clock1; 4497 else 4498 newmode->clock = clock2; 4499 4500 list_add_tail(&newmode->head, &list); 4501 } 4502 4503 list_for_each_entry_safe(mode, tmp, &list, head) { 4504 list_del(&mode->head); 4505 drm_mode_probed_add(connector, mode); 4506 modes++; 4507 } 4508 4509 return modes; 4510 } 4511 4512 static u8 svd_to_vic(u8 svd) 4513 { 4514 /* 0-6 bit vic, 7th bit native mode indicator */ 4515 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 4516 return svd & 127; 4517 4518 return svd; 4519 } 4520 4521 /* 4522 * Return a display mode for the 0-based vic_index'th VIC across all CTA VDBs in 4523 * the EDID, or NULL on errors. 4524 */ 4525 static struct drm_display_mode * 4526 drm_display_mode_from_vic_index(struct drm_connector *connector, int vic_index) 4527 { 4528 const struct drm_display_info *info = &connector->display_info; 4529 struct drm_device *dev = connector->dev; 4530 4531 if (!info->vics || vic_index >= info->vics_len || !info->vics[vic_index]) 4532 return NULL; 4533 4534 return drm_display_mode_from_cea_vic(dev, info->vics[vic_index]); 4535 } 4536 4537 /* 4538 * do_y420vdb_modes - Parse YCBCR 420 only modes 4539 * @connector: connector corresponding to the HDMI sink 4540 * @svds: start of the data block of CEA YCBCR 420 VDB 4541 * @len: length of the CEA YCBCR 420 VDB 4542 * 4543 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 4544 * which contains modes which can be supported in YCBCR 420 4545 * output format only. 4546 */ 4547 static int do_y420vdb_modes(struct drm_connector *connector, 4548 const u8 *svds, u8 svds_len) 4549 { 4550 struct drm_device *dev = connector->dev; 4551 int modes = 0, i; 4552 4553 for (i = 0; i < svds_len; i++) { 4554 u8 vic = svd_to_vic(svds[i]); 4555 struct drm_display_mode *newmode; 4556 4557 if (!drm_valid_cea_vic(vic)) 4558 continue; 4559 4560 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 4561 if (!newmode) 4562 break; 4563 drm_mode_probed_add(connector, newmode); 4564 modes++; 4565 } 4566 4567 return modes; 4568 } 4569 4570 /** 4571 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC 4572 * @dev: DRM device 4573 * @video_code: CEA VIC of the mode 4574 * 4575 * Creates a new mode matching the specified CEA VIC. 4576 * 4577 * Returns: A new drm_display_mode on success or NULL on failure 4578 */ 4579 struct drm_display_mode * 4580 drm_display_mode_from_cea_vic(struct drm_device *dev, 4581 u8 video_code) 4582 { 4583 const struct drm_display_mode *cea_mode; 4584 struct drm_display_mode *newmode; 4585 4586 cea_mode = cea_mode_for_vic(video_code); 4587 if (!cea_mode) 4588 return NULL; 4589 4590 newmode = drm_mode_duplicate(dev, cea_mode); 4591 if (!newmode) 4592 return NULL; 4593 4594 return newmode; 4595 } 4596 EXPORT_SYMBOL(drm_display_mode_from_cea_vic); 4597 4598 /* Add modes based on VICs parsed in parse_cta_vdb() */ 4599 static int add_cta_vdb_modes(struct drm_connector *connector) 4600 { 4601 const struct drm_display_info *info = &connector->display_info; 4602 int i, modes = 0; 4603 4604 if (!info->vics) 4605 return 0; 4606 4607 for (i = 0; i < info->vics_len; i++) { 4608 struct drm_display_mode *mode; 4609 4610 mode = drm_display_mode_from_vic_index(connector, i); 4611 if (mode) { 4612 drm_mode_probed_add(connector, mode); 4613 modes++; 4614 } 4615 } 4616 4617 return modes; 4618 } 4619 4620 struct stereo_mandatory_mode { 4621 int width, height, vrefresh; 4622 unsigned int flags; 4623 }; 4624 4625 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 4626 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4627 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 4628 { 1920, 1080, 50, 4629 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 4630 { 1920, 1080, 60, 4631 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 4632 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4633 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 4634 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4635 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 4636 }; 4637 4638 static bool 4639 stereo_match_mandatory(const struct drm_display_mode *mode, 4640 const struct stereo_mandatory_mode *stereo_mode) 4641 { 4642 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 4643 4644 return mode->hdisplay == stereo_mode->width && 4645 mode->vdisplay == stereo_mode->height && 4646 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 4647 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 4648 } 4649 4650 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 4651 { 4652 struct drm_device *dev = connector->dev; 4653 const struct drm_display_mode *mode; 4654 struct list_head stereo_modes; 4655 int modes = 0, i; 4656 4657 INIT_LIST_HEAD(&stereo_modes); 4658 4659 list_for_each_entry(mode, &connector->probed_modes, head) { 4660 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 4661 const struct stereo_mandatory_mode *mandatory; 4662 struct drm_display_mode *new_mode; 4663 4664 if (!stereo_match_mandatory(mode, 4665 &stereo_mandatory_modes[i])) 4666 continue; 4667 4668 mandatory = &stereo_mandatory_modes[i]; 4669 new_mode = drm_mode_duplicate(dev, mode); 4670 if (!new_mode) 4671 continue; 4672 4673 new_mode->flags |= mandatory->flags; 4674 list_add_tail(&new_mode->head, &stereo_modes); 4675 modes++; 4676 } 4677 } 4678 4679 list_splice_tail(&stereo_modes, &connector->probed_modes); 4680 4681 return modes; 4682 } 4683 4684 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 4685 { 4686 struct drm_device *dev = connector->dev; 4687 struct drm_display_mode *newmode; 4688 4689 if (!drm_valid_hdmi_vic(vic)) { 4690 drm_err(connector->dev, "[CONNECTOR:%d:%s] Unknown HDMI VIC: %d\n", 4691 connector->base.id, connector->name, vic); 4692 return 0; 4693 } 4694 4695 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 4696 if (!newmode) 4697 return 0; 4698 4699 drm_mode_probed_add(connector, newmode); 4700 4701 return 1; 4702 } 4703 4704 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 4705 int vic_index) 4706 { 4707 struct drm_display_mode *newmode; 4708 int modes = 0; 4709 4710 if (structure & (1 << 0)) { 4711 newmode = drm_display_mode_from_vic_index(connector, vic_index); 4712 if (newmode) { 4713 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 4714 drm_mode_probed_add(connector, newmode); 4715 modes++; 4716 } 4717 } 4718 if (structure & (1 << 6)) { 4719 newmode = drm_display_mode_from_vic_index(connector, vic_index); 4720 if (newmode) { 4721 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 4722 drm_mode_probed_add(connector, newmode); 4723 modes++; 4724 } 4725 } 4726 if (structure & (1 << 8)) { 4727 newmode = drm_display_mode_from_vic_index(connector, vic_index); 4728 if (newmode) { 4729 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4730 drm_mode_probed_add(connector, newmode); 4731 modes++; 4732 } 4733 } 4734 4735 return modes; 4736 } 4737 4738 static bool hdmi_vsdb_latency_present(const u8 *db) 4739 { 4740 return db[8] & BIT(7); 4741 } 4742 4743 static bool hdmi_vsdb_i_latency_present(const u8 *db) 4744 { 4745 return hdmi_vsdb_latency_present(db) && db[8] & BIT(6); 4746 } 4747 4748 static int hdmi_vsdb_latency_length(const u8 *db) 4749 { 4750 if (hdmi_vsdb_i_latency_present(db)) 4751 return 4; 4752 else if (hdmi_vsdb_latency_present(db)) 4753 return 2; 4754 else 4755 return 0; 4756 } 4757 4758 /* 4759 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 4760 * @connector: connector corresponding to the HDMI sink 4761 * @db: start of the CEA vendor specific block 4762 * @len: length of the CEA block payload, ie. one can access up to db[len] 4763 * 4764 * Parses the HDMI VSDB looking for modes to add to @connector. This function 4765 * also adds the stereo 3d modes when applicable. 4766 */ 4767 static int 4768 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len) 4769 { 4770 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 4771 u8 vic_len, hdmi_3d_len = 0; 4772 u16 mask; 4773 u16 structure_all; 4774 4775 if (len < 8) 4776 goto out; 4777 4778 /* no HDMI_Video_Present */ 4779 if (!(db[8] & (1 << 5))) 4780 goto out; 4781 4782 offset += hdmi_vsdb_latency_length(db); 4783 4784 /* the declared length is not long enough for the 2 first bytes 4785 * of additional video format capabilities */ 4786 if (len < (8 + offset + 2)) 4787 goto out; 4788 4789 /* 3D_Present */ 4790 offset++; 4791 if (db[8 + offset] & (1 << 7)) { 4792 modes += add_hdmi_mandatory_stereo_modes(connector); 4793 4794 /* 3D_Multi_present */ 4795 multi_present = (db[8 + offset] & 0x60) >> 5; 4796 } 4797 4798 offset++; 4799 vic_len = db[8 + offset] >> 5; 4800 hdmi_3d_len = db[8 + offset] & 0x1f; 4801 4802 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 4803 u8 vic; 4804 4805 vic = db[9 + offset + i]; 4806 modes += add_hdmi_mode(connector, vic); 4807 } 4808 offset += 1 + vic_len; 4809 4810 if (multi_present == 1) 4811 multi_len = 2; 4812 else if (multi_present == 2) 4813 multi_len = 4; 4814 else 4815 multi_len = 0; 4816 4817 if (len < (8 + offset + hdmi_3d_len - 1)) 4818 goto out; 4819 4820 if (hdmi_3d_len < multi_len) 4821 goto out; 4822 4823 if (multi_present == 1 || multi_present == 2) { 4824 /* 3D_Structure_ALL */ 4825 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 4826 4827 /* check if 3D_MASK is present */ 4828 if (multi_present == 2) 4829 mask = (db[10 + offset] << 8) | db[11 + offset]; 4830 else 4831 mask = 0xffff; 4832 4833 for (i = 0; i < 16; i++) { 4834 if (mask & (1 << i)) 4835 modes += add_3d_struct_modes(connector, 4836 structure_all, i); 4837 } 4838 } 4839 4840 offset += multi_len; 4841 4842 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 4843 int vic_index; 4844 struct drm_display_mode *newmode = NULL; 4845 unsigned int newflag = 0; 4846 bool detail_present; 4847 4848 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 4849 4850 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 4851 break; 4852 4853 /* 2D_VIC_order_X */ 4854 vic_index = db[8 + offset + i] >> 4; 4855 4856 /* 3D_Structure_X */ 4857 switch (db[8 + offset + i] & 0x0f) { 4858 case 0: 4859 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 4860 break; 4861 case 6: 4862 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 4863 break; 4864 case 8: 4865 /* 3D_Detail_X */ 4866 if ((db[9 + offset + i] >> 4) == 1) 4867 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4868 break; 4869 } 4870 4871 if (newflag != 0) { 4872 newmode = drm_display_mode_from_vic_index(connector, 4873 vic_index); 4874 4875 if (newmode) { 4876 newmode->flags |= newflag; 4877 drm_mode_probed_add(connector, newmode); 4878 modes++; 4879 } 4880 } 4881 4882 if (detail_present) 4883 i++; 4884 } 4885 4886 out: 4887 return modes; 4888 } 4889 4890 static int 4891 cea_revision(const u8 *cea) 4892 { 4893 /* 4894 * FIXME is this correct for the DispID variant? 4895 * The DispID spec doesn't really specify whether 4896 * this is the revision of the CEA extension or 4897 * the DispID CEA data block. And the only value 4898 * given as an example is 0. 4899 */ 4900 return cea[1]; 4901 } 4902 4903 /* 4904 * CTA Data Block iterator. 4905 * 4906 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID 4907 * CTA Data Blocks. 4908 * 4909 * struct cea_db *db: 4910 * struct cea_db_iter iter; 4911 * 4912 * cea_db_iter_edid_begin(edid, &iter); 4913 * cea_db_iter_for_each(db, &iter) { 4914 * // do stuff with db 4915 * } 4916 * cea_db_iter_end(&iter); 4917 */ 4918 struct cea_db_iter { 4919 struct drm_edid_iter edid_iter; 4920 struct displayid_iter displayid_iter; 4921 4922 /* Current Data Block Collection. */ 4923 const u8 *collection; 4924 4925 /* Current Data Block index in current collection. */ 4926 int index; 4927 4928 /* End index in current collection. */ 4929 int end; 4930 }; 4931 4932 /* CTA-861-H section 7.4 CTA Data BLock Collection */ 4933 struct cea_db { 4934 u8 tag_length; 4935 u8 data[]; 4936 } __packed; 4937 4938 static int cea_db_tag(const struct cea_db *db) 4939 { 4940 return db->tag_length >> 5; 4941 } 4942 4943 static int cea_db_payload_len(const void *_db) 4944 { 4945 /* FIXME: Transition to passing struct cea_db * everywhere. */ 4946 const struct cea_db *db = _db; 4947 4948 return db->tag_length & 0x1f; 4949 } 4950 4951 static const void *cea_db_data(const struct cea_db *db) 4952 { 4953 return db->data; 4954 } 4955 4956 static bool cea_db_is_extended_tag(const struct cea_db *db, int tag) 4957 { 4958 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG && 4959 cea_db_payload_len(db) >= 1 && 4960 db->data[0] == tag; 4961 } 4962 4963 static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui) 4964 { 4965 const u8 *data = cea_db_data(db); 4966 4967 return cea_db_tag(db) == CTA_DB_VENDOR && 4968 cea_db_payload_len(db) >= 3 && 4969 oui(data[2], data[1], data[0]) == vendor_oui; 4970 } 4971 4972 static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid, 4973 struct cea_db_iter *iter) 4974 { 4975 memset(iter, 0, sizeof(*iter)); 4976 4977 drm_edid_iter_begin(drm_edid, &iter->edid_iter); 4978 displayid_iter_edid_begin(drm_edid, &iter->displayid_iter); 4979 } 4980 4981 static const struct cea_db * 4982 __cea_db_iter_current_block(const struct cea_db_iter *iter) 4983 { 4984 const struct cea_db *db; 4985 4986 if (!iter->collection) 4987 return NULL; 4988 4989 db = (const struct cea_db *)&iter->collection[iter->index]; 4990 4991 if (iter->index + sizeof(*db) <= iter->end && 4992 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end) 4993 return db; 4994 4995 return NULL; 4996 } 4997 4998 /* 4999 * References: 5000 * - CTA-861-H section 7.3.3 CTA Extension Version 3 5001 */ 5002 static int cea_db_collection_size(const u8 *cta) 5003 { 5004 u8 d = cta[2]; 5005 5006 if (d < 4 || d > 127) 5007 return 0; 5008 5009 return d - 4; 5010 } 5011 5012 /* 5013 * References: 5014 * - VESA E-EDID v1.4 5015 * - CTA-861-H section 7.3.3 CTA Extension Version 3 5016 */ 5017 static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter) 5018 { 5019 const u8 *ext; 5020 5021 drm_edid_iter_for_each(ext, &iter->edid_iter) { 5022 int size; 5023 5024 /* Only support CTA Extension revision 3+ */ 5025 if (ext[0] != CEA_EXT || cea_revision(ext) < 3) 5026 continue; 5027 5028 size = cea_db_collection_size(ext); 5029 if (!size) 5030 continue; 5031 5032 iter->index = 4; 5033 iter->end = iter->index + size; 5034 5035 return ext; 5036 } 5037 5038 return NULL; 5039 } 5040 5041 /* 5042 * References: 5043 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block 5044 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block 5045 * 5046 * Note that the above do not specify any connection between DisplayID Data 5047 * Block revision and CTA Extension versions. 5048 */ 5049 static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter) 5050 { 5051 const struct displayid_block *block; 5052 5053 displayid_iter_for_each(block, &iter->displayid_iter) { 5054 if (block->tag != DATA_BLOCK_CTA) 5055 continue; 5056 5057 /* 5058 * The displayid iterator has already verified the block bounds 5059 * in displayid_iter_block(). 5060 */ 5061 iter->index = sizeof(*block); 5062 iter->end = iter->index + block->num_bytes; 5063 5064 return block; 5065 } 5066 5067 return NULL; 5068 } 5069 5070 static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter) 5071 { 5072 const struct cea_db *db; 5073 5074 if (iter->collection) { 5075 /* Current collection should always be valid. */ 5076 db = __cea_db_iter_current_block(iter); 5077 if (WARN_ON(!db)) { 5078 iter->collection = NULL; 5079 return NULL; 5080 } 5081 5082 /* Next block in CTA Data Block Collection */ 5083 iter->index += sizeof(*db) + cea_db_payload_len(db); 5084 5085 db = __cea_db_iter_current_block(iter); 5086 if (db) 5087 return db; 5088 } 5089 5090 for (;;) { 5091 /* 5092 * Find the next CTA Data Block Collection. First iterate all 5093 * the EDID CTA Extensions, then all the DisplayID CTA blocks. 5094 * 5095 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID 5096 * Extension, it's recommended that DisplayID extensions are 5097 * exposed after all of the CTA Extensions. 5098 */ 5099 iter->collection = __cea_db_iter_edid_next(iter); 5100 if (!iter->collection) 5101 iter->collection = __cea_db_iter_displayid_next(iter); 5102 5103 if (!iter->collection) 5104 return NULL; 5105 5106 db = __cea_db_iter_current_block(iter); 5107 if (db) 5108 return db; 5109 } 5110 } 5111 5112 #define cea_db_iter_for_each(__db, __iter) \ 5113 while (((__db) = __cea_db_iter_next(__iter))) 5114 5115 static void cea_db_iter_end(struct cea_db_iter *iter) 5116 { 5117 displayid_iter_end(&iter->displayid_iter); 5118 drm_edid_iter_end(&iter->edid_iter); 5119 5120 memset(iter, 0, sizeof(*iter)); 5121 } 5122 5123 static bool cea_db_is_hdmi_vsdb(const struct cea_db *db) 5124 { 5125 return cea_db_is_vendor(db, HDMI_IEEE_OUI) && 5126 cea_db_payload_len(db) >= 5; 5127 } 5128 5129 static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db) 5130 { 5131 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) && 5132 cea_db_payload_len(db) >= 7; 5133 } 5134 5135 static bool cea_db_is_hdmi_forum_eeodb(const void *db) 5136 { 5137 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) && 5138 cea_db_payload_len(db) >= 2; 5139 } 5140 5141 static bool cea_db_is_microsoft_vsdb(const struct cea_db *db) 5142 { 5143 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) && 5144 cea_db_payload_len(db) == 21; 5145 } 5146 5147 static bool cea_db_is_vcdb(const struct cea_db *db) 5148 { 5149 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) && 5150 cea_db_payload_len(db) == 2; 5151 } 5152 5153 static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db) 5154 { 5155 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) && 5156 cea_db_payload_len(db) >= 7; 5157 } 5158 5159 static bool cea_db_is_y420cmdb(const struct cea_db *db) 5160 { 5161 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP); 5162 } 5163 5164 static bool cea_db_is_y420vdb(const struct cea_db *db) 5165 { 5166 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA); 5167 } 5168 5169 static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db) 5170 { 5171 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) && 5172 cea_db_payload_len(db) >= 3; 5173 } 5174 5175 /* 5176 * Get the HF-EEODB override extension block count from EDID. 5177 * 5178 * The passed in EDID may be partially read, as long as it has at least two 5179 * blocks (base block and one extension block) if EDID extension count is > 0. 5180 * 5181 * Note that this is *not* how you should parse CTA Data Blocks in general; this 5182 * is only to handle partially read EDIDs. Normally, use the CTA Data Block 5183 * iterators instead. 5184 * 5185 * References: 5186 * - HDMI 2.1 section 10.3.6 HDMI Forum EDID Extension Override Data Block 5187 */ 5188 static int edid_hfeeodb_extension_block_count(const struct edid *edid) 5189 { 5190 const u8 *cta; 5191 5192 /* No extensions according to base block, no HF-EEODB. */ 5193 if (!edid_extension_block_count(edid)) 5194 return 0; 5195 5196 /* HF-EEODB is always in the first EDID extension block only */ 5197 cta = edid_extension_block_data(edid, 0); 5198 if (edid_block_tag(cta) != CEA_EXT || cea_revision(cta) < 3) 5199 return 0; 5200 5201 /* Need to have the data block collection, and at least 3 bytes. */ 5202 if (cea_db_collection_size(cta) < 3) 5203 return 0; 5204 5205 /* 5206 * Sinks that include the HF-EEODB in their E-EDID shall include one and 5207 * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4 5208 * through 6 of Block 1 of the E-EDID. 5209 */ 5210 if (!cea_db_is_hdmi_forum_eeodb(&cta[4])) 5211 return 0; 5212 5213 return cta[4 + 2]; 5214 } 5215 5216 /* 5217 * CTA-861 YCbCr 4:2:0 Capability Map Data Block (CTA Y420CMDB) 5218 * 5219 * Y420CMDB contains a bitmap which gives the index of CTA modes from CTA VDB, 5220 * which can support YCBCR 420 sampling output also (apart from RGB/YCBCR444 5221 * etc). For example, if the bit 0 in bitmap is set, first mode in VDB can 5222 * support YCBCR420 output too. 5223 */ 5224 static void parse_cta_y420cmdb(struct drm_connector *connector, 5225 const struct cea_db *db, u64 *y420cmdb_map) 5226 { 5227 struct drm_display_info *info = &connector->display_info; 5228 int i, map_len = cea_db_payload_len(db) - 1; 5229 const u8 *data = cea_db_data(db) + 1; 5230 u64 map = 0; 5231 5232 if (map_len == 0) { 5233 /* All CEA modes support ycbcr420 sampling also.*/ 5234 map = U64_MAX; 5235 goto out; 5236 } 5237 5238 /* 5239 * This map indicates which of the existing CEA block modes 5240 * from VDB can support YCBCR420 output too. So if bit=0 is 5241 * set, first mode from VDB can support YCBCR420 output too. 5242 * We will parse and keep this map, before parsing VDB itself 5243 * to avoid going through the same block again and again. 5244 * 5245 * Spec is not clear about max possible size of this block. 5246 * Clamping max bitmap block size at 8 bytes. Every byte can 5247 * address 8 CEA modes, in this way this map can address 5248 * 8*8 = first 64 SVDs. 5249 */ 5250 if (WARN_ON_ONCE(map_len > 8)) 5251 map_len = 8; 5252 5253 for (i = 0; i < map_len; i++) 5254 map |= (u64)data[i] << (8 * i); 5255 5256 out: 5257 if (map) 5258 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; 5259 5260 *y420cmdb_map = map; 5261 } 5262 5263 static int add_cea_modes(struct drm_connector *connector, 5264 const struct drm_edid *drm_edid) 5265 { 5266 const struct cea_db *db; 5267 struct cea_db_iter iter; 5268 int modes; 5269 5270 /* CTA VDB block VICs parsed earlier */ 5271 modes = add_cta_vdb_modes(connector); 5272 5273 cea_db_iter_edid_begin(drm_edid, &iter); 5274 cea_db_iter_for_each(db, &iter) { 5275 if (cea_db_is_hdmi_vsdb(db)) { 5276 modes += do_hdmi_vsdb_modes(connector, (const u8 *)db, 5277 cea_db_payload_len(db)); 5278 } else if (cea_db_is_y420vdb(db)) { 5279 const u8 *vdb420 = cea_db_data(db) + 1; 5280 5281 /* Add 4:2:0(only) modes present in EDID */ 5282 modes += do_y420vdb_modes(connector, vdb420, 5283 cea_db_payload_len(db) - 1); 5284 } 5285 } 5286 cea_db_iter_end(&iter); 5287 5288 return modes; 5289 } 5290 5291 static void fixup_detailed_cea_mode_clock(struct drm_connector *connector, 5292 struct drm_display_mode *mode) 5293 { 5294 const struct drm_display_mode *cea_mode; 5295 int clock1, clock2, clock; 5296 u8 vic; 5297 const char *type; 5298 5299 /* 5300 * allow 5kHz clock difference either way to account for 5301 * the 10kHz clock resolution limit of detailed timings. 5302 */ 5303 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 5304 if (drm_valid_cea_vic(vic)) { 5305 type = "CEA"; 5306 cea_mode = cea_mode_for_vic(vic); 5307 clock1 = cea_mode->clock; 5308 clock2 = cea_mode_alternate_clock(cea_mode); 5309 } else { 5310 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 5311 if (drm_valid_hdmi_vic(vic)) { 5312 type = "HDMI"; 5313 cea_mode = &edid_4k_modes[vic]; 5314 clock1 = cea_mode->clock; 5315 clock2 = hdmi_mode_alternate_clock(cea_mode); 5316 } else { 5317 return; 5318 } 5319 } 5320 5321 /* pick whichever is closest */ 5322 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 5323 clock = clock1; 5324 else 5325 clock = clock2; 5326 5327 if (mode->clock == clock) 5328 return; 5329 5330 drm_dbg_kms(connector->dev, 5331 "[CONNECTOR:%d:%s] detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 5332 connector->base.id, connector->name, 5333 type, vic, mode->clock, clock); 5334 mode->clock = clock; 5335 } 5336 5337 static void drm_calculate_luminance_range(struct drm_connector *connector) 5338 { 5339 struct hdr_static_metadata *hdr_metadata = &connector->hdr_sink_metadata.hdmi_type1; 5340 struct drm_luminance_range_info *luminance_range = 5341 &connector->display_info.luminance_range; 5342 static const u8 pre_computed_values[] = { 5343 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69, 5344 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98 5345 }; 5346 u32 max_avg, min_cll, max, min, q, r; 5347 5348 if (!(hdr_metadata->metadata_type & BIT(HDMI_STATIC_METADATA_TYPE1))) 5349 return; 5350 5351 max_avg = hdr_metadata->max_fall; 5352 min_cll = hdr_metadata->min_cll; 5353 5354 /* 5355 * From the specification (CTA-861-G), for calculating the maximum 5356 * luminance we need to use: 5357 * Luminance = 50*2**(CV/32) 5358 * Where CV is a one-byte value. 5359 * For calculating this expression we may need float point precision; 5360 * to avoid this complexity level, we take advantage that CV is divided 5361 * by a constant. From the Euclids division algorithm, we know that CV 5362 * can be written as: CV = 32*q + r. Next, we replace CV in the 5363 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just 5364 * need to pre-compute the value of r/32. For pre-computing the values 5365 * We just used the following Ruby line: 5366 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round} 5367 * The results of the above expressions can be verified at 5368 * pre_computed_values. 5369 */ 5370 q = max_avg >> 5; 5371 r = max_avg % 32; 5372 max = (1 << q) * pre_computed_values[r]; 5373 5374 /* min luminance: maxLum * (CV/255)^2 / 100 */ 5375 q = DIV_ROUND_CLOSEST(min_cll, 255); 5376 min = max * DIV_ROUND_CLOSEST((q * q), 100); 5377 5378 luminance_range->min_luminance = min; 5379 luminance_range->max_luminance = max; 5380 } 5381 5382 static uint8_t eotf_supported(const u8 *edid_ext) 5383 { 5384 return edid_ext[2] & 5385 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) | 5386 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) | 5387 BIT(HDMI_EOTF_SMPTE_ST2084) | 5388 BIT(HDMI_EOTF_BT_2100_HLG)); 5389 } 5390 5391 static uint8_t hdr_metadata_type(const u8 *edid_ext) 5392 { 5393 return edid_ext[3] & 5394 BIT(HDMI_STATIC_METADATA_TYPE1); 5395 } 5396 5397 static void 5398 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db) 5399 { 5400 u16 len; 5401 5402 len = cea_db_payload_len(db); 5403 5404 connector->hdr_sink_metadata.hdmi_type1.eotf = 5405 eotf_supported(db); 5406 connector->hdr_sink_metadata.hdmi_type1.metadata_type = 5407 hdr_metadata_type(db); 5408 5409 if (len >= 4) 5410 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4]; 5411 if (len >= 5) 5412 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5]; 5413 if (len >= 6) { 5414 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6]; 5415 5416 /* Calculate only when all values are available */ 5417 drm_calculate_luminance_range(connector); 5418 } 5419 } 5420 5421 /* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */ 5422 static void 5423 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 5424 { 5425 u8 len = cea_db_payload_len(db); 5426 5427 if (len >= 6 && (db[6] & (1 << 7))) 5428 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI; 5429 5430 if (len >= 10 && hdmi_vsdb_latency_present(db)) { 5431 connector->latency_present[0] = true; 5432 connector->video_latency[0] = db[9]; 5433 connector->audio_latency[0] = db[10]; 5434 } 5435 5436 if (len >= 12 && hdmi_vsdb_i_latency_present(db)) { 5437 connector->latency_present[1] = true; 5438 connector->video_latency[1] = db[11]; 5439 connector->audio_latency[1] = db[12]; 5440 } 5441 5442 drm_dbg_kms(connector->dev, 5443 "[CONNECTOR:%d:%s] HDMI: latency present %d %d, video latency %d %d, audio latency %d %d\n", 5444 connector->base.id, connector->name, 5445 connector->latency_present[0], connector->latency_present[1], 5446 connector->video_latency[0], connector->video_latency[1], 5447 connector->audio_latency[0], connector->audio_latency[1]); 5448 } 5449 5450 static void 5451 monitor_name(const struct detailed_timing *timing, void *data) 5452 { 5453 const char **res = data; 5454 5455 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME)) 5456 return; 5457 5458 *res = timing->data.other_data.data.str.str; 5459 } 5460 5461 static int get_monitor_name(const struct drm_edid *drm_edid, char name[13]) 5462 { 5463 const char *edid_name = NULL; 5464 int mnl; 5465 5466 if (!drm_edid || !name) 5467 return 0; 5468 5469 drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name); 5470 for (mnl = 0; edid_name && mnl < 13; mnl++) { 5471 if (edid_name[mnl] == 0x0a) 5472 break; 5473 5474 name[mnl] = edid_name[mnl]; 5475 } 5476 5477 return mnl; 5478 } 5479 5480 /** 5481 * drm_edid_get_monitor_name - fetch the monitor name from the edid 5482 * @edid: monitor EDID information 5483 * @name: pointer to a character array to hold the name of the monitor 5484 * @bufsize: The size of the name buffer (should be at least 14 chars.) 5485 * 5486 */ 5487 void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize) 5488 { 5489 int name_length = 0; 5490 5491 if (bufsize <= 0) 5492 return; 5493 5494 if (edid) { 5495 char buf[13]; 5496 struct drm_edid drm_edid = { 5497 .edid = edid, 5498 .size = edid_size(edid), 5499 }; 5500 5501 name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1); 5502 memcpy(name, buf, name_length); 5503 } 5504 5505 name[name_length] = '\0'; 5506 } 5507 EXPORT_SYMBOL(drm_edid_get_monitor_name); 5508 5509 static void clear_eld(struct drm_connector *connector) 5510 { 5511 memset(connector->eld, 0, sizeof(connector->eld)); 5512 5513 connector->latency_present[0] = false; 5514 connector->latency_present[1] = false; 5515 connector->video_latency[0] = 0; 5516 connector->audio_latency[0] = 0; 5517 connector->video_latency[1] = 0; 5518 connector->audio_latency[1] = 0; 5519 } 5520 5521 /* 5522 * drm_edid_to_eld - build ELD from EDID 5523 * @connector: connector corresponding to the HDMI/DP sink 5524 * @drm_edid: EDID to parse 5525 * 5526 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 5527 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 5528 */ 5529 static void drm_edid_to_eld(struct drm_connector *connector, 5530 const struct drm_edid *drm_edid) 5531 { 5532 const struct drm_display_info *info = &connector->display_info; 5533 const struct cea_db *db; 5534 struct cea_db_iter iter; 5535 uint8_t *eld = connector->eld; 5536 int total_sad_count = 0; 5537 int mnl; 5538 5539 if (!drm_edid) 5540 return; 5541 5542 mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]); 5543 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD monitor %s\n", 5544 connector->base.id, connector->name, 5545 &eld[DRM_ELD_MONITOR_NAME_STRING]); 5546 5547 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT; 5548 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl; 5549 5550 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D; 5551 5552 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0]; 5553 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1]; 5554 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0]; 5555 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1]; 5556 5557 cea_db_iter_edid_begin(drm_edid, &iter); 5558 cea_db_iter_for_each(db, &iter) { 5559 const u8 *data = cea_db_data(db); 5560 int len = cea_db_payload_len(db); 5561 int sad_count; 5562 5563 switch (cea_db_tag(db)) { 5564 case CTA_DB_AUDIO: 5565 /* Audio Data Block, contains SADs */ 5566 sad_count = min(len / 3, 15 - total_sad_count); 5567 if (sad_count >= 1) 5568 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)], 5569 data, sad_count * 3); 5570 total_sad_count += sad_count; 5571 break; 5572 case CTA_DB_SPEAKER: 5573 /* Speaker Allocation Data Block */ 5574 if (len >= 1) 5575 eld[DRM_ELD_SPEAKER] = data[0]; 5576 break; 5577 case CTA_DB_VENDOR: 5578 /* HDMI Vendor-Specific Data Block */ 5579 if (cea_db_is_hdmi_vsdb(db)) 5580 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db); 5581 break; 5582 default: 5583 break; 5584 } 5585 } 5586 cea_db_iter_end(&iter); 5587 5588 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT; 5589 5590 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 5591 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 5592 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 5593 else 5594 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 5595 5596 eld[DRM_ELD_BASELINE_ELD_LEN] = 5597 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 5598 5599 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD size %d, SAD count %d\n", 5600 connector->base.id, connector->name, 5601 drm_eld_size(eld), total_sad_count); 5602 } 5603 5604 static int _drm_edid_to_sad(const struct drm_edid *drm_edid, 5605 struct cea_sad **sads) 5606 { 5607 const struct cea_db *db; 5608 struct cea_db_iter iter; 5609 int count = 0; 5610 5611 cea_db_iter_edid_begin(drm_edid, &iter); 5612 cea_db_iter_for_each(db, &iter) { 5613 if (cea_db_tag(db) == CTA_DB_AUDIO) { 5614 int j; 5615 5616 count = cea_db_payload_len(db) / 3; /* SAD is 3B */ 5617 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 5618 if (!*sads) 5619 return -ENOMEM; 5620 for (j = 0; j < count; j++) { 5621 const u8 *sad = &db->data[j * 3]; 5622 5623 (*sads)[j].format = (sad[0] & 0x78) >> 3; 5624 (*sads)[j].channels = sad[0] & 0x7; 5625 (*sads)[j].freq = sad[1] & 0x7F; 5626 (*sads)[j].byte2 = sad[2]; 5627 } 5628 break; 5629 } 5630 } 5631 cea_db_iter_end(&iter); 5632 5633 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count); 5634 5635 return count; 5636 } 5637 5638 /** 5639 * drm_edid_to_sad - extracts SADs from EDID 5640 * @edid: EDID to parse 5641 * @sads: pointer that will be set to the extracted SADs 5642 * 5643 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 5644 * 5645 * Note: The returned pointer needs to be freed using kfree(). 5646 * 5647 * Return: The number of found SADs or negative number on error. 5648 */ 5649 int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads) 5650 { 5651 struct drm_edid drm_edid; 5652 5653 return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads); 5654 } 5655 EXPORT_SYMBOL(drm_edid_to_sad); 5656 5657 static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid, 5658 u8 **sadb) 5659 { 5660 const struct cea_db *db; 5661 struct cea_db_iter iter; 5662 int count = 0; 5663 5664 cea_db_iter_edid_begin(drm_edid, &iter); 5665 cea_db_iter_for_each(db, &iter) { 5666 if (cea_db_tag(db) == CTA_DB_SPEAKER && 5667 cea_db_payload_len(db) == 3) { 5668 *sadb = kmemdup(db->data, cea_db_payload_len(db), 5669 GFP_KERNEL); 5670 if (!*sadb) 5671 return -ENOMEM; 5672 count = cea_db_payload_len(db); 5673 break; 5674 } 5675 } 5676 cea_db_iter_end(&iter); 5677 5678 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count); 5679 5680 return count; 5681 } 5682 5683 /** 5684 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 5685 * @edid: EDID to parse 5686 * @sadb: pointer to the speaker block 5687 * 5688 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 5689 * 5690 * Note: The returned pointer needs to be freed using kfree(). 5691 * 5692 * Return: The number of found Speaker Allocation Blocks or negative number on 5693 * error. 5694 */ 5695 int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb) 5696 { 5697 struct drm_edid drm_edid; 5698 5699 return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid), 5700 sadb); 5701 } 5702 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 5703 5704 /** 5705 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 5706 * @connector: connector associated with the HDMI/DP sink 5707 * @mode: the display mode 5708 * 5709 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 5710 * the sink doesn't support audio or video. 5711 */ 5712 int drm_av_sync_delay(struct drm_connector *connector, 5713 const struct drm_display_mode *mode) 5714 { 5715 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 5716 int a, v; 5717 5718 if (!connector->latency_present[0]) 5719 return 0; 5720 if (!connector->latency_present[1]) 5721 i = 0; 5722 5723 a = connector->audio_latency[i]; 5724 v = connector->video_latency[i]; 5725 5726 /* 5727 * HDMI/DP sink doesn't support audio or video? 5728 */ 5729 if (a == 255 || v == 255) 5730 return 0; 5731 5732 /* 5733 * Convert raw EDID values to millisecond. 5734 * Treat unknown latency as 0ms. 5735 */ 5736 if (a) 5737 a = min(2 * (a - 1), 500); 5738 if (v) 5739 v = min(2 * (v - 1), 500); 5740 5741 return max(v - a, 0); 5742 } 5743 EXPORT_SYMBOL(drm_av_sync_delay); 5744 5745 static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid) 5746 { 5747 const struct cea_db *db; 5748 struct cea_db_iter iter; 5749 bool hdmi = false; 5750 5751 /* 5752 * Because HDMI identifier is in Vendor Specific Block, 5753 * search it from all data blocks of CEA extension. 5754 */ 5755 cea_db_iter_edid_begin(drm_edid, &iter); 5756 cea_db_iter_for_each(db, &iter) { 5757 if (cea_db_is_hdmi_vsdb(db)) { 5758 hdmi = true; 5759 break; 5760 } 5761 } 5762 cea_db_iter_end(&iter); 5763 5764 return hdmi; 5765 } 5766 5767 /** 5768 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 5769 * @edid: monitor EDID information 5770 * 5771 * Parse the CEA extension according to CEA-861-B. 5772 * 5773 * Drivers that have added the modes parsed from EDID to drm_display_info 5774 * should use &drm_display_info.is_hdmi instead of calling this function. 5775 * 5776 * Return: True if the monitor is HDMI, false if not or unknown. 5777 */ 5778 bool drm_detect_hdmi_monitor(const struct edid *edid) 5779 { 5780 struct drm_edid drm_edid; 5781 5782 return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid)); 5783 } 5784 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 5785 5786 static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid) 5787 { 5788 struct drm_edid_iter edid_iter; 5789 const struct cea_db *db; 5790 struct cea_db_iter iter; 5791 const u8 *edid_ext; 5792 bool has_audio = false; 5793 5794 drm_edid_iter_begin(drm_edid, &edid_iter); 5795 drm_edid_iter_for_each(edid_ext, &edid_iter) { 5796 if (edid_ext[0] == CEA_EXT) { 5797 has_audio = edid_ext[3] & EDID_BASIC_AUDIO; 5798 if (has_audio) 5799 break; 5800 } 5801 } 5802 drm_edid_iter_end(&edid_iter); 5803 5804 if (has_audio) { 5805 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 5806 goto end; 5807 } 5808 5809 cea_db_iter_edid_begin(drm_edid, &iter); 5810 cea_db_iter_for_each(db, &iter) { 5811 if (cea_db_tag(db) == CTA_DB_AUDIO) { 5812 const u8 *data = cea_db_data(db); 5813 int i; 5814 5815 for (i = 0; i < cea_db_payload_len(db); i += 3) 5816 DRM_DEBUG_KMS("CEA audio format %d\n", 5817 (data[i] >> 3) & 0xf); 5818 has_audio = true; 5819 break; 5820 } 5821 } 5822 cea_db_iter_end(&iter); 5823 5824 end: 5825 return has_audio; 5826 } 5827 5828 /** 5829 * drm_detect_monitor_audio - check monitor audio capability 5830 * @edid: EDID block to scan 5831 * 5832 * Monitor should have CEA extension block. 5833 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 5834 * audio' only. If there is any audio extension block and supported 5835 * audio format, assume at least 'basic audio' support, even if 'basic 5836 * audio' is not defined in EDID. 5837 * 5838 * Return: True if the monitor supports audio, false otherwise. 5839 */ 5840 bool drm_detect_monitor_audio(const struct edid *edid) 5841 { 5842 struct drm_edid drm_edid; 5843 5844 return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid)); 5845 } 5846 EXPORT_SYMBOL(drm_detect_monitor_audio); 5847 5848 5849 /** 5850 * drm_default_rgb_quant_range - default RGB quantization range 5851 * @mode: display mode 5852 * 5853 * Determine the default RGB quantization range for the mode, 5854 * as specified in CEA-861. 5855 * 5856 * Return: The default RGB quantization range for the mode 5857 */ 5858 enum hdmi_quantization_range 5859 drm_default_rgb_quant_range(const struct drm_display_mode *mode) 5860 { 5861 /* All CEA modes other than VIC 1 use limited quantization range. */ 5862 return drm_match_cea_mode(mode) > 1 ? 5863 HDMI_QUANTIZATION_RANGE_LIMITED : 5864 HDMI_QUANTIZATION_RANGE_FULL; 5865 } 5866 EXPORT_SYMBOL(drm_default_rgb_quant_range); 5867 5868 /* CTA-861 Video Data Block (CTA VDB) */ 5869 static void parse_cta_vdb(struct drm_connector *connector, const struct cea_db *db) 5870 { 5871 struct drm_display_info *info = &connector->display_info; 5872 int i, vic_index, len = cea_db_payload_len(db); 5873 const u8 *svds = cea_db_data(db); 5874 u8 *vics; 5875 5876 if (!len) 5877 return; 5878 5879 /* Gracefully handle multiple VDBs, however unlikely that is */ 5880 vics = krealloc(info->vics, info->vics_len + len, GFP_KERNEL); 5881 if (!vics) 5882 return; 5883 5884 vic_index = info->vics_len; 5885 info->vics_len += len; 5886 info->vics = vics; 5887 5888 for (i = 0; i < len; i++) { 5889 u8 vic = svd_to_vic(svds[i]); 5890 5891 if (!drm_valid_cea_vic(vic)) 5892 vic = 0; 5893 5894 info->vics[vic_index++] = vic; 5895 } 5896 } 5897 5898 /* 5899 * Update y420_cmdb_modes based on previously parsed CTA VDB and Y420CMDB. 5900 * 5901 * Translate the y420cmdb_map based on VIC indexes to y420_cmdb_modes indexed 5902 * using the VICs themselves. 5903 */ 5904 static void update_cta_y420cmdb(struct drm_connector *connector, u64 y420cmdb_map) 5905 { 5906 struct drm_display_info *info = &connector->display_info; 5907 struct drm_hdmi_info *hdmi = &info->hdmi; 5908 int i, len = min_t(int, info->vics_len, BITS_PER_TYPE(y420cmdb_map)); 5909 5910 for (i = 0; i < len; i++) { 5911 u8 vic = info->vics[i]; 5912 5913 if (vic && y420cmdb_map & BIT_ULL(i)) 5914 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 5915 } 5916 } 5917 5918 static bool cta_vdb_has_vic(const struct drm_connector *connector, u8 vic) 5919 { 5920 const struct drm_display_info *info = &connector->display_info; 5921 int i; 5922 5923 if (!vic || !info->vics) 5924 return false; 5925 5926 for (i = 0; i < info->vics_len; i++) { 5927 if (info->vics[i] == vic) 5928 return true; 5929 } 5930 5931 return false; 5932 } 5933 5934 /* CTA-861-H YCbCr 4:2:0 Video Data Block (CTA Y420VDB) */ 5935 static void parse_cta_y420vdb(struct drm_connector *connector, 5936 const struct cea_db *db) 5937 { 5938 struct drm_display_info *info = &connector->display_info; 5939 struct drm_hdmi_info *hdmi = &info->hdmi; 5940 const u8 *svds = cea_db_data(db) + 1; 5941 int i; 5942 5943 for (i = 0; i < cea_db_payload_len(db) - 1; i++) { 5944 u8 vic = svd_to_vic(svds[i]); 5945 5946 if (!drm_valid_cea_vic(vic)) 5947 continue; 5948 5949 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 5950 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; 5951 } 5952 } 5953 5954 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db) 5955 { 5956 struct drm_display_info *info = &connector->display_info; 5957 5958 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] CEA VCDB 0x%02x\n", 5959 connector->base.id, connector->name, db[2]); 5960 5961 if (db[2] & EDID_CEA_VCDB_QS) 5962 info->rgb_quant_range_selectable = true; 5963 } 5964 5965 static 5966 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane) 5967 { 5968 switch (max_frl_rate) { 5969 case 1: 5970 *max_lanes = 3; 5971 *max_rate_per_lane = 3; 5972 break; 5973 case 2: 5974 *max_lanes = 3; 5975 *max_rate_per_lane = 6; 5976 break; 5977 case 3: 5978 *max_lanes = 4; 5979 *max_rate_per_lane = 6; 5980 break; 5981 case 4: 5982 *max_lanes = 4; 5983 *max_rate_per_lane = 8; 5984 break; 5985 case 5: 5986 *max_lanes = 4; 5987 *max_rate_per_lane = 10; 5988 break; 5989 case 6: 5990 *max_lanes = 4; 5991 *max_rate_per_lane = 12; 5992 break; 5993 case 0: 5994 default: 5995 *max_lanes = 0; 5996 *max_rate_per_lane = 0; 5997 } 5998 } 5999 6000 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 6001 const u8 *db) 6002 { 6003 u8 dc_mask; 6004 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 6005 6006 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 6007 hdmi->y420_dc_modes = dc_mask; 6008 } 6009 6010 static void drm_parse_dsc_info(struct drm_hdmi_dsc_cap *hdmi_dsc, 6011 const u8 *hf_scds) 6012 { 6013 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2; 6014 6015 if (!hdmi_dsc->v_1p2) 6016 return; 6017 6018 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420; 6019 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP; 6020 6021 if (hf_scds[11] & DRM_EDID_DSC_16BPC) 6022 hdmi_dsc->bpc_supported = 16; 6023 else if (hf_scds[11] & DRM_EDID_DSC_12BPC) 6024 hdmi_dsc->bpc_supported = 12; 6025 else if (hf_scds[11] & DRM_EDID_DSC_10BPC) 6026 hdmi_dsc->bpc_supported = 10; 6027 else 6028 /* Supports min 8 BPC if DSC 1.2 is supported*/ 6029 hdmi_dsc->bpc_supported = 8; 6030 6031 if (cea_db_payload_len(hf_scds) >= 12 && hf_scds[12]) { 6032 u8 dsc_max_slices; 6033 u8 dsc_max_frl_rate; 6034 6035 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4; 6036 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes, 6037 &hdmi_dsc->max_frl_rate_per_lane); 6038 6039 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES; 6040 6041 switch (dsc_max_slices) { 6042 case 1: 6043 hdmi_dsc->max_slices = 1; 6044 hdmi_dsc->clk_per_slice = 340; 6045 break; 6046 case 2: 6047 hdmi_dsc->max_slices = 2; 6048 hdmi_dsc->clk_per_slice = 340; 6049 break; 6050 case 3: 6051 hdmi_dsc->max_slices = 4; 6052 hdmi_dsc->clk_per_slice = 340; 6053 break; 6054 case 4: 6055 hdmi_dsc->max_slices = 8; 6056 hdmi_dsc->clk_per_slice = 340; 6057 break; 6058 case 5: 6059 hdmi_dsc->max_slices = 8; 6060 hdmi_dsc->clk_per_slice = 400; 6061 break; 6062 case 6: 6063 hdmi_dsc->max_slices = 12; 6064 hdmi_dsc->clk_per_slice = 400; 6065 break; 6066 case 7: 6067 hdmi_dsc->max_slices = 16; 6068 hdmi_dsc->clk_per_slice = 400; 6069 break; 6070 case 0: 6071 default: 6072 hdmi_dsc->max_slices = 0; 6073 hdmi_dsc->clk_per_slice = 0; 6074 } 6075 } 6076 6077 if (cea_db_payload_len(hf_scds) >= 13 && hf_scds[13]) 6078 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES; 6079 } 6080 6081 /* Sink Capability Data Structure */ 6082 static void drm_parse_hdmi_forum_scds(struct drm_connector *connector, 6083 const u8 *hf_scds) 6084 { 6085 struct drm_display_info *info = &connector->display_info; 6086 struct drm_hdmi_info *hdmi = &info->hdmi; 6087 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap; 6088 int max_tmds_clock = 0; 6089 u8 max_frl_rate = 0; 6090 bool dsc_support = false; 6091 6092 info->has_hdmi_infoframe = true; 6093 6094 if (hf_scds[6] & 0x80) { 6095 hdmi->scdc.supported = true; 6096 if (hf_scds[6] & 0x40) 6097 hdmi->scdc.read_request = true; 6098 } 6099 6100 /* 6101 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 6102 * And as per the spec, three factors confirm this: 6103 * * Availability of a HF-VSDB block in EDID (check) 6104 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 6105 * * SCDC support available (let's check) 6106 * Lets check it out. 6107 */ 6108 6109 if (hf_scds[5]) { 6110 struct drm_scdc *scdc = &hdmi->scdc; 6111 6112 /* max clock is 5000 KHz times block value */ 6113 max_tmds_clock = hf_scds[5] * 5000; 6114 6115 if (max_tmds_clock > 340000) { 6116 info->max_tmds_clock = max_tmds_clock; 6117 } 6118 6119 if (scdc->supported) { 6120 scdc->scrambling.supported = true; 6121 6122 /* Few sinks support scrambling for clocks < 340M */ 6123 if ((hf_scds[6] & 0x8)) 6124 scdc->scrambling.low_rates = true; 6125 } 6126 } 6127 6128 if (hf_scds[7]) { 6129 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4; 6130 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes, 6131 &hdmi->max_frl_rate_per_lane); 6132 } 6133 6134 drm_parse_ycbcr420_deep_color_info(connector, hf_scds); 6135 6136 if (cea_db_payload_len(hf_scds) >= 11 && hf_scds[11]) { 6137 drm_parse_dsc_info(hdmi_dsc, hf_scds); 6138 dsc_support = true; 6139 } 6140 6141 drm_dbg_kms(connector->dev, 6142 "[CONNECTOR:%d:%s] HF-VSDB: max TMDS clock: %d KHz, HDMI 2.1 support: %s, DSC 1.2 support: %s\n", 6143 connector->base.id, connector->name, 6144 max_tmds_clock, str_yes_no(max_frl_rate), str_yes_no(dsc_support)); 6145 } 6146 6147 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 6148 const u8 *hdmi) 6149 { 6150 struct drm_display_info *info = &connector->display_info; 6151 unsigned int dc_bpc = 0; 6152 6153 /* HDMI supports at least 8 bpc */ 6154 info->bpc = 8; 6155 6156 if (cea_db_payload_len(hdmi) < 6) 6157 return; 6158 6159 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 6160 dc_bpc = 10; 6161 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30; 6162 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 30.\n", 6163 connector->base.id, connector->name); 6164 } 6165 6166 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 6167 dc_bpc = 12; 6168 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36; 6169 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 36.\n", 6170 connector->base.id, connector->name); 6171 } 6172 6173 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 6174 dc_bpc = 16; 6175 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48; 6176 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 48.\n", 6177 connector->base.id, connector->name); 6178 } 6179 6180 if (dc_bpc == 0) { 6181 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] No deep color support on this HDMI sink.\n", 6182 connector->base.id, connector->name); 6183 return; 6184 } 6185 6186 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Assigning HDMI sink color depth as %d bpc.\n", 6187 connector->base.id, connector->name, dc_bpc); 6188 info->bpc = dc_bpc; 6189 6190 /* YCRCB444 is optional according to spec. */ 6191 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 6192 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes; 6193 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does YCRCB444 in deep color.\n", 6194 connector->base.id, connector->name); 6195 } 6196 6197 /* 6198 * Spec says that if any deep color mode is supported at all, 6199 * then deep color 36 bit must be supported. 6200 */ 6201 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 6202 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink should do DC_36, but does not!\n", 6203 connector->base.id, connector->name); 6204 } 6205 } 6206 6207 /* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */ 6208 static void 6209 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 6210 { 6211 struct drm_display_info *info = &connector->display_info; 6212 u8 len = cea_db_payload_len(db); 6213 6214 info->is_hdmi = true; 6215 6216 if (len >= 6) 6217 info->dvi_dual = db[6] & 1; 6218 if (len >= 7) 6219 info->max_tmds_clock = db[7] * 5000; 6220 6221 /* 6222 * Try to infer whether the sink supports HDMI infoframes. 6223 * 6224 * HDMI infoframe support was first added in HDMI 1.4. Assume the sink 6225 * supports infoframes if HDMI_Video_present is set. 6226 */ 6227 if (len >= 8 && db[8] & BIT(5)) 6228 info->has_hdmi_infoframe = true; 6229 6230 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI: DVI dual %d, max TMDS clock %d kHz\n", 6231 connector->base.id, connector->name, 6232 info->dvi_dual, info->max_tmds_clock); 6233 6234 drm_parse_hdmi_deep_color_info(connector, db); 6235 } 6236 6237 /* 6238 * See EDID extension for head-mounted and specialized monitors, specified at: 6239 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension 6240 */ 6241 static void drm_parse_microsoft_vsdb(struct drm_connector *connector, 6242 const u8 *db) 6243 { 6244 struct drm_display_info *info = &connector->display_info; 6245 u8 version = db[4]; 6246 bool desktop_usage = db[5] & BIT(6); 6247 6248 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */ 6249 if (version == 1 || version == 2 || (version == 3 && !desktop_usage)) 6250 info->non_desktop = true; 6251 6252 drm_dbg_kms(connector->dev, 6253 "[CONNECTOR:%d:%s] HMD or specialized display VSDB version %u: 0x%02x\n", 6254 connector->base.id, connector->name, version, db[5]); 6255 } 6256 6257 static void drm_parse_cea_ext(struct drm_connector *connector, 6258 const struct drm_edid *drm_edid) 6259 { 6260 struct drm_display_info *info = &connector->display_info; 6261 struct drm_edid_iter edid_iter; 6262 const struct cea_db *db; 6263 struct cea_db_iter iter; 6264 const u8 *edid_ext; 6265 u64 y420cmdb_map = 0; 6266 6267 drm_edid_iter_begin(drm_edid, &edid_iter); 6268 drm_edid_iter_for_each(edid_ext, &edid_iter) { 6269 if (edid_ext[0] != CEA_EXT) 6270 continue; 6271 6272 if (!info->cea_rev) 6273 info->cea_rev = edid_ext[1]; 6274 6275 if (info->cea_rev != edid_ext[1]) 6276 drm_dbg_kms(connector->dev, 6277 "[CONNECTOR:%d:%s] CEA extension version mismatch %u != %u\n", 6278 connector->base.id, connector->name, 6279 info->cea_rev, edid_ext[1]); 6280 6281 /* The existence of a CTA extension should imply RGB support */ 6282 info->color_formats = DRM_COLOR_FORMAT_RGB444; 6283 if (edid_ext[3] & EDID_CEA_YCRCB444) 6284 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444; 6285 if (edid_ext[3] & EDID_CEA_YCRCB422) 6286 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422; 6287 if (edid_ext[3] & EDID_BASIC_AUDIO) 6288 info->has_audio = true; 6289 6290 } 6291 drm_edid_iter_end(&edid_iter); 6292 6293 cea_db_iter_edid_begin(drm_edid, &iter); 6294 cea_db_iter_for_each(db, &iter) { 6295 /* FIXME: convert parsers to use struct cea_db */ 6296 const u8 *data = (const u8 *)db; 6297 6298 if (cea_db_is_hdmi_vsdb(db)) 6299 drm_parse_hdmi_vsdb_video(connector, data); 6300 else if (cea_db_is_hdmi_forum_vsdb(db) || 6301 cea_db_is_hdmi_forum_scdb(db)) 6302 drm_parse_hdmi_forum_scds(connector, data); 6303 else if (cea_db_is_microsoft_vsdb(db)) 6304 drm_parse_microsoft_vsdb(connector, data); 6305 else if (cea_db_is_y420cmdb(db)) 6306 parse_cta_y420cmdb(connector, db, &y420cmdb_map); 6307 else if (cea_db_is_y420vdb(db)) 6308 parse_cta_y420vdb(connector, db); 6309 else if (cea_db_is_vcdb(db)) 6310 drm_parse_vcdb(connector, data); 6311 else if (cea_db_is_hdmi_hdr_metadata_block(db)) 6312 drm_parse_hdr_metadata_block(connector, data); 6313 else if (cea_db_tag(db) == CTA_DB_VIDEO) 6314 parse_cta_vdb(connector, db); 6315 else if (cea_db_tag(db) == CTA_DB_AUDIO) 6316 info->has_audio = true; 6317 } 6318 cea_db_iter_end(&iter); 6319 6320 if (y420cmdb_map) 6321 update_cta_y420cmdb(connector, y420cmdb_map); 6322 } 6323 6324 static 6325 void get_monitor_range(const struct detailed_timing *timing, void *c) 6326 { 6327 struct detailed_mode_closure *closure = c; 6328 struct drm_display_info *info = &closure->connector->display_info; 6329 struct drm_monitor_range_info *monitor_range = &info->monitor_range; 6330 const struct detailed_non_pixel *data = &timing->data.other_data; 6331 const struct detailed_data_monitor_range *range = &data->data.range; 6332 const struct edid *edid = closure->drm_edid->edid; 6333 6334 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE)) 6335 return; 6336 6337 /* 6338 * These limits are used to determine the VRR refresh 6339 * rate range. Only the "range limits only" variant 6340 * of the range descriptor seems to guarantee that 6341 * any and all timings are accepted by the sink, as 6342 * opposed to just timings conforming to the indicated 6343 * formula (GTF/GTF2/CVT). Thus other variants of the 6344 * range descriptor are not accepted here. 6345 */ 6346 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG) 6347 return; 6348 6349 monitor_range->min_vfreq = range->min_vfreq; 6350 monitor_range->max_vfreq = range->max_vfreq; 6351 6352 if (edid->revision >= 4) { 6353 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ) 6354 monitor_range->min_vfreq += 255; 6355 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ) 6356 monitor_range->max_vfreq += 255; 6357 } 6358 } 6359 6360 static void drm_get_monitor_range(struct drm_connector *connector, 6361 const struct drm_edid *drm_edid) 6362 { 6363 const struct drm_display_info *info = &connector->display_info; 6364 struct detailed_mode_closure closure = { 6365 .connector = connector, 6366 .drm_edid = drm_edid, 6367 }; 6368 6369 if (drm_edid->edid->revision < 4) 6370 return; 6371 6372 if (!(drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ)) 6373 return; 6374 6375 drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure); 6376 6377 drm_dbg_kms(connector->dev, 6378 "[CONNECTOR:%d:%s] Supported Monitor Refresh rate range is %d Hz - %d Hz\n", 6379 connector->base.id, connector->name, 6380 info->monitor_range.min_vfreq, info->monitor_range.max_vfreq); 6381 } 6382 6383 static void drm_parse_vesa_mso_data(struct drm_connector *connector, 6384 const struct displayid_block *block) 6385 { 6386 struct displayid_vesa_vendor_specific_block *vesa = 6387 (struct displayid_vesa_vendor_specific_block *)block; 6388 struct drm_display_info *info = &connector->display_info; 6389 6390 if (block->num_bytes < 3) { 6391 drm_dbg_kms(connector->dev, 6392 "[CONNECTOR:%d:%s] Unexpected vendor block size %u\n", 6393 connector->base.id, connector->name, block->num_bytes); 6394 return; 6395 } 6396 6397 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI) 6398 return; 6399 6400 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) { 6401 drm_dbg_kms(connector->dev, 6402 "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n", 6403 connector->base.id, connector->name); 6404 return; 6405 } 6406 6407 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) { 6408 default: 6409 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n", 6410 connector->base.id, connector->name); 6411 fallthrough; 6412 case 0: 6413 info->mso_stream_count = 0; 6414 break; 6415 case 1: 6416 info->mso_stream_count = 2; /* 2 or 4 links */ 6417 break; 6418 case 2: 6419 info->mso_stream_count = 4; /* 4 links */ 6420 break; 6421 } 6422 6423 if (!info->mso_stream_count) { 6424 info->mso_pixel_overlap = 0; 6425 return; 6426 } 6427 6428 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso); 6429 if (info->mso_pixel_overlap > 8) { 6430 drm_dbg_kms(connector->dev, 6431 "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n", 6432 connector->base.id, connector->name, 6433 info->mso_pixel_overlap); 6434 info->mso_pixel_overlap = 8; 6435 } 6436 6437 drm_dbg_kms(connector->dev, 6438 "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n", 6439 connector->base.id, connector->name, 6440 info->mso_stream_count, info->mso_pixel_overlap); 6441 } 6442 6443 static void drm_update_mso(struct drm_connector *connector, 6444 const struct drm_edid *drm_edid) 6445 { 6446 const struct displayid_block *block; 6447 struct displayid_iter iter; 6448 6449 displayid_iter_edid_begin(drm_edid, &iter); 6450 displayid_iter_for_each(block, &iter) { 6451 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC) 6452 drm_parse_vesa_mso_data(connector, block); 6453 } 6454 displayid_iter_end(&iter); 6455 } 6456 6457 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset 6458 * all of the values which would have been set from EDID 6459 */ 6460 static void drm_reset_display_info(struct drm_connector *connector) 6461 { 6462 struct drm_display_info *info = &connector->display_info; 6463 6464 info->width_mm = 0; 6465 info->height_mm = 0; 6466 6467 info->bpc = 0; 6468 info->color_formats = 0; 6469 info->cea_rev = 0; 6470 info->max_tmds_clock = 0; 6471 info->dvi_dual = false; 6472 info->is_hdmi = false; 6473 info->has_audio = false; 6474 info->has_hdmi_infoframe = false; 6475 info->rgb_quant_range_selectable = false; 6476 memset(&info->hdmi, 0, sizeof(info->hdmi)); 6477 6478 info->edid_hdmi_rgb444_dc_modes = 0; 6479 info->edid_hdmi_ycbcr444_dc_modes = 0; 6480 6481 info->non_desktop = 0; 6482 memset(&info->monitor_range, 0, sizeof(info->monitor_range)); 6483 memset(&info->luminance_range, 0, sizeof(info->luminance_range)); 6484 6485 info->mso_stream_count = 0; 6486 info->mso_pixel_overlap = 0; 6487 info->max_dsc_bpp = 0; 6488 6489 kfree(info->vics); 6490 info->vics = NULL; 6491 info->vics_len = 0; 6492 6493 info->quirks = 0; 6494 } 6495 6496 static void update_displayid_info(struct drm_connector *connector, 6497 const struct drm_edid *drm_edid) 6498 { 6499 struct drm_display_info *info = &connector->display_info; 6500 const struct displayid_block *block; 6501 struct displayid_iter iter; 6502 6503 displayid_iter_edid_begin(drm_edid, &iter); 6504 displayid_iter_for_each(block, &iter) { 6505 if (displayid_version(&iter) == DISPLAY_ID_STRUCTURE_VER_20 && 6506 (displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_VR || 6507 displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_AR)) 6508 info->non_desktop = true; 6509 6510 /* 6511 * We're only interested in the base section here, no need to 6512 * iterate further. 6513 */ 6514 break; 6515 } 6516 displayid_iter_end(&iter); 6517 } 6518 6519 static void update_display_info(struct drm_connector *connector, 6520 const struct drm_edid *drm_edid) 6521 { 6522 struct drm_display_info *info = &connector->display_info; 6523 const struct edid *edid; 6524 6525 drm_reset_display_info(connector); 6526 clear_eld(connector); 6527 6528 if (!drm_edid) 6529 return; 6530 6531 edid = drm_edid->edid; 6532 6533 info->quirks = edid_get_quirks(drm_edid); 6534 6535 info->width_mm = edid->width_cm * 10; 6536 info->height_mm = edid->height_cm * 10; 6537 6538 drm_get_monitor_range(connector, drm_edid); 6539 6540 if (edid->revision < 3) 6541 goto out; 6542 6543 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 6544 goto out; 6545 6546 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 6547 drm_parse_cea_ext(connector, drm_edid); 6548 6549 update_displayid_info(connector, drm_edid); 6550 6551 /* 6552 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 6553 * 6554 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 6555 * tells us to assume 8 bpc color depth if the EDID doesn't have 6556 * extensions which tell otherwise. 6557 */ 6558 if (info->bpc == 0 && edid->revision == 3 && 6559 edid->input & DRM_EDID_DIGITAL_DFP_1_X) { 6560 info->bpc = 8; 6561 drm_dbg_kms(connector->dev, 6562 "[CONNECTOR:%d:%s] Assigning DFP sink color depth as %d bpc.\n", 6563 connector->base.id, connector->name, info->bpc); 6564 } 6565 6566 /* Only defined for 1.4 with digital displays */ 6567 if (edid->revision < 4) 6568 goto out; 6569 6570 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 6571 case DRM_EDID_DIGITAL_DEPTH_6: 6572 info->bpc = 6; 6573 break; 6574 case DRM_EDID_DIGITAL_DEPTH_8: 6575 info->bpc = 8; 6576 break; 6577 case DRM_EDID_DIGITAL_DEPTH_10: 6578 info->bpc = 10; 6579 break; 6580 case DRM_EDID_DIGITAL_DEPTH_12: 6581 info->bpc = 12; 6582 break; 6583 case DRM_EDID_DIGITAL_DEPTH_14: 6584 info->bpc = 14; 6585 break; 6586 case DRM_EDID_DIGITAL_DEPTH_16: 6587 info->bpc = 16; 6588 break; 6589 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 6590 default: 6591 info->bpc = 0; 6592 break; 6593 } 6594 6595 drm_dbg_kms(connector->dev, 6596 "[CONNECTOR:%d:%s] Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 6597 connector->base.id, connector->name, info->bpc); 6598 6599 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 6600 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444; 6601 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 6602 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422; 6603 6604 drm_update_mso(connector, drm_edid); 6605 6606 out: 6607 if (info->quirks & EDID_QUIRK_NON_DESKTOP) { 6608 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Non-desktop display%s\n", 6609 connector->base.id, connector->name, 6610 info->non_desktop ? " (redundant quirk)" : ""); 6611 info->non_desktop = true; 6612 } 6613 6614 if (info->quirks & EDID_QUIRK_CAP_DSC_15BPP) 6615 info->max_dsc_bpp = 15; 6616 6617 if (info->quirks & EDID_QUIRK_FORCE_6BPC) 6618 info->bpc = 6; 6619 6620 if (info->quirks & EDID_QUIRK_FORCE_8BPC) 6621 info->bpc = 8; 6622 6623 if (info->quirks & EDID_QUIRK_FORCE_10BPC) 6624 info->bpc = 10; 6625 6626 if (info->quirks & EDID_QUIRK_FORCE_12BPC) 6627 info->bpc = 12; 6628 6629 /* Depends on info->cea_rev set by drm_parse_cea_ext() above */ 6630 drm_edid_to_eld(connector, drm_edid); 6631 } 6632 6633 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 6634 struct displayid_detailed_timings_1 *timings, 6635 bool type_7) 6636 { 6637 struct drm_display_mode *mode; 6638 unsigned pixel_clock = (timings->pixel_clock[0] | 6639 (timings->pixel_clock[1] << 8) | 6640 (timings->pixel_clock[2] << 16)) + 1; 6641 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 6642 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 6643 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 6644 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 6645 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 6646 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 6647 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 6648 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 6649 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 6650 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 6651 6652 mode = drm_mode_create(dev); 6653 if (!mode) 6654 return NULL; 6655 6656 /* resolution is kHz for type VII, and 10 kHz for type I */ 6657 mode->clock = type_7 ? pixel_clock : pixel_clock * 10; 6658 mode->hdisplay = hactive; 6659 mode->hsync_start = mode->hdisplay + hsync; 6660 mode->hsync_end = mode->hsync_start + hsync_width; 6661 mode->htotal = mode->hdisplay + hblank; 6662 6663 mode->vdisplay = vactive; 6664 mode->vsync_start = mode->vdisplay + vsync; 6665 mode->vsync_end = mode->vsync_start + vsync_width; 6666 mode->vtotal = mode->vdisplay + vblank; 6667 6668 mode->flags = 0; 6669 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 6670 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 6671 mode->type = DRM_MODE_TYPE_DRIVER; 6672 6673 if (timings->flags & 0x80) 6674 mode->type |= DRM_MODE_TYPE_PREFERRED; 6675 drm_mode_set_name(mode); 6676 6677 return mode; 6678 } 6679 6680 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 6681 const struct displayid_block *block) 6682 { 6683 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 6684 int i; 6685 int num_timings; 6686 struct drm_display_mode *newmode; 6687 int num_modes = 0; 6688 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING; 6689 /* blocks must be multiple of 20 bytes length */ 6690 if (block->num_bytes % 20) 6691 return 0; 6692 6693 num_timings = block->num_bytes / 20; 6694 for (i = 0; i < num_timings; i++) { 6695 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 6696 6697 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7); 6698 if (!newmode) 6699 continue; 6700 6701 drm_mode_probed_add(connector, newmode); 6702 num_modes++; 6703 } 6704 return num_modes; 6705 } 6706 6707 static int add_displayid_detailed_modes(struct drm_connector *connector, 6708 const struct drm_edid *drm_edid) 6709 { 6710 const struct displayid_block *block; 6711 struct displayid_iter iter; 6712 int num_modes = 0; 6713 6714 displayid_iter_edid_begin(drm_edid, &iter); 6715 displayid_iter_for_each(block, &iter) { 6716 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING || 6717 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING) 6718 num_modes += add_displayid_detailed_1_modes(connector, block); 6719 } 6720 displayid_iter_end(&iter); 6721 6722 return num_modes; 6723 } 6724 6725 static int _drm_edid_connector_add_modes(struct drm_connector *connector, 6726 const struct drm_edid *drm_edid) 6727 { 6728 const struct drm_display_info *info = &connector->display_info; 6729 int num_modes = 0; 6730 6731 if (!drm_edid) 6732 return 0; 6733 6734 /* 6735 * EDID spec says modes should be preferred in this order: 6736 * - preferred detailed mode 6737 * - other detailed modes from base block 6738 * - detailed modes from extension blocks 6739 * - CVT 3-byte code modes 6740 * - standard timing codes 6741 * - established timing codes 6742 * - modes inferred from GTF or CVT range information 6743 * 6744 * We get this pretty much right. 6745 * 6746 * XXX order for additional mode types in extension blocks? 6747 */ 6748 num_modes += add_detailed_modes(connector, drm_edid); 6749 num_modes += add_cvt_modes(connector, drm_edid); 6750 num_modes += add_standard_modes(connector, drm_edid); 6751 num_modes += add_established_modes(connector, drm_edid); 6752 num_modes += add_cea_modes(connector, drm_edid); 6753 num_modes += add_alternate_cea_modes(connector, drm_edid); 6754 num_modes += add_displayid_detailed_modes(connector, drm_edid); 6755 if (drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ) 6756 num_modes += add_inferred_modes(connector, drm_edid); 6757 6758 if (info->quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 6759 edid_fixup_preferred(connector); 6760 6761 return num_modes; 6762 } 6763 6764 static void _drm_update_tile_info(struct drm_connector *connector, 6765 const struct drm_edid *drm_edid); 6766 6767 static int _drm_edid_connector_property_update(struct drm_connector *connector, 6768 const struct drm_edid *drm_edid) 6769 { 6770 struct drm_device *dev = connector->dev; 6771 int ret; 6772 6773 if (connector->edid_blob_ptr) { 6774 const struct edid *old_edid = connector->edid_blob_ptr->data; 6775 6776 if (old_edid) { 6777 if (!drm_edid_are_equal(drm_edid ? drm_edid->edid : NULL, old_edid)) { 6778 connector->epoch_counter++; 6779 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n", 6780 connector->base.id, connector->name, 6781 connector->epoch_counter); 6782 } 6783 } 6784 } 6785 6786 ret = drm_property_replace_global_blob(dev, 6787 &connector->edid_blob_ptr, 6788 drm_edid ? drm_edid->size : 0, 6789 drm_edid ? drm_edid->edid : NULL, 6790 &connector->base, 6791 dev->mode_config.edid_property); 6792 if (ret) { 6793 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n", 6794 connector->base.id, connector->name, ret); 6795 goto out; 6796 } 6797 6798 ret = drm_object_property_set_value(&connector->base, 6799 dev->mode_config.non_desktop_property, 6800 connector->display_info.non_desktop); 6801 if (ret) { 6802 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n", 6803 connector->base.id, connector->name, ret); 6804 goto out; 6805 } 6806 6807 ret = drm_connector_set_tile_property(connector); 6808 if (ret) { 6809 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n", 6810 connector->base.id, connector->name, ret); 6811 goto out; 6812 } 6813 6814 out: 6815 return ret; 6816 } 6817 6818 /** 6819 * drm_edid_connector_update - Update connector information from EDID 6820 * @connector: Connector 6821 * @drm_edid: EDID 6822 * 6823 * Update the connector display info, ELD, HDR metadata, relevant properties, 6824 * etc. from the passed in EDID. 6825 * 6826 * If EDID is NULL, reset the information. 6827 * 6828 * Must be called before calling drm_edid_connector_add_modes(). 6829 * 6830 * Return: 0 on success, negative error on errors. 6831 */ 6832 int drm_edid_connector_update(struct drm_connector *connector, 6833 const struct drm_edid *drm_edid) 6834 { 6835 update_display_info(connector, drm_edid); 6836 6837 _drm_update_tile_info(connector, drm_edid); 6838 6839 return _drm_edid_connector_property_update(connector, drm_edid); 6840 } 6841 EXPORT_SYMBOL(drm_edid_connector_update); 6842 6843 /** 6844 * drm_edid_connector_add_modes - Update probed modes from the EDID property 6845 * @connector: Connector 6846 * 6847 * Add the modes from the previously updated EDID property to the connector 6848 * probed modes list. 6849 * 6850 * drm_edid_connector_update() must have been called before this to update the 6851 * EDID property. 6852 * 6853 * Return: The number of modes added, or 0 if we couldn't find any. 6854 */ 6855 int drm_edid_connector_add_modes(struct drm_connector *connector) 6856 { 6857 const struct drm_edid *drm_edid = NULL; 6858 int count; 6859 6860 if (connector->edid_blob_ptr) 6861 drm_edid = drm_edid_alloc(connector->edid_blob_ptr->data, 6862 connector->edid_blob_ptr->length); 6863 6864 count = _drm_edid_connector_add_modes(connector, drm_edid); 6865 6866 drm_edid_free(drm_edid); 6867 6868 return count; 6869 } 6870 EXPORT_SYMBOL(drm_edid_connector_add_modes); 6871 6872 /** 6873 * drm_connector_update_edid_property - update the edid property of a connector 6874 * @connector: drm connector 6875 * @edid: new value of the edid property 6876 * 6877 * This function creates a new blob modeset object and assigns its id to the 6878 * connector's edid property. 6879 * Since we also parse tile information from EDID's displayID block, we also 6880 * set the connector's tile property here. See drm_connector_set_tile_property() 6881 * for more details. 6882 * 6883 * This function is deprecated. Use drm_edid_connector_update() instead. 6884 * 6885 * Returns: 6886 * Zero on success, negative errno on failure. 6887 */ 6888 int drm_connector_update_edid_property(struct drm_connector *connector, 6889 const struct edid *edid) 6890 { 6891 struct drm_edid drm_edid; 6892 6893 return drm_edid_connector_update(connector, drm_edid_legacy_init(&drm_edid, edid)); 6894 } 6895 EXPORT_SYMBOL(drm_connector_update_edid_property); 6896 6897 /** 6898 * drm_add_edid_modes - add modes from EDID data, if available 6899 * @connector: connector we're probing 6900 * @edid: EDID data 6901 * 6902 * Add the specified modes to the connector's mode list. Also fills out the 6903 * &drm_display_info structure and ELD in @connector with any information which 6904 * can be derived from the edid. 6905 * 6906 * This function is deprecated. Use drm_edid_connector_add_modes() instead. 6907 * 6908 * Return: The number of modes added or 0 if we couldn't find any. 6909 */ 6910 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 6911 { 6912 struct drm_edid _drm_edid; 6913 const struct drm_edid *drm_edid; 6914 6915 if (edid && !drm_edid_is_valid(edid)) { 6916 drm_warn(connector->dev, "[CONNECTOR:%d:%s] EDID invalid.\n", 6917 connector->base.id, connector->name); 6918 edid = NULL; 6919 } 6920 6921 drm_edid = drm_edid_legacy_init(&_drm_edid, edid); 6922 6923 update_display_info(connector, drm_edid); 6924 6925 return _drm_edid_connector_add_modes(connector, drm_edid); 6926 } 6927 EXPORT_SYMBOL(drm_add_edid_modes); 6928 6929 /** 6930 * drm_add_modes_noedid - add modes for the connectors without EDID 6931 * @connector: connector we're probing 6932 * @hdisplay: the horizontal display limit 6933 * @vdisplay: the vertical display limit 6934 * 6935 * Add the specified modes to the connector's mode list. Only when the 6936 * hdisplay/vdisplay is not beyond the given limit, it will be added. 6937 * 6938 * Return: The number of modes added or 0 if we couldn't find any. 6939 */ 6940 int drm_add_modes_noedid(struct drm_connector *connector, 6941 int hdisplay, int vdisplay) 6942 { 6943 int i, count, num_modes = 0; 6944 struct drm_display_mode *mode; 6945 struct drm_device *dev = connector->dev; 6946 6947 count = ARRAY_SIZE(drm_dmt_modes); 6948 if (hdisplay < 0) 6949 hdisplay = 0; 6950 if (vdisplay < 0) 6951 vdisplay = 0; 6952 6953 for (i = 0; i < count; i++) { 6954 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 6955 6956 if (hdisplay && vdisplay) { 6957 /* 6958 * Only when two are valid, they will be used to check 6959 * whether the mode should be added to the mode list of 6960 * the connector. 6961 */ 6962 if (ptr->hdisplay > hdisplay || 6963 ptr->vdisplay > vdisplay) 6964 continue; 6965 } 6966 if (drm_mode_vrefresh(ptr) > 61) 6967 continue; 6968 mode = drm_mode_duplicate(dev, ptr); 6969 if (mode) { 6970 drm_mode_probed_add(connector, mode); 6971 num_modes++; 6972 } 6973 } 6974 return num_modes; 6975 } 6976 EXPORT_SYMBOL(drm_add_modes_noedid); 6977 6978 /** 6979 * drm_set_preferred_mode - Sets the preferred mode of a connector 6980 * @connector: connector whose mode list should be processed 6981 * @hpref: horizontal resolution of preferred mode 6982 * @vpref: vertical resolution of preferred mode 6983 * 6984 * Marks a mode as preferred if it matches the resolution specified by @hpref 6985 * and @vpref. 6986 */ 6987 void drm_set_preferred_mode(struct drm_connector *connector, 6988 int hpref, int vpref) 6989 { 6990 struct drm_display_mode *mode; 6991 6992 list_for_each_entry(mode, &connector->probed_modes, head) { 6993 if (mode->hdisplay == hpref && 6994 mode->vdisplay == vpref) 6995 mode->type |= DRM_MODE_TYPE_PREFERRED; 6996 } 6997 } 6998 EXPORT_SYMBOL(drm_set_preferred_mode); 6999 7000 static bool is_hdmi2_sink(const struct drm_connector *connector) 7001 { 7002 /* 7003 * FIXME: sil-sii8620 doesn't have a connector around when 7004 * we need one, so we have to be prepared for a NULL connector. 7005 */ 7006 if (!connector) 7007 return true; 7008 7009 return connector->display_info.hdmi.scdc.supported || 7010 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420; 7011 } 7012 7013 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector, 7014 const struct drm_display_mode *mode) 7015 { 7016 bool has_hdmi_infoframe = connector ? 7017 connector->display_info.has_hdmi_infoframe : false; 7018 7019 if (!has_hdmi_infoframe) 7020 return 0; 7021 7022 /* No HDMI VIC when signalling 3D video format */ 7023 if (mode->flags & DRM_MODE_FLAG_3D_MASK) 7024 return 0; 7025 7026 return drm_match_hdmi_mode(mode); 7027 } 7028 7029 static u8 drm_mode_cea_vic(const struct drm_connector *connector, 7030 const struct drm_display_mode *mode) 7031 { 7032 /* 7033 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 7034 * we should send its VIC in vendor infoframes, else send the 7035 * VIC in AVI infoframes. Lets check if this mode is present in 7036 * HDMI 1.4b 4K modes 7037 */ 7038 if (drm_mode_hdmi_vic(connector, mode)) 7039 return 0; 7040 7041 return drm_match_cea_mode(mode); 7042 } 7043 7044 /* 7045 * Avoid sending VICs defined in HDMI 2.0 in AVI infoframes to sinks that 7046 * conform to HDMI 1.4. 7047 * 7048 * HDMI 1.4 (CTA-861-D) VIC range: [1..64] 7049 * HDMI 2.0 (CTA-861-F) VIC range: [1..107] 7050 * 7051 * If the sink lists the VIC in CTA VDB, assume it's fine, regardless of HDMI 7052 * version. 7053 */ 7054 static u8 vic_for_avi_infoframe(const struct drm_connector *connector, u8 vic) 7055 { 7056 if (!is_hdmi2_sink(connector) && vic > 64 && 7057 !cta_vdb_has_vic(connector, vic)) 7058 return 0; 7059 7060 return vic; 7061 } 7062 7063 /** 7064 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 7065 * data from a DRM display mode 7066 * @frame: HDMI AVI infoframe 7067 * @connector: the connector 7068 * @mode: DRM display mode 7069 * 7070 * Return: 0 on success or a negative error code on failure. 7071 */ 7072 int 7073 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 7074 const struct drm_connector *connector, 7075 const struct drm_display_mode *mode) 7076 { 7077 enum hdmi_picture_aspect picture_aspect; 7078 u8 vic, hdmi_vic; 7079 7080 if (!frame || !mode) 7081 return -EINVAL; 7082 7083 hdmi_avi_infoframe_init(frame); 7084 7085 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 7086 frame->pixel_repeat = 1; 7087 7088 vic = drm_mode_cea_vic(connector, mode); 7089 hdmi_vic = drm_mode_hdmi_vic(connector, mode); 7090 7091 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 7092 7093 /* 7094 * As some drivers don't support atomic, we can't use connector state. 7095 * So just initialize the frame with default values, just the same way 7096 * as it's done with other properties here. 7097 */ 7098 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; 7099 frame->itc = 0; 7100 7101 /* 7102 * Populate picture aspect ratio from either 7103 * user input (if specified) or from the CEA/HDMI mode lists. 7104 */ 7105 picture_aspect = mode->picture_aspect_ratio; 7106 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) { 7107 if (vic) 7108 picture_aspect = drm_get_cea_aspect_ratio(vic); 7109 else if (hdmi_vic) 7110 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic); 7111 } 7112 7113 /* 7114 * The infoframe can't convey anything but none, 4:3 7115 * and 16:9, so if the user has asked for anything else 7116 * we can only satisfy it by specifying the right VIC. 7117 */ 7118 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { 7119 if (vic) { 7120 if (picture_aspect != drm_get_cea_aspect_ratio(vic)) 7121 return -EINVAL; 7122 } else if (hdmi_vic) { 7123 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic)) 7124 return -EINVAL; 7125 } else { 7126 return -EINVAL; 7127 } 7128 7129 picture_aspect = HDMI_PICTURE_ASPECT_NONE; 7130 } 7131 7132 frame->video_code = vic_for_avi_infoframe(connector, vic); 7133 frame->picture_aspect = picture_aspect; 7134 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 7135 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 7136 7137 return 0; 7138 } 7139 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 7140 7141 /** 7142 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 7143 * quantization range information 7144 * @frame: HDMI AVI infoframe 7145 * @connector: the connector 7146 * @mode: DRM display mode 7147 * @rgb_quant_range: RGB quantization range (Q) 7148 */ 7149 void 7150 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 7151 const struct drm_connector *connector, 7152 const struct drm_display_mode *mode, 7153 enum hdmi_quantization_range rgb_quant_range) 7154 { 7155 const struct drm_display_info *info = &connector->display_info; 7156 7157 /* 7158 * CEA-861: 7159 * "A Source shall not send a non-zero Q value that does not correspond 7160 * to the default RGB Quantization Range for the transmitted Picture 7161 * unless the Sink indicates support for the Q bit in a Video 7162 * Capabilities Data Block." 7163 * 7164 * HDMI 2.0 recommends sending non-zero Q when it does match the 7165 * default RGB quantization range for the mode, even when QS=0. 7166 */ 7167 if (info->rgb_quant_range_selectable || 7168 rgb_quant_range == drm_default_rgb_quant_range(mode)) 7169 frame->quantization_range = rgb_quant_range; 7170 else 7171 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 7172 7173 /* 7174 * CEA-861-F: 7175 * "When transmitting any RGB colorimetry, the Source should set the 7176 * YQ-field to match the RGB Quantization Range being transmitted 7177 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 7178 * set YQ=1) and the Sink shall ignore the YQ-field." 7179 * 7180 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused 7181 * by non-zero YQ when receiving RGB. There doesn't seem to be any 7182 * good way to tell which version of CEA-861 the sink supports, so 7183 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based 7184 * on CEA-861-F. 7185 */ 7186 if (!is_hdmi2_sink(connector) || 7187 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 7188 frame->ycc_quantization_range = 7189 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 7190 else 7191 frame->ycc_quantization_range = 7192 HDMI_YCC_QUANTIZATION_RANGE_FULL; 7193 } 7194 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 7195 7196 static enum hdmi_3d_structure 7197 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 7198 { 7199 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 7200 7201 switch (layout) { 7202 case DRM_MODE_FLAG_3D_FRAME_PACKING: 7203 return HDMI_3D_STRUCTURE_FRAME_PACKING; 7204 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 7205 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 7206 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 7207 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 7208 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 7209 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 7210 case DRM_MODE_FLAG_3D_L_DEPTH: 7211 return HDMI_3D_STRUCTURE_L_DEPTH; 7212 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 7213 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 7214 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 7215 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 7216 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 7217 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 7218 default: 7219 return HDMI_3D_STRUCTURE_INVALID; 7220 } 7221 } 7222 7223 /** 7224 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 7225 * data from a DRM display mode 7226 * @frame: HDMI vendor infoframe 7227 * @connector: the connector 7228 * @mode: DRM display mode 7229 * 7230 * Note that there's is a need to send HDMI vendor infoframes only when using a 7231 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 7232 * function will return -EINVAL, error that can be safely ignored. 7233 * 7234 * Return: 0 on success or a negative error code on failure. 7235 */ 7236 int 7237 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 7238 const struct drm_connector *connector, 7239 const struct drm_display_mode *mode) 7240 { 7241 /* 7242 * FIXME: sil-sii8620 doesn't have a connector around when 7243 * we need one, so we have to be prepared for a NULL connector. 7244 */ 7245 bool has_hdmi_infoframe = connector ? 7246 connector->display_info.has_hdmi_infoframe : false; 7247 int err; 7248 7249 if (!frame || !mode) 7250 return -EINVAL; 7251 7252 if (!has_hdmi_infoframe) 7253 return -EINVAL; 7254 7255 err = hdmi_vendor_infoframe_init(frame); 7256 if (err < 0) 7257 return err; 7258 7259 /* 7260 * Even if it's not absolutely necessary to send the infoframe 7261 * (ie.vic==0 and s3d_struct==0) we will still send it if we 7262 * know that the sink can handle it. This is based on a 7263 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks 7264 * have trouble realizing that they should switch from 3D to 2D 7265 * mode if the source simply stops sending the infoframe when 7266 * it wants to switch from 3D to 2D. 7267 */ 7268 frame->vic = drm_mode_hdmi_vic(connector, mode); 7269 frame->s3d_struct = s3d_structure_from_display_mode(mode); 7270 7271 return 0; 7272 } 7273 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 7274 7275 static void drm_parse_tiled_block(struct drm_connector *connector, 7276 const struct displayid_block *block) 7277 { 7278 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 7279 u16 w, h; 7280 u8 tile_v_loc, tile_h_loc; 7281 u8 num_v_tile, num_h_tile; 7282 struct drm_tile_group *tg; 7283 7284 w = tile->tile_size[0] | tile->tile_size[1] << 8; 7285 h = tile->tile_size[2] | tile->tile_size[3] << 8; 7286 7287 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 7288 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 7289 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 7290 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 7291 7292 connector->has_tile = true; 7293 if (tile->tile_cap & 0x80) 7294 connector->tile_is_single_monitor = true; 7295 7296 connector->num_h_tile = num_h_tile + 1; 7297 connector->num_v_tile = num_v_tile + 1; 7298 connector->tile_h_loc = tile_h_loc; 7299 connector->tile_v_loc = tile_v_loc; 7300 connector->tile_h_size = w + 1; 7301 connector->tile_v_size = h + 1; 7302 7303 drm_dbg_kms(connector->dev, 7304 "[CONNECTOR:%d:%s] tile cap 0x%x, size %dx%d, num tiles %dx%d, location %dx%d, vend %c%c%c", 7305 connector->base.id, connector->name, 7306 tile->tile_cap, 7307 connector->tile_h_size, connector->tile_v_size, 7308 connector->num_h_tile, connector->num_v_tile, 7309 connector->tile_h_loc, connector->tile_v_loc, 7310 tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 7311 7312 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 7313 if (!tg) 7314 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 7315 if (!tg) 7316 return; 7317 7318 if (connector->tile_group != tg) { 7319 /* if we haven't got a pointer, 7320 take the reference, drop ref to old tile group */ 7321 if (connector->tile_group) 7322 drm_mode_put_tile_group(connector->dev, connector->tile_group); 7323 connector->tile_group = tg; 7324 } else { 7325 /* if same tile group, then release the ref we just took. */ 7326 drm_mode_put_tile_group(connector->dev, tg); 7327 } 7328 } 7329 7330 static bool displayid_is_tiled_block(const struct displayid_iter *iter, 7331 const struct displayid_block *block) 7332 { 7333 return (displayid_version(iter) == DISPLAY_ID_STRUCTURE_VER_12 && 7334 block->tag == DATA_BLOCK_TILED_DISPLAY) || 7335 (displayid_version(iter) == DISPLAY_ID_STRUCTURE_VER_20 && 7336 block->tag == DATA_BLOCK_2_TILED_DISPLAY_TOPOLOGY); 7337 } 7338 7339 static void _drm_update_tile_info(struct drm_connector *connector, 7340 const struct drm_edid *drm_edid) 7341 { 7342 const struct displayid_block *block; 7343 struct displayid_iter iter; 7344 7345 connector->has_tile = false; 7346 7347 displayid_iter_edid_begin(drm_edid, &iter); 7348 displayid_iter_for_each(block, &iter) { 7349 if (displayid_is_tiled_block(&iter, block)) 7350 drm_parse_tiled_block(connector, block); 7351 } 7352 displayid_iter_end(&iter); 7353 7354 if (!connector->has_tile && connector->tile_group) { 7355 drm_mode_put_tile_group(connector->dev, connector->tile_group); 7356 connector->tile_group = NULL; 7357 } 7358 } 7359