1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 #include <linux/kernel.h> 31 #include <linux/slab.h> 32 #include <linux/hdmi.h> 33 #include <linux/i2c.h> 34 #include <linux/module.h> 35 #include <linux/vga_switcheroo.h> 36 #include <drm/drmP.h> 37 #include <drm/drm_edid.h> 38 #include <drm/drm_encoder.h> 39 #include <drm/drm_displayid.h> 40 #include <drm/drm_scdc_helper.h> 41 42 #include "drm_crtc_internal.h" 43 44 #define version_greater(edid, maj, min) \ 45 (((edid)->version > (maj)) || \ 46 ((edid)->version == (maj) && (edid)->revision > (min))) 47 48 #define EDID_EST_TIMINGS 16 49 #define EDID_STD_TIMINGS 8 50 #define EDID_DETAILED_TIMINGS 4 51 52 /* 53 * EDID blocks out in the wild have a variety of bugs, try to collect 54 * them here (note that userspace may work around broken monitors first, 55 * but fixes should make their way here so that the kernel "just works" 56 * on as many displays as possible). 57 */ 58 59 /* First detailed mode wrong, use largest 60Hz mode */ 60 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 61 /* Reported 135MHz pixel clock is too high, needs adjustment */ 62 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 63 /* Prefer the largest mode at 75 Hz */ 64 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 65 /* Detail timing is in cm not mm */ 66 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 67 /* Detailed timing descriptors have bogus size values, so just take the 68 * maximum size and use that. 69 */ 70 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 71 /* Monitor forgot to set the first detailed is preferred bit. */ 72 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5) 73 /* use +hsync +vsync for detailed mode */ 74 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 75 /* Force reduced-blanking timings for detailed modes */ 76 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 77 /* Force 8bpc */ 78 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 79 /* Force 12bpc */ 80 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 81 /* Force 6bpc */ 82 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 83 /* Force 10bpc */ 84 #define EDID_QUIRK_FORCE_10BPC (1 << 11) 85 86 struct detailed_mode_closure { 87 struct drm_connector *connector; 88 struct edid *edid; 89 bool preferred; 90 u32 quirks; 91 int modes; 92 }; 93 94 #define LEVEL_DMT 0 95 #define LEVEL_GTF 1 96 #define LEVEL_GTF2 2 97 #define LEVEL_CVT 3 98 99 static const struct edid_quirk { 100 char vendor[4]; 101 int product_id; 102 u32 quirks; 103 } edid_quirk_list[] = { 104 /* Acer AL1706 */ 105 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 106 /* Acer F51 */ 107 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 108 /* Unknown Acer */ 109 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 110 111 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 112 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 113 114 /* Belinea 10 15 55 */ 115 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 116 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 117 118 /* Envision Peripherals, Inc. EN-7100e */ 119 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 120 /* Envision EN2028 */ 121 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 122 123 /* Funai Electronics PM36B */ 124 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 125 EDID_QUIRK_DETAILED_IN_CM }, 126 127 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 128 { "LGD", 764, EDID_QUIRK_FORCE_10BPC }, 129 130 /* LG Philips LCD LP154W01-A5 */ 131 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 132 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 133 134 /* Philips 107p5 CRT */ 135 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 136 137 /* Proview AY765C */ 138 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 139 140 /* Samsung SyncMaster 205BW. Note: irony */ 141 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 142 /* Samsung SyncMaster 22[5-6]BW */ 143 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 144 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 145 146 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 147 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 148 149 /* ViewSonic VA2026w */ 150 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 151 152 /* Medion MD 30217 PG */ 153 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 154 155 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 156 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 157 158 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 159 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, 160 }; 161 162 /* 163 * Autogenerated from the DMT spec. 164 * This table is copied from xfree86/modes/xf86EdidModes.c. 165 */ 166 static const struct drm_display_mode drm_dmt_modes[] = { 167 /* 0x01 - 640x350@85Hz */ 168 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 169 736, 832, 0, 350, 382, 385, 445, 0, 170 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 171 /* 0x02 - 640x400@85Hz */ 172 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 173 736, 832, 0, 400, 401, 404, 445, 0, 174 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 175 /* 0x03 - 720x400@85Hz */ 176 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 177 828, 936, 0, 400, 401, 404, 446, 0, 178 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 179 /* 0x04 - 640x480@60Hz */ 180 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 181 752, 800, 0, 480, 490, 492, 525, 0, 182 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 183 /* 0x05 - 640x480@72Hz */ 184 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 185 704, 832, 0, 480, 489, 492, 520, 0, 186 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 187 /* 0x06 - 640x480@75Hz */ 188 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 189 720, 840, 0, 480, 481, 484, 500, 0, 190 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 191 /* 0x07 - 640x480@85Hz */ 192 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 193 752, 832, 0, 480, 481, 484, 509, 0, 194 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 195 /* 0x08 - 800x600@56Hz */ 196 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 197 896, 1024, 0, 600, 601, 603, 625, 0, 198 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 199 /* 0x09 - 800x600@60Hz */ 200 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 201 968, 1056, 0, 600, 601, 605, 628, 0, 202 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 203 /* 0x0a - 800x600@72Hz */ 204 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 205 976, 1040, 0, 600, 637, 643, 666, 0, 206 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 207 /* 0x0b - 800x600@75Hz */ 208 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 209 896, 1056, 0, 600, 601, 604, 625, 0, 210 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 211 /* 0x0c - 800x600@85Hz */ 212 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 213 896, 1048, 0, 600, 601, 604, 631, 0, 214 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 215 /* 0x0d - 800x600@120Hz RB */ 216 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 217 880, 960, 0, 600, 603, 607, 636, 0, 218 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 219 /* 0x0e - 848x480@60Hz */ 220 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 221 976, 1088, 0, 480, 486, 494, 517, 0, 222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 223 /* 0x0f - 1024x768@43Hz, interlace */ 224 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 225 1208, 1264, 0, 768, 768, 776, 817, 0, 226 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 227 DRM_MODE_FLAG_INTERLACE) }, 228 /* 0x10 - 1024x768@60Hz */ 229 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 230 1184, 1344, 0, 768, 771, 777, 806, 0, 231 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 232 /* 0x11 - 1024x768@70Hz */ 233 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 234 1184, 1328, 0, 768, 771, 777, 806, 0, 235 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 236 /* 0x12 - 1024x768@75Hz */ 237 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 238 1136, 1312, 0, 768, 769, 772, 800, 0, 239 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 240 /* 0x13 - 1024x768@85Hz */ 241 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 242 1168, 1376, 0, 768, 769, 772, 808, 0, 243 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 244 /* 0x14 - 1024x768@120Hz RB */ 245 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 246 1104, 1184, 0, 768, 771, 775, 813, 0, 247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 248 /* 0x15 - 1152x864@75Hz */ 249 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 250 1344, 1600, 0, 864, 865, 868, 900, 0, 251 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 252 /* 0x55 - 1280x720@60Hz */ 253 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 254 1430, 1650, 0, 720, 725, 730, 750, 0, 255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 256 /* 0x16 - 1280x768@60Hz RB */ 257 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 258 1360, 1440, 0, 768, 771, 778, 790, 0, 259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 260 /* 0x17 - 1280x768@60Hz */ 261 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 262 1472, 1664, 0, 768, 771, 778, 798, 0, 263 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 264 /* 0x18 - 1280x768@75Hz */ 265 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 266 1488, 1696, 0, 768, 771, 778, 805, 0, 267 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 268 /* 0x19 - 1280x768@85Hz */ 269 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 270 1496, 1712, 0, 768, 771, 778, 809, 0, 271 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 272 /* 0x1a - 1280x768@120Hz RB */ 273 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 274 1360, 1440, 0, 768, 771, 778, 813, 0, 275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 276 /* 0x1b - 1280x800@60Hz RB */ 277 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 278 1360, 1440, 0, 800, 803, 809, 823, 0, 279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 280 /* 0x1c - 1280x800@60Hz */ 281 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 282 1480, 1680, 0, 800, 803, 809, 831, 0, 283 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 284 /* 0x1d - 1280x800@75Hz */ 285 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 286 1488, 1696, 0, 800, 803, 809, 838, 0, 287 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 288 /* 0x1e - 1280x800@85Hz */ 289 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 290 1496, 1712, 0, 800, 803, 809, 843, 0, 291 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 292 /* 0x1f - 1280x800@120Hz RB */ 293 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 294 1360, 1440, 0, 800, 803, 809, 847, 0, 295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 296 /* 0x20 - 1280x960@60Hz */ 297 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 298 1488, 1800, 0, 960, 961, 964, 1000, 0, 299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 300 /* 0x21 - 1280x960@85Hz */ 301 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 302 1504, 1728, 0, 960, 961, 964, 1011, 0, 303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 304 /* 0x22 - 1280x960@120Hz RB */ 305 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 306 1360, 1440, 0, 960, 963, 967, 1017, 0, 307 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 308 /* 0x23 - 1280x1024@60Hz */ 309 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 310 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 311 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 312 /* 0x24 - 1280x1024@75Hz */ 313 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 314 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 315 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 316 /* 0x25 - 1280x1024@85Hz */ 317 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 318 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 319 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 320 /* 0x26 - 1280x1024@120Hz RB */ 321 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 322 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 323 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 324 /* 0x27 - 1360x768@60Hz */ 325 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 326 1536, 1792, 0, 768, 771, 777, 795, 0, 327 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 328 /* 0x28 - 1360x768@120Hz RB */ 329 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 330 1440, 1520, 0, 768, 771, 776, 813, 0, 331 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 332 /* 0x51 - 1366x768@60Hz */ 333 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 334 1579, 1792, 0, 768, 771, 774, 798, 0, 335 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 336 /* 0x56 - 1366x768@60Hz */ 337 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 338 1436, 1500, 0, 768, 769, 772, 800, 0, 339 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 340 /* 0x29 - 1400x1050@60Hz RB */ 341 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 342 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 343 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 344 /* 0x2a - 1400x1050@60Hz */ 345 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 346 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 347 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 348 /* 0x2b - 1400x1050@75Hz */ 349 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 350 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 351 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 352 /* 0x2c - 1400x1050@85Hz */ 353 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 354 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 355 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 356 /* 0x2d - 1400x1050@120Hz RB */ 357 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 358 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 359 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 360 /* 0x2e - 1440x900@60Hz RB */ 361 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 362 1520, 1600, 0, 900, 903, 909, 926, 0, 363 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 364 /* 0x2f - 1440x900@60Hz */ 365 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 366 1672, 1904, 0, 900, 903, 909, 934, 0, 367 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 368 /* 0x30 - 1440x900@75Hz */ 369 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 370 1688, 1936, 0, 900, 903, 909, 942, 0, 371 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 372 /* 0x31 - 1440x900@85Hz */ 373 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 374 1696, 1952, 0, 900, 903, 909, 948, 0, 375 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 376 /* 0x32 - 1440x900@120Hz RB */ 377 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 378 1520, 1600, 0, 900, 903, 909, 953, 0, 379 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 380 /* 0x53 - 1600x900@60Hz */ 381 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 382 1704, 1800, 0, 900, 901, 904, 1000, 0, 383 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 384 /* 0x33 - 1600x1200@60Hz */ 385 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 386 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 387 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 388 /* 0x34 - 1600x1200@65Hz */ 389 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 390 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 391 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 392 /* 0x35 - 1600x1200@70Hz */ 393 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 394 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 395 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 396 /* 0x36 - 1600x1200@75Hz */ 397 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 398 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 399 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 400 /* 0x37 - 1600x1200@85Hz */ 401 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 402 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 403 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 404 /* 0x38 - 1600x1200@120Hz RB */ 405 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 406 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 407 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 408 /* 0x39 - 1680x1050@60Hz RB */ 409 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 410 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 411 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 412 /* 0x3a - 1680x1050@60Hz */ 413 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 414 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 415 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 416 /* 0x3b - 1680x1050@75Hz */ 417 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 418 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 419 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 420 /* 0x3c - 1680x1050@85Hz */ 421 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 422 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 423 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 424 /* 0x3d - 1680x1050@120Hz RB */ 425 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 426 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 427 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 428 /* 0x3e - 1792x1344@60Hz */ 429 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 430 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 431 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 432 /* 0x3f - 1792x1344@75Hz */ 433 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 434 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 435 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 436 /* 0x40 - 1792x1344@120Hz RB */ 437 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 438 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 439 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 440 /* 0x41 - 1856x1392@60Hz */ 441 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 442 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 443 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 444 /* 0x42 - 1856x1392@75Hz */ 445 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 446 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 447 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 448 /* 0x43 - 1856x1392@120Hz RB */ 449 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 450 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 451 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 452 /* 0x52 - 1920x1080@60Hz */ 453 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 454 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 455 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 456 /* 0x44 - 1920x1200@60Hz RB */ 457 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 458 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 459 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 460 /* 0x45 - 1920x1200@60Hz */ 461 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 462 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 463 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 464 /* 0x46 - 1920x1200@75Hz */ 465 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 466 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 467 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 468 /* 0x47 - 1920x1200@85Hz */ 469 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 470 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 471 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 472 /* 0x48 - 1920x1200@120Hz RB */ 473 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 474 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 475 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 476 /* 0x49 - 1920x1440@60Hz */ 477 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 478 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 479 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 480 /* 0x4a - 1920x1440@75Hz */ 481 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 482 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 483 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 484 /* 0x4b - 1920x1440@120Hz RB */ 485 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 486 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 487 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 488 /* 0x54 - 2048x1152@60Hz */ 489 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 490 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 491 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 492 /* 0x4c - 2560x1600@60Hz RB */ 493 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 494 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 495 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 496 /* 0x4d - 2560x1600@60Hz */ 497 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 498 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 499 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 500 /* 0x4e - 2560x1600@75Hz */ 501 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 502 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 503 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 504 /* 0x4f - 2560x1600@85Hz */ 505 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 506 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 507 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 508 /* 0x50 - 2560x1600@120Hz RB */ 509 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 510 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 511 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 512 /* 0x57 - 4096x2160@60Hz RB */ 513 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 514 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 515 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 516 /* 0x58 - 4096x2160@59.94Hz RB */ 517 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 518 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 519 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 520 }; 521 522 /* 523 * These more or less come from the DMT spec. The 720x400 modes are 524 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 525 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 526 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 527 * mode. 528 * 529 * The DMT modes have been fact-checked; the rest are mild guesses. 530 */ 531 static const struct drm_display_mode edid_est_modes[] = { 532 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 533 968, 1056, 0, 600, 601, 605, 628, 0, 534 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 535 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 536 896, 1024, 0, 600, 601, 603, 625, 0, 537 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 538 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 539 720, 840, 0, 480, 481, 484, 500, 0, 540 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 541 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 542 704, 832, 0, 480, 489, 492, 520, 0, 543 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 544 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 545 768, 864, 0, 480, 483, 486, 525, 0, 546 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 547 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 548 752, 800, 0, 480, 490, 492, 525, 0, 549 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 550 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 551 846, 900, 0, 400, 421, 423, 449, 0, 552 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 553 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 554 846, 900, 0, 400, 412, 414, 449, 0, 555 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 556 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 557 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 558 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 559 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 560 1136, 1312, 0, 768, 769, 772, 800, 0, 561 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 562 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 563 1184, 1328, 0, 768, 771, 777, 806, 0, 564 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 565 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 566 1184, 1344, 0, 768, 771, 777, 806, 0, 567 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 568 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 569 1208, 1264, 0, 768, 768, 776, 817, 0, 570 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 571 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 572 928, 1152, 0, 624, 625, 628, 667, 0, 573 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 574 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 575 896, 1056, 0, 600, 601, 604, 625, 0, 576 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 577 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 578 976, 1040, 0, 600, 637, 643, 666, 0, 579 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 580 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 581 1344, 1600, 0, 864, 865, 868, 900, 0, 582 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 583 }; 584 585 struct minimode { 586 short w; 587 short h; 588 short r; 589 short rb; 590 }; 591 592 static const struct minimode est3_modes[] = { 593 /* byte 6 */ 594 { 640, 350, 85, 0 }, 595 { 640, 400, 85, 0 }, 596 { 720, 400, 85, 0 }, 597 { 640, 480, 85, 0 }, 598 { 848, 480, 60, 0 }, 599 { 800, 600, 85, 0 }, 600 { 1024, 768, 85, 0 }, 601 { 1152, 864, 75, 0 }, 602 /* byte 7 */ 603 { 1280, 768, 60, 1 }, 604 { 1280, 768, 60, 0 }, 605 { 1280, 768, 75, 0 }, 606 { 1280, 768, 85, 0 }, 607 { 1280, 960, 60, 0 }, 608 { 1280, 960, 85, 0 }, 609 { 1280, 1024, 60, 0 }, 610 { 1280, 1024, 85, 0 }, 611 /* byte 8 */ 612 { 1360, 768, 60, 0 }, 613 { 1440, 900, 60, 1 }, 614 { 1440, 900, 60, 0 }, 615 { 1440, 900, 75, 0 }, 616 { 1440, 900, 85, 0 }, 617 { 1400, 1050, 60, 1 }, 618 { 1400, 1050, 60, 0 }, 619 { 1400, 1050, 75, 0 }, 620 /* byte 9 */ 621 { 1400, 1050, 85, 0 }, 622 { 1680, 1050, 60, 1 }, 623 { 1680, 1050, 60, 0 }, 624 { 1680, 1050, 75, 0 }, 625 { 1680, 1050, 85, 0 }, 626 { 1600, 1200, 60, 0 }, 627 { 1600, 1200, 65, 0 }, 628 { 1600, 1200, 70, 0 }, 629 /* byte 10 */ 630 { 1600, 1200, 75, 0 }, 631 { 1600, 1200, 85, 0 }, 632 { 1792, 1344, 60, 0 }, 633 { 1792, 1344, 75, 0 }, 634 { 1856, 1392, 60, 0 }, 635 { 1856, 1392, 75, 0 }, 636 { 1920, 1200, 60, 1 }, 637 { 1920, 1200, 60, 0 }, 638 /* byte 11 */ 639 { 1920, 1200, 75, 0 }, 640 { 1920, 1200, 85, 0 }, 641 { 1920, 1440, 60, 0 }, 642 { 1920, 1440, 75, 0 }, 643 }; 644 645 static const struct minimode extra_modes[] = { 646 { 1024, 576, 60, 0 }, 647 { 1366, 768, 60, 0 }, 648 { 1600, 900, 60, 0 }, 649 { 1680, 945, 60, 0 }, 650 { 1920, 1080, 60, 0 }, 651 { 2048, 1152, 60, 0 }, 652 { 2048, 1536, 60, 0 }, 653 }; 654 655 /* 656 * Probably taken from CEA-861 spec. 657 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. 658 * 659 * Index using the VIC. 660 */ 661 static const struct drm_display_mode edid_cea_modes[] = { 662 /* 0 - dummy, VICs start at 1 */ 663 { }, 664 /* 1 - 640x480@60Hz */ 665 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 666 752, 800, 0, 480, 490, 492, 525, 0, 667 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 668 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 669 /* 2 - 720x480@60Hz */ 670 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 671 798, 858, 0, 480, 489, 495, 525, 0, 672 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 673 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 674 /* 3 - 720x480@60Hz */ 675 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 676 798, 858, 0, 480, 489, 495, 525, 0, 677 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 678 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 679 /* 4 - 1280x720@60Hz */ 680 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 681 1430, 1650, 0, 720, 725, 730, 750, 0, 682 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 683 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 684 /* 5 - 1920x1080i@60Hz */ 685 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 686 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 687 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 688 DRM_MODE_FLAG_INTERLACE), 689 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 690 /* 6 - 720(1440)x480i@60Hz */ 691 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 692 801, 858, 0, 480, 488, 494, 525, 0, 693 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 694 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 695 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 696 /* 7 - 720(1440)x480i@60Hz */ 697 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 698 801, 858, 0, 480, 488, 494, 525, 0, 699 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 700 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 701 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 702 /* 8 - 720(1440)x240@60Hz */ 703 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 704 801, 858, 0, 240, 244, 247, 262, 0, 705 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 706 DRM_MODE_FLAG_DBLCLK), 707 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 708 /* 9 - 720(1440)x240@60Hz */ 709 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 710 801, 858, 0, 240, 244, 247, 262, 0, 711 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 712 DRM_MODE_FLAG_DBLCLK), 713 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 714 /* 10 - 2880x480i@60Hz */ 715 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 716 3204, 3432, 0, 480, 488, 494, 525, 0, 717 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 718 DRM_MODE_FLAG_INTERLACE), 719 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 720 /* 11 - 2880x480i@60Hz */ 721 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 722 3204, 3432, 0, 480, 488, 494, 525, 0, 723 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 724 DRM_MODE_FLAG_INTERLACE), 725 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 726 /* 12 - 2880x240@60Hz */ 727 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 728 3204, 3432, 0, 240, 244, 247, 262, 0, 729 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 730 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 731 /* 13 - 2880x240@60Hz */ 732 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 733 3204, 3432, 0, 240, 244, 247, 262, 0, 734 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 735 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 736 /* 14 - 1440x480@60Hz */ 737 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 738 1596, 1716, 0, 480, 489, 495, 525, 0, 739 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 740 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 741 /* 15 - 1440x480@60Hz */ 742 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 743 1596, 1716, 0, 480, 489, 495, 525, 0, 744 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 745 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 746 /* 16 - 1920x1080@60Hz */ 747 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 748 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 749 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 750 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 751 /* 17 - 720x576@50Hz */ 752 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 753 796, 864, 0, 576, 581, 586, 625, 0, 754 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 755 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 756 /* 18 - 720x576@50Hz */ 757 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 758 796, 864, 0, 576, 581, 586, 625, 0, 759 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 760 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 761 /* 19 - 1280x720@50Hz */ 762 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 763 1760, 1980, 0, 720, 725, 730, 750, 0, 764 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 765 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 766 /* 20 - 1920x1080i@50Hz */ 767 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 768 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 769 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 770 DRM_MODE_FLAG_INTERLACE), 771 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 772 /* 21 - 720(1440)x576i@50Hz */ 773 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 774 795, 864, 0, 576, 580, 586, 625, 0, 775 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 776 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 777 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 778 /* 22 - 720(1440)x576i@50Hz */ 779 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 780 795, 864, 0, 576, 580, 586, 625, 0, 781 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 782 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 783 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 784 /* 23 - 720(1440)x288@50Hz */ 785 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 786 795, 864, 0, 288, 290, 293, 312, 0, 787 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 788 DRM_MODE_FLAG_DBLCLK), 789 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 790 /* 24 - 720(1440)x288@50Hz */ 791 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 792 795, 864, 0, 288, 290, 293, 312, 0, 793 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 794 DRM_MODE_FLAG_DBLCLK), 795 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 796 /* 25 - 2880x576i@50Hz */ 797 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 798 3180, 3456, 0, 576, 580, 586, 625, 0, 799 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 800 DRM_MODE_FLAG_INTERLACE), 801 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 802 /* 26 - 2880x576i@50Hz */ 803 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 804 3180, 3456, 0, 576, 580, 586, 625, 0, 805 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 806 DRM_MODE_FLAG_INTERLACE), 807 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 808 /* 27 - 2880x288@50Hz */ 809 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 810 3180, 3456, 0, 288, 290, 293, 312, 0, 811 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 812 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 813 /* 28 - 2880x288@50Hz */ 814 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 815 3180, 3456, 0, 288, 290, 293, 312, 0, 816 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 817 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 818 /* 29 - 1440x576@50Hz */ 819 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 820 1592, 1728, 0, 576, 581, 586, 625, 0, 821 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 822 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 823 /* 30 - 1440x576@50Hz */ 824 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 825 1592, 1728, 0, 576, 581, 586, 625, 0, 826 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 827 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 828 /* 31 - 1920x1080@50Hz */ 829 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 830 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 831 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 832 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 833 /* 32 - 1920x1080@24Hz */ 834 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 835 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 836 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 837 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 838 /* 33 - 1920x1080@25Hz */ 839 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 840 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 841 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 842 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 843 /* 34 - 1920x1080@30Hz */ 844 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 845 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 846 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 847 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 848 /* 35 - 2880x480@60Hz */ 849 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 850 3192, 3432, 0, 480, 489, 495, 525, 0, 851 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 852 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 853 /* 36 - 2880x480@60Hz */ 854 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 855 3192, 3432, 0, 480, 489, 495, 525, 0, 856 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 857 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 858 /* 37 - 2880x576@50Hz */ 859 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 860 3184, 3456, 0, 576, 581, 586, 625, 0, 861 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 862 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 863 /* 38 - 2880x576@50Hz */ 864 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 865 3184, 3456, 0, 576, 581, 586, 625, 0, 866 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 867 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 868 /* 39 - 1920x1080i@50Hz */ 869 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 870 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 871 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 872 DRM_MODE_FLAG_INTERLACE), 873 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 874 /* 40 - 1920x1080i@100Hz */ 875 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 876 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 877 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 878 DRM_MODE_FLAG_INTERLACE), 879 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 880 /* 41 - 1280x720@100Hz */ 881 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 882 1760, 1980, 0, 720, 725, 730, 750, 0, 883 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 884 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 885 /* 42 - 720x576@100Hz */ 886 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 887 796, 864, 0, 576, 581, 586, 625, 0, 888 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 889 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 890 /* 43 - 720x576@100Hz */ 891 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 892 796, 864, 0, 576, 581, 586, 625, 0, 893 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 894 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 895 /* 44 - 720(1440)x576i@100Hz */ 896 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 897 795, 864, 0, 576, 580, 586, 625, 0, 898 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 899 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 900 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 901 /* 45 - 720(1440)x576i@100Hz */ 902 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 903 795, 864, 0, 576, 580, 586, 625, 0, 904 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 905 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 906 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 907 /* 46 - 1920x1080i@120Hz */ 908 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 909 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 910 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 911 DRM_MODE_FLAG_INTERLACE), 912 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 913 /* 47 - 1280x720@120Hz */ 914 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 915 1430, 1650, 0, 720, 725, 730, 750, 0, 916 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 917 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 918 /* 48 - 720x480@120Hz */ 919 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 920 798, 858, 0, 480, 489, 495, 525, 0, 921 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 922 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 923 /* 49 - 720x480@120Hz */ 924 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 925 798, 858, 0, 480, 489, 495, 525, 0, 926 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 927 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 928 /* 50 - 720(1440)x480i@120Hz */ 929 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 930 801, 858, 0, 480, 488, 494, 525, 0, 931 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 932 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 933 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 934 /* 51 - 720(1440)x480i@120Hz */ 935 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 936 801, 858, 0, 480, 488, 494, 525, 0, 937 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 938 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 939 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 940 /* 52 - 720x576@200Hz */ 941 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 942 796, 864, 0, 576, 581, 586, 625, 0, 943 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 944 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 945 /* 53 - 720x576@200Hz */ 946 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 947 796, 864, 0, 576, 581, 586, 625, 0, 948 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 949 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 950 /* 54 - 720(1440)x576i@200Hz */ 951 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 952 795, 864, 0, 576, 580, 586, 625, 0, 953 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 954 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 955 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 956 /* 55 - 720(1440)x576i@200Hz */ 957 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 958 795, 864, 0, 576, 580, 586, 625, 0, 959 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 960 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 961 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 962 /* 56 - 720x480@240Hz */ 963 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 964 798, 858, 0, 480, 489, 495, 525, 0, 965 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 966 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 967 /* 57 - 720x480@240Hz */ 968 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 969 798, 858, 0, 480, 489, 495, 525, 0, 970 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 971 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 972 /* 58 - 720(1440)x480i@240Hz */ 973 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 974 801, 858, 0, 480, 488, 494, 525, 0, 975 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 976 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 977 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 978 /* 59 - 720(1440)x480i@240Hz */ 979 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 980 801, 858, 0, 480, 488, 494, 525, 0, 981 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 982 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 983 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 984 /* 60 - 1280x720@24Hz */ 985 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 986 3080, 3300, 0, 720, 725, 730, 750, 0, 987 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 988 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 989 /* 61 - 1280x720@25Hz */ 990 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 991 3740, 3960, 0, 720, 725, 730, 750, 0, 992 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 993 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 994 /* 62 - 1280x720@30Hz */ 995 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 996 3080, 3300, 0, 720, 725, 730, 750, 0, 997 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 998 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 999 /* 63 - 1920x1080@120Hz */ 1000 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1001 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1002 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1003 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1004 /* 64 - 1920x1080@100Hz */ 1005 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1006 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1007 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1008 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1009 /* 65 - 1280x720@24Hz */ 1010 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1011 3080, 3300, 0, 720, 725, 730, 750, 0, 1012 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1013 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1014 /* 66 - 1280x720@25Hz */ 1015 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1016 3740, 3960, 0, 720, 725, 730, 750, 0, 1017 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1018 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1019 /* 67 - 1280x720@30Hz */ 1020 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1021 3080, 3300, 0, 720, 725, 730, 750, 0, 1022 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1023 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1024 /* 68 - 1280x720@50Hz */ 1025 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1026 1760, 1980, 0, 720, 725, 730, 750, 0, 1027 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1028 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1029 /* 69 - 1280x720@60Hz */ 1030 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1031 1430, 1650, 0, 720, 725, 730, 750, 0, 1032 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1033 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1034 /* 70 - 1280x720@100Hz */ 1035 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1036 1760, 1980, 0, 720, 725, 730, 750, 0, 1037 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1038 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1039 /* 71 - 1280x720@120Hz */ 1040 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1041 1430, 1650, 0, 720, 725, 730, 750, 0, 1042 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1043 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1044 /* 72 - 1920x1080@24Hz */ 1045 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1046 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1047 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1048 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1049 /* 73 - 1920x1080@25Hz */ 1050 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1051 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1052 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1053 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1054 /* 74 - 1920x1080@30Hz */ 1055 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1056 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1057 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1058 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1059 /* 75 - 1920x1080@50Hz */ 1060 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1061 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1062 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1063 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1064 /* 76 - 1920x1080@60Hz */ 1065 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1066 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1067 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1068 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1069 /* 77 - 1920x1080@100Hz */ 1070 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1071 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1072 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1073 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1074 /* 78 - 1920x1080@120Hz */ 1075 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1076 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1077 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1078 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1079 /* 79 - 1680x720@24Hz */ 1080 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 1081 3080, 3300, 0, 720, 725, 730, 750, 0, 1082 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1083 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1084 /* 80 - 1680x720@25Hz */ 1085 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 1086 2948, 3168, 0, 720, 725, 730, 750, 0, 1087 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1088 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1089 /* 81 - 1680x720@30Hz */ 1090 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 1091 2420, 2640, 0, 720, 725, 730, 750, 0, 1092 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1093 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1094 /* 82 - 1680x720@50Hz */ 1095 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1096 1980, 2200, 0, 720, 725, 730, 750, 0, 1097 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1098 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1099 /* 83 - 1680x720@60Hz */ 1100 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1101 1980, 2200, 0, 720, 725, 730, 750, 0, 1102 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1103 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1104 /* 84 - 1680x720@100Hz */ 1105 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1106 1780, 2000, 0, 720, 725, 730, 825, 0, 1107 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1108 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1109 /* 85 - 1680x720@120Hz */ 1110 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1111 1780, 2000, 0, 720, 725, 730, 825, 0, 1112 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1113 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1114 /* 86 - 2560x1080@24Hz */ 1115 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 1116 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1117 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1118 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1119 /* 87 - 2560x1080@25Hz */ 1120 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 1121 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, 1122 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1123 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1124 /* 88 - 2560x1080@30Hz */ 1125 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 1126 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, 1127 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1128 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1129 /* 89 - 2560x1080@50Hz */ 1130 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 1131 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, 1132 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1133 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1134 /* 90 - 2560x1080@60Hz */ 1135 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 1136 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, 1137 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1138 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1139 /* 91 - 2560x1080@100Hz */ 1140 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 1141 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, 1142 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1143 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1144 /* 92 - 2560x1080@120Hz */ 1145 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 1146 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, 1147 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1148 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1149 /* 93 - 3840x2160p@24Hz 16:9 */ 1150 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1151 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1152 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1153 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1154 /* 94 - 3840x2160p@25Hz 16:9 */ 1155 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1156 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1157 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1158 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1159 /* 95 - 3840x2160p@30Hz 16:9 */ 1160 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1161 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1162 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1163 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1164 /* 96 - 3840x2160p@50Hz 16:9 */ 1165 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1166 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1167 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1168 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1169 /* 97 - 3840x2160p@60Hz 16:9 */ 1170 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1171 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1172 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1173 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1174 /* 98 - 4096x2160p@24Hz 256:135 */ 1175 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1176 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1177 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1178 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1179 /* 99 - 4096x2160p@25Hz 256:135 */ 1180 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1181 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1182 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1183 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1184 /* 100 - 4096x2160p@30Hz 256:135 */ 1185 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1186 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1187 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1188 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1189 /* 101 - 4096x2160p@50Hz 256:135 */ 1190 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1191 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1192 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1193 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1194 /* 102 - 4096x2160p@60Hz 256:135 */ 1195 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1196 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1197 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1198 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1199 /* 103 - 3840x2160p@24Hz 64:27 */ 1200 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1201 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1202 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1203 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1204 /* 104 - 3840x2160p@25Hz 64:27 */ 1205 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1206 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1207 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1208 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1209 /* 105 - 3840x2160p@30Hz 64:27 */ 1210 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1211 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1212 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1213 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1214 /* 106 - 3840x2160p@50Hz 64:27 */ 1215 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1216 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1217 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1218 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1219 /* 107 - 3840x2160p@60Hz 64:27 */ 1220 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1221 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1223 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1224 }; 1225 1226 /* 1227 * HDMI 1.4 4k modes. Index using the VIC. 1228 */ 1229 static const struct drm_display_mode edid_4k_modes[] = { 1230 /* 0 - dummy, VICs start at 1 */ 1231 { }, 1232 /* 1 - 3840x2160@30Hz */ 1233 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1234 3840, 4016, 4104, 4400, 0, 1235 2160, 2168, 2178, 2250, 0, 1236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1237 .vrefresh = 30, }, 1238 /* 2 - 3840x2160@25Hz */ 1239 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1240 3840, 4896, 4984, 5280, 0, 1241 2160, 2168, 2178, 2250, 0, 1242 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1243 .vrefresh = 25, }, 1244 /* 3 - 3840x2160@24Hz */ 1245 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1246 3840, 5116, 5204, 5500, 0, 1247 2160, 2168, 2178, 2250, 0, 1248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1249 .vrefresh = 24, }, 1250 /* 4 - 4096x2160@24Hz (SMPTE) */ 1251 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1252 4096, 5116, 5204, 5500, 0, 1253 2160, 2168, 2178, 2250, 0, 1254 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1255 .vrefresh = 24, }, 1256 }; 1257 1258 /*** DDC fetch and block validation ***/ 1259 1260 static const u8 edid_header[] = { 1261 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1262 }; 1263 1264 /** 1265 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1266 * @raw_edid: pointer to raw base EDID block 1267 * 1268 * Sanity check the header of the base EDID block. 1269 * 1270 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1271 */ 1272 int drm_edid_header_is_valid(const u8 *raw_edid) 1273 { 1274 int i, score = 0; 1275 1276 for (i = 0; i < sizeof(edid_header); i++) 1277 if (raw_edid[i] == edid_header[i]) 1278 score++; 1279 1280 return score; 1281 } 1282 EXPORT_SYMBOL(drm_edid_header_is_valid); 1283 1284 static int edid_fixup __read_mostly = 6; 1285 module_param_named(edid_fixup, edid_fixup, int, 0400); 1286 MODULE_PARM_DESC(edid_fixup, 1287 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1288 1289 static void drm_get_displayid(struct drm_connector *connector, 1290 struct edid *edid); 1291 1292 static int drm_edid_block_checksum(const u8 *raw_edid) 1293 { 1294 int i; 1295 u8 csum = 0; 1296 for (i = 0; i < EDID_LENGTH; i++) 1297 csum += raw_edid[i]; 1298 1299 return csum; 1300 } 1301 1302 static bool drm_edid_is_zero(const u8 *in_edid, int length) 1303 { 1304 if (memchr_inv(in_edid, 0, length)) 1305 return false; 1306 1307 return true; 1308 } 1309 1310 /** 1311 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1312 * @raw_edid: pointer to raw EDID block 1313 * @block: type of block to validate (0 for base, extension otherwise) 1314 * @print_bad_edid: if true, dump bad EDID blocks to the console 1315 * @edid_corrupt: if true, the header or checksum is invalid 1316 * 1317 * Validate a base or extension EDID block and optionally dump bad blocks to 1318 * the console. 1319 * 1320 * Return: True if the block is valid, false otherwise. 1321 */ 1322 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 1323 bool *edid_corrupt) 1324 { 1325 u8 csum; 1326 struct edid *edid = (struct edid *)raw_edid; 1327 1328 if (WARN_ON(!raw_edid)) 1329 return false; 1330 1331 if (edid_fixup > 8 || edid_fixup < 0) 1332 edid_fixup = 6; 1333 1334 if (block == 0) { 1335 int score = drm_edid_header_is_valid(raw_edid); 1336 if (score == 8) { 1337 if (edid_corrupt) 1338 *edid_corrupt = false; 1339 } else if (score >= edid_fixup) { 1340 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 1341 * The corrupt flag needs to be set here otherwise, the 1342 * fix-up code here will correct the problem, the 1343 * checksum is correct and the test fails 1344 */ 1345 if (edid_corrupt) 1346 *edid_corrupt = true; 1347 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1348 memcpy(raw_edid, edid_header, sizeof(edid_header)); 1349 } else { 1350 if (edid_corrupt) 1351 *edid_corrupt = true; 1352 goto bad; 1353 } 1354 } 1355 1356 csum = drm_edid_block_checksum(raw_edid); 1357 if (csum) { 1358 if (edid_corrupt) 1359 *edid_corrupt = true; 1360 1361 /* allow CEA to slide through, switches mangle this */ 1362 if (raw_edid[0] == CEA_EXT) { 1363 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum); 1364 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n"); 1365 } else { 1366 if (print_bad_edid) 1367 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum); 1368 1369 goto bad; 1370 } 1371 } 1372 1373 /* per-block-type checks */ 1374 switch (raw_edid[0]) { 1375 case 0: /* base */ 1376 if (edid->version != 1) { 1377 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version); 1378 goto bad; 1379 } 1380 1381 if (edid->revision > 4) 1382 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1383 break; 1384 1385 default: 1386 break; 1387 } 1388 1389 return true; 1390 1391 bad: 1392 if (print_bad_edid) { 1393 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) { 1394 pr_notice("EDID block is all zeroes\n"); 1395 } else { 1396 pr_notice("Raw EDID:\n"); 1397 print_hex_dump(KERN_NOTICE, 1398 " \t", DUMP_PREFIX_NONE, 16, 1, 1399 raw_edid, EDID_LENGTH, false); 1400 } 1401 } 1402 return false; 1403 } 1404 EXPORT_SYMBOL(drm_edid_block_valid); 1405 1406 /** 1407 * drm_edid_is_valid - sanity check EDID data 1408 * @edid: EDID data 1409 * 1410 * Sanity-check an entire EDID record (including extensions) 1411 * 1412 * Return: True if the EDID data is valid, false otherwise. 1413 */ 1414 bool drm_edid_is_valid(struct edid *edid) 1415 { 1416 int i; 1417 u8 *raw = (u8 *)edid; 1418 1419 if (!edid) 1420 return false; 1421 1422 for (i = 0; i <= edid->extensions; i++) 1423 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL)) 1424 return false; 1425 1426 return true; 1427 } 1428 EXPORT_SYMBOL(drm_edid_is_valid); 1429 1430 #define DDC_SEGMENT_ADDR 0x30 1431 /** 1432 * drm_do_probe_ddc_edid() - get EDID information via I2C 1433 * @data: I2C device adapter 1434 * @buf: EDID data buffer to be filled 1435 * @block: 128 byte EDID block to start fetching from 1436 * @len: EDID data buffer length to fetch 1437 * 1438 * Try to fetch EDID information by calling I2C driver functions. 1439 * 1440 * Return: 0 on success or -1 on failure. 1441 */ 1442 static int 1443 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 1444 { 1445 struct i2c_adapter *adapter = data; 1446 unsigned char start = block * EDID_LENGTH; 1447 unsigned char segment = block >> 1; 1448 unsigned char xfers = segment ? 3 : 2; 1449 int ret, retries = 5; 1450 1451 /* 1452 * The core I2C driver will automatically retry the transfer if the 1453 * adapter reports EAGAIN. However, we find that bit-banging transfers 1454 * are susceptible to errors under a heavily loaded machine and 1455 * generate spurious NAKs and timeouts. Retrying the transfer 1456 * of the individual block a few times seems to overcome this. 1457 */ 1458 do { 1459 struct i2c_msg msgs[] = { 1460 { 1461 .addr = DDC_SEGMENT_ADDR, 1462 .flags = 0, 1463 .len = 1, 1464 .buf = &segment, 1465 }, { 1466 .addr = DDC_ADDR, 1467 .flags = 0, 1468 .len = 1, 1469 .buf = &start, 1470 }, { 1471 .addr = DDC_ADDR, 1472 .flags = I2C_M_RD, 1473 .len = len, 1474 .buf = buf, 1475 } 1476 }; 1477 1478 /* 1479 * Avoid sending the segment addr to not upset non-compliant 1480 * DDC monitors. 1481 */ 1482 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 1483 1484 if (ret == -ENXIO) { 1485 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 1486 adapter->name); 1487 break; 1488 } 1489 } while (ret != xfers && --retries); 1490 1491 return ret == xfers ? 0 : -1; 1492 } 1493 1494 static void connector_bad_edid(struct drm_connector *connector, 1495 u8 *edid, int num_blocks) 1496 { 1497 int i; 1498 1499 if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS)) 1500 return; 1501 1502 dev_warn(connector->dev->dev, 1503 "%s: EDID is invalid:\n", 1504 connector->name); 1505 for (i = 0; i < num_blocks; i++) { 1506 u8 *block = edid + i * EDID_LENGTH; 1507 char prefix[20]; 1508 1509 if (drm_edid_is_zero(block, EDID_LENGTH)) 1510 sprintf(prefix, "\t[%02x] ZERO ", i); 1511 else if (!drm_edid_block_valid(block, i, false, NULL)) 1512 sprintf(prefix, "\t[%02x] BAD ", i); 1513 else 1514 sprintf(prefix, "\t[%02x] GOOD ", i); 1515 1516 print_hex_dump(KERN_WARNING, 1517 prefix, DUMP_PREFIX_NONE, 16, 1, 1518 block, EDID_LENGTH, false); 1519 } 1520 } 1521 1522 /** 1523 * drm_do_get_edid - get EDID data using a custom EDID block read function 1524 * @connector: connector we're probing 1525 * @get_edid_block: EDID block read function 1526 * @data: private data passed to the block read function 1527 * 1528 * When the I2C adapter connected to the DDC bus is hidden behind a device that 1529 * exposes a different interface to read EDID blocks this function can be used 1530 * to get EDID data using a custom block read function. 1531 * 1532 * As in the general case the DDC bus is accessible by the kernel at the I2C 1533 * level, drivers must make all reasonable efforts to expose it as an I2C 1534 * adapter and use drm_get_edid() instead of abusing this function. 1535 * 1536 * The EDID may be overridden using debugfs override_edid or firmare EDID 1537 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority 1538 * order. Having either of them bypasses actual EDID reads. 1539 * 1540 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1541 */ 1542 struct edid *drm_do_get_edid(struct drm_connector *connector, 1543 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 1544 size_t len), 1545 void *data) 1546 { 1547 int i, j = 0, valid_extensions = 0; 1548 u8 *edid, *new; 1549 struct edid *override = NULL; 1550 1551 if (connector->override_edid) 1552 override = drm_edid_duplicate((const struct edid *) 1553 connector->edid_blob_ptr->data); 1554 1555 if (!override) 1556 override = drm_load_edid_firmware(connector); 1557 1558 if (!IS_ERR_OR_NULL(override)) 1559 return override; 1560 1561 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) 1562 return NULL; 1563 1564 /* base block fetch */ 1565 for (i = 0; i < 4; i++) { 1566 if (get_edid_block(data, edid, 0, EDID_LENGTH)) 1567 goto out; 1568 if (drm_edid_block_valid(edid, 0, false, 1569 &connector->edid_corrupt)) 1570 break; 1571 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) { 1572 connector->null_edid_counter++; 1573 goto carp; 1574 } 1575 } 1576 if (i == 4) 1577 goto carp; 1578 1579 /* if there's no extensions, we're done */ 1580 valid_extensions = edid[0x7e]; 1581 if (valid_extensions == 0) 1582 return (struct edid *)edid; 1583 1584 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1585 if (!new) 1586 goto out; 1587 edid = new; 1588 1589 for (j = 1; j <= edid[0x7e]; j++) { 1590 u8 *block = edid + j * EDID_LENGTH; 1591 1592 for (i = 0; i < 4; i++) { 1593 if (get_edid_block(data, block, j, EDID_LENGTH)) 1594 goto out; 1595 if (drm_edid_block_valid(block, j, false, NULL)) 1596 break; 1597 } 1598 1599 if (i == 4) 1600 valid_extensions--; 1601 } 1602 1603 if (valid_extensions != edid[0x7e]) { 1604 u8 *base; 1605 1606 connector_bad_edid(connector, edid, edid[0x7e] + 1); 1607 1608 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions; 1609 edid[0x7e] = valid_extensions; 1610 1611 new = kmalloc((valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1612 if (!new) 1613 goto out; 1614 1615 base = new; 1616 for (i = 0; i <= edid[0x7e]; i++) { 1617 u8 *block = edid + i * EDID_LENGTH; 1618 1619 if (!drm_edid_block_valid(block, i, false, NULL)) 1620 continue; 1621 1622 memcpy(base, block, EDID_LENGTH); 1623 base += EDID_LENGTH; 1624 } 1625 1626 kfree(edid); 1627 edid = new; 1628 } 1629 1630 return (struct edid *)edid; 1631 1632 carp: 1633 connector_bad_edid(connector, edid, 1); 1634 out: 1635 kfree(edid); 1636 return NULL; 1637 } 1638 EXPORT_SYMBOL_GPL(drm_do_get_edid); 1639 1640 /** 1641 * drm_probe_ddc() - probe DDC presence 1642 * @adapter: I2C adapter to probe 1643 * 1644 * Return: True on success, false on failure. 1645 */ 1646 bool 1647 drm_probe_ddc(struct i2c_adapter *adapter) 1648 { 1649 unsigned char out; 1650 1651 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 1652 } 1653 EXPORT_SYMBOL(drm_probe_ddc); 1654 1655 /** 1656 * drm_get_edid - get EDID data, if available 1657 * @connector: connector we're probing 1658 * @adapter: I2C adapter to use for DDC 1659 * 1660 * Poke the given I2C channel to grab EDID data if possible. If found, 1661 * attach it to the connector. 1662 * 1663 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1664 */ 1665 struct edid *drm_get_edid(struct drm_connector *connector, 1666 struct i2c_adapter *adapter) 1667 { 1668 struct edid *edid; 1669 1670 if (connector->force == DRM_FORCE_OFF) 1671 return NULL; 1672 1673 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 1674 return NULL; 1675 1676 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); 1677 if (edid) 1678 drm_get_displayid(connector, edid); 1679 return edid; 1680 } 1681 EXPORT_SYMBOL(drm_get_edid); 1682 1683 /** 1684 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 1685 * @connector: connector we're probing 1686 * @adapter: I2C adapter to use for DDC 1687 * 1688 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 1689 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 1690 * switch DDC to the GPU which is retrieving EDID. 1691 * 1692 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 1693 */ 1694 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 1695 struct i2c_adapter *adapter) 1696 { 1697 struct pci_dev *pdev = connector->dev->pdev; 1698 struct edid *edid; 1699 1700 vga_switcheroo_lock_ddc(pdev); 1701 edid = drm_get_edid(connector, adapter); 1702 vga_switcheroo_unlock_ddc(pdev); 1703 1704 return edid; 1705 } 1706 EXPORT_SYMBOL(drm_get_edid_switcheroo); 1707 1708 /** 1709 * drm_edid_duplicate - duplicate an EDID and the extensions 1710 * @edid: EDID to duplicate 1711 * 1712 * Return: Pointer to duplicated EDID or NULL on allocation failure. 1713 */ 1714 struct edid *drm_edid_duplicate(const struct edid *edid) 1715 { 1716 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1717 } 1718 EXPORT_SYMBOL(drm_edid_duplicate); 1719 1720 /*** EDID parsing ***/ 1721 1722 /** 1723 * edid_vendor - match a string against EDID's obfuscated vendor field 1724 * @edid: EDID to match 1725 * @vendor: vendor string 1726 * 1727 * Returns true if @vendor is in @edid, false otherwise 1728 */ 1729 static bool edid_vendor(struct edid *edid, const char *vendor) 1730 { 1731 char edid_vendor[3]; 1732 1733 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 1734 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 1735 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 1736 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 1737 1738 return !strncmp(edid_vendor, vendor, 3); 1739 } 1740 1741 /** 1742 * edid_get_quirks - return quirk flags for a given EDID 1743 * @edid: EDID to process 1744 * 1745 * This tells subsequent routines what fixes they need to apply. 1746 */ 1747 static u32 edid_get_quirks(struct edid *edid) 1748 { 1749 const struct edid_quirk *quirk; 1750 int i; 1751 1752 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 1753 quirk = &edid_quirk_list[i]; 1754 1755 if (edid_vendor(edid, quirk->vendor) && 1756 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 1757 return quirk->quirks; 1758 } 1759 1760 return 0; 1761 } 1762 1763 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 1764 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 1765 1766 /** 1767 * edid_fixup_preferred - set preferred modes based on quirk list 1768 * @connector: has mode list to fix up 1769 * @quirks: quirks list 1770 * 1771 * Walk the mode list for @connector, clearing the preferred status 1772 * on existing modes and setting it anew for the right mode ala @quirks. 1773 */ 1774 static void edid_fixup_preferred(struct drm_connector *connector, 1775 u32 quirks) 1776 { 1777 struct drm_display_mode *t, *cur_mode, *preferred_mode; 1778 int target_refresh = 0; 1779 int cur_vrefresh, preferred_vrefresh; 1780 1781 if (list_empty(&connector->probed_modes)) 1782 return; 1783 1784 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 1785 target_refresh = 60; 1786 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 1787 target_refresh = 75; 1788 1789 preferred_mode = list_first_entry(&connector->probed_modes, 1790 struct drm_display_mode, head); 1791 1792 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 1793 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 1794 1795 if (cur_mode == preferred_mode) 1796 continue; 1797 1798 /* Largest mode is preferred */ 1799 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 1800 preferred_mode = cur_mode; 1801 1802 cur_vrefresh = cur_mode->vrefresh ? 1803 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode); 1804 preferred_vrefresh = preferred_mode->vrefresh ? 1805 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode); 1806 /* At a given size, try to get closest to target refresh */ 1807 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 1808 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 1809 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 1810 preferred_mode = cur_mode; 1811 } 1812 } 1813 1814 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 1815 } 1816 1817 static bool 1818 mode_is_rb(const struct drm_display_mode *mode) 1819 { 1820 return (mode->htotal - mode->hdisplay == 160) && 1821 (mode->hsync_end - mode->hdisplay == 80) && 1822 (mode->hsync_end - mode->hsync_start == 32) && 1823 (mode->vsync_start - mode->vdisplay == 3); 1824 } 1825 1826 /* 1827 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 1828 * @dev: Device to duplicate against 1829 * @hsize: Mode width 1830 * @vsize: Mode height 1831 * @fresh: Mode refresh rate 1832 * @rb: Mode reduced-blanking-ness 1833 * 1834 * Walk the DMT mode list looking for a match for the given parameters. 1835 * 1836 * Return: A newly allocated copy of the mode, or NULL if not found. 1837 */ 1838 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 1839 int hsize, int vsize, int fresh, 1840 bool rb) 1841 { 1842 int i; 1843 1844 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 1845 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 1846 if (hsize != ptr->hdisplay) 1847 continue; 1848 if (vsize != ptr->vdisplay) 1849 continue; 1850 if (fresh != drm_mode_vrefresh(ptr)) 1851 continue; 1852 if (rb != mode_is_rb(ptr)) 1853 continue; 1854 1855 return drm_mode_duplicate(dev, ptr); 1856 } 1857 1858 return NULL; 1859 } 1860 EXPORT_SYMBOL(drm_mode_find_dmt); 1861 1862 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 1863 1864 static void 1865 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1866 { 1867 int i, n = 0; 1868 u8 d = ext[0x02]; 1869 u8 *det_base = ext + d; 1870 1871 n = (127 - d) / 18; 1872 for (i = 0; i < n; i++) 1873 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1874 } 1875 1876 static void 1877 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1878 { 1879 unsigned int i, n = min((int)ext[0x02], 6); 1880 u8 *det_base = ext + 5; 1881 1882 if (ext[0x01] != 1) 1883 return; /* unknown version */ 1884 1885 for (i = 0; i < n; i++) 1886 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1887 } 1888 1889 static void 1890 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 1891 { 1892 int i; 1893 struct edid *edid = (struct edid *)raw_edid; 1894 1895 if (edid == NULL) 1896 return; 1897 1898 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 1899 cb(&(edid->detailed_timings[i]), closure); 1900 1901 for (i = 1; i <= raw_edid[0x7e]; i++) { 1902 u8 *ext = raw_edid + (i * EDID_LENGTH); 1903 switch (*ext) { 1904 case CEA_EXT: 1905 cea_for_each_detailed_block(ext, cb, closure); 1906 break; 1907 case VTB_EXT: 1908 vtb_for_each_detailed_block(ext, cb, closure); 1909 break; 1910 default: 1911 break; 1912 } 1913 } 1914 } 1915 1916 static void 1917 is_rb(struct detailed_timing *t, void *data) 1918 { 1919 u8 *r = (u8 *)t; 1920 if (r[3] == EDID_DETAIL_MONITOR_RANGE) 1921 if (r[15] & 0x10) 1922 *(bool *)data = true; 1923 } 1924 1925 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 1926 static bool 1927 drm_monitor_supports_rb(struct edid *edid) 1928 { 1929 if (edid->revision >= 4) { 1930 bool ret = false; 1931 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 1932 return ret; 1933 } 1934 1935 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 1936 } 1937 1938 static void 1939 find_gtf2(struct detailed_timing *t, void *data) 1940 { 1941 u8 *r = (u8 *)t; 1942 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) 1943 *(u8 **)data = r; 1944 } 1945 1946 /* Secondary GTF curve kicks in above some break frequency */ 1947 static int 1948 drm_gtf2_hbreak(struct edid *edid) 1949 { 1950 u8 *r = NULL; 1951 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1952 return r ? (r[12] * 2) : 0; 1953 } 1954 1955 static int 1956 drm_gtf2_2c(struct edid *edid) 1957 { 1958 u8 *r = NULL; 1959 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1960 return r ? r[13] : 0; 1961 } 1962 1963 static int 1964 drm_gtf2_m(struct edid *edid) 1965 { 1966 u8 *r = NULL; 1967 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1968 return r ? (r[15] << 8) + r[14] : 0; 1969 } 1970 1971 static int 1972 drm_gtf2_k(struct edid *edid) 1973 { 1974 u8 *r = NULL; 1975 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1976 return r ? r[16] : 0; 1977 } 1978 1979 static int 1980 drm_gtf2_2j(struct edid *edid) 1981 { 1982 u8 *r = NULL; 1983 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1984 return r ? r[17] : 0; 1985 } 1986 1987 /** 1988 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 1989 * @edid: EDID block to scan 1990 */ 1991 static int standard_timing_level(struct edid *edid) 1992 { 1993 if (edid->revision >= 2) { 1994 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 1995 return LEVEL_CVT; 1996 if (drm_gtf2_hbreak(edid)) 1997 return LEVEL_GTF2; 1998 return LEVEL_GTF; 1999 } 2000 return LEVEL_DMT; 2001 } 2002 2003 /* 2004 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 2005 * monitors fill with ascii space (0x20) instead. 2006 */ 2007 static int 2008 bad_std_timing(u8 a, u8 b) 2009 { 2010 return (a == 0x00 && b == 0x00) || 2011 (a == 0x01 && b == 0x01) || 2012 (a == 0x20 && b == 0x20); 2013 } 2014 2015 /** 2016 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 2017 * @connector: connector of for the EDID block 2018 * @edid: EDID block to scan 2019 * @t: standard timing params 2020 * 2021 * Take the standard timing params (in this case width, aspect, and refresh) 2022 * and convert them into a real mode using CVT/GTF/DMT. 2023 */ 2024 static struct drm_display_mode * 2025 drm_mode_std(struct drm_connector *connector, struct edid *edid, 2026 struct std_timing *t) 2027 { 2028 struct drm_device *dev = connector->dev; 2029 struct drm_display_mode *m, *mode = NULL; 2030 int hsize, vsize; 2031 int vrefresh_rate; 2032 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 2033 >> EDID_TIMING_ASPECT_SHIFT; 2034 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 2035 >> EDID_TIMING_VFREQ_SHIFT; 2036 int timing_level = standard_timing_level(edid); 2037 2038 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 2039 return NULL; 2040 2041 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 2042 hsize = t->hsize * 8 + 248; 2043 /* vrefresh_rate = vfreq + 60 */ 2044 vrefresh_rate = vfreq + 60; 2045 /* the vdisplay is calculated based on the aspect ratio */ 2046 if (aspect_ratio == 0) { 2047 if (edid->revision < 3) 2048 vsize = hsize; 2049 else 2050 vsize = (hsize * 10) / 16; 2051 } else if (aspect_ratio == 1) 2052 vsize = (hsize * 3) / 4; 2053 else if (aspect_ratio == 2) 2054 vsize = (hsize * 4) / 5; 2055 else 2056 vsize = (hsize * 9) / 16; 2057 2058 /* HDTV hack, part 1 */ 2059 if (vrefresh_rate == 60 && 2060 ((hsize == 1360 && vsize == 765) || 2061 (hsize == 1368 && vsize == 769))) { 2062 hsize = 1366; 2063 vsize = 768; 2064 } 2065 2066 /* 2067 * If this connector already has a mode for this size and refresh 2068 * rate (because it came from detailed or CVT info), use that 2069 * instead. This way we don't have to guess at interlace or 2070 * reduced blanking. 2071 */ 2072 list_for_each_entry(m, &connector->probed_modes, head) 2073 if (m->hdisplay == hsize && m->vdisplay == vsize && 2074 drm_mode_vrefresh(m) == vrefresh_rate) 2075 return NULL; 2076 2077 /* HDTV hack, part 2 */ 2078 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 2079 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 2080 false); 2081 mode->hdisplay = 1366; 2082 mode->hsync_start = mode->hsync_start - 1; 2083 mode->hsync_end = mode->hsync_end - 1; 2084 return mode; 2085 } 2086 2087 /* check whether it can be found in default mode table */ 2088 if (drm_monitor_supports_rb(edid)) { 2089 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 2090 true); 2091 if (mode) 2092 return mode; 2093 } 2094 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 2095 if (mode) 2096 return mode; 2097 2098 /* okay, generate it */ 2099 switch (timing_level) { 2100 case LEVEL_DMT: 2101 break; 2102 case LEVEL_GTF: 2103 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2104 break; 2105 case LEVEL_GTF2: 2106 /* 2107 * This is potentially wrong if there's ever a monitor with 2108 * more than one ranges section, each claiming a different 2109 * secondary GTF curve. Please don't do that. 2110 */ 2111 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2112 if (!mode) 2113 return NULL; 2114 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 2115 drm_mode_destroy(dev, mode); 2116 mode = drm_gtf_mode_complex(dev, hsize, vsize, 2117 vrefresh_rate, 0, 0, 2118 drm_gtf2_m(edid), 2119 drm_gtf2_2c(edid), 2120 drm_gtf2_k(edid), 2121 drm_gtf2_2j(edid)); 2122 } 2123 break; 2124 case LEVEL_CVT: 2125 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 2126 false); 2127 break; 2128 } 2129 return mode; 2130 } 2131 2132 /* 2133 * EDID is delightfully ambiguous about how interlaced modes are to be 2134 * encoded. Our internal representation is of frame height, but some 2135 * HDTV detailed timings are encoded as field height. 2136 * 2137 * The format list here is from CEA, in frame size. Technically we 2138 * should be checking refresh rate too. Whatever. 2139 */ 2140 static void 2141 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 2142 struct detailed_pixel_timing *pt) 2143 { 2144 int i; 2145 static const struct { 2146 int w, h; 2147 } cea_interlaced[] = { 2148 { 1920, 1080 }, 2149 { 720, 480 }, 2150 { 1440, 480 }, 2151 { 2880, 480 }, 2152 { 720, 576 }, 2153 { 1440, 576 }, 2154 { 2880, 576 }, 2155 }; 2156 2157 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 2158 return; 2159 2160 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 2161 if ((mode->hdisplay == cea_interlaced[i].w) && 2162 (mode->vdisplay == cea_interlaced[i].h / 2)) { 2163 mode->vdisplay *= 2; 2164 mode->vsync_start *= 2; 2165 mode->vsync_end *= 2; 2166 mode->vtotal *= 2; 2167 mode->vtotal |= 1; 2168 } 2169 } 2170 2171 mode->flags |= DRM_MODE_FLAG_INTERLACE; 2172 } 2173 2174 /** 2175 * drm_mode_detailed - create a new mode from an EDID detailed timing section 2176 * @dev: DRM device (needed to create new mode) 2177 * @edid: EDID block 2178 * @timing: EDID detailed timing info 2179 * @quirks: quirks to apply 2180 * 2181 * An EDID detailed timing block contains enough info for us to create and 2182 * return a new struct drm_display_mode. 2183 */ 2184 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 2185 struct edid *edid, 2186 struct detailed_timing *timing, 2187 u32 quirks) 2188 { 2189 struct drm_display_mode *mode; 2190 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 2191 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 2192 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 2193 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 2194 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 2195 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 2196 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 2197 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 2198 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 2199 2200 /* ignore tiny modes */ 2201 if (hactive < 64 || vactive < 64) 2202 return NULL; 2203 2204 if (pt->misc & DRM_EDID_PT_STEREO) { 2205 DRM_DEBUG_KMS("stereo mode not supported\n"); 2206 return NULL; 2207 } 2208 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 2209 DRM_DEBUG_KMS("composite sync not supported\n"); 2210 } 2211 2212 /* it is incorrect if hsync/vsync width is zero */ 2213 if (!hsync_pulse_width || !vsync_pulse_width) { 2214 DRM_DEBUG_KMS("Incorrect Detailed timing. " 2215 "Wrong Hsync/Vsync pulse width\n"); 2216 return NULL; 2217 } 2218 2219 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 2220 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 2221 if (!mode) 2222 return NULL; 2223 2224 goto set_size; 2225 } 2226 2227 mode = drm_mode_create(dev); 2228 if (!mode) 2229 return NULL; 2230 2231 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 2232 timing->pixel_clock = cpu_to_le16(1088); 2233 2234 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 2235 2236 mode->hdisplay = hactive; 2237 mode->hsync_start = mode->hdisplay + hsync_offset; 2238 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 2239 mode->htotal = mode->hdisplay + hblank; 2240 2241 mode->vdisplay = vactive; 2242 mode->vsync_start = mode->vdisplay + vsync_offset; 2243 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 2244 mode->vtotal = mode->vdisplay + vblank; 2245 2246 /* Some EDIDs have bogus h/vtotal values */ 2247 if (mode->hsync_end > mode->htotal) 2248 mode->htotal = mode->hsync_end + 1; 2249 if (mode->vsync_end > mode->vtotal) 2250 mode->vtotal = mode->vsync_end + 1; 2251 2252 drm_mode_do_interlace_quirk(mode, pt); 2253 2254 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 2255 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; 2256 } 2257 2258 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 2259 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 2260 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 2261 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 2262 2263 set_size: 2264 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 2265 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 2266 2267 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 2268 mode->width_mm *= 10; 2269 mode->height_mm *= 10; 2270 } 2271 2272 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 2273 mode->width_mm = edid->width_cm * 10; 2274 mode->height_mm = edid->height_cm * 10; 2275 } 2276 2277 mode->type = DRM_MODE_TYPE_DRIVER; 2278 mode->vrefresh = drm_mode_vrefresh(mode); 2279 drm_mode_set_name(mode); 2280 2281 return mode; 2282 } 2283 2284 static bool 2285 mode_in_hsync_range(const struct drm_display_mode *mode, 2286 struct edid *edid, u8 *t) 2287 { 2288 int hsync, hmin, hmax; 2289 2290 hmin = t[7]; 2291 if (edid->revision >= 4) 2292 hmin += ((t[4] & 0x04) ? 255 : 0); 2293 hmax = t[8]; 2294 if (edid->revision >= 4) 2295 hmax += ((t[4] & 0x08) ? 255 : 0); 2296 hsync = drm_mode_hsync(mode); 2297 2298 return (hsync <= hmax && hsync >= hmin); 2299 } 2300 2301 static bool 2302 mode_in_vsync_range(const struct drm_display_mode *mode, 2303 struct edid *edid, u8 *t) 2304 { 2305 int vsync, vmin, vmax; 2306 2307 vmin = t[5]; 2308 if (edid->revision >= 4) 2309 vmin += ((t[4] & 0x01) ? 255 : 0); 2310 vmax = t[6]; 2311 if (edid->revision >= 4) 2312 vmax += ((t[4] & 0x02) ? 255 : 0); 2313 vsync = drm_mode_vrefresh(mode); 2314 2315 return (vsync <= vmax && vsync >= vmin); 2316 } 2317 2318 static u32 2319 range_pixel_clock(struct edid *edid, u8 *t) 2320 { 2321 /* unspecified */ 2322 if (t[9] == 0 || t[9] == 255) 2323 return 0; 2324 2325 /* 1.4 with CVT support gives us real precision, yay */ 2326 if (edid->revision >= 4 && t[10] == 0x04) 2327 return (t[9] * 10000) - ((t[12] >> 2) * 250); 2328 2329 /* 1.3 is pathetic, so fuzz up a bit */ 2330 return t[9] * 10000 + 5001; 2331 } 2332 2333 static bool 2334 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 2335 struct detailed_timing *timing) 2336 { 2337 u32 max_clock; 2338 u8 *t = (u8 *)timing; 2339 2340 if (!mode_in_hsync_range(mode, edid, t)) 2341 return false; 2342 2343 if (!mode_in_vsync_range(mode, edid, t)) 2344 return false; 2345 2346 if ((max_clock = range_pixel_clock(edid, t))) 2347 if (mode->clock > max_clock) 2348 return false; 2349 2350 /* 1.4 max horizontal check */ 2351 if (edid->revision >= 4 && t[10] == 0x04) 2352 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 2353 return false; 2354 2355 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 2356 return false; 2357 2358 return true; 2359 } 2360 2361 static bool valid_inferred_mode(const struct drm_connector *connector, 2362 const struct drm_display_mode *mode) 2363 { 2364 const struct drm_display_mode *m; 2365 bool ok = false; 2366 2367 list_for_each_entry(m, &connector->probed_modes, head) { 2368 if (mode->hdisplay == m->hdisplay && 2369 mode->vdisplay == m->vdisplay && 2370 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 2371 return false; /* duplicated */ 2372 if (mode->hdisplay <= m->hdisplay && 2373 mode->vdisplay <= m->vdisplay) 2374 ok = true; 2375 } 2376 return ok; 2377 } 2378 2379 static int 2380 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2381 struct detailed_timing *timing) 2382 { 2383 int i, modes = 0; 2384 struct drm_display_mode *newmode; 2385 struct drm_device *dev = connector->dev; 2386 2387 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2388 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 2389 valid_inferred_mode(connector, drm_dmt_modes + i)) { 2390 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 2391 if (newmode) { 2392 drm_mode_probed_add(connector, newmode); 2393 modes++; 2394 } 2395 } 2396 } 2397 2398 return modes; 2399 } 2400 2401 /* fix up 1366x768 mode from 1368x768; 2402 * GFT/CVT can't express 1366 width which isn't dividable by 8 2403 */ 2404 void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 2405 { 2406 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 2407 mode->hdisplay = 1366; 2408 mode->hsync_start--; 2409 mode->hsync_end--; 2410 drm_mode_set_name(mode); 2411 } 2412 } 2413 2414 static int 2415 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, 2416 struct detailed_timing *timing) 2417 { 2418 int i, modes = 0; 2419 struct drm_display_mode *newmode; 2420 struct drm_device *dev = connector->dev; 2421 2422 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2423 const struct minimode *m = &extra_modes[i]; 2424 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 2425 if (!newmode) 2426 return modes; 2427 2428 drm_mode_fixup_1366x768(newmode); 2429 if (!mode_in_range(newmode, edid, timing) || 2430 !valid_inferred_mode(connector, newmode)) { 2431 drm_mode_destroy(dev, newmode); 2432 continue; 2433 } 2434 2435 drm_mode_probed_add(connector, newmode); 2436 modes++; 2437 } 2438 2439 return modes; 2440 } 2441 2442 static int 2443 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2444 struct detailed_timing *timing) 2445 { 2446 int i, modes = 0; 2447 struct drm_display_mode *newmode; 2448 struct drm_device *dev = connector->dev; 2449 bool rb = drm_monitor_supports_rb(edid); 2450 2451 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2452 const struct minimode *m = &extra_modes[i]; 2453 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 2454 if (!newmode) 2455 return modes; 2456 2457 drm_mode_fixup_1366x768(newmode); 2458 if (!mode_in_range(newmode, edid, timing) || 2459 !valid_inferred_mode(connector, newmode)) { 2460 drm_mode_destroy(dev, newmode); 2461 continue; 2462 } 2463 2464 drm_mode_probed_add(connector, newmode); 2465 modes++; 2466 } 2467 2468 return modes; 2469 } 2470 2471 static void 2472 do_inferred_modes(struct detailed_timing *timing, void *c) 2473 { 2474 struct detailed_mode_closure *closure = c; 2475 struct detailed_non_pixel *data = &timing->data.other_data; 2476 struct detailed_data_monitor_range *range = &data->data.range; 2477 2478 if (data->type != EDID_DETAIL_MONITOR_RANGE) 2479 return; 2480 2481 closure->modes += drm_dmt_modes_for_range(closure->connector, 2482 closure->edid, 2483 timing); 2484 2485 if (!version_greater(closure->edid, 1, 1)) 2486 return; /* GTF not defined yet */ 2487 2488 switch (range->flags) { 2489 case 0x02: /* secondary gtf, XXX could do more */ 2490 case 0x00: /* default gtf */ 2491 closure->modes += drm_gtf_modes_for_range(closure->connector, 2492 closure->edid, 2493 timing); 2494 break; 2495 case 0x04: /* cvt, only in 1.4+ */ 2496 if (!version_greater(closure->edid, 1, 3)) 2497 break; 2498 2499 closure->modes += drm_cvt_modes_for_range(closure->connector, 2500 closure->edid, 2501 timing); 2502 break; 2503 case 0x01: /* just the ranges, no formula */ 2504 default: 2505 break; 2506 } 2507 } 2508 2509 static int 2510 add_inferred_modes(struct drm_connector *connector, struct edid *edid) 2511 { 2512 struct detailed_mode_closure closure = { 2513 .connector = connector, 2514 .edid = edid, 2515 }; 2516 2517 if (version_greater(edid, 1, 0)) 2518 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 2519 &closure); 2520 2521 return closure.modes; 2522 } 2523 2524 static int 2525 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 2526 { 2527 int i, j, m, modes = 0; 2528 struct drm_display_mode *mode; 2529 u8 *est = ((u8 *)timing) + 6; 2530 2531 for (i = 0; i < 6; i++) { 2532 for (j = 7; j >= 0; j--) { 2533 m = (i * 8) + (7 - j); 2534 if (m >= ARRAY_SIZE(est3_modes)) 2535 break; 2536 if (est[i] & (1 << j)) { 2537 mode = drm_mode_find_dmt(connector->dev, 2538 est3_modes[m].w, 2539 est3_modes[m].h, 2540 est3_modes[m].r, 2541 est3_modes[m].rb); 2542 if (mode) { 2543 drm_mode_probed_add(connector, mode); 2544 modes++; 2545 } 2546 } 2547 } 2548 } 2549 2550 return modes; 2551 } 2552 2553 static void 2554 do_established_modes(struct detailed_timing *timing, void *c) 2555 { 2556 struct detailed_mode_closure *closure = c; 2557 struct detailed_non_pixel *data = &timing->data.other_data; 2558 2559 if (data->type == EDID_DETAIL_EST_TIMINGS) 2560 closure->modes += drm_est3_modes(closure->connector, timing); 2561 } 2562 2563 /** 2564 * add_established_modes - get est. modes from EDID and add them 2565 * @connector: connector to add mode(s) to 2566 * @edid: EDID block to scan 2567 * 2568 * Each EDID block contains a bitmap of the supported "established modes" list 2569 * (defined above). Tease them out and add them to the global modes list. 2570 */ 2571 static int 2572 add_established_modes(struct drm_connector *connector, struct edid *edid) 2573 { 2574 struct drm_device *dev = connector->dev; 2575 unsigned long est_bits = edid->established_timings.t1 | 2576 (edid->established_timings.t2 << 8) | 2577 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 2578 int i, modes = 0; 2579 struct detailed_mode_closure closure = { 2580 .connector = connector, 2581 .edid = edid, 2582 }; 2583 2584 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 2585 if (est_bits & (1<<i)) { 2586 struct drm_display_mode *newmode; 2587 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 2588 if (newmode) { 2589 drm_mode_probed_add(connector, newmode); 2590 modes++; 2591 } 2592 } 2593 } 2594 2595 if (version_greater(edid, 1, 0)) 2596 drm_for_each_detailed_block((u8 *)edid, 2597 do_established_modes, &closure); 2598 2599 return modes + closure.modes; 2600 } 2601 2602 static void 2603 do_standard_modes(struct detailed_timing *timing, void *c) 2604 { 2605 struct detailed_mode_closure *closure = c; 2606 struct detailed_non_pixel *data = &timing->data.other_data; 2607 struct drm_connector *connector = closure->connector; 2608 struct edid *edid = closure->edid; 2609 2610 if (data->type == EDID_DETAIL_STD_MODES) { 2611 int i; 2612 for (i = 0; i < 6; i++) { 2613 struct std_timing *std; 2614 struct drm_display_mode *newmode; 2615 2616 std = &data->data.timings[i]; 2617 newmode = drm_mode_std(connector, edid, std); 2618 if (newmode) { 2619 drm_mode_probed_add(connector, newmode); 2620 closure->modes++; 2621 } 2622 } 2623 } 2624 } 2625 2626 /** 2627 * add_standard_modes - get std. modes from EDID and add them 2628 * @connector: connector to add mode(s) to 2629 * @edid: EDID block to scan 2630 * 2631 * Standard modes can be calculated using the appropriate standard (DMT, 2632 * GTF or CVT. Grab them from @edid and add them to the list. 2633 */ 2634 static int 2635 add_standard_modes(struct drm_connector *connector, struct edid *edid) 2636 { 2637 int i, modes = 0; 2638 struct detailed_mode_closure closure = { 2639 .connector = connector, 2640 .edid = edid, 2641 }; 2642 2643 for (i = 0; i < EDID_STD_TIMINGS; i++) { 2644 struct drm_display_mode *newmode; 2645 2646 newmode = drm_mode_std(connector, edid, 2647 &edid->standard_timings[i]); 2648 if (newmode) { 2649 drm_mode_probed_add(connector, newmode); 2650 modes++; 2651 } 2652 } 2653 2654 if (version_greater(edid, 1, 0)) 2655 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 2656 &closure); 2657 2658 /* XXX should also look for standard codes in VTB blocks */ 2659 2660 return modes + closure.modes; 2661 } 2662 2663 static int drm_cvt_modes(struct drm_connector *connector, 2664 struct detailed_timing *timing) 2665 { 2666 int i, j, modes = 0; 2667 struct drm_display_mode *newmode; 2668 struct drm_device *dev = connector->dev; 2669 struct cvt_timing *cvt; 2670 const int rates[] = { 60, 85, 75, 60, 50 }; 2671 const u8 empty[3] = { 0, 0, 0 }; 2672 2673 for (i = 0; i < 4; i++) { 2674 int uninitialized_var(width), height; 2675 cvt = &(timing->data.other_data.data.cvt[i]); 2676 2677 if (!memcmp(cvt->code, empty, 3)) 2678 continue; 2679 2680 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 2681 switch (cvt->code[1] & 0x0c) { 2682 case 0x00: 2683 width = height * 4 / 3; 2684 break; 2685 case 0x04: 2686 width = height * 16 / 9; 2687 break; 2688 case 0x08: 2689 width = height * 16 / 10; 2690 break; 2691 case 0x0c: 2692 width = height * 15 / 9; 2693 break; 2694 } 2695 2696 for (j = 1; j < 5; j++) { 2697 if (cvt->code[2] & (1 << j)) { 2698 newmode = drm_cvt_mode(dev, width, height, 2699 rates[j], j == 0, 2700 false, false); 2701 if (newmode) { 2702 drm_mode_probed_add(connector, newmode); 2703 modes++; 2704 } 2705 } 2706 } 2707 } 2708 2709 return modes; 2710 } 2711 2712 static void 2713 do_cvt_mode(struct detailed_timing *timing, void *c) 2714 { 2715 struct detailed_mode_closure *closure = c; 2716 struct detailed_non_pixel *data = &timing->data.other_data; 2717 2718 if (data->type == EDID_DETAIL_CVT_3BYTE) 2719 closure->modes += drm_cvt_modes(closure->connector, timing); 2720 } 2721 2722 static int 2723 add_cvt_modes(struct drm_connector *connector, struct edid *edid) 2724 { 2725 struct detailed_mode_closure closure = { 2726 .connector = connector, 2727 .edid = edid, 2728 }; 2729 2730 if (version_greater(edid, 1, 2)) 2731 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 2732 2733 /* XXX should also look for CVT codes in VTB blocks */ 2734 2735 return closure.modes; 2736 } 2737 2738 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); 2739 2740 static void 2741 do_detailed_mode(struct detailed_timing *timing, void *c) 2742 { 2743 struct detailed_mode_closure *closure = c; 2744 struct drm_display_mode *newmode; 2745 2746 if (timing->pixel_clock) { 2747 newmode = drm_mode_detailed(closure->connector->dev, 2748 closure->edid, timing, 2749 closure->quirks); 2750 if (!newmode) 2751 return; 2752 2753 if (closure->preferred) 2754 newmode->type |= DRM_MODE_TYPE_PREFERRED; 2755 2756 /* 2757 * Detailed modes are limited to 10kHz pixel clock resolution, 2758 * so fix up anything that looks like CEA/HDMI mode, but the clock 2759 * is just slightly off. 2760 */ 2761 fixup_detailed_cea_mode_clock(newmode); 2762 2763 drm_mode_probed_add(closure->connector, newmode); 2764 closure->modes++; 2765 closure->preferred = 0; 2766 } 2767 } 2768 2769 /* 2770 * add_detailed_modes - Add modes from detailed timings 2771 * @connector: attached connector 2772 * @edid: EDID block to scan 2773 * @quirks: quirks to apply 2774 */ 2775 static int 2776 add_detailed_modes(struct drm_connector *connector, struct edid *edid, 2777 u32 quirks) 2778 { 2779 struct detailed_mode_closure closure = { 2780 .connector = connector, 2781 .edid = edid, 2782 .preferred = 1, 2783 .quirks = quirks, 2784 }; 2785 2786 if (closure.preferred && !version_greater(edid, 1, 3)) 2787 closure.preferred = 2788 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 2789 2790 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 2791 2792 return closure.modes; 2793 } 2794 2795 #define AUDIO_BLOCK 0x01 2796 #define VIDEO_BLOCK 0x02 2797 #define VENDOR_BLOCK 0x03 2798 #define SPEAKER_BLOCK 0x04 2799 #define USE_EXTENDED_TAG 0x07 2800 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00 2801 #define EXT_VIDEO_DATA_BLOCK_420 0x0E 2802 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F 2803 #define EDID_BASIC_AUDIO (1 << 6) 2804 #define EDID_CEA_YCRCB444 (1 << 5) 2805 #define EDID_CEA_YCRCB422 (1 << 4) 2806 #define EDID_CEA_VCDB_QS (1 << 6) 2807 2808 /* 2809 * Search EDID for CEA extension block. 2810 */ 2811 static u8 *drm_find_edid_extension(struct edid *edid, int ext_id) 2812 { 2813 u8 *edid_ext = NULL; 2814 int i; 2815 2816 /* No EDID or EDID extensions */ 2817 if (edid == NULL || edid->extensions == 0) 2818 return NULL; 2819 2820 /* Find CEA extension */ 2821 for (i = 0; i < edid->extensions; i++) { 2822 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); 2823 if (edid_ext[0] == ext_id) 2824 break; 2825 } 2826 2827 if (i == edid->extensions) 2828 return NULL; 2829 2830 return edid_ext; 2831 } 2832 2833 static u8 *drm_find_cea_extension(struct edid *edid) 2834 { 2835 return drm_find_edid_extension(edid, CEA_EXT); 2836 } 2837 2838 static u8 *drm_find_displayid_extension(struct edid *edid) 2839 { 2840 return drm_find_edid_extension(edid, DISPLAYID_EXT); 2841 } 2842 2843 /* 2844 * Calculate the alternate clock for the CEA mode 2845 * (60Hz vs. 59.94Hz etc.) 2846 */ 2847 static unsigned int 2848 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 2849 { 2850 unsigned int clock = cea_mode->clock; 2851 2852 if (cea_mode->vrefresh % 6 != 0) 2853 return clock; 2854 2855 /* 2856 * edid_cea_modes contains the 59.94Hz 2857 * variant for 240 and 480 line modes, 2858 * and the 60Hz variant otherwise. 2859 */ 2860 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 2861 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 2862 else 2863 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 2864 2865 return clock; 2866 } 2867 2868 static bool 2869 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 2870 { 2871 /* 2872 * For certain VICs the spec allows the vertical 2873 * front porch to vary by one or two lines. 2874 * 2875 * cea_modes[] stores the variant with the shortest 2876 * vertical front porch. We can adjust the mode to 2877 * get the other variants by simply increasing the 2878 * vertical front porch length. 2879 */ 2880 BUILD_BUG_ON(edid_cea_modes[8].vtotal != 262 || 2881 edid_cea_modes[9].vtotal != 262 || 2882 edid_cea_modes[12].vtotal != 262 || 2883 edid_cea_modes[13].vtotal != 262 || 2884 edid_cea_modes[23].vtotal != 312 || 2885 edid_cea_modes[24].vtotal != 312 || 2886 edid_cea_modes[27].vtotal != 312 || 2887 edid_cea_modes[28].vtotal != 312); 2888 2889 if (((vic == 8 || vic == 9 || 2890 vic == 12 || vic == 13) && mode->vtotal < 263) || 2891 ((vic == 23 || vic == 24 || 2892 vic == 27 || vic == 28) && mode->vtotal < 314)) { 2893 mode->vsync_start++; 2894 mode->vsync_end++; 2895 mode->vtotal++; 2896 2897 return true; 2898 } 2899 2900 return false; 2901 } 2902 2903 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 2904 unsigned int clock_tolerance) 2905 { 2906 u8 vic; 2907 2908 if (!to_match->clock) 2909 return 0; 2910 2911 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 2912 struct drm_display_mode cea_mode = edid_cea_modes[vic]; 2913 unsigned int clock1, clock2; 2914 2915 /* Check both 60Hz and 59.94Hz */ 2916 clock1 = cea_mode.clock; 2917 clock2 = cea_mode_alternate_clock(&cea_mode); 2918 2919 if (abs(to_match->clock - clock1) > clock_tolerance && 2920 abs(to_match->clock - clock2) > clock_tolerance) 2921 continue; 2922 2923 do { 2924 if (drm_mode_equal_no_clocks_no_stereo(to_match, &cea_mode)) 2925 return vic; 2926 } while (cea_mode_alternate_timings(vic, &cea_mode)); 2927 } 2928 2929 return 0; 2930 } 2931 2932 /** 2933 * drm_match_cea_mode - look for a CEA mode matching given mode 2934 * @to_match: display mode 2935 * 2936 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 2937 * mode. 2938 */ 2939 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 2940 { 2941 u8 vic; 2942 2943 if (!to_match->clock) 2944 return 0; 2945 2946 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 2947 struct drm_display_mode cea_mode = edid_cea_modes[vic]; 2948 unsigned int clock1, clock2; 2949 2950 /* Check both 60Hz and 59.94Hz */ 2951 clock1 = cea_mode.clock; 2952 clock2 = cea_mode_alternate_clock(&cea_mode); 2953 2954 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 2955 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 2956 continue; 2957 2958 do { 2959 if (drm_mode_equal_no_clocks_no_stereo(to_match, &cea_mode)) 2960 return vic; 2961 } while (cea_mode_alternate_timings(vic, &cea_mode)); 2962 } 2963 2964 return 0; 2965 } 2966 EXPORT_SYMBOL(drm_match_cea_mode); 2967 2968 static bool drm_valid_cea_vic(u8 vic) 2969 { 2970 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes); 2971 } 2972 2973 /** 2974 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to 2975 * the input VIC from the CEA mode list 2976 * @video_code: ID given to each of the CEA modes 2977 * 2978 * Returns picture aspect ratio 2979 */ 2980 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 2981 { 2982 return edid_cea_modes[video_code].picture_aspect_ratio; 2983 } 2984 EXPORT_SYMBOL(drm_get_cea_aspect_ratio); 2985 2986 /* 2987 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 2988 * specific block). 2989 * 2990 * It's almost like cea_mode_alternate_clock(), we just need to add an 2991 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this 2992 * one. 2993 */ 2994 static unsigned int 2995 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 2996 { 2997 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) 2998 return hdmi_mode->clock; 2999 3000 return cea_mode_alternate_clock(hdmi_mode); 3001 } 3002 3003 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 3004 unsigned int clock_tolerance) 3005 { 3006 u8 vic; 3007 3008 if (!to_match->clock) 3009 return 0; 3010 3011 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3012 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3013 unsigned int clock1, clock2; 3014 3015 /* Make sure to also match alternate clocks */ 3016 clock1 = hdmi_mode->clock; 3017 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3018 3019 if (abs(to_match->clock - clock1) > clock_tolerance && 3020 abs(to_match->clock - clock2) > clock_tolerance) 3021 continue; 3022 3023 if (drm_mode_equal_no_clocks(to_match, hdmi_mode)) 3024 return vic; 3025 } 3026 3027 return 0; 3028 } 3029 3030 /* 3031 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 3032 * @to_match: display mode 3033 * 3034 * An HDMI mode is one defined in the HDMI vendor specific block. 3035 * 3036 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 3037 */ 3038 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 3039 { 3040 u8 vic; 3041 3042 if (!to_match->clock) 3043 return 0; 3044 3045 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3046 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3047 unsigned int clock1, clock2; 3048 3049 /* Make sure to also match alternate clocks */ 3050 clock1 = hdmi_mode->clock; 3051 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3052 3053 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 3054 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 3055 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode)) 3056 return vic; 3057 } 3058 return 0; 3059 } 3060 3061 static bool drm_valid_hdmi_vic(u8 vic) 3062 { 3063 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 3064 } 3065 3066 static int 3067 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) 3068 { 3069 struct drm_device *dev = connector->dev; 3070 struct drm_display_mode *mode, *tmp; 3071 LIST_HEAD(list); 3072 int modes = 0; 3073 3074 /* Don't add CEA modes if the CEA extension block is missing */ 3075 if (!drm_find_cea_extension(edid)) 3076 return 0; 3077 3078 /* 3079 * Go through all probed modes and create a new mode 3080 * with the alternate clock for certain CEA modes. 3081 */ 3082 list_for_each_entry(mode, &connector->probed_modes, head) { 3083 const struct drm_display_mode *cea_mode = NULL; 3084 struct drm_display_mode *newmode; 3085 u8 vic = drm_match_cea_mode(mode); 3086 unsigned int clock1, clock2; 3087 3088 if (drm_valid_cea_vic(vic)) { 3089 cea_mode = &edid_cea_modes[vic]; 3090 clock2 = cea_mode_alternate_clock(cea_mode); 3091 } else { 3092 vic = drm_match_hdmi_mode(mode); 3093 if (drm_valid_hdmi_vic(vic)) { 3094 cea_mode = &edid_4k_modes[vic]; 3095 clock2 = hdmi_mode_alternate_clock(cea_mode); 3096 } 3097 } 3098 3099 if (!cea_mode) 3100 continue; 3101 3102 clock1 = cea_mode->clock; 3103 3104 if (clock1 == clock2) 3105 continue; 3106 3107 if (mode->clock != clock1 && mode->clock != clock2) 3108 continue; 3109 3110 newmode = drm_mode_duplicate(dev, cea_mode); 3111 if (!newmode) 3112 continue; 3113 3114 /* Carry over the stereo flags */ 3115 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 3116 3117 /* 3118 * The current mode could be either variant. Make 3119 * sure to pick the "other" clock for the new mode. 3120 */ 3121 if (mode->clock != clock1) 3122 newmode->clock = clock1; 3123 else 3124 newmode->clock = clock2; 3125 3126 list_add_tail(&newmode->head, &list); 3127 } 3128 3129 list_for_each_entry_safe(mode, tmp, &list, head) { 3130 list_del(&mode->head); 3131 drm_mode_probed_add(connector, mode); 3132 modes++; 3133 } 3134 3135 return modes; 3136 } 3137 3138 static u8 svd_to_vic(u8 svd) 3139 { 3140 /* 0-6 bit vic, 7th bit native mode indicator */ 3141 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 3142 return svd & 127; 3143 3144 return svd; 3145 } 3146 3147 static struct drm_display_mode * 3148 drm_display_mode_from_vic_index(struct drm_connector *connector, 3149 const u8 *video_db, u8 video_len, 3150 u8 video_index) 3151 { 3152 struct drm_device *dev = connector->dev; 3153 struct drm_display_mode *newmode; 3154 u8 vic; 3155 3156 if (video_db == NULL || video_index >= video_len) 3157 return NULL; 3158 3159 /* CEA modes are numbered 1..127 */ 3160 vic = svd_to_vic(video_db[video_index]); 3161 if (!drm_valid_cea_vic(vic)) 3162 return NULL; 3163 3164 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]); 3165 if (!newmode) 3166 return NULL; 3167 3168 newmode->vrefresh = 0; 3169 3170 return newmode; 3171 } 3172 3173 /* 3174 * do_y420vdb_modes - Parse YCBCR 420 only modes 3175 * @connector: connector corresponding to the HDMI sink 3176 * @svds: start of the data block of CEA YCBCR 420 VDB 3177 * @len: length of the CEA YCBCR 420 VDB 3178 * 3179 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 3180 * which contains modes which can be supported in YCBCR 420 3181 * output format only. 3182 */ 3183 static int do_y420vdb_modes(struct drm_connector *connector, 3184 const u8 *svds, u8 svds_len) 3185 { 3186 int modes = 0, i; 3187 struct drm_device *dev = connector->dev; 3188 struct drm_display_info *info = &connector->display_info; 3189 struct drm_hdmi_info *hdmi = &info->hdmi; 3190 3191 for (i = 0; i < svds_len; i++) { 3192 u8 vic = svd_to_vic(svds[i]); 3193 struct drm_display_mode *newmode; 3194 3195 if (!drm_valid_cea_vic(vic)) 3196 continue; 3197 3198 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]); 3199 if (!newmode) 3200 break; 3201 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 3202 drm_mode_probed_add(connector, newmode); 3203 modes++; 3204 } 3205 3206 if (modes > 0) 3207 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3208 return modes; 3209 } 3210 3211 /* 3212 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap 3213 * @connector: connector corresponding to the HDMI sink 3214 * @vic: CEA vic for the video mode to be added in the map 3215 * 3216 * Makes an entry for a videomode in the YCBCR 420 bitmap 3217 */ 3218 static void 3219 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd) 3220 { 3221 u8 vic = svd_to_vic(svd); 3222 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3223 3224 if (!drm_valid_cea_vic(vic)) 3225 return; 3226 3227 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 3228 } 3229 3230 static int 3231 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 3232 { 3233 int i, modes = 0; 3234 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3235 3236 for (i = 0; i < len; i++) { 3237 struct drm_display_mode *mode; 3238 mode = drm_display_mode_from_vic_index(connector, db, len, i); 3239 if (mode) { 3240 /* 3241 * YCBCR420 capability block contains a bitmap which 3242 * gives the index of CEA modes from CEA VDB, which 3243 * can support YCBCR 420 sampling output also (apart 3244 * from RGB/YCBCR444 etc). 3245 * For example, if the bit 0 in bitmap is set, 3246 * first mode in VDB can support YCBCR420 output too. 3247 * Add YCBCR420 modes only if sink is HDMI 2.0 capable. 3248 */ 3249 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) 3250 drm_add_cmdb_modes(connector, db[i]); 3251 3252 drm_mode_probed_add(connector, mode); 3253 modes++; 3254 } 3255 } 3256 3257 return modes; 3258 } 3259 3260 struct stereo_mandatory_mode { 3261 int width, height, vrefresh; 3262 unsigned int flags; 3263 }; 3264 3265 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 3266 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3267 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3268 { 1920, 1080, 50, 3269 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3270 { 1920, 1080, 60, 3271 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3272 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3273 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3274 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3275 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 3276 }; 3277 3278 static bool 3279 stereo_match_mandatory(const struct drm_display_mode *mode, 3280 const struct stereo_mandatory_mode *stereo_mode) 3281 { 3282 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 3283 3284 return mode->hdisplay == stereo_mode->width && 3285 mode->vdisplay == stereo_mode->height && 3286 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 3287 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 3288 } 3289 3290 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 3291 { 3292 struct drm_device *dev = connector->dev; 3293 const struct drm_display_mode *mode; 3294 struct list_head stereo_modes; 3295 int modes = 0, i; 3296 3297 INIT_LIST_HEAD(&stereo_modes); 3298 3299 list_for_each_entry(mode, &connector->probed_modes, head) { 3300 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 3301 const struct stereo_mandatory_mode *mandatory; 3302 struct drm_display_mode *new_mode; 3303 3304 if (!stereo_match_mandatory(mode, 3305 &stereo_mandatory_modes[i])) 3306 continue; 3307 3308 mandatory = &stereo_mandatory_modes[i]; 3309 new_mode = drm_mode_duplicate(dev, mode); 3310 if (!new_mode) 3311 continue; 3312 3313 new_mode->flags |= mandatory->flags; 3314 list_add_tail(&new_mode->head, &stereo_modes); 3315 modes++; 3316 } 3317 } 3318 3319 list_splice_tail(&stereo_modes, &connector->probed_modes); 3320 3321 return modes; 3322 } 3323 3324 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 3325 { 3326 struct drm_device *dev = connector->dev; 3327 struct drm_display_mode *newmode; 3328 3329 if (!drm_valid_hdmi_vic(vic)) { 3330 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 3331 return 0; 3332 } 3333 3334 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 3335 if (!newmode) 3336 return 0; 3337 3338 drm_mode_probed_add(connector, newmode); 3339 3340 return 1; 3341 } 3342 3343 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 3344 const u8 *video_db, u8 video_len, u8 video_index) 3345 { 3346 struct drm_display_mode *newmode; 3347 int modes = 0; 3348 3349 if (structure & (1 << 0)) { 3350 newmode = drm_display_mode_from_vic_index(connector, video_db, 3351 video_len, 3352 video_index); 3353 if (newmode) { 3354 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 3355 drm_mode_probed_add(connector, newmode); 3356 modes++; 3357 } 3358 } 3359 if (structure & (1 << 6)) { 3360 newmode = drm_display_mode_from_vic_index(connector, video_db, 3361 video_len, 3362 video_index); 3363 if (newmode) { 3364 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3365 drm_mode_probed_add(connector, newmode); 3366 modes++; 3367 } 3368 } 3369 if (structure & (1 << 8)) { 3370 newmode = drm_display_mode_from_vic_index(connector, video_db, 3371 video_len, 3372 video_index); 3373 if (newmode) { 3374 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3375 drm_mode_probed_add(connector, newmode); 3376 modes++; 3377 } 3378 } 3379 3380 return modes; 3381 } 3382 3383 /* 3384 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 3385 * @connector: connector corresponding to the HDMI sink 3386 * @db: start of the CEA vendor specific block 3387 * @len: length of the CEA block payload, ie. one can access up to db[len] 3388 * 3389 * Parses the HDMI VSDB looking for modes to add to @connector. This function 3390 * also adds the stereo 3d modes when applicable. 3391 */ 3392 static int 3393 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 3394 const u8 *video_db, u8 video_len) 3395 { 3396 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 3397 u8 vic_len, hdmi_3d_len = 0; 3398 u16 mask; 3399 u16 structure_all; 3400 3401 if (len < 8) 3402 goto out; 3403 3404 /* no HDMI_Video_Present */ 3405 if (!(db[8] & (1 << 5))) 3406 goto out; 3407 3408 /* Latency_Fields_Present */ 3409 if (db[8] & (1 << 7)) 3410 offset += 2; 3411 3412 /* I_Latency_Fields_Present */ 3413 if (db[8] & (1 << 6)) 3414 offset += 2; 3415 3416 /* the declared length is not long enough for the 2 first bytes 3417 * of additional video format capabilities */ 3418 if (len < (8 + offset + 2)) 3419 goto out; 3420 3421 /* 3D_Present */ 3422 offset++; 3423 if (db[8 + offset] & (1 << 7)) { 3424 modes += add_hdmi_mandatory_stereo_modes(connector); 3425 3426 /* 3D_Multi_present */ 3427 multi_present = (db[8 + offset] & 0x60) >> 5; 3428 } 3429 3430 offset++; 3431 vic_len = db[8 + offset] >> 5; 3432 hdmi_3d_len = db[8 + offset] & 0x1f; 3433 3434 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 3435 u8 vic; 3436 3437 vic = db[9 + offset + i]; 3438 modes += add_hdmi_mode(connector, vic); 3439 } 3440 offset += 1 + vic_len; 3441 3442 if (multi_present == 1) 3443 multi_len = 2; 3444 else if (multi_present == 2) 3445 multi_len = 4; 3446 else 3447 multi_len = 0; 3448 3449 if (len < (8 + offset + hdmi_3d_len - 1)) 3450 goto out; 3451 3452 if (hdmi_3d_len < multi_len) 3453 goto out; 3454 3455 if (multi_present == 1 || multi_present == 2) { 3456 /* 3D_Structure_ALL */ 3457 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 3458 3459 /* check if 3D_MASK is present */ 3460 if (multi_present == 2) 3461 mask = (db[10 + offset] << 8) | db[11 + offset]; 3462 else 3463 mask = 0xffff; 3464 3465 for (i = 0; i < 16; i++) { 3466 if (mask & (1 << i)) 3467 modes += add_3d_struct_modes(connector, 3468 structure_all, 3469 video_db, 3470 video_len, i); 3471 } 3472 } 3473 3474 offset += multi_len; 3475 3476 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 3477 int vic_index; 3478 struct drm_display_mode *newmode = NULL; 3479 unsigned int newflag = 0; 3480 bool detail_present; 3481 3482 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 3483 3484 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 3485 break; 3486 3487 /* 2D_VIC_order_X */ 3488 vic_index = db[8 + offset + i] >> 4; 3489 3490 /* 3D_Structure_X */ 3491 switch (db[8 + offset + i] & 0x0f) { 3492 case 0: 3493 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 3494 break; 3495 case 6: 3496 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3497 break; 3498 case 8: 3499 /* 3D_Detail_X */ 3500 if ((db[9 + offset + i] >> 4) == 1) 3501 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3502 break; 3503 } 3504 3505 if (newflag != 0) { 3506 newmode = drm_display_mode_from_vic_index(connector, 3507 video_db, 3508 video_len, 3509 vic_index); 3510 3511 if (newmode) { 3512 newmode->flags |= newflag; 3513 drm_mode_probed_add(connector, newmode); 3514 modes++; 3515 } 3516 } 3517 3518 if (detail_present) 3519 i++; 3520 } 3521 3522 out: 3523 return modes; 3524 } 3525 3526 static int 3527 cea_db_payload_len(const u8 *db) 3528 { 3529 return db[0] & 0x1f; 3530 } 3531 3532 static int 3533 cea_db_extended_tag(const u8 *db) 3534 { 3535 return db[1]; 3536 } 3537 3538 static int 3539 cea_db_tag(const u8 *db) 3540 { 3541 return db[0] >> 5; 3542 } 3543 3544 static int 3545 cea_revision(const u8 *cea) 3546 { 3547 return cea[1]; 3548 } 3549 3550 static int 3551 cea_db_offsets(const u8 *cea, int *start, int *end) 3552 { 3553 /* Data block offset in CEA extension block */ 3554 *start = 4; 3555 *end = cea[2]; 3556 if (*end == 0) 3557 *end = 127; 3558 if (*end < 4 || *end > 127) 3559 return -ERANGE; 3560 return 0; 3561 } 3562 3563 static bool cea_db_is_hdmi_vsdb(const u8 *db) 3564 { 3565 int hdmi_id; 3566 3567 if (cea_db_tag(db) != VENDOR_BLOCK) 3568 return false; 3569 3570 if (cea_db_payload_len(db) < 5) 3571 return false; 3572 3573 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 3574 3575 return hdmi_id == HDMI_IEEE_OUI; 3576 } 3577 3578 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db) 3579 { 3580 unsigned int oui; 3581 3582 if (cea_db_tag(db) != VENDOR_BLOCK) 3583 return false; 3584 3585 if (cea_db_payload_len(db) < 7) 3586 return false; 3587 3588 oui = db[3] << 16 | db[2] << 8 | db[1]; 3589 3590 return oui == HDMI_FORUM_IEEE_OUI; 3591 } 3592 3593 static bool cea_db_is_y420cmdb(const u8 *db) 3594 { 3595 if (cea_db_tag(db) != USE_EXTENDED_TAG) 3596 return false; 3597 3598 if (!cea_db_payload_len(db)) 3599 return false; 3600 3601 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB) 3602 return false; 3603 3604 return true; 3605 } 3606 3607 static bool cea_db_is_y420vdb(const u8 *db) 3608 { 3609 if (cea_db_tag(db) != USE_EXTENDED_TAG) 3610 return false; 3611 3612 if (!cea_db_payload_len(db)) 3613 return false; 3614 3615 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420) 3616 return false; 3617 3618 return true; 3619 } 3620 3621 #define for_each_cea_db(cea, i, start, end) \ 3622 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 3623 3624 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector, 3625 const u8 *db) 3626 { 3627 struct drm_display_info *info = &connector->display_info; 3628 struct drm_hdmi_info *hdmi = &info->hdmi; 3629 u8 map_len = cea_db_payload_len(db) - 1; 3630 u8 count; 3631 u64 map = 0; 3632 3633 if (map_len == 0) { 3634 /* All CEA modes support ycbcr420 sampling also.*/ 3635 hdmi->y420_cmdb_map = U64_MAX; 3636 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3637 return; 3638 } 3639 3640 /* 3641 * This map indicates which of the existing CEA block modes 3642 * from VDB can support YCBCR420 output too. So if bit=0 is 3643 * set, first mode from VDB can support YCBCR420 output too. 3644 * We will parse and keep this map, before parsing VDB itself 3645 * to avoid going through the same block again and again. 3646 * 3647 * Spec is not clear about max possible size of this block. 3648 * Clamping max bitmap block size at 8 bytes. Every byte can 3649 * address 8 CEA modes, in this way this map can address 3650 * 8*8 = first 64 SVDs. 3651 */ 3652 if (WARN_ON_ONCE(map_len > 8)) 3653 map_len = 8; 3654 3655 for (count = 0; count < map_len; count++) 3656 map |= (u64)db[2 + count] << (8 * count); 3657 3658 if (map) 3659 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3660 3661 hdmi->y420_cmdb_map = map; 3662 } 3663 3664 static int 3665 add_cea_modes(struct drm_connector *connector, struct edid *edid) 3666 { 3667 const u8 *cea = drm_find_cea_extension(edid); 3668 const u8 *db, *hdmi = NULL, *video = NULL; 3669 u8 dbl, hdmi_len, video_len = 0; 3670 int modes = 0; 3671 3672 if (cea && cea_revision(cea) >= 3) { 3673 int i, start, end; 3674 3675 if (cea_db_offsets(cea, &start, &end)) 3676 return 0; 3677 3678 for_each_cea_db(cea, i, start, end) { 3679 db = &cea[i]; 3680 dbl = cea_db_payload_len(db); 3681 3682 if (cea_db_tag(db) == VIDEO_BLOCK) { 3683 video = db + 1; 3684 video_len = dbl; 3685 modes += do_cea_modes(connector, video, dbl); 3686 } else if (cea_db_is_hdmi_vsdb(db)) { 3687 hdmi = db; 3688 hdmi_len = dbl; 3689 } else if (cea_db_is_y420vdb(db)) { 3690 const u8 *vdb420 = &db[2]; 3691 3692 /* Add 4:2:0(only) modes present in EDID */ 3693 modes += do_y420vdb_modes(connector, 3694 vdb420, 3695 dbl - 1); 3696 } 3697 } 3698 } 3699 3700 /* 3701 * We parse the HDMI VSDB after having added the cea modes as we will 3702 * be patching their flags when the sink supports stereo 3D. 3703 */ 3704 if (hdmi) 3705 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, 3706 video_len); 3707 3708 return modes; 3709 } 3710 3711 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 3712 { 3713 const struct drm_display_mode *cea_mode; 3714 int clock1, clock2, clock; 3715 u8 vic; 3716 const char *type; 3717 3718 /* 3719 * allow 5kHz clock difference either way to account for 3720 * the 10kHz clock resolution limit of detailed timings. 3721 */ 3722 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 3723 if (drm_valid_cea_vic(vic)) { 3724 type = "CEA"; 3725 cea_mode = &edid_cea_modes[vic]; 3726 clock1 = cea_mode->clock; 3727 clock2 = cea_mode_alternate_clock(cea_mode); 3728 } else { 3729 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 3730 if (drm_valid_hdmi_vic(vic)) { 3731 type = "HDMI"; 3732 cea_mode = &edid_4k_modes[vic]; 3733 clock1 = cea_mode->clock; 3734 clock2 = hdmi_mode_alternate_clock(cea_mode); 3735 } else { 3736 return; 3737 } 3738 } 3739 3740 /* pick whichever is closest */ 3741 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 3742 clock = clock1; 3743 else 3744 clock = clock2; 3745 3746 if (mode->clock == clock) 3747 return; 3748 3749 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 3750 type, vic, mode->clock, clock); 3751 mode->clock = clock; 3752 } 3753 3754 static void 3755 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 3756 { 3757 u8 len = cea_db_payload_len(db); 3758 3759 if (len >= 6) 3760 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */ 3761 if (len >= 8) { 3762 connector->latency_present[0] = db[8] >> 7; 3763 connector->latency_present[1] = (db[8] >> 6) & 1; 3764 } 3765 if (len >= 9) 3766 connector->video_latency[0] = db[9]; 3767 if (len >= 10) 3768 connector->audio_latency[0] = db[10]; 3769 if (len >= 11) 3770 connector->video_latency[1] = db[11]; 3771 if (len >= 12) 3772 connector->audio_latency[1] = db[12]; 3773 3774 DRM_DEBUG_KMS("HDMI: latency present %d %d, " 3775 "video latency %d %d, " 3776 "audio latency %d %d\n", 3777 connector->latency_present[0], 3778 connector->latency_present[1], 3779 connector->video_latency[0], 3780 connector->video_latency[1], 3781 connector->audio_latency[0], 3782 connector->audio_latency[1]); 3783 } 3784 3785 static void 3786 monitor_name(struct detailed_timing *t, void *data) 3787 { 3788 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME) 3789 *(u8 **)data = t->data.other_data.data.str.str; 3790 } 3791 3792 static int get_monitor_name(struct edid *edid, char name[13]) 3793 { 3794 char *edid_name = NULL; 3795 int mnl; 3796 3797 if (!edid || !name) 3798 return 0; 3799 3800 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name); 3801 for (mnl = 0; edid_name && mnl < 13; mnl++) { 3802 if (edid_name[mnl] == 0x0a) 3803 break; 3804 3805 name[mnl] = edid_name[mnl]; 3806 } 3807 3808 return mnl; 3809 } 3810 3811 /** 3812 * drm_edid_get_monitor_name - fetch the monitor name from the edid 3813 * @edid: monitor EDID information 3814 * @name: pointer to a character array to hold the name of the monitor 3815 * @bufsize: The size of the name buffer (should be at least 14 chars.) 3816 * 3817 */ 3818 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize) 3819 { 3820 int name_length; 3821 char buf[13]; 3822 3823 if (bufsize <= 0) 3824 return; 3825 3826 name_length = min(get_monitor_name(edid, buf), bufsize - 1); 3827 memcpy(name, buf, name_length); 3828 name[name_length] = '\0'; 3829 } 3830 EXPORT_SYMBOL(drm_edid_get_monitor_name); 3831 3832 /** 3833 * drm_edid_to_eld - build ELD from EDID 3834 * @connector: connector corresponding to the HDMI/DP sink 3835 * @edid: EDID to parse 3836 * 3837 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 3838 * Conn_Type, HDCP and Port_ID ELD fields are left for the graphics driver to 3839 * fill in. 3840 */ 3841 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 3842 { 3843 uint8_t *eld = connector->eld; 3844 u8 *cea; 3845 u8 *db; 3846 int total_sad_count = 0; 3847 int mnl; 3848 int dbl; 3849 3850 memset(eld, 0, sizeof(connector->eld)); 3851 3852 connector->latency_present[0] = false; 3853 connector->latency_present[1] = false; 3854 connector->video_latency[0] = 0; 3855 connector->audio_latency[0] = 0; 3856 connector->video_latency[1] = 0; 3857 connector->audio_latency[1] = 0; 3858 3859 if (!edid) 3860 return; 3861 3862 cea = drm_find_cea_extension(edid); 3863 if (!cea) { 3864 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 3865 return; 3866 } 3867 3868 mnl = get_monitor_name(edid, eld + 20); 3869 3870 eld[4] = (cea[1] << 5) | mnl; 3871 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20); 3872 3873 eld[0] = 2 << 3; /* ELD version: 2 */ 3874 3875 eld[16] = edid->mfg_id[0]; 3876 eld[17] = edid->mfg_id[1]; 3877 eld[18] = edid->prod_code[0]; 3878 eld[19] = edid->prod_code[1]; 3879 3880 if (cea_revision(cea) >= 3) { 3881 int i, start, end; 3882 3883 if (cea_db_offsets(cea, &start, &end)) { 3884 start = 0; 3885 end = 0; 3886 } 3887 3888 for_each_cea_db(cea, i, start, end) { 3889 db = &cea[i]; 3890 dbl = cea_db_payload_len(db); 3891 3892 switch (cea_db_tag(db)) { 3893 int sad_count; 3894 3895 case AUDIO_BLOCK: 3896 /* Audio Data Block, contains SADs */ 3897 sad_count = min(dbl / 3, 15 - total_sad_count); 3898 if (sad_count >= 1) 3899 memcpy(eld + 20 + mnl + total_sad_count * 3, 3900 &db[1], sad_count * 3); 3901 total_sad_count += sad_count; 3902 break; 3903 case SPEAKER_BLOCK: 3904 /* Speaker Allocation Data Block */ 3905 if (dbl >= 1) 3906 eld[7] = db[1]; 3907 break; 3908 case VENDOR_BLOCK: 3909 /* HDMI Vendor-Specific Data Block */ 3910 if (cea_db_is_hdmi_vsdb(db)) 3911 drm_parse_hdmi_vsdb_audio(connector, db); 3912 break; 3913 default: 3914 break; 3915 } 3916 } 3917 } 3918 eld[5] |= total_sad_count << 4; 3919 3920 eld[DRM_ELD_BASELINE_ELD_LEN] = 3921 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 3922 3923 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", 3924 drm_eld_size(eld), total_sad_count); 3925 } 3926 EXPORT_SYMBOL(drm_edid_to_eld); 3927 3928 /** 3929 * drm_edid_to_sad - extracts SADs from EDID 3930 * @edid: EDID to parse 3931 * @sads: pointer that will be set to the extracted SADs 3932 * 3933 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 3934 * 3935 * Note: The returned pointer needs to be freed using kfree(). 3936 * 3937 * Return: The number of found SADs or negative number on error. 3938 */ 3939 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) 3940 { 3941 int count = 0; 3942 int i, start, end, dbl; 3943 u8 *cea; 3944 3945 cea = drm_find_cea_extension(edid); 3946 if (!cea) { 3947 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 3948 return -ENOENT; 3949 } 3950 3951 if (cea_revision(cea) < 3) { 3952 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 3953 return -ENOTSUPP; 3954 } 3955 3956 if (cea_db_offsets(cea, &start, &end)) { 3957 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 3958 return -EPROTO; 3959 } 3960 3961 for_each_cea_db(cea, i, start, end) { 3962 u8 *db = &cea[i]; 3963 3964 if (cea_db_tag(db) == AUDIO_BLOCK) { 3965 int j; 3966 dbl = cea_db_payload_len(db); 3967 3968 count = dbl / 3; /* SAD is 3B */ 3969 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 3970 if (!*sads) 3971 return -ENOMEM; 3972 for (j = 0; j < count; j++) { 3973 u8 *sad = &db[1 + j * 3]; 3974 3975 (*sads)[j].format = (sad[0] & 0x78) >> 3; 3976 (*sads)[j].channels = sad[0] & 0x7; 3977 (*sads)[j].freq = sad[1] & 0x7F; 3978 (*sads)[j].byte2 = sad[2]; 3979 } 3980 break; 3981 } 3982 } 3983 3984 return count; 3985 } 3986 EXPORT_SYMBOL(drm_edid_to_sad); 3987 3988 /** 3989 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 3990 * @edid: EDID to parse 3991 * @sadb: pointer to the speaker block 3992 * 3993 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 3994 * 3995 * Note: The returned pointer needs to be freed using kfree(). 3996 * 3997 * Return: The number of found Speaker Allocation Blocks or negative number on 3998 * error. 3999 */ 4000 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) 4001 { 4002 int count = 0; 4003 int i, start, end, dbl; 4004 const u8 *cea; 4005 4006 cea = drm_find_cea_extension(edid); 4007 if (!cea) { 4008 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4009 return -ENOENT; 4010 } 4011 4012 if (cea_revision(cea) < 3) { 4013 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4014 return -ENOTSUPP; 4015 } 4016 4017 if (cea_db_offsets(cea, &start, &end)) { 4018 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4019 return -EPROTO; 4020 } 4021 4022 for_each_cea_db(cea, i, start, end) { 4023 const u8 *db = &cea[i]; 4024 4025 if (cea_db_tag(db) == SPEAKER_BLOCK) { 4026 dbl = cea_db_payload_len(db); 4027 4028 /* Speaker Allocation Data Block */ 4029 if (dbl == 3) { 4030 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); 4031 if (!*sadb) 4032 return -ENOMEM; 4033 count = dbl; 4034 break; 4035 } 4036 } 4037 } 4038 4039 return count; 4040 } 4041 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 4042 4043 /** 4044 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 4045 * @connector: connector associated with the HDMI/DP sink 4046 * @mode: the display mode 4047 * 4048 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 4049 * the sink doesn't support audio or video. 4050 */ 4051 int drm_av_sync_delay(struct drm_connector *connector, 4052 const struct drm_display_mode *mode) 4053 { 4054 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 4055 int a, v; 4056 4057 if (!connector->latency_present[0]) 4058 return 0; 4059 if (!connector->latency_present[1]) 4060 i = 0; 4061 4062 a = connector->audio_latency[i]; 4063 v = connector->video_latency[i]; 4064 4065 /* 4066 * HDMI/DP sink doesn't support audio or video? 4067 */ 4068 if (a == 255 || v == 255) 4069 return 0; 4070 4071 /* 4072 * Convert raw EDID values to millisecond. 4073 * Treat unknown latency as 0ms. 4074 */ 4075 if (a) 4076 a = min(2 * (a - 1), 500); 4077 if (v) 4078 v = min(2 * (v - 1), 500); 4079 4080 return max(v - a, 0); 4081 } 4082 EXPORT_SYMBOL(drm_av_sync_delay); 4083 4084 /** 4085 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 4086 * @edid: monitor EDID information 4087 * 4088 * Parse the CEA extension according to CEA-861-B. 4089 * 4090 * Return: True if the monitor is HDMI, false if not or unknown. 4091 */ 4092 bool drm_detect_hdmi_monitor(struct edid *edid) 4093 { 4094 u8 *edid_ext; 4095 int i; 4096 int start_offset, end_offset; 4097 4098 edid_ext = drm_find_cea_extension(edid); 4099 if (!edid_ext) 4100 return false; 4101 4102 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4103 return false; 4104 4105 /* 4106 * Because HDMI identifier is in Vendor Specific Block, 4107 * search it from all data blocks of CEA extension. 4108 */ 4109 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4110 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 4111 return true; 4112 } 4113 4114 return false; 4115 } 4116 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 4117 4118 /** 4119 * drm_detect_monitor_audio - check monitor audio capability 4120 * @edid: EDID block to scan 4121 * 4122 * Monitor should have CEA extension block. 4123 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 4124 * audio' only. If there is any audio extension block and supported 4125 * audio format, assume at least 'basic audio' support, even if 'basic 4126 * audio' is not defined in EDID. 4127 * 4128 * Return: True if the monitor supports audio, false otherwise. 4129 */ 4130 bool drm_detect_monitor_audio(struct edid *edid) 4131 { 4132 u8 *edid_ext; 4133 int i, j; 4134 bool has_audio = false; 4135 int start_offset, end_offset; 4136 4137 edid_ext = drm_find_cea_extension(edid); 4138 if (!edid_ext) 4139 goto end; 4140 4141 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 4142 4143 if (has_audio) { 4144 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 4145 goto end; 4146 } 4147 4148 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4149 goto end; 4150 4151 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4152 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 4153 has_audio = true; 4154 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 4155 DRM_DEBUG_KMS("CEA audio format %d\n", 4156 (edid_ext[i + j] >> 3) & 0xf); 4157 goto end; 4158 } 4159 } 4160 end: 4161 return has_audio; 4162 } 4163 EXPORT_SYMBOL(drm_detect_monitor_audio); 4164 4165 /** 4166 * drm_rgb_quant_range_selectable - is RGB quantization range selectable? 4167 * @edid: EDID block to scan 4168 * 4169 * Check whether the monitor reports the RGB quantization range selection 4170 * as supported. The AVI infoframe can then be used to inform the monitor 4171 * which quantization range (full or limited) is used. 4172 * 4173 * Return: True if the RGB quantization range is selectable, false otherwise. 4174 */ 4175 bool drm_rgb_quant_range_selectable(struct edid *edid) 4176 { 4177 u8 *edid_ext; 4178 int i, start, end; 4179 4180 edid_ext = drm_find_cea_extension(edid); 4181 if (!edid_ext) 4182 return false; 4183 4184 if (cea_db_offsets(edid_ext, &start, &end)) 4185 return false; 4186 4187 for_each_cea_db(edid_ext, i, start, end) { 4188 if (cea_db_tag(&edid_ext[i]) == USE_EXTENDED_TAG && 4189 cea_db_payload_len(&edid_ext[i]) == 2 && 4190 cea_db_extended_tag(&edid_ext[i]) == 4191 EXT_VIDEO_CAPABILITY_BLOCK) { 4192 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]); 4193 return edid_ext[i + 2] & EDID_CEA_VCDB_QS; 4194 } 4195 } 4196 4197 return false; 4198 } 4199 EXPORT_SYMBOL(drm_rgb_quant_range_selectable); 4200 4201 /** 4202 * drm_default_rgb_quant_range - default RGB quantization range 4203 * @mode: display mode 4204 * 4205 * Determine the default RGB quantization range for the mode, 4206 * as specified in CEA-861. 4207 * 4208 * Return: The default RGB quantization range for the mode 4209 */ 4210 enum hdmi_quantization_range 4211 drm_default_rgb_quant_range(const struct drm_display_mode *mode) 4212 { 4213 /* All CEA modes other than VIC 1 use limited quantization range. */ 4214 return drm_match_cea_mode(mode) > 1 ? 4215 HDMI_QUANTIZATION_RANGE_LIMITED : 4216 HDMI_QUANTIZATION_RANGE_FULL; 4217 } 4218 EXPORT_SYMBOL(drm_default_rgb_quant_range); 4219 4220 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 4221 const u8 *db) 4222 { 4223 u8 dc_mask; 4224 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 4225 4226 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 4227 hdmi->y420_dc_modes |= dc_mask; 4228 } 4229 4230 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector, 4231 const u8 *hf_vsdb) 4232 { 4233 struct drm_display_info *display = &connector->display_info; 4234 struct drm_hdmi_info *hdmi = &display->hdmi; 4235 4236 if (hf_vsdb[6] & 0x80) { 4237 hdmi->scdc.supported = true; 4238 if (hf_vsdb[6] & 0x40) 4239 hdmi->scdc.read_request = true; 4240 } 4241 4242 /* 4243 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 4244 * And as per the spec, three factors confirm this: 4245 * * Availability of a HF-VSDB block in EDID (check) 4246 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 4247 * * SCDC support available (let's check) 4248 * Lets check it out. 4249 */ 4250 4251 if (hf_vsdb[5]) { 4252 /* max clock is 5000 KHz times block value */ 4253 u32 max_tmds_clock = hf_vsdb[5] * 5000; 4254 struct drm_scdc *scdc = &hdmi->scdc; 4255 4256 if (max_tmds_clock > 340000) { 4257 display->max_tmds_clock = max_tmds_clock; 4258 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n", 4259 display->max_tmds_clock); 4260 } 4261 4262 if (scdc->supported) { 4263 scdc->scrambling.supported = true; 4264 4265 /* Few sinks support scrambling for cloks < 340M */ 4266 if ((hf_vsdb[6] & 0x8)) 4267 scdc->scrambling.low_rates = true; 4268 } 4269 } 4270 4271 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb); 4272 } 4273 4274 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 4275 const u8 *hdmi) 4276 { 4277 struct drm_display_info *info = &connector->display_info; 4278 unsigned int dc_bpc = 0; 4279 4280 /* HDMI supports at least 8 bpc */ 4281 info->bpc = 8; 4282 4283 if (cea_db_payload_len(hdmi) < 6) 4284 return; 4285 4286 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 4287 dc_bpc = 10; 4288 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 4289 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 4290 connector->name); 4291 } 4292 4293 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 4294 dc_bpc = 12; 4295 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 4296 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 4297 connector->name); 4298 } 4299 4300 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 4301 dc_bpc = 16; 4302 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 4303 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 4304 connector->name); 4305 } 4306 4307 if (dc_bpc == 0) { 4308 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 4309 connector->name); 4310 return; 4311 } 4312 4313 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 4314 connector->name, dc_bpc); 4315 info->bpc = dc_bpc; 4316 4317 /* 4318 * Deep color support mandates RGB444 support for all video 4319 * modes and forbids YCRCB422 support for all video modes per 4320 * HDMI 1.3 spec. 4321 */ 4322 info->color_formats = DRM_COLOR_FORMAT_RGB444; 4323 4324 /* YCRCB444 is optional according to spec. */ 4325 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 4326 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4327 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 4328 connector->name); 4329 } 4330 4331 /* 4332 * Spec says that if any deep color mode is supported at all, 4333 * then deep color 36 bit must be supported. 4334 */ 4335 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 4336 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 4337 connector->name); 4338 } 4339 } 4340 4341 static void 4342 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 4343 { 4344 struct drm_display_info *info = &connector->display_info; 4345 u8 len = cea_db_payload_len(db); 4346 4347 if (len >= 6) 4348 info->dvi_dual = db[6] & 1; 4349 if (len >= 7) 4350 info->max_tmds_clock = db[7] * 5000; 4351 4352 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 4353 "max TMDS clock %d kHz\n", 4354 info->dvi_dual, 4355 info->max_tmds_clock); 4356 4357 drm_parse_hdmi_deep_color_info(connector, db); 4358 } 4359 4360 static void drm_parse_cea_ext(struct drm_connector *connector, 4361 struct edid *edid) 4362 { 4363 struct drm_display_info *info = &connector->display_info; 4364 const u8 *edid_ext; 4365 int i, start, end; 4366 4367 edid_ext = drm_find_cea_extension(edid); 4368 if (!edid_ext) 4369 return; 4370 4371 info->cea_rev = edid_ext[1]; 4372 4373 /* The existence of a CEA block should imply RGB support */ 4374 info->color_formats = DRM_COLOR_FORMAT_RGB444; 4375 if (edid_ext[3] & EDID_CEA_YCRCB444) 4376 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4377 if (edid_ext[3] & EDID_CEA_YCRCB422) 4378 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 4379 4380 if (cea_db_offsets(edid_ext, &start, &end)) 4381 return; 4382 4383 for_each_cea_db(edid_ext, i, start, end) { 4384 const u8 *db = &edid_ext[i]; 4385 4386 if (cea_db_is_hdmi_vsdb(db)) 4387 drm_parse_hdmi_vsdb_video(connector, db); 4388 if (cea_db_is_hdmi_forum_vsdb(db)) 4389 drm_parse_hdmi_forum_vsdb(connector, db); 4390 if (cea_db_is_y420cmdb(db)) 4391 drm_parse_y420cmdb_bitmap(connector, db); 4392 } 4393 } 4394 4395 static void drm_add_display_info(struct drm_connector *connector, 4396 struct edid *edid) 4397 { 4398 struct drm_display_info *info = &connector->display_info; 4399 4400 info->width_mm = edid->width_cm * 10; 4401 info->height_mm = edid->height_cm * 10; 4402 4403 /* driver figures it out in this case */ 4404 info->bpc = 0; 4405 info->color_formats = 0; 4406 info->cea_rev = 0; 4407 info->max_tmds_clock = 0; 4408 info->dvi_dual = false; 4409 4410 if (edid->revision < 3) 4411 return; 4412 4413 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 4414 return; 4415 4416 drm_parse_cea_ext(connector, edid); 4417 4418 /* 4419 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 4420 * 4421 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 4422 * tells us to assume 8 bpc color depth if the EDID doesn't have 4423 * extensions which tell otherwise. 4424 */ 4425 if ((info->bpc == 0) && (edid->revision < 4) && 4426 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) { 4427 info->bpc = 8; 4428 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n", 4429 connector->name, info->bpc); 4430 } 4431 4432 /* Only defined for 1.4 with digital displays */ 4433 if (edid->revision < 4) 4434 return; 4435 4436 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 4437 case DRM_EDID_DIGITAL_DEPTH_6: 4438 info->bpc = 6; 4439 break; 4440 case DRM_EDID_DIGITAL_DEPTH_8: 4441 info->bpc = 8; 4442 break; 4443 case DRM_EDID_DIGITAL_DEPTH_10: 4444 info->bpc = 10; 4445 break; 4446 case DRM_EDID_DIGITAL_DEPTH_12: 4447 info->bpc = 12; 4448 break; 4449 case DRM_EDID_DIGITAL_DEPTH_14: 4450 info->bpc = 14; 4451 break; 4452 case DRM_EDID_DIGITAL_DEPTH_16: 4453 info->bpc = 16; 4454 break; 4455 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 4456 default: 4457 info->bpc = 0; 4458 break; 4459 } 4460 4461 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 4462 connector->name, info->bpc); 4463 4464 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 4465 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 4466 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4467 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 4468 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 4469 } 4470 4471 static int validate_displayid(u8 *displayid, int length, int idx) 4472 { 4473 int i; 4474 u8 csum = 0; 4475 struct displayid_hdr *base; 4476 4477 base = (struct displayid_hdr *)&displayid[idx]; 4478 4479 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n", 4480 base->rev, base->bytes, base->prod_id, base->ext_count); 4481 4482 if (base->bytes + 5 > length - idx) 4483 return -EINVAL; 4484 for (i = idx; i <= base->bytes + 5; i++) { 4485 csum += displayid[i]; 4486 } 4487 if (csum) { 4488 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum); 4489 return -EINVAL; 4490 } 4491 return 0; 4492 } 4493 4494 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 4495 struct displayid_detailed_timings_1 *timings) 4496 { 4497 struct drm_display_mode *mode; 4498 unsigned pixel_clock = (timings->pixel_clock[0] | 4499 (timings->pixel_clock[1] << 8) | 4500 (timings->pixel_clock[2] << 16)); 4501 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 4502 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 4503 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 4504 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 4505 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 4506 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 4507 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 4508 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 4509 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 4510 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 4511 mode = drm_mode_create(dev); 4512 if (!mode) 4513 return NULL; 4514 4515 mode->clock = pixel_clock * 10; 4516 mode->hdisplay = hactive; 4517 mode->hsync_start = mode->hdisplay + hsync; 4518 mode->hsync_end = mode->hsync_start + hsync_width; 4519 mode->htotal = mode->hdisplay + hblank; 4520 4521 mode->vdisplay = vactive; 4522 mode->vsync_start = mode->vdisplay + vsync; 4523 mode->vsync_end = mode->vsync_start + vsync_width; 4524 mode->vtotal = mode->vdisplay + vblank; 4525 4526 mode->flags = 0; 4527 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 4528 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 4529 mode->type = DRM_MODE_TYPE_DRIVER; 4530 4531 if (timings->flags & 0x80) 4532 mode->type |= DRM_MODE_TYPE_PREFERRED; 4533 mode->vrefresh = drm_mode_vrefresh(mode); 4534 drm_mode_set_name(mode); 4535 4536 return mode; 4537 } 4538 4539 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 4540 struct displayid_block *block) 4541 { 4542 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 4543 int i; 4544 int num_timings; 4545 struct drm_display_mode *newmode; 4546 int num_modes = 0; 4547 /* blocks must be multiple of 20 bytes length */ 4548 if (block->num_bytes % 20) 4549 return 0; 4550 4551 num_timings = block->num_bytes / 20; 4552 for (i = 0; i < num_timings; i++) { 4553 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 4554 4555 newmode = drm_mode_displayid_detailed(connector->dev, timings); 4556 if (!newmode) 4557 continue; 4558 4559 drm_mode_probed_add(connector, newmode); 4560 num_modes++; 4561 } 4562 return num_modes; 4563 } 4564 4565 static int add_displayid_detailed_modes(struct drm_connector *connector, 4566 struct edid *edid) 4567 { 4568 u8 *displayid; 4569 int ret; 4570 int idx = 1; 4571 int length = EDID_LENGTH; 4572 struct displayid_block *block; 4573 int num_modes = 0; 4574 4575 displayid = drm_find_displayid_extension(edid); 4576 if (!displayid) 4577 return 0; 4578 4579 ret = validate_displayid(displayid, length, idx); 4580 if (ret) 4581 return 0; 4582 4583 idx += sizeof(struct displayid_hdr); 4584 while (block = (struct displayid_block *)&displayid[idx], 4585 idx + sizeof(struct displayid_block) <= length && 4586 idx + sizeof(struct displayid_block) + block->num_bytes <= length && 4587 block->num_bytes > 0) { 4588 idx += block->num_bytes + sizeof(struct displayid_block); 4589 switch (block->tag) { 4590 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 4591 num_modes += add_displayid_detailed_1_modes(connector, block); 4592 break; 4593 } 4594 } 4595 return num_modes; 4596 } 4597 4598 /** 4599 * drm_add_edid_modes - add modes from EDID data, if available 4600 * @connector: connector we're probing 4601 * @edid: EDID data 4602 * 4603 * Add the specified modes to the connector's mode list. Also fills out the 4604 * &drm_display_info structure in @connector with any information which can be 4605 * derived from the edid. 4606 * 4607 * Return: The number of modes added or 0 if we couldn't find any. 4608 */ 4609 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 4610 { 4611 int num_modes = 0; 4612 u32 quirks; 4613 4614 if (edid == NULL) { 4615 return 0; 4616 } 4617 if (!drm_edid_is_valid(edid)) { 4618 dev_warn(connector->dev->dev, "%s: EDID invalid.\n", 4619 connector->name); 4620 return 0; 4621 } 4622 4623 quirks = edid_get_quirks(edid); 4624 4625 /* 4626 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. 4627 * To avoid multiple parsing of same block, lets parse that map 4628 * from sink info, before parsing CEA modes. 4629 */ 4630 drm_add_display_info(connector, edid); 4631 4632 /* 4633 * EDID spec says modes should be preferred in this order: 4634 * - preferred detailed mode 4635 * - other detailed modes from base block 4636 * - detailed modes from extension blocks 4637 * - CVT 3-byte code modes 4638 * - standard timing codes 4639 * - established timing codes 4640 * - modes inferred from GTF or CVT range information 4641 * 4642 * We get this pretty much right. 4643 * 4644 * XXX order for additional mode types in extension blocks? 4645 */ 4646 num_modes += add_detailed_modes(connector, edid, quirks); 4647 num_modes += add_cvt_modes(connector, edid); 4648 num_modes += add_standard_modes(connector, edid); 4649 num_modes += add_established_modes(connector, edid); 4650 num_modes += add_cea_modes(connector, edid); 4651 num_modes += add_alternate_cea_modes(connector, edid); 4652 num_modes += add_displayid_detailed_modes(connector, edid); 4653 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 4654 num_modes += add_inferred_modes(connector, edid); 4655 4656 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 4657 edid_fixup_preferred(connector, quirks); 4658 4659 if (quirks & EDID_QUIRK_FORCE_6BPC) 4660 connector->display_info.bpc = 6; 4661 4662 if (quirks & EDID_QUIRK_FORCE_8BPC) 4663 connector->display_info.bpc = 8; 4664 4665 if (quirks & EDID_QUIRK_FORCE_10BPC) 4666 connector->display_info.bpc = 10; 4667 4668 if (quirks & EDID_QUIRK_FORCE_12BPC) 4669 connector->display_info.bpc = 12; 4670 4671 return num_modes; 4672 } 4673 EXPORT_SYMBOL(drm_add_edid_modes); 4674 4675 /** 4676 * drm_add_modes_noedid - add modes for the connectors without EDID 4677 * @connector: connector we're probing 4678 * @hdisplay: the horizontal display limit 4679 * @vdisplay: the vertical display limit 4680 * 4681 * Add the specified modes to the connector's mode list. Only when the 4682 * hdisplay/vdisplay is not beyond the given limit, it will be added. 4683 * 4684 * Return: The number of modes added or 0 if we couldn't find any. 4685 */ 4686 int drm_add_modes_noedid(struct drm_connector *connector, 4687 int hdisplay, int vdisplay) 4688 { 4689 int i, count, num_modes = 0; 4690 struct drm_display_mode *mode; 4691 struct drm_device *dev = connector->dev; 4692 4693 count = ARRAY_SIZE(drm_dmt_modes); 4694 if (hdisplay < 0) 4695 hdisplay = 0; 4696 if (vdisplay < 0) 4697 vdisplay = 0; 4698 4699 for (i = 0; i < count; i++) { 4700 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 4701 if (hdisplay && vdisplay) { 4702 /* 4703 * Only when two are valid, they will be used to check 4704 * whether the mode should be added to the mode list of 4705 * the connector. 4706 */ 4707 if (ptr->hdisplay > hdisplay || 4708 ptr->vdisplay > vdisplay) 4709 continue; 4710 } 4711 if (drm_mode_vrefresh(ptr) > 61) 4712 continue; 4713 mode = drm_mode_duplicate(dev, ptr); 4714 if (mode) { 4715 drm_mode_probed_add(connector, mode); 4716 num_modes++; 4717 } 4718 } 4719 return num_modes; 4720 } 4721 EXPORT_SYMBOL(drm_add_modes_noedid); 4722 4723 /** 4724 * drm_set_preferred_mode - Sets the preferred mode of a connector 4725 * @connector: connector whose mode list should be processed 4726 * @hpref: horizontal resolution of preferred mode 4727 * @vpref: vertical resolution of preferred mode 4728 * 4729 * Marks a mode as preferred if it matches the resolution specified by @hpref 4730 * and @vpref. 4731 */ 4732 void drm_set_preferred_mode(struct drm_connector *connector, 4733 int hpref, int vpref) 4734 { 4735 struct drm_display_mode *mode; 4736 4737 list_for_each_entry(mode, &connector->probed_modes, head) { 4738 if (mode->hdisplay == hpref && 4739 mode->vdisplay == vpref) 4740 mode->type |= DRM_MODE_TYPE_PREFERRED; 4741 } 4742 } 4743 EXPORT_SYMBOL(drm_set_preferred_mode); 4744 4745 /** 4746 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 4747 * data from a DRM display mode 4748 * @frame: HDMI AVI infoframe 4749 * @mode: DRM display mode 4750 * @is_hdmi2_sink: Sink is HDMI 2.0 compliant 4751 * 4752 * Return: 0 on success or a negative error code on failure. 4753 */ 4754 int 4755 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 4756 const struct drm_display_mode *mode, 4757 bool is_hdmi2_sink) 4758 { 4759 int err; 4760 4761 if (!frame || !mode) 4762 return -EINVAL; 4763 4764 err = hdmi_avi_infoframe_init(frame); 4765 if (err < 0) 4766 return err; 4767 4768 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 4769 frame->pixel_repeat = 1; 4770 4771 frame->video_code = drm_match_cea_mode(mode); 4772 4773 /* 4774 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but 4775 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we 4776 * have to make sure we dont break HDMI 1.4 sinks. 4777 */ 4778 if (!is_hdmi2_sink && frame->video_code > 64) 4779 frame->video_code = 0; 4780 4781 /* 4782 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 4783 * we should send its VIC in vendor infoframes, else send the 4784 * VIC in AVI infoframes. Lets check if this mode is present in 4785 * HDMI 1.4b 4K modes 4786 */ 4787 if (frame->video_code) { 4788 u8 vendor_if_vic = drm_match_hdmi_mode(mode); 4789 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK; 4790 4791 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d) 4792 frame->video_code = 0; 4793 } 4794 4795 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 4796 4797 /* 4798 * Populate picture aspect ratio from either 4799 * user input (if specified) or from the CEA mode list. 4800 */ 4801 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 || 4802 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9) 4803 frame->picture_aspect = mode->picture_aspect_ratio; 4804 else if (frame->video_code > 0) 4805 frame->picture_aspect = drm_get_cea_aspect_ratio( 4806 frame->video_code); 4807 4808 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 4809 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 4810 4811 return 0; 4812 } 4813 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 4814 4815 /** 4816 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 4817 * quantization range information 4818 * @frame: HDMI AVI infoframe 4819 * @mode: DRM display mode 4820 * @rgb_quant_range: RGB quantization range (Q) 4821 * @rgb_quant_range_selectable: Sink support selectable RGB quantization range (QS) 4822 */ 4823 void 4824 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 4825 const struct drm_display_mode *mode, 4826 enum hdmi_quantization_range rgb_quant_range, 4827 bool rgb_quant_range_selectable) 4828 { 4829 /* 4830 * CEA-861: 4831 * "A Source shall not send a non-zero Q value that does not correspond 4832 * to the default RGB Quantization Range for the transmitted Picture 4833 * unless the Sink indicates support for the Q bit in a Video 4834 * Capabilities Data Block." 4835 * 4836 * HDMI 2.0 recommends sending non-zero Q when it does match the 4837 * default RGB quantization range for the mode, even when QS=0. 4838 */ 4839 if (rgb_quant_range_selectable || 4840 rgb_quant_range == drm_default_rgb_quant_range(mode)) 4841 frame->quantization_range = rgb_quant_range; 4842 else 4843 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 4844 4845 /* 4846 * CEA-861-F: 4847 * "When transmitting any RGB colorimetry, the Source should set the 4848 * YQ-field to match the RGB Quantization Range being transmitted 4849 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 4850 * set YQ=1) and the Sink shall ignore the YQ-field." 4851 */ 4852 if (rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 4853 frame->ycc_quantization_range = 4854 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 4855 else 4856 frame->ycc_quantization_range = 4857 HDMI_YCC_QUANTIZATION_RANGE_FULL; 4858 } 4859 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 4860 4861 static enum hdmi_3d_structure 4862 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 4863 { 4864 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 4865 4866 switch (layout) { 4867 case DRM_MODE_FLAG_3D_FRAME_PACKING: 4868 return HDMI_3D_STRUCTURE_FRAME_PACKING; 4869 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 4870 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 4871 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 4872 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 4873 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 4874 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 4875 case DRM_MODE_FLAG_3D_L_DEPTH: 4876 return HDMI_3D_STRUCTURE_L_DEPTH; 4877 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 4878 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 4879 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 4880 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 4881 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 4882 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 4883 default: 4884 return HDMI_3D_STRUCTURE_INVALID; 4885 } 4886 } 4887 4888 /** 4889 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 4890 * data from a DRM display mode 4891 * @frame: HDMI vendor infoframe 4892 * @mode: DRM display mode 4893 * 4894 * Note that there's is a need to send HDMI vendor infoframes only when using a 4895 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 4896 * function will return -EINVAL, error that can be safely ignored. 4897 * 4898 * Return: 0 on success or a negative error code on failure. 4899 */ 4900 int 4901 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 4902 const struct drm_display_mode *mode) 4903 { 4904 int err; 4905 u32 s3d_flags; 4906 u8 vic; 4907 4908 if (!frame || !mode) 4909 return -EINVAL; 4910 4911 vic = drm_match_hdmi_mode(mode); 4912 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; 4913 4914 if (!vic && !s3d_flags) 4915 return -EINVAL; 4916 4917 if (vic && s3d_flags) 4918 return -EINVAL; 4919 4920 err = hdmi_vendor_infoframe_init(frame); 4921 if (err < 0) 4922 return err; 4923 4924 if (vic) 4925 frame->vic = vic; 4926 else 4927 frame->s3d_struct = s3d_structure_from_display_mode(mode); 4928 4929 return 0; 4930 } 4931 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 4932 4933 static int drm_parse_tiled_block(struct drm_connector *connector, 4934 struct displayid_block *block) 4935 { 4936 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 4937 u16 w, h; 4938 u8 tile_v_loc, tile_h_loc; 4939 u8 num_v_tile, num_h_tile; 4940 struct drm_tile_group *tg; 4941 4942 w = tile->tile_size[0] | tile->tile_size[1] << 8; 4943 h = tile->tile_size[2] | tile->tile_size[3] << 8; 4944 4945 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 4946 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 4947 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 4948 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 4949 4950 connector->has_tile = true; 4951 if (tile->tile_cap & 0x80) 4952 connector->tile_is_single_monitor = true; 4953 4954 connector->num_h_tile = num_h_tile + 1; 4955 connector->num_v_tile = num_v_tile + 1; 4956 connector->tile_h_loc = tile_h_loc; 4957 connector->tile_v_loc = tile_v_loc; 4958 connector->tile_h_size = w + 1; 4959 connector->tile_v_size = h + 1; 4960 4961 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); 4962 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); 4963 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", 4964 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); 4965 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 4966 4967 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 4968 if (!tg) { 4969 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 4970 } 4971 if (!tg) 4972 return -ENOMEM; 4973 4974 if (connector->tile_group != tg) { 4975 /* if we haven't got a pointer, 4976 take the reference, drop ref to old tile group */ 4977 if (connector->tile_group) { 4978 drm_mode_put_tile_group(connector->dev, connector->tile_group); 4979 } 4980 connector->tile_group = tg; 4981 } else 4982 /* if same tile group, then release the ref we just took. */ 4983 drm_mode_put_tile_group(connector->dev, tg); 4984 return 0; 4985 } 4986 4987 static int drm_parse_display_id(struct drm_connector *connector, 4988 u8 *displayid, int length, 4989 bool is_edid_extension) 4990 { 4991 /* if this is an EDID extension the first byte will be 0x70 */ 4992 int idx = 0; 4993 struct displayid_block *block; 4994 int ret; 4995 4996 if (is_edid_extension) 4997 idx = 1; 4998 4999 ret = validate_displayid(displayid, length, idx); 5000 if (ret) 5001 return ret; 5002 5003 idx += sizeof(struct displayid_hdr); 5004 while (block = (struct displayid_block *)&displayid[idx], 5005 idx + sizeof(struct displayid_block) <= length && 5006 idx + sizeof(struct displayid_block) + block->num_bytes <= length && 5007 block->num_bytes > 0) { 5008 idx += block->num_bytes + sizeof(struct displayid_block); 5009 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n", 5010 block->tag, block->rev, block->num_bytes); 5011 5012 switch (block->tag) { 5013 case DATA_BLOCK_TILED_DISPLAY: 5014 ret = drm_parse_tiled_block(connector, block); 5015 if (ret) 5016 return ret; 5017 break; 5018 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 5019 /* handled in mode gathering code. */ 5020 break; 5021 default: 5022 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag); 5023 break; 5024 } 5025 } 5026 return 0; 5027 } 5028 5029 static void drm_get_displayid(struct drm_connector *connector, 5030 struct edid *edid) 5031 { 5032 void *displayid = NULL; 5033 int ret; 5034 connector->has_tile = false; 5035 displayid = drm_find_displayid_extension(edid); 5036 if (!displayid) { 5037 /* drop reference to any tile group we had */ 5038 goto out_drop_ref; 5039 } 5040 5041 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true); 5042 if (ret < 0) 5043 goto out_drop_ref; 5044 if (!connector->has_tile) 5045 goto out_drop_ref; 5046 return; 5047 out_drop_ref: 5048 if (connector->tile_group) { 5049 drm_mode_put_tile_group(connector->dev, connector->tile_group); 5050 connector->tile_group = NULL; 5051 } 5052 return; 5053 } 5054