1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 31 #include <linux/bitfield.h> 32 #include <linux/byteorder/generic.h> 33 #include <linux/cec.h> 34 #include <linux/export.h> 35 #include <linux/hdmi.h> 36 #include <linux/i2c.h> 37 #include <linux/kernel.h> 38 #include <linux/module.h> 39 #include <linux/pci.h> 40 #include <linux/seq_buf.h> 41 #include <linux/slab.h> 42 #include <linux/vga_switcheroo.h> 43 44 #include <drm/drm_drv.h> 45 #include <drm/drm_edid.h> 46 #include <drm/drm_eld.h> 47 #include <drm/drm_encoder.h> 48 #include <drm/drm_print.h> 49 50 #include "drm_crtc_internal.h" 51 #include "drm_displayid_internal.h" 52 #include "drm_internal.h" 53 54 static int oui(u8 first, u8 second, u8 third) 55 { 56 return (first << 16) | (second << 8) | third; 57 } 58 59 #define EDID_EST_TIMINGS 16 60 #define EDID_STD_TIMINGS 8 61 #define EDID_DETAILED_TIMINGS 4 62 63 /* 64 * EDID blocks out in the wild have a variety of bugs, try to collect 65 * them here (note that userspace may work around broken monitors first, 66 * but fixes should make their way here so that the kernel "just works" 67 * on as many displays as possible). 68 */ 69 70 enum drm_edid_internal_quirk { 71 /* First detailed mode wrong, use largest 60Hz mode */ 72 EDID_QUIRK_PREFER_LARGE_60 = DRM_EDID_QUIRK_NUM, 73 /* Reported 135MHz pixel clock is too high, needs adjustment */ 74 EDID_QUIRK_135_CLOCK_TOO_HIGH, 75 /* Prefer the largest mode at 75 Hz */ 76 EDID_QUIRK_PREFER_LARGE_75, 77 /* Detail timing is in cm not mm */ 78 EDID_QUIRK_DETAILED_IN_CM, 79 /* Detailed timing descriptors have bogus size values, so just take the 80 * maximum size and use that. 81 */ 82 EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE, 83 /* use +hsync +vsync for detailed mode */ 84 EDID_QUIRK_DETAILED_SYNC_PP, 85 /* Force reduced-blanking timings for detailed modes */ 86 EDID_QUIRK_FORCE_REDUCED_BLANKING, 87 /* Force 8bpc */ 88 EDID_QUIRK_FORCE_8BPC, 89 /* Force 12bpc */ 90 EDID_QUIRK_FORCE_12BPC, 91 /* Force 6bpc */ 92 EDID_QUIRK_FORCE_6BPC, 93 /* Force 10bpc */ 94 EDID_QUIRK_FORCE_10BPC, 95 /* Non desktop display (i.e. HMD) */ 96 EDID_QUIRK_NON_DESKTOP, 97 /* Cap the DSC target bitrate to 15bpp */ 98 EDID_QUIRK_CAP_DSC_15BPP, 99 }; 100 101 #define MICROSOFT_IEEE_OUI 0xca125c 102 #define AMD_IEEE_OUI 0x00001A 103 104 #define AMD_VSDB_V3_PAYLOAD_MIN_LEN 15 105 #define AMD_VSDB_V3_PAYLOAD_MAX_LEN 20 106 107 struct amd_vsdb_v3_payload { 108 u8 oui[3]; 109 u8 version; 110 u8 feature_caps; 111 u8 rsvd0[3]; 112 u8 cs_eotf_support; 113 u8 lum1_max; 114 u8 lum1_min; 115 u8 lum2_max; 116 u8 lum2_min; 117 u8 rsvd1[2]; 118 /* 119 * Bytes beyond AMD_VSDB_V3_PAYLOAD_MIN_LEN are optional; a 120 * monitor may provide a payload as short as 15 bytes. Always 121 * check cea_db_payload_len() before accessing extra[]. 122 */ 123 u8 extra[AMD_VSDB_V3_PAYLOAD_MAX_LEN - AMD_VSDB_V3_PAYLOAD_MIN_LEN]; 124 } __packed; 125 126 struct detailed_mode_closure { 127 struct drm_connector *connector; 128 const struct drm_edid *drm_edid; 129 bool preferred; 130 int modes; 131 }; 132 133 struct drm_edid_match_closure { 134 const struct drm_edid_ident *ident; 135 bool matched; 136 }; 137 138 #define LEVEL_DMT 0 139 #define LEVEL_GTF 1 140 #define LEVEL_GTF2 2 141 #define LEVEL_CVT 3 142 143 #define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \ 144 { \ 145 .ident = { \ 146 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, \ 147 vend_chr_2, product_id), \ 148 }, \ 149 .quirks = _quirks \ 150 } 151 152 static const struct edid_quirk { 153 const struct drm_edid_ident ident; 154 u32 quirks; 155 } edid_quirk_list[] = { 156 /* Acer AL1706 */ 157 EDID_QUIRK('A', 'C', 'R', 44358, BIT(EDID_QUIRK_PREFER_LARGE_60)), 158 /* Acer F51 */ 159 EDID_QUIRK('A', 'P', 'I', 0x7602, BIT(EDID_QUIRK_PREFER_LARGE_60)), 160 161 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 162 EDID_QUIRK('A', 'E', 'O', 0, BIT(EDID_QUIRK_FORCE_6BPC)), 163 164 /* BenQ GW2765 */ 165 EDID_QUIRK('B', 'N', 'Q', 0x78d6, BIT(EDID_QUIRK_FORCE_8BPC)), 166 167 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */ 168 EDID_QUIRK('B', 'O', 'E', 0x78b, BIT(EDID_QUIRK_FORCE_6BPC)), 169 170 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 171 EDID_QUIRK('C', 'P', 'T', 0x17df, BIT(EDID_QUIRK_FORCE_6BPC)), 172 173 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ 174 EDID_QUIRK('S', 'D', 'C', 0x3652, BIT(EDID_QUIRK_FORCE_6BPC)), 175 176 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ 177 EDID_QUIRK('B', 'O', 'E', 0x0771, BIT(EDID_QUIRK_FORCE_6BPC)), 178 179 /* Belinea 10 15 55 */ 180 EDID_QUIRK('M', 'A', 'X', 1516, BIT(EDID_QUIRK_PREFER_LARGE_60)), 181 EDID_QUIRK('M', 'A', 'X', 0x77e, BIT(EDID_QUIRK_PREFER_LARGE_60)), 182 183 /* Envision Peripherals, Inc. EN-7100e */ 184 EDID_QUIRK('E', 'P', 'I', 59264, BIT(EDID_QUIRK_135_CLOCK_TOO_HIGH)), 185 /* Envision EN2028 */ 186 EDID_QUIRK('E', 'P', 'I', 8232, BIT(EDID_QUIRK_PREFER_LARGE_60)), 187 188 /* Funai Electronics PM36B */ 189 EDID_QUIRK('F', 'C', 'M', 13600, BIT(EDID_QUIRK_PREFER_LARGE_75) | 190 BIT(EDID_QUIRK_DETAILED_IN_CM)), 191 192 /* LG 27GP950 */ 193 EDID_QUIRK('G', 'S', 'M', 0x5bbf, BIT(EDID_QUIRK_CAP_DSC_15BPP)), 194 195 /* LG 27GN950 */ 196 EDID_QUIRK('G', 'S', 'M', 0x5b9a, BIT(EDID_QUIRK_CAP_DSC_15BPP)), 197 198 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 199 EDID_QUIRK('L', 'G', 'D', 764, BIT(EDID_QUIRK_FORCE_10BPC)), 200 201 /* LG Philips LCD LP154W01-A5 */ 202 EDID_QUIRK('L', 'P', 'L', 0, BIT(EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE)), 203 EDID_QUIRK('L', 'P', 'L', 0x2a00, BIT(EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE)), 204 205 /* Samsung SyncMaster 205BW. Note: irony */ 206 EDID_QUIRK('S', 'A', 'M', 541, BIT(EDID_QUIRK_DETAILED_SYNC_PP)), 207 /* Samsung SyncMaster 22[5-6]BW */ 208 EDID_QUIRK('S', 'A', 'M', 596, BIT(EDID_QUIRK_PREFER_LARGE_60)), 209 EDID_QUIRK('S', 'A', 'M', 638, BIT(EDID_QUIRK_PREFER_LARGE_60)), 210 211 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 212 EDID_QUIRK('S', 'N', 'Y', 0x2541, BIT(EDID_QUIRK_FORCE_12BPC)), 213 214 /* ViewSonic VA2026w */ 215 EDID_QUIRK('V', 'S', 'C', 5020, BIT(EDID_QUIRK_FORCE_REDUCED_BLANKING)), 216 217 /* Medion MD 30217 PG */ 218 EDID_QUIRK('M', 'E', 'D', 0x7b8, BIT(EDID_QUIRK_PREFER_LARGE_75)), 219 220 /* Lenovo G50 */ 221 EDID_QUIRK('S', 'D', 'C', 18514, BIT(EDID_QUIRK_FORCE_6BPC)), 222 223 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 224 EDID_QUIRK('S', 'E', 'C', 0xd033, BIT(EDID_QUIRK_FORCE_8BPC)), 225 226 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 227 EDID_QUIRK('E', 'T', 'R', 13896, BIT(EDID_QUIRK_FORCE_8BPC)), 228 229 /* Valve Index Headset */ 230 EDID_QUIRK('V', 'L', 'V', 0x91a8, BIT(EDID_QUIRK_NON_DESKTOP)), 231 EDID_QUIRK('V', 'L', 'V', 0x91b0, BIT(EDID_QUIRK_NON_DESKTOP)), 232 EDID_QUIRK('V', 'L', 'V', 0x91b1, BIT(EDID_QUIRK_NON_DESKTOP)), 233 EDID_QUIRK('V', 'L', 'V', 0x91b2, BIT(EDID_QUIRK_NON_DESKTOP)), 234 EDID_QUIRK('V', 'L', 'V', 0x91b3, BIT(EDID_QUIRK_NON_DESKTOP)), 235 EDID_QUIRK('V', 'L', 'V', 0x91b4, BIT(EDID_QUIRK_NON_DESKTOP)), 236 EDID_QUIRK('V', 'L', 'V', 0x91b5, BIT(EDID_QUIRK_NON_DESKTOP)), 237 EDID_QUIRK('V', 'L', 'V', 0x91b6, BIT(EDID_QUIRK_NON_DESKTOP)), 238 EDID_QUIRK('V', 'L', 'V', 0x91b7, BIT(EDID_QUIRK_NON_DESKTOP)), 239 EDID_QUIRK('V', 'L', 'V', 0x91b8, BIT(EDID_QUIRK_NON_DESKTOP)), 240 EDID_QUIRK('V', 'L', 'V', 0x91b9, BIT(EDID_QUIRK_NON_DESKTOP)), 241 EDID_QUIRK('V', 'L', 'V', 0x91ba, BIT(EDID_QUIRK_NON_DESKTOP)), 242 EDID_QUIRK('V', 'L', 'V', 0x91bb, BIT(EDID_QUIRK_NON_DESKTOP)), 243 EDID_QUIRK('V', 'L', 'V', 0x91bc, BIT(EDID_QUIRK_NON_DESKTOP)), 244 EDID_QUIRK('V', 'L', 'V', 0x91bd, BIT(EDID_QUIRK_NON_DESKTOP)), 245 EDID_QUIRK('V', 'L', 'V', 0x91be, BIT(EDID_QUIRK_NON_DESKTOP)), 246 EDID_QUIRK('V', 'L', 'V', 0x91bf, BIT(EDID_QUIRK_NON_DESKTOP)), 247 248 /* HTC Vive and Vive Pro VR Headsets */ 249 EDID_QUIRK('H', 'V', 'R', 0xaa01, BIT(EDID_QUIRK_NON_DESKTOP)), 250 EDID_QUIRK('H', 'V', 'R', 0xaa02, BIT(EDID_QUIRK_NON_DESKTOP)), 251 252 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */ 253 EDID_QUIRK('O', 'V', 'R', 0x0001, BIT(EDID_QUIRK_NON_DESKTOP)), 254 EDID_QUIRK('O', 'V', 'R', 0x0003, BIT(EDID_QUIRK_NON_DESKTOP)), 255 EDID_QUIRK('O', 'V', 'R', 0x0004, BIT(EDID_QUIRK_NON_DESKTOP)), 256 EDID_QUIRK('O', 'V', 'R', 0x0012, BIT(EDID_QUIRK_NON_DESKTOP)), 257 258 /* Windows Mixed Reality Headsets */ 259 EDID_QUIRK('A', 'C', 'R', 0x7fce, BIT(EDID_QUIRK_NON_DESKTOP)), 260 EDID_QUIRK('L', 'E', 'N', 0x0408, BIT(EDID_QUIRK_NON_DESKTOP)), 261 EDID_QUIRK('F', 'U', 'J', 0x1970, BIT(EDID_QUIRK_NON_DESKTOP)), 262 EDID_QUIRK('D', 'E', 'L', 0x7fce, BIT(EDID_QUIRK_NON_DESKTOP)), 263 EDID_QUIRK('S', 'E', 'C', 0x144a, BIT(EDID_QUIRK_NON_DESKTOP)), 264 EDID_QUIRK('A', 'U', 'S', 0xc102, BIT(EDID_QUIRK_NON_DESKTOP)), 265 266 /* Sony PlayStation VR Headset */ 267 EDID_QUIRK('S', 'N', 'Y', 0x0704, BIT(EDID_QUIRK_NON_DESKTOP)), 268 269 /* Sensics VR Headsets */ 270 EDID_QUIRK('S', 'E', 'N', 0x1019, BIT(EDID_QUIRK_NON_DESKTOP)), 271 272 /* OSVR HDK and HDK2 VR Headsets */ 273 EDID_QUIRK('S', 'V', 'R', 0x1019, BIT(EDID_QUIRK_NON_DESKTOP)), 274 EDID_QUIRK('A', 'U', 'O', 0x1111, BIT(EDID_QUIRK_NON_DESKTOP)), 275 276 /* LQ116M1JW10 displays noise when 8 bpc, but display fine as 6 bpc */ 277 EDID_QUIRK('S', 'H', 'P', 0x154c, BIT(EDID_QUIRK_FORCE_6BPC)), 278 279 /* 280 * @drm_edid_internal_quirk entries end here, following with the 281 * @drm_edid_quirk entries. 282 */ 283 284 /* HP ZR24w DP AUX DPCD access requires probing to prevent corruption. */ 285 EDID_QUIRK('H', 'W', 'P', 0x2869, BIT(DRM_EDID_QUIRK_DP_DPCD_PROBE)), 286 }; 287 288 /* 289 * Autogenerated from the DMT spec. 290 * This table is copied from xfree86/modes/xf86EdidModes.c. 291 */ 292 static const struct drm_display_mode drm_dmt_modes[] = { 293 /* 0x01 - 640x350@85Hz */ 294 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 295 736, 832, 0, 350, 382, 385, 445, 0, 296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 297 /* 0x02 - 640x400@85Hz */ 298 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 299 736, 832, 0, 400, 401, 404, 445, 0, 300 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 301 /* 0x03 - 720x400@85Hz */ 302 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 303 828, 936, 0, 400, 401, 404, 446, 0, 304 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 305 /* 0x04 - 640x480@60Hz */ 306 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 307 752, 800, 0, 480, 490, 492, 525, 0, 308 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 309 /* 0x05 - 640x480@72Hz */ 310 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 311 704, 832, 0, 480, 489, 492, 520, 0, 312 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 313 /* 0x06 - 640x480@75Hz */ 314 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 315 720, 840, 0, 480, 481, 484, 500, 0, 316 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 317 /* 0x07 - 640x480@85Hz */ 318 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 319 752, 832, 0, 480, 481, 484, 509, 0, 320 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 321 /* 0x08 - 800x600@56Hz */ 322 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 323 896, 1024, 0, 600, 601, 603, 625, 0, 324 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 325 /* 0x09 - 800x600@60Hz */ 326 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 327 968, 1056, 0, 600, 601, 605, 628, 0, 328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 329 /* 0x0a - 800x600@72Hz */ 330 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 331 976, 1040, 0, 600, 637, 643, 666, 0, 332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 333 /* 0x0b - 800x600@75Hz */ 334 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 335 896, 1056, 0, 600, 601, 604, 625, 0, 336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 337 /* 0x0c - 800x600@85Hz */ 338 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 339 896, 1048, 0, 600, 601, 604, 631, 0, 340 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 341 /* 0x0d - 800x600@120Hz RB */ 342 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 343 880, 960, 0, 600, 603, 607, 636, 0, 344 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 345 /* 0x0e - 848x480@60Hz */ 346 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 347 976, 1088, 0, 480, 486, 494, 517, 0, 348 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 349 /* 0x0f - 1024x768@43Hz, interlace */ 350 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 351 1208, 1264, 0, 768, 768, 776, 817, 0, 352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 353 DRM_MODE_FLAG_INTERLACE) }, 354 /* 0x10 - 1024x768@60Hz */ 355 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 356 1184, 1344, 0, 768, 771, 777, 806, 0, 357 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 358 /* 0x11 - 1024x768@70Hz */ 359 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 360 1184, 1328, 0, 768, 771, 777, 806, 0, 361 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 362 /* 0x12 - 1024x768@75Hz */ 363 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 364 1136, 1312, 0, 768, 769, 772, 800, 0, 365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 366 /* 0x13 - 1024x768@85Hz */ 367 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 368 1168, 1376, 0, 768, 769, 772, 808, 0, 369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 370 /* 0x14 - 1024x768@120Hz RB */ 371 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 372 1104, 1184, 0, 768, 771, 775, 813, 0, 373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 374 /* 0x15 - 1152x864@75Hz */ 375 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 376 1344, 1600, 0, 864, 865, 868, 900, 0, 377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 378 /* 0x55 - 1280x720@60Hz */ 379 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 380 1430, 1650, 0, 720, 725, 730, 750, 0, 381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 382 /* 0x16 - 1280x768@60Hz RB */ 383 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 384 1360, 1440, 0, 768, 771, 778, 790, 0, 385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 386 /* 0x17 - 1280x768@60Hz */ 387 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 388 1472, 1664, 0, 768, 771, 778, 798, 0, 389 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 390 /* 0x18 - 1280x768@75Hz */ 391 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 392 1488, 1696, 0, 768, 771, 778, 805, 0, 393 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 394 /* 0x19 - 1280x768@85Hz */ 395 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 396 1496, 1712, 0, 768, 771, 778, 809, 0, 397 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 398 /* 0x1a - 1280x768@120Hz RB */ 399 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 400 1360, 1440, 0, 768, 771, 778, 813, 0, 401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 402 /* 0x1b - 1280x800@60Hz RB */ 403 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 404 1360, 1440, 0, 800, 803, 809, 823, 0, 405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 406 /* 0x1c - 1280x800@60Hz */ 407 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 408 1480, 1680, 0, 800, 803, 809, 831, 0, 409 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 410 /* 0x1d - 1280x800@75Hz */ 411 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 412 1488, 1696, 0, 800, 803, 809, 838, 0, 413 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 414 /* 0x1e - 1280x800@85Hz */ 415 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 416 1496, 1712, 0, 800, 803, 809, 843, 0, 417 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 418 /* 0x1f - 1280x800@120Hz RB */ 419 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 420 1360, 1440, 0, 800, 803, 809, 847, 0, 421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 422 /* 0x20 - 1280x960@60Hz */ 423 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 424 1488, 1800, 0, 960, 961, 964, 1000, 0, 425 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 426 /* 0x21 - 1280x960@85Hz */ 427 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 428 1504, 1728, 0, 960, 961, 964, 1011, 0, 429 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 430 /* 0x22 - 1280x960@120Hz RB */ 431 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 432 1360, 1440, 0, 960, 963, 967, 1017, 0, 433 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 434 /* 0x23 - 1280x1024@60Hz */ 435 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 436 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 438 /* 0x24 - 1280x1024@75Hz */ 439 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 440 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 442 /* 0x25 - 1280x1024@85Hz */ 443 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 444 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 446 /* 0x26 - 1280x1024@120Hz RB */ 447 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 448 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 450 /* 0x27 - 1360x768@60Hz */ 451 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 452 1536, 1792, 0, 768, 771, 777, 795, 0, 453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 454 /* 0x28 - 1360x768@120Hz RB */ 455 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 456 1440, 1520, 0, 768, 771, 776, 813, 0, 457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 458 /* 0x51 - 1366x768@60Hz */ 459 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 460 1579, 1792, 0, 768, 771, 774, 798, 0, 461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 462 /* 0x56 - 1366x768@60Hz */ 463 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 464 1436, 1500, 0, 768, 769, 772, 800, 0, 465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 466 /* 0x29 - 1400x1050@60Hz RB */ 467 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 468 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 470 /* 0x2a - 1400x1050@60Hz */ 471 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 472 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 473 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 474 /* 0x2b - 1400x1050@75Hz */ 475 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 476 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 477 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 478 /* 0x2c - 1400x1050@85Hz */ 479 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 480 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 481 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 482 /* 0x2d - 1400x1050@120Hz RB */ 483 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 484 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 486 /* 0x2e - 1440x900@60Hz RB */ 487 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 488 1520, 1600, 0, 900, 903, 909, 926, 0, 489 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 490 /* 0x2f - 1440x900@60Hz */ 491 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 492 1672, 1904, 0, 900, 903, 909, 934, 0, 493 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 494 /* 0x30 - 1440x900@75Hz */ 495 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 496 1688, 1936, 0, 900, 903, 909, 942, 0, 497 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 498 /* 0x31 - 1440x900@85Hz */ 499 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 500 1696, 1952, 0, 900, 903, 909, 948, 0, 501 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 502 /* 0x32 - 1440x900@120Hz RB */ 503 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 504 1520, 1600, 0, 900, 903, 909, 953, 0, 505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 506 /* 0x53 - 1600x900@60Hz */ 507 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 508 1704, 1800, 0, 900, 901, 904, 1000, 0, 509 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 510 /* 0x33 - 1600x1200@60Hz */ 511 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 512 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 513 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 514 /* 0x34 - 1600x1200@65Hz */ 515 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 516 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 518 /* 0x35 - 1600x1200@70Hz */ 519 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 520 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 521 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 522 /* 0x36 - 1600x1200@75Hz */ 523 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 524 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 525 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 526 /* 0x37 - 1600x1200@85Hz */ 527 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 528 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 529 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 530 /* 0x38 - 1600x1200@120Hz RB */ 531 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 532 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 533 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 534 /* 0x39 - 1680x1050@60Hz RB */ 535 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 536 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 537 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 538 /* 0x3a - 1680x1050@60Hz */ 539 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 540 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 541 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 542 /* 0x3b - 1680x1050@75Hz */ 543 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 544 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 545 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 546 /* 0x3c - 1680x1050@85Hz */ 547 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 548 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 549 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 550 /* 0x3d - 1680x1050@120Hz RB */ 551 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 552 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 554 /* 0x3e - 1792x1344@60Hz */ 555 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 556 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 557 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 558 /* 0x3f - 1792x1344@75Hz */ 559 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 560 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 561 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 562 /* 0x40 - 1792x1344@120Hz RB */ 563 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 564 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 566 /* 0x41 - 1856x1392@60Hz */ 567 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 568 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 569 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 570 /* 0x42 - 1856x1392@75Hz */ 571 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 572 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 573 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 574 /* 0x43 - 1856x1392@120Hz RB */ 575 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 576 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 577 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 578 /* 0x52 - 1920x1080@60Hz */ 579 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 580 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 581 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 582 /* 0x44 - 1920x1200@60Hz RB */ 583 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 584 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 585 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 586 /* 0x45 - 1920x1200@60Hz */ 587 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 588 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 589 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 590 /* 0x46 - 1920x1200@75Hz */ 591 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 592 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 593 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 594 /* 0x47 - 1920x1200@85Hz */ 595 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 596 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 597 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 598 /* 0x48 - 1920x1200@120Hz RB */ 599 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 600 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 601 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 602 /* 0x49 - 1920x1440@60Hz */ 603 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 604 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 605 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 606 /* 0x4a - 1920x1440@75Hz */ 607 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 608 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 609 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 610 /* 0x4b - 1920x1440@120Hz RB */ 611 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 612 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 613 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 614 /* 0x54 - 2048x1152@60Hz */ 615 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 616 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 617 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 618 /* 0x4c - 2560x1600@60Hz RB */ 619 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 620 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 621 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 622 /* 0x4d - 2560x1600@60Hz */ 623 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 624 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 625 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 626 /* 0x4e - 2560x1600@75Hz */ 627 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 628 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 629 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 630 /* 0x4f - 2560x1600@85Hz */ 631 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 632 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 633 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 634 /* 0x50 - 2560x1600@120Hz RB */ 635 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 636 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 637 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 638 /* 0x57 - 4096x2160@60Hz RB */ 639 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 640 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 641 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 642 /* 0x58 - 4096x2160@59.94Hz RB */ 643 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 644 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 645 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 646 }; 647 648 /* 649 * These more or less come from the DMT spec. The 720x400 modes are 650 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 651 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 652 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 653 * mode. 654 * 655 * The DMT modes have been fact-checked; the rest are mild guesses. 656 */ 657 static const struct drm_display_mode edid_est_modes[] = { 658 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 659 968, 1056, 0, 600, 601, 605, 628, 0, 660 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 661 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 662 896, 1024, 0, 600, 601, 603, 625, 0, 663 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 664 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 665 720, 840, 0, 480, 481, 484, 500, 0, 666 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 667 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 668 704, 832, 0, 480, 489, 492, 520, 0, 669 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 670 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 671 768, 864, 0, 480, 483, 486, 525, 0, 672 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 673 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 674 752, 800, 0, 480, 490, 492, 525, 0, 675 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 676 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 677 846, 900, 0, 400, 421, 423, 449, 0, 678 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 679 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 680 846, 900, 0, 400, 412, 414, 449, 0, 681 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 682 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 683 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 684 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 685 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 686 1136, 1312, 0, 768, 769, 772, 800, 0, 687 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 688 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 689 1184, 1328, 0, 768, 771, 777, 806, 0, 690 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 691 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 692 1184, 1344, 0, 768, 771, 777, 806, 0, 693 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 694 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 695 1208, 1264, 0, 768, 768, 776, 817, 0, 696 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 697 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 698 928, 1152, 0, 624, 625, 628, 667, 0, 699 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 700 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 701 896, 1056, 0, 600, 601, 604, 625, 0, 702 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 703 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 704 976, 1040, 0, 600, 637, 643, 666, 0, 705 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 706 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 707 1344, 1600, 0, 864, 865, 868, 900, 0, 708 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 709 }; 710 711 struct minimode { 712 short w; 713 short h; 714 short r; 715 short rb; 716 }; 717 718 static const struct minimode est3_modes[] = { 719 /* byte 6 */ 720 { 640, 350, 85, 0 }, 721 { 640, 400, 85, 0 }, 722 { 720, 400, 85, 0 }, 723 { 640, 480, 85, 0 }, 724 { 848, 480, 60, 0 }, 725 { 800, 600, 85, 0 }, 726 { 1024, 768, 85, 0 }, 727 { 1152, 864, 75, 0 }, 728 /* byte 7 */ 729 { 1280, 768, 60, 1 }, 730 { 1280, 768, 60, 0 }, 731 { 1280, 768, 75, 0 }, 732 { 1280, 768, 85, 0 }, 733 { 1280, 960, 60, 0 }, 734 { 1280, 960, 85, 0 }, 735 { 1280, 1024, 60, 0 }, 736 { 1280, 1024, 85, 0 }, 737 /* byte 8 */ 738 { 1360, 768, 60, 0 }, 739 { 1440, 900, 60, 1 }, 740 { 1440, 900, 60, 0 }, 741 { 1440, 900, 75, 0 }, 742 { 1440, 900, 85, 0 }, 743 { 1400, 1050, 60, 1 }, 744 { 1400, 1050, 60, 0 }, 745 { 1400, 1050, 75, 0 }, 746 /* byte 9 */ 747 { 1400, 1050, 85, 0 }, 748 { 1680, 1050, 60, 1 }, 749 { 1680, 1050, 60, 0 }, 750 { 1680, 1050, 75, 0 }, 751 { 1680, 1050, 85, 0 }, 752 { 1600, 1200, 60, 0 }, 753 { 1600, 1200, 65, 0 }, 754 { 1600, 1200, 70, 0 }, 755 /* byte 10 */ 756 { 1600, 1200, 75, 0 }, 757 { 1600, 1200, 85, 0 }, 758 { 1792, 1344, 60, 0 }, 759 { 1792, 1344, 75, 0 }, 760 { 1856, 1392, 60, 0 }, 761 { 1856, 1392, 75, 0 }, 762 { 1920, 1200, 60, 1 }, 763 { 1920, 1200, 60, 0 }, 764 /* byte 11 */ 765 { 1920, 1200, 75, 0 }, 766 { 1920, 1200, 85, 0 }, 767 { 1920, 1440, 60, 0 }, 768 { 1920, 1440, 75, 0 }, 769 }; 770 771 static const struct minimode extra_modes[] = { 772 { 1024, 576, 60, 0 }, 773 { 1366, 768, 60, 0 }, 774 { 1600, 900, 60, 0 }, 775 { 1680, 945, 60, 0 }, 776 { 1920, 1080, 60, 0 }, 777 { 2048, 1152, 60, 0 }, 778 { 2048, 1536, 60, 0 }, 779 }; 780 781 /* 782 * From CEA/CTA-861 spec. 783 * 784 * Do not access directly, instead always use cea_mode_for_vic(). 785 */ 786 static const struct drm_display_mode edid_cea_modes_1[] = { 787 /* 1 - 640x480@60Hz 4:3 */ 788 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 789 752, 800, 0, 480, 490, 492, 525, 0, 790 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 791 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 792 /* 2 - 720x480@60Hz 4:3 */ 793 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 794 798, 858, 0, 480, 489, 495, 525, 0, 795 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 796 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 797 /* 3 - 720x480@60Hz 16:9 */ 798 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 799 798, 858, 0, 480, 489, 495, 525, 0, 800 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 801 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 802 /* 4 - 1280x720@60Hz 16:9 */ 803 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 804 1430, 1650, 0, 720, 725, 730, 750, 0, 805 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 806 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 807 /* 5 - 1920x1080i@60Hz 16:9 */ 808 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 809 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 810 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 811 DRM_MODE_FLAG_INTERLACE), 812 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 813 /* 6 - 720(1440)x480i@60Hz 4:3 */ 814 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 815 801, 858, 0, 480, 488, 494, 525, 0, 816 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 817 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 818 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 819 /* 7 - 720(1440)x480i@60Hz 16:9 */ 820 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 821 801, 858, 0, 480, 488, 494, 525, 0, 822 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 823 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 824 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 825 /* 8 - 720(1440)x240@60Hz 4:3 */ 826 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 827 801, 858, 0, 240, 244, 247, 262, 0, 828 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 829 DRM_MODE_FLAG_DBLCLK), 830 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 831 /* 9 - 720(1440)x240@60Hz 16:9 */ 832 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 833 801, 858, 0, 240, 244, 247, 262, 0, 834 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 835 DRM_MODE_FLAG_DBLCLK), 836 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 837 /* 10 - 2880x480i@60Hz 4:3 */ 838 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 839 3204, 3432, 0, 480, 488, 494, 525, 0, 840 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 841 DRM_MODE_FLAG_INTERLACE), 842 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 843 /* 11 - 2880x480i@60Hz 16:9 */ 844 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 845 3204, 3432, 0, 480, 488, 494, 525, 0, 846 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 847 DRM_MODE_FLAG_INTERLACE), 848 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 849 /* 12 - 2880x240@60Hz 4:3 */ 850 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 851 3204, 3432, 0, 240, 244, 247, 262, 0, 852 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 853 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 854 /* 13 - 2880x240@60Hz 16:9 */ 855 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 856 3204, 3432, 0, 240, 244, 247, 262, 0, 857 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 858 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 859 /* 14 - 1440x480@60Hz 4:3 */ 860 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 861 1596, 1716, 0, 480, 489, 495, 525, 0, 862 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 863 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 864 /* 15 - 1440x480@60Hz 16:9 */ 865 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 866 1596, 1716, 0, 480, 489, 495, 525, 0, 867 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 868 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 869 /* 16 - 1920x1080@60Hz 16:9 */ 870 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 871 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 872 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 873 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 874 /* 17 - 720x576@50Hz 4:3 */ 875 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 876 796, 864, 0, 576, 581, 586, 625, 0, 877 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 878 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 879 /* 18 - 720x576@50Hz 16:9 */ 880 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 881 796, 864, 0, 576, 581, 586, 625, 0, 882 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 883 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 884 /* 19 - 1280x720@50Hz 16:9 */ 885 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 886 1760, 1980, 0, 720, 725, 730, 750, 0, 887 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 888 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 889 /* 20 - 1920x1080i@50Hz 16:9 */ 890 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 891 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 892 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 893 DRM_MODE_FLAG_INTERLACE), 894 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 895 /* 21 - 720(1440)x576i@50Hz 4:3 */ 896 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 897 795, 864, 0, 576, 580, 586, 625, 0, 898 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 899 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 900 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 901 /* 22 - 720(1440)x576i@50Hz 16:9 */ 902 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 903 795, 864, 0, 576, 580, 586, 625, 0, 904 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 905 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 906 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 907 /* 23 - 720(1440)x288@50Hz 4:3 */ 908 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 909 795, 864, 0, 288, 290, 293, 312, 0, 910 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 911 DRM_MODE_FLAG_DBLCLK), 912 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 913 /* 24 - 720(1440)x288@50Hz 16:9 */ 914 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 915 795, 864, 0, 288, 290, 293, 312, 0, 916 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 917 DRM_MODE_FLAG_DBLCLK), 918 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 919 /* 25 - 2880x576i@50Hz 4:3 */ 920 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 921 3180, 3456, 0, 576, 580, 586, 625, 0, 922 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 923 DRM_MODE_FLAG_INTERLACE), 924 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 925 /* 26 - 2880x576i@50Hz 16:9 */ 926 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 927 3180, 3456, 0, 576, 580, 586, 625, 0, 928 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 929 DRM_MODE_FLAG_INTERLACE), 930 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 931 /* 27 - 2880x288@50Hz 4:3 */ 932 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 933 3180, 3456, 0, 288, 290, 293, 312, 0, 934 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 935 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 936 /* 28 - 2880x288@50Hz 16:9 */ 937 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 938 3180, 3456, 0, 288, 290, 293, 312, 0, 939 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 940 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 941 /* 29 - 1440x576@50Hz 4:3 */ 942 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 943 1592, 1728, 0, 576, 581, 586, 625, 0, 944 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 945 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 946 /* 30 - 1440x576@50Hz 16:9 */ 947 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 948 1592, 1728, 0, 576, 581, 586, 625, 0, 949 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 950 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 951 /* 31 - 1920x1080@50Hz 16:9 */ 952 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 953 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 954 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 955 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 956 /* 32 - 1920x1080@24Hz 16:9 */ 957 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 958 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 959 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 960 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 961 /* 33 - 1920x1080@25Hz 16:9 */ 962 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 963 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 964 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 965 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 966 /* 34 - 1920x1080@30Hz 16:9 */ 967 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 968 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 969 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 970 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 971 /* 35 - 2880x480@60Hz 4:3 */ 972 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 973 3192, 3432, 0, 480, 489, 495, 525, 0, 974 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 975 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 976 /* 36 - 2880x480@60Hz 16:9 */ 977 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 978 3192, 3432, 0, 480, 489, 495, 525, 0, 979 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 980 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 981 /* 37 - 2880x576@50Hz 4:3 */ 982 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 983 3184, 3456, 0, 576, 581, 586, 625, 0, 984 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 985 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 986 /* 38 - 2880x576@50Hz 16:9 */ 987 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 988 3184, 3456, 0, 576, 581, 586, 625, 0, 989 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 990 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 991 /* 39 - 1920x1080i@50Hz 16:9 */ 992 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 993 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 994 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 995 DRM_MODE_FLAG_INTERLACE), 996 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 997 /* 40 - 1920x1080i@100Hz 16:9 */ 998 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 999 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 1000 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 1001 DRM_MODE_FLAG_INTERLACE), 1002 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1003 /* 41 - 1280x720@100Hz 16:9 */ 1004 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1005 1760, 1980, 0, 720, 725, 730, 750, 0, 1006 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1007 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1008 /* 42 - 720x576@100Hz 4:3 */ 1009 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1010 796, 864, 0, 576, 581, 586, 625, 0, 1011 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1012 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1013 /* 43 - 720x576@100Hz 16:9 */ 1014 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1015 796, 864, 0, 576, 581, 586, 625, 0, 1016 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1017 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1018 /* 44 - 720(1440)x576i@100Hz 4:3 */ 1019 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 1020 795, 864, 0, 576, 580, 586, 625, 0, 1021 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1022 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1023 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1024 /* 45 - 720(1440)x576i@100Hz 16:9 */ 1025 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 1026 795, 864, 0, 576, 580, 586, 625, 0, 1027 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1028 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1029 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1030 /* 46 - 1920x1080i@120Hz 16:9 */ 1031 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1032 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 1033 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 1034 DRM_MODE_FLAG_INTERLACE), 1035 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1036 /* 47 - 1280x720@120Hz 16:9 */ 1037 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1038 1430, 1650, 0, 720, 725, 730, 750, 0, 1039 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1040 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1041 /* 48 - 720x480@120Hz 4:3 */ 1042 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 1043 798, 858, 0, 480, 489, 495, 525, 0, 1044 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1045 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1046 /* 49 - 720x480@120Hz 16:9 */ 1047 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 1048 798, 858, 0, 480, 489, 495, 525, 0, 1049 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1050 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1051 /* 50 - 720(1440)x480i@120Hz 4:3 */ 1052 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 1053 801, 858, 0, 480, 488, 494, 525, 0, 1054 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1055 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1056 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1057 /* 51 - 720(1440)x480i@120Hz 16:9 */ 1058 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 1059 801, 858, 0, 480, 488, 494, 525, 0, 1060 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1061 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1062 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1063 /* 52 - 720x576@200Hz 4:3 */ 1064 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1065 796, 864, 0, 576, 581, 586, 625, 0, 1066 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1067 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1068 /* 53 - 720x576@200Hz 16:9 */ 1069 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1070 796, 864, 0, 576, 581, 586, 625, 0, 1071 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1072 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1073 /* 54 - 720(1440)x576i@200Hz 4:3 */ 1074 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1075 795, 864, 0, 576, 580, 586, 625, 0, 1076 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1077 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1078 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1079 /* 55 - 720(1440)x576i@200Hz 16:9 */ 1080 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1081 795, 864, 0, 576, 580, 586, 625, 0, 1082 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1083 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1084 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1085 /* 56 - 720x480@240Hz 4:3 */ 1086 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1087 798, 858, 0, 480, 489, 495, 525, 0, 1088 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1089 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1090 /* 57 - 720x480@240Hz 16:9 */ 1091 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1092 798, 858, 0, 480, 489, 495, 525, 0, 1093 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1094 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1095 /* 58 - 720(1440)x480i@240Hz 4:3 */ 1096 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1097 801, 858, 0, 480, 488, 494, 525, 0, 1098 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1099 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1100 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1101 /* 59 - 720(1440)x480i@240Hz 16:9 */ 1102 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1103 801, 858, 0, 480, 488, 494, 525, 0, 1104 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1105 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1106 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1107 /* 60 - 1280x720@24Hz 16:9 */ 1108 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1109 3080, 3300, 0, 720, 725, 730, 750, 0, 1110 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1111 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1112 /* 61 - 1280x720@25Hz 16:9 */ 1113 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1114 3740, 3960, 0, 720, 725, 730, 750, 0, 1115 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1116 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1117 /* 62 - 1280x720@30Hz 16:9 */ 1118 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1119 3080, 3300, 0, 720, 725, 730, 750, 0, 1120 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1121 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1122 /* 63 - 1920x1080@120Hz 16:9 */ 1123 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1124 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1125 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1126 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1127 /* 64 - 1920x1080@100Hz 16:9 */ 1128 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1129 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1130 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1131 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1132 /* 65 - 1280x720@24Hz 64:27 */ 1133 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1134 3080, 3300, 0, 720, 725, 730, 750, 0, 1135 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1136 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1137 /* 66 - 1280x720@25Hz 64:27 */ 1138 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1139 3740, 3960, 0, 720, 725, 730, 750, 0, 1140 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1141 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1142 /* 67 - 1280x720@30Hz 64:27 */ 1143 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1144 3080, 3300, 0, 720, 725, 730, 750, 0, 1145 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1146 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1147 /* 68 - 1280x720@50Hz 64:27 */ 1148 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1149 1760, 1980, 0, 720, 725, 730, 750, 0, 1150 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1151 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1152 /* 69 - 1280x720@60Hz 64:27 */ 1153 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1154 1430, 1650, 0, 720, 725, 730, 750, 0, 1155 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1156 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1157 /* 70 - 1280x720@100Hz 64:27 */ 1158 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1159 1760, 1980, 0, 720, 725, 730, 750, 0, 1160 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1161 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1162 /* 71 - 1280x720@120Hz 64:27 */ 1163 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1164 1430, 1650, 0, 720, 725, 730, 750, 0, 1165 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1166 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1167 /* 72 - 1920x1080@24Hz 64:27 */ 1168 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1169 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1170 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1171 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1172 /* 73 - 1920x1080@25Hz 64:27 */ 1173 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1174 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1175 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1176 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1177 /* 74 - 1920x1080@30Hz 64:27 */ 1178 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1179 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1180 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1181 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1182 /* 75 - 1920x1080@50Hz 64:27 */ 1183 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1184 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1185 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1186 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1187 /* 76 - 1920x1080@60Hz 64:27 */ 1188 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1189 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1190 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1191 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1192 /* 77 - 1920x1080@100Hz 64:27 */ 1193 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1194 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1195 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1196 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1197 /* 78 - 1920x1080@120Hz 64:27 */ 1198 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1199 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1200 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1201 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1202 /* 79 - 1680x720@24Hz 64:27 */ 1203 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 1204 3080, 3300, 0, 720, 725, 730, 750, 0, 1205 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1206 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1207 /* 80 - 1680x720@25Hz 64:27 */ 1208 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 1209 2948, 3168, 0, 720, 725, 730, 750, 0, 1210 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1211 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1212 /* 81 - 1680x720@30Hz 64:27 */ 1213 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 1214 2420, 2640, 0, 720, 725, 730, 750, 0, 1215 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1216 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1217 /* 82 - 1680x720@50Hz 64:27 */ 1218 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1219 1980, 2200, 0, 720, 725, 730, 750, 0, 1220 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1221 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1222 /* 83 - 1680x720@60Hz 64:27 */ 1223 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1224 1980, 2200, 0, 720, 725, 730, 750, 0, 1225 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1226 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1227 /* 84 - 1680x720@100Hz 64:27 */ 1228 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1229 1780, 2000, 0, 720, 725, 730, 825, 0, 1230 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1231 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1232 /* 85 - 1680x720@120Hz 64:27 */ 1233 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1234 1780, 2000, 0, 720, 725, 730, 825, 0, 1235 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1236 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1237 /* 86 - 2560x1080@24Hz 64:27 */ 1238 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 1239 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1240 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1241 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1242 /* 87 - 2560x1080@25Hz 64:27 */ 1243 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 1244 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, 1245 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1246 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1247 /* 88 - 2560x1080@30Hz 64:27 */ 1248 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 1249 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, 1250 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1251 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1252 /* 89 - 2560x1080@50Hz 64:27 */ 1253 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 1254 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, 1255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1256 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1257 /* 90 - 2560x1080@60Hz 64:27 */ 1258 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 1259 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, 1260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1261 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1262 /* 91 - 2560x1080@100Hz 64:27 */ 1263 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 1264 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, 1265 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1266 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1267 /* 92 - 2560x1080@120Hz 64:27 */ 1268 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 1269 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, 1270 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1271 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1272 /* 93 - 3840x2160@24Hz 16:9 */ 1273 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1274 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1276 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1277 /* 94 - 3840x2160@25Hz 16:9 */ 1278 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1279 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1281 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1282 /* 95 - 3840x2160@30Hz 16:9 */ 1283 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1284 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1285 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1286 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1287 /* 96 - 3840x2160@50Hz 16:9 */ 1288 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1289 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1291 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1292 /* 97 - 3840x2160@60Hz 16:9 */ 1293 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1294 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1296 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1297 /* 98 - 4096x2160@24Hz 256:135 */ 1298 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1299 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1301 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1302 /* 99 - 4096x2160@25Hz 256:135 */ 1303 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1304 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1306 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1307 /* 100 - 4096x2160@30Hz 256:135 */ 1308 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1309 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1310 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1311 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1312 /* 101 - 4096x2160@50Hz 256:135 */ 1313 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1314 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1315 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1316 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1317 /* 102 - 4096x2160@60Hz 256:135 */ 1318 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1319 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1321 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1322 /* 103 - 3840x2160@24Hz 64:27 */ 1323 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1324 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1326 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1327 /* 104 - 3840x2160@25Hz 64:27 */ 1328 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1329 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1330 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1331 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1332 /* 105 - 3840x2160@30Hz 64:27 */ 1333 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1334 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1335 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1336 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1337 /* 106 - 3840x2160@50Hz 64:27 */ 1338 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1339 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1340 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1341 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1342 /* 107 - 3840x2160@60Hz 64:27 */ 1343 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1344 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1345 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1346 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1347 /* 108 - 1280x720@48Hz 16:9 */ 1348 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1349 2280, 2500, 0, 720, 725, 730, 750, 0, 1350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1351 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1352 /* 109 - 1280x720@48Hz 64:27 */ 1353 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1354 2280, 2500, 0, 720, 725, 730, 750, 0, 1355 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1356 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1357 /* 110 - 1680x720@48Hz 64:27 */ 1358 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490, 1359 2530, 2750, 0, 720, 725, 730, 750, 0, 1360 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1361 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1362 /* 111 - 1920x1080@48Hz 16:9 */ 1363 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1364 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1366 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1367 /* 112 - 1920x1080@48Hz 64:27 */ 1368 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1369 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1371 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1372 /* 113 - 2560x1080@48Hz 64:27 */ 1373 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558, 1374 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1375 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1376 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1377 /* 114 - 3840x2160@48Hz 16:9 */ 1378 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1379 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1381 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1382 /* 115 - 4096x2160@48Hz 256:135 */ 1383 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116, 1384 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1386 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1387 /* 116 - 3840x2160@48Hz 64:27 */ 1388 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1389 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1391 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1392 /* 117 - 3840x2160@100Hz 16:9 */ 1393 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1394 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1395 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1396 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1397 /* 118 - 3840x2160@120Hz 16:9 */ 1398 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1399 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1401 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1402 /* 119 - 3840x2160@100Hz 64:27 */ 1403 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1404 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1406 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1407 /* 120 - 3840x2160@120Hz 64:27 */ 1408 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1409 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1410 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1411 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1412 /* 121 - 5120x2160@24Hz 64:27 */ 1413 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116, 1414 7204, 7500, 0, 2160, 2168, 2178, 2200, 0, 1415 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1416 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1417 /* 122 - 5120x2160@25Hz 64:27 */ 1418 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816, 1419 6904, 7200, 0, 2160, 2168, 2178, 2200, 0, 1420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1421 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1422 /* 123 - 5120x2160@30Hz 64:27 */ 1423 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784, 1424 5872, 6000, 0, 2160, 2168, 2178, 2200, 0, 1425 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1426 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1427 /* 124 - 5120x2160@48Hz 64:27 */ 1428 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866, 1429 5954, 6250, 0, 2160, 2168, 2178, 2475, 0, 1430 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1431 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1432 /* 125 - 5120x2160@50Hz 64:27 */ 1433 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216, 1434 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1435 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1436 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1437 /* 126 - 5120x2160@60Hz 64:27 */ 1438 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284, 1439 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1440 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1441 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1442 /* 127 - 5120x2160@100Hz 64:27 */ 1443 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216, 1444 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1446 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1447 }; 1448 1449 /* 1450 * From CEA/CTA-861 spec. 1451 * 1452 * Do not access directly, instead always use cea_mode_for_vic(). 1453 */ 1454 static const struct drm_display_mode edid_cea_modes_193[] = { 1455 /* 193 - 5120x2160@120Hz 64:27 */ 1456 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284, 1457 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1458 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1459 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1460 /* 194 - 7680x4320@24Hz 16:9 */ 1461 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1462 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1463 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1464 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1465 /* 195 - 7680x4320@25Hz 16:9 */ 1466 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1467 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1469 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1470 /* 196 - 7680x4320@30Hz 16:9 */ 1471 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1472 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1474 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1475 /* 197 - 7680x4320@48Hz 16:9 */ 1476 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1477 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1479 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1480 /* 198 - 7680x4320@50Hz 16:9 */ 1481 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1482 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1483 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1484 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1485 /* 199 - 7680x4320@60Hz 16:9 */ 1486 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1487 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1488 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1489 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1490 /* 200 - 7680x4320@100Hz 16:9 */ 1491 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1492 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1494 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1495 /* 201 - 7680x4320@120Hz 16:9 */ 1496 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1497 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1498 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1499 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1500 /* 202 - 7680x4320@24Hz 64:27 */ 1501 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1502 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1503 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1504 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1505 /* 203 - 7680x4320@25Hz 64:27 */ 1506 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1507 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1508 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1509 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1510 /* 204 - 7680x4320@30Hz 64:27 */ 1511 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1512 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1513 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1514 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1515 /* 205 - 7680x4320@48Hz 64:27 */ 1516 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1517 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1518 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1519 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1520 /* 206 - 7680x4320@50Hz 64:27 */ 1521 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1522 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1523 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1524 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1525 /* 207 - 7680x4320@60Hz 64:27 */ 1526 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1527 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1528 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1529 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1530 /* 208 - 7680x4320@100Hz 64:27 */ 1531 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1532 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1533 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1534 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1535 /* 209 - 7680x4320@120Hz 64:27 */ 1536 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1537 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1538 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1539 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1540 /* 210 - 10240x4320@24Hz 64:27 */ 1541 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732, 1542 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1543 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1544 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1545 /* 211 - 10240x4320@25Hz 64:27 */ 1546 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732, 1547 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1548 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1549 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1550 /* 212 - 10240x4320@30Hz 64:27 */ 1551 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528, 1552 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1554 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1555 /* 213 - 10240x4320@48Hz 64:27 */ 1556 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732, 1557 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1558 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1559 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1560 /* 214 - 10240x4320@50Hz 64:27 */ 1561 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732, 1562 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1563 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1564 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1565 /* 215 - 10240x4320@60Hz 64:27 */ 1566 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528, 1567 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1568 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1569 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1570 /* 216 - 10240x4320@100Hz 64:27 */ 1571 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432, 1572 12608, 13200, 0, 4320, 4336, 4356, 4500, 0, 1573 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1574 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1575 /* 217 - 10240x4320@120Hz 64:27 */ 1576 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528, 1577 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1578 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1579 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1580 /* 218 - 4096x2160@100Hz 256:135 */ 1581 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896, 1582 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1583 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1584 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1585 /* 219 - 4096x2160@120Hz 256:135 */ 1586 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184, 1587 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1588 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1589 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1590 }; 1591 1592 /* 1593 * HDMI 1.4 4k modes. Index using the VIC. 1594 */ 1595 static const struct drm_display_mode edid_4k_modes[] = { 1596 /* 0 - dummy, VICs start at 1 */ 1597 { }, 1598 /* 1 - 3840x2160@30Hz */ 1599 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1600 3840, 4016, 4104, 4400, 0, 1601 2160, 2168, 2178, 2250, 0, 1602 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1603 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1604 /* 2 - 3840x2160@25Hz */ 1605 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1606 3840, 4896, 4984, 5280, 0, 1607 2160, 2168, 2178, 2250, 0, 1608 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1609 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1610 /* 3 - 3840x2160@24Hz */ 1611 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1612 3840, 5116, 5204, 5500, 0, 1613 2160, 2168, 2178, 2250, 0, 1614 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1615 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1616 /* 4 - 4096x2160@24Hz (SMPTE) */ 1617 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1618 4096, 5116, 5204, 5500, 0, 1619 2160, 2168, 2178, 2250, 0, 1620 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1621 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1622 }; 1623 1624 /*** DDC fetch and block validation ***/ 1625 1626 /* 1627 * The opaque EDID type, internal to drm_edid.c. 1628 */ 1629 struct drm_edid { 1630 /* Size allocated for edid */ 1631 size_t size; 1632 const struct edid *edid; 1633 }; 1634 1635 static int edid_hfeeodb_extension_block_count(const struct edid *edid); 1636 1637 static int edid_hfeeodb_block_count(const struct edid *edid) 1638 { 1639 int eeodb = edid_hfeeodb_extension_block_count(edid); 1640 1641 return eeodb ? eeodb + 1 : 0; 1642 } 1643 1644 static int edid_extension_block_count(const struct edid *edid) 1645 { 1646 return edid->extensions; 1647 } 1648 1649 static int edid_block_count(const struct edid *edid) 1650 { 1651 return edid_extension_block_count(edid) + 1; 1652 } 1653 1654 static int edid_size_by_blocks(int num_blocks) 1655 { 1656 return num_blocks * EDID_LENGTH; 1657 } 1658 1659 static int edid_size(const struct edid *edid) 1660 { 1661 return edid_size_by_blocks(edid_block_count(edid)); 1662 } 1663 1664 static const void *edid_block_data(const struct edid *edid, int index) 1665 { 1666 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH); 1667 1668 return edid + index; 1669 } 1670 1671 static const void *edid_extension_block_data(const struct edid *edid, int index) 1672 { 1673 return edid_block_data(edid, index + 1); 1674 } 1675 1676 /* EDID block count indicated in EDID, may exceed allocated size */ 1677 static int __drm_edid_block_count(const struct drm_edid *drm_edid) 1678 { 1679 int num_blocks; 1680 1681 /* Starting point */ 1682 num_blocks = edid_block_count(drm_edid->edid); 1683 1684 /* HF-EEODB override */ 1685 if (drm_edid->size >= edid_size_by_blocks(2)) { 1686 int eeodb; 1687 1688 /* 1689 * Note: HF-EEODB may specify a smaller extension count than the 1690 * regular one. Unlike in buffer allocation, here we can use it. 1691 */ 1692 eeodb = edid_hfeeodb_block_count(drm_edid->edid); 1693 if (eeodb) 1694 num_blocks = eeodb; 1695 } 1696 1697 return num_blocks; 1698 } 1699 1700 /* EDID block count, limited by allocated size */ 1701 static int drm_edid_block_count(const struct drm_edid *drm_edid) 1702 { 1703 /* Limit by allocated size */ 1704 return min(__drm_edid_block_count(drm_edid), 1705 (int)drm_edid->size / EDID_LENGTH); 1706 } 1707 1708 /* EDID extension block count, limited by allocated size */ 1709 static int drm_edid_extension_block_count(const struct drm_edid *drm_edid) 1710 { 1711 return drm_edid_block_count(drm_edid) - 1; 1712 } 1713 1714 static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index) 1715 { 1716 return edid_block_data(drm_edid->edid, index); 1717 } 1718 1719 static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid, 1720 int index) 1721 { 1722 return edid_extension_block_data(drm_edid->edid, index); 1723 } 1724 1725 /* 1726 * Initializer helper for legacy interfaces, where we have no choice but to 1727 * trust edid size. Not for general purpose use. 1728 */ 1729 static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid, 1730 const struct edid *edid) 1731 { 1732 if (!edid) 1733 return NULL; 1734 1735 memset(drm_edid, 0, sizeof(*drm_edid)); 1736 1737 drm_edid->edid = edid; 1738 drm_edid->size = edid_size(edid); 1739 1740 return drm_edid; 1741 } 1742 1743 /* 1744 * EDID base and extension block iterator. 1745 * 1746 * struct drm_edid_iter iter; 1747 * const u8 *block; 1748 * 1749 * drm_edid_iter_begin(drm_edid, &iter); 1750 * drm_edid_iter_for_each(block, &iter) { 1751 * // do stuff with block 1752 * } 1753 * drm_edid_iter_end(&iter); 1754 */ 1755 struct drm_edid_iter { 1756 const struct drm_edid *drm_edid; 1757 1758 /* Current block index. */ 1759 int index; 1760 }; 1761 1762 static void drm_edid_iter_begin(const struct drm_edid *drm_edid, 1763 struct drm_edid_iter *iter) 1764 { 1765 memset(iter, 0, sizeof(*iter)); 1766 1767 iter->drm_edid = drm_edid; 1768 } 1769 1770 static const void *__drm_edid_iter_next(struct drm_edid_iter *iter) 1771 { 1772 const void *block = NULL; 1773 1774 if (!iter->drm_edid) 1775 return NULL; 1776 1777 if (iter->index < drm_edid_block_count(iter->drm_edid)) 1778 block = drm_edid_block_data(iter->drm_edid, iter->index++); 1779 1780 return block; 1781 } 1782 1783 #define drm_edid_iter_for_each(__block, __iter) \ 1784 while (((__block) = __drm_edid_iter_next(__iter))) 1785 1786 static void drm_edid_iter_end(struct drm_edid_iter *iter) 1787 { 1788 memset(iter, 0, sizeof(*iter)); 1789 } 1790 1791 static const u8 edid_header[] = { 1792 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1793 }; 1794 1795 static void edid_header_fix(void *edid) 1796 { 1797 memcpy(edid, edid_header, sizeof(edid_header)); 1798 } 1799 1800 /** 1801 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1802 * @_edid: pointer to raw base EDID block 1803 * 1804 * Sanity check the header of the base EDID block. 1805 * 1806 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1807 */ 1808 int drm_edid_header_is_valid(const void *_edid) 1809 { 1810 const struct edid *edid = _edid; 1811 int i, score = 0; 1812 1813 for (i = 0; i < sizeof(edid_header); i++) { 1814 if (edid->header[i] == edid_header[i]) 1815 score++; 1816 } 1817 1818 return score; 1819 } 1820 EXPORT_SYMBOL(drm_edid_header_is_valid); 1821 1822 static int edid_fixup __read_mostly = 6; 1823 module_param_named(edid_fixup, edid_fixup, int, 0400); 1824 MODULE_PARM_DESC(edid_fixup, 1825 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1826 1827 static int edid_block_compute_checksum(const void *_block) 1828 { 1829 const u8 *block = _block; 1830 int i; 1831 u8 csum = 0, crc = 0; 1832 1833 for (i = 0; i < EDID_LENGTH - 1; i++) 1834 csum += block[i]; 1835 1836 crc = 0x100 - csum; 1837 1838 return crc; 1839 } 1840 1841 static int edid_block_get_checksum(const void *_block) 1842 { 1843 const struct edid *block = _block; 1844 1845 return block->checksum; 1846 } 1847 1848 static int edid_block_tag(const void *_block) 1849 { 1850 const u8 *block = _block; 1851 1852 return block[0]; 1853 } 1854 1855 static bool edid_block_is_zero(const void *edid) 1856 { 1857 return mem_is_zero(edid, EDID_LENGTH); 1858 } 1859 1860 static bool drm_edid_eq(const struct drm_edid *drm_edid, 1861 const void *raw_edid, size_t raw_edid_size) 1862 { 1863 bool edid1_present = drm_edid && drm_edid->edid && drm_edid->size; 1864 bool edid2_present = raw_edid && raw_edid_size; 1865 1866 if (edid1_present != edid2_present) 1867 return false; 1868 1869 if (edid1_present) { 1870 if (drm_edid->size != raw_edid_size) 1871 return false; 1872 1873 if (memcmp(drm_edid->edid, raw_edid, drm_edid->size)) 1874 return false; 1875 } 1876 1877 return true; 1878 } 1879 1880 enum edid_block_status { 1881 EDID_BLOCK_OK = 0, 1882 EDID_BLOCK_READ_FAIL, 1883 EDID_BLOCK_NULL, 1884 EDID_BLOCK_ZERO, 1885 EDID_BLOCK_HEADER_CORRUPT, 1886 EDID_BLOCK_HEADER_REPAIR, 1887 EDID_BLOCK_HEADER_FIXED, 1888 EDID_BLOCK_CHECKSUM, 1889 EDID_BLOCK_VERSION, 1890 }; 1891 1892 static enum edid_block_status edid_block_check(const void *_block, 1893 bool is_base_block) 1894 { 1895 const struct edid *block = _block; 1896 1897 if (!block) 1898 return EDID_BLOCK_NULL; 1899 1900 if (is_base_block) { 1901 int score = drm_edid_header_is_valid(block); 1902 1903 if (score < clamp(edid_fixup, 0, 8)) { 1904 if (edid_block_is_zero(block)) 1905 return EDID_BLOCK_ZERO; 1906 else 1907 return EDID_BLOCK_HEADER_CORRUPT; 1908 } 1909 1910 if (score < 8) 1911 return EDID_BLOCK_HEADER_REPAIR; 1912 } 1913 1914 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) { 1915 if (edid_block_is_zero(block)) 1916 return EDID_BLOCK_ZERO; 1917 else 1918 return EDID_BLOCK_CHECKSUM; 1919 } 1920 1921 if (is_base_block) { 1922 if (block->version != 1) 1923 return EDID_BLOCK_VERSION; 1924 } 1925 1926 return EDID_BLOCK_OK; 1927 } 1928 1929 static bool edid_block_status_valid(enum edid_block_status status, int tag) 1930 { 1931 return status == EDID_BLOCK_OK || 1932 status == EDID_BLOCK_HEADER_FIXED || 1933 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT); 1934 } 1935 1936 static bool edid_block_valid(const void *block, bool base) 1937 { 1938 return edid_block_status_valid(edid_block_check(block, base), 1939 edid_block_tag(block)); 1940 } 1941 1942 static void edid_block_status_print(enum edid_block_status status, 1943 const struct edid *block, 1944 int block_num) 1945 { 1946 switch (status) { 1947 case EDID_BLOCK_OK: 1948 break; 1949 case EDID_BLOCK_READ_FAIL: 1950 pr_debug("EDID block %d read failed\n", block_num); 1951 break; 1952 case EDID_BLOCK_NULL: 1953 pr_debug("EDID block %d pointer is NULL\n", block_num); 1954 break; 1955 case EDID_BLOCK_ZERO: 1956 pr_notice("EDID block %d is all zeroes\n", block_num); 1957 break; 1958 case EDID_BLOCK_HEADER_CORRUPT: 1959 pr_notice("EDID has corrupt header\n"); 1960 break; 1961 case EDID_BLOCK_HEADER_REPAIR: 1962 pr_debug("EDID corrupt header needs repair\n"); 1963 break; 1964 case EDID_BLOCK_HEADER_FIXED: 1965 pr_debug("EDID corrupt header fixed\n"); 1966 break; 1967 case EDID_BLOCK_CHECKSUM: 1968 if (edid_block_status_valid(status, edid_block_tag(block))) { 1969 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n", 1970 block_num, edid_block_tag(block), 1971 edid_block_compute_checksum(block)); 1972 } else { 1973 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n", 1974 block_num, edid_block_tag(block), 1975 edid_block_compute_checksum(block)); 1976 } 1977 break; 1978 case EDID_BLOCK_VERSION: 1979 pr_notice("EDID has major version %d, instead of 1\n", 1980 block->version); 1981 break; 1982 default: 1983 WARN(1, "EDID block %d unknown edid block status code %d\n", 1984 block_num, status); 1985 break; 1986 } 1987 } 1988 1989 static void edid_block_dump(const char *level, const void *block, int block_num) 1990 { 1991 enum edid_block_status status; 1992 char prefix[20]; 1993 1994 status = edid_block_check(block, block_num == 0); 1995 if (status == EDID_BLOCK_ZERO) 1996 sprintf(prefix, "\t[%02x] ZERO ", block_num); 1997 else if (!edid_block_status_valid(status, edid_block_tag(block))) 1998 sprintf(prefix, "\t[%02x] BAD ", block_num); 1999 else 2000 sprintf(prefix, "\t[%02x] GOOD ", block_num); 2001 2002 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1, 2003 block, EDID_LENGTH, false); 2004 } 2005 2006 /* 2007 * Validate a base or extension EDID block and optionally dump bad blocks to 2008 * the console. 2009 */ 2010 static bool drm_edid_block_valid(void *_block, int block_num, bool print_bad_edid, 2011 bool *edid_corrupt) 2012 { 2013 struct edid *block = _block; 2014 enum edid_block_status status; 2015 bool is_base_block = block_num == 0; 2016 bool valid; 2017 2018 if (WARN_ON(!block)) 2019 return false; 2020 2021 status = edid_block_check(block, is_base_block); 2022 if (status == EDID_BLOCK_HEADER_REPAIR) { 2023 DRM_DEBUG_KMS("Fixing EDID header, your hardware may be failing\n"); 2024 edid_header_fix(block); 2025 2026 /* Retry with fixed header, update status if that worked. */ 2027 status = edid_block_check(block, is_base_block); 2028 if (status == EDID_BLOCK_OK) 2029 status = EDID_BLOCK_HEADER_FIXED; 2030 } 2031 2032 if (edid_corrupt) { 2033 /* 2034 * Unknown major version isn't corrupt but we can't use it. Only 2035 * the base block can reset edid_corrupt to false. 2036 */ 2037 if (is_base_block && 2038 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)) 2039 *edid_corrupt = false; 2040 else if (status != EDID_BLOCK_OK) 2041 *edid_corrupt = true; 2042 } 2043 2044 edid_block_status_print(status, block, block_num); 2045 2046 /* Determine whether we can use this block with this status. */ 2047 valid = edid_block_status_valid(status, edid_block_tag(block)); 2048 2049 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) { 2050 pr_notice("Raw EDID:\n"); 2051 edid_block_dump(KERN_NOTICE, block, block_num); 2052 } 2053 2054 return valid; 2055 } 2056 2057 /** 2058 * drm_edid_is_valid - sanity check EDID data 2059 * @edid: EDID data 2060 * 2061 * Sanity-check an entire EDID record (including extensions) 2062 * 2063 * Return: True if the EDID data is valid, false otherwise. 2064 */ 2065 bool drm_edid_is_valid(struct edid *edid) 2066 { 2067 int i; 2068 2069 if (!edid) 2070 return false; 2071 2072 for (i = 0; i < edid_block_count(edid); i++) { 2073 void *block = (void *)edid_block_data(edid, i); 2074 2075 if (!drm_edid_block_valid(block, i, true, NULL)) 2076 return false; 2077 } 2078 2079 return true; 2080 } 2081 EXPORT_SYMBOL(drm_edid_is_valid); 2082 2083 /** 2084 * drm_edid_valid - sanity check EDID data 2085 * @drm_edid: EDID data 2086 * 2087 * Sanity check an EDID. Cross check block count against allocated size and 2088 * checksum the blocks. 2089 * 2090 * Return: True if the EDID data is valid, false otherwise. 2091 */ 2092 bool drm_edid_valid(const struct drm_edid *drm_edid) 2093 { 2094 int i; 2095 2096 if (!drm_edid) 2097 return false; 2098 2099 if (edid_size_by_blocks(__drm_edid_block_count(drm_edid)) != drm_edid->size) 2100 return false; 2101 2102 for (i = 0; i < drm_edid_block_count(drm_edid); i++) { 2103 const void *block = drm_edid_block_data(drm_edid, i); 2104 2105 if (!edid_block_valid(block, i == 0)) 2106 return false; 2107 } 2108 2109 return true; 2110 } 2111 EXPORT_SYMBOL(drm_edid_valid); 2112 2113 static struct edid *edid_filter_invalid_blocks(struct edid *edid, 2114 size_t *alloc_size) 2115 { 2116 struct edid *new; 2117 int i, valid_blocks = 0; 2118 2119 /* 2120 * Note: If the EDID uses HF-EEODB, but has invalid blocks, we'll revert 2121 * back to regular extension count here. We don't want to start 2122 * modifying the HF-EEODB extension too. 2123 */ 2124 for (i = 0; i < edid_block_count(edid); i++) { 2125 const void *src_block = edid_block_data(edid, i); 2126 2127 if (edid_block_valid(src_block, i == 0)) { 2128 void *dst_block = (void *)edid_block_data(edid, valid_blocks); 2129 2130 memmove(dst_block, src_block, EDID_LENGTH); 2131 valid_blocks++; 2132 } 2133 } 2134 2135 /* We already trusted the base block to be valid here... */ 2136 if (WARN_ON(!valid_blocks)) { 2137 kfree(edid); 2138 return NULL; 2139 } 2140 2141 edid->extensions = valid_blocks - 1; 2142 edid->checksum = edid_block_compute_checksum(edid); 2143 2144 *alloc_size = edid_size_by_blocks(valid_blocks); 2145 2146 new = krealloc(edid, *alloc_size, GFP_KERNEL); 2147 if (!new) 2148 kfree(edid); 2149 2150 return new; 2151 } 2152 2153 #define DDC_SEGMENT_ADDR 0x30 2154 /** 2155 * drm_do_probe_ddc_edid() - get EDID information via I2C 2156 * @data: I2C device adapter 2157 * @buf: EDID data buffer to be filled 2158 * @block: 128 byte EDID block to start fetching from 2159 * @len: EDID data buffer length to fetch 2160 * 2161 * Try to fetch EDID information by calling I2C driver functions. 2162 * 2163 * Return: 0 on success or -1 on failure. 2164 */ 2165 static int 2166 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 2167 { 2168 struct i2c_adapter *adapter = data; 2169 unsigned char start = block * EDID_LENGTH; 2170 unsigned char segment = block >> 1; 2171 unsigned char xfers = segment ? 3 : 2; 2172 int ret, retries = 5; 2173 2174 /* 2175 * The core I2C driver will automatically retry the transfer if the 2176 * adapter reports EAGAIN. However, we find that bit-banging transfers 2177 * are susceptible to errors under a heavily loaded machine and 2178 * generate spurious NAKs and timeouts. Retrying the transfer 2179 * of the individual block a few times seems to overcome this. 2180 */ 2181 do { 2182 struct i2c_msg msgs[] = { 2183 { 2184 .addr = DDC_SEGMENT_ADDR, 2185 .flags = 0, 2186 .len = 1, 2187 .buf = &segment, 2188 }, { 2189 .addr = DDC_ADDR, 2190 .flags = 0, 2191 .len = 1, 2192 .buf = &start, 2193 }, { 2194 .addr = DDC_ADDR, 2195 .flags = I2C_M_RD, 2196 .len = len, 2197 .buf = buf, 2198 } 2199 }; 2200 2201 /* 2202 * Avoid sending the segment addr to not upset non-compliant 2203 * DDC monitors. 2204 */ 2205 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 2206 2207 if (ret == -ENXIO) { 2208 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 2209 adapter->name); 2210 break; 2211 } 2212 } while (ret != xfers && --retries); 2213 2214 return ret == xfers ? 0 : -1; 2215 } 2216 2217 static void connector_bad_edid(struct drm_connector *connector, 2218 const struct edid *edid, int num_blocks) 2219 { 2220 int i; 2221 u8 last_block; 2222 2223 /* 2224 * 0x7e in the EDID is the number of extension blocks. The EDID 2225 * is 1 (base block) + num_ext_blocks big. That means we can think 2226 * of 0x7e in the EDID of the _index_ of the last block in the 2227 * combined chunk of memory. 2228 */ 2229 last_block = edid->extensions; 2230 2231 /* Calculate real checksum for the last edid extension block data */ 2232 if (last_block < num_blocks) 2233 connector->real_edid_checksum = 2234 edid_block_compute_checksum(edid + last_block); 2235 2236 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS)) 2237 return; 2238 2239 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID is invalid:\n", 2240 connector->base.id, connector->name); 2241 for (i = 0; i < num_blocks; i++) 2242 edid_block_dump(KERN_DEBUG, edid + i, i); 2243 } 2244 2245 /* Get override or firmware EDID */ 2246 static const struct drm_edid *drm_edid_override_get(struct drm_connector *connector) 2247 { 2248 const struct drm_edid *override = NULL; 2249 2250 mutex_lock(&connector->edid_override_mutex); 2251 2252 if (connector->edid_override) 2253 override = drm_edid_dup(connector->edid_override); 2254 2255 mutex_unlock(&connector->edid_override_mutex); 2256 2257 if (!override) 2258 override = drm_edid_load_firmware(connector); 2259 2260 return IS_ERR(override) ? NULL : override; 2261 } 2262 2263 /* For debugfs edid_override implementation */ 2264 int drm_edid_override_show(struct drm_connector *connector, struct seq_file *m) 2265 { 2266 const struct drm_edid *drm_edid; 2267 2268 mutex_lock(&connector->edid_override_mutex); 2269 2270 drm_edid = connector->edid_override; 2271 if (drm_edid) 2272 seq_write(m, drm_edid->edid, drm_edid->size); 2273 2274 mutex_unlock(&connector->edid_override_mutex); 2275 2276 return 0; 2277 } 2278 2279 /* For debugfs edid_override implementation */ 2280 int drm_edid_override_set(struct drm_connector *connector, const void *edid, 2281 size_t size) 2282 { 2283 const struct drm_edid *drm_edid; 2284 2285 drm_edid = drm_edid_alloc(edid, size); 2286 if (!drm_edid_valid(drm_edid)) { 2287 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override invalid\n", 2288 connector->base.id, connector->name); 2289 drm_edid_free(drm_edid); 2290 return -EINVAL; 2291 } 2292 2293 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override set\n", 2294 connector->base.id, connector->name); 2295 2296 mutex_lock(&connector->edid_override_mutex); 2297 2298 drm_edid_free(connector->edid_override); 2299 connector->edid_override = drm_edid; 2300 2301 mutex_unlock(&connector->edid_override_mutex); 2302 2303 return 0; 2304 } 2305 2306 /* For debugfs edid_override implementation */ 2307 int drm_edid_override_reset(struct drm_connector *connector) 2308 { 2309 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override reset\n", 2310 connector->base.id, connector->name); 2311 2312 mutex_lock(&connector->edid_override_mutex); 2313 2314 drm_edid_free(connector->edid_override); 2315 connector->edid_override = NULL; 2316 2317 mutex_unlock(&connector->edid_override_mutex); 2318 2319 return 0; 2320 } 2321 2322 /** 2323 * drm_edid_override_connector_update - add modes from override/firmware EDID 2324 * @connector: connector we're probing 2325 * 2326 * Add modes from the override/firmware EDID, if available. Only to be used from 2327 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe 2328 * failed during drm_get_edid() and caused the override/firmware EDID to be 2329 * skipped. 2330 * 2331 * Return: The number of modes added or 0 if we couldn't find any. 2332 */ 2333 int drm_edid_override_connector_update(struct drm_connector *connector) 2334 { 2335 const struct drm_edid *override; 2336 int num_modes = 0; 2337 2338 override = drm_edid_override_get(connector); 2339 if (override) { 2340 if (drm_edid_connector_update(connector, override) == 0) 2341 num_modes = drm_edid_connector_add_modes(connector); 2342 2343 drm_edid_free(override); 2344 2345 drm_dbg_kms(connector->dev, 2346 "[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n", 2347 connector->base.id, connector->name, num_modes); 2348 } 2349 2350 return num_modes; 2351 } 2352 EXPORT_SYMBOL(drm_edid_override_connector_update); 2353 2354 typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len); 2355 2356 static enum edid_block_status edid_block_read(void *block, unsigned int block_num, 2357 read_block_fn read_block, 2358 void *context) 2359 { 2360 enum edid_block_status status; 2361 bool is_base_block = block_num == 0; 2362 int try; 2363 2364 for (try = 0; try < 4; try++) { 2365 if (read_block(context, block, block_num, EDID_LENGTH)) 2366 return EDID_BLOCK_READ_FAIL; 2367 2368 status = edid_block_check(block, is_base_block); 2369 if (status == EDID_BLOCK_HEADER_REPAIR) { 2370 edid_header_fix(block); 2371 2372 /* Retry with fixed header, update status if that worked. */ 2373 status = edid_block_check(block, is_base_block); 2374 if (status == EDID_BLOCK_OK) 2375 status = EDID_BLOCK_HEADER_FIXED; 2376 } 2377 2378 if (edid_block_status_valid(status, edid_block_tag(block))) 2379 break; 2380 2381 /* Fail early for unrepairable base block all zeros. */ 2382 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO) 2383 break; 2384 } 2385 2386 return status; 2387 } 2388 2389 static struct edid *_drm_do_get_edid(struct drm_connector *connector, 2390 read_block_fn read_block, void *context, 2391 size_t *size) 2392 { 2393 enum edid_block_status status; 2394 int i, num_blocks, invalid_blocks = 0; 2395 const struct drm_edid *override; 2396 struct edid *edid, *new; 2397 size_t alloc_size = EDID_LENGTH; 2398 2399 override = drm_edid_override_get(connector); 2400 if (override) { 2401 alloc_size = override->size; 2402 edid = kmemdup(override->edid, alloc_size, GFP_KERNEL); 2403 drm_edid_free(override); 2404 if (!edid) 2405 return NULL; 2406 goto ok; 2407 } 2408 2409 edid = kmalloc(alloc_size, GFP_KERNEL); 2410 if (!edid) 2411 return NULL; 2412 2413 status = edid_block_read(edid, 0, read_block, context); 2414 2415 edid_block_status_print(status, edid, 0); 2416 2417 if (status == EDID_BLOCK_READ_FAIL) 2418 goto fail; 2419 2420 /* FIXME: Clarify what a corrupt EDID actually means. */ 2421 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION) 2422 connector->edid_corrupt = false; 2423 else 2424 connector->edid_corrupt = true; 2425 2426 if (!edid_block_status_valid(status, edid_block_tag(edid))) { 2427 if (status == EDID_BLOCK_ZERO) 2428 connector->null_edid_counter++; 2429 2430 connector_bad_edid(connector, edid, 1); 2431 goto fail; 2432 } 2433 2434 if (!edid_extension_block_count(edid)) 2435 goto ok; 2436 2437 alloc_size = edid_size(edid); 2438 new = krealloc(edid, alloc_size, GFP_KERNEL); 2439 if (!new) 2440 goto fail; 2441 edid = new; 2442 2443 num_blocks = edid_block_count(edid); 2444 for (i = 1; i < num_blocks; i++) { 2445 void *block = (void *)edid_block_data(edid, i); 2446 2447 status = edid_block_read(block, i, read_block, context); 2448 2449 edid_block_status_print(status, block, i); 2450 2451 if (!edid_block_status_valid(status, edid_block_tag(block))) { 2452 if (status == EDID_BLOCK_READ_FAIL) 2453 goto fail; 2454 invalid_blocks++; 2455 } else if (i == 1) { 2456 /* 2457 * If the first EDID extension is a CTA extension, and 2458 * the first Data Block is HF-EEODB, override the 2459 * extension block count. 2460 * 2461 * Note: HF-EEODB could specify a smaller extension 2462 * count too, but we can't risk allocating a smaller 2463 * amount. 2464 */ 2465 int eeodb = edid_hfeeodb_block_count(edid); 2466 2467 if (eeodb > num_blocks) { 2468 num_blocks = eeodb; 2469 alloc_size = edid_size_by_blocks(num_blocks); 2470 new = krealloc(edid, alloc_size, GFP_KERNEL); 2471 if (!new) 2472 goto fail; 2473 edid = new; 2474 } 2475 } 2476 } 2477 2478 if (invalid_blocks) { 2479 connector_bad_edid(connector, edid, num_blocks); 2480 2481 edid = edid_filter_invalid_blocks(edid, &alloc_size); 2482 } 2483 2484 ok: 2485 if (size) 2486 *size = alloc_size; 2487 2488 return edid; 2489 2490 fail: 2491 kfree(edid); 2492 return NULL; 2493 } 2494 2495 /** 2496 * drm_edid_raw - Get a pointer to the raw EDID data. 2497 * @drm_edid: drm_edid container 2498 * 2499 * Get a pointer to the raw EDID data. 2500 * 2501 * This is for transition only. Avoid using this like the plague. 2502 * 2503 * Return: Pointer to raw EDID data. 2504 */ 2505 const struct edid *drm_edid_raw(const struct drm_edid *drm_edid) 2506 { 2507 if (!drm_edid || !drm_edid->size) 2508 return NULL; 2509 2510 /* 2511 * Do not return pointers where relying on EDID extension count would 2512 * lead to buffer overflow. 2513 */ 2514 if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size)) 2515 return NULL; 2516 2517 return drm_edid->edid; 2518 } 2519 EXPORT_SYMBOL(drm_edid_raw); 2520 2521 /* Allocate struct drm_edid container *without* duplicating the edid data */ 2522 static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size) 2523 { 2524 struct drm_edid *drm_edid; 2525 2526 if (!edid || !size || size < EDID_LENGTH) 2527 return NULL; 2528 2529 drm_edid = kzalloc_obj(*drm_edid); 2530 if (drm_edid) { 2531 drm_edid->edid = edid; 2532 drm_edid->size = size; 2533 } 2534 2535 return drm_edid; 2536 } 2537 2538 /** 2539 * drm_edid_alloc - Allocate a new drm_edid container 2540 * @edid: Pointer to raw EDID data 2541 * @size: Size of memory allocated for EDID 2542 * 2543 * Allocate a new drm_edid container. Do not calculate edid size from edid, pass 2544 * the actual size that has been allocated for the data. There is no validation 2545 * of the raw EDID data against the size, but at least the EDID base block must 2546 * fit in the buffer. 2547 * 2548 * The returned pointer must be freed using drm_edid_free(). 2549 * 2550 * Return: drm_edid container, or NULL on errors 2551 */ 2552 const struct drm_edid *drm_edid_alloc(const void *edid, size_t size) 2553 { 2554 const struct drm_edid *drm_edid; 2555 2556 if (!edid || !size || size < EDID_LENGTH) 2557 return NULL; 2558 2559 edid = kmemdup(edid, size, GFP_KERNEL); 2560 if (!edid) 2561 return NULL; 2562 2563 drm_edid = _drm_edid_alloc(edid, size); 2564 if (!drm_edid) 2565 kfree(edid); 2566 2567 return drm_edid; 2568 } 2569 EXPORT_SYMBOL(drm_edid_alloc); 2570 2571 /** 2572 * drm_edid_dup - Duplicate a drm_edid container 2573 * @drm_edid: EDID to duplicate 2574 * 2575 * The returned pointer must be freed using drm_edid_free(). 2576 * 2577 * Returns: drm_edid container copy, or NULL on errors 2578 */ 2579 const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid) 2580 { 2581 if (!drm_edid) 2582 return NULL; 2583 2584 return drm_edid_alloc(drm_edid->edid, drm_edid->size); 2585 } 2586 EXPORT_SYMBOL(drm_edid_dup); 2587 2588 /** 2589 * drm_edid_free - Free the drm_edid container 2590 * @drm_edid: EDID to free 2591 */ 2592 void drm_edid_free(const struct drm_edid *drm_edid) 2593 { 2594 if (!drm_edid) 2595 return; 2596 2597 kfree(drm_edid->edid); 2598 kfree(drm_edid); 2599 } 2600 EXPORT_SYMBOL(drm_edid_free); 2601 2602 /** 2603 * drm_probe_ddc() - probe DDC presence 2604 * @adapter: I2C adapter to probe 2605 * 2606 * Return: True on success, false on failure. 2607 */ 2608 bool 2609 drm_probe_ddc(struct i2c_adapter *adapter) 2610 { 2611 unsigned char out; 2612 2613 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 2614 } 2615 EXPORT_SYMBOL(drm_probe_ddc); 2616 2617 /** 2618 * drm_get_edid - get EDID data, if available 2619 * @connector: connector we're probing 2620 * @adapter: I2C adapter to use for DDC 2621 * 2622 * Poke the given I2C channel to grab EDID data if possible. If found, 2623 * attach it to the connector. 2624 * 2625 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2626 */ 2627 struct edid *drm_get_edid(struct drm_connector *connector, 2628 struct i2c_adapter *adapter) 2629 { 2630 struct edid *edid; 2631 2632 if (connector->force == DRM_FORCE_OFF) 2633 return NULL; 2634 2635 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2636 return NULL; 2637 2638 edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL); 2639 drm_connector_update_edid_property(connector, edid); 2640 return edid; 2641 } 2642 EXPORT_SYMBOL(drm_get_edid); 2643 2644 /** 2645 * drm_edid_read_custom - Read EDID data using given EDID block read function 2646 * @connector: Connector to use 2647 * @read_block: EDID block read function 2648 * @context: Private data passed to the block read function 2649 * 2650 * When the I2C adapter connected to the DDC bus is hidden behind a device that 2651 * exposes a different interface to read EDID blocks this function can be used 2652 * to get EDID data using a custom block read function. 2653 * 2654 * As in the general case the DDC bus is accessible by the kernel at the I2C 2655 * level, drivers must make all reasonable efforts to expose it as an I2C 2656 * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing 2657 * this function. 2658 * 2659 * The EDID may be overridden using debugfs override_edid or firmware EDID 2660 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2661 * order. Having either of them bypasses actual EDID reads. 2662 * 2663 * The returned pointer must be freed using drm_edid_free(). 2664 * 2665 * Return: Pointer to EDID, or NULL if probe/read failed. 2666 */ 2667 const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector, 2668 read_block_fn read_block, 2669 void *context) 2670 { 2671 const struct drm_edid *drm_edid; 2672 struct edid *edid; 2673 size_t size = 0; 2674 2675 edid = _drm_do_get_edid(connector, read_block, context, &size); 2676 if (!edid) 2677 return NULL; 2678 2679 /* Sanity check for now */ 2680 drm_WARN_ON(connector->dev, !size); 2681 2682 drm_edid = _drm_edid_alloc(edid, size); 2683 if (!drm_edid) 2684 kfree(edid); 2685 2686 return drm_edid; 2687 } 2688 EXPORT_SYMBOL(drm_edid_read_custom); 2689 2690 /** 2691 * drm_edid_read_ddc - Read EDID data using given I2C adapter 2692 * @connector: Connector to use 2693 * @adapter: I2C adapter to use for DDC 2694 * 2695 * Read EDID using the given I2C adapter. 2696 * 2697 * The EDID may be overridden using debugfs override_edid or firmware EDID 2698 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2699 * order. Having either of them bypasses actual EDID reads. 2700 * 2701 * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and 2702 * using drm_edid_read() instead of this function. 2703 * 2704 * The returned pointer must be freed using drm_edid_free(). 2705 * 2706 * Return: Pointer to EDID, or NULL if probe/read failed. 2707 */ 2708 const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector, 2709 struct i2c_adapter *adapter) 2710 { 2711 const struct drm_edid *drm_edid; 2712 2713 if (connector->force == DRM_FORCE_OFF) 2714 return NULL; 2715 2716 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2717 return NULL; 2718 2719 drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter); 2720 2721 /* Note: Do *not* call connector updates here. */ 2722 2723 return drm_edid; 2724 } 2725 EXPORT_SYMBOL(drm_edid_read_ddc); 2726 2727 /** 2728 * drm_edid_read - Read EDID data using connector's I2C adapter 2729 * @connector: Connector to use 2730 * 2731 * Read EDID using the connector's I2C adapter. 2732 * 2733 * The EDID may be overridden using debugfs override_edid or firmware EDID 2734 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2735 * order. Having either of them bypasses actual EDID reads. 2736 * 2737 * The returned pointer must be freed using drm_edid_free(). 2738 * 2739 * Return: Pointer to EDID, or NULL if probe/read failed. 2740 */ 2741 const struct drm_edid *drm_edid_read(struct drm_connector *connector) 2742 { 2743 if (drm_WARN_ON(connector->dev, !connector->ddc)) 2744 return NULL; 2745 2746 return drm_edid_read_ddc(connector, connector->ddc); 2747 } 2748 EXPORT_SYMBOL(drm_edid_read); 2749 2750 /** 2751 * drm_edid_get_product_id - Get the vendor and product identification 2752 * @drm_edid: EDID 2753 * @id: Where to place the product id 2754 */ 2755 void drm_edid_get_product_id(const struct drm_edid *drm_edid, 2756 struct drm_edid_product_id *id) 2757 { 2758 if (drm_edid && drm_edid->edid && drm_edid->size >= EDID_LENGTH) 2759 memcpy(id, &drm_edid->edid->product_id, sizeof(*id)); 2760 else 2761 memset(id, 0, sizeof(*id)); 2762 } 2763 EXPORT_SYMBOL(drm_edid_get_product_id); 2764 2765 static void decode_date(struct seq_buf *s, const struct drm_edid_product_id *id) 2766 { 2767 int week = id->week_of_manufacture; 2768 int year = id->year_of_manufacture + 1990; 2769 2770 if (week == 0xff) 2771 seq_buf_printf(s, "model year: %d", year); 2772 else if (!week) 2773 seq_buf_printf(s, "year of manufacture: %d", year); 2774 else 2775 seq_buf_printf(s, "week/year of manufacture: %d/%d", week, year); 2776 } 2777 2778 /** 2779 * drm_edid_print_product_id - Print decoded product id to printer 2780 * @p: drm printer 2781 * @id: EDID product id 2782 * @raw: If true, also print the raw hex 2783 * 2784 * See VESA E-EDID 1.4 section 3.4. 2785 */ 2786 void drm_edid_print_product_id(struct drm_printer *p, 2787 const struct drm_edid_product_id *id, bool raw) 2788 { 2789 DECLARE_SEQ_BUF(date, 40); 2790 char vend[4]; 2791 2792 drm_edid_decode_mfg_id(be16_to_cpu(id->manufacturer_name), vend); 2793 2794 decode_date(&date, id); 2795 2796 drm_printf(p, "manufacturer name: %s, product code: %u, serial number: %u, %s\n", 2797 vend, le16_to_cpu(id->product_code), 2798 le32_to_cpu(id->serial_number), seq_buf_str(&date)); 2799 2800 if (raw) 2801 drm_printf(p, "raw product id: %*ph\n", (int)sizeof(*id), id); 2802 2803 WARN_ON(seq_buf_has_overflowed(&date)); 2804 } 2805 EXPORT_SYMBOL(drm_edid_print_product_id); 2806 2807 /** 2808 * drm_edid_get_panel_id - Get a panel's ID from EDID 2809 * @drm_edid: EDID that contains panel ID. 2810 * 2811 * This function uses the first block of the EDID of a panel and (assuming 2812 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value 2813 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's 2814 * supposed to be different for each different modem of panel. 2815 * 2816 * Return: A 32-bit ID that should be different for each make/model of panel. 2817 * See the functions drm_edid_encode_panel_id() and 2818 * drm_edid_decode_panel_id() for some details on the structure of this 2819 * ID. Return 0 if the EDID size is less than a base block. 2820 */ 2821 u32 drm_edid_get_panel_id(const struct drm_edid *drm_edid) 2822 { 2823 const struct edid *edid = drm_edid->edid; 2824 2825 if (drm_edid->size < EDID_LENGTH) 2826 return 0; 2827 2828 /* 2829 * We represent the ID as a 32-bit number so it can easily be compared 2830 * with "==". 2831 * 2832 * NOTE that we deal with endianness differently for the top half 2833 * of this ID than for the bottom half. The bottom half (the product 2834 * id) gets decoded as little endian by the EDID_PRODUCT_ID because 2835 * that's how everyone seems to interpret it. The top half (the mfg_id) 2836 * gets stored as big endian because that makes 2837 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier 2838 * to write (it's easier to extract the ASCII). It doesn't really 2839 * matter, though, as long as the number here is unique. 2840 */ 2841 return (u32)edid->mfg_id[0] << 24 | 2842 (u32)edid->mfg_id[1] << 16 | 2843 (u32)EDID_PRODUCT_ID(edid); 2844 } 2845 EXPORT_SYMBOL(drm_edid_get_panel_id); 2846 2847 /** 2848 * drm_edid_read_base_block - Get a panel's EDID base block 2849 * @adapter: I2C adapter to use for DDC 2850 * 2851 * This function returns the drm_edid containing the first block of the EDID of 2852 * a panel. 2853 * 2854 * This function is intended to be used during early probing on devices where 2855 * more than one panel might be present. Because of its intended use it must 2856 * assume that the EDID of the panel is correct, at least as far as the base 2857 * block is concerned (in other words, we don't process any overrides here). 2858 * 2859 * Caller should call drm_edid_free() after use. 2860 * 2861 * NOTE: it's expected that this function and drm_do_get_edid() will both 2862 * be read the EDID, but there is no caching between them. Since we're only 2863 * reading the first block, hopefully this extra overhead won't be too big. 2864 * 2865 * WARNING: Only use this function when the connector is unknown. For example, 2866 * during the early probe of panel. The EDID read from the function is temporary 2867 * and should be replaced by the full EDID returned from other drm_edid_read. 2868 * 2869 * Return: Pointer to allocated EDID base block, or NULL on any failure. 2870 */ 2871 const struct drm_edid *drm_edid_read_base_block(struct i2c_adapter *adapter) 2872 { 2873 enum edid_block_status status; 2874 void *base_block; 2875 2876 base_block = kzalloc(EDID_LENGTH, GFP_KERNEL); 2877 if (!base_block) 2878 return NULL; 2879 2880 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter); 2881 2882 edid_block_status_print(status, base_block, 0); 2883 2884 if (!edid_block_status_valid(status, edid_block_tag(base_block))) { 2885 edid_block_dump(KERN_NOTICE, base_block, 0); 2886 kfree(base_block); 2887 return NULL; 2888 } 2889 2890 return _drm_edid_alloc(base_block, EDID_LENGTH); 2891 } 2892 EXPORT_SYMBOL(drm_edid_read_base_block); 2893 2894 /** 2895 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 2896 * @connector: connector we're probing 2897 * @adapter: I2C adapter to use for DDC 2898 * 2899 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 2900 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 2901 * switch DDC to the GPU which is retrieving EDID. 2902 * 2903 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2904 */ 2905 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 2906 struct i2c_adapter *adapter) 2907 { 2908 struct drm_device *dev = connector->dev; 2909 struct pci_dev *pdev = to_pci_dev(dev->dev); 2910 struct edid *edid; 2911 2912 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev))) 2913 return NULL; 2914 2915 vga_switcheroo_lock_ddc(pdev); 2916 edid = drm_get_edid(connector, adapter); 2917 vga_switcheroo_unlock_ddc(pdev); 2918 2919 return edid; 2920 } 2921 EXPORT_SYMBOL(drm_get_edid_switcheroo); 2922 2923 /** 2924 * drm_edid_read_switcheroo - get EDID data for a vga_switcheroo output 2925 * @connector: connector we're probing 2926 * @adapter: I2C adapter to use for DDC 2927 * 2928 * Wrapper around drm_edid_read_ddc() for laptops with dual GPUs using one set 2929 * of outputs. The wrapper adds the requisite vga_switcheroo calls to 2930 * temporarily switch DDC to the GPU which is retrieving EDID. 2931 * 2932 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2933 */ 2934 const struct drm_edid *drm_edid_read_switcheroo(struct drm_connector *connector, 2935 struct i2c_adapter *adapter) 2936 { 2937 struct drm_device *dev = connector->dev; 2938 struct pci_dev *pdev = to_pci_dev(dev->dev); 2939 const struct drm_edid *drm_edid; 2940 2941 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev))) 2942 return NULL; 2943 2944 vga_switcheroo_lock_ddc(pdev); 2945 drm_edid = drm_edid_read_ddc(connector, adapter); 2946 vga_switcheroo_unlock_ddc(pdev); 2947 2948 return drm_edid; 2949 } 2950 EXPORT_SYMBOL(drm_edid_read_switcheroo); 2951 2952 /** 2953 * drm_edid_duplicate - duplicate an EDID and the extensions 2954 * @edid: EDID to duplicate 2955 * 2956 * Return: Pointer to duplicated EDID or NULL on allocation failure. 2957 */ 2958 struct edid *drm_edid_duplicate(const struct edid *edid) 2959 { 2960 if (!edid) 2961 return NULL; 2962 2963 return kmemdup(edid, edid_size(edid), GFP_KERNEL); 2964 } 2965 EXPORT_SYMBOL(drm_edid_duplicate); 2966 2967 /*** EDID parsing ***/ 2968 2969 /** 2970 * edid_get_quirks - return quirk flags for a given EDID 2971 * @drm_edid: EDID to process 2972 * 2973 * This tells subsequent routines what fixes they need to apply. 2974 * 2975 * Return: A u32 represents the quirks to apply. 2976 */ 2977 static u32 edid_get_quirks(const struct drm_edid *drm_edid) 2978 { 2979 const struct edid_quirk *quirk; 2980 int i; 2981 2982 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 2983 quirk = &edid_quirk_list[i]; 2984 if (drm_edid_match(drm_edid, &quirk->ident)) 2985 return quirk->quirks; 2986 } 2987 2988 return 0; 2989 } 2990 2991 static bool drm_edid_has_internal_quirk(struct drm_connector *connector, 2992 enum drm_edid_internal_quirk quirk) 2993 { 2994 return connector->display_info.quirks & BIT(quirk); 2995 } 2996 2997 bool drm_edid_has_quirk(struct drm_connector *connector, enum drm_edid_quirk quirk) 2998 { 2999 return connector->display_info.quirks & BIT(quirk); 3000 } 3001 EXPORT_SYMBOL(drm_edid_has_quirk); 3002 3003 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 3004 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 3005 3006 /* 3007 * Walk the mode list for connector, clearing the preferred status on existing 3008 * modes and setting it anew for the right mode ala quirks. 3009 */ 3010 static void edid_fixup_preferred(struct drm_connector *connector) 3011 { 3012 struct drm_display_mode *t, *cur_mode, *preferred_mode; 3013 int target_refresh = 0; 3014 int cur_vrefresh, preferred_vrefresh; 3015 3016 if (list_empty(&connector->probed_modes)) 3017 return; 3018 3019 if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_PREFER_LARGE_60)) 3020 target_refresh = 60; 3021 if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_PREFER_LARGE_75)) 3022 target_refresh = 75; 3023 3024 preferred_mode = list_first_entry(&connector->probed_modes, 3025 struct drm_display_mode, head); 3026 3027 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 3028 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 3029 3030 if (cur_mode == preferred_mode) 3031 continue; 3032 3033 /* Largest mode is preferred */ 3034 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 3035 preferred_mode = cur_mode; 3036 3037 cur_vrefresh = drm_mode_vrefresh(cur_mode); 3038 preferred_vrefresh = drm_mode_vrefresh(preferred_mode); 3039 /* At a given size, try to get closest to target refresh */ 3040 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 3041 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 3042 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 3043 preferred_mode = cur_mode; 3044 } 3045 } 3046 3047 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 3048 } 3049 3050 static bool 3051 mode_is_rb(const struct drm_display_mode *mode) 3052 { 3053 return (mode->htotal - mode->hdisplay == 160) && 3054 (mode->hsync_end - mode->hdisplay == 80) && 3055 (mode->hsync_end - mode->hsync_start == 32) && 3056 (mode->vsync_start - mode->vdisplay == 3); 3057 } 3058 3059 /* 3060 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 3061 * @dev: Device to duplicate against 3062 * @hsize: Mode width 3063 * @vsize: Mode height 3064 * @fresh: Mode refresh rate 3065 * @rb: Mode reduced-blanking-ness 3066 * 3067 * Walk the DMT mode list looking for a match for the given parameters. 3068 * 3069 * Return: A newly allocated copy of the mode, or NULL if not found. 3070 */ 3071 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 3072 int hsize, int vsize, int fresh, 3073 bool rb) 3074 { 3075 int i; 3076 3077 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 3078 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 3079 3080 if (hsize != ptr->hdisplay) 3081 continue; 3082 if (vsize != ptr->vdisplay) 3083 continue; 3084 if (fresh != drm_mode_vrefresh(ptr)) 3085 continue; 3086 if (rb != mode_is_rb(ptr)) 3087 continue; 3088 3089 return drm_mode_duplicate(dev, ptr); 3090 } 3091 3092 return NULL; 3093 } 3094 EXPORT_SYMBOL(drm_mode_find_dmt); 3095 3096 static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type) 3097 { 3098 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0); 3099 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2); 3100 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3); 3101 3102 return descriptor->pixel_clock == 0 && 3103 descriptor->data.other_data.pad1 == 0 && 3104 descriptor->data.other_data.type == type; 3105 } 3106 3107 static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor) 3108 { 3109 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0); 3110 3111 return descriptor->pixel_clock != 0; 3112 } 3113 3114 typedef void detailed_cb(const struct detailed_timing *timing, void *closure); 3115 3116 static void 3117 cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure) 3118 { 3119 int i, n; 3120 u8 d = ext[0x02]; 3121 const u8 *det_base = ext + d; 3122 3123 if (d < 4 || d > 127) 3124 return; 3125 3126 n = (127 - d) / 18; 3127 for (i = 0; i < n; i++) 3128 cb((const struct detailed_timing *)(det_base + 18 * i), closure); 3129 } 3130 3131 static void 3132 vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure) 3133 { 3134 unsigned int i, n = min((int)ext[0x02], 6); 3135 const u8 *det_base = ext + 5; 3136 3137 if (ext[0x01] != 1) 3138 return; /* unknown version */ 3139 3140 for (i = 0; i < n; i++) 3141 cb((const struct detailed_timing *)(det_base + 18 * i), closure); 3142 } 3143 3144 static void drm_for_each_detailed_block(const struct drm_edid *drm_edid, 3145 detailed_cb *cb, void *closure) 3146 { 3147 struct drm_edid_iter edid_iter; 3148 const u8 *ext; 3149 int i; 3150 3151 if (!drm_edid) 3152 return; 3153 3154 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 3155 cb(&drm_edid->edid->detailed_timings[i], closure); 3156 3157 drm_edid_iter_begin(drm_edid, &edid_iter); 3158 drm_edid_iter_for_each(ext, &edid_iter) { 3159 switch (*ext) { 3160 case CEA_EXT: 3161 cea_for_each_detailed_block(ext, cb, closure); 3162 break; 3163 case VTB_EXT: 3164 vtb_for_each_detailed_block(ext, cb, closure); 3165 break; 3166 default: 3167 break; 3168 } 3169 } 3170 drm_edid_iter_end(&edid_iter); 3171 } 3172 3173 static void 3174 is_rb(const struct detailed_timing *descriptor, void *data) 3175 { 3176 bool *res = data; 3177 3178 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 3179 return; 3180 3181 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 3182 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15); 3183 3184 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG && 3185 descriptor->data.other_data.data.range.formula.cvt.flags & DRM_EDID_CVT_FLAGS_REDUCED_BLANKING) 3186 *res = true; 3187 } 3188 3189 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 3190 static bool 3191 drm_monitor_supports_rb(const struct drm_edid *drm_edid) 3192 { 3193 if (drm_edid->edid->revision >= 4) { 3194 bool ret = false; 3195 3196 drm_for_each_detailed_block(drm_edid, is_rb, &ret); 3197 return ret; 3198 } 3199 3200 return drm_edid_is_digital(drm_edid); 3201 } 3202 3203 static void 3204 find_gtf2(const struct detailed_timing *descriptor, void *data) 3205 { 3206 const struct detailed_timing **res = data; 3207 3208 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 3209 return; 3210 3211 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 3212 3213 if (descriptor->data.other_data.data.range.flags == DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG) 3214 *res = descriptor; 3215 } 3216 3217 /* Secondary GTF curve kicks in above some break frequency */ 3218 static int 3219 drm_gtf2_hbreak(const struct drm_edid *drm_edid) 3220 { 3221 const struct detailed_timing *descriptor = NULL; 3222 3223 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3224 3225 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12); 3226 3227 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0; 3228 } 3229 3230 static int 3231 drm_gtf2_2c(const struct drm_edid *drm_edid) 3232 { 3233 const struct detailed_timing *descriptor = NULL; 3234 3235 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3236 3237 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13); 3238 3239 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0; 3240 } 3241 3242 static int 3243 drm_gtf2_m(const struct drm_edid *drm_edid) 3244 { 3245 const struct detailed_timing *descriptor = NULL; 3246 3247 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3248 3249 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14); 3250 3251 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0; 3252 } 3253 3254 static int 3255 drm_gtf2_k(const struct drm_edid *drm_edid) 3256 { 3257 const struct detailed_timing *descriptor = NULL; 3258 3259 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3260 3261 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16); 3262 3263 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0; 3264 } 3265 3266 static int 3267 drm_gtf2_2j(const struct drm_edid *drm_edid) 3268 { 3269 const struct detailed_timing *descriptor = NULL; 3270 3271 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3272 3273 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17); 3274 3275 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0; 3276 } 3277 3278 static void 3279 get_timing_level(const struct detailed_timing *descriptor, void *data) 3280 { 3281 int *res = data; 3282 3283 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 3284 return; 3285 3286 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 3287 3288 switch (descriptor->data.other_data.data.range.flags) { 3289 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG: 3290 *res = LEVEL_GTF; 3291 break; 3292 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG: 3293 *res = LEVEL_GTF2; 3294 break; 3295 case DRM_EDID_CVT_SUPPORT_FLAG: 3296 *res = LEVEL_CVT; 3297 break; 3298 default: 3299 break; 3300 } 3301 } 3302 3303 /* Get standard timing level (CVT/GTF/DMT). */ 3304 static int standard_timing_level(const struct drm_edid *drm_edid) 3305 { 3306 const struct edid *edid = drm_edid->edid; 3307 3308 if (edid->revision >= 4) { 3309 /* 3310 * If the range descriptor doesn't 3311 * indicate otherwise default to CVT 3312 */ 3313 int ret = LEVEL_CVT; 3314 3315 drm_for_each_detailed_block(drm_edid, get_timing_level, &ret); 3316 3317 return ret; 3318 } else if (edid->revision >= 3 && drm_gtf2_hbreak(drm_edid)) { 3319 return LEVEL_GTF2; 3320 } else if (edid->revision >= 2) { 3321 return LEVEL_GTF; 3322 } else { 3323 return LEVEL_DMT; 3324 } 3325 } 3326 3327 /* 3328 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 3329 * monitors fill with ascii space (0x20) instead. 3330 */ 3331 static int 3332 bad_std_timing(u8 a, u8 b) 3333 { 3334 return (a == 0x00 && b == 0x00) || 3335 (a == 0x01 && b == 0x01) || 3336 (a == 0x20 && b == 0x20); 3337 } 3338 3339 static int drm_mode_hsync(const struct drm_display_mode *mode) 3340 { 3341 if (mode->htotal <= 0) 3342 return 0; 3343 3344 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal); 3345 } 3346 3347 static struct drm_display_mode * 3348 drm_gtf2_mode(struct drm_device *dev, 3349 const struct drm_edid *drm_edid, 3350 int hsize, int vsize, int vrefresh_rate) 3351 { 3352 struct drm_display_mode *mode; 3353 3354 /* 3355 * This is potentially wrong if there's ever a monitor with 3356 * more than one ranges section, each claiming a different 3357 * secondary GTF curve. Please don't do that. 3358 */ 3359 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 3360 if (!mode) 3361 return NULL; 3362 3363 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) { 3364 drm_mode_destroy(dev, mode); 3365 mode = drm_gtf_mode_complex(dev, hsize, vsize, 3366 vrefresh_rate, 0, 0, 3367 drm_gtf2_m(drm_edid), 3368 drm_gtf2_2c(drm_edid), 3369 drm_gtf2_k(drm_edid), 3370 drm_gtf2_2j(drm_edid)); 3371 } 3372 3373 return mode; 3374 } 3375 3376 /* 3377 * Take the standard timing params (in this case width, aspect, and refresh) 3378 * and convert them into a real mode using CVT/GTF/DMT. 3379 */ 3380 static struct drm_display_mode *drm_mode_std(struct drm_connector *connector, 3381 const struct drm_edid *drm_edid, 3382 const struct std_timing *t) 3383 { 3384 struct drm_device *dev = connector->dev; 3385 struct drm_display_mode *m, *mode = NULL; 3386 int hsize, vsize; 3387 int vrefresh_rate; 3388 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 3389 >> EDID_TIMING_ASPECT_SHIFT; 3390 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 3391 >> EDID_TIMING_VFREQ_SHIFT; 3392 int timing_level = standard_timing_level(drm_edid); 3393 3394 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 3395 return NULL; 3396 3397 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 3398 hsize = t->hsize * 8 + 248; 3399 /* vrefresh_rate = vfreq + 60 */ 3400 vrefresh_rate = vfreq + 60; 3401 /* the vdisplay is calculated based on the aspect ratio */ 3402 if (aspect_ratio == 0) { 3403 if (drm_edid->edid->revision < 3) 3404 vsize = hsize; 3405 else 3406 vsize = (hsize * 10) / 16; 3407 } else if (aspect_ratio == 1) 3408 vsize = (hsize * 3) / 4; 3409 else if (aspect_ratio == 2) 3410 vsize = (hsize * 4) / 5; 3411 else 3412 vsize = (hsize * 9) / 16; 3413 3414 /* HDTV hack, part 1 */ 3415 if (vrefresh_rate == 60 && 3416 ((hsize == 1360 && vsize == 765) || 3417 (hsize == 1368 && vsize == 769))) { 3418 hsize = 1366; 3419 vsize = 768; 3420 } 3421 3422 /* 3423 * If this connector already has a mode for this size and refresh 3424 * rate (because it came from detailed or CVT info), use that 3425 * instead. This way we don't have to guess at interlace or 3426 * reduced blanking. 3427 */ 3428 list_for_each_entry(m, &connector->probed_modes, head) 3429 if (m->hdisplay == hsize && m->vdisplay == vsize && 3430 drm_mode_vrefresh(m) == vrefresh_rate) 3431 return NULL; 3432 3433 /* HDTV hack, part 2 */ 3434 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 3435 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 3436 false); 3437 if (!mode) 3438 return NULL; 3439 mode->hdisplay = 1366; 3440 mode->hsync_start = mode->hsync_start - 1; 3441 mode->hsync_end = mode->hsync_end - 1; 3442 return mode; 3443 } 3444 3445 /* check whether it can be found in default mode table */ 3446 if (drm_monitor_supports_rb(drm_edid)) { 3447 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 3448 true); 3449 if (mode) 3450 return mode; 3451 } 3452 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 3453 if (mode) 3454 return mode; 3455 3456 /* okay, generate it */ 3457 switch (timing_level) { 3458 case LEVEL_DMT: 3459 break; 3460 case LEVEL_GTF: 3461 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 3462 break; 3463 case LEVEL_GTF2: 3464 mode = drm_gtf2_mode(dev, drm_edid, hsize, vsize, vrefresh_rate); 3465 break; 3466 case LEVEL_CVT: 3467 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 3468 false); 3469 break; 3470 } 3471 return mode; 3472 } 3473 3474 /* 3475 * EDID is delightfully ambiguous about how interlaced modes are to be 3476 * encoded. Our internal representation is of frame height, but some 3477 * HDTV detailed timings are encoded as field height. 3478 * 3479 * The format list here is from CEA, in frame size. Technically we 3480 * should be checking refresh rate too. Whatever. 3481 */ 3482 static void 3483 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 3484 const struct detailed_pixel_timing *pt) 3485 { 3486 int i; 3487 static const struct { 3488 int w, h; 3489 } cea_interlaced[] = { 3490 { 1920, 1080 }, 3491 { 720, 480 }, 3492 { 1440, 480 }, 3493 { 2880, 480 }, 3494 { 720, 576 }, 3495 { 1440, 576 }, 3496 { 2880, 576 }, 3497 }; 3498 3499 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 3500 return; 3501 3502 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 3503 if ((mode->hdisplay == cea_interlaced[i].w) && 3504 (mode->vdisplay == cea_interlaced[i].h / 2)) { 3505 mode->vdisplay *= 2; 3506 mode->vsync_start *= 2; 3507 mode->vsync_end *= 2; 3508 mode->vtotal *= 2; 3509 mode->vtotal |= 1; 3510 } 3511 } 3512 3513 mode->flags |= DRM_MODE_FLAG_INTERLACE; 3514 } 3515 3516 /* 3517 * Create a new mode from an EDID detailed timing section. An EDID detailed 3518 * timing block contains enough info for us to create and return a new struct 3519 * drm_display_mode. 3520 */ 3521 static struct drm_display_mode *drm_mode_detailed(struct drm_connector *connector, 3522 const struct drm_edid *drm_edid, 3523 const struct detailed_timing *timing) 3524 { 3525 struct drm_device *dev = connector->dev; 3526 struct drm_display_mode *mode; 3527 const struct detailed_pixel_timing *pt = &timing->data.pixel_data; 3528 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 3529 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 3530 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 3531 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 3532 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 3533 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 3534 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 3535 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 3536 3537 /* ignore tiny modes */ 3538 if (hactive < 64 || vactive < 64) 3539 return NULL; 3540 3541 if (pt->misc & DRM_EDID_PT_STEREO) { 3542 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Stereo mode not supported\n", 3543 connector->base.id, connector->name); 3544 return NULL; 3545 } 3546 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 3547 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Composite sync not supported\n", 3548 connector->base.id, connector->name); 3549 } 3550 3551 /* it is incorrect if hsync/vsync width is zero */ 3552 if (!hsync_pulse_width || !vsync_pulse_width) { 3553 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Incorrect Detailed timing. Wrong Hsync/Vsync pulse width\n", 3554 connector->base.id, connector->name); 3555 return NULL; 3556 } 3557 3558 if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_FORCE_REDUCED_BLANKING)) { 3559 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 3560 if (!mode) 3561 return NULL; 3562 3563 goto set_size; 3564 } 3565 3566 mode = drm_mode_create(dev); 3567 if (!mode) 3568 return NULL; 3569 3570 if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_135_CLOCK_TOO_HIGH)) 3571 mode->clock = 1088 * 10; 3572 else 3573 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 3574 3575 mode->hdisplay = hactive; 3576 mode->hsync_start = mode->hdisplay + hsync_offset; 3577 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 3578 mode->htotal = mode->hdisplay + hblank; 3579 3580 mode->vdisplay = vactive; 3581 mode->vsync_start = mode->vdisplay + vsync_offset; 3582 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 3583 mode->vtotal = mode->vdisplay + vblank; 3584 3585 /* Some EDIDs have bogus h/vsync_end values */ 3586 if (mode->hsync_end > mode->htotal) { 3587 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing hsync_end %d->%d\n", 3588 connector->base.id, connector->name, 3589 mode->hsync_end, mode->htotal); 3590 mode->hsync_end = mode->htotal; 3591 } 3592 if (mode->vsync_end > mode->vtotal) { 3593 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing vsync_end %d->%d\n", 3594 connector->base.id, connector->name, 3595 mode->vsync_end, mode->vtotal); 3596 mode->vsync_end = mode->vtotal; 3597 } 3598 3599 drm_mode_do_interlace_quirk(mode, pt); 3600 3601 if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_DETAILED_SYNC_PP)) { 3602 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC; 3603 } else { 3604 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 3605 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 3606 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 3607 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 3608 } 3609 3610 set_size: 3611 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 3612 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 3613 3614 if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_DETAILED_IN_CM)) { 3615 mode->width_mm *= 10; 3616 mode->height_mm *= 10; 3617 } 3618 3619 if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE)) { 3620 mode->width_mm = drm_edid->edid->width_cm * 10; 3621 mode->height_mm = drm_edid->edid->height_cm * 10; 3622 } 3623 3624 mode->type = DRM_MODE_TYPE_DRIVER; 3625 drm_mode_set_name(mode); 3626 3627 return mode; 3628 } 3629 3630 static bool 3631 mode_in_hsync_range(const struct drm_display_mode *mode, 3632 const struct edid *edid, const u8 *t) 3633 { 3634 int hsync, hmin, hmax; 3635 3636 hmin = t[7]; 3637 if (edid->revision >= 4) 3638 hmin += ((t[4] & 0x04) ? 255 : 0); 3639 hmax = t[8]; 3640 if (edid->revision >= 4) 3641 hmax += ((t[4] & 0x08) ? 255 : 0); 3642 hsync = drm_mode_hsync(mode); 3643 3644 return (hsync <= hmax && hsync >= hmin); 3645 } 3646 3647 static bool 3648 mode_in_vsync_range(const struct drm_display_mode *mode, 3649 const struct edid *edid, const u8 *t) 3650 { 3651 int vsync, vmin, vmax; 3652 3653 vmin = t[5]; 3654 if (edid->revision >= 4) 3655 vmin += ((t[4] & 0x01) ? 255 : 0); 3656 vmax = t[6]; 3657 if (edid->revision >= 4) 3658 vmax += ((t[4] & 0x02) ? 255 : 0); 3659 vsync = drm_mode_vrefresh(mode); 3660 3661 return (vsync <= vmax && vsync >= vmin); 3662 } 3663 3664 static u32 3665 range_pixel_clock(const struct edid *edid, const u8 *t) 3666 { 3667 /* unspecified */ 3668 if (t[9] == 0 || t[9] == 255) 3669 return 0; 3670 3671 /* 1.4 with CVT support gives us real precision, yay */ 3672 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG) 3673 return (t[9] * 10000) - ((t[12] >> 2) * 250); 3674 3675 /* 1.3 is pathetic, so fuzz up a bit */ 3676 return t[9] * 10000 + 5001; 3677 } 3678 3679 static bool mode_in_range(const struct drm_display_mode *mode, 3680 const struct drm_edid *drm_edid, 3681 const struct detailed_timing *timing) 3682 { 3683 const struct edid *edid = drm_edid->edid; 3684 u32 max_clock; 3685 const u8 *t = (const u8 *)timing; 3686 3687 if (!mode_in_hsync_range(mode, edid, t)) 3688 return false; 3689 3690 if (!mode_in_vsync_range(mode, edid, t)) 3691 return false; 3692 3693 max_clock = range_pixel_clock(edid, t); 3694 if (max_clock) 3695 if (mode->clock > max_clock) 3696 return false; 3697 3698 /* 1.4 max horizontal check */ 3699 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG) 3700 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 3701 return false; 3702 3703 if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid)) 3704 return false; 3705 3706 return true; 3707 } 3708 3709 static bool valid_inferred_mode(const struct drm_connector *connector, 3710 const struct drm_display_mode *mode) 3711 { 3712 const struct drm_display_mode *m; 3713 bool ok = false; 3714 3715 list_for_each_entry(m, &connector->probed_modes, head) { 3716 if (mode->hdisplay == m->hdisplay && 3717 mode->vdisplay == m->vdisplay && 3718 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 3719 return false; /* duplicated */ 3720 if (mode->hdisplay <= m->hdisplay && 3721 mode->vdisplay <= m->vdisplay) 3722 ok = true; 3723 } 3724 return ok; 3725 } 3726 3727 static int drm_dmt_modes_for_range(struct drm_connector *connector, 3728 const struct drm_edid *drm_edid, 3729 const struct detailed_timing *timing) 3730 { 3731 int i, modes = 0; 3732 struct drm_display_mode *newmode; 3733 struct drm_device *dev = connector->dev; 3734 3735 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 3736 if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) && 3737 valid_inferred_mode(connector, drm_dmt_modes + i)) { 3738 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 3739 if (newmode) { 3740 drm_mode_probed_add(connector, newmode); 3741 modes++; 3742 } 3743 } 3744 } 3745 3746 return modes; 3747 } 3748 3749 /* fix up 1366x768 mode from 1368x768; 3750 * GFT/CVT can't express 1366 width which isn't dividable by 8 3751 */ 3752 void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 3753 { 3754 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 3755 mode->hdisplay = 1366; 3756 mode->hsync_start--; 3757 mode->hsync_end--; 3758 drm_mode_set_name(mode); 3759 } 3760 } 3761 3762 static int drm_gtf_modes_for_range(struct drm_connector *connector, 3763 const struct drm_edid *drm_edid, 3764 const struct detailed_timing *timing) 3765 { 3766 int i, modes = 0; 3767 struct drm_display_mode *newmode; 3768 struct drm_device *dev = connector->dev; 3769 3770 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3771 const struct minimode *m = &extra_modes[i]; 3772 3773 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 3774 if (!newmode) 3775 return modes; 3776 3777 drm_mode_fixup_1366x768(newmode); 3778 if (!mode_in_range(newmode, drm_edid, timing) || 3779 !valid_inferred_mode(connector, newmode)) { 3780 drm_mode_destroy(dev, newmode); 3781 continue; 3782 } 3783 3784 drm_mode_probed_add(connector, newmode); 3785 modes++; 3786 } 3787 3788 return modes; 3789 } 3790 3791 static int drm_gtf2_modes_for_range(struct drm_connector *connector, 3792 const struct drm_edid *drm_edid, 3793 const struct detailed_timing *timing) 3794 { 3795 int i, modes = 0; 3796 struct drm_display_mode *newmode; 3797 struct drm_device *dev = connector->dev; 3798 3799 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3800 const struct minimode *m = &extra_modes[i]; 3801 3802 newmode = drm_gtf2_mode(dev, drm_edid, m->w, m->h, m->r); 3803 if (!newmode) 3804 return modes; 3805 3806 drm_mode_fixup_1366x768(newmode); 3807 if (!mode_in_range(newmode, drm_edid, timing) || 3808 !valid_inferred_mode(connector, newmode)) { 3809 drm_mode_destroy(dev, newmode); 3810 continue; 3811 } 3812 3813 drm_mode_probed_add(connector, newmode); 3814 modes++; 3815 } 3816 3817 return modes; 3818 } 3819 3820 static int drm_cvt_modes_for_range(struct drm_connector *connector, 3821 const struct drm_edid *drm_edid, 3822 const struct detailed_timing *timing) 3823 { 3824 int i, modes = 0; 3825 struct drm_display_mode *newmode; 3826 struct drm_device *dev = connector->dev; 3827 bool rb = drm_monitor_supports_rb(drm_edid); 3828 3829 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3830 const struct minimode *m = &extra_modes[i]; 3831 3832 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 3833 if (!newmode) 3834 return modes; 3835 3836 drm_mode_fixup_1366x768(newmode); 3837 if (!mode_in_range(newmode, drm_edid, timing) || 3838 !valid_inferred_mode(connector, newmode)) { 3839 drm_mode_destroy(dev, newmode); 3840 continue; 3841 } 3842 3843 drm_mode_probed_add(connector, newmode); 3844 modes++; 3845 } 3846 3847 return modes; 3848 } 3849 3850 static void 3851 do_inferred_modes(const struct detailed_timing *timing, void *c) 3852 { 3853 struct detailed_mode_closure *closure = c; 3854 const struct detailed_non_pixel *data = &timing->data.other_data; 3855 const struct detailed_data_monitor_range *range = &data->data.range; 3856 3857 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE)) 3858 return; 3859 3860 closure->modes += drm_dmt_modes_for_range(closure->connector, 3861 closure->drm_edid, 3862 timing); 3863 3864 if (closure->drm_edid->edid->revision < 2) 3865 return; /* GTF not defined yet */ 3866 3867 switch (range->flags) { 3868 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG: 3869 closure->modes += drm_gtf2_modes_for_range(closure->connector, 3870 closure->drm_edid, 3871 timing); 3872 break; 3873 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG: 3874 closure->modes += drm_gtf_modes_for_range(closure->connector, 3875 closure->drm_edid, 3876 timing); 3877 break; 3878 case DRM_EDID_CVT_SUPPORT_FLAG: 3879 if (closure->drm_edid->edid->revision < 4) 3880 break; 3881 3882 closure->modes += drm_cvt_modes_for_range(closure->connector, 3883 closure->drm_edid, 3884 timing); 3885 break; 3886 case DRM_EDID_RANGE_LIMITS_ONLY_FLAG: 3887 default: 3888 break; 3889 } 3890 } 3891 3892 static int add_inferred_modes(struct drm_connector *connector, 3893 const struct drm_edid *drm_edid) 3894 { 3895 struct detailed_mode_closure closure = { 3896 .connector = connector, 3897 .drm_edid = drm_edid, 3898 }; 3899 3900 if (drm_edid->edid->revision >= 1) 3901 drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure); 3902 3903 return closure.modes; 3904 } 3905 3906 static int 3907 drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing) 3908 { 3909 int i, j, m, modes = 0; 3910 struct drm_display_mode *mode; 3911 const u8 *est = ((const u8 *)timing) + 6; 3912 3913 for (i = 0; i < 6; i++) { 3914 for (j = 7; j >= 0; j--) { 3915 m = (i * 8) + (7 - j); 3916 if (m >= ARRAY_SIZE(est3_modes)) 3917 break; 3918 if (est[i] & (1 << j)) { 3919 mode = drm_mode_find_dmt(connector->dev, 3920 est3_modes[m].w, 3921 est3_modes[m].h, 3922 est3_modes[m].r, 3923 est3_modes[m].rb); 3924 if (mode) { 3925 drm_mode_probed_add(connector, mode); 3926 modes++; 3927 } 3928 } 3929 } 3930 } 3931 3932 return modes; 3933 } 3934 3935 static void 3936 do_established_modes(const struct detailed_timing *timing, void *c) 3937 { 3938 struct detailed_mode_closure *closure = c; 3939 3940 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS)) 3941 return; 3942 3943 closure->modes += drm_est3_modes(closure->connector, timing); 3944 } 3945 3946 /* 3947 * Get established modes from EDID and add them. Each EDID block contains a 3948 * bitmap of the supported "established modes" list (defined above). Tease them 3949 * out and add them to the global modes list. 3950 */ 3951 static int add_established_modes(struct drm_connector *connector, 3952 const struct drm_edid *drm_edid) 3953 { 3954 struct drm_device *dev = connector->dev; 3955 const struct edid *edid = drm_edid->edid; 3956 unsigned long est_bits = edid->established_timings.t1 | 3957 (edid->established_timings.t2 << 8) | 3958 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 3959 int i, modes = 0; 3960 struct detailed_mode_closure closure = { 3961 .connector = connector, 3962 .drm_edid = drm_edid, 3963 }; 3964 3965 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 3966 if (est_bits & (1<<i)) { 3967 struct drm_display_mode *newmode; 3968 3969 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 3970 if (newmode) { 3971 drm_mode_probed_add(connector, newmode); 3972 modes++; 3973 } 3974 } 3975 } 3976 3977 if (edid->revision >= 1) 3978 drm_for_each_detailed_block(drm_edid, do_established_modes, 3979 &closure); 3980 3981 return modes + closure.modes; 3982 } 3983 3984 static void 3985 do_standard_modes(const struct detailed_timing *timing, void *c) 3986 { 3987 struct detailed_mode_closure *closure = c; 3988 const struct detailed_non_pixel *data = &timing->data.other_data; 3989 struct drm_connector *connector = closure->connector; 3990 int i; 3991 3992 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES)) 3993 return; 3994 3995 for (i = 0; i < 6; i++) { 3996 const struct std_timing *std = &data->data.timings[i]; 3997 struct drm_display_mode *newmode; 3998 3999 newmode = drm_mode_std(connector, closure->drm_edid, std); 4000 if (newmode) { 4001 drm_mode_probed_add(connector, newmode); 4002 closure->modes++; 4003 } 4004 } 4005 } 4006 4007 /* 4008 * Get standard modes from EDID and add them. Standard modes can be calculated 4009 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and 4010 * add them to the list. 4011 */ 4012 static int add_standard_modes(struct drm_connector *connector, 4013 const struct drm_edid *drm_edid) 4014 { 4015 int i, modes = 0; 4016 struct detailed_mode_closure closure = { 4017 .connector = connector, 4018 .drm_edid = drm_edid, 4019 }; 4020 4021 for (i = 0; i < EDID_STD_TIMINGS; i++) { 4022 struct drm_display_mode *newmode; 4023 4024 newmode = drm_mode_std(connector, drm_edid, 4025 &drm_edid->edid->standard_timings[i]); 4026 if (newmode) { 4027 drm_mode_probed_add(connector, newmode); 4028 modes++; 4029 } 4030 } 4031 4032 if (drm_edid->edid->revision >= 1) 4033 drm_for_each_detailed_block(drm_edid, do_standard_modes, 4034 &closure); 4035 4036 /* XXX should also look for standard codes in VTB blocks */ 4037 4038 return modes + closure.modes; 4039 } 4040 4041 static int drm_cvt_modes(struct drm_connector *connector, 4042 const struct detailed_timing *timing) 4043 { 4044 int i, j, modes = 0; 4045 struct drm_display_mode *newmode; 4046 struct drm_device *dev = connector->dev; 4047 const struct cvt_timing *cvt; 4048 static const int rates[] = { 60, 85, 75, 60, 50 }; 4049 const u8 empty[3] = { 0, 0, 0 }; 4050 4051 for (i = 0; i < 4; i++) { 4052 int width, height; 4053 4054 cvt = &(timing->data.other_data.data.cvt[i]); 4055 4056 if (!memcmp(cvt->code, empty, 3)) 4057 continue; 4058 4059 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 4060 switch (cvt->code[1] & 0x0c) { 4061 /* default - because compiler doesn't see that we've enumerated all cases */ 4062 default: 4063 case 0x00: 4064 width = height * 4 / 3; 4065 break; 4066 case 0x04: 4067 width = height * 16 / 9; 4068 break; 4069 case 0x08: 4070 width = height * 16 / 10; 4071 break; 4072 case 0x0c: 4073 width = height * 15 / 9; 4074 break; 4075 } 4076 4077 for (j = 1; j < 5; j++) { 4078 if (cvt->code[2] & (1 << j)) { 4079 newmode = drm_cvt_mode(dev, width, height, 4080 rates[j], j == 0, 4081 false, false); 4082 if (newmode) { 4083 drm_mode_probed_add(connector, newmode); 4084 modes++; 4085 } 4086 } 4087 } 4088 } 4089 4090 return modes; 4091 } 4092 4093 static void 4094 do_cvt_mode(const struct detailed_timing *timing, void *c) 4095 { 4096 struct detailed_mode_closure *closure = c; 4097 4098 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE)) 4099 return; 4100 4101 closure->modes += drm_cvt_modes(closure->connector, timing); 4102 } 4103 4104 static int 4105 add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid) 4106 { 4107 struct detailed_mode_closure closure = { 4108 .connector = connector, 4109 .drm_edid = drm_edid, 4110 }; 4111 4112 if (drm_edid->edid->revision >= 3) 4113 drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure); 4114 4115 /* XXX should also look for CVT codes in VTB blocks */ 4116 4117 return closure.modes; 4118 } 4119 4120 static void fixup_detailed_cea_mode_clock(struct drm_connector *connector, 4121 struct drm_display_mode *mode); 4122 4123 static void 4124 do_detailed_mode(const struct detailed_timing *timing, void *c) 4125 { 4126 struct detailed_mode_closure *closure = c; 4127 struct drm_display_mode *newmode; 4128 4129 if (!is_detailed_timing_descriptor(timing)) 4130 return; 4131 4132 newmode = drm_mode_detailed(closure->connector, 4133 closure->drm_edid, timing); 4134 if (!newmode) 4135 return; 4136 4137 if (closure->preferred) 4138 newmode->type |= DRM_MODE_TYPE_PREFERRED; 4139 4140 /* 4141 * Detailed modes are limited to 10kHz pixel clock resolution, 4142 * so fix up anything that looks like CEA/HDMI mode, but the clock 4143 * is just slightly off. 4144 */ 4145 fixup_detailed_cea_mode_clock(closure->connector, newmode); 4146 4147 drm_mode_probed_add(closure->connector, newmode); 4148 closure->modes++; 4149 closure->preferred = false; 4150 } 4151 4152 /* 4153 * add_detailed_modes - Add modes from detailed timings 4154 * @connector: attached connector 4155 * @drm_edid: EDID block to scan 4156 */ 4157 static int add_detailed_modes(struct drm_connector *connector, 4158 const struct drm_edid *drm_edid) 4159 { 4160 struct detailed_mode_closure closure = { 4161 .connector = connector, 4162 .drm_edid = drm_edid, 4163 }; 4164 4165 if (drm_edid->edid->revision >= 4) 4166 closure.preferred = true; /* first detailed timing is always preferred */ 4167 else 4168 closure.preferred = 4169 drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING; 4170 4171 drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure); 4172 4173 return closure.modes; 4174 } 4175 4176 /* CTA-861-H Table 60 - CTA Tag Codes */ 4177 #define CTA_DB_AUDIO 1 4178 #define CTA_DB_VIDEO 2 4179 #define CTA_DB_VENDOR 3 4180 #define CTA_DB_SPEAKER 4 4181 #define CTA_DB_EXTENDED_TAG 7 4182 4183 /* CTA-861-H Table 62 - CTA Extended Tag Codes */ 4184 #define CTA_EXT_DB_VIDEO_CAP 0 4185 #define CTA_EXT_DB_VENDOR 1 4186 #define CTA_EXT_DB_HDR_STATIC_METADATA 6 4187 #define CTA_EXT_DB_420_VIDEO_DATA 14 4188 #define CTA_EXT_DB_420_VIDEO_CAP_MAP 15 4189 #define CTA_EXT_DB_HF_EEODB 0x78 4190 #define CTA_EXT_DB_HF_SCDB 0x79 4191 4192 #define EDID_BASIC_AUDIO (1 << 6) 4193 #define EDID_CEA_YCRCB444 (1 << 5) 4194 #define EDID_CEA_YCRCB422 (1 << 4) 4195 #define EDID_CEA_VCDB_QS (1 << 6) 4196 4197 /* 4198 * Search EDID for CEA extension block. 4199 * 4200 * FIXME: Prefer not returning pointers to raw EDID data. 4201 */ 4202 const u8 *drm_edid_find_extension(const struct drm_edid *drm_edid, 4203 int ext_id, int *ext_index) 4204 { 4205 const u8 *edid_ext = NULL; 4206 int i; 4207 4208 /* No EDID or EDID extensions */ 4209 if (!drm_edid || !drm_edid_extension_block_count(drm_edid)) 4210 return NULL; 4211 4212 /* Find CEA extension */ 4213 for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) { 4214 edid_ext = drm_edid_extension_block_data(drm_edid, i); 4215 if (edid_block_tag(edid_ext) == ext_id) 4216 break; 4217 } 4218 4219 if (i >= drm_edid_extension_block_count(drm_edid)) 4220 return NULL; 4221 4222 *ext_index = i + 1; 4223 4224 return edid_ext; 4225 } 4226 4227 /* Return true if the EDID has a CTA extension or a DisplayID CTA data block */ 4228 static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid) 4229 { 4230 const struct displayid_block *block; 4231 struct displayid_iter iter; 4232 struct drm_edid_iter edid_iter; 4233 const u8 *ext; 4234 bool found = false; 4235 4236 /* Look for a top level CEA extension block */ 4237 drm_edid_iter_begin(drm_edid, &edid_iter); 4238 drm_edid_iter_for_each(ext, &edid_iter) { 4239 if (ext[0] == CEA_EXT) { 4240 found = true; 4241 break; 4242 } 4243 } 4244 drm_edid_iter_end(&edid_iter); 4245 4246 if (found) 4247 return true; 4248 4249 /* CEA blocks can also be found embedded in a DisplayID block */ 4250 displayid_iter_edid_begin(drm_edid, &iter); 4251 displayid_iter_for_each(block, &iter) { 4252 if (block->tag == DATA_BLOCK_CTA) { 4253 found = true; 4254 break; 4255 } 4256 } 4257 displayid_iter_end(&iter); 4258 4259 return found; 4260 } 4261 4262 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic) 4263 { 4264 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127); 4265 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219); 4266 4267 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1)) 4268 return &edid_cea_modes_1[vic - 1]; 4269 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193)) 4270 return &edid_cea_modes_193[vic - 193]; 4271 return NULL; 4272 } 4273 4274 static u8 cea_num_vics(void) 4275 { 4276 return 193 + ARRAY_SIZE(edid_cea_modes_193); 4277 } 4278 4279 static u8 cea_next_vic(u8 vic) 4280 { 4281 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1)) 4282 vic = 193; 4283 return vic; 4284 } 4285 4286 /* 4287 * Calculate the alternate clock for the CEA mode 4288 * (60Hz vs. 59.94Hz etc.) 4289 */ 4290 static unsigned int 4291 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 4292 { 4293 unsigned int clock = cea_mode->clock; 4294 4295 if (drm_mode_vrefresh(cea_mode) % 6 != 0) 4296 return clock; 4297 4298 /* 4299 * edid_cea_modes contains the 59.94Hz 4300 * variant for 240 and 480 line modes, 4301 * and the 60Hz variant otherwise. 4302 */ 4303 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 4304 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 4305 else 4306 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 4307 4308 return clock; 4309 } 4310 4311 static bool 4312 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 4313 { 4314 /* 4315 * For certain VICs the spec allows the vertical 4316 * front porch to vary by one or two lines. 4317 * 4318 * cea_modes[] stores the variant with the shortest 4319 * vertical front porch. We can adjust the mode to 4320 * get the other variants by simply increasing the 4321 * vertical front porch length. 4322 */ 4323 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 || 4324 cea_mode_for_vic(9)->vtotal != 262 || 4325 cea_mode_for_vic(12)->vtotal != 262 || 4326 cea_mode_for_vic(13)->vtotal != 262 || 4327 cea_mode_for_vic(23)->vtotal != 312 || 4328 cea_mode_for_vic(24)->vtotal != 312 || 4329 cea_mode_for_vic(27)->vtotal != 312 || 4330 cea_mode_for_vic(28)->vtotal != 312); 4331 4332 if (((vic == 8 || vic == 9 || 4333 vic == 12 || vic == 13) && mode->vtotal < 263) || 4334 ((vic == 23 || vic == 24 || 4335 vic == 27 || vic == 28) && mode->vtotal < 314)) { 4336 mode->vsync_start++; 4337 mode->vsync_end++; 4338 mode->vtotal++; 4339 4340 return true; 4341 } 4342 4343 return false; 4344 } 4345 4346 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 4347 unsigned int clock_tolerance) 4348 { 4349 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4350 u8 vic; 4351 4352 if (!to_match->clock) 4353 return 0; 4354 4355 if (to_match->picture_aspect_ratio) 4356 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4357 4358 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 4359 struct drm_display_mode cea_mode; 4360 unsigned int clock1, clock2; 4361 4362 drm_mode_init(&cea_mode, cea_mode_for_vic(vic)); 4363 4364 /* Check both 60Hz and 59.94Hz */ 4365 clock1 = cea_mode.clock; 4366 clock2 = cea_mode_alternate_clock(&cea_mode); 4367 4368 if (abs(to_match->clock - clock1) > clock_tolerance && 4369 abs(to_match->clock - clock2) > clock_tolerance) 4370 continue; 4371 4372 do { 4373 if (drm_mode_match(to_match, &cea_mode, match_flags)) 4374 return vic; 4375 } while (cea_mode_alternate_timings(vic, &cea_mode)); 4376 } 4377 4378 return 0; 4379 } 4380 4381 /** 4382 * drm_match_cea_mode - look for a CEA mode matching given mode 4383 * @to_match: display mode 4384 * 4385 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 4386 * mode. 4387 */ 4388 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 4389 { 4390 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4391 u8 vic; 4392 4393 if (!to_match->clock) 4394 return 0; 4395 4396 if (to_match->picture_aspect_ratio) 4397 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4398 4399 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 4400 struct drm_display_mode cea_mode; 4401 unsigned int clock1, clock2; 4402 4403 drm_mode_init(&cea_mode, cea_mode_for_vic(vic)); 4404 4405 /* Check both 60Hz and 59.94Hz */ 4406 clock1 = cea_mode.clock; 4407 clock2 = cea_mode_alternate_clock(&cea_mode); 4408 4409 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 4410 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 4411 continue; 4412 4413 do { 4414 if (drm_mode_match(to_match, &cea_mode, match_flags)) 4415 return vic; 4416 } while (cea_mode_alternate_timings(vic, &cea_mode)); 4417 } 4418 4419 return 0; 4420 } 4421 EXPORT_SYMBOL(drm_match_cea_mode); 4422 4423 static bool drm_valid_cea_vic(u8 vic) 4424 { 4425 return cea_mode_for_vic(vic) != NULL; 4426 } 4427 4428 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 4429 { 4430 const struct drm_display_mode *mode = cea_mode_for_vic(video_code); 4431 4432 if (mode) 4433 return mode->picture_aspect_ratio; 4434 4435 return HDMI_PICTURE_ASPECT_NONE; 4436 } 4437 4438 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code) 4439 { 4440 return edid_4k_modes[video_code].picture_aspect_ratio; 4441 } 4442 4443 /* 4444 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 4445 * specific block). 4446 */ 4447 static unsigned int 4448 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 4449 { 4450 return cea_mode_alternate_clock(hdmi_mode); 4451 } 4452 4453 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 4454 unsigned int clock_tolerance) 4455 { 4456 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4457 u8 vic; 4458 4459 if (!to_match->clock) 4460 return 0; 4461 4462 if (to_match->picture_aspect_ratio) 4463 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4464 4465 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4466 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4467 unsigned int clock1, clock2; 4468 4469 /* Make sure to also match alternate clocks */ 4470 clock1 = hdmi_mode->clock; 4471 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4472 4473 if (abs(to_match->clock - clock1) > clock_tolerance && 4474 abs(to_match->clock - clock2) > clock_tolerance) 4475 continue; 4476 4477 if (drm_mode_match(to_match, hdmi_mode, match_flags)) 4478 return vic; 4479 } 4480 4481 return 0; 4482 } 4483 4484 /* 4485 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 4486 * @to_match: display mode 4487 * 4488 * An HDMI mode is one defined in the HDMI vendor specific block. 4489 * 4490 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 4491 */ 4492 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 4493 { 4494 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4495 u8 vic; 4496 4497 if (!to_match->clock) 4498 return 0; 4499 4500 if (to_match->picture_aspect_ratio) 4501 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4502 4503 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4504 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4505 unsigned int clock1, clock2; 4506 4507 /* Make sure to also match alternate clocks */ 4508 clock1 = hdmi_mode->clock; 4509 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4510 4511 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 4512 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 4513 drm_mode_match(to_match, hdmi_mode, match_flags)) 4514 return vic; 4515 } 4516 return 0; 4517 } 4518 4519 static bool drm_valid_hdmi_vic(u8 vic) 4520 { 4521 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 4522 } 4523 4524 static int add_alternate_cea_modes(struct drm_connector *connector, 4525 const struct drm_edid *drm_edid) 4526 { 4527 struct drm_device *dev = connector->dev; 4528 struct drm_display_mode *mode, *tmp; 4529 LIST_HEAD(list); 4530 int modes = 0; 4531 4532 /* Don't add CTA modes if the CTA extension block is missing */ 4533 if (!drm_edid_has_cta_extension(drm_edid)) 4534 return 0; 4535 4536 /* 4537 * Go through all probed modes and create a new mode 4538 * with the alternate clock for certain CEA modes. 4539 */ 4540 list_for_each_entry(mode, &connector->probed_modes, head) { 4541 const struct drm_display_mode *cea_mode = NULL; 4542 struct drm_display_mode *newmode; 4543 u8 vic = drm_match_cea_mode(mode); 4544 unsigned int clock1, clock2; 4545 4546 if (drm_valid_cea_vic(vic)) { 4547 cea_mode = cea_mode_for_vic(vic); 4548 clock2 = cea_mode_alternate_clock(cea_mode); 4549 } else { 4550 vic = drm_match_hdmi_mode(mode); 4551 if (drm_valid_hdmi_vic(vic)) { 4552 cea_mode = &edid_4k_modes[vic]; 4553 clock2 = hdmi_mode_alternate_clock(cea_mode); 4554 } 4555 } 4556 4557 if (!cea_mode) 4558 continue; 4559 4560 clock1 = cea_mode->clock; 4561 4562 if (clock1 == clock2) 4563 continue; 4564 4565 if (mode->clock != clock1 && mode->clock != clock2) 4566 continue; 4567 4568 newmode = drm_mode_duplicate(dev, cea_mode); 4569 if (!newmode) 4570 continue; 4571 4572 /* Carry over the stereo flags */ 4573 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 4574 4575 /* 4576 * The current mode could be either variant. Make 4577 * sure to pick the "other" clock for the new mode. 4578 */ 4579 if (mode->clock != clock1) 4580 newmode->clock = clock1; 4581 else 4582 newmode->clock = clock2; 4583 4584 list_add_tail(&newmode->head, &list); 4585 } 4586 4587 list_for_each_entry_safe(mode, tmp, &list, head) { 4588 list_del(&mode->head); 4589 drm_mode_probed_add(connector, mode); 4590 modes++; 4591 } 4592 4593 return modes; 4594 } 4595 4596 static u8 svd_to_vic(u8 svd) 4597 { 4598 /* 0-6 bit vic, 7th bit native mode indicator */ 4599 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 4600 return svd & 127; 4601 4602 return svd; 4603 } 4604 4605 /* 4606 * Return a display mode for the 0-based vic_index'th VIC across all CTA VDBs in 4607 * the EDID, or NULL on errors. 4608 */ 4609 static struct drm_display_mode * 4610 drm_display_mode_from_vic_index(struct drm_connector *connector, int vic_index) 4611 { 4612 const struct drm_display_info *info = &connector->display_info; 4613 struct drm_device *dev = connector->dev; 4614 4615 if (!info->vics || vic_index >= info->vics_len || !info->vics[vic_index]) 4616 return NULL; 4617 4618 return drm_display_mode_from_cea_vic(dev, info->vics[vic_index]); 4619 } 4620 4621 /* 4622 * do_y420vdb_modes - Parse YCBCR 420 only modes 4623 * @connector: connector corresponding to the HDMI sink 4624 * @svds: start of the data block of CEA YCBCR 420 VDB 4625 * @len: length of the CEA YCBCR 420 VDB 4626 * 4627 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 4628 * which contains modes which can be supported in YCBCR 420 4629 * output format only. 4630 */ 4631 static int do_y420vdb_modes(struct drm_connector *connector, 4632 const u8 *svds, u8 svds_len) 4633 { 4634 struct drm_device *dev = connector->dev; 4635 int modes = 0, i; 4636 4637 for (i = 0; i < svds_len; i++) { 4638 u8 vic = svd_to_vic(svds[i]); 4639 struct drm_display_mode *newmode; 4640 4641 if (!drm_valid_cea_vic(vic)) 4642 continue; 4643 4644 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 4645 if (!newmode) 4646 break; 4647 drm_mode_probed_add(connector, newmode); 4648 modes++; 4649 } 4650 4651 return modes; 4652 } 4653 4654 /** 4655 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC 4656 * @dev: DRM device 4657 * @video_code: CEA VIC of the mode 4658 * 4659 * Creates a new mode matching the specified CEA VIC. 4660 * 4661 * Returns: A new drm_display_mode on success or NULL on failure 4662 */ 4663 struct drm_display_mode * 4664 drm_display_mode_from_cea_vic(struct drm_device *dev, 4665 u8 video_code) 4666 { 4667 const struct drm_display_mode *cea_mode; 4668 struct drm_display_mode *newmode; 4669 4670 cea_mode = cea_mode_for_vic(video_code); 4671 if (!cea_mode) 4672 return NULL; 4673 4674 newmode = drm_mode_duplicate(dev, cea_mode); 4675 if (!newmode) 4676 return NULL; 4677 4678 return newmode; 4679 } 4680 EXPORT_SYMBOL(drm_display_mode_from_cea_vic); 4681 4682 /* Add modes based on VICs parsed in parse_cta_vdb() */ 4683 static int add_cta_vdb_modes(struct drm_connector *connector) 4684 { 4685 const struct drm_display_info *info = &connector->display_info; 4686 int i, modes = 0; 4687 4688 if (!info->vics) 4689 return 0; 4690 4691 for (i = 0; i < info->vics_len; i++) { 4692 struct drm_display_mode *mode; 4693 4694 mode = drm_display_mode_from_vic_index(connector, i); 4695 if (mode) { 4696 drm_mode_probed_add(connector, mode); 4697 modes++; 4698 } 4699 } 4700 4701 return modes; 4702 } 4703 4704 struct stereo_mandatory_mode { 4705 int width, height, vrefresh; 4706 unsigned int flags; 4707 }; 4708 4709 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 4710 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4711 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 4712 { 1920, 1080, 50, 4713 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 4714 { 1920, 1080, 60, 4715 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 4716 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4717 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 4718 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4719 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 4720 }; 4721 4722 static bool 4723 stereo_match_mandatory(const struct drm_display_mode *mode, 4724 const struct stereo_mandatory_mode *stereo_mode) 4725 { 4726 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 4727 4728 return mode->hdisplay == stereo_mode->width && 4729 mode->vdisplay == stereo_mode->height && 4730 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 4731 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 4732 } 4733 4734 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 4735 { 4736 struct drm_device *dev = connector->dev; 4737 const struct drm_display_mode *mode; 4738 struct list_head stereo_modes; 4739 int modes = 0, i; 4740 4741 INIT_LIST_HEAD(&stereo_modes); 4742 4743 list_for_each_entry(mode, &connector->probed_modes, head) { 4744 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 4745 const struct stereo_mandatory_mode *mandatory; 4746 struct drm_display_mode *new_mode; 4747 4748 if (!stereo_match_mandatory(mode, 4749 &stereo_mandatory_modes[i])) 4750 continue; 4751 4752 mandatory = &stereo_mandatory_modes[i]; 4753 new_mode = drm_mode_duplicate(dev, mode); 4754 if (!new_mode) 4755 continue; 4756 4757 new_mode->flags |= mandatory->flags; 4758 list_add_tail(&new_mode->head, &stereo_modes); 4759 modes++; 4760 } 4761 } 4762 4763 list_splice_tail(&stereo_modes, &connector->probed_modes); 4764 4765 return modes; 4766 } 4767 4768 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 4769 { 4770 struct drm_device *dev = connector->dev; 4771 struct drm_display_mode *newmode; 4772 4773 if (!drm_valid_hdmi_vic(vic)) { 4774 drm_err(connector->dev, "[CONNECTOR:%d:%s] Unknown HDMI VIC: %d\n", 4775 connector->base.id, connector->name, vic); 4776 return 0; 4777 } 4778 4779 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 4780 if (!newmode) 4781 return 0; 4782 4783 drm_mode_probed_add(connector, newmode); 4784 4785 return 1; 4786 } 4787 4788 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 4789 int vic_index) 4790 { 4791 struct drm_display_mode *newmode; 4792 int modes = 0; 4793 4794 if (structure & (1 << 0)) { 4795 newmode = drm_display_mode_from_vic_index(connector, vic_index); 4796 if (newmode) { 4797 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 4798 drm_mode_probed_add(connector, newmode); 4799 modes++; 4800 } 4801 } 4802 if (structure & (1 << 6)) { 4803 newmode = drm_display_mode_from_vic_index(connector, vic_index); 4804 if (newmode) { 4805 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 4806 drm_mode_probed_add(connector, newmode); 4807 modes++; 4808 } 4809 } 4810 if (structure & (1 << 8)) { 4811 newmode = drm_display_mode_from_vic_index(connector, vic_index); 4812 if (newmode) { 4813 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4814 drm_mode_probed_add(connector, newmode); 4815 modes++; 4816 } 4817 } 4818 4819 return modes; 4820 } 4821 4822 static bool hdmi_vsdb_latency_present(const u8 *db) 4823 { 4824 return db[8] & BIT(7); 4825 } 4826 4827 static bool hdmi_vsdb_i_latency_present(const u8 *db) 4828 { 4829 return hdmi_vsdb_latency_present(db) && db[8] & BIT(6); 4830 } 4831 4832 static int hdmi_vsdb_latency_length(const u8 *db) 4833 { 4834 if (hdmi_vsdb_i_latency_present(db)) 4835 return 4; 4836 else if (hdmi_vsdb_latency_present(db)) 4837 return 2; 4838 else 4839 return 0; 4840 } 4841 4842 /* 4843 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 4844 * @connector: connector corresponding to the HDMI sink 4845 * @db: start of the CEA vendor specific block 4846 * @len: length of the CEA block payload, ie. one can access up to db[len] 4847 * 4848 * Parses the HDMI VSDB looking for modes to add to @connector. This function 4849 * also adds the stereo 3d modes when applicable. 4850 */ 4851 static int 4852 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len) 4853 { 4854 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 4855 u8 vic_len, hdmi_3d_len = 0; 4856 u16 mask; 4857 u16 structure_all; 4858 4859 if (len < 8) 4860 goto out; 4861 4862 /* no HDMI_Video_Present */ 4863 if (!(db[8] & (1 << 5))) 4864 goto out; 4865 4866 offset += hdmi_vsdb_latency_length(db); 4867 4868 /* the declared length is not long enough for the 2 first bytes 4869 * of additional video format capabilities */ 4870 if (len < (8 + offset + 2)) 4871 goto out; 4872 4873 /* 3D_Present */ 4874 offset++; 4875 if (db[8 + offset] & (1 << 7)) { 4876 modes += add_hdmi_mandatory_stereo_modes(connector); 4877 4878 /* 3D_Multi_present */ 4879 multi_present = (db[8 + offset] & 0x60) >> 5; 4880 } 4881 4882 offset++; 4883 vic_len = db[8 + offset] >> 5; 4884 hdmi_3d_len = db[8 + offset] & 0x1f; 4885 4886 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 4887 u8 vic; 4888 4889 vic = db[9 + offset + i]; 4890 modes += add_hdmi_mode(connector, vic); 4891 } 4892 offset += 1 + vic_len; 4893 4894 if (multi_present == 1) 4895 multi_len = 2; 4896 else if (multi_present == 2) 4897 multi_len = 4; 4898 else 4899 multi_len = 0; 4900 4901 if (len < (8 + offset + hdmi_3d_len - 1)) 4902 goto out; 4903 4904 if (hdmi_3d_len < multi_len) 4905 goto out; 4906 4907 if (multi_present == 1 || multi_present == 2) { 4908 /* 3D_Structure_ALL */ 4909 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 4910 4911 /* check if 3D_MASK is present */ 4912 if (multi_present == 2) 4913 mask = (db[10 + offset] << 8) | db[11 + offset]; 4914 else 4915 mask = 0xffff; 4916 4917 for (i = 0; i < 16; i++) { 4918 if (mask & (1 << i)) 4919 modes += add_3d_struct_modes(connector, 4920 structure_all, i); 4921 } 4922 } 4923 4924 offset += multi_len; 4925 4926 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 4927 int vic_index; 4928 struct drm_display_mode *newmode = NULL; 4929 unsigned int newflag = 0; 4930 bool detail_present; 4931 4932 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 4933 4934 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 4935 break; 4936 4937 /* 2D_VIC_order_X */ 4938 vic_index = db[8 + offset + i] >> 4; 4939 4940 /* 3D_Structure_X */ 4941 switch (db[8 + offset + i] & 0x0f) { 4942 case 0: 4943 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 4944 break; 4945 case 6: 4946 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 4947 break; 4948 case 8: 4949 /* 3D_Detail_X */ 4950 if ((db[9 + offset + i] >> 4) == 1) 4951 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4952 break; 4953 } 4954 4955 if (newflag != 0) { 4956 newmode = drm_display_mode_from_vic_index(connector, 4957 vic_index); 4958 4959 if (newmode) { 4960 newmode->flags |= newflag; 4961 drm_mode_probed_add(connector, newmode); 4962 modes++; 4963 } 4964 } 4965 4966 if (detail_present) 4967 i++; 4968 } 4969 4970 out: 4971 return modes; 4972 } 4973 4974 static int 4975 cea_revision(const u8 *cea) 4976 { 4977 /* 4978 * FIXME is this correct for the DispID variant? 4979 * The DispID spec doesn't really specify whether 4980 * this is the revision of the CEA extension or 4981 * the DispID CEA data block. And the only value 4982 * given as an example is 0. 4983 */ 4984 return cea[1]; 4985 } 4986 4987 /* 4988 * CTA Data Block iterator. 4989 * 4990 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID 4991 * CTA Data Blocks. 4992 * 4993 * struct cea_db *db: 4994 * struct cea_db_iter iter; 4995 * 4996 * cea_db_iter_edid_begin(edid, &iter); 4997 * cea_db_iter_for_each(db, &iter) { 4998 * // do stuff with db 4999 * } 5000 * cea_db_iter_end(&iter); 5001 */ 5002 struct cea_db_iter { 5003 struct drm_edid_iter edid_iter; 5004 struct displayid_iter displayid_iter; 5005 5006 /* Current Data Block Collection. */ 5007 const u8 *collection; 5008 5009 /* Current Data Block index in current collection. */ 5010 int index; 5011 5012 /* End index in current collection. */ 5013 int end; 5014 }; 5015 5016 /* CTA-861-H section 7.4 CTA Data BLock Collection */ 5017 struct cea_db { 5018 u8 tag_length; 5019 u8 data[]; 5020 } __packed; 5021 5022 static int cea_db_tag(const struct cea_db *db) 5023 { 5024 return db->tag_length >> 5; 5025 } 5026 5027 static int cea_db_payload_len(const void *_db) 5028 { 5029 /* FIXME: Transition to passing struct cea_db * everywhere. */ 5030 const struct cea_db *db = _db; 5031 5032 return db->tag_length & 0x1f; 5033 } 5034 5035 static const void *cea_db_data(const struct cea_db *db) 5036 { 5037 return db->data; 5038 } 5039 5040 static bool cea_db_is_extended_tag(const struct cea_db *db, int tag) 5041 { 5042 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG && 5043 cea_db_payload_len(db) >= 1 && 5044 db->data[0] == tag; 5045 } 5046 5047 static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui) 5048 { 5049 const u8 *data = cea_db_data(db); 5050 5051 return cea_db_tag(db) == CTA_DB_VENDOR && 5052 cea_db_payload_len(db) >= 3 && 5053 oui(data[2], data[1], data[0]) == vendor_oui; 5054 } 5055 5056 static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid, 5057 struct cea_db_iter *iter) 5058 { 5059 memset(iter, 0, sizeof(*iter)); 5060 5061 drm_edid_iter_begin(drm_edid, &iter->edid_iter); 5062 displayid_iter_edid_begin(drm_edid, &iter->displayid_iter); 5063 } 5064 5065 static const struct cea_db * 5066 __cea_db_iter_current_block(const struct cea_db_iter *iter) 5067 { 5068 const struct cea_db *db; 5069 5070 if (!iter->collection) 5071 return NULL; 5072 5073 db = (const struct cea_db *)&iter->collection[iter->index]; 5074 5075 if (iter->index + sizeof(*db) <= iter->end && 5076 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end) 5077 return db; 5078 5079 return NULL; 5080 } 5081 5082 /* 5083 * References: 5084 * - CTA-861-H section 7.3.3 CTA Extension Version 3 5085 */ 5086 static int cea_db_collection_size(const u8 *cta) 5087 { 5088 u8 d = cta[2]; 5089 5090 if (d < 4 || d > 127) 5091 return 0; 5092 5093 return d - 4; 5094 } 5095 5096 /* 5097 * References: 5098 * - VESA E-EDID v1.4 5099 * - CTA-861-H section 7.3.3 CTA Extension Version 3 5100 */ 5101 static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter) 5102 { 5103 const u8 *ext; 5104 5105 drm_edid_iter_for_each(ext, &iter->edid_iter) { 5106 int size; 5107 5108 /* Only support CTA Extension revision 3+ */ 5109 if (ext[0] != CEA_EXT || cea_revision(ext) < 3) 5110 continue; 5111 5112 size = cea_db_collection_size(ext); 5113 if (!size) 5114 continue; 5115 5116 iter->index = 4; 5117 iter->end = iter->index + size; 5118 5119 return ext; 5120 } 5121 5122 return NULL; 5123 } 5124 5125 /* 5126 * References: 5127 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block 5128 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block 5129 * 5130 * Note that the above do not specify any connection between DisplayID Data 5131 * Block revision and CTA Extension versions. 5132 */ 5133 static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter) 5134 { 5135 const struct displayid_block *block; 5136 5137 displayid_iter_for_each(block, &iter->displayid_iter) { 5138 if (block->tag != DATA_BLOCK_CTA) 5139 continue; 5140 5141 /* 5142 * The displayid iterator has already verified the block bounds 5143 * in displayid_iter_block(). 5144 */ 5145 iter->index = sizeof(*block); 5146 iter->end = iter->index + block->num_bytes; 5147 5148 return block; 5149 } 5150 5151 return NULL; 5152 } 5153 5154 static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter) 5155 { 5156 const struct cea_db *db; 5157 5158 if (iter->collection) { 5159 /* Current collection should always be valid. */ 5160 db = __cea_db_iter_current_block(iter); 5161 if (WARN_ON(!db)) { 5162 iter->collection = NULL; 5163 return NULL; 5164 } 5165 5166 /* Next block in CTA Data Block Collection */ 5167 iter->index += sizeof(*db) + cea_db_payload_len(db); 5168 5169 db = __cea_db_iter_current_block(iter); 5170 if (db) 5171 return db; 5172 } 5173 5174 for (;;) { 5175 /* 5176 * Find the next CTA Data Block Collection. First iterate all 5177 * the EDID CTA Extensions, then all the DisplayID CTA blocks. 5178 * 5179 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID 5180 * Extension, it's recommended that DisplayID extensions are 5181 * exposed after all of the CTA Extensions. 5182 */ 5183 iter->collection = __cea_db_iter_edid_next(iter); 5184 if (!iter->collection) 5185 iter->collection = __cea_db_iter_displayid_next(iter); 5186 5187 if (!iter->collection) 5188 return NULL; 5189 5190 db = __cea_db_iter_current_block(iter); 5191 if (db) 5192 return db; 5193 } 5194 } 5195 5196 #define cea_db_iter_for_each(__db, __iter) \ 5197 while (((__db) = __cea_db_iter_next(__iter))) 5198 5199 static void cea_db_iter_end(struct cea_db_iter *iter) 5200 { 5201 displayid_iter_end(&iter->displayid_iter); 5202 drm_edid_iter_end(&iter->edid_iter); 5203 5204 memset(iter, 0, sizeof(*iter)); 5205 } 5206 5207 static bool cea_db_is_hdmi_vsdb(const struct cea_db *db) 5208 { 5209 return cea_db_is_vendor(db, HDMI_IEEE_OUI) && 5210 cea_db_payload_len(db) >= 5; 5211 } 5212 5213 static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db) 5214 { 5215 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) && 5216 cea_db_payload_len(db) >= 7; 5217 } 5218 5219 static bool cea_db_is_hdmi_forum_eeodb(const void *db) 5220 { 5221 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) && 5222 cea_db_payload_len(db) >= 2; 5223 } 5224 5225 static bool cea_db_is_microsoft_vsdb(const struct cea_db *db) 5226 { 5227 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) && 5228 cea_db_payload_len(db) == 21; 5229 } 5230 5231 static bool cea_db_is_amd_vsdb(const struct cea_db *db) 5232 { 5233 return cea_db_is_vendor(db, AMD_IEEE_OUI) && 5234 cea_db_payload_len(db) >= AMD_VSDB_V3_PAYLOAD_MIN_LEN && 5235 cea_db_payload_len(db) <= AMD_VSDB_V3_PAYLOAD_MAX_LEN; 5236 } 5237 5238 static bool cea_db_is_vcdb(const struct cea_db *db) 5239 { 5240 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) && 5241 cea_db_payload_len(db) == 2; 5242 } 5243 5244 static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db) 5245 { 5246 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) && 5247 cea_db_payload_len(db) >= 7; 5248 } 5249 5250 static bool cea_db_is_y420cmdb(const struct cea_db *db) 5251 { 5252 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP); 5253 } 5254 5255 static bool cea_db_is_y420vdb(const struct cea_db *db) 5256 { 5257 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA); 5258 } 5259 5260 static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db) 5261 { 5262 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) && 5263 cea_db_payload_len(db) >= 3; 5264 } 5265 5266 /* 5267 * Get the HF-EEODB override extension block count from EDID. 5268 * 5269 * The passed in EDID may be partially read, as long as it has at least two 5270 * blocks (base block and one extension block) if EDID extension count is > 0. 5271 * 5272 * Note that this is *not* how you should parse CTA Data Blocks in general; this 5273 * is only to handle partially read EDIDs. Normally, use the CTA Data Block 5274 * iterators instead. 5275 * 5276 * References: 5277 * - HDMI 2.1 section 10.3.6 HDMI Forum EDID Extension Override Data Block 5278 */ 5279 static int edid_hfeeodb_extension_block_count(const struct edid *edid) 5280 { 5281 const u8 *cta; 5282 5283 /* No extensions according to base block, no HF-EEODB. */ 5284 if (!edid_extension_block_count(edid)) 5285 return 0; 5286 5287 /* HF-EEODB is always in the first EDID extension block only */ 5288 cta = edid_extension_block_data(edid, 0); 5289 if (edid_block_tag(cta) != CEA_EXT || cea_revision(cta) < 3) 5290 return 0; 5291 5292 /* Need to have the data block collection, and at least 3 bytes. */ 5293 if (cea_db_collection_size(cta) < 3) 5294 return 0; 5295 5296 /* 5297 * Sinks that include the HF-EEODB in their E-EDID shall include one and 5298 * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4 5299 * through 6 of Block 1 of the E-EDID. 5300 */ 5301 if (!cea_db_is_hdmi_forum_eeodb(&cta[4])) 5302 return 0; 5303 5304 return cta[4 + 2]; 5305 } 5306 5307 /* 5308 * CTA-861 YCbCr 4:2:0 Capability Map Data Block (CTA Y420CMDB) 5309 * 5310 * Y420CMDB contains a bitmap which gives the index of CTA modes from CTA VDB, 5311 * which can support YCBCR 420 sampling output also (apart from RGB/YCBCR444 5312 * etc). For example, if the bit 0 in bitmap is set, first mode in VDB can 5313 * support YCBCR420 output too. 5314 */ 5315 static void parse_cta_y420cmdb(struct drm_connector *connector, 5316 const struct cea_db *db, u64 *y420cmdb_map) 5317 { 5318 struct drm_display_info *info = &connector->display_info; 5319 int i, map_len = cea_db_payload_len(db) - 1; 5320 const u8 *data = cea_db_data(db) + 1; 5321 u64 map = 0; 5322 5323 if (map_len == 0) { 5324 /* All CEA modes support ycbcr420 sampling also.*/ 5325 map = U64_MAX; 5326 goto out; 5327 } 5328 5329 /* 5330 * This map indicates which of the existing CEA block modes 5331 * from VDB can support YCBCR420 output too. So if bit=0 is 5332 * set, first mode from VDB can support YCBCR420 output too. 5333 * We will parse and keep this map, before parsing VDB itself 5334 * to avoid going through the same block again and again. 5335 * 5336 * Spec is not clear about max possible size of this block. 5337 * Clamping max bitmap block size at 8 bytes. Every byte can 5338 * address 8 CEA modes, in this way this map can address 5339 * 8*8 = first 64 SVDs. 5340 */ 5341 if (WARN_ON_ONCE(map_len > 8)) 5342 map_len = 8; 5343 5344 for (i = 0; i < map_len; i++) 5345 map |= (u64)data[i] << (8 * i); 5346 5347 out: 5348 if (map) 5349 info->color_formats |= BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR420); 5350 5351 *y420cmdb_map = map; 5352 } 5353 5354 static int add_cea_modes(struct drm_connector *connector, 5355 const struct drm_edid *drm_edid) 5356 { 5357 const struct cea_db *db; 5358 struct cea_db_iter iter; 5359 int modes; 5360 5361 /* CTA VDB block VICs parsed earlier */ 5362 modes = add_cta_vdb_modes(connector); 5363 5364 cea_db_iter_edid_begin(drm_edid, &iter); 5365 cea_db_iter_for_each(db, &iter) { 5366 if (cea_db_is_hdmi_vsdb(db)) { 5367 modes += do_hdmi_vsdb_modes(connector, (const u8 *)db, 5368 cea_db_payload_len(db)); 5369 } else if (cea_db_is_y420vdb(db)) { 5370 const u8 *vdb420 = cea_db_data(db) + 1; 5371 5372 /* Add 4:2:0(only) modes present in EDID */ 5373 modes += do_y420vdb_modes(connector, vdb420, 5374 cea_db_payload_len(db) - 1); 5375 } 5376 } 5377 cea_db_iter_end(&iter); 5378 5379 return modes; 5380 } 5381 5382 static void fixup_detailed_cea_mode_clock(struct drm_connector *connector, 5383 struct drm_display_mode *mode) 5384 { 5385 const struct drm_display_mode *cea_mode; 5386 int clock1, clock2, clock; 5387 u8 vic; 5388 const char *type; 5389 5390 /* 5391 * allow 5kHz clock difference either way to account for 5392 * the 10kHz clock resolution limit of detailed timings. 5393 */ 5394 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 5395 if (drm_valid_cea_vic(vic)) { 5396 type = "CEA"; 5397 cea_mode = cea_mode_for_vic(vic); 5398 clock1 = cea_mode->clock; 5399 clock2 = cea_mode_alternate_clock(cea_mode); 5400 } else { 5401 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 5402 if (drm_valid_hdmi_vic(vic)) { 5403 type = "HDMI"; 5404 cea_mode = &edid_4k_modes[vic]; 5405 clock1 = cea_mode->clock; 5406 clock2 = hdmi_mode_alternate_clock(cea_mode); 5407 } else { 5408 return; 5409 } 5410 } 5411 5412 /* pick whichever is closest */ 5413 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 5414 clock = clock1; 5415 else 5416 clock = clock2; 5417 5418 if (mode->clock == clock) 5419 return; 5420 5421 drm_dbg_kms(connector->dev, 5422 "[CONNECTOR:%d:%s] detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 5423 connector->base.id, connector->name, 5424 type, vic, mode->clock, clock); 5425 mode->clock = clock; 5426 } 5427 5428 static void drm_calculate_luminance_range(struct drm_connector *connector) 5429 { 5430 const struct hdr_static_metadata *hdr_metadata = 5431 &connector->display_info.hdr_sink_metadata.hdmi_type1; 5432 struct drm_luminance_range_info *luminance_range = 5433 &connector->display_info.luminance_range; 5434 static const u8 pre_computed_values[] = { 5435 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69, 5436 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98 5437 }; 5438 u32 max_avg, min_cll, max, min, q, r; 5439 5440 if (!(hdr_metadata->metadata_type & BIT(HDMI_STATIC_METADATA_TYPE1))) 5441 return; 5442 5443 max_avg = hdr_metadata->max_fall; 5444 min_cll = hdr_metadata->min_cll; 5445 5446 /* 5447 * From the specification (CTA-861-G), for calculating the maximum 5448 * luminance we need to use: 5449 * Luminance = 50*2**(CV/32) 5450 * Where CV is a one-byte value. 5451 * For calculating this expression we may need float point precision; 5452 * to avoid this complexity level, we take advantage that CV is divided 5453 * by a constant. From the Euclids division algorithm, we know that CV 5454 * can be written as: CV = 32*q + r. Next, we replace CV in the 5455 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just 5456 * need to pre-compute the value of r/32. For pre-computing the values 5457 * We just used the following Ruby line: 5458 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round} 5459 * The results of the above expressions can be verified at 5460 * pre_computed_values. 5461 */ 5462 q = max_avg >> 5; 5463 r = max_avg % 32; 5464 max = (1 << q) * pre_computed_values[r]; 5465 5466 /* min luminance: maxLum * (CV/255)^2 / 100 */ 5467 q = DIV_ROUND_CLOSEST(min_cll, 255); 5468 min = max * DIV_ROUND_CLOSEST((q * q), 100); 5469 5470 luminance_range->min_luminance = min; 5471 luminance_range->max_luminance = max; 5472 } 5473 5474 static uint8_t eotf_supported(const u8 *edid_ext) 5475 { 5476 return edid_ext[2] & 5477 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) | 5478 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) | 5479 BIT(HDMI_EOTF_SMPTE_ST2084) | 5480 BIT(HDMI_EOTF_BT_2100_HLG)); 5481 } 5482 5483 static uint8_t hdr_metadata_type(const u8 *edid_ext) 5484 { 5485 return edid_ext[3] & 5486 BIT(HDMI_STATIC_METADATA_TYPE1); 5487 } 5488 5489 static void 5490 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db) 5491 { 5492 struct hdr_static_metadata *hdr_metadata = 5493 &connector->display_info.hdr_sink_metadata.hdmi_type1; 5494 u16 len; 5495 5496 len = cea_db_payload_len(db); 5497 5498 hdr_metadata->eotf = eotf_supported(db); 5499 hdr_metadata->metadata_type = hdr_metadata_type(db); 5500 5501 if (len >= 4) 5502 hdr_metadata->max_cll = db[4]; 5503 if (len >= 5) 5504 hdr_metadata->max_fall = db[5]; 5505 if (len >= 6) { 5506 hdr_metadata->min_cll = db[6]; 5507 5508 /* Calculate only when all values are available */ 5509 drm_calculate_luminance_range(connector); 5510 } 5511 } 5512 5513 /* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */ 5514 static void 5515 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 5516 { 5517 u8 len = cea_db_payload_len(db); 5518 5519 if (len >= 6 && (db[6] & (1 << 7))) 5520 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI; 5521 5522 if (len >= 10 && hdmi_vsdb_latency_present(db)) { 5523 connector->latency_present[0] = true; 5524 connector->video_latency[0] = db[9]; 5525 connector->audio_latency[0] = db[10]; 5526 } 5527 5528 if (len >= 12 && hdmi_vsdb_i_latency_present(db)) { 5529 connector->latency_present[1] = true; 5530 connector->video_latency[1] = db[11]; 5531 connector->audio_latency[1] = db[12]; 5532 } 5533 5534 drm_dbg_kms(connector->dev, 5535 "[CONNECTOR:%d:%s] HDMI: latency present %d %d, video latency %d %d, audio latency %d %d\n", 5536 connector->base.id, connector->name, 5537 connector->latency_present[0], connector->latency_present[1], 5538 connector->video_latency[0], connector->video_latency[1], 5539 connector->audio_latency[0], connector->audio_latency[1]); 5540 } 5541 5542 static void 5543 match_identity(const struct detailed_timing *timing, void *data) 5544 { 5545 struct drm_edid_match_closure *closure = data; 5546 unsigned int i; 5547 const char *name = closure->ident->name; 5548 unsigned int name_len = strlen(name); 5549 const char *desc = timing->data.other_data.data.str.str; 5550 unsigned int desc_len = ARRAY_SIZE(timing->data.other_data.data.str.str); 5551 5552 if (name_len > desc_len || 5553 !(is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME) || 5554 is_display_descriptor(timing, EDID_DETAIL_MONITOR_STRING))) 5555 return; 5556 5557 if (strncmp(name, desc, name_len)) 5558 return; 5559 5560 for (i = name_len; i < desc_len; i++) { 5561 if (desc[i] == '\n') 5562 break; 5563 /* Allow white space before EDID string terminator. */ 5564 if (!isspace(desc[i])) 5565 return; 5566 } 5567 5568 closure->matched = true; 5569 } 5570 5571 /** 5572 * drm_edid_match - match drm_edid with given identity 5573 * @drm_edid: EDID 5574 * @ident: the EDID identity to match with 5575 * 5576 * Check if the EDID matches with the given identity. 5577 * 5578 * Return: True if the given identity matched with EDID, false otherwise. 5579 */ 5580 bool drm_edid_match(const struct drm_edid *drm_edid, 5581 const struct drm_edid_ident *ident) 5582 { 5583 if (!drm_edid || drm_edid_get_panel_id(drm_edid) != ident->panel_id) 5584 return false; 5585 5586 /* Match with name only if it's not NULL. */ 5587 if (ident->name) { 5588 struct drm_edid_match_closure closure = { 5589 .ident = ident, 5590 .matched = false, 5591 }; 5592 5593 drm_for_each_detailed_block(drm_edid, match_identity, &closure); 5594 5595 return closure.matched; 5596 } 5597 5598 return true; 5599 } 5600 EXPORT_SYMBOL(drm_edid_match); 5601 5602 static void 5603 monitor_name(const struct detailed_timing *timing, void *data) 5604 { 5605 const char **res = data; 5606 5607 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME)) 5608 return; 5609 5610 *res = timing->data.other_data.data.str.str; 5611 } 5612 5613 static int get_monitor_name(const struct drm_edid *drm_edid, char name[13]) 5614 { 5615 const char *edid_name = NULL; 5616 int mnl; 5617 5618 if (!drm_edid || !name) 5619 return 0; 5620 5621 drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name); 5622 for (mnl = 0; edid_name && mnl < 13; mnl++) { 5623 if (edid_name[mnl] == 0x0a) 5624 break; 5625 5626 name[mnl] = edid_name[mnl]; 5627 } 5628 5629 return mnl; 5630 } 5631 5632 /** 5633 * drm_edid_get_monitor_name - fetch the monitor name from the edid 5634 * @edid: monitor EDID information 5635 * @name: pointer to a character array to hold the name of the monitor 5636 * @bufsize: The size of the name buffer (should be at least 14 chars.) 5637 * 5638 */ 5639 void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize) 5640 { 5641 int name_length = 0; 5642 5643 if (bufsize <= 0) 5644 return; 5645 5646 if (edid) { 5647 char buf[13]; 5648 struct drm_edid drm_edid = { 5649 .edid = edid, 5650 .size = edid_size(edid), 5651 }; 5652 5653 name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1); 5654 memcpy(name, buf, name_length); 5655 } 5656 5657 name[name_length] = '\0'; 5658 } 5659 EXPORT_SYMBOL(drm_edid_get_monitor_name); 5660 5661 static void clear_eld(struct drm_connector *connector) 5662 { 5663 mutex_lock(&connector->eld_mutex); 5664 memset(connector->eld, 0, sizeof(connector->eld)); 5665 mutex_unlock(&connector->eld_mutex); 5666 5667 connector->latency_present[0] = false; 5668 connector->latency_present[1] = false; 5669 connector->video_latency[0] = 0; 5670 connector->audio_latency[0] = 0; 5671 connector->video_latency[1] = 0; 5672 connector->audio_latency[1] = 0; 5673 } 5674 5675 /* 5676 * Get 3-byte SAD buffer from struct cea_sad. 5677 */ 5678 void drm_edid_cta_sad_get(const struct cea_sad *cta_sad, u8 *sad) 5679 { 5680 sad[0] = cta_sad->format << 3 | cta_sad->channels; 5681 sad[1] = cta_sad->freq; 5682 sad[2] = cta_sad->byte2; 5683 } 5684 5685 /* 5686 * Set struct cea_sad from 3-byte SAD buffer. 5687 */ 5688 void drm_edid_cta_sad_set(struct cea_sad *cta_sad, const u8 *sad) 5689 { 5690 cta_sad->format = (sad[0] & 0x78) >> 3; 5691 cta_sad->channels = sad[0] & 0x07; 5692 cta_sad->freq = sad[1] & 0x7f; 5693 cta_sad->byte2 = sad[2]; 5694 } 5695 5696 /* 5697 * drm_edid_to_eld - build ELD from EDID 5698 * @connector: connector corresponding to the HDMI/DP sink 5699 * @drm_edid: EDID to parse 5700 * 5701 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 5702 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 5703 */ 5704 static void drm_edid_to_eld(struct drm_connector *connector, 5705 const struct drm_edid *drm_edid) 5706 { 5707 const struct drm_display_info *info = &connector->display_info; 5708 const struct cea_db *db; 5709 struct cea_db_iter iter; 5710 uint8_t *eld = connector->eld; 5711 int total_sad_count = 0; 5712 int mnl; 5713 5714 if (!drm_edid) 5715 return; 5716 5717 mutex_lock(&connector->eld_mutex); 5718 5719 mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]); 5720 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD monitor %s\n", 5721 connector->base.id, connector->name, 5722 &eld[DRM_ELD_MONITOR_NAME_STRING]); 5723 5724 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT; 5725 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl; 5726 5727 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D; 5728 5729 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0]; 5730 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1]; 5731 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0]; 5732 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1]; 5733 5734 cea_db_iter_edid_begin(drm_edid, &iter); 5735 cea_db_iter_for_each(db, &iter) { 5736 const u8 *data = cea_db_data(db); 5737 int len = cea_db_payload_len(db); 5738 int sad_count; 5739 5740 switch (cea_db_tag(db)) { 5741 case CTA_DB_AUDIO: 5742 /* Audio Data Block, contains SADs */ 5743 sad_count = min(len / 3, 15 - total_sad_count); 5744 if (sad_count >= 1) 5745 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)], 5746 data, sad_count * 3); 5747 total_sad_count += sad_count; 5748 break; 5749 case CTA_DB_SPEAKER: 5750 /* Speaker Allocation Data Block */ 5751 if (len >= 1) 5752 eld[DRM_ELD_SPEAKER] = data[0]; 5753 break; 5754 case CTA_DB_VENDOR: 5755 /* HDMI Vendor-Specific Data Block */ 5756 if (cea_db_is_hdmi_vsdb(db)) 5757 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db); 5758 break; 5759 default: 5760 break; 5761 } 5762 } 5763 cea_db_iter_end(&iter); 5764 5765 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT; 5766 5767 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 5768 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 5769 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 5770 else 5771 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 5772 5773 eld[DRM_ELD_BASELINE_ELD_LEN] = 5774 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 5775 5776 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD size %d, SAD count %d\n", 5777 connector->base.id, connector->name, 5778 drm_eld_size(eld), total_sad_count); 5779 5780 mutex_unlock(&connector->eld_mutex); 5781 } 5782 5783 static int _drm_edid_to_sad(const struct drm_edid *drm_edid, 5784 struct cea_sad **psads) 5785 { 5786 const struct cea_db *db; 5787 struct cea_db_iter iter; 5788 int count = 0; 5789 5790 cea_db_iter_edid_begin(drm_edid, &iter); 5791 cea_db_iter_for_each(db, &iter) { 5792 if (cea_db_tag(db) == CTA_DB_AUDIO) { 5793 struct cea_sad *sads; 5794 int i; 5795 5796 count = cea_db_payload_len(db) / 3; /* SAD is 3B */ 5797 sads = kzalloc_objs(*sads, count); 5798 *psads = sads; 5799 if (!sads) 5800 return -ENOMEM; 5801 for (i = 0; i < count; i++) 5802 drm_edid_cta_sad_set(&sads[i], &db->data[i * 3]); 5803 break; 5804 } 5805 } 5806 cea_db_iter_end(&iter); 5807 5808 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count); 5809 5810 return count; 5811 } 5812 5813 /** 5814 * drm_edid_to_sad - extracts SADs from EDID 5815 * @edid: EDID to parse 5816 * @sads: pointer that will be set to the extracted SADs 5817 * 5818 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 5819 * 5820 * Note: The returned pointer needs to be freed using kfree(). 5821 * 5822 * Return: The number of found SADs or negative number on error. 5823 */ 5824 int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads) 5825 { 5826 struct drm_edid drm_edid; 5827 5828 return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads); 5829 } 5830 EXPORT_SYMBOL(drm_edid_to_sad); 5831 5832 static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid, 5833 u8 **sadb) 5834 { 5835 const struct cea_db *db; 5836 struct cea_db_iter iter; 5837 int count = 0; 5838 5839 cea_db_iter_edid_begin(drm_edid, &iter); 5840 cea_db_iter_for_each(db, &iter) { 5841 if (cea_db_tag(db) == CTA_DB_SPEAKER && 5842 cea_db_payload_len(db) == 3) { 5843 *sadb = kmemdup(db->data, cea_db_payload_len(db), 5844 GFP_KERNEL); 5845 if (!*sadb) 5846 return -ENOMEM; 5847 count = cea_db_payload_len(db); 5848 break; 5849 } 5850 } 5851 cea_db_iter_end(&iter); 5852 5853 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count); 5854 5855 return count; 5856 } 5857 5858 /** 5859 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 5860 * @edid: EDID to parse 5861 * @sadb: pointer to the speaker block 5862 * 5863 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 5864 * 5865 * Note: The returned pointer needs to be freed using kfree(). 5866 * 5867 * Return: The number of found Speaker Allocation Blocks or negative number on 5868 * error. 5869 */ 5870 int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb) 5871 { 5872 struct drm_edid drm_edid; 5873 5874 return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid), 5875 sadb); 5876 } 5877 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 5878 5879 /** 5880 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 5881 * @connector: connector associated with the HDMI/DP sink 5882 * @mode: the display mode 5883 * 5884 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 5885 * the sink doesn't support audio or video. 5886 */ 5887 int drm_av_sync_delay(struct drm_connector *connector, 5888 const struct drm_display_mode *mode) 5889 { 5890 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 5891 int a, v; 5892 5893 if (!connector->latency_present[0]) 5894 return 0; 5895 if (!connector->latency_present[1]) 5896 i = 0; 5897 5898 a = connector->audio_latency[i]; 5899 v = connector->video_latency[i]; 5900 5901 /* 5902 * HDMI/DP sink doesn't support audio or video? 5903 */ 5904 if (a == 255 || v == 255) 5905 return 0; 5906 5907 /* 5908 * Convert raw EDID values to millisecond. 5909 * Treat unknown latency as 0ms. 5910 */ 5911 if (a) 5912 a = min(2 * (a - 1), 500); 5913 if (v) 5914 v = min(2 * (v - 1), 500); 5915 5916 return max(v - a, 0); 5917 } 5918 EXPORT_SYMBOL(drm_av_sync_delay); 5919 5920 static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid) 5921 { 5922 const struct cea_db *db; 5923 struct cea_db_iter iter; 5924 bool hdmi = false; 5925 5926 /* 5927 * Because HDMI identifier is in Vendor Specific Block, 5928 * search it from all data blocks of CEA extension. 5929 */ 5930 cea_db_iter_edid_begin(drm_edid, &iter); 5931 cea_db_iter_for_each(db, &iter) { 5932 if (cea_db_is_hdmi_vsdb(db)) { 5933 hdmi = true; 5934 break; 5935 } 5936 } 5937 cea_db_iter_end(&iter); 5938 5939 return hdmi; 5940 } 5941 5942 /** 5943 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 5944 * @edid: monitor EDID information 5945 * 5946 * Parse the CEA extension according to CEA-861-B. 5947 * 5948 * Drivers that have added the modes parsed from EDID to drm_display_info 5949 * should use &drm_display_info.is_hdmi instead of calling this function. 5950 * 5951 * Return: True if the monitor is HDMI, false if not or unknown. 5952 */ 5953 bool drm_detect_hdmi_monitor(const struct edid *edid) 5954 { 5955 struct drm_edid drm_edid; 5956 5957 return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid)); 5958 } 5959 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 5960 5961 static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid) 5962 { 5963 struct drm_edid_iter edid_iter; 5964 const struct cea_db *db; 5965 struct cea_db_iter iter; 5966 const u8 *edid_ext; 5967 bool has_audio = false; 5968 5969 drm_edid_iter_begin(drm_edid, &edid_iter); 5970 drm_edid_iter_for_each(edid_ext, &edid_iter) { 5971 if (edid_ext[0] == CEA_EXT) { 5972 has_audio = edid_ext[3] & EDID_BASIC_AUDIO; 5973 if (has_audio) 5974 break; 5975 } 5976 } 5977 drm_edid_iter_end(&edid_iter); 5978 5979 if (has_audio) { 5980 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 5981 goto end; 5982 } 5983 5984 cea_db_iter_edid_begin(drm_edid, &iter); 5985 cea_db_iter_for_each(db, &iter) { 5986 if (cea_db_tag(db) == CTA_DB_AUDIO) { 5987 const u8 *data = cea_db_data(db); 5988 int i; 5989 5990 for (i = 0; i < cea_db_payload_len(db); i += 3) 5991 DRM_DEBUG_KMS("CEA audio format %d\n", 5992 (data[i] >> 3) & 0xf); 5993 has_audio = true; 5994 break; 5995 } 5996 } 5997 cea_db_iter_end(&iter); 5998 5999 end: 6000 return has_audio; 6001 } 6002 6003 /** 6004 * drm_detect_monitor_audio - check monitor audio capability 6005 * @edid: EDID block to scan 6006 * 6007 * Monitor should have CEA extension block. 6008 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 6009 * audio' only. If there is any audio extension block and supported 6010 * audio format, assume at least 'basic audio' support, even if 'basic 6011 * audio' is not defined in EDID. 6012 * 6013 * Return: True if the monitor supports audio, false otherwise. 6014 */ 6015 bool drm_detect_monitor_audio(const struct edid *edid) 6016 { 6017 struct drm_edid drm_edid; 6018 6019 return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid)); 6020 } 6021 EXPORT_SYMBOL(drm_detect_monitor_audio); 6022 6023 6024 /** 6025 * drm_default_rgb_quant_range - default RGB quantization range 6026 * @mode: display mode 6027 * 6028 * Determine the default RGB quantization range for the mode, 6029 * as specified in CEA-861. 6030 * 6031 * Return: The default RGB quantization range for the mode 6032 */ 6033 enum hdmi_quantization_range 6034 drm_default_rgb_quant_range(const struct drm_display_mode *mode) 6035 { 6036 /* All CEA modes other than VIC 1 use limited quantization range. */ 6037 return drm_match_cea_mode(mode) > 1 ? 6038 HDMI_QUANTIZATION_RANGE_LIMITED : 6039 HDMI_QUANTIZATION_RANGE_FULL; 6040 } 6041 EXPORT_SYMBOL(drm_default_rgb_quant_range); 6042 6043 /* CTA-861 Video Data Block (CTA VDB) */ 6044 static void parse_cta_vdb(struct drm_connector *connector, const struct cea_db *db) 6045 { 6046 struct drm_display_info *info = &connector->display_info; 6047 int i, vic_index, len = cea_db_payload_len(db); 6048 const u8 *svds = cea_db_data(db); 6049 u8 *vics; 6050 6051 if (!len) 6052 return; 6053 6054 /* Gracefully handle multiple VDBs, however unlikely that is */ 6055 vics = krealloc(info->vics, info->vics_len + len, GFP_KERNEL); 6056 if (!vics) 6057 return; 6058 6059 vic_index = info->vics_len; 6060 info->vics_len += len; 6061 info->vics = vics; 6062 6063 for (i = 0; i < len; i++) { 6064 u8 vic = svd_to_vic(svds[i]); 6065 6066 if (!drm_valid_cea_vic(vic)) 6067 vic = 0; 6068 6069 info->vics[vic_index++] = vic; 6070 } 6071 } 6072 6073 /* 6074 * Update y420_cmdb_modes based on previously parsed CTA VDB and Y420CMDB. 6075 * 6076 * Translate the y420cmdb_map based on VIC indexes to y420_cmdb_modes indexed 6077 * using the VICs themselves. 6078 */ 6079 static void update_cta_y420cmdb(struct drm_connector *connector, u64 y420cmdb_map) 6080 { 6081 struct drm_display_info *info = &connector->display_info; 6082 struct drm_hdmi_info *hdmi = &info->hdmi; 6083 int i, len = min_t(int, info->vics_len, BITS_PER_TYPE(y420cmdb_map)); 6084 6085 for (i = 0; i < len; i++) { 6086 u8 vic = info->vics[i]; 6087 6088 if (vic && y420cmdb_map & BIT_ULL(i)) 6089 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 6090 } 6091 } 6092 6093 static bool cta_vdb_has_vic(const struct drm_connector *connector, u8 vic) 6094 { 6095 const struct drm_display_info *info = &connector->display_info; 6096 int i; 6097 6098 if (!vic || !info->vics) 6099 return false; 6100 6101 for (i = 0; i < info->vics_len; i++) { 6102 if (info->vics[i] == vic) 6103 return true; 6104 } 6105 6106 return false; 6107 } 6108 6109 /* CTA-861-H YCbCr 4:2:0 Video Data Block (CTA Y420VDB) */ 6110 static void parse_cta_y420vdb(struct drm_connector *connector, 6111 const struct cea_db *db) 6112 { 6113 struct drm_display_info *info = &connector->display_info; 6114 struct drm_hdmi_info *hdmi = &info->hdmi; 6115 const u8 *svds = cea_db_data(db) + 1; 6116 int i; 6117 6118 for (i = 0; i < cea_db_payload_len(db) - 1; i++) { 6119 u8 vic = svd_to_vic(svds[i]); 6120 6121 if (!drm_valid_cea_vic(vic)) 6122 continue; 6123 6124 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 6125 info->color_formats |= BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR420); 6126 } 6127 } 6128 6129 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db) 6130 { 6131 struct drm_display_info *info = &connector->display_info; 6132 6133 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] CEA VCDB 0x%02x\n", 6134 connector->base.id, connector->name, db[2]); 6135 6136 if (db[2] & EDID_CEA_VCDB_QS) 6137 info->rgb_quant_range_selectable = true; 6138 } 6139 6140 static 6141 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane) 6142 { 6143 switch (max_frl_rate) { 6144 case 1: 6145 *max_lanes = 3; 6146 *max_rate_per_lane = 3; 6147 break; 6148 case 2: 6149 *max_lanes = 3; 6150 *max_rate_per_lane = 6; 6151 break; 6152 case 3: 6153 *max_lanes = 4; 6154 *max_rate_per_lane = 6; 6155 break; 6156 case 4: 6157 *max_lanes = 4; 6158 *max_rate_per_lane = 8; 6159 break; 6160 case 5: 6161 *max_lanes = 4; 6162 *max_rate_per_lane = 10; 6163 break; 6164 case 6: 6165 *max_lanes = 4; 6166 *max_rate_per_lane = 12; 6167 break; 6168 case 0: 6169 default: 6170 *max_lanes = 0; 6171 *max_rate_per_lane = 0; 6172 } 6173 } 6174 6175 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 6176 const u8 *db) 6177 { 6178 u8 dc_mask; 6179 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 6180 6181 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 6182 hdmi->y420_dc_modes = dc_mask; 6183 } 6184 6185 static void drm_parse_dsc_info(struct drm_hdmi_dsc_cap *hdmi_dsc, 6186 const u8 *hf_scds) 6187 { 6188 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2; 6189 6190 if (!hdmi_dsc->v_1p2) 6191 return; 6192 6193 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420; 6194 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP; 6195 6196 if (hf_scds[11] & DRM_EDID_DSC_16BPC) 6197 hdmi_dsc->bpc_supported = 16; 6198 else if (hf_scds[11] & DRM_EDID_DSC_12BPC) 6199 hdmi_dsc->bpc_supported = 12; 6200 else if (hf_scds[11] & DRM_EDID_DSC_10BPC) 6201 hdmi_dsc->bpc_supported = 10; 6202 else 6203 /* Supports min 8 BPC if DSC 1.2 is supported*/ 6204 hdmi_dsc->bpc_supported = 8; 6205 6206 if (cea_db_payload_len(hf_scds) >= 12 && hf_scds[12]) { 6207 u8 dsc_max_slices; 6208 u8 dsc_max_frl_rate; 6209 6210 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4; 6211 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes, 6212 &hdmi_dsc->max_frl_rate_per_lane); 6213 6214 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES; 6215 6216 switch (dsc_max_slices) { 6217 case 1: 6218 hdmi_dsc->max_slices = 1; 6219 hdmi_dsc->clk_per_slice = 340; 6220 break; 6221 case 2: 6222 hdmi_dsc->max_slices = 2; 6223 hdmi_dsc->clk_per_slice = 340; 6224 break; 6225 case 3: 6226 hdmi_dsc->max_slices = 4; 6227 hdmi_dsc->clk_per_slice = 340; 6228 break; 6229 case 4: 6230 hdmi_dsc->max_slices = 8; 6231 hdmi_dsc->clk_per_slice = 340; 6232 break; 6233 case 5: 6234 hdmi_dsc->max_slices = 8; 6235 hdmi_dsc->clk_per_slice = 400; 6236 break; 6237 case 6: 6238 hdmi_dsc->max_slices = 12; 6239 hdmi_dsc->clk_per_slice = 400; 6240 break; 6241 case 7: 6242 hdmi_dsc->max_slices = 16; 6243 hdmi_dsc->clk_per_slice = 400; 6244 break; 6245 case 0: 6246 default: 6247 hdmi_dsc->max_slices = 0; 6248 hdmi_dsc->clk_per_slice = 0; 6249 } 6250 } 6251 6252 if (cea_db_payload_len(hf_scds) >= 13 && hf_scds[13]) 6253 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES; 6254 } 6255 6256 /* Sink Capability Data Structure */ 6257 static void drm_parse_hdmi_forum_scds(struct drm_connector *connector, 6258 const u8 *hf_scds) 6259 { 6260 struct drm_display_info *info = &connector->display_info; 6261 struct drm_hdmi_info *hdmi = &info->hdmi; 6262 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap; 6263 int max_tmds_clock = 0; 6264 u8 max_frl_rate = 0; 6265 bool dsc_support = false; 6266 6267 info->has_hdmi_infoframe = true; 6268 6269 if (hf_scds[6] & 0x80) { 6270 hdmi->scdc.supported = true; 6271 if (hf_scds[6] & 0x40) 6272 hdmi->scdc.read_request = true; 6273 } 6274 6275 /* 6276 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 6277 * And as per the spec, three factors confirm this: 6278 * * Availability of a HF-VSDB block in EDID (check) 6279 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 6280 * * SCDC support available (let's check) 6281 * Lets check it out. 6282 */ 6283 6284 if (hf_scds[5]) { 6285 struct drm_scdc *scdc = &hdmi->scdc; 6286 6287 /* max clock is 5000 KHz times block value */ 6288 max_tmds_clock = hf_scds[5] * 5000; 6289 6290 if (max_tmds_clock > 340000) { 6291 info->max_tmds_clock = max_tmds_clock; 6292 } 6293 6294 if (scdc->supported) { 6295 scdc->scrambling.supported = true; 6296 6297 /* Few sinks support scrambling for clocks < 340M */ 6298 if ((hf_scds[6] & 0x8)) 6299 scdc->scrambling.low_rates = true; 6300 } 6301 } 6302 6303 if (hf_scds[7]) { 6304 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4; 6305 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes, 6306 &hdmi->max_frl_rate_per_lane); 6307 } 6308 6309 drm_parse_ycbcr420_deep_color_info(connector, hf_scds); 6310 6311 if (cea_db_payload_len(hf_scds) >= 11 && hf_scds[11]) { 6312 drm_parse_dsc_info(hdmi_dsc, hf_scds); 6313 dsc_support = true; 6314 } 6315 6316 drm_dbg_kms(connector->dev, 6317 "[CONNECTOR:%d:%s] HF-VSDB: max TMDS clock: %d KHz, HDMI 2.1 support: %s, DSC 1.2 support: %s\n", 6318 connector->base.id, connector->name, 6319 max_tmds_clock, str_yes_no(max_frl_rate), str_yes_no(dsc_support)); 6320 } 6321 6322 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 6323 const u8 *hdmi) 6324 { 6325 struct drm_display_info *info = &connector->display_info; 6326 unsigned int dc_bpc = 0; 6327 6328 /* HDMI supports at least 8 bpc */ 6329 info->bpc = 8; 6330 6331 if (cea_db_payload_len(hdmi) < 6) 6332 return; 6333 6334 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 6335 dc_bpc = 10; 6336 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30; 6337 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 30.\n", 6338 connector->base.id, connector->name); 6339 } 6340 6341 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 6342 dc_bpc = 12; 6343 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36; 6344 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 36.\n", 6345 connector->base.id, connector->name); 6346 } 6347 6348 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 6349 dc_bpc = 16; 6350 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48; 6351 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 48.\n", 6352 connector->base.id, connector->name); 6353 } 6354 6355 if (dc_bpc == 0) { 6356 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] No deep color support on this HDMI sink.\n", 6357 connector->base.id, connector->name); 6358 return; 6359 } 6360 6361 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Assigning HDMI sink color depth as %d bpc.\n", 6362 connector->base.id, connector->name, dc_bpc); 6363 info->bpc = dc_bpc; 6364 6365 /* YCRCB444 is optional according to spec. */ 6366 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 6367 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes; 6368 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does YCRCB444 in deep color.\n", 6369 connector->base.id, connector->name); 6370 } 6371 6372 /* 6373 * Spec says that if any deep color mode is supported at all, 6374 * then deep color 36 bit must be supported. 6375 */ 6376 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 6377 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink should do DC_36, but does not!\n", 6378 connector->base.id, connector->name); 6379 } 6380 } 6381 6382 /* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */ 6383 static void 6384 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 6385 { 6386 struct drm_display_info *info = &connector->display_info; 6387 u8 len = cea_db_payload_len(db); 6388 6389 info->is_hdmi = true; 6390 6391 info->source_physical_address = (db[4] << 8) | db[5]; 6392 6393 if (len >= 6) 6394 info->dvi_dual = db[6] & 1; 6395 if (len >= 7) 6396 info->max_tmds_clock = db[7] * 5000; 6397 6398 /* 6399 * Try to infer whether the sink supports HDMI infoframes. 6400 * 6401 * HDMI infoframe support was first added in HDMI 1.4. Assume the sink 6402 * supports infoframes if HDMI_Video_present is set. 6403 */ 6404 if (len >= 8 && db[8] & BIT(5)) 6405 info->has_hdmi_infoframe = true; 6406 6407 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI: DVI dual %d, max TMDS clock %d kHz\n", 6408 connector->base.id, connector->name, 6409 info->dvi_dual, info->max_tmds_clock); 6410 6411 drm_parse_hdmi_deep_color_info(connector, db); 6412 } 6413 6414 /* 6415 * See EDID extension for head-mounted and specialized monitors, specified at: 6416 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension 6417 */ 6418 static void drm_parse_microsoft_vsdb(struct drm_connector *connector, 6419 const u8 *db) 6420 { 6421 struct drm_display_info *info = &connector->display_info; 6422 u8 version = db[4]; 6423 bool desktop_usage = db[5] & BIT(6); 6424 6425 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */ 6426 if (version == 1 || version == 2 || (version == 3 && !desktop_usage)) 6427 info->non_desktop = true; 6428 6429 drm_dbg_kms(connector->dev, 6430 "[CONNECTOR:%d:%s] HMD or specialized display VSDB version %u: 0x%02x\n", 6431 connector->base.id, connector->name, version, db[5]); 6432 } 6433 6434 static void drm_parse_amd_vsdb(struct drm_connector *connector, 6435 const struct cea_db *db) 6436 { 6437 struct drm_display_info *info = &connector->display_info; 6438 const u8 *data = cea_db_data(db); 6439 const struct amd_vsdb_v3_payload *p; 6440 6441 p = (const struct amd_vsdb_v3_payload *)data; 6442 6443 if (p->version != 0x03) { 6444 drm_dbg_kms(connector->dev, 6445 "[CONNECTOR:%d:%s] Unsupported AMD VSDB version %u\n", 6446 connector->base.id, connector->name, p->version); 6447 return; 6448 } 6449 6450 info->amd_vsdb.version = p->version; 6451 info->amd_vsdb.replay_mode = p->feature_caps & 0x40; 6452 info->amd_vsdb.panel_type = (p->cs_eotf_support & 0xC0) >> 6; 6453 info->amd_vsdb.luminance_range1.max_luminance = p->lum1_max; 6454 info->amd_vsdb.luminance_range1.min_luminance = p->lum1_min; 6455 info->amd_vsdb.luminance_range2.max_luminance = p->lum2_max; 6456 info->amd_vsdb.luminance_range2.min_luminance = p->lum2_min; 6457 6458 /* 6459 * The AMD VSDB v3 payload length is variable (15..20 bytes). 6460 * All fields through p->rsvd1 (byte 14) are always present, 6461 * but p->extra[] (bytes 15+) may not be. Any future access to 6462 * extra[] must be guarded with a runtime length check to avoid 6463 * out-of-bounds reads on shorter (but spec-valid) payloads. 6464 * For example: 6465 * 6466 * int len = cea_db_payload_len(db); 6467 * 6468 * if (len > AMD_VSDB_V3_PAYLOAD_MIN_LEN) 6469 * info->amd_vsdb.foo = p->extra[0]; 6470 */ 6471 } 6472 6473 static void drm_parse_cea_ext(struct drm_connector *connector, 6474 const struct drm_edid *drm_edid) 6475 { 6476 struct drm_display_info *info = &connector->display_info; 6477 struct drm_edid_iter edid_iter; 6478 const struct cea_db *db; 6479 struct cea_db_iter iter; 6480 const u8 *edid_ext; 6481 u64 y420cmdb_map = 0; 6482 6483 drm_edid_iter_begin(drm_edid, &edid_iter); 6484 drm_edid_iter_for_each(edid_ext, &edid_iter) { 6485 if (edid_ext[0] != CEA_EXT) 6486 continue; 6487 6488 if (!info->cea_rev) 6489 info->cea_rev = edid_ext[1]; 6490 6491 if (info->cea_rev != edid_ext[1]) 6492 drm_dbg_kms(connector->dev, 6493 "[CONNECTOR:%d:%s] CEA extension version mismatch %u != %u\n", 6494 connector->base.id, connector->name, 6495 info->cea_rev, edid_ext[1]); 6496 6497 /* The existence of a CTA extension should imply RGB support */ 6498 info->color_formats = BIT(DRM_OUTPUT_COLOR_FORMAT_RGB444); 6499 if (edid_ext[3] & EDID_CEA_YCRCB444) 6500 info->color_formats |= BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR444); 6501 if (edid_ext[3] & EDID_CEA_YCRCB422) 6502 info->color_formats |= BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR422); 6503 if (edid_ext[3] & EDID_BASIC_AUDIO) 6504 info->has_audio = true; 6505 6506 } 6507 drm_edid_iter_end(&edid_iter); 6508 6509 cea_db_iter_edid_begin(drm_edid, &iter); 6510 cea_db_iter_for_each(db, &iter) { 6511 /* FIXME: convert parsers to use struct cea_db */ 6512 const u8 *data = (const u8 *)db; 6513 6514 if (cea_db_is_hdmi_vsdb(db)) 6515 drm_parse_hdmi_vsdb_video(connector, data); 6516 else if (cea_db_is_hdmi_forum_vsdb(db) || 6517 cea_db_is_hdmi_forum_scdb(db)) 6518 drm_parse_hdmi_forum_scds(connector, data); 6519 else if (cea_db_is_microsoft_vsdb(db)) 6520 drm_parse_microsoft_vsdb(connector, data); 6521 else if (cea_db_is_amd_vsdb(db)) 6522 drm_parse_amd_vsdb(connector, db); 6523 else if (cea_db_is_y420cmdb(db)) 6524 parse_cta_y420cmdb(connector, db, &y420cmdb_map); 6525 else if (cea_db_is_y420vdb(db)) 6526 parse_cta_y420vdb(connector, db); 6527 else if (cea_db_is_vcdb(db)) 6528 drm_parse_vcdb(connector, data); 6529 else if (cea_db_is_hdmi_hdr_metadata_block(db)) 6530 drm_parse_hdr_metadata_block(connector, data); 6531 else if (cea_db_tag(db) == CTA_DB_VIDEO) 6532 parse_cta_vdb(connector, db); 6533 else if (cea_db_tag(db) == CTA_DB_AUDIO) 6534 info->has_audio = true; 6535 } 6536 cea_db_iter_end(&iter); 6537 6538 if (y420cmdb_map) 6539 update_cta_y420cmdb(connector, y420cmdb_map); 6540 } 6541 6542 static 6543 void get_monitor_range(const struct detailed_timing *timing, void *c) 6544 { 6545 struct detailed_mode_closure *closure = c; 6546 struct drm_display_info *info = &closure->connector->display_info; 6547 struct drm_monitor_range_info *monitor_range = &info->monitor_range; 6548 const struct detailed_non_pixel *data = &timing->data.other_data; 6549 const struct detailed_data_monitor_range *range = &data->data.range; 6550 const struct edid *edid = closure->drm_edid->edid; 6551 6552 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE)) 6553 return; 6554 6555 /* 6556 * These limits are used to determine the VRR refresh 6557 * rate range. Only the "range limits only" variant 6558 * of the range descriptor seems to guarantee that 6559 * any and all timings are accepted by the sink, as 6560 * opposed to just timings conforming to the indicated 6561 * formula (GTF/GTF2/CVT). Thus other variants of the 6562 * range descriptor are not accepted here. 6563 */ 6564 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG) 6565 return; 6566 6567 monitor_range->min_vfreq = range->min_vfreq; 6568 monitor_range->max_vfreq = range->max_vfreq; 6569 6570 if (edid->revision >= 4) { 6571 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ) 6572 monitor_range->min_vfreq += 255; 6573 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ) 6574 monitor_range->max_vfreq += 255; 6575 } 6576 } 6577 6578 static void drm_get_monitor_range(struct drm_connector *connector, 6579 const struct drm_edid *drm_edid) 6580 { 6581 const struct drm_display_info *info = &connector->display_info; 6582 struct detailed_mode_closure closure = { 6583 .connector = connector, 6584 .drm_edid = drm_edid, 6585 }; 6586 6587 if (drm_edid->edid->revision < 4) 6588 return; 6589 6590 if (!(drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ)) 6591 return; 6592 6593 drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure); 6594 6595 drm_dbg_kms(connector->dev, 6596 "[CONNECTOR:%d:%s] Supported Monitor Refresh rate range is %d Hz - %d Hz\n", 6597 connector->base.id, connector->name, 6598 info->monitor_range.min_vfreq, info->monitor_range.max_vfreq); 6599 } 6600 6601 static void drm_parse_vesa_mso_data(struct drm_connector *connector, 6602 const struct displayid_block *block) 6603 { 6604 struct displayid_vesa_vendor_specific_block *vesa = 6605 (struct displayid_vesa_vendor_specific_block *)block; 6606 struct drm_display_info *info = &connector->display_info; 6607 6608 if (block->num_bytes < 3) { 6609 drm_dbg_kms(connector->dev, 6610 "[CONNECTOR:%d:%s] Unexpected vendor block size %u\n", 6611 connector->base.id, connector->name, block->num_bytes); 6612 return; 6613 } 6614 6615 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI) 6616 return; 6617 6618 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) { 6619 drm_dbg_kms(connector->dev, 6620 "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n", 6621 connector->base.id, connector->name); 6622 return; 6623 } 6624 6625 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) { 6626 default: 6627 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n", 6628 connector->base.id, connector->name); 6629 fallthrough; 6630 case 0: 6631 info->mso_stream_count = 0; 6632 break; 6633 case 1: 6634 info->mso_stream_count = 2; /* 2 or 4 links */ 6635 break; 6636 case 2: 6637 info->mso_stream_count = 4; /* 4 links */ 6638 break; 6639 } 6640 6641 if (!info->mso_stream_count) { 6642 info->mso_pixel_overlap = 0; 6643 return; 6644 } 6645 6646 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso); 6647 if (info->mso_pixel_overlap > 8) { 6648 drm_dbg_kms(connector->dev, 6649 "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n", 6650 connector->base.id, connector->name, 6651 info->mso_pixel_overlap); 6652 info->mso_pixel_overlap = 8; 6653 } 6654 6655 drm_dbg_kms(connector->dev, 6656 "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n", 6657 connector->base.id, connector->name, 6658 info->mso_stream_count, info->mso_pixel_overlap); 6659 } 6660 6661 static void drm_update_mso(struct drm_connector *connector, 6662 const struct drm_edid *drm_edid) 6663 { 6664 const struct displayid_block *block; 6665 struct displayid_iter iter; 6666 6667 displayid_iter_edid_begin(drm_edid, &iter); 6668 displayid_iter_for_each(block, &iter) { 6669 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC) 6670 drm_parse_vesa_mso_data(connector, block); 6671 } 6672 displayid_iter_end(&iter); 6673 } 6674 6675 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset 6676 * all of the values which would have been set from EDID 6677 */ 6678 static void drm_reset_display_info(struct drm_connector *connector) 6679 { 6680 struct drm_display_info *info = &connector->display_info; 6681 6682 info->width_mm = 0; 6683 info->height_mm = 0; 6684 6685 info->bpc = 0; 6686 info->color_formats = 0; 6687 info->cea_rev = 0; 6688 info->max_tmds_clock = 0; 6689 info->dvi_dual = false; 6690 info->is_hdmi = false; 6691 info->has_audio = false; 6692 info->has_hdmi_infoframe = false; 6693 info->rgb_quant_range_selectable = false; 6694 memset(&info->hdmi, 0, sizeof(info->hdmi)); 6695 memset(&info->hdr_sink_metadata, 0, sizeof(info->hdr_sink_metadata)); 6696 6697 info->edid_hdmi_rgb444_dc_modes = 0; 6698 info->edid_hdmi_ycbcr444_dc_modes = 0; 6699 6700 info->non_desktop = 0; 6701 memset(&info->monitor_range, 0, sizeof(info->monitor_range)); 6702 memset(&info->luminance_range, 0, sizeof(info->luminance_range)); 6703 6704 info->mso_stream_count = 0; 6705 info->mso_pixel_overlap = 0; 6706 info->max_dsc_bpp = 0; 6707 6708 kfree(info->vics); 6709 info->vics = NULL; 6710 info->vics_len = 0; 6711 6712 info->quirks = 0; 6713 6714 info->source_physical_address = CEC_PHYS_ADDR_INVALID; 6715 memset(&info->amd_vsdb, 0, sizeof(info->amd_vsdb)); 6716 } 6717 6718 static void update_displayid_info(struct drm_connector *connector, 6719 const struct drm_edid *drm_edid) 6720 { 6721 struct drm_display_info *info = &connector->display_info; 6722 const struct displayid_block *block; 6723 struct displayid_iter iter; 6724 6725 displayid_iter_edid_begin(drm_edid, &iter); 6726 displayid_iter_for_each(block, &iter) { 6727 drm_dbg_kms(connector->dev, 6728 "[CONNECTOR:%d:%s] DisplayID extension version 0x%02x, primary use 0x%02x\n", 6729 connector->base.id, connector->name, 6730 displayid_version(&iter), 6731 displayid_primary_use(&iter)); 6732 if (displayid_version(&iter) == DISPLAY_ID_STRUCTURE_VER_20 && 6733 (displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_VR || 6734 displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_AR)) 6735 info->non_desktop = true; 6736 6737 /* 6738 * We're only interested in the base section here, no need to 6739 * iterate further. 6740 */ 6741 break; 6742 } 6743 displayid_iter_end(&iter); 6744 } 6745 6746 static void update_display_info(struct drm_connector *connector, 6747 const struct drm_edid *drm_edid) 6748 { 6749 struct drm_display_info *info = &connector->display_info; 6750 const struct edid *edid; 6751 6752 drm_reset_display_info(connector); 6753 clear_eld(connector); 6754 6755 if (!drm_edid) 6756 return; 6757 6758 edid = drm_edid->edid; 6759 6760 info->quirks = edid_get_quirks(drm_edid); 6761 6762 info->width_mm = edid->width_cm * 10; 6763 info->height_mm = edid->height_cm * 10; 6764 6765 drm_get_monitor_range(connector, drm_edid); 6766 6767 if (edid->revision < 3) 6768 goto out; 6769 6770 if (!drm_edid_is_digital(drm_edid)) 6771 goto out; 6772 6773 info->color_formats |= BIT(DRM_OUTPUT_COLOR_FORMAT_RGB444); 6774 drm_parse_cea_ext(connector, drm_edid); 6775 6776 update_displayid_info(connector, drm_edid); 6777 6778 /* 6779 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 6780 * 6781 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 6782 * tells us to assume 8 bpc color depth if the EDID doesn't have 6783 * extensions which tell otherwise. 6784 */ 6785 if (info->bpc == 0 && edid->revision == 3 && 6786 edid->input & DRM_EDID_DIGITAL_DFP_1_X) { 6787 info->bpc = 8; 6788 drm_dbg_kms(connector->dev, 6789 "[CONNECTOR:%d:%s] Assigning DFP sink color depth as %d bpc.\n", 6790 connector->base.id, connector->name, info->bpc); 6791 } 6792 6793 /* Only defined for 1.4 with digital displays */ 6794 if (edid->revision < 4) 6795 goto out; 6796 6797 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 6798 case DRM_EDID_DIGITAL_DEPTH_6: 6799 info->bpc = 6; 6800 break; 6801 case DRM_EDID_DIGITAL_DEPTH_8: 6802 info->bpc = 8; 6803 break; 6804 case DRM_EDID_DIGITAL_DEPTH_10: 6805 info->bpc = 10; 6806 break; 6807 case DRM_EDID_DIGITAL_DEPTH_12: 6808 info->bpc = 12; 6809 break; 6810 case DRM_EDID_DIGITAL_DEPTH_14: 6811 info->bpc = 14; 6812 break; 6813 case DRM_EDID_DIGITAL_DEPTH_16: 6814 info->bpc = 16; 6815 break; 6816 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 6817 default: 6818 info->bpc = 0; 6819 break; 6820 } 6821 6822 drm_dbg_kms(connector->dev, 6823 "[CONNECTOR:%d:%s] Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 6824 connector->base.id, connector->name, info->bpc); 6825 6826 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 6827 info->color_formats |= BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR444); 6828 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 6829 info->color_formats |= BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR422); 6830 6831 drm_update_mso(connector, drm_edid); 6832 6833 out: 6834 if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_NON_DESKTOP)) { 6835 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Non-desktop display%s\n", 6836 connector->base.id, connector->name, 6837 info->non_desktop ? " (redundant quirk)" : ""); 6838 info->non_desktop = true; 6839 } 6840 6841 if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_CAP_DSC_15BPP)) 6842 info->max_dsc_bpp = 15; 6843 6844 if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_FORCE_6BPC)) 6845 info->bpc = 6; 6846 6847 if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_FORCE_8BPC)) 6848 info->bpc = 8; 6849 6850 if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_FORCE_10BPC)) 6851 info->bpc = 10; 6852 6853 if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_FORCE_12BPC)) 6854 info->bpc = 12; 6855 6856 /* Depends on info->cea_rev set by drm_parse_cea_ext() above */ 6857 drm_edid_to_eld(connector, drm_edid); 6858 } 6859 6860 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 6861 const struct displayid_detailed_timings_1 *timings, 6862 bool type_7) 6863 { 6864 struct drm_display_mode *mode; 6865 unsigned int pixel_clock = (timings->pixel_clock[0] | 6866 (timings->pixel_clock[1] << 8) | 6867 (timings->pixel_clock[2] << 16)) + 1; 6868 unsigned int hactive = le16_to_cpu(timings->hactive) + 1; 6869 unsigned int hblank = le16_to_cpu(timings->hblank) + 1; 6870 unsigned int hsync = (le16_to_cpu(timings->hsync) & 0x7fff) + 1; 6871 unsigned int hsync_width = le16_to_cpu(timings->hsw) + 1; 6872 unsigned int vactive = le16_to_cpu(timings->vactive) + 1; 6873 unsigned int vblank = le16_to_cpu(timings->vblank) + 1; 6874 unsigned int vsync = (le16_to_cpu(timings->vsync) & 0x7fff) + 1; 6875 unsigned int vsync_width = le16_to_cpu(timings->vsw) + 1; 6876 bool hsync_positive = le16_to_cpu(timings->hsync) & (1 << 15); 6877 bool vsync_positive = le16_to_cpu(timings->vsync) & (1 << 15); 6878 6879 mode = drm_mode_create(dev); 6880 if (!mode) 6881 return NULL; 6882 6883 /* resolution is kHz for type VII, and 10 kHz for type I */ 6884 mode->clock = type_7 ? pixel_clock : pixel_clock * 10; 6885 mode->hdisplay = hactive; 6886 mode->hsync_start = mode->hdisplay + hsync; 6887 mode->hsync_end = mode->hsync_start + hsync_width; 6888 mode->htotal = mode->hdisplay + hblank; 6889 6890 mode->vdisplay = vactive; 6891 mode->vsync_start = mode->vdisplay + vsync; 6892 mode->vsync_end = mode->vsync_start + vsync_width; 6893 mode->vtotal = mode->vdisplay + vblank; 6894 6895 mode->flags = 0; 6896 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 6897 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 6898 mode->type = DRM_MODE_TYPE_DRIVER; 6899 6900 if (timings->flags & 0x80) 6901 mode->type |= DRM_MODE_TYPE_PREFERRED; 6902 drm_mode_set_name(mode); 6903 6904 return mode; 6905 } 6906 6907 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 6908 const struct displayid_block *block) 6909 { 6910 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 6911 int i; 6912 int num_timings; 6913 struct drm_display_mode *newmode; 6914 int num_modes = 0; 6915 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING; 6916 /* blocks must be multiple of 20 bytes length */ 6917 if (block->num_bytes % 20) 6918 return 0; 6919 6920 num_timings = block->num_bytes / 20; 6921 for (i = 0; i < num_timings; i++) { 6922 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 6923 6924 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7); 6925 if (!newmode) 6926 continue; 6927 6928 drm_mode_probed_add(connector, newmode); 6929 num_modes++; 6930 } 6931 return num_modes; 6932 } 6933 6934 static struct drm_display_mode *drm_mode_displayid_formula(struct drm_device *dev, 6935 const struct displayid_formula_timings_9 *timings, 6936 bool type_10) 6937 { 6938 struct drm_display_mode *mode; 6939 u16 hactive = le16_to_cpu(timings->hactive) + 1; 6940 u16 vactive = le16_to_cpu(timings->vactive) + 1; 6941 u8 timing_formula = timings->flags & 0x7; 6942 6943 /* TODO: support RB-v2 & RB-v3 */ 6944 if (timing_formula > 1) 6945 return NULL; 6946 6947 /* TODO: support video-optimized refresh rate */ 6948 if (timings->flags & (1 << 4)) 6949 drm_dbg_kms(dev, "Fractional vrefresh is not implemented, proceeding with non-video-optimized refresh rate"); 6950 6951 mode = drm_cvt_mode(dev, hactive, vactive, timings->vrefresh + 1, timing_formula == 1, false, false); 6952 if (!mode) 6953 return NULL; 6954 6955 /* TODO: interpret S3D flags */ 6956 6957 mode->type = DRM_MODE_TYPE_DRIVER; 6958 drm_mode_set_name(mode); 6959 6960 return mode; 6961 } 6962 6963 static int add_displayid_formula_modes(struct drm_connector *connector, 6964 const struct displayid_block *block) 6965 { 6966 const struct displayid_formula_timing_block *formula_block = (struct displayid_formula_timing_block *)block; 6967 int num_timings; 6968 struct drm_display_mode *newmode; 6969 int num_modes = 0; 6970 bool type_10 = block->tag == DATA_BLOCK_2_TYPE_10_FORMULA_TIMING; 6971 int timing_size = 6 + ((formula_block->base.rev & 0x70) >> 4); 6972 6973 /* extended blocks are not supported yet */ 6974 if (timing_size != 6) 6975 return 0; 6976 6977 if (block->num_bytes % timing_size) 6978 return 0; 6979 6980 num_timings = block->num_bytes / timing_size; 6981 for (int i = 0; i < num_timings; i++) { 6982 const struct displayid_formula_timings_9 *timings = &formula_block->timings[i]; 6983 6984 newmode = drm_mode_displayid_formula(connector->dev, timings, type_10); 6985 if (!newmode) 6986 continue; 6987 6988 drm_mode_probed_add(connector, newmode); 6989 num_modes++; 6990 } 6991 return num_modes; 6992 } 6993 6994 static int add_displayid_detailed_modes(struct drm_connector *connector, 6995 const struct drm_edid *drm_edid) 6996 { 6997 const struct displayid_block *block; 6998 struct displayid_iter iter; 6999 int num_modes = 0; 7000 7001 displayid_iter_edid_begin(drm_edid, &iter); 7002 displayid_iter_for_each(block, &iter) { 7003 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING || 7004 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING) 7005 num_modes += add_displayid_detailed_1_modes(connector, block); 7006 else if (block->tag == DATA_BLOCK_2_TYPE_9_FORMULA_TIMING || 7007 block->tag == DATA_BLOCK_2_TYPE_10_FORMULA_TIMING) 7008 num_modes += add_displayid_formula_modes(connector, block); 7009 } 7010 displayid_iter_end(&iter); 7011 7012 return num_modes; 7013 } 7014 7015 static int _drm_edid_connector_add_modes(struct drm_connector *connector, 7016 const struct drm_edid *drm_edid) 7017 { 7018 int num_modes = 0; 7019 7020 if (!drm_edid) 7021 return 0; 7022 7023 /* 7024 * EDID spec says modes should be preferred in this order: 7025 * - preferred detailed mode 7026 * - other detailed modes from base block 7027 * - detailed modes from extension blocks 7028 * - CVT 3-byte code modes 7029 * - standard timing codes 7030 * - established timing codes 7031 * - modes inferred from GTF or CVT range information 7032 * 7033 * We get this pretty much right. 7034 * 7035 * XXX order for additional mode types in extension blocks? 7036 */ 7037 num_modes += add_detailed_modes(connector, drm_edid); 7038 num_modes += add_cvt_modes(connector, drm_edid); 7039 num_modes += add_standard_modes(connector, drm_edid); 7040 num_modes += add_established_modes(connector, drm_edid); 7041 num_modes += add_cea_modes(connector, drm_edid); 7042 num_modes += add_alternate_cea_modes(connector, drm_edid); 7043 num_modes += add_displayid_detailed_modes(connector, drm_edid); 7044 if (drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ) 7045 num_modes += add_inferred_modes(connector, drm_edid); 7046 7047 if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_PREFER_LARGE_60) || 7048 drm_edid_has_internal_quirk(connector, EDID_QUIRK_PREFER_LARGE_75)) 7049 edid_fixup_preferred(connector); 7050 7051 return num_modes; 7052 } 7053 7054 static void _drm_update_tile_info(struct drm_connector *connector, 7055 const struct drm_edid *drm_edid); 7056 7057 static int _drm_edid_connector_property_update(struct drm_connector *connector, 7058 const struct drm_edid *drm_edid) 7059 { 7060 struct drm_device *dev = connector->dev; 7061 int ret; 7062 7063 if (connector->edid_blob_ptr) { 7064 const void *old_edid = connector->edid_blob_ptr->data; 7065 size_t old_edid_size = connector->edid_blob_ptr->length; 7066 7067 if (old_edid && !drm_edid_eq(drm_edid, old_edid, old_edid_size)) { 7068 connector->epoch_counter++; 7069 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n", 7070 connector->base.id, connector->name, 7071 connector->epoch_counter); 7072 } 7073 } 7074 7075 ret = drm_property_replace_global_blob(dev, 7076 &connector->edid_blob_ptr, 7077 drm_edid ? drm_edid->size : 0, 7078 drm_edid ? drm_edid->edid : NULL, 7079 &connector->base, 7080 dev->mode_config.edid_property); 7081 if (ret) { 7082 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n", 7083 connector->base.id, connector->name, ret); 7084 goto out; 7085 } 7086 7087 ret = drm_object_property_set_value(&connector->base, 7088 dev->mode_config.non_desktop_property, 7089 connector->display_info.non_desktop); 7090 if (ret) { 7091 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n", 7092 connector->base.id, connector->name, ret); 7093 goto out; 7094 } 7095 7096 ret = drm_connector_set_tile_property(connector); 7097 if (ret) { 7098 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n", 7099 connector->base.id, connector->name, ret); 7100 goto out; 7101 } 7102 7103 out: 7104 return ret; 7105 } 7106 7107 /* For sysfs edid show implementation */ 7108 ssize_t drm_edid_connector_property_show(struct drm_connector *connector, 7109 char *buf, loff_t off, size_t count) 7110 { 7111 const void *edid; 7112 size_t size; 7113 ssize_t ret = 0; 7114 7115 mutex_lock(&connector->dev->mode_config.mutex); 7116 7117 if (!connector->edid_blob_ptr) 7118 goto unlock; 7119 7120 edid = connector->edid_blob_ptr->data; 7121 size = connector->edid_blob_ptr->length; 7122 if (!edid) 7123 goto unlock; 7124 7125 if (off >= size) 7126 goto unlock; 7127 7128 if (off + count > size) 7129 count = size - off; 7130 7131 memcpy(buf, edid + off, count); 7132 7133 ret = count; 7134 unlock: 7135 mutex_unlock(&connector->dev->mode_config.mutex); 7136 7137 return ret; 7138 } 7139 7140 /** 7141 * drm_edid_connector_update - Update connector information from EDID 7142 * @connector: Connector 7143 * @drm_edid: EDID 7144 * 7145 * Update the connector display info, ELD, HDR metadata, relevant properties, 7146 * etc. from the passed in EDID. 7147 * 7148 * If EDID is NULL, reset the information. 7149 * 7150 * Must be called before calling drm_edid_connector_add_modes(). 7151 * 7152 * Return: 0 on success, negative error on errors. 7153 */ 7154 int drm_edid_connector_update(struct drm_connector *connector, 7155 const struct drm_edid *drm_edid) 7156 { 7157 update_display_info(connector, drm_edid); 7158 7159 _drm_update_tile_info(connector, drm_edid); 7160 7161 return _drm_edid_connector_property_update(connector, drm_edid); 7162 } 7163 EXPORT_SYMBOL(drm_edid_connector_update); 7164 7165 /** 7166 * drm_edid_connector_add_modes - Update probed modes from the EDID property 7167 * @connector: Connector 7168 * 7169 * Add the modes from the previously updated EDID property to the connector 7170 * probed modes list. 7171 * 7172 * drm_edid_connector_update() must have been called before this to update the 7173 * EDID property. 7174 * 7175 * Return: The number of modes added, or 0 if we couldn't find any. 7176 */ 7177 int drm_edid_connector_add_modes(struct drm_connector *connector) 7178 { 7179 const struct drm_edid *drm_edid = NULL; 7180 int count; 7181 7182 if (connector->edid_blob_ptr) 7183 drm_edid = drm_edid_alloc(connector->edid_blob_ptr->data, 7184 connector->edid_blob_ptr->length); 7185 7186 count = _drm_edid_connector_add_modes(connector, drm_edid); 7187 7188 drm_edid_free(drm_edid); 7189 7190 return count; 7191 } 7192 EXPORT_SYMBOL(drm_edid_connector_add_modes); 7193 7194 /** 7195 * drm_connector_update_edid_property - update the edid property of a connector 7196 * @connector: drm connector 7197 * @edid: new value of the edid property 7198 * 7199 * This function creates a new blob modeset object and assigns its id to the 7200 * connector's edid property. 7201 * Since we also parse tile information from EDID's displayID block, we also 7202 * set the connector's tile property here. See drm_connector_set_tile_property() 7203 * for more details. 7204 * 7205 * This function is deprecated. Use drm_edid_connector_update() instead. 7206 * 7207 * Returns: 7208 * Zero on success, negative errno on failure. 7209 */ 7210 int drm_connector_update_edid_property(struct drm_connector *connector, 7211 const struct edid *edid) 7212 { 7213 struct drm_edid drm_edid; 7214 7215 return drm_edid_connector_update(connector, drm_edid_legacy_init(&drm_edid, edid)); 7216 } 7217 EXPORT_SYMBOL(drm_connector_update_edid_property); 7218 7219 /** 7220 * drm_add_edid_modes - add modes from EDID data, if available 7221 * @connector: connector we're probing 7222 * @edid: EDID data 7223 * 7224 * Add the specified modes to the connector's mode list. Also fills out the 7225 * &drm_display_info structure and ELD in @connector with any information which 7226 * can be derived from the edid. 7227 * 7228 * This function is deprecated. Use drm_edid_connector_add_modes() instead. 7229 * 7230 * Return: The number of modes added or 0 if we couldn't find any. 7231 */ 7232 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 7233 { 7234 struct drm_edid _drm_edid; 7235 const struct drm_edid *drm_edid; 7236 7237 if (edid && !drm_edid_is_valid(edid)) { 7238 drm_warn(connector->dev, "[CONNECTOR:%d:%s] EDID invalid.\n", 7239 connector->base.id, connector->name); 7240 edid = NULL; 7241 } 7242 7243 drm_edid = drm_edid_legacy_init(&_drm_edid, edid); 7244 7245 update_display_info(connector, drm_edid); 7246 7247 return _drm_edid_connector_add_modes(connector, drm_edid); 7248 } 7249 EXPORT_SYMBOL(drm_add_edid_modes); 7250 7251 /** 7252 * drm_add_modes_noedid - add modes for the connectors without EDID 7253 * @connector: connector we're probing 7254 * @hdisplay: the horizontal display limit 7255 * @vdisplay: the vertical display limit 7256 * 7257 * Add the specified modes to the connector's mode list. Only when the 7258 * hdisplay/vdisplay is not beyond the given limit, it will be added. 7259 * 7260 * Return: The number of modes added or 0 if we couldn't find any. 7261 */ 7262 int drm_add_modes_noedid(struct drm_connector *connector, 7263 unsigned int hdisplay, unsigned int vdisplay) 7264 { 7265 int i, count = ARRAY_SIZE(drm_dmt_modes), num_modes = 0; 7266 struct drm_display_mode *mode; 7267 struct drm_device *dev = connector->dev; 7268 7269 for (i = 0; i < count; i++) { 7270 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 7271 7272 if (hdisplay && vdisplay) { 7273 /* 7274 * Only when two are valid, they will be used to check 7275 * whether the mode should be added to the mode list of 7276 * the connector. 7277 */ 7278 if (ptr->hdisplay > hdisplay || 7279 ptr->vdisplay > vdisplay) 7280 continue; 7281 } 7282 if (drm_mode_vrefresh(ptr) > 61) 7283 continue; 7284 mode = drm_mode_duplicate(dev, ptr); 7285 if (mode) { 7286 drm_mode_probed_add(connector, mode); 7287 num_modes++; 7288 } 7289 } 7290 return num_modes; 7291 } 7292 EXPORT_SYMBOL(drm_add_modes_noedid); 7293 7294 static bool is_hdmi2_sink(const struct drm_connector *connector) 7295 { 7296 /* 7297 * FIXME: sil-sii8620 doesn't have a connector around when 7298 * we need one, so we have to be prepared for a NULL connector. 7299 */ 7300 if (!connector) 7301 return true; 7302 7303 return connector->display_info.hdmi.scdc.supported || 7304 connector->display_info.color_formats & BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR420); 7305 } 7306 7307 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector, 7308 const struct drm_display_mode *mode) 7309 { 7310 bool has_hdmi_infoframe = connector ? 7311 connector->display_info.has_hdmi_infoframe : false; 7312 7313 if (!has_hdmi_infoframe) 7314 return 0; 7315 7316 /* No HDMI VIC when signalling 3D video format */ 7317 if (mode->flags & DRM_MODE_FLAG_3D_MASK) 7318 return 0; 7319 7320 return drm_match_hdmi_mode(mode); 7321 } 7322 7323 static u8 drm_mode_cea_vic(const struct drm_connector *connector, 7324 const struct drm_display_mode *mode) 7325 { 7326 /* 7327 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 7328 * we should send its VIC in vendor infoframes, else send the 7329 * VIC in AVI infoframes. Lets check if this mode is present in 7330 * HDMI 1.4b 4K modes 7331 */ 7332 if (drm_mode_hdmi_vic(connector, mode)) 7333 return 0; 7334 7335 return drm_match_cea_mode(mode); 7336 } 7337 7338 /* 7339 * Avoid sending VICs defined in HDMI 2.0 in AVI infoframes to sinks that 7340 * conform to HDMI 1.4. 7341 * 7342 * HDMI 1.4 (CTA-861-D) VIC range: [1..64] 7343 * HDMI 2.0 (CTA-861-F) VIC range: [1..107] 7344 * 7345 * If the sink lists the VIC in CTA VDB, assume it's fine, regardless of HDMI 7346 * version. 7347 */ 7348 static u8 vic_for_avi_infoframe(const struct drm_connector *connector, u8 vic) 7349 { 7350 if (!is_hdmi2_sink(connector) && vic > 64 && 7351 !cta_vdb_has_vic(connector, vic)) 7352 return 0; 7353 7354 return vic; 7355 } 7356 7357 /** 7358 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 7359 * data from a DRM display mode 7360 * @frame: HDMI AVI infoframe 7361 * @connector: the connector 7362 * @mode: DRM display mode 7363 * 7364 * Return: 0 on success or a negative error code on failure. 7365 */ 7366 int 7367 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 7368 const struct drm_connector *connector, 7369 const struct drm_display_mode *mode) 7370 { 7371 enum hdmi_picture_aspect picture_aspect; 7372 u8 vic, hdmi_vic; 7373 7374 if (!frame || !mode) 7375 return -EINVAL; 7376 7377 hdmi_avi_infoframe_init(frame); 7378 7379 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 7380 frame->pixel_repeat = 1; 7381 7382 vic = drm_mode_cea_vic(connector, mode); 7383 hdmi_vic = drm_mode_hdmi_vic(connector, mode); 7384 7385 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 7386 7387 /* 7388 * As some drivers don't support atomic, we can't use connector state. 7389 * So just initialize the frame with default values, just the same way 7390 * as it's done with other properties here. 7391 */ 7392 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; 7393 frame->itc = 0; 7394 7395 /* 7396 * Populate picture aspect ratio from either 7397 * user input (if specified) or from the CEA/HDMI mode lists. 7398 */ 7399 picture_aspect = mode->picture_aspect_ratio; 7400 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) { 7401 if (vic) 7402 picture_aspect = drm_get_cea_aspect_ratio(vic); 7403 else if (hdmi_vic) 7404 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic); 7405 } 7406 7407 /* 7408 * The infoframe can't convey anything but none, 4:3 7409 * and 16:9, so if the user has asked for anything else 7410 * we can only satisfy it by specifying the right VIC. 7411 */ 7412 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { 7413 if (vic) { 7414 if (picture_aspect != drm_get_cea_aspect_ratio(vic)) 7415 return -EINVAL; 7416 } else if (hdmi_vic) { 7417 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic)) 7418 return -EINVAL; 7419 } else { 7420 return -EINVAL; 7421 } 7422 7423 picture_aspect = HDMI_PICTURE_ASPECT_NONE; 7424 } 7425 7426 frame->video_code = vic_for_avi_infoframe(connector, vic); 7427 frame->picture_aspect = picture_aspect; 7428 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 7429 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 7430 7431 return 0; 7432 } 7433 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 7434 7435 /** 7436 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 7437 * quantization range information 7438 * @frame: HDMI AVI infoframe 7439 * @connector: the connector 7440 * @mode: DRM display mode 7441 * @rgb_quant_range: RGB quantization range (Q) 7442 */ 7443 void 7444 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 7445 const struct drm_connector *connector, 7446 const struct drm_display_mode *mode, 7447 enum hdmi_quantization_range rgb_quant_range) 7448 { 7449 const struct drm_display_info *info = &connector->display_info; 7450 7451 /* 7452 * CEA-861: 7453 * "A Source shall not send a non-zero Q value that does not correspond 7454 * to the default RGB Quantization Range for the transmitted Picture 7455 * unless the Sink indicates support for the Q bit in a Video 7456 * Capabilities Data Block." 7457 * 7458 * HDMI 2.0 recommends sending non-zero Q when it does match the 7459 * default RGB quantization range for the mode, even when QS=0. 7460 */ 7461 if (info->rgb_quant_range_selectable || 7462 rgb_quant_range == drm_default_rgb_quant_range(mode)) 7463 frame->quantization_range = rgb_quant_range; 7464 else 7465 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 7466 7467 /* 7468 * CEA-861-F: 7469 * "When transmitting any RGB colorimetry, the Source should set the 7470 * YQ-field to match the RGB Quantization Range being transmitted 7471 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 7472 * set YQ=1) and the Sink shall ignore the YQ-field." 7473 * 7474 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused 7475 * by non-zero YQ when receiving RGB. There doesn't seem to be any 7476 * good way to tell which version of CEA-861 the sink supports, so 7477 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based 7478 * on CEA-861-F. 7479 */ 7480 if (!is_hdmi2_sink(connector) || 7481 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 7482 frame->ycc_quantization_range = 7483 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 7484 else 7485 frame->ycc_quantization_range = 7486 HDMI_YCC_QUANTIZATION_RANGE_FULL; 7487 } 7488 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 7489 7490 static enum hdmi_3d_structure 7491 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 7492 { 7493 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 7494 7495 switch (layout) { 7496 case DRM_MODE_FLAG_3D_FRAME_PACKING: 7497 return HDMI_3D_STRUCTURE_FRAME_PACKING; 7498 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 7499 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 7500 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 7501 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 7502 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 7503 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 7504 case DRM_MODE_FLAG_3D_L_DEPTH: 7505 return HDMI_3D_STRUCTURE_L_DEPTH; 7506 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 7507 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 7508 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 7509 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 7510 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 7511 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 7512 default: 7513 return HDMI_3D_STRUCTURE_INVALID; 7514 } 7515 } 7516 7517 /** 7518 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 7519 * data from a DRM display mode 7520 * @frame: HDMI vendor infoframe 7521 * @connector: the connector 7522 * @mode: DRM display mode 7523 * 7524 * Note that there's is a need to send HDMI vendor infoframes only when using a 7525 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 7526 * function will return -EINVAL, error that can be safely ignored. 7527 * 7528 * Return: 0 on success or a negative error code on failure. 7529 */ 7530 int 7531 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 7532 const struct drm_connector *connector, 7533 const struct drm_display_mode *mode) 7534 { 7535 /* 7536 * FIXME: sil-sii8620 doesn't have a connector around when 7537 * we need one, so we have to be prepared for a NULL connector. 7538 */ 7539 bool has_hdmi_infoframe = connector ? 7540 connector->display_info.has_hdmi_infoframe : false; 7541 int err; 7542 7543 if (!frame || !mode) 7544 return -EINVAL; 7545 7546 if (!has_hdmi_infoframe) 7547 return -EINVAL; 7548 7549 err = hdmi_vendor_infoframe_init(frame); 7550 if (err < 0) 7551 return err; 7552 7553 /* 7554 * Even if it's not absolutely necessary to send the infoframe 7555 * (ie.vic==0 and s3d_struct==0) we will still send it if we 7556 * know that the sink can handle it. This is based on a 7557 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks 7558 * have trouble realizing that they should switch from 3D to 2D 7559 * mode if the source simply stops sending the infoframe when 7560 * it wants to switch from 3D to 2D. 7561 */ 7562 frame->vic = drm_mode_hdmi_vic(connector, mode); 7563 frame->s3d_struct = s3d_structure_from_display_mode(mode); 7564 7565 return 0; 7566 } 7567 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 7568 7569 static void drm_parse_tiled_block(struct drm_connector *connector, 7570 const struct displayid_block *block) 7571 { 7572 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 7573 u16 w, h; 7574 u8 tile_v_loc, tile_h_loc; 7575 u8 num_v_tile, num_h_tile; 7576 struct drm_tile_group *tg; 7577 7578 w = tile->tile_size[0] | tile->tile_size[1] << 8; 7579 h = tile->tile_size[2] | tile->tile_size[3] << 8; 7580 7581 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 7582 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 7583 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 7584 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 7585 7586 connector->has_tile = true; 7587 if (tile->tile_cap & 0x80) 7588 connector->tile_is_single_monitor = true; 7589 7590 connector->num_h_tile = num_h_tile + 1; 7591 connector->num_v_tile = num_v_tile + 1; 7592 connector->tile_h_loc = tile_h_loc; 7593 connector->tile_v_loc = tile_v_loc; 7594 connector->tile_h_size = w + 1; 7595 connector->tile_v_size = h + 1; 7596 7597 drm_dbg_kms(connector->dev, 7598 "[CONNECTOR:%d:%s] tile cap 0x%x, size %dx%d, num tiles %dx%d, location %dx%d, vend %c%c%c", 7599 connector->base.id, connector->name, 7600 tile->tile_cap, 7601 connector->tile_h_size, connector->tile_v_size, 7602 connector->num_h_tile, connector->num_v_tile, 7603 connector->tile_h_loc, connector->tile_v_loc, 7604 tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 7605 7606 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 7607 if (!tg) 7608 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 7609 if (!tg) 7610 return; 7611 7612 if (connector->tile_group != tg) { 7613 /* if we haven't got a pointer, 7614 take the reference, drop ref to old tile group */ 7615 if (connector->tile_group) 7616 drm_mode_put_tile_group(connector->dev, connector->tile_group); 7617 connector->tile_group = tg; 7618 } else { 7619 /* if same tile group, then release the ref we just took. */ 7620 drm_mode_put_tile_group(connector->dev, tg); 7621 } 7622 } 7623 7624 static bool displayid_is_tiled_block(const struct displayid_iter *iter, 7625 const struct displayid_block *block) 7626 { 7627 return (displayid_version(iter) < DISPLAY_ID_STRUCTURE_VER_20 && 7628 block->tag == DATA_BLOCK_TILED_DISPLAY) || 7629 (displayid_version(iter) == DISPLAY_ID_STRUCTURE_VER_20 && 7630 block->tag == DATA_BLOCK_2_TILED_DISPLAY_TOPOLOGY); 7631 } 7632 7633 static void _drm_update_tile_info(struct drm_connector *connector, 7634 const struct drm_edid *drm_edid) 7635 { 7636 const struct displayid_block *block; 7637 struct displayid_iter iter; 7638 7639 connector->has_tile = false; 7640 7641 displayid_iter_edid_begin(drm_edid, &iter); 7642 displayid_iter_for_each(block, &iter) { 7643 if (displayid_is_tiled_block(&iter, block)) 7644 drm_parse_tiled_block(connector, block); 7645 } 7646 displayid_iter_end(&iter); 7647 7648 if (!connector->has_tile && connector->tile_group) { 7649 drm_mode_put_tile_group(connector->dev, connector->tile_group); 7650 connector->tile_group = NULL; 7651 } 7652 } 7653 7654 /** 7655 * drm_edid_is_digital - is digital? 7656 * @drm_edid: The EDID 7657 * 7658 * Return true if input is digital. 7659 */ 7660 bool drm_edid_is_digital(const struct drm_edid *drm_edid) 7661 { 7662 return drm_edid && drm_edid->edid && 7663 drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL; 7664 } 7665 EXPORT_SYMBOL(drm_edid_is_digital); 7666